// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
ENSC
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED |
| 9:0 | ENSC | RW | Set the GPIO73-64 output enables |
| Instance 0 Address: | 0x400100C8 |
GPIO Enable A Clear (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENCA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENCA | RW | Clear the GPIO31-0 output enables |
| Instance 0 Address: | 0x400100CC |
GPIO Enable B Clear (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENCB
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENCB | RW | Clear the GPIO49-32 output enables |
| Instance 0 Address: | 0x400100D0 |
GPIO Enable C Clear (73-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
ENCC
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED |
| 9:0 | ENCC | RW | Clear the GPIO73-64 output enables |
| Instance 0 Address: | 0x400100D4 |
STIMER Capture trigger select and enable.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| STPOL3
0x0 |
STSEL3
0x3f |
STPOL2
0x0 |
STSEL2
0x3f |
STPOL1
0x0 |
STSEL1
0x3f |
STPOL0
0x0 |
STSEL0
0x3f |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | STPOL3 | RW | STIMER Capture 3 Polarity. CAPLH = 0x0 - Capture on low to high GPIO transition CAPHL = 0x1 - Capture on high to low GPIO transition |
| 30:24 | STSEL3 | RW | STIMER Capture 3 Select. |
| 23 | STPOL2 | RW | STIMER Capture 2 Polarity. CAPLH = 0x0 - Capture on low to high GPIO transition CAPHL = 0x1 - Capture on high to low GPIO transition |
| 22:16 | STSEL2 | RW | STIMER Capture 2 Select. |
| 15 | STPOL1 | RW | STIMER Capture 1 Polarity. CAPLH = 0x0 - Capture on low to high GPIO transition CAPHL = 0x1 - Capture on high to low GPIO transition |
| 14:8 | STSEL1 | RW | STIMER Capture 1 Select. |
| 7 | STPOL0 | RW | STIMER Capture 0 Polarity. CAPLH = 0x0 - Capture on low to high GPIO transition CAPHL = 0x1 - Capture on high to low GPIO transition |
| 6:0 | STSEL0 | RW | STIMER Capture 0 Select. |
| Instance 0 Address: | 0x400100D8 |
IOMSTR0 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM0IRQ
0x7f |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM0IRQ | RW | IOMSTR0 IRQ pad select. |
| Instance 0 Address: | 0x400100DC |
IOMSTR1 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM1IRQ
0x7f |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM1IRQ | RW | IOMSTR1 IRQ pad select. |
| Instance 0 Address: | 0x400100E0 |
IOMSTR2 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM2IRQ
0x7f |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM2IRQ | RW | IOMSTR2 IRQ pad select. |
| Instance 0 Address: | 0x400100E4 |
IOMSTR3 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM3IRQ
0x7f |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM3IRQ | RW | IOMSTR3 IRQ pad select. |
| Instance 0 Address: | 0x400100E8 |
IOMSTR4 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM4IRQ
0x3f |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM4IRQ | RW | IOMSTR4 IRQ pad select. |
| Instance 0 Address: | 0x400100EC |
IOMSTR5 IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IOM5IRQ
0x7f |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | IOM5IRQ | RW | IOMSTR5 IRQ pad select. |
| Instance 0 Address: | 0x400100F0 |
BLE IF IRQ select for flow control.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
BLEIFIRQ
0x7f |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | BLEIFIRQ | RW | BLEIF IRQ pad select. |
| Instance 0 Address: | 0x400100F4 |
GPIO Observation mode sample register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
OBS_DATA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | RSVD | RO | RESERVED |
| 15:0 | OBS_DATA | RW | Sample of the data output on the GPIO observation port. May have sampling non-synchronization issues, as the data is not synchronized to the read operation. Intended for debug purposes only |
| Instance 0 Address: | 0x400100F8 |
This register has additional configuration control for pads [3:0]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD3_SR
0x0 |
RSVD
0x0 |
PAD3_DS1
0x0 |
RSVD
0x0 |
PAD2_SR
0x0 |
RSVD
0x0 |
PAD2_DS1
0x0 |
RSVD
0x0 |
PAD1_SR
0x0 |
RSVD
0x0 |
PAD1_DS1
0x0 |
RSVD
0x0 |
PAD0_SR
0x0 |
RSVD
0x0 |
PAD0_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD3_SR | RW | Pad 3 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD3_DS1 | RW | Pad 3 high order drive strength selection. Used in conjunction with PAD3STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD2_SR | RW | Pad 3 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD2_DS1 | RW | Pad 2 high order drive strength selection. Used in conjunction with PAD2STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD1_SR | RW | Pad 3 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD1_DS1 | RW | Pad 1 high order drive strength selection. Used in conjunction with PAD1STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD0_SR | RW | Pad 3 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD0_DS1 | RW | Pad 0 high order drive strength selection. Used in conjunction with PAD0STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x400100FC |
This register has additional configuration control for pads [7:4]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD7_SR
0x0 |
RSVD
0x0 |
PAD7_DS1
0x0 |
RSVD
0x0 |
PAD6_SR
0x0 |
RSVD
0x0 |
PAD6_DS1
0x0 |
RSVD
0x0 |
PAD5_SR
0x0 |
RSVD
0x0 |
PAD5_DS1
0x0 |
RSVD
0x0 |
PAD4_SR
0x0 |
RSVD
0x0 |
PAD4_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD7_SR | RW | Pad 7 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD7_DS1 | RW | Pad 7 high order drive strength selection. Used in conjunction with PAD7STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD6_SR | RW | Pad 7 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD6_DS1 | RW | Pad 6 high order drive strength selection. Used in conjunction with PAD6STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD5_SR | RW | Pad 7 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD5_DS1 | RW | Pad 5 high order drive strength selection. Used in conjunction with PAD5STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD4_SR | RW | Pad 7 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD4_DS1 | RW | Pad 4 high order drive strength selection. Used in conjunction with PAD4STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010100 |
This register has additional configuration control for pads [11:8]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD11_SR
0x0 |
RSVD
0x0 |
PAD11_DS1
0x0 |
RSVD
0x0 |
PAD10_SR
0x0 |
RSVD
0x0 |
PAD10_DS1
0x0 |
RSVD
0x0 |
PAD9_SR
0x0 |
RSVD
0x0 |
PAD9_DS1
0x0 |
RSVD
0x0 |
PAD8_SR
0x0 |
RSVD
0x0 |
PAD8_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD11_SR | RW | Pad 11 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD11_DS1 | RW | Pad 11 high order drive strength selection. Used in conjunction with PAD11STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD10_SR | RW | Pad 11 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD10_DS1 | RW | Pad 10 high order drive strength selection. Used in conjunction with PAD10STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD9_SR | RW | Pad 11 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD9_DS1 | RW | Pad 9 high order drive strength selection. Used in conjunction with PAD9STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD8_SR | RW | Pad 11 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD8_DS1 | RW | Pad 8 high order drive strength selection. Used in conjunction with PAD8STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010104 |
This register has additional configuration control for pads [15:12]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD15_SR
0x0 |
RSVD
0x0 |
PAD15_DS1
0x0 |
RSVD
0x0 |
PAD14_SR
0x0 |
RSVD
0x0 |
PAD14_DS1
0x0 |
RSVD
0x0 |
PAD13_SR
0x0 |
RSVD
0x0 |
PAD13_DS1
0x0 |
RSVD
0x0 |
PAD12_SR
0x0 |
RSVD
0x0 |
PAD12_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD15_SR | RW | Pad 15 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD15_DS1 | RW | Pad 15 high order drive strength selection. Used in conjunction with PAD15STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD14_SR | RW | Pad 15 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD14_DS1 | RW | Pad 14 high order drive strength selection. Used in conjunction with PAD14STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD13_SR | RW | Pad 15 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD13_DS1 | RW | Pad 13 high order drive strength selection. Used in conjunction with PAD13STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD12_SR | RW | Pad 15 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD12_DS1 | RW | Pad 12 high order drive strength selection. Used in conjunction with PAD12STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010108 |
This register has additional configuration control for pads [19:16]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD19_SR
0x0 |
RSVD
0x0 |
PAD19_DS1
0x0 |
RSVD
0x0 |
PAD18_SR
0x0 |
RSVD
0x0 |
PAD18_DS1
0x0 |
RSVD
0x0 |
PAD17_SR
0x0 |
RSVD
0x0 |
PAD17_DS1
0x0 |
RSVD
0x0 |
PAD16_SR
0x0 |
RSVD
0x0 |
PAD16_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD19_SR | RW | Pad 19 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD19_DS1 | RW | Pad 19 high order drive strength selection. Used in conjunction with PAD19STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD18_SR | RW | Pad 19 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD18_DS1 | RW | Pad 18 high order drive strength selection. Used in conjunction with PAD18STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD17_SR | RW | Pad 19 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD17_DS1 | RW | Pad 17 high order drive strength selection. Used in conjunction with PAD17STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD16_SR | RW | Pad 19 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD16_DS1 | RW | Pad 16 high order drive strength selection. Used in conjunction with PAD16STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x4001010C |
This register has additional configuration control for pads [23:20]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD23_SR
0x0 |
RSVD
0x0 |
PAD23_DS1
0x0 |
RSVD
0x0 |
PAD22_SR
0x0 |
RSVD
0x0 |
PAD22_DS1
0x0 |
RSVD
0x0 |
PAD21_SR
0x0 |
RSVD
0x0 |
PAD21_DS1
0x0 |
RSVD
0x0 |
PAD20_SR
0x0 |
RSVD
0x0 |
PAD20_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD23_SR | RW | Pad 23 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD23_DS1 | RW | Pad 23 high order drive strength selection. Used in conjunction with PAD23STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD22_SR | RW | Pad 23 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD22_DS1 | RW | Pad 22 high order drive strength selection. Used in conjunction with PAD22STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD21_SR | RW | Pad 23 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD21_DS1 | RW | Pad 21 high order drive strength selection. Used in conjunction with PAD21STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD20_SR | RW | Pad 23 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD20_DS1 | RW | Pad 20 high order drive strength selection. Used in conjunction with PAD20STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010110 |
This register has additional configuration control for pads [27:24]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD27_SR
0x0 |
RSVD
0x0 |
PAD27_DS1
0x0 |
RSVD
0x0 |
PAD26_SR
0x0 |
RSVD
0x0 |
PAD26_DS1
0x0 |
RSVD
0x0 |
PAD25_SR
0x0 |
RSVD
0x0 |
PAD25_DS1
0x0 |
RSVD
0x0 |
PAD24_SR
0x0 |
RSVD
0x0 |
PAD24_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD27_SR | RW | Pad 27 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD27_DS1 | RW | Pad 27 high order drive strength selection. Used in conjunction with PAD27STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD26_SR | RW | Pad 27 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD26_DS1 | RW | Pad 26 high order drive strength selection. Used in conjunction with PAD26STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD25_SR | RW | Pad 27 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD25_DS1 | RW | Pad 25 high order drive strength selection. Used in conjunction with PAD25STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD24_SR | RW | Pad 27 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD24_DS1 | RW | Pad 24 high order drive strength selection. Used in conjunction with PAD24STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010114 |
This register has additional configuration control for pads [31:28]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD31_SR
0x0 |
RSVD
0x0 |
PAD31_DS1
0x0 |
RSVD
0x0 |
PAD30_SR
0x0 |
RSVD
0x0 |
PAD30_DS1
0x0 |
RSVD
0x0 |
PAD29_SR
0x0 |
RSVD
0x0 |
PAD29_DS1
0x0 |
RSVD
0x0 |
PAD28_SR
0x0 |
RSVD
0x0 |
PAD28_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD31_SR | RW | Pad 31 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD31_DS1 | RW | Pad 31 high order drive strength selection. Used in conjunction with PAD31STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD30_SR | RW | Pad 31 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD30_DS1 | RW | Pad 30 high order drive strength selection. Used in conjunction with PAD30STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD29_SR | RW | Pad 31 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD29_DS1 | RW | Pad 29 high order drive strength selection. Used in conjunction with PAD29STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD28_SR | RW | Pad 31 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD28_DS1 | RW | Pad 28 high order drive strength selection. Used in conjunction with PAD28STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010118 |
This register has additional configuration control for pads [35:32]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD35_SR
0x0 |
RSVD
0x0 |
PAD35_DS1
0x0 |
RSVD
0x0 |
PAD34_SR
0x0 |
RSVD
0x0 |
PAD34_DS1
0x0 |
RSVD
0x0 |
PAD33_SR
0x0 |
RSVD
0x0 |
PAD33_DS1
0x0 |
RSVD
0x0 |
PAD32_SR
0x0 |
RSVD
0x0 |
PAD32_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD35_SR | RW | Pad 35 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD35_DS1 | RW | Pad 35 high order drive strength selection. Used in conjunction with PAD35STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD34_SR | RW | Pad 35 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD34_DS1 | RW | Pad 34 high order drive strength selection. Used in conjunction with PAD34STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD33_SR | RW | Pad 35 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD33_DS1 | RW | Pad 33 high order drive strength selection. Used in conjunction with PAD33STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD32_SR | RW | Pad 35 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD32_DS1 | RW | Pad 32 high order drive strength selection. Used in conjunction with PAD32STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x4001011C |
This register has additional configuration control for pads [39:36]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD39_SR
0x0 |
RSVD
0x0 |
PAD39_DS1
0x0 |
RSVD
0x0 |
PAD38_SR
0x0 |
RSVD
0x0 |
PAD38_DS1
0x0 |
RSVD
0x0 |
PAD37_SR
0x0 |
RSVD
0x0 |
PAD37_DS1
0x0 |
RSVD
0x0 |
PAD36_SR
0x0 |
RSVD
0x0 |
PAD36_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD39_SR | RW | Pad 39 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD39_DS1 | RW | Pad 39 high order drive strength selection. Used in conjunction with PAD39STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD38_SR | RW | Pad 39 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD38_DS1 | RW | Pad 38 high order drive strength selection. Used in conjunction with PAD38STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD37_SR | RW | Pad 39 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD37_DS1 | RW | Pad 37 high order drive strength selection. Used in conjunction with PAD37STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD36_SR | RW | Pad 39 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD36_DS1 | RW | Pad 36 high order drive strength selection. Used in conjunction with PAD36STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010120 |
This register has additional configuration control for pads [43:40]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD43_SR
0x0 |
RSVD
0x0 |
PAD43_DS1
0x0 |
RSVD
0x0 |
PAD42_SR
0x0 |
RSVD
0x0 |
PAD42_DS1
0x0 |
RSVD
0x0 |
PAD41_SR
0x0 |
RSVD
0x0 |
PAD41_DS1
0x0 |
RSVD
0x0 |
PAD40_SR
0x0 |
RSVD
0x0 |
PAD40_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD43_SR | RW | Pad 43 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD43_DS1 | RW | Pad 43 high order drive strength selection. Used in conjunction with PAD43STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD42_SR | RW | Pad 43 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD42_DS1 | RW | Pad 42 high order drive strength selection. Used in conjunction with PAD42STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD41_SR | RW | Pad 43 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD41_DS1 | RW | Pad 41 high order drive strength selection. Used in conjunction with PAD41STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD40_SR | RW | Pad 43 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD40_DS1 | RW | Pad 40 high order drive strength selection. Used in conjunction with PAD40STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010124 |
This register has additional configuration control for pads [47:44]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD47_SR
0x0 |
RSVD
0x0 |
PAD47_DS1
0x0 |
RSVD
0x0 |
PAD46_SR
0x0 |
RSVD
0x0 |
PAD46_DS1
0x0 |
RSVD
0x0 |
PAD45_SR
0x0 |
RSVD
0x0 |
PAD45_DS1
0x0 |
RSVD
0x0 |
PAD44_SR
0x0 |
RSVD
0x0 |
PAD44_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD47_SR | RW | Pad 47 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD47_DS1 | RW | Pad 47 high order drive strength selection. Used in conjunction with PAD47STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD46_SR | RW | Pad 47 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD46_DS1 | RW | Pad 46 high order drive strength selection. Used in conjunction with PAD46STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD45_SR | RW | Pad 47 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD45_DS1 | RW | Pad 45 high order drive strength selection. Used in conjunction with PAD45STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD44_SR | RW | Pad 47 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD44_DS1 | RW | Pad 44 high order drive strength selection. Used in conjunction with PAD44STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010128 |
This register has additional configuration control for pads [51:48]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD51_SR
0x0 |
RSVD
0x0 |
PAD51_DS1
0x0 |
RSVD
0x0 |
PAD50_SR
0x0 |
RSVD
0x0 |
PAD50_DS1
0x0 |
RSVD
0x0 |
PAD49_SR
0x0 |
RSVD
0x0 |
PAD49_DS1
0x0 |
RSVD
0x0 |
PAD48_SR
0x0 |
RSVD
0x0 |
PAD48_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD51_SR | RW | Pad 51 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD51_DS1 | RW | Pad 51 high order drive strength selection. Used in conjunction with PAD51STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD50_SR | RW | Pad 51 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD50_DS1 | RW | Pad 50 high order drive strength selection. Used in conjunction with PAD50STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD49_SR | RW | Pad 51 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD49_DS1 | RW | Pad 49 high order drive strength selection. Used in conjunction with PAD49STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD48_SR | RW | Pad 51 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD48_DS1 | RW | Pad 48 high order drive strength selection. Used in conjunction with PAD48STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x4001012C |
This register has additional configuration control for pads [55:52]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD55_SR
0x0 |
RSVD
0x0 |
PAD55_DS1
0x0 |
RSVD
0x0 |
PAD54_SR
0x0 |
RSVD
0x0 |
PAD54_DS1
0x0 |
RSVD
0x0 |
PAD53_SR
0x0 |
RSVD
0x0 |
PAD53_DS1
0x0 |
RSVD
0x0 |
PAD52_SR
0x0 |
RSVD
0x0 |
PAD52_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD55_SR | RW | Pad 55 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD55_DS1 | RW | Pad 55 high order drive strength selection. Used in conjunction with PAD55STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD54_SR | RW | Pad 55 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD54_DS1 | RW | Pad 54 high order drive strength selection. Used in conjunction with PAD54STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD53_SR | RW | Pad 55 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD53_DS1 | RW | Pad 53 high order drive strength selection. Used in conjunction with PAD53STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD52_SR | RW | Pad 55 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD52_DS1 | RW | Pad 52 high order drive strength selection. Used in conjunction with PAD52STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010130 |
This register has additional configuration control for pads [59:56]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD59_SR
0x0 |
RSVD
0x0 |
PAD59_DS1
0x0 |
RSVD
0x0 |
PAD58_SR
0x0 |
RSVD
0x0 |
PAD58_DS1
0x0 |
RSVD
0x0 |
PAD57_SR
0x0 |
RSVD
0x0 |
PAD57_DS1
0x0 |
RSVD
0x0 |
PAD56_SR
0x0 |
RSVD
0x0 |
PAD56_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD59_SR | RW | Pad 59 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD59_DS1 | RW | Pad 59 high order drive strength selection. Used in conjunction with PAD59STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD58_SR | RW | Pad 59 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD58_DS1 | RW | Pad 58 high order drive strength selection. Used in conjunction with PAD58STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD57_SR | RW | Pad 59 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD57_DS1 | RW | Pad 57 high order drive strength selection. Used in conjunction with PAD57STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD56_SR | RW | Pad 59 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD56_DS1 | RW | Pad 56 high order drive strength selection. Used in conjunction with PAD56STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010134 |
This register has additional configuration control for pads [63:60]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD63_SR
0x0 |
RSVD
0x0 |
PAD63_DS1
0x0 |
RSVD
0x0 |
PAD62_SR
0x0 |
RSVD
0x0 |
PAD62_DS1
0x0 |
RSVD
0x0 |
PAD61_SR
0x0 |
RSVD
0x0 |
PAD61_DS1
0x0 |
RSVD
0x0 |
PAD60_SR
0x0 |
RSVD
0x0 |
PAD60_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD63_SR | RW | Pad 63 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD63_DS1 | RW | Pad 63 high order drive strength selection. Used in conjunction with PAD63STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD62_SR | RW | Pad 63 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD62_DS1 | RW | Pad 62 high order drive strength selection. Used in conjunction with PAD62STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD61_SR | RW | Pad 63 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD61_DS1 | RW | Pad 61 high order drive strength selection. Used in conjunction with PAD61STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD60_SR | RW | Pad 63 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD60_DS1 | RW | Pad 60 high order drive strength selection. Used in conjunction with PAD60STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010138 |
This register has additional configuration control for pads [67:64]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD67_SR
0x0 |
RSVD
0x0 |
PAD67_DS1
0x0 |
RSVD
0x0 |
PAD66_SR
0x0 |
RSVD
0x0 |
PAD66_DS1
0x0 |
RSVD
0x0 |
PAD65_SR
0x0 |
RSVD
0x0 |
PAD65_DS1
0x0 |
RSVD
0x0 |
PAD64_SR
0x0 |
RSVD
0x0 |
PAD64_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD67_SR | RW | Pad 67 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD67_DS1 | RW | Pad 67 high order drive strength selection. Used in conjunction with PAD67STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD66_SR | RW | Pad 67 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD66_DS1 | RW | Pad 66 high order drive strength selection. Used in conjunction with PAD66STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD65_SR | RW | Pad 67 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD65_DS1 | RW | Pad 65 high order drive strength selection. Used in conjunction with PAD65STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD64_SR | RW | Pad 67 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD64_DS1 | RW | Pad 64 high order drive strength selection. Used in conjunction with PAD64STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x4001013C |
This register has additional configuration control for pads [71:68]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
PAD71_SR
0x0 |
RSVD
0x0 |
PAD71_DS1
0x0 |
RSVD
0x0 |
PAD70_SR
0x0 |
RSVD
0x0 |
PAD70_DS1
0x0 |
RSVD
0x0 |
PAD69_SR
0x0 |
RSVD
0x0 |
PAD69_DS1
0x0 |
RSVD
0x0 |
PAD68_SR
0x0 |
RSVD
0x0 |
PAD68_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | RESERVED |
| 28 | PAD71_SR | RW | Pad 71 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 27:25 | RSVD | RO | RESERVED |
| 24 | PAD71_DS1 | RW | Pad 71 high order drive strength selection. Used in conjunction with PAD71STRNG field to set the pad drive strength. |
| 23:21 | RSVD | RO | RESERVED |
| 20 | PAD70_SR | RW | Pad 71 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 19:17 | RSVD | RO | RESERVED |
| 16 | PAD70_DS1 | RW | Pad 70 high order drive strength selection. Used in conjunction with PAD70STRNG field to set the pad drive strength. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD69_SR | RW | Pad 71 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD69_DS1 | RW | Pad 69 high order drive strength selection. Used in conjunction with PAD69STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD68_SR | RW | Pad 71 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD68_DS1 | RW | Pad 68 high order drive strength selection. Used in conjunction with PAD68STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010140 |
This register has additional configuration control for pads [73:72]
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
RSVD
0x0 |
RSVD
0x0 |
PAD73_SR
0x0 |
RSVD
0x0 |
PAD73_DS1
0x0 |
RSVD
0x0 |
PAD72_SR
0x0 |
RSVD
0x0 |
PAD72_DS1
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:24 | RSVD | RO | RESERVED |
| 23:16 | RSVD | RO | RESERVED |
| 15:13 | RSVD | RO | RESERVED |
| 12 | PAD73_SR | RW | Pad 73 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 11:9 | RSVD | RO | RESERVED |
| 8 | PAD73_DS1 | RW | Pad 73 high order drive strength selection. Used in conjunction with PAD73STRNG field to set the pad drive strength. |
| 7:5 | RSVD | RO | RESERVED |
| 4 | PAD72_SR | RW | Pad 72 slew rate selection. SR_EN = 0x1 - Enables Slew rate control on pad |
| 3:1 | RSVD | RO | RESERVED |
| 0 | PAD72_DS1 | RW | Pad 72 high order drive strength selection. Used in conjunction with PAD72STRNG field to set the pad drive strength. |
| Instance 0 Address: | 0x40010144 |
SCARD card detect select.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
SCDET
0x7f |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:7 | RSVD | RO | RESERVED |
| 6:0 | SCDET | RW | SCARD card detect pad select. |
| Instance 0 Address: | 0x40010148 |
Pad enable configuration.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| EN31
0x1 |
EN30
0x1 |
EN29
0x1 |
EN28
0x1 |
EN27
0x1 |
EN26
0x1 |
EN25
0x1 |
EN24
0x1 |
EN23
0x1 |
EN22
0x1 |
EN21
0x1 |
EN20
0x1 |
EN19
0x1 |
EN18
0x1 |
EN17
0x1 |
EN16
0x1 |
EN15
0x1 |
EN14
0x1 |
EN13
0x1 |
EN12
0x1 |
EN11
0x1 |
EN10
0x1 |
EN9
0x1 |
EN8
0x1 |
EN7
0x1 |
EN6
0x1 |
EN5
0x1 |
EN4
0x1 |
EN3
0x1 |
EN2
0x1 |
EN1
0x1 |
EN0
0x1 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | EN31 | RW | CT31 Enable DIS = 0x1 - Disable CT31 for output EN = 0x0 - Enable CT31 for output |
| 30 | EN30 | RW | CT30 Enable DIS = 0x1 - Disable CT30 for output EN = 0x0 - Enable CT30 for output |
| 29 | EN29 | RW | CT29 Enable DIS = 0x1 - Disable CT29 for output EN = 0x0 - Enable CT29 for output |
| 28 | EN28 | RW | CT28 Enable DIS = 0x1 - Disable CT28 for output EN = 0x0 - Enable CT28 for output |
| 27 | EN27 | RW | CT27 Enable DIS = 0x1 - Disable CT27 for output EN = 0x0 - Enable CT27 for output |
| 26 | EN26 | RW | CT26 Enable DIS = 0x1 - Disable CT26 for output EN = 0x0 - Enable CT26 for output |
| 25 | EN25 | RW | CT25 Enable DIS = 0x1 - Disable CT25 for output EN = 0x0 - Enable CT25 for output |
| 24 | EN24 | RW | CT24 Enable DIS = 0x1 - Disable CT24 for output EN = 0x0 - Enable CT24 for output |
| 23 | EN23 | RW | CT23 Enable DIS = 0x1 - Disable CT23 for output EN = 0x0 - Enable CT23 for output |
| 22 | EN22 | RW | CT22 Enable DIS = 0x1 - Disable CT22 for output EN = 0x0 - Enable CT22 for output |
| 21 | EN21 | RW | CT21 Enable DIS = 0x1 - Disable CT21 for output EN = 0x0 - Enable CT21 for output |
| 20 | EN20 | RW | CT20 Enable DIS = 0x1 - Disable CT20 for output EN = 0x0 - Enable CT20 for output |
| 19 | EN19 | RW | CT19 Enable DIS = 0x1 - Disable CT19 for output EN = 0x0 - Enable CT19 for output |
| 18 | EN18 | RW | CT18 Enable DIS = 0x1 - Disable CT18 for output EN = 0x0 - Enable CT18 for output |
| 17 | EN17 | RW | CT17 Enable DIS = 0x1 - Disable CT17 for output EN = 0x0 - Enable CT17 for output |
| 16 | EN16 | RW | CT16 Enable DIS = 0x1 - Disable CT16 for output EN = 0x0 - Enable CT16 for output |
| 15 | EN15 | RW | CT15 Enable DIS = 0x1 - Disable CT15 for output EN = 0x0 - Enable CT15 for output |
| 14 | EN14 | RW | CT14 Enable DIS = 0x1 - Disable CT14 for output EN = 0x0 - Enable CT14 for output |
| 13 | EN13 | RW | CT13 Enable DIS = 0x1 - Disable CT13 for output EN = 0x0 - Enable CT13 for output |
| 12 | EN12 | RW | CT12 Enable DIS = 0x1 - Disable CT12 for output EN = 0x0 - Enable CT12 for output |
| 11 | EN11 | RW | CT11 Enable DIS = 0x1 - Disable CT11 for output EN = 0x0 - Enable CT11 for output |
| 10 | EN10 | RW | CT10 Enable DIS = 0x1 - Disable CT10 for output EN = 0x0 - Enable CT10 for output |
| 9 | EN9 | RW | CT9 Enable DIS = 0x0 - Disable CT9 for output EN = 0x0 - Enable CT9 for output |
| 8 | EN8 | RW | CT8 Enable DIS = 0x1 - Disable CT8 for output EN = 0x0 - Enable CT8 for output |
| 7 | EN7 | RW | CT7 Enable DIS = 0x1 - Disable CT7 for output EN = 0x0 - Enable CT7 for output |
| 6 | EN6 | RW | CT6 Enable DIS = 0x1 - Disable CT6 for output EN = 0x0 - Enable CT6 for output |
| 5 | EN5 | RW | CT5 Enable DIS = 0x1 - Disable CT5 for output EN = 0x0 - Enable CT5 for output |
| 4 | EN4 | RW | CT4 Enable DIS = 0x1 - Disable CT4 for output EN = 0x0 - Enable CT4 for output |
| 3 | EN3 | RW | CT3 Enable DIS = 0x1 - Disable CT3 for output EN = 0x0 - Enable CT3 for output |
| 2 | EN2 | RW | CT2 Enable DIS = 0x1 - Disable CT2 for output EN = 0x0 - Enable CT2 for output |
| 1 | EN1 | RW | CT1 Enable DIS = 0x1 - Disable CT1 for output EN = 0x0 - Enable CT1 for output |
| 0 | EN0 | RW | CT0 Enable DIS = 0x1 - Disable CT0 for output EN = 0x0 - Enable CT0 for output |
| Instance 0 Address: | 0x40010200 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO31 | RW | GPIO31 interrupt. |
| 30 | GPIO30 | RW | GPIO30 interrupt. |
| 29 | GPIO29 | RW | GPIO29 interrupt. |
| 28 | GPIO28 | RW | GPIO28 interrupt. |
| 27 | GPIO27 | RW | GPIO27 interrupt. |
| 26 | GPIO26 | RW | GPIO26 interrupt. |
| 25 | GPIO25 | RW | GPIO25 interrupt. |
| 24 | GPIO24 | RW | GPIO24 interrupt. |
| 23 | GPIO23 | RW | GPIO23 interrupt. |
| 22 | GPIO22 | RW | GPIO22 interrupt. |
| 21 | GPIO21 | RW | GPIO21 interrupt. |
| 20 | GPIO20 | RW | GPIO20 interrupt. |
| 19 | GPIO19 | RW | GPIO19 interrupt. |
| 18 | GPIO18 | RW | GPIO18interrupt. |
| 17 | GPIO17 | RW | GPIO17 interrupt. |
| 16 | GPIO16 | RW | GPIO16 interrupt. |
| 15 | GPIO15 | RW | GPIO15 interrupt. |
| 14 | GPIO14 | RW | GPIO14 interrupt. |
| 13 | GPIO13 | RW | GPIO13 interrupt. |
| 12 | GPIO12 | RW | GPIO12 interrupt. |
| 11 | GPIO11 | RW | GPIO11 interrupt. |
| 10 | GPIO10 | RW | GPIO10 interrupt. |
| 9 | GPIO9 | RW | GPIO9 interrupt. |
| 8 | GPIO8 | RW | GPIO8 interrupt. |
| 7 | GPIO7 | RW | GPIO7 interrupt. |
| 6 | GPIO6 | RW | GPIO6 interrupt. |
| 5 | GPIO5 | RW | GPIO5 interrupt. |
| 4 | GPIO4 | RW | GPIO4 interrupt. |
| 3 | GPIO3 | RW | GPIO3 interrupt. |
| 2 | GPIO2 | RW | GPIO2 interrupt. |
| 1 | GPIO1 | RW | GPIO1 interrupt. |
| 0 | GPIO0 | RW | GPIO0 interrupt. |
| Instance 0 Address: | 0x40010204 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO31 | RW | GPIO31 interrupt. |
| 30 | GPIO30 | RW | GPIO30 interrupt. |
| 29 | GPIO29 | RW | GPIO29 interrupt. |
| 28 | GPIO28 | RW | GPIO28 interrupt. |
| 27 | GPIO27 | RW | GPIO27 interrupt. |
| 26 | GPIO26 | RW | GPIO26 interrupt. |
| 25 | GPIO25 | RW | GPIO25 interrupt. |
| 24 | GPIO24 | RW | GPIO24 interrupt. |
| 23 | GPIO23 | RW | GPIO23 interrupt. |
| 22 | GPIO22 | RW | GPIO22 interrupt. |
| 21 | GPIO21 | RW | GPIO21 interrupt. |
| 20 | GPIO20 | RW | GPIO20 interrupt. |
| 19 | GPIO19 | RW | GPIO19 interrupt. |
| 18 | GPIO18 | RW | GPIO18interrupt. |
| 17 | GPIO17 | RW | GPIO17 interrupt. |
| 16 | GPIO16 | RW | GPIO16 interrupt. |
| 15 | GPIO15 | RW | GPIO15 interrupt. |
| 14 | GPIO14 | RW | GPIO14 interrupt. |
| 13 | GPIO13 | RW | GPIO13 interrupt. |
| 12 | GPIO12 | RW | GPIO12 interrupt. |
| 11 | GPIO11 | RW | GPIO11 interrupt. |
| 10 | GPIO10 | RW | GPIO10 interrupt. |
| 9 | GPIO9 | RW | GPIO9 interrupt. |
| 8 | GPIO8 | RW | GPIO8 interrupt. |
| 7 | GPIO7 | RW | GPIO7 interrupt. |
| 6 | GPIO6 | RW | GPIO6 interrupt. |
| 5 | GPIO5 | RW | GPIO5 interrupt. |
| 4 | GPIO4 | RW | GPIO4 interrupt. |
| 3 | GPIO3 | RW | GPIO3 interrupt. |
| 2 | GPIO2 | RW | GPIO2 interrupt. |
| 1 | GPIO1 | RW | GPIO1 interrupt. |
| 0 | GPIO0 | RW | GPIO0 interrupt. |
| Instance 0 Address: | 0x40010208 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO31 | RW | GPIO31 interrupt. |
| 30 | GPIO30 | RW | GPIO30 interrupt. |
| 29 | GPIO29 | RW | GPIO29 interrupt. |
| 28 | GPIO28 | RW | GPIO28 interrupt. |
| 27 | GPIO27 | RW | GPIO27 interrupt. |
| 26 | GPIO26 | RW | GPIO26 interrupt. |
| 25 | GPIO25 | RW | GPIO25 interrupt. |
| 24 | GPIO24 | RW | GPIO24 interrupt. |
| 23 | GPIO23 | RW | GPIO23 interrupt. |
| 22 | GPIO22 | RW | GPIO22 interrupt. |
| 21 | GPIO21 | RW | GPIO21 interrupt. |
| 20 | GPIO20 | RW | GPIO20 interrupt. |
| 19 | GPIO19 | RW | GPIO19 interrupt. |
| 18 | GPIO18 | RW | GPIO18interrupt. |
| 17 | GPIO17 | RW | GPIO17 interrupt. |
| 16 | GPIO16 | RW | GPIO16 interrupt. |
| 15 | GPIO15 | RW | GPIO15 interrupt. |
| 14 | GPIO14 | RW | GPIO14 interrupt. |
| 13 | GPIO13 | RW | GPIO13 interrupt. |
| 12 | GPIO12 | RW | GPIO12 interrupt. |
| 11 | GPIO11 | RW | GPIO11 interrupt. |
| 10 | GPIO10 | RW | GPIO10 interrupt. |
| 9 | GPIO9 | RW | GPIO9 interrupt. |
| 8 | GPIO8 | RW | GPIO8 interrupt. |
| 7 | GPIO7 | RW | GPIO7 interrupt. |
| 6 | GPIO6 | RW | GPIO6 interrupt. |
| 5 | GPIO5 | RW | GPIO5 interrupt. |
| 4 | GPIO4 | RW | GPIO4 interrupt. |
| 3 | GPIO3 | RW | GPIO3 interrupt. |
| 2 | GPIO2 | RW | GPIO2 interrupt. |
| 1 | GPIO1 | RW | GPIO1 interrupt. |
| 0 | GPIO0 | RW | GPIO0 interrupt. |
| Instance 0 Address: | 0x4001020C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO31
0x0 |
GPIO30
0x0 |
GPIO29
0x0 |
GPIO28
0x0 |
GPIO27
0x0 |
GPIO26
0x0 |
GPIO25
0x0 |
GPIO24
0x0 |
GPIO23
0x0 |
GPIO22
0x0 |
GPIO21
0x0 |
GPIO20
0x0 |
GPIO19
0x0 |
GPIO18
0x0 |
GPIO17
0x0 |
GPIO16
0x0 |
GPIO15
0x0 |
GPIO14
0x0 |
GPIO13
0x0 |
GPIO12
0x0 |
GPIO11
0x0 |
GPIO10
0x0 |
GPIO9
0x0 |
GPIO8
0x0 |
GPIO7
0x0 |
GPIO6
0x0 |
GPIO5
0x0 |
GPIO4
0x0 |
GPIO3
0x0 |
GPIO2
0x0 |
GPIO1
0x0 |
GPIO0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO31 | RW | GPIO31 interrupt. |
| 30 | GPIO30 | RW | GPIO30 interrupt. |
| 29 | GPIO29 | RW | GPIO29 interrupt. |
| 28 | GPIO28 | RW | GPIO28 interrupt. |
| 27 | GPIO27 | RW | GPIO27 interrupt. |
| 26 | GPIO26 | RW | GPIO26 interrupt. |
| 25 | GPIO25 | RW | GPIO25 interrupt. |
| 24 | GPIO24 | RW | GPIO24 interrupt. |
| 23 | GPIO23 | RW | GPIO23 interrupt. |
| 22 | GPIO22 | RW | GPIO22 interrupt. |
| 21 | GPIO21 | RW | GPIO21 interrupt. |
| 20 | GPIO20 | RW | GPIO20 interrupt. |
| 19 | GPIO19 | RW | GPIO19 interrupt. |
| 18 | GPIO18 | RW | GPIO18interrupt. |
| 17 | GPIO17 | RW | GPIO17 interrupt. |
| 16 | GPIO16 | RW | GPIO16 interrupt. |
| 15 | GPIO15 | RW | GPIO15 interrupt. |
| 14 | GPIO14 | RW | GPIO14 interrupt. |
| 13 | GPIO13 | RW | GPIO13 interrupt. |
| 12 | GPIO12 | RW | GPIO12 interrupt. |
| 11 | GPIO11 | RW | GPIO11 interrupt. |
| 10 | GPIO10 | RW | GPIO10 interrupt. |
| 9 | GPIO9 | RW | GPIO9 interrupt. |
| 8 | GPIO8 | RW | GPIO8 interrupt. |
| 7 | GPIO7 | RW | GPIO7 interrupt. |
| 6 | GPIO6 | RW | GPIO6 interrupt. |
| 5 | GPIO5 | RW | GPIO5 interrupt. |
| 4 | GPIO4 | RW | GPIO4 interrupt. |
| 3 | GPIO3 | RW | GPIO3 interrupt. |
| 2 | GPIO2 | RW | GPIO2 interrupt. |
| 1 | GPIO1 | RW | GPIO1 interrupt. |
| 0 | GPIO0 | RW | GPIO0 interrupt. |
| Instance 0 Address: | 0x40010220 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO63
0x0 |
GPIO62
0x0 |
GPIO61
0x0 |
GPIO60
0x0 |
GPIO59
0x0 |
GPIO58
0x0 |
GPIO57
0x0 |
GPIO56
0x0 |
GPIO55
0x0 |
GPIO54
0x0 |
GPIO53
0x0 |
GPIO52
0x0 |
GPIO51
0x0 |
GPIO50
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO63 | RW | GPIO63 interrupt. |
| 30 | GPIO62 | RW | GPIO62 interrupt. |
| 29 | GPIO61 | RW | GPIO61 interrupt. |
| 28 | GPIO60 | RW | GPIO60 interrupt. |
| 27 | GPIO59 | RW | GPIO59 interrupt. |
| 26 | GPIO58 | RW | GPIO58 interrupt. |
| 25 | GPIO57 | RW | GPIO57 interrupt. |
| 24 | GPIO56 | RW | GPIO56 interrupt. |
| 23 | GPIO55 | RW | GPIO55 interrupt. |
| 22 | GPIO54 | RW | GPIO54 interrupt. |
| 21 | GPIO53 | RW | GPIO53 interrupt. |
| 20 | GPIO52 | RW | GPIO52 interrupt. |
| 19 | GPIO51 | RW | GPIO51 interrupt. |
| 18 | GPIO50 | RW | GPIO50 interrupt. |
| 17 | GPIO49 | RW | GPIO49 interrupt. |
| 16 | GPIO48 | RW | GPIO48 interrupt. |
| 15 | GPIO47 | RW | GPIO47 interrupt. |
| 14 | GPIO46 | RW | GPIO46 interrupt. |
| 13 | GPIO45 | RW | GPIO45 interrupt. |
| 12 | GPIO44 | RW | GPIO44 interrupt. |
| 11 | GPIO43 | RW | GPIO43 interrupt. |
| 10 | GPIO42 | RW | GPIO42 interrupt. |
| 9 | GPIO41 | RW | GPIO41 interrupt. |
| 8 | GPIO40 | RW | GPIO40 interrupt. |
| 7 | GPIO39 | RW | GPIO39 interrupt. |
| 6 | GPIO38 | RW | GPIO38 interrupt. |
| 5 | GPIO37 | RW | GPIO37 interrupt. |
| 4 | GPIO36 | RW | GPIO36 interrupt. |
| 3 | GPIO35 | RW | GPIO35 interrupt. |
| 2 | GPIO34 | RW | GPIO34 interrupt. |
| 1 | GPIO33 | RW | GPIO33 interrupt. |
| 0 | GPIO32 | RW | GPIO32 interrupt. |
| Instance 0 Address: | 0x40010224 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO63
0x0 |
GPIO62
0x0 |
GPIO61
0x0 |
GPIO60
0x0 |
GPIO59
0x0 |
GPIO58
0x0 |
GPIO57
0x0 |
GPIO56
0x0 |
GPIO55
0x0 |
GPIO54
0x0 |
GPIO53
0x0 |
GPIO52
0x0 |
GPIO51
0x0 |
GPIO50
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO63 | RW | GPIO63 interrupt. |
| 30 | GPIO62 | RW | GPIO62 interrupt. |
| 29 | GPIO61 | RW | GPIO61 interrupt. |
| 28 | GPIO60 | RW | GPIO60 interrupt. |
| 27 | GPIO59 | RW | GPIO59 interrupt. |
| 26 | GPIO58 | RW | GPIO58 interrupt. |
| 25 | GPIO57 | RW | GPIO57 interrupt. |
| 24 | GPIO56 | RW | GPIO56 interrupt. |
| 23 | GPIO55 | RW | GPIO55 interrupt. |
| 22 | GPIO54 | RW | GPIO54 interrupt. |
| 21 | GPIO53 | RW | GPIO53 interrupt. |
| 20 | GPIO52 | RW | GPIO52 interrupt. |
| 19 | GPIO51 | RW | GPIO51 interrupt. |
| 18 | GPIO50 | RW | GPIO50 interrupt. |
| 17 | GPIO49 | RW | GPIO49 interrupt. |
| 16 | GPIO48 | RW | GPIO48 interrupt. |
| 15 | GPIO47 | RW | GPIO47 interrupt. |
| 14 | GPIO46 | RW | GPIO46 interrupt. |
| 13 | GPIO45 | RW | GPIO45 interrupt. |
| 12 | GPIO44 | RW | GPIO44 interrupt. |
| 11 | GPIO43 | RW | GPIO43 interrupt. |
| 10 | GPIO42 | RW | GPIO42 interrupt. |
| 9 | GPIO41 | RW | GPIO41 interrupt. |
| 8 | GPIO40 | RW | GPIO40 interrupt. |
| 7 | GPIO39 | RW | GPIO39 interrupt. |
| 6 | GPIO38 | RW | GPIO38 interrupt. |
| 5 | GPIO37 | RW | GPIO37 interrupt. |
| 4 | GPIO36 | RW | GPIO36 interrupt. |
| 3 | GPIO35 | RW | GPIO35 interrupt. |
| 2 | GPIO34 | RW | GPIO34 interrupt. |
| 1 | GPIO33 | RW | GPIO33 interrupt. |
| 0 | GPIO32 | RW | GPIO32 interrupt. |
| Instance 0 Address: | 0x40010228 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO63
0x0 |
GPIO62
0x0 |
GPIO61
0x0 |
GPIO60
0x0 |
GPIO59
0x0 |
GPIO58
0x0 |
GPIO57
0x0 |
GPIO56
0x0 |
GPIO55
0x0 |
GPIO54
0x0 |
GPIO53
0x0 |
GPIO52
0x0 |
GPIO51
0x0 |
GPIO50
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO63 | RW | GPIO63 interrupt. |
| 30 | GPIO62 | RW | GPIO62 interrupt. |
| 29 | GPIO61 | RW | GPIO61 interrupt. |
| 28 | GPIO60 | RW | GPIO60 interrupt. |
| 27 | GPIO59 | RW | GPIO59 interrupt. |
| 26 | GPIO58 | RW | GPIO58 interrupt. |
| 25 | GPIO57 | RW | GPIO57 interrupt. |
| 24 | GPIO56 | RW | GPIO56 interrupt. |
| 23 | GPIO55 | RW | GPIO55 interrupt. |
| 22 | GPIO54 | RW | GPIO54 interrupt. |
| 21 | GPIO53 | RW | GPIO53 interrupt. |
| 20 | GPIO52 | RW | GPIO52 interrupt. |
| 19 | GPIO51 | RW | GPIO51 interrupt. |
| 18 | GPIO50 | RW | GPIO50 interrupt. |
| 17 | GPIO49 | RW | GPIO49 interrupt. |
| 16 | GPIO48 | RW | GPIO48 interrupt. |
| 15 | GPIO47 | RW | GPIO47 interrupt. |
| 14 | GPIO46 | RW | GPIO46 interrupt. |
| 13 | GPIO45 | RW | GPIO45 interrupt. |
| 12 | GPIO44 | RW | GPIO44 interrupt. |
| 11 | GPIO43 | RW | GPIO43 interrupt. |
| 10 | GPIO42 | RW | GPIO42 interrupt. |
| 9 | GPIO41 | RW | GPIO41 interrupt. |
| 8 | GPIO40 | RW | GPIO40 interrupt. |
| 7 | GPIO39 | RW | GPIO39 interrupt. |
| 6 | GPIO38 | RW | GPIO38 interrupt. |
| 5 | GPIO37 | RW | GPIO37 interrupt. |
| 4 | GPIO36 | RW | GPIO36 interrupt. |
| 3 | GPIO35 | RW | GPIO35 interrupt. |
| 2 | GPIO34 | RW | GPIO34 interrupt. |
| 1 | GPIO33 | RW | GPIO33 interrupt. |
| 0 | GPIO32 | RW | GPIO32 interrupt. |
| Instance 0 Address: | 0x4001022C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO63
0x0 |
GPIO62
0x0 |
GPIO61
0x0 |
GPIO60
0x0 |
GPIO59
0x0 |
GPIO58
0x0 |
GPIO57
0x0 |
GPIO56
0x0 |
GPIO55
0x0 |
GPIO54
0x0 |
GPIO53
0x0 |
GPIO52
0x0 |
GPIO51
0x0 |
GPIO50
0x0 |
GPIO49
0x0 |
GPIO48
0x0 |
GPIO47
0x0 |
GPIO46
0x0 |
GPIO45
0x0 |
GPIO44
0x0 |
GPIO43
0x0 |
GPIO42
0x0 |
GPIO41
0x0 |
GPIO40
0x0 |
GPIO39
0x0 |
GPIO38
0x0 |
GPIO37
0x0 |
GPIO36
0x0 |
GPIO35
0x0 |
GPIO34
0x0 |
GPIO33
0x0 |
GPIO32
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO63 | RW | GPIO63 interrupt. |
| 30 | GPIO62 | RW | GPIO62 interrupt. |
| 29 | GPIO61 | RW | GPIO61 interrupt. |
| 28 | GPIO60 | RW | GPIO60 interrupt. |
| 27 | GPIO59 | RW | GPIO59 interrupt. |
| 26 | GPIO58 | RW | GPIO58 interrupt. |
| 25 | GPIO57 | RW | GPIO57 interrupt. |
| 24 | GPIO56 | RW | GPIO56 interrupt. |
| 23 | GPIO55 | RW | GPIO55 interrupt. |
| 22 | GPIO54 | RW | GPIO54 interrupt. |
| 21 | GPIO53 | RW | GPIO53 interrupt. |
| 20 | GPIO52 | RW | GPIO52 interrupt. |
| 19 | GPIO51 | RW | GPIO51 interrupt. |
| 18 | GPIO50 | RW | GPIO50 interrupt. |
| 17 | GPIO49 | RW | GPIO49 interrupt. |
| 16 | GPIO48 | RW | GPIO48 interrupt. |
| 15 | GPIO47 | RW | GPIO47 interrupt. |
| 14 | GPIO46 | RW | GPIO46 interrupt. |
| 13 | GPIO45 | RW | GPIO45 interrupt. |
| 12 | GPIO44 | RW | GPIO44 interrupt. |
| 11 | GPIO43 | RW | GPIO43 interrupt. |
| 10 | GPIO42 | RW | GPIO42 interrupt. |
| 9 | GPIO41 | RW | GPIO41 interrupt. |
| 8 | GPIO40 | RW | GPIO40 interrupt. |
| 7 | GPIO39 | RW | GPIO39 interrupt. |
| 6 | GPIO38 | RW | GPIO38 interrupt. |
| 5 | GPIO37 | RW | GPIO37 interrupt. |
| 4 | GPIO36 | RW | GPIO36 interrupt. |
| 3 | GPIO35 | RW | GPIO35 interrupt. |
| 2 | GPIO34 | RW | GPIO34 interrupt. |
| 1 | GPIO33 | RW | GPIO33 interrupt. |
| 0 | GPIO32 | RW | GPIO32 interrupt. |
| Instance 0 Address: | 0x40010240 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
GPIO73
0x0 |
GPIO72
0x0 |
GPIO71
0x0 |
GPIO70
0x0 |
GPIO69
0x0 |
GPIO68
0x0 |
GPIO67
0x0 |
GPIO66
0x0 |
GPIO65
0x0 |
GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED |
| 9 | GPIO73 | RW | GPIO73 interrupt. |
| 8 | GPIO72 | RW | GPIO72 interrupt. |
| 7 | GPIO71 | RW | GPIO71 interrupt. |
| 6 | GPIO70 | RW | GPIO70 interrupt. |
| 5 | GPIO69 | RW | GPIO69 interrupt. |
| 4 | GPIO68 | RW | GPIO68 interrupt. |
| 3 | GPIO67 | RW | GPIO67 interrupt. |
| 2 | GPIO66 | RW | GPIO66 interrupt. |
| 1 | GPIO65 | RW | GPIO65 interrupt. |
| 0 | GPIO64 | RW | GPIO64 interrupt. |
| Instance 0 Address: | 0x40010244 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
GPIO73
0x0 |
GPIO72
0x0 |
GPIO71
0x0 |
GPIO70
0x0 |
GPIO69
0x0 |
GPIO68
0x0 |
GPIO67
0x0 |
GPIO66
0x0 |
GPIO65
0x0 |
GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED |
| 9 | GPIO73 | RW | GPIO73 interrupt. |
| 8 | GPIO72 | RW | GPIO72 interrupt. |
| 7 | GPIO71 | RW | GPIO71 interrupt. |
| 6 | GPIO70 | RW | GPIO70 interrupt. |
| 5 | GPIO69 | RW | GPIO69 interrupt. |
| 4 | GPIO68 | RW | GPIO68 interrupt. |
| 3 | GPIO67 | RW | GPIO67 interrupt. |
| 2 | GPIO66 | RW | GPIO66 interrupt. |
| 1 | GPIO65 | RW | GPIO65 interrupt. |
| 0 | GPIO64 | RW | GPIO64 interrupt. |
| Instance 0 Address: | 0x40010248 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
GPIO73
0x0 |
GPIO72
0x0 |
GPIO71
0x0 |
GPIO70
0x0 |
GPIO69
0x0 |
GPIO68
0x0 |
GPIO67
0x0 |
GPIO66
0x0 |
GPIO65
0x0 |
GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED |
| 9 | GPIO73 | RW | GPIO73 interrupt. |
| 8 | GPIO72 | RW | GPIO72 interrupt. |
| 7 | GPIO71 | RW | GPIO71 interrupt. |
| 6 | GPIO70 | RW | GPIO70 interrupt. |
| 5 | GPIO69 | RW | GPIO69 interrupt. |
| 4 | GPIO68 | RW | GPIO68 interrupt. |
| 3 | GPIO67 | RW | GPIO67 interrupt. |
| 2 | GPIO66 | RW | GPIO66 interrupt. |
| 1 | GPIO65 | RW | GPIO65 interrupt. |
| 0 | GPIO64 | RW | GPIO64 interrupt. |
| Instance 0 Address: | 0x4001024C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
GPIO73
0x0 |
GPIO72
0x0 |
GPIO71
0x0 |
GPIO70
0x0 |
GPIO69
0x0 |
GPIO68
0x0 |
GPIO67
0x0 |
GPIO66
0x0 |
GPIO65
0x0 |
GPIO64
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED |
| 9 | GPIO73 | RW | GPIO73 interrupt. |
| 8 | GPIO72 | RW | GPIO72 interrupt. |
| 7 | GPIO71 | RW | GPIO71 interrupt. |
| 6 | GPIO70 | RW | GPIO70 interrupt. |
| 5 | GPIO69 | RW | GPIO69 interrupt. |
| 4 | GPIO68 | RW | GPIO68 interrupt. |
| 3 | GPIO67 | RW | GPIO67 interrupt. |
| 2 | GPIO66 | RW | GPIO66 interrupt. |
| 1 | GPIO65 | RW | GPIO65 interrupt. |
| 0 | GPIO64 | RW | GPIO64 interrupt. |
| Instance 0 Address: | 0x40010250 |
Debug control for test purposes only
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
GCLK5
0x0 |
GCLK4
0x0 |
GCLK3
0x0 |
GCLK2
0x0 |
GCLK1
0x0 |
GCLK0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:6 | RSVD | RO | RESERVED |
| 5 | GCLK5 | RW | Gate IOM5 CLK in SPI mode, allowing external input clock |
| 4 | GCLK4 | RW | Gate IOM4 CLK in SPI mode, allowing external input clock |
| 3 | GCLK3 | RW | Gate IOM3 CLK in SPI mode, allowing external input clock |
| 2 | GCLK2 | RW | Gate IOM2 CLK in SPI mode, allowing external input clock |
| 1 | GCLK1 | RW | Gate IOM1 CLK in SPI mode, allowing external input clock |
| 0 | GCLK0 | RW | Gate IOM0 CLK in SPI mode, allowing external input clock |