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Apollo Register Documentation v2.4.2
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| Instance 0 Address: | 0x50004000 |
| Instance 1 Address: | 0x50005000 |
| Instance 2 Address: | 0x50006000 |
| Instance 3 Address: | 0x50007000 |
| Instance 4 Address: | 0x50008000 |
| Instance 5 Address: | 0x50009000 |
Provides direct random access to both input and output fifos. The state of the FIFO is not distured by reading these locations (ie no POP will be done). FIFO0 is accessible from addresses 0x0 - 0x1C, and is used for data outuput from the IOM to external devices. These FIFO locations can be read and written directly. FIFO locations 0x20 - 0x3C provide read only access to the input fifo. These FIFO locations cannot be directly written by the MCU, and are updated only by the internal hardware. Writes to the FIFO0 will take effect immediately. The currently FIFO pointers in register FIFOLOC indicate the current offset into each FIFO0 for the read and write operations. Access to the FIFOs can only be done in word increments; Byte access and writes are not supported. For push and pop style access to FIFO0 can be done using the FIFOPOP and FIFOPUSH registers below.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| FIFO
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | FIFO | RW | FIFO direct access. Only locations 0 - 3F will return valid information. |
| Instance 0 Address: | 0x50004100 |
| Instance 1 Address: | 0x50005100 |
| Instance 2 Address: | 0x50006100 |
| Instance 3 Address: | 0x50007100 |
| Instance 4 Address: | 0x50008100 |
| Instance 5 Address: | 0x50009100 |
Provides the current valid byte count of data within the FIFO as seen from the internal state machines. FIFO0 is dedicated to outgoing transactions and FIFO1 is dedicated to incoming transactions. All counts are specified in units of bytes.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FIFO1REM
0x0 |
FIFO1SIZ
0x0 |
FIFO0REM
0x0 |
FIFO0SIZ
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:24 | FIFO1REM | RO | The number of remaining data bytes slots currently in FIFO 1 (written by interface, read by MCU) |
| 23:16 | FIFO1SIZ | RO | The number of valid data bytes currently in FIFO 1 (written by interface, read by MCU) |
| 15:8 | FIFO0REM | RO | The number of remaining data bytes slots currently in FIFO 0 (written by MCU, read by interface) |
| 7:0 | FIFO0SIZ | RO | The number of valid data bytes currently in the FIFO 0 (written by MCU, read by interface) |
| Instance 0 Address: | 0x50004104 |
| Instance 1 Address: | 0x50005104 |
| Instance 2 Address: | 0x50006104 |
| Instance 3 Address: | 0x50007104 |
| Instance 4 Address: | 0x50008104 |
| Instance 5 Address: | 0x50009104 |
Sets the threshold values for incoming and outgoing transactions. The threshold values are used to assert the interrupt if enabled, and also used during DMA to set the transfer size as a result of DMATHR trigger. The WTHR is used to indicate when there are more than WTHR bytes of open fifo locations available in the outgoing FIFO (FIFO0). The intended use to invoke an interrupt or DMA transfer that will refill the FIFO with a byte count up to this value. The RTHR is used to indicate when there are more than RTHR bytes in the incoming FIFO (FIFO1) and a data transfer of this size can be supported, either through direct POP of the FIFO, or through DMA. The value of both RTHR and WTHR are also used to set the data transfer size of DMA operations if DMATHR trigger is enabled.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
FIFOWTHR
0x0 |
RSVD
0x0 |
FIFORTHR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:14 | RSVD | RO | RESERVED |
| 13:8 | FIFOWTHR | RW | FIFO write threshold in bytes. A value of 0 will disable the write FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the write fifo contains FIFOWTHR free bytes, as indicated by the FIFO0REM field. This is intended to signal when a transfer of FIFOWTHR bytes can be done from the host to the IOM write fifo to support large IOM write operations. |
| 7:6 | RSVD | RO | RESERVED |
| 5:0 | FIFORTHR | RW | FIFO read threshold in bytes. A value of 0 will disable the read FIFO level from activating the threshold interrupt. If this field is non-zero, it will trigger a threshold interrupt when the read fifo contains FIFORTHR valid bytes of data, as indicated by the FIFO1SIZ field. This is intended to signal when a data transfer of FIFORTHR bytes can be done from the IOM module to the host via the read fifo to support large IOM read operations. |
| Instance 0 Address: | 0x50004108 |
| Instance 1 Address: | 0x50005108 |
| Instance 2 Address: | 0x50006108 |
| Instance 3 Address: | 0x50007108 |
| Instance 4 Address: | 0x50008108 |
| Instance 5 Address: | 0x50009108 |
Will advance the internal read pointer of the incoming FIFO (FIFO1) when read, if POPWR is not active. If POPWR is active, a write to this register is needed to advance the internal FIFO pointer.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FIFODOUT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | FIFODOUT | RW | This register will return the read data indicated by the current read pointer on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the fifo read pointer will be advanced by one word as a result of the read.
If the POPWR bit is set (1), the fifo read pointer will only be advanced after a write operation to this register. The write data is ignored for this register.
If less than a even word multiple is available, and the command is completed, the module will return the word containing these bytes and undetermined data in the unused fields of the word. |
| Instance 0 Address: | 0x5000410C |
| Instance 1 Address: | 0x5000510C |
| Instance 2 Address: | 0x5000610C |
| Instance 3 Address: | 0x5000710C |
| Instance 4 Address: | 0x5000810C |
| Instance 5 Address: | 0x5000910C |
Will write new data into the outgoing FIFO and advance the internal write pointer.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FIFODIN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | FIFODIN | RW | This register is used to write the FIFORAM in FIFO mode and will cause a push event to occur to the next open slot within the FIFORAM. Writing to this register will cause the write point to increment by 1 word(4 bytes). |
| Instance 0 Address: | 0x50004110 |
| Instance 1 Address: | 0x50005110 |
| Instance 2 Address: | 0x50006110 |
| Instance 3 Address: | 0x50007110 |
| Instance 4 Address: | 0x50008110 |
| Instance 5 Address: | 0x50009110 |
Provides controls for the operation of the internal FIFOs. Contains fields used to control the operation of the POP register, and also controls to reset the internal pointers of the FIFOs.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
FIFORSTN
0x1 |
POPWR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:2 | RSVD | RO | RESERVED |
| 1 | FIFORSTN | RW | Active low manual reset of the fifo. Write to 0 to reset fifo, and then write to 1 to remove the reset. |
| 0 | POPWR | RW | Selects the mode in which 'pop' events are done for the fifo read operations. A value of '1' will prevent a pop event on a read operation, and will require a write to the FIFOPOP register to create a pop event.
A value of '0' in this register will allow a pop event to occur on the read of the FIFOPOP register, and may cause inadvertant fifo pops when used in a debugging mode. |
| Instance 0 Address: | 0x50004114 |
| Instance 1 Address: | 0x50005114 |
| Instance 2 Address: | 0x50006114 |
| Instance 3 Address: | 0x50007114 |
| Instance 4 Address: | 0x50008114 |
| Instance 5 Address: | 0x50009114 |
Provides a read only value of the current read and write pointers. This register is read only and can be used alogn with the FIFO direct access method to determine the next data to be used for input and output functions.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
FIFORPTR
0x0 |
RSVD
0x0 |
FIFOWPTR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:12 | RSVD | RO | Reserved |
| 11:8 | FIFORPTR | RW | Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1), which is used to store read data returned from external devices during a read operation. |
| 7:4 | RSVD | RO | Reserved |
| 3:0 | FIFOWPTR | RW | Current FIFO write pointer. Value is the index into the outgoing FIFO (FIFO0), which is used during write operations to external devices. |
| Instance 0 Address: | 0x50004200 |
| Instance 1 Address: | 0x50005200 |
| Instance 2 Address: | 0x50006200 |
| Instance 3 Address: | 0x50007200 |
| Instance 4 Address: | 0x50008200 |
| Instance 5 Address: | 0x50009200 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CQERR
0x0 |
CQUPD
0x0 |
CQPAUSED
0x0 |
DERR
0x0 |
DCMP
0x0 |
ARB
0x0 |
STOP
0x0 |
START
0x0 |
ICMD
0x0 |
IACC
0x0 |
NAK
0x0 |
FOVFL
0x0 |
FUNDFL
0x0 |
THR
0x0 |
CMDCMP
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:15 | RSVD | RO | RESERVED |
| 14 | CQERR | RW | Error during command queue operations |
| 13 | CQUPD | RW | CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. |
| 12 | CQPAUSED | RO | Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. |
| 11 | DERR | RW | DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. |
| 10 | DCMP | RW | DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state |
| 9 | ARB | RW | Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. |
| 8 | STOP | RW | STOP command interrupt. Asserted when another master on the bus has signaled a STOP command. |
| 7 | START | RW | START command interrupt. Asserted when another master on the bus has signaled a START command. |
| 6 | ICMD | RW | illegal command interrupt. Asserted when a command is written when an active command is in progress. |
| 5 | IACC | RW | illegal FIFO access interrupt. Asserted when there is a overflow or underflow event |
| 4 | NAK | RW | I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus. |
| 3 | FOVFL | RW | Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. |
| 2 | FUNDFL | RW | Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo. |
| 1 | THR | RW | FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field.
For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. |
| 0 | CMDCMP | RW | Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. |
| Instance 0 Address: | 0x50004204 |
| Instance 1 Address: | 0x50005204 |
| Instance 2 Address: | 0x50006204 |
| Instance 3 Address: | 0x50007204 |
| Instance 4 Address: | 0x50008204 |
| Instance 5 Address: | 0x50009204 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CQERR
0x0 |
CQUPD
0x0 |
CQPAUSED
0x0 |
DERR
0x0 |
DCMP
0x0 |
ARB
0x0 |
STOP
0x0 |
START
0x0 |
ICMD
0x0 |
IACC
0x0 |
NAK
0x0 |
FOVFL
0x0 |
FUNDFL
0x0 |
THR
0x0 |
CMDCMP
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:15 | RSVD | RO | RESERVED |
| 14 | CQERR | RW | Error during command queue operations |
| 13 | CQUPD | RW | CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. |
| 12 | CQPAUSED | RO | Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. |
| 11 | DERR | RW | DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. |
| 10 | DCMP | RW | DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state |
| 9 | ARB | RW | Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. |
| 8 | STOP | RW | STOP command interrupt. Asserted when another master on the bus has signaled a STOP command. |
| 7 | START | RW | START command interrupt. Asserted when another master on the bus has signaled a START command. |
| 6 | ICMD | RW | illegal command interrupt. Asserted when a command is written when an active command is in progress. |
| 5 | IACC | RW | illegal FIFO access interrupt. Asserted when there is a overflow or underflow event |
| 4 | NAK | RW | I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus. |
| 3 | FOVFL | RW | Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. |
| 2 | FUNDFL | RW | Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo. |
| 1 | THR | RW | FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field.
For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. |
| 0 | CMDCMP | RW | Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. |
| Instance 0 Address: | 0x50004208 |
| Instance 1 Address: | 0x50005208 |
| Instance 2 Address: | 0x50006208 |
| Instance 3 Address: | 0x50007208 |
| Instance 4 Address: | 0x50008208 |
| Instance 5 Address: | 0x50009208 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CQERR
0x0 |
CQUPD
0x0 |
CQPAUSED
0x0 |
DERR
0x0 |
DCMP
0x0 |
ARB
0x0 |
STOP
0x0 |
START
0x0 |
ICMD
0x0 |
IACC
0x0 |
NAK
0x0 |
FOVFL
0x0 |
FUNDFL
0x0 |
THR
0x0 |
CMDCMP
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:15 | RSVD | RO | RESERVED |
| 14 | CQERR | RW | Error during command queue operations |
| 13 | CQUPD | RW | CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. |
| 12 | CQPAUSED | RO | Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. |
| 11 | DERR | RW | DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. |
| 10 | DCMP | RW | DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state |
| 9 | ARB | RW | Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. |
| 8 | STOP | RW | STOP command interrupt. Asserted when another master on the bus has signaled a STOP command. |
| 7 | START | RW | START command interrupt. Asserted when another master on the bus has signaled a START command. |
| 6 | ICMD | RW | illegal command interrupt. Asserted when a command is written when an active command is in progress. |
| 5 | IACC | RW | illegal FIFO access interrupt. Asserted when there is a overflow or underflow event |
| 4 | NAK | RW | I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus. |
| 3 | FOVFL | RW | Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. |
| 2 | FUNDFL | RW | Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo. |
| 1 | THR | RW | FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field.
For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. |
| 0 | CMDCMP | RW | Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. |
| Instance 0 Address: | 0x5000420C |
| Instance 1 Address: | 0x5000520C |
| Instance 2 Address: | 0x5000620C |
| Instance 3 Address: | 0x5000720C |
| Instance 4 Address: | 0x5000820C |
| Instance 5 Address: | 0x5000920C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CQERR
0x0 |
CQUPD
0x0 |
CQPAUSED
0x0 |
DERR
0x0 |
DCMP
0x0 |
ARB
0x0 |
STOP
0x0 |
START
0x0 |
ICMD
0x0 |
IACC
0x0 |
NAK
0x0 |
FOVFL
0x0 |
FUNDFL
0x0 |
THR
0x0 |
CMDCMP
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:15 | RSVD | RO | RESERVED |
| 14 | CQERR | RW | Error during command queue operations |
| 13 | CQUPD | RW | CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation. |
| 12 | CQPAUSED | RO | Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs. |
| 11 | DERR | RW | DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified. |
| 10 | DCMP | RW | DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state |
| 9 | ARB | RW | Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus. |
| 8 | STOP | RW | STOP command interrupt. Asserted when another master on the bus has signaled a STOP command. |
| 7 | START | RW | START command interrupt. Asserted when another master on the bus has signaled a START command. |
| 6 | ICMD | RW | illegal command interrupt. Asserted when a command is written when an active command is in progress. |
| 5 | IACC | RW | illegal FIFO access interrupt. Asserted when there is a overflow or underflow event |
| 4 | NAK | RW | I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus. |
| 3 | FOVFL | RW | Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop. |
| 2 | FUNDFL | RW | Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo. |
| 1 | THR | RW | FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field.
For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field. |
| 0 | CMDCMP | RW | Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed. |
| Instance 0 Address: | 0x50004210 |
| Instance 1 Address: | 0x50005210 |
| Instance 2 Address: | 0x50006210 |
| Instance 3 Address: | 0x50007210 |
| Instance 4 Address: | 0x50008210 |
| Instance 5 Address: | 0x50009210 |
Provides clock related controls used internal to the BLEIF module, and enablement of 32KHz clock to the BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3 using the DIV3 control. This register is also used to enable the clock, which must be done prior to performing any IO transactions.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| TOTPER
0x0 |
LOWPER
0x0 |
RSVD
0x0 |
DIVEN
0x0 |
DIV3
0x0 |
FSEL
0x0 |
RSVD
0x0 |
IOCLKEN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:24 | TOTPER | RW | Clock total clock count minus 1. This provides the total period of the divided clock -1 when the DIVEN is active. The
source clock is selected by FSEL. Only applicable when DIVEN = 1. |
| 23:16 | LOWPER | RW | Clock low clock count minus 1. This provides the number of clocks the divided clock will be low when the DIVEN = 1.
Only applicable when DIVEN = 1. |
| 15:13 | RSVD | RO | RESERVED |
| 12 | DIVEN | RW | Enable clock division by TOTPER and LOWPER DIS = 0x0 - Disable TOTPER division. EN = 0x1 - Enable TOTPER division. |
| 11 | DIV3 | RW | Enable divide by 3 of the source IOCLK. Division by 3 is done before the DIVEN programmable divider, and if enabled
will provide the divided by 3 clock as the source to the programmable divider. DIS = 0x0 - Select divide by 1. EN = 0x1 - Select divide by 3. |
| 10:8 | FSEL | RW | Select the input clock frequency. MIN_PWR = 0x0 - Selects the minimum power clock. This setting should be used whenever the IOM is not active. HFRC = 0x1 - Selects the HFRC as the input clock. HFRC_DIV2 = 0x2 - Selects the HFRC / 2 as the input clock. HFRC_DIV4 = 0x3 - Selects the HFRC / 4 as the input clock. HFRC_DIV8 = 0x4 - Selects the HFRC / 8 as the input clock. HFRC_DIV16 = 0x5 - Selects the HFRC / 16 as the input clock. HFRC_DIV32 = 0x6 - Selects the HFRC / 32 as the input clock. HFRC_DIV64 = 0x7 - Selects the HFRC / 64 as the input clock. |
| 7:1 | RSVD | RO | RESERVED |
| 0 | IOCLKEN | RW | Enable for the interface clock. Must be enabled prior to executing any IO operations. |
| Instance 0 Address: | 0x50004214 |
| Instance 1 Address: | 0x50005214 |
| Instance 2 Address: | 0x50006214 |
| Instance 3 Address: | 0x50007214 |
| Instance 4 Address: | 0x50008214 |
| Instance 5 Address: | 0x50009214 |
Provides enable for each submodule. Only a sigle submodule can be enabled at one time.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSRVD
0x0 |
SMOD1TYPE
0x1 |
SMOD1EN
0x0 |
SMOD0TYPE
0x0 |
SMOD0EN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:8 | RSRVD | RO | Reserved |
| 7:5 | SMOD1TYPE | RO | Submodule 0 module type. This is the I2C Master interface MSPI = 0x0 - SPI Master submodule I2C_MASTER = 0x1 - MI2C submodule SSPI = 0x2 - SPI Slave submodule SI2C = 0x3 - I2C Slave submodule NA = 0x7 - NOT INSTALLED |
| 4 | SMOD1EN | RW | Submodule 1 enable (1) or disable (0) |
| 3:1 | SMOD0TYPE | RO | Submodule 0 module type. This is the SPI Master interface. SPI_MASTER = 0x0 - MSPI submodule I2C_MASTER = 0x1 - I2C Master submodule SSPI = 0x2 - SPI Slave submodule SI2C = 0x3 - I2C Slave submodule NA = 0x7 - NOT INSTALLED |
| 0 | SMOD0EN | RW | Submodule 0 enable (1) or disable (0) |
| Instance 0 Address: | 0x50004218 |
| Instance 1 Address: | 0x50005218 |
| Instance 2 Address: | 0x50006218 |
| Instance 3 Address: | 0x50007218 |
| Instance 4 Address: | 0x50008218 |
| Instance 5 Address: | 0x50009218 |
Writes to this register will start an IO transaction, as well as set various parameters for the command itself. Reads will return the command value written to the CMD register. To read the number of bytes that have yet to be transferred, refer to the CTSIZE field within the CMDSTAT register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| OFFSETLO
0x0 |
RSRVD22
0x0 |
CMDSEL
0x0 |
TSIZE
0x0 |
CONT
0x0 |
OFFSETCNT
0x0 |
CMD
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:24 | OFFSETLO | RW | This register holds the low order byte of offset to be used in the transaction. The number of offset bytes to use is set with bits 1:0 of the command. |
| 23:22 | RSRVD22 | RO | Reserved |
| 21:20 | CMDSEL | RW | Command Specific selection information. Not used in Master I2C. Used as CEn select for Master SPI transactions |
| 19:8 | TSIZE | RW | Defines the transaction size in bytes. The offset transfer is not included in this size. |
| 7 | CONT | RW | Contine to hold the bus after the current transaction if set to a 1 with a new command issued. |
| 6:5 | OFFSETCNT | RW | Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selections. The second (byte 1) and third byte (byte 2) are read from the OFFSETHI register, and the low order byte is pulled from this register in the OFFSETLO field.
Offset bytes are transmitted highest byte first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted first, then OFFSETHI[7:0] then OFFSETLO.
If offsetcnt == 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.
If offsetcnt == 1, only OFFSETLO will be transmitted.
Offset bytes are always transmitted MSB first, regardless of the value of the LSB control bit within the module configuration. |
| 4:0 | CMD | RW | Command for submodule. WRITE = 0x1 - Write command using count of offset bytes specified in the OFFSETCNT field READ = 0x2 - Read command using count of offset bytes specified in the OFFSETCNT field TMW = 0x3 - SPI only. Test mode to do constant write operations. Useful for debug and power measurements. Will continually send data in OFFSET field TMR = 0x4 - SPI Only. Test mode to do constant read operations. Useful for debug and power measurements. Will continually read data from external input |
| Instance 0 Address: | 0x5000421C |
| Instance 1 Address: | 0x5000521C |
| Instance 2 Address: | 0x5000621C |
| Instance 3 Address: | 0x5000721C |
| Instance 4 Address: | 0x5000821C |
| Instance 5 Address: | 0x5000921C |
Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For Revision A, this register MUST NOT be programmed!
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DCXEN
0x0 |
CE3OUT
0x0 |
CE2OUT
0x0 |
CE1OUT
0x0 |
CE0OUT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:5 | RSVD | RO | RESERVED |
| 4 | DCXEN | RW | Revision A: MUST NOT be programmed! Revision B: Bit 4: DCX Signaling Enable via other CE signals. The selected DCX signal (unused CE pin) will be driven low during write of offset byte, and high during transmission of data bytes. EN = 0x1 - Enable DCX. DIS = 0x0 - Disable DCX. |
| 3 | CE3OUT | RW | Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE3 output. |
| 2 | CE2OUT | RW | Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE2 output. |
| 1 | CE1OUT | RW | Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE1 output. |
| 0 | CE0OUT | RW | Revision A: MUST NOT be programmed! Revision B: Enable DCX output for CE0 output. |
| Instance 0 Address: | 0x50004220 |
| Instance 1 Address: | 0x50005220 |
| Instance 2 Address: | 0x50006220 |
| Instance 3 Address: | 0x50007220 |
| Instance 4 Address: | 0x50008220 |
| Instance 5 Address: | 0x50009220 |
High order 2 bytes of 3 byte offset for IO transaction
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
OFFSETHI
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | RSVD | RO | Reserved |
| 15:0 | OFFSETHI | RW | Holds the high order 2 bytes of the 3 byte addressing/offset field to use with IO commands. The number of offset bytes to use is specified in the command register |
| Instance 0 Address: | 0x50004224 |
| Instance 1 Address: | 0x50005224 |
| Instance 2 Address: | 0x50006224 |
| Instance 3 Address: | 0x50007224 |
| Instance 4 Address: | 0x50008224 |
| Instance 5 Address: | 0x50009224 |
Provides staus on the execution of the command currently in progress. The fields in this register will reflect the real time status of the internal state machines and data transfers within the IOM. These are read only fields and writes to the registers are ignored.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSRVD0
0x0 |
CTSIZE
0x0 |
CMDSTAT
0x0 |
CCMD
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:20 | RSRVD0 | RO | Reserved |
| 19:8 | CTSIZE | RO | The current number of bytes still to be transferred with this command. This field will count down to zero. |
| 7:5 | CMDSTAT | RO | The current status of the command execution. ERR = 0x1 - Error encountered with command ACTIVE = 0x2 - Actively processing command IDLE = 0x4 - Idle state, no active command, no error WAIT = 0x6 - Command in progress, but waiting on data from host |
| 4:0 | CCMD | RO | current command that is being executed |
| Instance 0 Address: | 0x50004240 |
| Instance 1 Address: | 0x50005240 |
| Instance 2 Address: | 0x50006240 |
| Instance 3 Address: | 0x50007240 |
| Instance 4 Address: | 0x50008240 |
| Instance 5 Address: | 0x50009240 |
Provides control on which event will trigger the DMA transfer after the DMA operation is setup and enabled. The trigger event will cause a number of bytes (depending on trigger event) to be transferred via the DMA operation, and can be used to adjust the latency of data to/from the IOM module to/from the dma target. DMA transfers are broken into smaller transfers internally of up to 16 bytes each, and multiple trigger events can be used to complete the entire programmed DMA transfer.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DTHREN
0x0 |
DCMDCMPEN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:2 | RSVD | RO | RESERVED. |
| 1 | DTHREN | RW | Trigger DMA upon THR level reached. For M2P DMA operations (IOM writes), the trigger will assert when the write FIFO has (WTHR/4) number of words free in the write FIFO, and will transfer (WTHR/4) number of words
or, if the number of words left to transfer is less than the WTHR value, will transfer the remaining byte count.
For P2M DMA operations, the trigger will assert when the read FIFO has (RTHR/4) words available in the read FIFO, and will transfer (RTHR/4) words to SRAM. This trigger will NOT assert when the transaction
completes and there are less than RTHR bytes left in the fifo, since the RTHR has not been reached. In this case, the CMDCMP trigger must also be enabled to transfer the remaining read FIFO data to SRAM. |
| 0 | DCMDCMPEN | RW | Trigger DMA upon command complete. Enables the trigger of the DMA when a command is completed. When this event is triggered, the number of words transferred will be the lesser of the remaining TOTCOUNT bytes, or |
| Instance 0 Address: | 0x50004244 |
| Instance 1 Address: | 0x50005244 |
| Instance 2 Address: | 0x50006244 |
| Instance 3 Address: | 0x50007244 |
| Instance 4 Address: | 0x50008244 |
| Instance 5 Address: | 0x50009244 |
Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only and some can be reset via a write of 0.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DTOTCMP
0x0 |
DTHR
0x0 |
DCMDCMP
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:3 | RSVD | RO | RESERVED. |
| 2 | DTOTCMP | RO | DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO was enough to complete the DMA operation (greater than or equal to current TOTCOUNT) when the command completed. This trigger is default active when the DCMDCMP trigger is
disabled and there is enough data in the FIFO to complete the DMA operation. |
| 1 | DTHR | RO | Triggered DMA from THR event. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA. |
| 0 | DCMDCMP | RO | Triggered DMA from Command complete event. Bit is read only and can be cleared by disabling the DCMDCMP trigger enable or by disabling DMA. |
| Instance 0 Address: | 0x50004280 |
| Instance 1 Address: | 0x50005280 |
| Instance 2 Address: | 0x50006280 |
| Instance 3 Address: | 0x50007280 |
| Instance 4 Address: | 0x50008280 |
| Instance 5 Address: | 0x50009280 |
Configuration control of the DMA process, including the direction of DMA, and enablement of DMA
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DPWROFF
0x0 |
DMAPRI
0x0 |
RSVD
0x0 |
DMADIR
0x0 |
DMAEN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED. |
| 9 | DPWROFF | RW | Power off module after DMA is complete. If this bit is active, the module will request to power off the supply it is attached to. If there are other units still requiring power from the same domain, power down will not be performed. DIS = 0x0 - Power off disabled EN = 0x1 - Power off enabled |
| 8 | DMAPRI | RW | Sets the Priority of the DMA request LOW = 0x0 - Low Priority (service as best effort) HIGH = 0x1 - High Priority (service immediately) |
| 7:2 | RSVD | RO | RESERVED. |
| 1 | DMADIR | RW | Direction P2M = 0x0 - Peripheral to Memory (SRAM) transaction. To be set when doing IOM read operations, ie reading data from external devices. M2P = 0x1 - Memory to Peripheral transaction. To be set when doing IOM write operations, ie writing data to external devices. |
| 0 | DMAEN | RW | DMA Enable. Setting this bit to EN will start the DMA operation. This should be the last DMA related register set prior to issuing the command DIS = 0x0 - Disable DMA Function EN = 0x1 - Enable DMA Function |
| Instance 0 Address: | 0x50004288 |
| Instance 1 Address: | 0x50005288 |
| Instance 2 Address: | 0x50006288 |
| Instance 3 Address: | 0x50007288 |
| Instance 4 Address: | 0x50008288 |
| Instance 5 Address: | 0x50009288 |
Contains the number of bytes to be transferred for this DMA transaction. This register is decremented as the data is transferred, and will be 0 at the completion of the DMA operation.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSRVDD
0x0 |
TOTCOUNT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:12 | RSRVDD | RO | Reserved |
| 11:0 | TOTCOUNT | RW | Triggered DMA from Command complete event occured. Bit is read only and can be cleared by disabling the DTHR trigger enable or by disabling DMA. |
| Instance 0 Address: | 0x5000428C |
| Instance 1 Address: | 0x5000528C |
| Instance 2 Address: | 0x5000628C |
| Instance 3 Address: | 0x5000728C |
| Instance 4 Address: | 0x5000828C |
| Instance 5 Address: | 0x5000928C |
The source or destination address internal the SRAM for the DMA data. For write operations, this can only be SRAM data (ADDR bit 28 = 1); For read operations, this can ve either SRAM or FLASH (ADDR bit 28 = 0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
TARGADDR28
0x0 |
RSVD
0x0 |
TARGADDR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSVD | RO | Reserved |
| 28 | TARGADDR28 | RW | Bit 28 of the target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.
Setting to '1' will select the SRAM. Setting to '0' will select the flash |
| 27:20 | RSVD | RO | Reserved |
| 19:0 | TARGADDR | RW | Bits [19:0] of the target byte address for source of DMA (either read or write). The address can be any byte alignment, and does not have to be word aligned. In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written. |
| Instance 0 Address: | 0x50004290 |
| Instance 1 Address: | 0x50005290 |
| Instance 2 Address: | 0x50006290 |
| Instance 3 Address: | 0x50007290 |
| Instance 4 Address: | 0x50008290 |
| Instance 5 Address: | 0x50009290 |
Status of the DMA operation currently in progress.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DMAERR
0x0 |
DMACPL
0x0 |
DMATIP
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:3 | RSVD | RO | RESERVED. |
| 2 | DMAERR | RW | DMA Error. This active high bit signals an error was encountered during the DMA operation. The bit can be cleared by writing to 0. Once set, this bit will remain set until cleared by software. |
| 1 | DMACPL | RW | DMA Transfer Complete. This signals the end of the DMA operation. This bit can be cleared by writing to 0, and will also be cleared when a new DMA is started. |
| 0 | DMATIP | RO | DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority.
All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done. This bit is read only. |
| Instance 0 Address: | 0x50004294 |
| Instance 1 Address: | 0x50005294 |
| Instance 2 Address: | 0x50006294 |
| Instance 3 Address: | 0x50007294 |
| Instance 4 Address: | 0x50008294 |
| Instance 5 Address: | 0x50009294 |
Controls parameters and options for execution of the command queue operation. To enable command queue, create this in memory, set the address, and enable it with a write to CQEN
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CQPRI
0x0 |
CQEN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:2 | RSVD | RO | RESERVED. |
| 1 | CQPRI | RW | Sets the Priority of the command queue dma request LOW = 0x0 - Low Priority (service as best effort) HIGH = 0x1 - High Priority (service immediately) |
| 0 | CQEN | RW | Command queue enable. When set, will enable the processing of the command queue and fetches of address/data pairs will proceed from the word address within the CQADDR register. Can be disabled
using a CQ executed write to this bit as well. DIS = 0x0 - Disable CQ Function EN = 0x1 - Enable CQ Function |
| Instance 0 Address: | 0x50004298 |
| Instance 1 Address: | 0x50005298 |
| Instance 2 Address: | 0x50006298 |
| Instance 3 Address: | 0x50007298 |
| Instance 4 Address: | 0x50008298 |
| Instance 5 Address: | 0x50009298 |
The SRAM address which will be fetched next execution of the CQ operation. This register is updated as the CQ operation progresses, and is the live version of the register. The register can also be written by the Command Queue operation itself, allowing the relocation of successive CQ fetches. In this case, the new CQ address will be used for the next CQ address/data fetch
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSRVD2
0x0 |
CQADDR28
0x0 |
RSRVD1
0x0 |
CQADDR
0x0 |
RSRVD0
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:29 | RSRVD2 | RO | Reserved |
| 28 | CQADDR28 | RW | Bit 28 of target byte address for source of CQ (read only). Used to denote Flash (0) or SRAM (1) access |
| 27:20 | RSRVD1 | RO | Reserved |
| 19:2 | CQADDR | RW | Bits 19:2 of target byte address for source of CQ (read only). The buffer must be aligned on a word boundary |
| 1:0 | RSRVD0 | RO | Reserved |
| Instance 0 Address: | 0x5000429C |
| Instance 1 Address: | 0x5000529C |
| Instance 2 Address: | 0x5000629C |
| Instance 3 Address: | 0x5000729C |
| Instance 4 Address: | 0x5000829C |
| Instance 5 Address: | 0x5000929C |
Provides the status of the command queue operation. If the command queue is disabled, these bits will be cleared. The bits are read only
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CQERR
0x0 |
CQPAUSED
0x0 |
CQTIP
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:3 | RSVD | RO | RESERVED. |
| 2 | CQERR | RW | Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation. |
| 1 | CQPAUSED | RO | Command queue operation is currently paused. |
| 0 | CQTIP | RO | Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event. |
| Instance 0 Address: | 0x500042A0 |
| Instance 1 Address: | 0x500052A0 |
| Instance 2 Address: | 0x500062A0 |
| Instance 3 Address: | 0x500072A0 |
| Instance 4 Address: | 0x500082A0 |
| Instance 5 Address: | 0x500092A0 |
Command Queue Flag Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CQIRQMASK
0x0 |
CQFLAGS
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | CQIRQMASK | RW | Mask the bits used to generate the command queue interrupt. A '1' in the bit position will enable the pause event to trigger the interrupt, if the CQWT_int interrupt is enabled. Bits definitions are the same as CQPAUSE |
| 15:0 | CQFLAGS | RO | Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status. |
| Instance 0 Address: | 0x500042A4 |
| Instance 1 Address: | 0x500052A4 |
| Instance 2 Address: | 0x500062A4 |
| Instance 3 Address: | 0x500072A4 |
| Instance 4 Address: | 0x500082A4 |
| Instance 5 Address: | 0x500092A4 |
Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields, allowing for setting, clearing or toggling the value in the software flags. Priority when the same bit is enabled in each field is toggle, then set, then clear.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CQFCLR
0x0 |
CQFTGL
0x0 |
CQFSET
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:24 | RSVD | RO | Reserved |
| 23:16 | CQFCLR | WO | Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corresponding bit position of this field |
| 15:8 | CQFTGL | WO | Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in the corresponding bit position of this field |
| 7:0 | CQFSET | WO | Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in the corresponding bit position of this field |
| Instance 0 Address: | 0x500042A8 |
| Instance 1 Address: | 0x500052A8 |
| Instance 2 Address: | 0x500062A8 |
| Instance 3 Address: | 0x500072A8 |
| Instance 4 Address: | 0x500082A8 |
| Instance 5 Address: | 0x500092A8 |
Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the CQFLAG register is '1', CQ processing will halt until either value is changed to '0'.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CQPEN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:16 | RSVD | RO | Reserved |
| 15:0 | CQPEN | RW | Enables the specified event to pause command processing when active IDXEQ = 0x8000 - Pauses the command queue when the current index matches the last index BLEXOREN = 0x4000 - Pause command queue when input BLE bit XORed with SWFLAG4 is '1' IOMXOREN = 0x2000 - Pause command queue when input IOM bit XORed with SWFLAG3 is '1' GPIOXOREN = 0x1000 - Pause command queue when input GPIO irq_bit XORed with SWFLAG2 is '1' MSPI1XNOREN = 0x800 - Pause command queue when input MSPI1 bit XNORed with SWFLAG1 is '1' MSPI0XNOREN = 0x400 - Pause command queue when input MSPI0 bit XNORed with SWFLAG0 is '1' MSPI1XOREN = 0x200 - Pause command queue when input MSPI1 bit XORed with SWFLAG1 is '1' MSPI0XOREN = 0x100 - Pause command queue when input MSPI0 bit XORed with SWFLAG0 is '1' SWFLAGEN7 = 0x80 - Pause the command queue when software flag bit 7 is '1'. SWFLAGEN6 = 0x40 - Pause the command queue when software flag bit 6 is '1' SWFLAGEN5 = 0x20 - Pause the command queue when software flag bit 5 is '1' SWFLAGEN4 = 0x10 - Pause the command queue when software flag bit 4 is '1' SWFLAGEN3 = 0x8 - Pause the command queue when software flag bit 3 is '1' SWFLAGEN2 = 0x4 - Pause the command queue when software flag bit 2 is '1' SWFLAGEN1 = 0x2 - Pause the command queue when software flag bit 1 is '1' SWFLAGEN0 = 0x1 - Pause the command queue when software flag bit 0 is '1' |
| Instance 0 Address: | 0x500042AC |
| Instance 1 Address: | 0x500052AC |
| Instance 2 Address: | 0x500062AC |
| Instance 3 Address: | 0x500072AC |
| Instance 4 Address: | 0x500082AC |
| Instance 5 Address: | 0x500092AC |
Current index value, targeted to be written by register write operations within the command queue. This is compared to the CQENDIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and this current index equals the CQENDIDX register value. This will only pause when the values are equal.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CQCURIDX
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:8 | RSVD | RO | RESERVED |
| 7:0 | CQCURIDX | RW | Holds 8 bits of data that will be compared with the CQENDIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN. |
| Instance 0 Address: | 0x500042B0 |
| Instance 1 Address: | 0x500052B0 |
| Instance 2 Address: | 0x500062B0 |
| Instance 3 Address: | 0x500072B0 |
| Instance 4 Address: | 0x500082B0 |
| Instance 5 Address: | 0x500092B0 |
End index value, targeted to be written by software to indicate the last valid register pair contained within the command queue. rgister write operations within the command queue. This is compared to the CQCURIDX and will stop the CQ operation if bit 15 of the CQPAUSEEN is '1' and this current index equals the CQCURIDX register value. This will only pause when the values are equal.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
CQENDIDX
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:8 | RSVD | RO | RESERVED |
| 7:0 | CQENDIDX | RW | Holds 8 bits of data that will be compared with the CQCURIX register field. If the values match, the IDXEQ pause event will be activated, which will cause the pausing of command quue operation if the IDXEQ bit is enabled in CQPAUSEEN. |
| Instance 0 Address: | 0x500042B4 |
| Instance 1 Address: | 0x500052B4 |
| Instance 2 Address: | 0x500062B4 |
| Instance 3 Address: | 0x500072B4 |
| Instance 4 Address: | 0x500082B4 |
| Instance 5 Address: | 0x500092B4 |
IOM Module Status Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
IDLEST
0x0 |
CMDACT
0x0 |
ERR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:3 | RSVD | RO | RESERVED |
| 2 | IDLEST | RO | indicates if the active I/O state machine is IDLE. Note - The state machine could be in idle state due to holdoffs from data availability, or as the command gets propagated into the logic from the registers. IDLE = 0x1 - The I/O state machine is in the idle state. |
| 1 | CMDACT | RO | Indicates if the active I/O Command is currently processing a transaction, or command is complete, but the FIFO pointers are still syncronizing internally. This bit will go high at
the start of the transaction, and will go low when the command is complete, and the data and pointers within the FIFO have been syncronized. ACTIVE = 0x1 - An I/O command is active. Indicates the active module has an active command and is processing this. De-asserted when the command is completed. |
| 0 | ERR | RO | Bit has been deprecated. Please refer to the other error indicators. This will always return 0. ERROR = 0x1 - Bit has been deprecated and will always return 0. |
| Instance 0 Address: | 0x50004300 |
| Instance 1 Address: | 0x50005300 |
| Instance 2 Address: | 0x50006300 |
| Instance 3 Address: | 0x50007300 |
| Instance 4 Address: | 0x50008300 |
| Instance 5 Address: | 0x50009300 |
Controls the configuration of the SPI master module, including POL/PHA, LSB, flow control, and delays for MISO and MOSI
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
MSPIRST
0x0 |
DOUTDLY
0x0 |
DINDLY
0x0 |
SPILSB
0x0 |
RDFCPOL
0x0 |
WTFCPOL
0x1 |
WTFCIRQ
0x0 |
RSVD
0x0 |
MOSIINV
0x0 |
RDFC
0x0 |
WTFC
0x0 |
RSVD
0x0 |
FULLDUP
0x0 |
SPHA
0x0 |
SPOL
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | RSVD | RO | RESERVED |
| 30 | MSPIRST | RW | Not used. To reset the module, toggle the SMOD_EN for the module |
| 29:27 | DOUTDLY | RW | Delay tap to use for the output signal (MOSI). This give more hold time on the output data |
| 26:24 | DINDLY | RW | Delay tap to use for the input signal (MISO). This gives more hold time on the input data. |
| 23 | SPILSB | RW | Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first. MSB = 0x0 - Send and receive MSB bit first LSB = 0x1 - Send and receive LSB bit first |
| 22 | RDFCPOL | RW | selects the read flow control signal polarity. HIGH = 0x0 - Flow control signal high creates flow control. LOW = 0x1 - Flow control signal low creates flow control. |
| 21 | WTFCPOL | RW | selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers). HIGH = 0x0 - Flow control signal high(1) creates flow control and byte transfers will stop until the flow control signal goes low. LOW = 0x1 - Flow control signal low(0) creates flow control and byte transfers will stop until the flow control signal goes high(1). |
| 20 | WTFCIRQ | RW | selects the write mode flow control signal. MISO = 0x0 - MISO is used as the write mode flow control signal. IRQ = 0x1 - IRQ is used as the write mode flow control signal. |
| 19 | RSVD | RO | Reserved |
| 18 | MOSIINV | RW | inverts MOSI when flow control is enabled. NORMAL = 0x0 - MOSI is set to 0 in read mode and 1 in write mode. INVERT = 0x1 - MOSI is set to 1 in read mode and 0 in write mode. |
| 17 | RDFC | RW | enables read mode flow control. DIS = 0x0 - Read mode flow control disabled. EN = 0x1 - Read mode flow control enabled. |
| 16 | WTFC | RW | enables write mode flow control. DIS = 0x0 - Write mode flow control disabled. EN = 0x1 - Write mode flow control enabled. |
| 15:3 | RSVD | RO | RESERVED |
| 2 | FULLDUP | RW | Enables full duplex mode for Master SPI write operations. Data will be captured simultaneously into the read fifo |
| 1 | SPHA | RW | selects SPI phase. SAMPLE_LEADING_EDGE = 0x0 - Sample on the leading (first) clock edge. SAMPLE_TRAILING_EDGE = 0x1 - Sample on the trailing (second) clock edge. |
| 0 | SPOL | RW | selects SPI polarity. CLK_BASE_0 = 0x0 - The base value of the clock is 0. CLK_BASE_1 = 0x1 - The base value of the clock is 1. |
| Instance 0 Address: | 0x50004400 |
| Instance 1 Address: | 0x50005400 |
| Instance 2 Address: | 0x50006400 |
| Instance 3 Address: | 0x50007400 |
| Instance 4 Address: | 0x50008400 |
| Instance 5 Address: | 0x50009400 |
Controls the configuration of the I2C bus master.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSRVD3
0x0 |
STRDIS
0x0 |
SMPCNT
0x0 |
SDAENDLY
0x0 |
SCLENDLY
0x0 |
RSRVD2
0x0 |
MI2CRST
0x0 |
SDADLY
0x0 |
RSRVD1
0x0 |
ARBEN
0x0 |
I2CLSB
0x0 |
ADDRSZ
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:25 | RSRVD3 | RO | Reserved |
| 24 | STRDIS | RW | Disable detection of clock stretch events smaller than 1 cycle |
| 23:16 | SMPCNT | RW | Number of Base clk cycles to wait before sampling the SCL clock to determine if a clock stretch event has occured |
| 15:12 | SDAENDLY | RW | Number of IOCLK cycles to delay the SDA output en (all transitions affected). Used to delay data relative to clock |
| 11:8 | SCLENDLY | RW | Number of IOCLK cycles to delay the rising edge of the SCL output en (clock will go low on this edge). Used to allow clock shaping. |
| 7 | RSRVD2 | RO | Reserved |
| 6 | MI2CRST | RW | Not used. To reset the module, toggle the SMOD_EN for the module |
| 5:4 | SDADLY | RW | Delay to enable on the SDA output. Values are 0x0-0x3. |
| 3 | RSRVD1 | RO | Reserved |
| 2 | ARBEN | RW | Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master, this function can be disabled to save clock cycles on I2C transactions ARBEN = 0x1 - Enable multi-master bus arbitration support for this i2c master ARBDIS = 0x0 - Disable multi-master bus arbitration support for this i2c master |
| 1 | I2CLSB | RW | Direction of data transmit and receive, MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data, and read data will be bit MSBFIRST = 0x0 - Byte data is transmitted MSB first onto the bus/read from the bus LSBFIRST = 0x1 - Byte data is transmitted LSB first onto the bus/read from the bus |
| 0 | ADDRSZ | RW | Sets the I2C master device address size to either 7b (0) or 10b (1). ADDRSZ7 = 0x0 - Use 7b addressing for I2C master transactions ADDRSZ10 = 0x1 - Use 10b addressing for I2C master transactions |
| Instance 0 Address: | 0x50004404 |
| Instance 1 Address: | 0x50005404 |
| Instance 2 Address: | 0x50006404 |
| Instance 3 Address: | 0x50007404 |
| Instance 4 Address: | 0x50008404 |
| Instance 5 Address: | 0x50009404 |
Contains the I2C device address.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DEVADDR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | Reserved |
| 9:0 | DEVADDR | RW | I2C address of the device that the Master will use to target for read/write operations. This can be either a 7b or 10b address. |
| Instance 0 Address: | 0x50004410 |
| Instance 1 Address: | 0x50005410 |
| Instance 2 Address: | 0x50006410 |
| Instance 3 Address: | 0x50007410 |
| Instance 4 Address: | 0x50008410 |
| Instance 5 Address: | 0x50009410 |
Debug control
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DBGDATA
0x0 |
APBCLKON
0x0 |
IOCLKON
0x0 |
DBGEN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:3 | DBGDATA | RW | Debug control for various options. DBGDATA[1:0] is used to select between different debug data available in the DBG0 and DBG1 registers. |
| 2 | APBCLKON | RW | APBCLK debug clock control. Enable APB_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed. |
| 1 | IOCLKON | RW | IOCLK debug clock control. Enable IO_CLK to be active when this bit is '1'. Otherwise, the clock is controlled with gating from the logic as needed. |
| 0 | DBGEN | RW | Debug Enable. Setting bit will enable the update of data within this register, otherwise it is clock gated for power savings |


--- title: Quantity Toggle layout: layout-sidenav description: The quantity toggle component is used to increase or decrease an incremental venue, usually best used when the user needs to enter or adjust the quantity of a selected item. category: general react-link: ?path=/docs/components-quantitytoggle--default-story github-link: true toc: true --- {% capture quantity-toggle-left-disabled %}
Within the quantity toggle
Ensure that there is at least 16px of horizontal spacing withi the quantity toggle.
Quantity toggle should be used:
Quantity toggle should not be used:
Ensure that a default value is shown within the field.
List the current value of the input so that user is able to know how much the value should increase/decrease upon clicking on up/down button.
Enable the user to also choose to type a number in the field.
User may prefer to type the value instead of clicking on the buttons, so such options should remain enabled.


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