| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [5] | DBEN5 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [6] | DBEN6 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [7] | DBEN7 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [8] | DBEN8 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [9] | DBEN9 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [10] | DBEN10 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [11] | DBEN11 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [12] | DBEN12 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [13] | DBEN13 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [14] | DBEN14 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [15] | DBEN15 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. |
Definition at line 15615 of file NUC472_442.h.
| __IO uint32_t EADC_T::DBMEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | AD0DBM0 | Double Buffer Mode For SAMPLE00 |
| 0 = SAMPLE00 has one sample result register. (default). | ||
| 1 =SAMPLE00 has two sample result registers. | ||
| [1] | AD0DBM1 | Double Buffer Mode For SAMPLE01 |
| 0 = SAMPLE01 has one sample result register. (default). | ||
| 1 = SAMPLE01 has two sample result registers. | ||
| [2] | AD0DBM2 | Double Buffer Mode For SAMPLE02 |
| 0 = SAMPLE02 has one sample result register. (default). | ||
| 1 =SAMPLE02 has two sample result registers. | ||
| [3] | AD0DBM3 | Double Buffer Mode For SAMPLE03 |
| 0 = SAMPLE03 has one sample result register. (default). | ||
| 1 =SAMPLE03 has two sample result registers. | ||
| [8] | AD1DBM0 | Double Buffer Mode For SAMPLE10 |
| 0 = SAMPLE10 has one sample result register. (default) | ||
| 1 =SAMPLE10 has two sample result registers. | ||
| [9] | AD1DBM1 | Double Buffer Mode For SAMPLE11 |
| 0 = SAMPLE11 has one sample result register. (default). | ||
| 1 =SAMPLE11 has two sample result registers. | ||
| [10] | AD1DBM2 | Double Buffer Mode For SAMPLE12 |
| 0 = SAMPLE12 has one sample result register. (default). | ||
| 1 =SAMPLE12 has two sample result registers. | ||
| [11] | AD1DBM3 | Double Buffer Mode For SAMPLE13 |
| 0 = SAMPLE13 has one sample result register. (default) | ||
| 1 =SAMPLE13 has two sample result registers. |
Definition at line 9060 of file NUC472_442.h.
| __I uint32_t FMC_T::DFBA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DFBA | Data Flash Base Address |
| This register indicates data flash start address. It is a read only register. | ||
| The data flash is shared with APROM and data flash size is defined by user configuration and the content of this register is loaded from Config1. |
Definition at line 14695 of file NUC472_442.h.
| __IO uint32_t GPIO_T::DINOFF |
| Bits | Field | Descriptions |
|---|---|---|
| [16] | DINOFF0 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [17] | DINOFF1 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [18] | DINOFF2 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [19] | DINOFF3 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [20] | DINOFF4 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [21] | DINOFF5 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [22] | DINOFF6 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [23] | DINOFF7 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [24] | DINOFF8 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [25] | DINOFF9 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [26] | DINOFF10 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [27] | DINOFF11 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [28] | DINOFF12 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [29] | DINOFF13 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [30] | DINOFF14 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). | ||
| [31] | DINOFF15 | Port N Bit M Off Digital Input Path |
| Each of these bits is used to turn off the digital input path of port n bit m pin. | ||
| If input is analog signal, users can turn off digital input path to avoid input current leakage. | ||
| 0 = Digital input path Enabled. | ||
| 1 = Digital input path Disabled (Digital input is tied to low). |
Definition at line 15255 of file NUC472_442.h.
| __IO uint32_t USBD_T::DMAADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DMAADDR | DMAADDR |
| The register specifies the address from which the DMA has to read / write. | ||
| The address must WORD (32-bit) aligned. |
Definition at line 27943 of file NUC472_442.h.
| __I uint32_t SDH_T::DMABCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:25] | BCNT | DMA Transfer Byte Count (Read Only) |
| This field indicates the remained byte count of DMA transfer. | ||
| The value of this field is valid only when DMA is busy; otherwise, it is 0. |
Definition at line 22135 of file NUC472_442.h.
| __IO uint32_t USBD_T::DMACNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:19] | DMACNT | DMA Transfer Count |
| The transfer count of the DMA operation to be performed is written to this register. |
Definition at line 27924 of file NUC472_442.h.
| __IO uint32_t SDH_T::DMACTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DMAEN | DMA Engine Enable Control |
| 0 = DMA Disabled. | ||
| 1 = DMA Enabled. | ||
| If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. | ||
| Note: If target abort is occurred, DMAEN will be cleared. | ||
| [1] | DMARST | Software Engine Reset |
| 0 = No effect. | ||
| 1 = Reset internal state machine and pointers. | ||
| The contents of control register will not be cleared. | ||
| This bit will auto be cleared after few clock cycles. | ||
| Note: The software reset DMA related registers. | ||
| [3] | SGEN | Scatter-Gather Function Enable Control |
| 0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory). | ||
| 1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table. | ||
| The format of these Pads' will be described later). | ||
| [9] | DMABUSY | DMA Transfer Is In Progress |
| This bit indicates if SD Host is granted and doing DMA transfer or not. | ||
| 0 = DMA transfer is not in progress. | ||
| 1 = DMA transfer is in progress. |
Definition at line 22101 of file NUC472_442.h.
| __IO uint32_t USBD_T::DMACTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | EPNUM | DMA Endpoint Address Bits |
| Used to define the Endpoint Address | ||
| [4] | DMARD | DMA Operation |
| 0 = the operation is a DMA write. | ||
| 1 = the operation is a DMA read. | ||
| [5] | DMAEN | DMA Enable Control |
| 0 = DMA function Disabled. | ||
| 1 = DMA function Enabled. | ||
| [6] | SGEN | Scatter Gather Function Enable Control |
| 0 = Scatter gather function Disabled. | ||
| 1 = Scatter gather function Enabled. | ||
| [7] | DMARST | Reset DMA State Machine |
| 0 = No reset the DMA state machine. | ||
| 1 = Reset the DMA state machine. |
Definition at line 27912 of file NUC472_442.h.
| __IO uint32_t SDH_T::DMAINTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ABORTIEN | DMA Read/Write Target Abort Interrupt Enable Control |
| 0 = Target abort interrupt generation Disabled during DMA transfer. | ||
| 1 = Target abort interrupt generation Enabled during DMA transfer. | ||
| [1] | WEOTIEN | Wrong EOT Encountered Interrupt Enable Control |
| 0 = Interrupt generation Disabled when wrong EOT is encountered. | ||
| 1 = Interrupt generation Enabled when wrong EOT is encountered. |
Definition at line 22151 of file NUC472_442.h.
| __IO uint32_t SDH_T::DMAINTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ABORTIF | DMA Read/Write Target Abort Interrupt Flag |
| 0 = No bus ERROR response received. | ||
| 1 = Bus ERROR response received. | ||
| Note: This bit is read only, but can be cleared by writing '1' to it. | ||
| [1] | WEOTIF | Wrong EOT Encountered Interrupt Flag |
| When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set. | ||
| 0 = No EOT encountered before DMA transfer finished. | ||
| 1 = EOT encountered before DMA transfer finished. | ||
| Note: This bit is read only, but can be cleared by writing '1' to it. |
Definition at line 22170 of file NUC472_442.h.
| __IO uint32_t SDH_T::DMASA |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ORDER | Determined To The PAD Table Fetching Is In Order Or Out Of Order |
| 0 = PAD table is fetched in order. | ||
| 1 = PAD table is fetched out of order. | ||
| Note: the bit0 is valid in scatter-gather mode when SGEN = 1. | ||
| [1:31] | DMASA | DMA Transfer Starting Address |
| This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data. | ||
| If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table. |
Definition at line 22122 of file NUC472_442.h.
| __IO uint32_t GPIO_T::DOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DOUT0 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [1] | DOUT1 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [2] | DOUT2 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [3] | DOUT3 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [4] | DOUT4 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [5] | DOUT5 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [6] | DOUT6 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [7] | DOUT7 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [8] | DOUT8 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [9] | DOUT9 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [10] | DOUT10 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [11] | DOUT11 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [12] | DOUT12 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [13] | DOUT13 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [14] | DOUT14 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. | ||
| [15] | DOUT15 | Port N Bit M Output |
| Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode. | ||
| 0 = Drive port n bit m high low. | ||
| 1 = Drive port n bit m high level. |
Definition at line 15329 of file NUC472_442.h.
| DSCT_T PDMA_T::DSCT[16] |
Definition at line 18228 of file NUC472_442.h.
| __IO uint32_t EPWM_T::DTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:10] | DTCNT | Dead-Time Counter |
| The dead-time can be calculated from the following formula: | ||
| Dead-time = EPWMx_CLK period * (DTCNT.[10:0]+1). | ||
| [16] | DTEN0 | Dead-Time Insertion Enable Control For PWMx Pair (PWM0, PWM1) |
| Dead-time insertion is only active when this pair of complementary PWM is enabled. | ||
| If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-time insertion Disabled on the pin pair (PWM0, PWM1). | ||
| 1 = Dead-time insertion Enabled on the pin pair (PWM0, PWM1). | ||
| Note: x=0~1 for PWM unit0~1. | ||
| [17] | DTEN2 | Dead-Time Insertion Enable Control For PWMx Pair (PWM2, PWM3) |
| Dead-time insertion is only active when this pair of complementary PWM is enabled. | ||
| If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-time insertion Disabled on the pin pair (PWM2, PWM3). | ||
| 1 = Dead-time insertion Enabled on the pin pair (PWM2, PWM3). | ||
| Note: x=0~1 for PWM unit0~1. | ||
| [18] | DTEN4 | Dead-Time Insertion Enable Control For PWMx Pair (PWM4, PWM5) |
| Dead-time insertion is only active when this pair of complementary PWM is enabled. | ||
| If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-time insertion Disabled on the pin pair (PWM4, PWM5). | ||
| 1 = Dead-time insertion Enabled on the pin pair (PWM4, PWM5). | ||
| Note: x=0~1 for PWM unit0~1. |
Definition at line 14218 of file NUC472_442.h.
| __IO uint32_t PWM_T::DTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | DTCNT01 | Dead-Zone Interval For PWM Pair Of Channel 0 And Channel 1 |
| These 8-bit determine the Dead-zone length. | ||
| The unit time of Dead-zone length is received from corresponding PWM_CLKDIV. | ||
| [8:15] | DTCNT23 | Dead-Zone Interval For PWM Pair Of Channel 2 And Channel 3 |
| These 8-bit determine the Dead-zone length. | ||
| The unit time of Dead-zone length is received from corresponding PWM_CLKDIV. | ||
| [16:23] | DTCNT45 | Dead-Zone Interval For PWM Pair Of Channel 4 And Channel 5 |
| These 8-bit determine the Dead-zone length. | ||
| The unit time of Dead-zone length is received from corresponding PWM_CLKDIV. | ||
| [24:25] | DTDIV | Dead-Zone Generator Divider |
| 00 = Dead-zone clock equal to PWM base clock divide 1. | ||
| 01 = Dead-zone clock equal to PWM base clock divide 2. | ||
| 10 = Dead-zone clock equal to PWM base clock divide 4. | ||
| 11 = Dead-zone clock equal to PWM base clock divide 8. | ||
| [28] | DTEN01 | Dead-Zone Enable Control For PWM Pair Of Channel 0 And Channel 1 |
| Dead-zone insertion is only active when this pair of complementary PWM is enabled. | ||
| If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-zone insertion Disabled. | ||
| 1 = Dead-zone insertion Enabled. | ||
| [29] | DTEN23 | Dead-Zone Enable Control For PWM Pair Of Channel 2 And Channel 3 |
| Dead-zone insertion is only active when this pair of complementary PWM is enabled. | ||
| If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-zone insertion Disabled. | ||
| 1 = Dead-zone insertion Enabled. | ||
| [30] | DTEN45 | Dead-Zone Enable Control For PWM Pair Of Channel 4 And Channel 5 |
| Dead-zone insertion is only active when this pair of complementary PWM is enabled. | ||
| If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-zone insertion Disabled. | ||
| 1 = Dead-zone insertion Enabled. |
Definition at line 19291 of file NUC472_442.h.
| __IO uint32_t SC_T::EGT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | EGT | Extended Guard Time |
| This field indicates the extended guard timer value. | ||
| Note: The counter is ETU base and the real extended guard time is EGT. |
Definition at line 21338 of file NUC472_442.h.
| __IO uint32_t EPWM_T::EINTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | EDGEIEN0 | PWMx0 Edge Interrupt Enable Control |
| 0 = Disabling flag EIF0 to trigger PWM interrupt. | ||
| 1 = Enabling flag EIF0 can trigger PWM interrupt. | ||
| [1] | EDGEIEN2 | PWMx2 Edge Interrupt Enable Control |
| 0 = Disabling flag EIF2 can trigger PWM interrupt. | ||
| 1 = Enabling flag EIF2 can trigger PWM interrupt. | ||
| [2] | EDGEIEN4 | PWMx4 Edge Interrupt Enable Control |
| 0 = Disable flag EIF4 to trigger PWM interrupt. | ||
| 1 = Enabling flag EIF4 can trigger PWM interrupt. | ||
| [8] | EINTTYPE0 | PWMx0 Edge Interrupt Type |
| 0 = EIF0 will be set if falling edge is detected at PWMx0. | ||
| 1 = EIF0 will be set if rising edge is detected at PWMx0. | ||
| [9] | EINTTYPE2 | PWMx2 Edge Interrupt Type |
| 0 = EIF2 will be set if falling edge is detected at PWMx2. | ||
| 1 = EIF2 will be set if rising edge is detected at PWMx2. | ||
| [10] | EINTTYPE4 | PWMx4 Edge Interrupt Type |
| 0 = EIF4 will be set if falling edge is detected at PWMx4. | ||
| 1 = EIF4 will be set if rising edge is detected at PWMx4. |
Definition at line 14369 of file NUC472_442.h.
| __IO uint32_t TIMER_T::EINTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CAPIF | Timer External Interrupt Flag |
| This bit indicates the timer external interrupt flag status. | ||
| When CAPEN (TIMER_EXTCTL[3]) bit is set, CAPFUNCS (TIMER_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMER_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. | ||
| 0 = TMx_EXT (x= 0~3) pin interrupt did not occur. | ||
| 1 = TMx_EXT (x= 0~3) pin interrupt occurred. | ||
| Note: This bit is cleared by writing 1 to it. |
Definition at line 25075 of file NUC472_442.h.
| __IO uint32_t DSCT_T::ENDDA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | ENDDA | PDMA Transfer Ending Destination Address Bits |
| This field indicates a 32-bit ending destination address of PDMA. | ||
| Note: If the destination start address is 0x2000_0000, the transfer count is 0x100 and the destination address increment is word, this field must be filled 0x2000_0400. | ||
| The equation is "0x2000_0400 = 0x2000_0000 + 0x100*4(word)". |
Definition at line 18208 of file NUC472_442.h.
| __IO uint32_t DSCT_T::ENDSA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | ENDSA | PDMA Transfer Ending Source Address Bits |
| This field indicates a 32-bit ending source address of PDMA. | ||
| Note: If the source start address is 0x2000_0000, the transfer count is 0x100 and the source address increment is word, this field must be filled 0x2000_0400. | ||
| The equation is "0x2000_0400 = 0x2000_0000 + 0x100*4(word)". |
Definition at line 18194 of file NUC472_442.h.
| USBD_EP_T USBD_T::EP[12] |
Definition at line 27926 of file NUC472_442.h.
| __IO uint32_t USBD_EP_T::EPBUFEND |
| Bits | Field | Descriptions |
|---|---|---|
| [0:11] | EADDR | Endpoint End Address |
| This is the end-address of the RAM space allocated for the endpoint A~L. |
Definition at line 27252 of file NUC472_442.h.
| __IO uint32_t USBD_EP_T::EPBUFSTART |
| Bits | Field | Descriptions |
|---|---|---|
| [0:11] | SADDR | Endpoint Start Address |
| This is the start-address of the RAM space allocated for the endpoint A~L. |
Definition at line 27240 of file NUC472_442.h.
| __IO uint32_t USBD_EP_T::EPCFG |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | EPEN | Endpoint Valid |
| When set, this bit enables this endpoint. | ||
| This bit has no effect on Endpoint 0, which is always enabled. | ||
| 0 = The endpoint Disabled. | ||
| 1 = The endpoint Enabled. | ||
| [1:2] | EPTYPE | Endpoint Type |
| This field selects the type of this endpoint. Endpoint 0 is forced to a Control type. | ||
| 00 = Reserved. | ||
| 01 = Bulk. | ||
| 10 = Interrupt. | ||
| 11 = Isochronous. | ||
| [3] | EPDIR | Endpoint Direction |
| 0 = out-endpoint (Host OUT to Device). | ||
| 1 = in-endpoint (Host IN to Device). | ||
| Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number. | ||
| [4:7] | EPNUM | Endpoint Number |
| This field selects the number of the endpoint. Valid numbers 1 to 15. |
Definition at line 27228 of file NUC472_442.h.
| __IO uint32_t USBD_EP_T::EPDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | EPDAT | Endpoint A~L Data Register |
| Endpoint A~L data buffer for the buffer transaction (read or write). | ||
| Note: Only word or byte access are supported. |
Definition at line 26967 of file NUC472_442.h.
| __IO uint32_t { ... } ::EPDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | EPDAT | Endpoint A~L Data Register |
| Endpoint A~L data buffer for the buffer transaction (read or write). | ||
| Note: Only word or byte access are supported. |
Definition at line 26967 of file NUC472_442.h.
| __IO uint8_t USBD_EP_T::EPDAT_BYTE |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | EPDAT | Endpoint A~L Data Register |
| Endpoint A~L data buffer for the buffer transaction (read or write). | ||
| Note: Only word or byte access are supported. |
Definition at line 26979 of file NUC472_442.h.
| __IO uint8_t { ... } ::EPDAT_BYTE |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | EPDAT | Endpoint A~L Data Register |
| Endpoint A~L data buffer for the buffer transaction (read or write). | ||
| Note: Only word or byte access are supported. |
Definition at line 26979 of file NUC472_442.h.
| __I uint32_t USBD_EP_T::EPDATCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | DATCNT | Data Count |
| For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer. | ||
| [16:30] | DMALOOP | DMA Loop |
| This register is the remaining DMA loop to complete. Each loop means 32-byte transfer. |
Definition at line 27126 of file NUC472_442.h.
| __IO uint32_t USBD_EP_T::EPINTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUFFULLIEN | Buffer Full Interrupt |
| When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus. | ||
| 0 = Buffer full interrupt Disabled. | ||
| 1 = Buffer full interrupt Enabled. | ||
| [1] | BUFEMPTYIEN | Buffer Empty Interrupt |
| When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus. | ||
| 0 = Buffer empty interrupt Disabled. | ||
| 1 = Buffer empty interrupt Enabled. | ||
| [2] | SHORTTXIEN | Short Packet Transferred Interrupt Enable Control |
| When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host. | ||
| 0 = Short data packet interrupt Disabled. | ||
| 1 = Short data packet interrupt Enabled. | ||
| [3] | TXPKIEN | Data Packet Transmitted Interrupt Enable Control |
| When set, this bit enables a local interrupt to be set when a data packet has been received from the host. | ||
| 0 = Data packet has been received from the host interrupt Disabled. | ||
| 1 = Data packet has been received from the host interrupt Enabled. | ||
| [4] | RXPKIEN | Data Packet Received Interrupt Enable Control |
| When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host. | ||
| 0 = Data packet has been transmitted to the host interrupt Disabled. | ||
| 1 = Data packet has been transmitted to the host interrupt Enabled. | ||
| [5] | OUTTKIEN | Data OUT Token Interrupt Enable Control |
| When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host. | ||
| 0 = Data OUT token interrupt Disabled. | ||
| 1 = Data OUT token interrupt Enabled. | ||
| [6] | INTKIEN | Data IN Token Interrupt Enable Control |
| When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host. | ||
| 0 = Data IN token interrupt Disabled. | ||
| 1 = Data IN token interrupt Enabled. | ||
| [7] | PINGIEN | PING Token Interrupt Enable Control |
| When set, this bit enables a local interrupt to be set when a PING token has been received from the host. | ||
| 0 = PING token interrupt Disabled. | ||
| 1 = PING token interrupt Enabled. | ||
| [8] | NAKIEN | USB NAK Sent Interrupt Enable Control |
| When set, this bit enables a local interrupt to be set when a NAK token is sent to the host. | ||
| 0 = NAK token interrupt Disabled. | ||
| 1 = NAK token interrupt Enabled. | ||
| [9] | STALLIEN | USB STALL Sent Interrupt Enable Control |
| When set, this bit enables a local interrupt to be set when a stall token is sent to the host. | ||
| 0 = STALL token interrupt Disabled. | ||
| 1 = STALL token interrupt Enabled. | ||
| [10] | NYETIEN | NYET Interrupt Enable Control |
| When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint. | ||
| 0 = NYET condition interrupt Disabled. | ||
| 1 = NYET condition interrupt Enabled. | ||
| [11] | ERRIEN | ERR Interrupt Enable Control |
| When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint. | ||
| 0 = Error event interrupt Disabled. | ||
| 1 = Error event interrupt Enabled. | ||
| [12] | SHORTRXIEN | Bulk Out Short Packet Interrupt Enable Control |
| When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint. | ||
| 0 = Bulk out interrupt Disabled. | ||
| 1 = Bulk out interrupt Enabled. |
Definition at line 27112 of file NUC472_442.h.
| __IO uint32_t USBD_EP_T::EPINTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUFFULLIF | Buffer Full |
| For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write). | ||
| For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading). | ||
| 0 = The endpoint packet buffer is not full. | ||
| 1 = The endpoint packet buffer is full. | ||
| Note: This bit is read-only. | ||
| [1] | BUFEMPTYIF | Buffer Empty |
| For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes. | ||
| 0 = The endpoint buffer is not empty. | ||
| 1 = The endpoint buffer is empty. | ||
| For an OUT endpoint: | ||
| 0 = The currently selected buffer has not a count of 0. | ||
| 1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read). | ||
| Note: This bit is read-only. | ||
| [2] | SHORTTXIF | Short Packet Transferred Interrupt |
| 0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS). | ||
| 1 = The length of the last packet was less than the Maximum Packet Size (EPMPS). | ||
| Note: Write 1 to clear this bit to 0. | ||
| [3] | TXPKIF | Data Packet Transmitted Interrupt |
| 0 = Not a data packet is transmitted from the endpoint to the host. | ||
| 1 = A data packet is transmitted from the endpoint to the host. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [4] | RXPKIF | Data Packet Received Interrupt |
| 0 = No data packet is received from the host by the endpoint. | ||
| 1 = A data packet is received from the host by the endpoint. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [5] | OUTTKIF | Data OUT Token Interrupt |
| 0 = A Data OUT token has not been received from the host. | ||
| 1 = A Data OUT token has been received from the host. | ||
| This bit also set by PING tokens(in high-speed only). | ||
| Note: Write 1 to clear this bit to 0. | ||
| [6] | INTKIF | Data IN Token Interrupt |
| 0 = Not Data IN token has been received from the host. | ||
| 1 = A Data IN token has been received from the host. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [7] | PINGIF | PING Token Interrupt |
| 0 = A Data PING token has not been received from the host. | ||
| 1 = A Data PING token has been received from the host. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [8] | NAKIF | USB NAK Sent |
| 0 = The last USB IN packet could be provided, and was acknowledged with a ACK. | ||
| 1 = The last USB IN packet could not be provided, and was acknowledged with a NAK. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [9] | STALLIF | USB STALL Sent |
| 0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. | ||
| 1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [10] | NYETIF | NYET Sent |
| 0 = The space available in the RAM is sufficient to accommodate the next on coming data packet. | ||
| 1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [11] | ERRIF | ERR Sent |
| 0 = No any error in the transaction. | ||
| 1 = There occurs any error in the transaction. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [12] | SHORTRXIF | Bulk Out Short Packet Received |
| 0 = No bulk out short packet is received. | ||
| 1 = Received bulk out short packet (including zero length packet ). | ||
| Note: Write 1 to clear this bit to 0. |
Definition at line 27050 of file NUC472_442.h.
| __IO uint32_t USBD_EP_T::EPMPS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:10] | EPMPS | Endpoint Maximum Packet Size |
| This field determines the Maximum Packet Size of the Endpoint. |
Definition at line 27188 of file NUC472_442.h.
| __IO uint32_t USBD_EP_T::EPRSPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FLUSH | Buffer Flush |
| Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. | ||
| This bit is self-clearing. | ||
| This bit should always be written after an configuration event. | ||
| 0 = The packet buffer is not flushed. | ||
| 1 = The packet buffer is flushed by user. | ||
| [1:2] | MODE | Mode Control |
| The two bits decide the operation mode of the in-endpoint. | ||
| 00: Auto-Validate Mode | ||
| 01: Manual-Validate Mode | ||
| 10: Fly Mode | ||
| 11: Reserved | ||
| These bits are not valid for an out-endpoint. | ||
| The auto validate mode will be activated when the reserved mode is selected. | ||
| [3] | TOGGLE | Endpoint Toggle |
| This bit is used to clear the endpoint data toggle bit. | ||
| Reading this bit returns the current state of the endpoint data toggle bit. | ||
| The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host. | ||
| Only when toggle bit is "1", this bit can be written into the inversed write data bit[3]. | ||
| 0 = Not clear the endpoint data toggle bit. | ||
| 1 = Clear the endpoint data toggle bit. | ||
| [4] | HALT | Endpoint Halt |
| This bit is used to send a STALL handshake as response to the token from the host. | ||
| When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit. | ||
| 0 = Not send a STALL handshake as response to the token from the host. | ||
| 1 = Send a STALL handshake as response to the token from the host. | ||
| [5] | ZEROLEN | Zero Length |
| This bit is used to send a zero-length packet n response to an IN-token. | ||
| When this bit is set, a zero packet is sent to the host on reception of an IN-token. | ||
| 0 = A zero packet is not sent to the host on reception of an IN-token. | ||
| 1 = A zero packet is sent to the host on reception of an IN-token. | ||
| [6] | SHORTTXEN | Short Packet Transfer Enable |
| This bit is applicable only in case of Auto-Validate Method. | ||
| This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer. | ||
| 0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint. | ||
| 1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint. | ||
| [7] | DISBUF | Buffer Disable Control |
| This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received. | ||
| 0 = Buffer Not Disabled when Bulk-OUT short packet is received. | ||
| 1 = Buffer Disabled when Bulk-OUT short packet is received. |
Definition at line 27176 of file NUC472_442.h.
| __IO uint32_t USBD_EP_T::EPTXCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:10] | TXCNT | Endpoint Transfer Count |
| For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method. | ||
| For OUT endpoints, this field has no effect. |
Definition at line 27201 of file NUC472_442.h.
| __IO uint32_t CAN_T::ERR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | TEC | Transmit Error Counter |
| Actual state of the Transmit Error Counter. Values between 0 and 255. | ||
| [8:14] | REC | Receive Error Counter |
| Actual state of the Receive Error Counter. Values between 0 and 127. | ||
| [15] | RP | Receive Error Passive |
| 0 = The Receive Error Counter is below the error passive level. | ||
| 1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification. |
Definition at line 1205 of file NUC472_442.h.
| __IO uint32_t SC_T::ETUCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:11] | ETURDIV | ETU Rate Divider |
| The field indicates the clock rate divider. | ||
| The real ETU is ETURDIV + 1. | ||
| Note: Software can configure this field, but this field must be greater than 0x004. | ||
| [15] | CMPEN | Compensation Mode Enable Control |
| This bit enables clock compensation function. | ||
| When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV . | ||
| 0 = Compensation function Disabled. | ||
| 1 = Compensation function Enabled. |
Definition at line 21372 of file NUC472_442.h.
| __IO uint32_t TIMER_T::EXTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CNTPHASE | Timer External Count Phase |
| This bit indicates the detection phase of external counting pin. | ||
| 0 = A falling edge of external counting pin will be counted. | ||
| 1 = A rising edge of external counting pin will be counted. | ||
| [1:2] | CAPEDGE | Timer External Pin Edge Detect |
| 00 = A 1 to 0 transition on TMx_EXT (x= 0~3) pin will be detected. | ||
| 01 = A 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected. | ||
| 10 = Either 1 to 0 or 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected. | ||
| 11 = Reserved. | ||
| [3] | CAPEN | Timer External Pin Enable |
| This bit enables the CAPFUNCS (TIMER_EXTCTL[4]) function on the TMx_EXT pin. | ||
| 0 = CAPFUNCS function of TMx_EXT (x= 0~3) pin will be ignored. | ||
| 1 = CAPFUNCS function of TMx_EXT (x= 0~3) pin is active. | ||
| [4] | CAPFUNCS | Timer External Reset Counter / Capture Mode Select |
| 0 = Transition on TMx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value. | ||
| (TIMER_CNT value) to timer capture value (TIMER_CAP value) if CAPIF (TIMER_EINTSTS[0]) is set to 1 | ||
| 1 = Transition on TMx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value. | ||
| [5] | CAPIEN | Timer External Interrupt Enable |
| 0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled. | ||
| 1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled. | ||
| CAPIEN is used to enable timer external interrupt. | ||
| If CAPIEN enabled, timer will rise an interrupt when CAPIF = 1. | ||
| For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TEX pin will cause the CAPIF(TIMER_EINTSTS[0]) interrupt flag to be set then the interrupt signal is generated and sent to NVIC to inform CPU. | ||
| [6] | CAPDBEN | Timer External Capture Pin De-Bounce Enable |
| 0 = TMx_EXT (x= 0~3) pin de-bounce Disabled. | ||
| 1 = TMx_EXT (x= 0~3) pin de-bounce Enabled. | ||
| If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit. | ||
| [7] | ECNTDBEN | Timer Counter Pin De-Bounce Enable |
| 0 = TMx (x= 0~3) pin de-bounce Disabled. | ||
| 1 = TMx (x= 0~3) pin de-bounce Enabled. | ||
| If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. |
Definition at line 25059 of file NUC472_442.h.
| __IO uint32_t EADC_T::EXTSMPT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | EXTSMPT0 | ADC0 Extend Sampling Time |
| When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time. | ||
| The range of start delay time is from 0~255 ADC clock. | ||
| [16:23] | EXTSMPT1 | ADC1 Extend Sampling Time |
| When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time. | ||
| The range of start delay time is from 0~255 ADC clock. |
Definition at line 8890 of file NUC472_442.h.
| __IO uint32_t USBD_T::FADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:6] | FADDR | USB Function Address |
| This field contains the current USB address of the device. | ||
| This field is cleared when a root port reset is detected. |
Definition at line 27537 of file NUC472_442.h.
| uint32_t SDH_T::FB[32] |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | BUF | Shared Buffer |
Definition at line 22068 of file NUC472_442.h.
| __IO uint32_t FMC_T::FBWP |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | BWP | Flash Block Write Protect Control |
| If BWP.N bit is set to 0, the APROM memory relative region cannot program and erase by ISP. (N=0~31). | ||
| Bit Block Protect Region | ||
| BWP0 0x00_0000 ~ 0x00_3FFF | ||
| BWP1 0x00_4000 ~ 0x00_7FFF | ||
| BWP2 0x00_8000 ~ 0x00_BFFF | ||
| BWP3 0x00_C000 ~ 0x00_FFFF | ||
| BWP4 0x01_0000 ~ 0x01_3FFF | ||
| BWP5 0x01_4000 ~ 0x01_7FFF | ||
| BWP6 0x01_8000 ~ 0x01_BFFF | ||
| BWP7 0x01_C000 ~ 0x01_FFFF | ||
| BWP8 0x02_0000 ~ 0x02_3FFF | ||
| BWP9 0x02_4000 ~ 0x02_7FFF | ||
| BWP10 0x02_8000 ~ 0x02_BFFF | ||
| BWP11 0x02_C000 ~ 0x02_FFFF | ||
| BWP12 0x03_0000 ~ 0x03_3FFF | ||
| BWP13 0x03_4000 ~ 0x03_7FFF | ||
| BWP14 0x03_8000 ~ 0x03_BFFF | ||
| BWP15 0x03_C000 ~ 0x03_FFFF | ||
| BWP16 0x04_0000 ~ 0x04_3FFF | ||
| BWP17 0x04_4000 ~ 0x04_7FFF | ||
| BWP18 0x04_8000 ~ 0x04_BFFF | ||
| BWP19 0x04_C000 ~ 0x04_FFFF | ||
| BWP20 0x05_0000 ~ 0x05_3FFF | ||
| BWP21 0x05_4000 ~ 0x05_7FFF | ||
| BWP22 0x05_8000 ~ 0x05_BFFF | ||
| BWP23 0x05_C000 ~ 0x05_FFFF | ||
| BWP24 0x06_0000 ~ 0x06_3FFF | ||
| BWP25 0x06_4000 ~ 0x06_7FFF | ||
| BWP26 0x06_8000 ~ 0x06_BFFF | ||
| BWP27 0x06_C000 ~ 0x06_FFFF | ||
| BWP28 0x07_0000 ~ 0x07_3FFF | ||
| BWP29 0x07_4000 ~ 0x07_7FFF | ||
| BWP30 0x07_8000 ~ 0x07_BFFF | ||
| BWP31 0x07_C000 ~ 0x07_FFFF | ||
| This register is loaded from Config2 when chip is power on. | ||
| It is read only, except the correct Super Key is matched. | ||
| This register is also a protected bit which means programming this bit needs to write "59h", "16h", "88h" to address GCR_BA+0x100 to disable register protection. | ||
| Refer to the register REGWRPROT at address GCR_BA+0x100. |
Definition at line 14799 of file NUC472_442.h.
| __I uint32_t PWM_T::FCAPDAT0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | FCAPDAT | Capture Falling Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition. |
Definition at line 19603 of file NUC472_442.h.
| __I uint32_t PWM_T::FCAPDAT1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | FCAPDAT | Capture Falling Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition. |
Definition at line 19627 of file NUC472_442.h.
| __I uint32_t PWM_T::FCAPDAT2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | FCAPDAT | Capture Falling Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition. |
Definition at line 19651 of file NUC472_442.h.
| __I uint32_t PWM_T::FCAPDAT3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | FCAPDAT | Capture Falling Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition. |
Definition at line 19675 of file NUC472_442.h.
| __I uint32_t PWM_T::FCAPDAT4 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | FCAPDAT | Capture Falling Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition. |
Definition at line 19699 of file NUC472_442.h.
| __I uint32_t PWM_T::FCAPDAT5 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | FCAPDAT | Capture Falling Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition. |
Definition at line 19723 of file NUC472_442.h.
| __IO uint32_t UART_T::FIFO |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | RXRST | RX Field Software Reset |
| When RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the RX internal state machine and pointers. | ||
| Note: This bit will be automatically cleared for at least 3 UART engine clock cycles. | ||
| [2] | TXRST | TX Field Software Reset |
| When TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the TX internal state machine and pointers. | ||
| Note: This bit will auto clear needs at least 3 UART engine clock cycles. | ||
| [4:7] | RFITL | RX FIFO Interrupt (INT_RDA) Trigger Level |
| When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) is enabled, an interrupt will generated). | ||
| 0000 = 1 byte | ||
| 0001 = 4 bytes | ||
| 0010 = 8 bytes | ||
| 0011 = 14 bytes | ||
| 0100 = 30/14 bytes (High-speed/Normal Speed) | ||
| 0101 = 46/14 bytes (High-speed/Normal Speed) | ||
| 0110 = 62/14 bytes (High-speed/Normal Speed) | ||
| others = 62/14 bytes (High-speed/Normal Speed) | ||
| [8] | RXOFF | Receiver Disable |
| The receiver is disabled or not. | ||
| 0 = Receiver Enabled. | ||
| 1 = Receiver Disabled. | ||
| Note: This field is used for RS-485 Normal Multi-drop mode. | ||
| It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed. | ||
| [16:19] | RTSTRGLV | RTS Trigger Level For Auto-Flow Control Use |
| 0000 = 01 byte | ||
| 0001 = 04 bytes | ||
| 0010 = 08 bytes | ||
| 0011 = 14 bytes | ||
| 0100 = 30/14 bytes (High-speed/Normal Speed) | ||
| 0101 = 46/14 bytes (High-speed/Normal Speed) | ||
| 0110 = 62/14 bytes (High-speed/Normal Speed) | ||
| others = 62/14 bytes (High-speed/Normal Speed) | ||
| Note: This field is used for auto RTS flow control. |
Definition at line 25288 of file NUC472_442.h.
| __IO uint32_t EMAC_T::FIFOCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | RXFIFOTH | RXFIFO Low Threshold |
| The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO and system memory. | ||
| The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold. | ||
| The low threshold is the half of high threshold always. | ||
| During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to transfer frame data from RXFIFO to system memory. | ||
| If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame data to system memory. | ||
| 00 = Depend on the burst length setting. | ||
| If the burst length is 8 words, high threshold is 8 words, too. | ||
| 01 = RXFIFO high threshold is 64B and low threshold is 32B. | ||
| 10 = RXFIFO high threshold is 128B and low threshold is 64B. | ||
| 11 = RXFIFO high threshold is 192B and low threshold is 96B. | ||
| [8:9] | TXFIFOTH | TXFIFO Low Threshold |
| The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system memory and TXFIFO. | ||
| The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold. | ||
| The high threshold is the twice of low threshold always.During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops generate request to transfer frame data from system memory to TXFIFO. | ||
| If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data from system memory to TXFIFO. | ||
| The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network. | ||
| The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold during the transmission of the frame. | ||
| If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame out after the frame data are all inside the TXFIFO. | ||
| 00 = Undefined. | ||
| 01 = TXFIFO low threshold is 64B and high threshold is 128B. | ||
| 10 = TXFIFO low threshold is 80B and high threshold is 160B. | ||
| 11 = TXFIFO low threshold is 96B and high threshold is 192B. | ||
| [20:21] | BURSTLEN | DMA Burst Length |
| This defines the burst length of AHB bus cycle while EMAC accesses system memory. | ||
| 00 = 16 words. | ||
| 01 = 16 words. | ||
| 10 = 8 words. | ||
| 11 = 4 words. |
Definition at line 12568 of file NUC472_442.h.
| __IO uint32_t SPI_T::FIFOCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXRST | Clear Receive FIFO Buffer |
| 0 = No effect. | ||
| 1 = Clear receive FIFO buffer. | ||
| Note1: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST, SPI_SSCTL[6], is enabled. | ||
| Note2: The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. | ||
| This bit will be cleared to 0 by hardware about 3 system clocks + 3 peripheral clock after it is set to 1. | ||
| [1] | TXRST | Clear Transmit FIFO Buffer |
| 0 = No effect. | ||
| 1 = Clear transmit FIFO buffer. | ||
| Note1: If there is slave receive time-out event, the TXRST will be set 1 when the SLVTORST, SPI_SSCTL[6], is enabled. | ||
| Note2: The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. | ||
| This bit will be cleared to 0 by hardware about 3 system clocks + 3 peripheral clock after it is set to 1. | ||
| [2] | RXTHIEN | Receive FIFO Threshold Interrupt Enable Control |
| 0 = RX FIFO threshold interrupt Disabled. | ||
| 1 = RX FIFO threshold interrupt Enabled. | ||
| [3] | TXTHIEN | Transmit FIFO Threshold Interrupt Enable Control |
| 0 = TX FIFO threshold interrupt Disabled. | ||
| 1 = TX FIFO threshold interrupt Enabled. | ||
| [4] | RXTOIEN | Slave Receive Time-Out Interrupt Enable Control (Slave Only) |
| 0 = Receive time-out interrupt Disabled. | ||
| 1 = Receive time-out interrupt Enabled. | ||
| [5] | RXOVIEN | Receive FIFO Overrun Interrupt Enable Control |
| 0 = Receive FIFO overrun interrupt Disabled. | ||
| 1 = Receive FIFO overrun interrupt Enabled. | ||
| [6] | TXUFPOL | Transmit Under-Run Data Out (Slave Only) |
| 0 = The SPI data bus is keep low if there is transmit under-run event. | ||
| 1 = The SPI data bus is keep high if there is transmit under-run event. | ||
| Note1: The under run event is activated after the bus clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the peripheral clock) data out will be the last transaction data. | ||
| Note2: If the frequency of system clock approach to peripheral clock, they may need 3-bit time to report the transmit under-run event. | ||
| [7] | TXUFIEN | Transmit Under Run Interrupt Enable Control (Slave Only) |
| 0 = Transmit FIFO under-run interrupt Disabled. | ||
| 1 = Transmit FIFO under-run interrupt Enabled. | ||
| [24:26] | RXTH | Receive FIFO Threshold |
| If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. | ||
| [28:30] | TXTH | Transmit FIFO Threshold |
| If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. |
Definition at line 22919 of file NUC472_442.h.
| __IO uint32_t UART_T::FIFOSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXOVIF | RX Overflow Error IF (Read Only) |
| This bit is set when RX FIFO overflow. | ||
| If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 64/16 bytes of UART0/UART1, this bit will be set. | ||
| Note: This bit is read only, but it can be cleared by writing '1' to it. | ||
| [2] | SCERR | Smart Card Over Error Retry Flag |
| It is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0])) | ||
| 0 = No any transmitter re-transmits over or receiver transfer error retry over. | ||
| 1 = one of the transmitter re-transmits over active or receiver transfer error retry over active. | ||
| Note1: This field is used for SC function mode. | ||
| Note2: This bit is read only, but it can be cleared by writing '1' to it. | ||
| [3] | ADDRDETF | RS-485 Address Byte Detection Flag (Read Only) |
| This bit is set to logic 1 and set RS-485_ADD_EN (UART_ALTCTL[15]) whenever in RS-485 mode the receiver detect any address byte received address byte character (bit9 = '1') bit, and it is reset whenever the CPU writes 1 to this bit. | ||
| Note1: This field is used for RS-485 function mode. | ||
| Note2: This bit is read only, but it can be cleared by writing '1' to it. | ||
| [4] | PEF | Parity Error Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit. | ||
| Note: This bit is read only, but it can be cleared by writing '1' to it. | ||
| [5] | FEF | Framing Error Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit. | ||
| Note: This bit is read only, but it can be cleared by writing '1' to it. | ||
| [6] | BIF | Break Interrupt Flag (Read Only) |
| This bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit. | ||
| Note: This bit is read only, but it can be cleared by writing '1' to it. | ||
| [8:13] | RXPTR | RX FIFO Pointer (Read Only) |
| This field indicates the RX FIFO Buffer Pointer. | ||
| When UART receives one byte from external device, RXPTR increases one. | ||
| When one byte of RX FIFO is read by CPU, RXPTR decreases one. | ||
| [14] | RXEMPTY | Receiver FIFO Empty (Read Only) |
| This bit initiate RX FIFO empty or not. | ||
| When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. | ||
| It will be cleared when UART receives any new data. | ||
| [15] | RXFULL | Receiver FIFO Full (Read Only) |
| This bit initiates RX FIFO full or not. | ||
| This bit is set when RXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware. | ||
| [16:21] | TXPTR | TX FIFO Pointer (Read Only) |
| This field indicates the TX FIFO Buffer Pointer. | ||
| When CPU writes one byte into UART_DAT, TXPTR increases one. | ||
| When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. | ||
| [22] | TXEMPTY | Transmitter FIFO Empty (Read Only) |
| This bit indicates TX FIFO empty or not. | ||
| When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. | ||
| It will be cleared when writing data into DAT (TX FIFO not empty). | ||
| [23] | TX_FULL | Transmitter FIFO Full (Read Only) |
| This bit indicates TX FIFO full or not. | ||
| This bit is set when TXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware. | ||
| [24] | TXOVIF | TX Overflow Error Interrupt Flag (Read Only) |
| If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to | ||
| logic 1. | ||
| Note: This bit is read only, but it can be cleared by writing '1' to it. | ||
| [28] | TXEMPTYF | Transmitter Empty Flag (Read Only) |
| Bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. | ||
| Bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. |
Definition at line 25425 of file NUC472_442.h.
| __IO uint32_t CAP_T::FIFOTH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PLNVFTH | Planar V FIFO Threshold |
| [8:11] | PLNUFTH | Planar U FIFO Threshold |
| [16:20] | PLNYFTH | Planar Y FIFO Threshold |
| [24:28] | PKTFTH | Packet FIFO Threshold |
| [31] | OVF | FIFO Overflow Flag |
Definition at line 2004 of file NUC472_442.h.
| __I uint32_t USBD_T::FRAMECNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:2] | MFRAMECNT | Micro-Frame Counter |
| This field contains the micro-frame number for the frame number in the frame counter field. | ||
| [3:13] | FRAMECNT | Frame Counter |
| This field contains the frame count from the most recent start-of-frame packet. |
Definition at line 27524 of file NUC472_442.h.
| __IO uint32_t CAP_T::FRCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | FRM | Scaling Frame Rate Factor M |
| Specify the denominator part (M) of the frame rate scaling factor. | ||
| The output image frame rate will be equal to input image frame rate * (N/M). | ||
| Note: The value of N must be equal to or less than M. | ||
| [8:13] | FRN | Scaling Frame Rate Factor N |
| Specify the denominator part (N) of the frame rate scaling factor. |
Definition at line 1971 of file NUC472_442.h.
| __IO uint32_t RTC_T::FREQADJ |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | FRACTION | Fraction Part |
| Formula = (fraction part of detected value) x 60. | ||
| Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number. | ||
| [8:11] | INTEGER | Integer Part |
Definition at line 20450 of file NUC472_442.h.
| __IO uint32_t EMAC_T::FRSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | RXFLT | Receive Frame LENGTH |
| The RXFLT keeps the LENGTH field of each incoming Ethernet packet. | ||
| If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt. | ||
| And, the content of LENGTH field will be stored in RXFLT. |
Definition at line 13045 of file NUC472_442.h.
| __IO uint32_t FMC_T::FTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [4:6] | FOM | Frequency Optimization Mode (Write Protect) |
| When chip operation frequency is lower, chip can work more efficiently by setting FOM bits | ||
| FOM[2:0] | ||
| Optimized Frequency (OF) | ||
| 001 | ||
| 0 MHz < OF <= 24 MHz | ||
| 010 | ||
| 24 MHz < OF <= 48 MHz | ||
| 011 | ||
| 48 MHz < OF <= 72 MHz | ||
| others | ||
| Reserved |
Definition at line 14717 of file NUC472_442.h.
| __IO uint32_t UART_T::FUNCSEL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:2] | FUNCSEL | Function Select Enable Control |
| 000 = UART function. | ||
| 001 = LIN function Enabled. | ||
| 010 = IrDA function Enabled. | ||
| 011 = RS-485 function Enabled. | ||
| 100 = Smart-Card function Enabled. |
Definition at line 25651 of file NUC472_442.h.
| __IO uint32_t SDH_T::GCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GCTLRST | Software Engine Reset |
| 0 = No effect. | ||
| 1 = Reset SD host. | ||
| The contents of control register will not be cleared. | ||
| This bit will auto cleared after reset complete. | ||
| [1] | SDEN | Secure Digital Functionality Enable Control |
| 0 = SD functionality disabled. | ||
| 1 = SD functionality enabled. |
Definition at line 22192 of file NUC472_442.h.
| __IO uint32_t EMAC_T::GENSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CFRIF | Control Frame Received |
| The CFRIF high indicates EMAC receives a flow control frame. | ||
| The CFRIF only available while EMAC is operating on full duplex mode. | ||
| 0 = The EMAC does not receive the flow control frame. | ||
| 1 = The EMAC receives a flow control frame. | ||
| [1] | RXHALT | Receive Halted |
| The RXHALT high indicates the next normal packet reception process will be halted because the bit RXON of MCMDR is disabled be S/W. | ||
| 0 = Next normal packet reception process will go on. | ||
| 1 = Next normal packet reception process will be halted. | ||
| [2] | RXFFULL | RXFIFO Full |
| The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO and the following incoming packet will be dropped. | ||
| 0 = The RXFIFO is not full. | ||
| 1 = The RXFIFO is full and the following incoming packet will be dropped. | ||
| [4:7] | COLCNT | Collision Count |
| The COLCNT indicates that how many collisions occurred consecutively during a packet transmission. | ||
| If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be 0 and bit TXABTIF will be set to 1. | ||
| [8] | DEF | Deferred Transmission |
| The DEF high indicates the packet transmission has deferred once. | ||
| The DEF is only available while EMAC is operating on half-duplex mode. | ||
| 0 = Packet transmission does not defer. | ||
| 1 = Packet transmission has deferred once. | ||
| [9] | TXPAUSED | Transmission Paused |
| The TXPAUSED high indicates the next normal packet transmission process will be paused temporally because EMAC received a PAUSE control frame. | ||
| 0 = Next normal packet transmission process will go on. | ||
| 1 = Next normal packet transmission process will be paused. | ||
| [10] | SQE | Signal Quality Error |
| The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode. | ||
| The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC is operating on 10Mbps half-duplex mode. | ||
| 0 = No SQE error found at end of packet transmission. | ||
| 1 = SQE error found at end of packet transmission. | ||
| [11] | TXHALT | Transmission Halted |
| The TXHALT high indicates the next normal packet transmission process will be halted because the bit TXON (EMAC_CTL[8]) is disabled be S/W. | ||
| 0 = Next normal packet transmission process will go on. | ||
| 1 = Next normal packet transmission process will be halted. | ||
| [12] | RPSTS | Remote Pause Status |
| The RPSTS indicates that remote pause counter down counting actives. | ||
| After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause counter down counting. | ||
| When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet transmission until the down counting done. | ||
| 0 = Remote pause counter down counting done. | ||
| 1 = Remote pause counter down counting actives. |
Definition at line 12998 of file NUC472_442.h.
| __IO uint32_t SDH_T::GINTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DTAIEN | DMA READ/WRITE Target Abort Interrupt Enable Control |
| 0 = DMA READ/WRITE target abort interrupt generation disabled. | ||
| 1 = DMA READ/WRITE target abort interrupt generation enabled. |
Definition at line 22205 of file NUC472_442.h.
| __IO uint32_t USBD_T::GINTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | USBIE | USB Interrupt Enable Control |
| When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus. | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [1] | CEPIE | Control Endpoint Interrupt Enable Control |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint. | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [2] | EPAIE | Interrupt Enable Control For Endpoint A |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A. | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [3] | EPBIE | Interrupt Enable Control For Endpoint B |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [4] | EPCIE | Interrupt Enable Control For Endpoint C |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [5] | EPDIE | Interrupt Enable Control For Endpoint D |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [6] | EPEIE | Interrupt Enable Control For Endpoint E |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [7] | EPFIE | Interrupt Enable Control For Endpoint F |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [8] | EPGIE | Interrupt Enable Control For Endpoint G |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [9] | EPHIE | Interrupt Enable Control For Endpoint H |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [10] | EPIIE | Interrupt Enable Control For Endpoint I |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [11] | EPJIE | Interrupt Enable Control For Endpoint J |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [12] | EPKIE | Interrupt Enable Control For Endpoint K |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. | ||
| [13] | EPLIE | Interrupt Enable Control For Endpoint L |
| When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L | ||
| 0 = The related interrupt Disabled. | ||
| 1 = The related interrupt Enabled. |
Definition at line 27397 of file NUC472_442.h.
| __I uint32_t SDH_T::GINTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DTAIF | DMA READ/WRITE Target Abort Interrupt Flag (Read Only) |
| This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation. | ||
| When Target Abort is occurred, please reset all engine. | ||
| 0 = No bus ERROR response received. | ||
| 1 = Bus ERROR response received. | ||
| Note: This bit is read only, but can be cleared by writing '1' to it. |
Definition at line 22221 of file NUC472_442.h.
| __I uint32_t USBD_T::GINTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | USBIF | USB Interrupt |
| This bit conveys the interrupt status for USB specific events endpoint. | ||
| When set, USB interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [1] | CEPIF | Control Endpoint Interrupt |
| This bit conveys the interrupt status for control endpoint. | ||
| When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [2] | EPAIF | Endpoints A Interrupt |
| When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [3] | EPBIF | Endpoints B Interrupt |
| When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [4] | EPCIF | Endpoints C Interrupt |
| When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [5] | EPDIF | Endpoints D Interrupt |
| When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [6] | EPEIF | Endpoints E Interrupt |
| When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [7] | EPFIF | Endpoints F Interrupt |
| When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [8] | EPGIF | Endpoints G Interrupt |
| When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [9] | EPHIF | Endpoints H Interrupt |
| When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [10] | EPIIF | Endpoints I Interrupt |
| When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [11] | EPJIF | Endpoints J Interrupt |
| When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [12] | EPKIF | Endpoints K Interrupt |
| When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. | ||
| [13] | EPLIF | Endpoints L Interrupt |
| When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. | ||
| 0 = No interrupt event occurred. | ||
| 1 = The related interrupt event is occurred. |
Definition at line 27327 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPA_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PA8MFP | PA.8 Multi-function Pin Selection |
| [4:7] | PA9MFP | PA.9 Multi-function Pin Selection |
| [8:11] | PA10MFP | PA.10 Multi-function Pin Selection |
| [12:15] | PA11MFP | PA.11 Multi-function Pin Selection |
| [16:19] | PA12MFP | PA.12 Multi-function Pin Selection |
| [20:23] | PA13MFP | PA.13 Multi-function Pin Selection |
| [24:27] | PA14MFP | PA.14 Multi-function Pin Selection |
| [28:31] | PA15MFP | PA.15 Multi-function Pin Selection |
Definition at line 23710 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPA_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PA0MFP | PA.0 Multi-function Pin Selection |
| [4:7] | PA1MFP | PA.1 Multi-function Pin Selection |
| [8:11] | PA2MFP | PA.2 Multi-function Pin Selection |
| [12:15] | PA3MFP | PA.3 Multi-function Pin Selection |
| [16:19] | PA4MFP | PA.4 Multi-function Pin Selection |
| [20:23] | PA5MFP | PA.5 Multi-function Pin Selection |
| [24:27] | PA6MFP | PA.6 Multi-function Pin Selection |
| [28:31] | PA7MFP | PA.7 Multi-function Pin Selection |
Definition at line 23692 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPB_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PB8MFP | PB.8 Multi-function Pin Selection |
| [4:7] | PB9MFP | PB.9 Multi-function Pin Selection |
| [8:11] | PB10MFP | PB.10 Multi-function Pin Selection |
| [12:15] | PB11MFP | PB.11 Multi-function Pin Selection |
| [16:19] | PB12MFP | PB.12 Multi-function Pin Selection |
| [20:23] | PB13MFP | PB.13 Multi-function Pin Selection |
| [24:27] | PB14MFP | PB.14 Multi-function Pin Selection |
| [28:31] | PB15MFP | PB.15 Multi-function Pin Selection |
Definition at line 23746 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPB_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PB0MFP | PB.0 Multi-function Pin Selection |
| [4:7] | PB1MFP | PB.1 Multi-function Pin Selection |
| [8:11] | PB2MFP | PB.2 Multi-function Pin Selection |
| [12:15] | PB3MFP | PB.3 Multi-function Pin Selection |
| [16:19] | PB4MFP | PB.4 Multi-function Pin Selection |
| [20:23] | PB5MFP | PB.5 Multi-function Pin Selection |
| [24:27] | PB6MFP | PB.6 Multi-function Pin Selection |
| [28:31] | PB7MFP | PB.7 Multi-function Pin Selection |
Definition at line 23728 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPC_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PC8MFP | PC.8 Multi-function Pin Selection |
| [4:7] | PC9MFP | PC.9 Multi-function Pin Selection |
| [8:11] | PC10MFP | PC.10 Multi-function Pin Selection |
| [12:15] | PC11MFP | PC.11 Multi-function Pin Selection |
| [16:19] | PC12MFP | PC.12 Multi-function Pin Selection |
| [20:23] | PC13MFP | PC.13 Multi-function Pin Selection |
| [24:27] | PC14MFP | PC.14 Multi-function Pin Selection |
| [28:31] | PC15MFP | PC.15 Multi-function Pin Selection |
Definition at line 23782 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPC_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PC0MFP | PC.0 Multi-function Pin Selection |
| [4:7] | PC1MFP | PC.1 Multi-function Pin Selection |
| [8:11] | PC2MFP | PC.2 Multi-function Pin Selection |
| [12:15] | PC3MFP | PC.3 Multi-function Pin Selection |
| [16:19] | PC4MFP | PC.4 Multi-function Pin Selection |
| [20:23] | PC5MFP | PC.5 Multi-function Pin Selection |
| [24:27] | PC6MFP | PC.6 Multi-function Pin Selection |
| [28:31] | PC7MFP | PC.7 Multi-function Pin Selection |
Definition at line 23764 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPD_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PD8MFP | PD.8 Multi-function Pin Selection |
| [4:7] | PD9MFP | PD.9 Multi-function Pin Selection |
| [8:11] | PD10MFP | PD.10 Multi-function Pin Selection |
| [12:15] | PD11MFP | PD.11 Multi-function Pin Selection |
| [16:19] | PD12MFP | PD.12 Multi-function Pin Selection |
| [20:23] | PD13MFP | PD.13 Multi-function Pin Selection |
| [24:27] | PD14MFP | PD.14 Multi-function Pin Selection |
| [28:31] | PD15MFP | PD.15 Multi-function Pin Selection |
Definition at line 23818 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPD_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PD0MFP | PD.0 Multi-function Pin Selection |
| [4:7] | PD1MFP | PD.1 Multi-function Pin Selection |
| [8:11] | PD2MFP | PD.2 Multi-function Pin Selection |
| [12:15] | PD3MFP | PD.3 Multi-function Pin Selection |
| [16:19] | PD4MFP | PD.4 Multi-function Pin Selection |
| [20:23] | PD5MFP | PD.5 Multi-function Pin Selection |
| [24:27] | PD6MFP | PD.6 Multi-function Pin Selection |
| [28:31] | PD7MFP | PD.7 Multi-function Pin Selection |
Definition at line 23800 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPE_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PE8MFP | PE.8 Multi-function Pin Selection |
| [4:7] | PE9MFP | PE.9 Multi-function Pin Selection |
| [8:11] | PE10MFP | PE.10 Multi-function Pin Selection |
| [12:15] | PE11MFP | PE.11 Multi-function Pin Selection |
| [16:19] | PE12MFP | PE.12 Multi-function Pin Selection |
| [20:23] | PE13MFP | PE.13 Multi-function Pin Selection |
| [24:27] | PE14MFP | PE.14 Multi-function Pin Selection |
| [28:31] | PE15MFP | PE.15 Multi-function Pin Selection |
Definition at line 23854 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPE_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PE0MFP | PE.0 Multi-function Pin Selection |
| [4:7] | PE1MFP | PE.1 Multi-function Pin Selection |
| [8:11] | PE2MFP | PE.2 Multi-function Pin Selection |
| [12:15] | PE3MFP | PE.3 Multi-function Pin Selection |
| [16:19] | PE4MFP | PE.4 Multi-function Pin Selection |
| [20:23] | PE5MFP | PE.5 Multi-function Pin Selection |
| [24:27] | PE6MFP | PE.6 Multi-function Pin Selection |
| [28:31] | PE7MFP | PE.7 Multi-function Pin Selection |
Definition at line 23836 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPF_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PF8MFP | PF.8 Multi-function Pin Selection |
| [4:7] | PF9MFP | PF.9 Multi-function Pin Selection |
| [8:11] | PF10MFP | PF.10 Multi-function Pin Selection |
| [12:15] | PF11MFP | PF.11 Multi-function Pin Selection |
| [16:19] | PF12MFP | PF.12 Multi-function Pin Selection |
| [20:23] | PF13MFP | PF.13 Multi-function Pin Selection |
| [24:27] | PF14MFP | PF.14 Multi-function Pin Selection |
| [28:31] | PF15MFP | PF.15 Multi-function Pin Selection |
Definition at line 23890 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPF_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PF0MFP | PF.0 Multi-function Pin Selection |
| [4:7] | PF1MFP | PF.1 Multi-function Pin Selection |
| [8:11] | PF2MFP | PF.2 Multi-function Pin Selection |
| [12:15] | PF3MFP | PF.3 Multi-function Pin Selection |
| [16:19] | PF4MFP | PF.4 Multi-function Pin Selection |
| [20:23] | PF5MFP | PF.5 Multi-function Pin Selection |
| [24:27] | PF6MFP | PF.6 Multi-function Pin Selection |
| [28:31] | PF7MFP | PF.7 Multi-function Pin Selection |
Definition at line 23872 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPG_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PG8MFP | PG.8 Multi-function Pin Selection |
| [4:7] | PG9MFP | PG.9 Multi-function Pin Selection |
| [8:11] | PG10MFP | PG.10 Multi-function Pin Selection |
| [12:15] | PG11MFP | PG.11 Multi-function Pin Selection |
| [16:19] | PG12MFP | PG.12 Multi-function Pin Selection |
| [20:23] | PG13MFP | PG.13 Multi-function Pin Selection |
| [24:27] | PG14MFP | PG.14 Multi-function Pin Selection |
| [28:31] | PG15MFP | PG.15 Multi-function Pin Selection |
Definition at line 23926 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPG_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PG0MFP | PG.0 Multi-function Pin Selection |
| [4:7] | PG1MFP | PG.1 Multi-function Pin Selection |
| [8:11] | PG2MFP | PG.2 Multi-function Pin Selection |
| [12:15] | PG3MFP | PG.3 Multi-function Pin Selection |
| [16:19] | PG4MFP | PG.4 Multi-function Pin Selection |
| [20:23] | PG5MFP | PG.5 Multi-function Pin Selection |
| [24:27] | PG6MFP | PG.6 Multi-function Pin Selection |
| [28:31] | PG7MFP | PG.7 Multi-function Pin Selection |
Definition at line 23908 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPH_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PH8MFP | PH.8 Multi-function Pin Selection |
| [4:7] | PH9MFP | PH.9 Multi-function Pin Selection |
| [8:11] | PH10MFP | PH.10 Multi-function Pin Selection |
| [12:15] | PH11MFP | PH.11 Multi-function Pin Selection |
| [16:19] | PH12MFP | PH.12 Multi-function Pin Selection |
| [20:23] | PH13MFP | PH.13 Multi-function Pin Selection |
| [24:27] | PH14MFP | PH.14 Multi-function Pin Selection |
| [28:31] | PH15MFP | PH.15 Multi-function Pin Selection |
Definition at line 23962 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPH_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PH0MFP | PH.0 Multi-function Pin Selection |
| [4:7] | PH1MFP | PH.1 Multi-function Pin Selection |
| [8:11] | PH2MFP | PH.2 Multi-function Pin Selection |
| [12:15] | PH3MFP | PH.3 Multi-function Pin Selection |
| [16:19] | PH4MFP | PH.4 Multi-function Pin Selection |
| [20:23] | PH5MFP | PH.5 Multi-function Pin Selection |
| [24:27] | PH6MFP | PH.6 Multi-function Pin Selection |
| [28:31] | PH7MFP | PH.7 Multi-function Pin Selection |
Definition at line 23944 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPI_MFPH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PI8MFP | PI.8 Multi-function Pin Selection |
| [4:7] | PI9MFP | PI.9 Multi-function Pin Selection |
| [8:11] | PI10MFP | PI.10 Multi-function Pin Selection |
| [12:15] | PI11MFP | PI.11 Multi-function Pin Selection |
| [16:19] | PI12MFP | PI.12 Multi-function Pin Selection |
| [20:23] | PI13MFP | PI.13 Multi-function Pin Selection |
| [24:27] | PI14MFP | PI.14 Multi-function Pin Selection |
| [28:31] | PI15MFP | PI.15 Multi-function Pin Selection |
Definition at line 23998 of file NUC472_442.h.
| __IO uint32_t SYS_T::GPI_MFPL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PI0MFP | PI.0 Multi-function Pin Selection |
| [4:7] | PI1MFP | PI.1 Multi-function Pin Selection |
| [8:11] | PI2MFP | PI.2 Multi-function Pin Selection |
| [12:15] | PI3MFP | PI.3 Multi-function Pin Selection |
| [16:19] | PI4MFP | PI.4 Multi-function Pin Selection |
| [20:23] | PI5MFP | PI.5 Multi-function Pin Selection |
| [24:27] | PI6MFP | PI.6 Multi-function Pin Selection |
| [28:31] | PI7MFP | PI.7 Multi-function Pin Selection |
Definition at line 23980 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcBulkCurrentED |
| Bits | Field | Descriptions |
|---|---|---|
| [4:31] | BCED | Bulk Current Head ED |
| Pointer to the current Bulk List Head ED. |
Definition at line 26383 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcBulkHeadED |
| Bits | Field | Descriptions |
|---|---|---|
| [4:31] | BHED | Bulk Head ED |
| Pointer to the Bulk List Head ED. |
Definition at line 26371 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcCommandStatus |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HCR | Host Controller Reset |
| This bit is set to initiate the software reset. | ||
| This bit is cleared by the Host Controller, upon completed of the reset operation. | ||
| [1] | CLF | Control List Filled |
| Set to indicate there is an active ED on the Control List. | ||
| It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. | ||
| [2] | BLF | Bulk List Filled |
| Set to indicate there is an active ED on the Bulk List. | ||
| The bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk List. | ||
| [16:17] | SOC | Schedule Overrun Count |
| This field is incremented every time the SchedulingOverrun bit in HcInterruptStatus is set. | ||
| The count wraps from '11' to '00'. |
Definition at line 26222 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcControl |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | CBSR | Control Bulk Service Ratio |
| Specifies the number of Control Endpoints serviced for every Bulk Endpoint. | ||
| Encoding is N-1 where N is the number of Control Endpoints (i.e. | ||
| '00' = 1 Control Endpoint; '11' = 3 Control Endpoints). | ||
| [2] | PLE | Periodic List Enable Control |
| When set, this bit enables processing of the Periodic (interrupt and isochronous) list. | ||
| The Host Controller checks this bit prior to attempting any periodic transfers in a frame. | ||
| [3] | IE | Isochronous List Enable Control |
| When cleared, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs may be serviced). | ||
| While processing the Periodic List, the Host Controller will check this bit when it finds an isochronous ED. | ||
| [4] | CLE | Control List Enable Control |
| When set, this bit enables processing of the Control list. | ||
| [5] | BLE | Bulk List Enable Control |
| When set, this bit enables processing of the Bulk list. | ||
| [6:7] | HCFS | Host Controller Functional State |
| This field sets the Host Controller state. | ||
| The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port. | ||
| States are:. | ||
| 00 = USBSUSPEND. | ||
| 01 = USBRESUME. | ||
| 10 = USBOPERATIONAL. | ||
| 11 = USBRESET. | ||
| [9] | RWC | Remote Wake-Up Connected |
| This bit indicated whether the HC supports a remote wake-up signal. | ||
| This implementation does not support any such signal. | ||
| The bit is hard-coded to '0.'. | ||
| [10] | RWE | Remote Wake-Up Connected Enable Control |
| If a remote wake-up signal is supported, this bit enables that operation. | ||
| Since there is no remote wake-up signal supported, this bit is ignored. |
Definition at line 26200 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcControlCurrentED |
| Bits | Field | Descriptions |
|---|---|---|
| [4:31] | CCED | Control Current Head ED |
| Pointer to the current Control List Head ED. |
Definition at line 26359 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcControlHeadED |
| Bits | Field | Descriptions |
|---|---|---|
| [4:31] | CHED | Control Head ED |
| Pointer to the Control List Head ED. |
Definition at line 26347 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcDoneHead |
| Bits | Field | Descriptions |
|---|---|---|
| [4:31] | DH | Done Head |
| Pointer to the current Done List Head ED. |
Definition at line 26395 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcFmInterval |
| Bits | Field | Descriptions |
|---|---|---|
| [0:13] | FI | Frame Interval |
| This field specifies the length of a frame as (bit times - 1). | ||
| For 12,000 bit times in a frame, a value of 11,999 is stored here. | ||
| [16:30] | FSMPS | FS Largest Data Packet |
| This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. | ||
| [31] | FIT | Frame Interval Toggle |
| This bit is toggled by HCD when it loads a new value into Frame Interval. |
Definition at line 26412 of file NUC472_442.h.
| __I uint32_t USBH_T::HcFmNumber |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | FN | Frame Number |
| This 16-bit incrementing counter field is incremented coincident with the loading of FrameRemaining. | ||
| The count rolls over from 'FFFFh' to '0h.'. |
Definition at line 26441 of file NUC472_442.h.
| __I uint32_t USBH_T::HcFmRemaining |
| Bits | Field | Descriptions |
|---|---|---|
| [0:13] | FR | Frame Remaining |
| When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period. | ||
| When the count reaches 0, (end of frame) the counter reloads with Frame Interval. | ||
| In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. | ||
| [31] | FRT | Frame Remaining Toggle |
| Loaded with Frame Interval Toggle when FrameRemaining is loaded. |
Definition at line 26428 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcHCCA |
| Bits | Field | Descriptions |
|---|---|---|
| [8:31] | HCCA | Host Controller Communication Area |
| Pointer to HCCA base address. |
Definition at line 26323 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcInterruptDisable |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SO | Scheduling Overrun Disable Control |
| 0 = No effect. | ||
| 1 = Interrupt generation Disabled due to Scheduling Overrun. | ||
| [1] | WDH | Write Back Done Head Disable Control |
| 0 = No effect. | ||
| 1 = Interrupt generation Disabled due to Write-back Done Head. | ||
| [2] | SF | Start Of Frame Disable Control |
| 0 = No effect. | ||
| 1 = Interrupt generation Disabled due to Start of Frame. | ||
| [3] | RD | Resume Detected Disable Control |
| 0 = No effect. | ||
| 1 = Interrupt generation Disabled due to Resume Detected. | ||
| [4] | UE | Unrecoverable Error Disable Control |
| This event is not implemented. All writes to this bit are ignored. | ||
| [5] | FNO | Frame Number Overflow Disable Control |
| 0 = No effect. | ||
| 1 = Interrupt generation Disabled due to Frame Number Overflow. | ||
| [6] | RHSC | Root Hub Status Change Disable Control |
| 0 = No effect. | ||
| 1 = Interrupt generation Disabled due to Root Hub Status Change. | ||
| [31] | MIE | Master Interrupt Disable Control |
| Global interrupt disable. Writing '1' to disable all interrupts. |
Definition at line 26311 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcInterruptEnable |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SO | Scheduling Overrun Enable Control |
| 0 = The interrupt function Disabled. | ||
| 1 = Interrupt generation Enabled due to Scheduling Overrun. | ||
| [1] | WDH | Write Back Done Head Enable Control |
| 0 = The interrupt function Disabled. | ||
| 1 = Interrupt generation Enabled due to Write-back Done Head. | ||
| [2] | SF | Start Of Frame Enable Control |
| 0 = The interrupt function Disabled. | ||
| 1 = interrupt generation Enabled due to Start of Frame. | ||
| [3] | RD | Resume Detected Enable Control |
| 0 = The interrupt function Disabled. | ||
| 1 = interrupt generation Enabled due to Resume Detected. | ||
| [4] | UE | Unrecoverable Error Enable Control |
| This event is not implemented. All writes to this bit are ignored. | ||
| [5] | FNO | Frame Number Overflow Enable Control |
| 0 = The interrupt function Disabled. | ||
| 1 = Interrupt generation Enabled due to Frame Number Overflow. | ||
| [6] | RHSC | Root Hub Status Change Enable Control |
| 0 = The interrupt function Disabled. | ||
| 1 = interrupt generation Enabled due to Root Hub Status Change. | ||
| [31] | MIE | Master Interrupt Enable Control |
| This bit is a global interrupt enable. | ||
| A write of '1' allows interrupts to be enabled via the specific enable bits listed above. |
Definition at line 26279 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcInterruptStatus |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SO | Scheduling Overrun |
| Set when the List Processor determines a Schedule Overrun has occurred. | ||
| [1] | WDH | Write Back Done Head |
| Set after the Host Controller has written HcDoneHead to HccaDoneHead. | ||
| [2] | SF | Start Of Frame |
| Set when the Frame Management block signals a 'Start of Frame' event. | ||
| [3] | RD | Resume Detected |
| Set when Host Controller detects resume signaling on a downstream port. | ||
| [4] | UE | Unrecoverable Error |
| This event is not implemented and is hard-coded to '0.' Writes are ignored. | ||
| [5] | FNOF | Frame Number Overflow |
| Set when bit 15 of Frame Number changes value. | ||
| [6] | RHSC | Root Hub Status Change |
| This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has changed. |
Definition at line 26246 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcLSThreshold |
| Bits | Field | Descriptions |
|---|---|---|
| [0:11] | LST | Low-Speed Threshold |
| This field contains a value which is compared to the FrameRemaining field prior to initiating a Low-speed transaction. | ||
| The transaction is started only if FrameRemaining >= this field. | ||
| The value is calculated by HCD with the consideration of transmission and setup overhead. |
Definition at line 26467 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcMiscControl |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DBR16 | Data Buffer Region 16 |
| When set, the size of the data buffer region is 16 bytes. Otherwise, the size is 32 bytes. | ||
| [1] | ABORT | AHB Bus ERROR Response |
| This bit indicates there is an ERROR response received in AHB bus. | ||
| 0 = No ERROR response received. | ||
| 1 = ERROR response received. | ||
| [3] | OCA | Overcurrent Active Low |
| This bit controls the polarity of overcurrent flag from external power IC. | ||
| 0 = Overcurrent flag is high active. | ||
| 1 = Overcurrent flag is low active. | ||
| [4] | PCAL | Port Power Control Active Low |
| This bit controls the polarity of port power control to external power IC. | ||
| 0 = Port power control is high active. | ||
| 1 = Port power control is low active. | ||
| [8] | SIEPD | SIE Pipeline Disable Control |
| When set, waits for all USB bus activity to complete prior to returning completion status to the List Processor. | ||
| This is a fail safe mechanism to avoid potential problems with the clk_dr transition between 1.5 MHz and 12 MHz. | ||
| [16] | DPRT1 | Port 1 Disable Control |
| This bit controls if the connection between USB host controller and transceiver of port 1 is disabled. | ||
| If the connection is disabled, the USB host controller will not recognize any event of USB bus. | ||
| Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. | ||
| 0 = The connection between USB host controller and transceiver of port 1 is enabled. | ||
| 1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode. | ||
| [17] | DPRT2 | Port 2 Disable Control |
| This bit controls if the connection between USB host controller and transceiver of port 2 is disabled. | ||
| If the connection is disabled, the USB host controller will not recognize any event of USB bus. | ||
| Set this bit high, the transceiver of port 2 will also be forced into the standby mode no matter what USB host controller operation is. | ||
| 0 = The connection between USB host controller and transceiver of port 2 is enabled. | ||
| 1 = The connection between USB host controller and transceiver of port 2 is disabled and the transceiver of port 2 will also be forced into the standby mode. |
Definition at line 26691 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcPeriodCurrentED |
| Bits | Field | Descriptions |
|---|---|---|
| [4:31] | PCED | Periodic Current ED |
| Pointer to the current Periodic List ED. |
Definition at line 26335 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcPeriodicStart |
| Bits | Field | Descriptions |
|---|---|---|
| [0:13] | PS | Periodic Start |
| This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. |
Definition at line 26453 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcPhyControl |
| Bits | Field | Descriptions |
|---|---|---|
| [27] | STBYEN | USB Transceiver Standby Enable Control |
| This bit controls if USB 1.1 transceiver could enter the standby mode to reduce power consumption. | ||
| If this bit is low, the USB 1.1 transceiver would never enter the standby mode. | ||
| If this bit is high, the USB 1.1 transceiver will enter standby mode while port is in power off state (port power is inactive). |
Definition at line 26652 of file NUC472_442.h.
| __I uint32_t USBH_T::HcRevision |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | REV | Revision |
| Indicates the Open HCI Specification revision number implemented by the Hardware. | ||
| Host Controller supports 1.1 specification. | ||
| (X.Y = XYh). |
Definition at line 26161 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcRhDescriptorA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | NDP | Number Downstream Ports |
| Root Hub supports two downstream ports. It's 2 in this Root Hub. | ||
| [8] | PSM | Power Switching Mode |
| Global power switching mode implemented in Root Hub. | ||
| This bit is only valid when NPS bit is cleared. | ||
| This bit should be written '0'. | ||
| 0 = Global Switching. | ||
| 1 = Individual Switching. | ||
| [9] | NPS | No Power Switching |
| Global power switching implemented in Root Hub. | ||
| This bit should be written to support the external system port power switching implementation. | ||
| 0 = Ports are power switched. | ||
| 1 = Ports are always powered on. | ||
| [10] | DT | Device Type |
| The OHCI Root Hub is not a compound device. | ||
| [11] | OCPM | Overcurrent Protection Mode |
| Global overcurrent reporting implemented in Root Hub. | ||
| This bit should be written 0 and is only valid when NOCP bit is cleared. | ||
| 0 = Global Overcurrent. | ||
| 1 = Individual Overcurrent. | ||
| [12] | NOCP | No Overcurrent Protection |
| Global overcurrent reporting implemented in Root Hub. | ||
| This bit should be written to support the external system port overcurrent implementation. | ||
| 0 = Overcurrent status is reported. | ||
| 1 = Overcurrent status is not reported. | ||
| [24:31] | POTGT | Power On To Power Good Time |
| This field value is represented as the number of 2 ms intervals, which ensuring that the power switching is effective within 2 ms. | ||
| Only bits [25:24] are implemented as R/W. | ||
| The remaining bits are read only as '0'. | ||
| It is not expected that these bits be written to anything other than 1h, but limited adjustment is provided. | ||
| This field should be written to support system implementation. | ||
| This field should always be written to a non-zero value. |
Definition at line 26509 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcRhDescriptorB |
| Bits | Field | Descriptions |
|---|---|---|
| [0:2] | DR | Device Removable |
| Root Hub ports default to removable devices. | ||
| 0 = Device not removable. | ||
| 1 = Device removable. | ||
| Port Bit relationship: | ||
| DevRemove[0] = Reserved. | ||
| DevRemove[1] = Port 1. | ||
| DevRemove[2] = Port 2. |
Definition at line 26527 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcRhPortStatus[2] |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CCS | Current Connect Status (Read) |
| 0 = No device connected. | ||
| 1 = Device connected. | ||
| Clear Port Enable Control (Write) | ||
| Writing '1' a clears PE. Writing '0' has no effect. | ||
| [1] | PES | Port Enable Status (Read) |
| 0 = Port Disabled. | ||
| 1 = Port Enabled. | ||
| SetPortEnable (Write) | ||
| Writing '1' sets PE. Writing '0' has no effect. | ||
| [2] | PSS | PortSuspendStatus (Read) |
| 0 = Port is not suspended. | ||
| 1 = Port is selectively suspended. | ||
| SetPortSuspend (Write) | ||
| Writing '1' sets PortSuspendStatus. Writing '0' has no effect. | ||
| [3] | POCI | PortOverCurrentIndicator (Read) |
| Root Hub supports global overcurrent reporting. | ||
| This bit reflects the state of the OVRCUR pin dedicated to this port. | ||
| This field is only valid if NOCP (RHDESA[12]) is cleared and OCPM (RHDESA[11]) is set. | ||
| 0 = No overcurrent condition. | ||
| 1 = Overcurrent condition. | ||
| ClearPortSuspend (Write) | ||
| Writing '1' initiates the selective resume sequence for the port. Writing '0' has no effect. | ||
| [4] | PRS | PortResetStatus (Read) |
| This bit reflects the power state of the port regardless of the power switching mode. | ||
| 0 = Port reset signal is not active. | ||
| 1 = Port reset signal is active. | ||
| SetPortReset (Write) | ||
| Writing '1' sets PR. Writing '0' has no effect. | ||
| [8] | PPS | PortPowerStatus (Read) |
| This bit reflects the power state of the port regardless of the power switching mode. | ||
| 0 = Port power is off. | ||
| 1 = Port power is on. | ||
| Note: If NPS (RHDESA[9]) is set, this bit is always read as '1'. | ||
| SetPortPower (Write) | ||
| Writing '1' sets PPS. Writing '0' has no effect. | ||
| [9] | LSDA | LowSpeedDeviceAttached (Read) |
| This bit defines the speed (and bud idle) of the attached device. It is only valid when CC bit is set. | ||
| 0 = Full Speed device. | ||
| 1 = Low-speed device. | ||
| ClearPortPower (Write) | ||
| Writing '1' clears PPS bit. Writing '0' has no effect. | ||
| [16] | CSC | Connect Status Change |
| This bit indicates connect or disconnect event has been detected. | ||
| Writing '1' clears this bit. | ||
| Writing '0' has no effect. | ||
| 0 = No connect/disconnect event. | ||
| 1 = Hardware detection of connect/disconnect event. | ||
| Note: If DevRemove (HcRhDescriptorB[2:0]) is set, this bit resets to '1'. | ||
| [17] | PESC | Port Enable Status Change |
| This bit indicates that the port has been disabled due to a hardware event (cleared PE bit). | ||
| 0 = No port enable change event. | ||
| 1 = Port enable state has been changed. | ||
| [18] | PSSC | Port Reset Status Change |
| This bit indicates the completion of the selective resume sequence for the port. | ||
| 0 = Port is not resumed. | ||
| 1 = Port resume is complete. | ||
| [19] | OCIC | Port Overcurrent Indicator Change |
| This bit is set when OC (HcRhStatus[1]) changes. Writing '1' clears this bit. Writing '0' has no effect. | ||
| [20] | PRSC | Port Reset Status Change |
| This bit indicates that the port reset signal has completed. | ||
| 0 = Port reset is not complete. | ||
| 1 = Port reset is complete. |
Definition at line 26634 of file NUC472_442.h.
| __IO uint32_t USBH_T::HcRhStatus |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | LPS | LocalPowerStatus (Read) |
| Not Supported. Always read '0'. | ||
| ClearGlobalPower (Write) | ||
| Writing '1' issues a ClearGlobalPower command to the ports. Writing '0' has no effect. | ||
| [1] | OCI | Overcurrent Indicator |
| This bit reflects the state of the OVRCUR pin. | ||
| This field is only valid if NOCP (RHDESA[12]) and OCPM (RHDESA[11]) are cleared. | ||
| 0 = No overcurrent condition. | ||
| 1 = Overcurrent condition. | ||
| [15] | DRWE | Device Remote Wake-Up Enable Control (Read) |
| This bit enables ports' CC (HcRhPtr[0]) as a remote wake-up event. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Set Remote Wake-up Enable Control (Write) | ||
| Writing 1' sets DRWEn. Writing '0' has no effect. | ||
| [16] | LPSC | Local Power Status Change (Read) |
| Not supported. Always read '0'. | ||
| SetGlobalPower (Write) | ||
| Writing '1' issues a SetGlobalPower command to the ports. Writing '0' has no effect. | ||
| [17] | OCIC | Overcurrent Indicator Change |
| This bit is set when OC bit changes. | ||
| Writing '1' clears this bit. Writing '0' has no effect. | ||
| [31] | CRWE | Clear Remote Wake-Up Enable Control |
| Writing '1' to this bit clears DRWEn (HcRhStatus[15]). Writing '0' has no effect. |
Definition at line 26561 of file NUC472_442.h.
| __IO uint32_t ECAP_T::HOLD0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:23] | VAL | Input Capture Counter Hold Register |
| When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register. | ||
| Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. |
Definition at line 2449 of file NUC472_442.h.
| __IO uint32_t ECAP_T::HOLD1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:23] | VAL | Input Capture Counter Hold Register |
| When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register. | ||
| Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. |
Definition at line 2462 of file NUC472_442.h.
| __IO uint32_t ECAP_T::HOLD2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:23] | VAL | Input Capture Counter Hold Register |
| When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register. | ||
| Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. |
Definition at line 2475 of file NUC472_442.h.
| __IO uint32_t I2S_T::IEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXUDIEN | Receive FIFO Underflow Interrupt E Enable Control |
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| Note: If software reads receive FIFO when it is empty then RXUDIF(I2S_STATUS[8]) flag is set to 1. | ||
| [1] | RXOVIEN | Receive FIFO Overflow Interrupt Enable Control |
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| Note: Interrupt occurs if this bit is set to 1 and RXOVIEN(I2S_STATUS[9]) flag is set to 1 | ||
| [2] | RXTHIEN | Receive FIFO Threshold Level Interrupt Enable Control |
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| Note: When data word in receive FIFO is equal or higher than RXTH(I2S_CTL[14:12]) and the RXTHF bit is set to 1. | ||
| If RXTHIEN bit is enabled, interrupt occur. | ||
| [8] | TXUDIEN | Transmit FIFO Underflow Interrupt Enable Control |
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| Note: Interrupt occur if this bit is set to 1 and TXUDIEN(I2S_STATUS[16]) flag is set to 1. | ||
| [9] | TXOVIEN | Transmit FIFO Overflow Interrupt Enable Control |
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| Note: Interrupt occurs if this bit is set to 1 and TXOVIEN(I2S_STATUS[17]) flag is set to 1 | ||
| [10] | TXTHIEN | Transmit FIFO Threshold Level Interrupt Enable Control |
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH(I2S_CTL[11:9]). | ||
| [11] | RZCIEN | Right Channel Zero-Cross Interrupt Enable Control |
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| Note: Interrupt occurs if this bit is set to 1 and right channel zero-cross | ||
| [12] | LZCIEN | Left Channel Zero-Cross Interrupt Enable Control |
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| Note: Interrupt occurs if this bit is set to 1 and left channel zero-cross |
Definition at line 17345 of file NUC472_442.h.
| __IO CAN_IF_T CAN_T::IF[2] |
Definition at line 1295 of file NUC472_442.h.
| __IO uint32_t CAN_T::IIDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | IntId | Interrupt Identifier (Indicates The Source Of The Interrupt) |
| If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. | ||
| An interrupt remains pending until the application software has cleared it. | ||
| If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active. | ||
| The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset. | ||
| The Status Interrupt has the highest priority. | ||
| Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number. | ||
| A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]). | ||
| The Status Interrupt is cleared by reading the Status Register. |
Definition at line 1248 of file NUC472_442.h.
| __IO uint32_t RTC_T::INIT |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | INIT_Active | RTC Active Status (Read Only) |
| 0 = RTC is at reset state. | ||
| 1 = RTC is at normal active state. | ||
| [1:31] | INIT | RTC Initiation |
| When RTC block is powered on, RTC is at reset state. | ||
| User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state. | ||
| Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. | ||
| The INIT is a write-only field and read value will be always "0". |
Definition at line 20420 of file NUC472_442.h.
| __IO uint32_t CAP_T::INT |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | VINTF | Video Frame End Interrupt |
| If this bit shows 1, receiving a frame completed. | ||
| Write 1 to clear it. | ||
| [1] | MEINTF | Bus Master Transfer Error Interrupt |
| If this bit shows 1, Transfer Error occurred. Write 1 to clear it. | ||
| [3] | ADDRMINTF | Memory Address Match Interrupt |
| If this bit shows 1, Memory Address Match Interrupt occurred. | ||
| Write 1 to clear it. | ||
| [4] | MDINTF | Motion Detection Output Finish Interrupt |
| If this bit shows 1, Motion Detection Output Finish Interrupt occurred. | ||
| Write 1 to clear it. | ||
| [16] | VIEN | Video Frame End Interrupt Enable |
| 0 = Video frame end interrupt Disabled. | ||
| 1 = Video frame end interrupt Enabled. | ||
| [17] | MEIEN | System Memory Error Interrupt Enable |
| 0 = System memory error interrupt Disabled. | ||
| 1 = System memory error interrupt Enabled. | ||
| [19] | ADDRMIEN | Address Match Interrupt Enable |
| 0 = Address match interrupt Disabled. | ||
| 1 = Address match interrupt Enabled. | ||
| [20] | MDIEN | Motion Detection Output Finish Interrupt Enable |
| 0 = CAP_MD finish interrupt Disabled. | ||
| 1 = CAP_MD finish interrupt Enabled. |
Definition at line 1804 of file NUC472_442.h.
| __IO uint32_t PWM_T::INTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | PINTTYPE | PWM Period Interrupt Type Selection |
| 0 = PIF[n] will be set if PWM counter underflow. | ||
| 1 = PIF[n] will be set if PWM counter matches PWM_PERIODn register. | ||
| Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type. | ||
| Note2: Each bit controls the corresponding PWM channel. | ||
| [8:13] | DINTTYPE | PWM Duty Interrupt Type Selection |
| 0 = DIF[n] will be set if PWM counter matches PWM_CMPDATn register during down counting. | ||
| 1 = DIF[n] will be set if PWM counter matches PWM_CMPDATn register during up counting. | ||
| Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type. | ||
| Note2: Each bit controls the corresponding PWM channel. |
Definition at line 19431 of file NUC472_442.h.
| __IO uint32_t CRPT_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | AESIEN | AES Interrupt Enable Control |
| 0 = AES interrupt Disabled. | ||
| 1 = AES interrupt Enabled. | ||
| In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. | ||
| In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. | ||
| [1] | AESERRIEN | AES Error Flag Enable Control |
| 0 = AES error interrupt flag Disabled. | ||
| 1 = AES error interrupt flag Enabled. | ||
| [8] | TDESIEN | TDES/DES Interrupt Enable Control |
| 0 = TDES/DES interrupt Disabled. | ||
| 1 = TDES/DES interrupt Enabled. | ||
| In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine. | ||
| In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation. | ||
| [9] | TDESERRIEN | TDES/DES Error Flag Enable Control |
| 0 = TDES/DES error interrupt flag Disabled. | ||
| 1 = TDES/DES error interrupt flag Enabled. | ||
| [16] | PRNGIEN | PRNG Interrupt Enable Control |
| 0 = PRNG interrupt Disabled. | ||
| 1 = PRNG interrupt Enabled. | ||
| [24] | SHAIEN | SHA Interrupt Enable Control |
| 0 = SHA interrupt Disabled. | ||
| 1 = SHA interrupt Enabled. | ||
| In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine. | ||
| In Non-DMA mode, an interrupt will be triggered when the SHA engine finishes the operation. | ||
| [25] | SHAERRIEN | SHA Error Interrupt Enable Control |
| 0 = SHA error interrupt flag Disabled. | ||
| 1 = SHA error interrupt flag Enabled. |
Definition at line 4159 of file NUC472_442.h.
| __IO uint32_t EMAC_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXIEN | Receive Interrupt Enable Control |
| The RXIEN controls the RX interrupt generation. | ||
| If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU. | ||
| If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1] is set and the corresponding bit of EMAC_INTEN is enabled. | ||
| In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled. | ||
| And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit. | ||
| 0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled. | ||
| 1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled. | ||
| [1] | CRCEIEN | CRC Error Interrupt Enable Control |
| The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation. | ||
| If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CRCEIF (EMAC_INTSTS[1]) is set. | ||
| 0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled. | ||
| 1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled. | ||
| [2] | RXOVIEN | Receive FIFO Overflow Interrupt Enable Control |
| The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation. | ||
| If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXOVIF (EMAC_INTSTS[2]) is set. | ||
| 0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled. | ||
| 1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled. | ||
| [3] | LPIEN | Long Packet Interrupt Enable |
| The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation. | ||
| If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF (EMAC_INTSTS[3]) is set. | ||
| 0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled. | ||
| 1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled. | ||
| [4] | RXGDIEN | Receive Good Interrupt Enable Control |
| The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation. | ||
| If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXGDIF (EMAC_INTSTS[4]) is set. | ||
| 0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled. | ||
| 1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled. | ||
| [5] | ALIEIEN | Alignment Error Interrupt Enable Control |
| The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation. | ||
| If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the ALIEIF (EMAC_INTSTS[5]) is set. | ||
| 0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled. | ||
| 1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled. | ||
| [6] | RPIEN | Runt Packet Interrupt Enable Control |
| The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation. | ||
| If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RPIF (EMAC_INTSTS[6]) is set. | ||
| 0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled. | ||
| 1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled. | ||
| [7] | MPCOVIEN | Miss Packet Counter Overrun Interrupt Enable |
| The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation. | ||
| If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MPCOVIF (EMAC_INTSTS[7]) is set. | ||
| 0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled. | ||
| 1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled. | ||
| [8] | MFLEIEN | Maximum Frame Length Exceed Interrupt Enable |
| The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation. | ||
| If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MFLEIF (EMAC_INTSTS[8]) is set. | ||
| 0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled. | ||
| 1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled. | ||
| [9] | DENIEN | DMA Early Notification Interrupt Enable Control |
| The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation. | ||
| If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the DENIF (EMAC_INTSTS[9]) is set. | ||
| 0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled. | ||
| 1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled. | ||
| [10] | RDUIEN | Receive Descriptor Unavailable Interrupt Enable Control |
| The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation. | ||
| If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RDUIF (EMAC_MIOSTA[10]) register is set. | ||
| 0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled. | ||
| 1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled. | ||
| [11] | RXBEIEN | Receive Bus Error Interrupt Enable Control |
| The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation. | ||
| If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXBEIF (EMAC_INTSTS[11]) is set. | ||
| 0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled. | ||
| 1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled. | ||
| [14] | CFRIEN | Control Frame Receive Interrupt Enable Control |
| The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation. | ||
| If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CFRIF (EMAC_INTSTS[14]) register is set. | ||
| 0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled. | ||
| 1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled. | ||
| [15] | WOLIEN | Wake On LAN Interrupt Enable |
| The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation. | ||
| If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. | ||
| If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the WOLIF (EMAC_INTSTS[15]) is set. | ||
| 0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled. | ||
| 1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled. | ||
| [16] | TXIEN | Transmit Interrupt Enable Control |