| Once this bit is set, the auto trim operation stopped and FREQSEL will be cleared to 0 by hardware automatically. | ||
| If this bit is set and TFAILIEN is high, an interrupt will be triggered to notify that HFIRC trim value update limitation count was reached. | ||
| Software can write 1 to clear this bit to zero. | ||
| 0 = Trim value update limitation count is not reached. | ||
| 1 = Trim value update limitation count is reached and HFIRC frequency is still not locked. | ||
| [2] | CLKERRIF | LXT Clock Error Interrupt Status |
| This bit indicates that LXT clock frequency is inaccuracy. | ||
| Once this bit is set, the auto trim operation stopped and FREQSEL will be cleared to 0 by hardware automatically. | ||
| If this bit is set and CLKEIEN is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy. | ||
| Software can write 1 to clear this bit to zero. | ||
| 0 = LXT clock frequency is accuracy. | ||
| 1 = LXT clock frequency is inaccuracy. |
Definition at line 5461 of file Mini55Series.h.
| __IO uint32_t UART_T::IRDA |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | TXEN | TXEN |
| 0 = IrDA receiver Enabled. | ||
| 1 = IrDA transmitter Enabled. | ||
| [5] | TXINV | TXINV |
| 0 = No inversion. | ||
| 1 = Inverse TX output signal. | ||
| [6] | RXINV | RXINV |
| 0 = No inversion. | ||
| 1 = Inverse RX input signal. |
Definition at line 6566 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ0SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2524 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ12SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2648 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ13SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2660 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ14SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2672 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ16SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2688 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ17SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2700 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ18SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
Definition at line 2711 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ1SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2536 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ25SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2727 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ28SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2743 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ29SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2755 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ2SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2548 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ3SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2560 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ4SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2572 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ5SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2584 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ6SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2596 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ7SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2608 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ8SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2620 of file Mini55Series.h.
| __I uint32_t INTR_T::IRQ9SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2632 of file Mini55Series.h.
| __IO uint32_t INTR_T::IRQSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | IRQ | MCU IRQ Source Register |
| The IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. | ||
| There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mode. | ||
| The IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0. | ||
| When the IRQ[n] is 0, setting IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n]. | ||
| When the IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting IRQ[n] 0 has no effect. |
Definition at line 2792 of file Mini55Series.h.
| __IO uint32_t FMC_T::ISPADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | ISPADR | ISP Address |
| The NuMicro Mini55 series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation. |
Definition at line 1324 of file Mini55Series.h.
| __IO uint32_t FMC_T::ISPCMD |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CMD | ISP Command |
| ISP commands are shown below: | ||
| 0x00 = Read. | ||
| 0x04 = Read Unique ID. | ||
| 0x0B = Read Company ID (0xDA). | ||
| 0x21 = Program. | ||
| 0x22 = Page Erase. | ||
| 0x2E = Set Vector Page Re-Map. |
Definition at line 1355 of file Mini55Series.h.
| __IO uint32_t FMC_T::ISPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPEN | ISP Enable Control (Write Protect) |
| Set this bit to enable ISP function. | ||
| 0 = ISP function Disabled. | ||
| 1 = ISP function Enabled. | ||
| [1] | BS | Boot Select (Write Protect) |
| Set/clear this bit to select next booting from LDROM/APROM, respectively. | ||
| This bit also functions as chip booting status flag, which can be used to check where chip booted from. | ||
| This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (CPURF is 1) or system reset (SYSRF) is happened. | ||
| 0 = Boot from APROM. | ||
| 1 = Boot from LDROM. | ||
| [3] | APUEN | APROM Update Enable Control (Write Protect) |
| 0 = APROM cannot be updated when chip runs in APROM. | ||
| 1 = APROM can be updated when chip runs in APROM. | ||
| [4] | CFGUEN | CONFIG Update Enable Control (Write Protect) |
| Writing this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM. | ||
| 0 = ISP update User Configuration Disabled. | ||
| 1 = ISP update User Configuration Enabled. | ||
| [5] | LDUEN | LDROM Update Enable Control (Write Protect) |
| 0 = LDROM cannot be updated. | ||
| 1 = LDROM can be updated when the MCU runs in APROM. | ||
| [6] | ISPFF | ISP Fail Flag (Write Protect) |
| This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
| (1) APROM writes to itself if APUEN is set to 0. | ||
| (2) LDROM writes to itself. | ||
| (3) Destination address is illegal, such as over an available range. | ||
| Note: Write 1 to clear this bit to 0. |
Definition at line 1312 of file Mini55Series.h.
| __IO uint32_t FMC_T::ISPDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | ISPDAT | ISP Data |
| Write data to this register before ISP program operation. | ||
| Read data from this register after ISP read operation. |
Definition at line 1337 of file Mini55Series.h.
| __I uint32_t FMC_T::ISPSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPBUSY | ISP Start Trigger (Read Only) |
| Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. | ||
| 0 = ISP operation is finished. | ||
| 1 = ISP operation is progressed. | ||
| Note: This bit is the same with FMC_ISPTRG bit 0. | ||
| [2:1] | CBS | Config Boot Selection (Read Only) |
| This is a mirror of CBS in CONFIG0. | ||
| [6] | ISPFF | ISP Fail Flag (Write-Protection Bit) |
| This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
| (1) APROM writes to itself if APUEN is set to 0. | ||
| (2) LDROM writes to itself if LDUEN is set to 0. | ||
| (3) CONFIG is erased/programmed if CFGUEN is set to 0. | ||
| (4) Destination address is illegal, such as over an available range. | ||
| Write 1 to clear. | ||
| Note: This bit functions the same as FMC_ISPCTL bit 6. | ||
| [20:9] | VECMAP | Vector Page Mapping Address (Read Only) |
| The current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}. |
Definition at line 1414 of file Mini55Series.h.
| __IO uint32_t FMC_T::ISPTRG |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPGO | ISP Start Trigger (Write Protect) |
| Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. | ||
| 0 = ISP operation is finished. | ||
| 1 = ISP operation is progressed. |
Definition at line 1369 of file Mini55Series.h.
| __IO uint32_t UART_T::LINE |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | WLS | Word Length Selection |
| 00 = Word length is 5-bit. | ||
| 01 = Word length is 6-bit. | ||
| 10 = Word length is 7-bit. | ||
| 11 = Word length is 8-bit. | ||
| [2] | NSB | Number Of "STOP Bit" |
| 0 = One "STOP bit" is generated in the transmitted data. | ||
| 1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. | ||
| When select 6-, 7- and 8-bti word length, 2 "STOP bit" is generated in the transmitted data. | ||
| [3] | PBE | Parity Bit Enable Control |
| 0 = No parity bit. | ||
| 1 = Parity bit is generated on each outgoing character and is checked on each incoming data. | ||
| [4] | EPE | Even Parity Enable Control |
| 0 = Odd number of logic 1's is transmitted and checked in each word. | ||
| 1 = Even number of logic 1's is transmitted and checked in each word. | ||
| This bit has effect only when PBE (UART_LINE[3]) is set. | ||
| [5] | SPE | Stick Parity Enable Control |
| 0 = Stick parity Disabled. | ||
| 1 = If PBE (UART_LINE[3]) and EBE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. | ||
| If PBE (UART_LINE[3]) is 1 and EBE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. | ||
| [6] | BCB | Break Control Bit |
| When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). | ||
| This bit acts only on TX and has no effect on the transmitter logic. | ||
| 0 = Break control Disabled. | ||
| 1 = Break control Enabled. |
Definition at line 6303 of file Mini55Series.h.
| __IO uint32_t GPIO_T::MODE |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | MODE0 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. | ||
| MODEn[1:0] | ||
| Pin I/O Mode (x = 0~5, n = 0~7). | ||
| 00 = Input mode. | ||
| 01 = Push-pull Output mode. | ||
| 10 = Open-Drain Output mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| [3:2] | MODE1 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. | ||
| MODEn[1:0] | ||
| Pin I/O Mode (x = 0~5, n = 0~7). | ||
| 00 = Input mode. | ||
| 01 = Push-pull Output mode. | ||
| 10 = Open-Drain Output mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| [5:4] | MODE2 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. | ||
| MODEn[1:0] | ||
| Pin I/O Mode (x = 0~5, n = 0~7). | ||
| 00 = Input mode. | ||
| 01 = Push-pull Output mode. | ||
| 10 = Open-Drain Output mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| [7:6] | MODE3 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. | ||
| MODEn[1:0] | ||
| Pin I/O Mode (x = 0~5, n = 0~7). | ||
| 00 = Input mode. | ||
| 01 = Push-pull Output mode. | ||
| 10 = Open-Drain Output mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| [9:8] | MODE4 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. | ||
| MODEn[1:0] | ||
| Pin I/O Mode (x = 0~5, n = 0~7). | ||
| 00 = Input mode. | ||
| 01 = Push-pull Output mode. | ||
| 10 = Open-Drain Output mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| [11:10] | MODE5 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. | ||
| MODEn[1:0] | ||
| Pin I/O Mode (x = 0~5, n = 0~7). | ||
| 00 = Input mode. | ||
| 01 = Push-pull Output mode. | ||
| 10 = Open-Drain Output mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| [13:12] | MODE6 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. | ||
| MODEn[1:0] | ||
| Pin I/O Mode (x = 0~5, n = 0~7). | ||
| 00 = Input mode. | ||
| 01 = Push-pull Output mode. | ||
| 10 = Open-Drain Output mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| [15:14] | MODE7 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. | ||
| MODEn[1:0] | ||
| Pin I/O Mode (x = 0~5, n = 0~7). | ||
| 00 = Input mode. | ||
| 01 = Push-pull Output mode. | ||
| 10 = Open-Drain Output mode. | ||
| 11 = Quasi-bidirectional mode. |
Definition at line 1554 of file Mini55Series.h.
| __IO uint32_t UART_T::MODEM |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | RTS | RTS (Request-To-Send) Signal Control |
| This bit is direct control internal RTS signal active or not, and then drive the RTS pin output with RTSACTLV bit configuration. | ||
| 0 = RTS signal is active. | ||
| 1 = RTS signal is inactive. | ||
| Note1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode. | ||
| Note2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. | ||
| [9] | RTSACTLV | RTS Pin Active Level |
| This bit defines the active level state of RTS pin output. | ||
| 0 = RTS pin output is high level active. | ||
| 1 = RTS pin output is low level active. | ||
| [13] | RTSSTS | RTS Pin State (Read Only) |
| This bit mirror from RTS pin output of voltage logic status. | ||
| 0 = RTS pin output is low level voltage logic state. | ||
| 1 = RTS pin output is high level voltage logic state. |
Definition at line 6327 of file Mini55Series.h.
| __IO uint32_t UART_T::MODEMSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CTSDETF | Detect CTS State Change Flag |
| This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. | ||
| 0 = CTS input has not change state. | ||
| 1 = CTS input has change state. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [4] | CTSSTS | CTS Pin Status (Read Only) |
| This bit mirror from CTS pin input of voltage logic status. | ||
| 0 = CTS pin input is low level voltage logic state. | ||
| 1 = CTS pin input is high level voltage logic state. | ||
| Note: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected. | ||
| [8] | CTSACTLV | CTS Pin Active Level |
| This bit defines the active level state of CTS pin input. | ||
| 0 = CTS pin input is high level active. | ||
| 1 = CTS pin input is low level active. | ||
| Note: Refer to Figure 6.14-10 |
Definition at line 6352 of file Mini55Series.h.
| __IO uint32_t INTR_T::NMICTL |
| Bits | Field | Descriptions |
|---|---|---|
| [4:0] | NMTSEL | NMI Interrupt Source Selection |
| The NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMTSEL. | ||
| [8] | NMISELEN | NMI Interrupt Enable Control (Write Protected) |
| 0 = NMI interrupt Disabled. | ||
| 1 = NMI interrupt Enabled. | ||
| Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. | ||
| Refer to the register REGWRPROT at address SYS_BA+0x100. |
Definition at line 2776 of file Mini55Series.h.
| __IO uint32_t SYS_T::P0_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P0 Multiple Function Selection |
| The pin function of P0 depends on P0_MFP and ALT. | ||
| [8:15] | ALT | P0 Alternate Function Selection |
| The pin function of P0 depends on P0_MFP and ALT. | ||
| [23:16] | TYPE | P0[7:0] Input Schmitt Trigger Function Enable |
| 0 = P0[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P0[7:0] I/O input Schmitt Trigger function Enabled. | ||
| [31:24] | HS | P0[7:0] Slew Rate Control |
| 0 = P0[7:0] Low slew rate output, 16MHz available. | ||
| 1 = P0[7:0] High slew rate output, 24MHz available. |
Definition at line 5263 of file Mini55Series.h.
| __IO uint32_t SYS_T::P1_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P1 Multiple Function Selection |
| The pin function of P1 depends on MFP and ALT. | ||
| Refer to P1_ALT Description for details. | ||
| [8:15] | ALT | P1 Alternate Function Selection |
| The pin function of P1 depends on MFP and ALT. | ||
| [23:16] | TYPE | P1[7:0] Input Schmitt Trigger Function Enable |
| 0 = P1[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P1[7:0] I/O input Schmitt Trigger function Enabled. | ||
| [31:24] | HS | P1[7:0] Slew Rate Control |
| 0 = P1[7:0] Low slew rate output, 16MHz available. | ||
| 1 = P1[7:0] High slew rate output, 24MHz available. |
Definition at line 5284 of file Mini55Series.h.
| __IO uint32_t SYS_T::P2_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P2 Multiple Function Selection |
| The pin function of P2 depends on P2_MFP and ALT. | ||
| Refer to ALT Description for details. | ||
| [8:15] | ALT | P2 Alternate Function Selection |
| The pin function of P2 depends on MFP and ALT. | ||
| [23:16] | TYPE | P2[7:0] Input Schmitt Trigger Function Enable |
| 0 = P2[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P2[7:0] I/O input Schmitt Trigger function Enabled. | ||
| [31:24] | HS | P2[7:0] Slew Rate Control |
| 0 = P2[7:0] Low slew rate output, 16MHz available. | ||
| 1 = P2[7:0] High slew rate output, 24MHz available. |
Definition at line 5305 of file Mini55Series.h.
| __IO uint32_t SYS_T::P3_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P3 Multiple Function Selection |
| The pin function of P3 depends on MFP and ALT. | ||
| Refer to ALT Description for details. | ||
| [8:15] | ALT | P3 Alternate Function Selection |
| The pin function of P3 depends on MFP and ALT. | ||
| [23:16] | TYPE | P3[7:0] Input Schmitt Trigger Function Enable |
| 0 = P3[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P3[7:0] I/O input Schmitt Trigger function Enabled. | ||
| [24] | P32CTL | P3.2 Alternate Function Selection Extension |
| 0 = P3.2 is set by ALT[2] and MFP[2]. | ||
| 1 = P3.2 is set to CPP1 of ACMP1. | ||
| [31:25] | HS | P3[6:0] Slew Rate Control |
| 0 = P3[6:0] Low slew rate output, 16MHz available. | ||
| 1 = P3[6:0] High slew rate output, 24MHz available. |
Definition at line 5329 of file Mini55Series.h.
| __IO uint32_t SYS_T::P4_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P4 Multiple Function Selection |
| The pin function of P4 depends on MFP and P4_ALT. | ||
| Refer to ALT Description for details. | ||
| [8:15] | ALT | P4 Alternate Function Selection |
| The pin function of P4 depends on MFP and ALT. | ||
| [23:16] | TYPE | P4[7:0] Input Schmitt Trigger Function Enable |
| 0 = P4[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P4[7:0] I/O input Schmitt Trigger function Enabled. | ||
| [31:24] | HS | P4[7:0] Slew Rate Control |
| 0 = P4[7:0] Low slew rate output, 16MHz available. | ||
| 1 = P4[7:0] High slew rate output, 24MHz available. |
Definition at line 5350 of file Mini55Series.h.
| __IO uint32_t SYS_T::P5_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P5 Multiple Function Selection |
| The pin function of P5 depends on MFP and ALT. | ||
| Refer to ALT Description for details. | ||
| [8:15] | ALT | P5 Alternate Function Selection |
| The pin function of P5 depends on MFP and ALT. | ||
| [23:16] | TYPE | P5[7:0] Input Schmitt Trigger Function Enable |
| 0 = P5[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P5[7:0] I/O input Schmitt Trigger function Enabled. | ||
| [31:24] | HS | P5[7:0] Slew Rate Control |
| 0 = P5[7:0] Low slew rate output, 16MHz available. | ||
| 1 = P5[7:0] High slew rate output, 24MHz available. |
Definition at line 5371 of file Mini55Series.h.
| __I uint32_t SYS_T::PDID |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | PDID | Product Device Identification Number |
| This register reflects the device part number code. | ||
| Software can read this register to identify which device is used. |
Definition at line 5073 of file Mini55Series.h.
| __IO uint32_t PWM_T::PERIOD[6] |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PERIOD | PWM Counter/Timer Loaded Value |
| PERIOD determines the PWM period. | ||
| Edge-aligned mode: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/(PERIOD+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMP+1)/(PERIOD+1). | ||
| CMP >= PERIOD: PWM output is always high. | ||
| CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit. | ||
| CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit. | ||
| Center-aligned mode: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIOD+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIOD - CMP)/(PERIOD+1). | ||
| CMP >= PERIOD: PWM output is always low. | ||
| CMP < PERIOD: PWM low width = (CMP + 1) * 2 unit; PWM high width = (PERIOD - CMP) * 2 unit. | ||
| CMP = 0: PWM low width = 2 unit; PWM high width = (PERIOD) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIOD will take effect in next PWM cycle. |
Definition at line 3068 of file Mini55Series.h.
| __IO uint32_t PWM_T::PHCHG |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | MSKDAT0 | MSKDAT0: When MSKEN0 Is Zero, Channel 0's Output Waveform Is MSKDAT0 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [1] | MSKDAT1 | MSKDAT1: When MSKEN1 Is Zero, Channel 1's Output Waveform Is MSKDAT1 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [2] | MSKDAT2 | MSKDAT2: When MSKEN2 Is Zero, Channel 2's Output Waveform Is MSKDAT2 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [3] | MSKDAT3 | MSKDAT3: When MSKEN3 Is Zero, Channel 3's Output Waveform Is MSKDAT3 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [4] | MSKDAT4 | MSKDAT4: When MSKEN4 Is Zero, Channel 4's Output Waveform Is MSKDAT4 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [5] | MSKDAT5 | MSKDAT5: When MSKEN5 Is Zero, Channel 5's Output Waveform Is MSKDAT5 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [6] | MSKDAT6 | MSKDAT6: When MSKEN6 Is 1, Channel 6's Output Waveform Is MSKDAT6 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [7] | MSKDAT7 | MSKDAT7: When MSKEN7 Is 1, Channel 7's Output Waveform Is MSKDAT7 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [8] | MSKEN0 | MSKEN Channel 0 Output Enable Control |
| 0 = Output the original channel 0 waveform. | ||
| 1 = Output MSKDAT0 specified in bit 0 of PWM_PHCHG register. | ||
| [9] | MSKEN1 | MSKEN Channel 1 Output Enable Control |
| 0 = Output the original channel 1 waveform. | ||
| 1 = Output MSKDAT1 specified in bit 1 of PWM_PHCHG register. | ||
| [10] | MSKEN2 | MSKEN Channel 2 Output Enable Control |
| 0 = Output the original channel 2 waveform. | ||
| 1 = Output MSKDAT2 specified in bit 2 of PWM_PHCHG register. | ||
| [11] | MSKEN3 | MSKEN Channel 3 Output Enable Control |
| 0 = Output the original channel 3 waveform. | ||
| 1 = Output MSKDAT3 specified in bit 3 of PWM_PHCHG register. | ||
| [12] | MSKEN4 | MSKEN Channel 4 Output Enable Control |
| 0 = Output the original channel 4 waveform. | ||
| 1 = Output MSKDAT4 specified in bit 4 of PWM_PHCHG register. | ||
| [13] | MSKEN5 | MSKEN Channel 5 Output Enable Control |
| 0 = Output the original channel 5 waveform. | ||
| 1 = Output MSKDAT5 specified in bit 5 of PWM_PHCHG register. | ||
| [14] | AUTOCLR0 | Hardware Auto Clear ACMP0TEN When ACMP0 Trigger It |
| 0 = Enabled. | ||
| 1 = Disabled. | ||
| [15] | AUTOCLR1 | Hardware Auto Clear ACMP1TEN When ACMP1 Trigger It |
| 0 = Enabled. | ||
| 1 = Disabled. | ||
| [16] | OFFEN01 | Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [17] | OFFEN11 | Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [18] | OFFEN21 | Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [19] | OFFEN31 | Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [21:20] | A1POSSEL | A1POSSEL |
| Select the positive input source of ACMP1. | ||
| 00 = Select P3.1 as the input of ACMP1 | ||
| 01 = Select P3.2 as the input of ACMP1 | ||
| 10 = Select P3.3 as the input of ACMP1 | ||
| 11 = Select P3.4 as the input of ACMP1 | ||
| [22] | TMR1TEN | Enable Timer1 Trigger PWM Function |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| When this bit is set, timer1 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register. | ||
| [23] | ACMP1TEN | Enable ACMP1 Trigger Function |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set. | ||
| [24] | OFFEN00 | Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [25] | OFFEN10 | Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [26] | OFFEN20 | Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [27] | OFFEN30 | Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [29:28] | A0POSSEL | A0POSSEL |
| Select the positive input source of ACMP0. | ||
| 00 = Select P1.5 as the input of ACMP0 | ||
| 01 = Select P1.0 as the input of ACMP0 | ||
| 10 = Select P1.2 as the input of ACMP0 | ||
| 11 = Select P1.3 as the input of ACMP0 | ||
| [30] | T0 | Enable Timer0 Trigger PWM Function |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| When this bit is set, timer0 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register. | ||
| [31] | ACMP0TEN | Enable ACMP0 Trigger Function |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set. |
Definition at line 3703 of file Mini55Series.h.
| __IO uint32_t PWM_T::PHCHGMSK |
| Bits | Field | Descriptions |
|---|---|---|
| [6] | MASKEND6 | MASK For D6 |
| 0 = Original GPIO P0.1. | ||
| 1 = D6. | ||
| [7] | MASKEND7 | MASK For D7 |
| 0 = Original GPIO P0.0. | ||
| 1 = D7. | ||
| [8] | POSCTL0 | ACMP0 Positive Input Selection Control |
| 0 = The input of ACMP0 is controlled by CMP0CR. | ||
| 1 = The input of ACMP0 is controlled by A0POSSEL of PWM_PHCHG register. | ||
| Note: Register CMP0CR is describe in Comparator Controller chapter | ||
| [9] | POSCTL1 | ACMP1 Positive Input Selection Control |
| 0 = The input of ACMP1 is controlled by CMP1CR. | ||
| 1 = The input of ACMP1 is controlled by A1POSSEL of PWM_PHCHG register. | ||
| Note: Register CMP1CR is describe in Comparator Controller chapter |
Definition at line 3845 of file Mini55Series.h.
| __IO uint32_t PWM_T::PHCHGNXT |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | MSKDAT0 | MSKDAT0: When MSKEN0 Is Zero, Channel 0's Output Waveform Is MSKDAT0 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [1] | MSKDAT1 | MSKDAT1: When MSKEN1 Is Zero, Channel 1's Output Waveform Is MSKDAT1 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [2] | MSKDAT2 | MSKDAT2: When MSKEN2 Is Zero, Channel 2's Output Waveform Is MSKDAT2 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [3] | MSKDAT3 | MSKDAT3: When MSKEN3 Is Zero, Channel 3's Output Waveform Is MSKDAT3 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [4] | MSKDAT4 | MSKDAT4: When MSKEN4 Is Zero, Channel 4's Output Waveform Is MSKDAT4 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [5] | MSKDAT5 | MSKDAT5: When MSKEN5 Is Zero, Channel 5's Output Waveform Is MSKDAT5 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [6] | MSKDAT6 | MSKDAT6: When MSKEN6 Is 1, Channel 6's Output Waveform Is MSKDAT6 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [7] | MSKDAT7 | MSKDAT7: When MSKEN7 Is 1, Channel 7's Output Waveform Is MSKDAT7 |
| 0 = Output low. | ||
| 1 = Output high. | ||
| [8] | MSKEN0 | MSKEN Channel 0 Output Enable Control |
| 0 = Output the original channel 0 waveform. | ||
| 1 = Output D0 specified in bit 0 of PWM_PHCHG register. | ||
| [9] | MSKEN1 | MSKEN Channel 1 Output Enable Control |
| 0 = Output the original channel 1 waveform. | ||
| 1 = Output MSKDAT1 specified in bit 1 of PWM_PHCHG register. | ||
| [10] | MSKEN2 | MSKEN Channel 2 Output Enable Control |
| 0 = Output the original channel 2 waveform. | ||
| 1 = Output MSKDAT2 specified in bit 2 of PWM_PHCHG register. | ||
| [11] | MSKEN3 | MSKEN Channel 3 Output Enable Control |
| 0 = Output the original channel 3 waveform. | ||
| 1 = Output MSKDAT3 specified in bit 3 of PWM_PHCHG register. | ||
| [12] | MSKEN4 | MSKEN Channel 4 Output Enable Control |
| 0 = Output the original channel 4 waveform. | ||
| 1 = Output MSKDAT4 specified in bit 4 of PWM_PHCHG register. | ||
| [13] | MSKEN5 | MSKEN Channel 5 Output Enable Control |
| 0 = Output the original channel 5 waveform. | ||
| 1 = Output MSKDAT5 specified in bit 5 of PWM_PHCHG register. | ||
| [14] | AUTOCLR0 | Hardware Auto Clear ACMP0TEN When ACMP0 Trigger It |
| 0 = Enabled. | ||
| 1 = Disabled. | ||
| [15] | AUTOCLR1 | Hardware Auto Clear ACMP1TEN When ACMP1 Trigger It |
| 0 = Enabled. | ||
| 1 = Disabled. | ||
| [16] | OFFEN01 | Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [17] | OFFEN11 | Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [18] | OFFEN21 | Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [19] | OFFEN31 | Setting This Bit Will Force MSKEN3to Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [21:20] | A1POSSEL | A1POSSEL |
| Select the positive input source of ACMP1. | ||
| 00 = Select P3.1 as the input of ACMP1 | ||
| 01 = Select P3.2 as the input of ACMP1 | ||
| 10 = Select P3.3 as the input of ACMP1 | ||
| 11 = Select P3.4 as the input of ACMP1 | ||
| [22] | TMR1TEN | Enable Timer1 Trigger PWM Function |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| When this bit is set, timer1 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register. | ||
| [23] | ACMP1TEN | Enable ACMP1 Trigger Function |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set. | ||
| [24] | OFFEN00 | Setting This Bit Will Force MSKEN0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [25] | OFFEN10 | Setting This Bit Will Force MSKEN1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [26] | OFFEN20 | Setting This Bit Will Force MSKEN2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [27] | OFFEN30 | Setting This Bit Will Force MSKEN3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It; This Feature Is Usually In Step Motor Application |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Only for MSKEN0, MSKEN3, MSKEN2, MSKEN3. | ||
| [29:28] | A0POSSEL | A0POSSEL |
| Select the positive input source of ACMP0. | ||
| 00 = Select P1.5 as the input of ACMP0 | ||
| 01 = Select P1.0 as the input of ACMP0 | ||
| 10 = Select P1.2 as the input of ACMP0 | ||
| 11 = Select P1.3 as the input of ACMP0 | ||
| [30] | TMR0TEN | Enable Timer0 Trigger PWM Function |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| When this bit is set, timer0 time-out event will update PWM_PHCHG with PWM_PHCHG_NXT register. | ||
| [31] | ACMP0TEN | Enable ACMP0 Trigger Function |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set. |
Definition at line 3821 of file Mini55Series.h.
| __I uint32_t GPIO_T::PIN |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | PIN | Port 0-5 Pin [N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin. | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note: x = 0~5, n = 0~7. |
Definition at line 1615 of file Mini55Series.h.
| __IO uint32_t PWM_T::POEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | POEN0 | PWM Channel 0 Output Enable Register |
| 0 = PWM channel 0 output to pin Disabled. | ||
| 1 = PWM channel 0 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [1] | POEN1 | PWM Channel 1 Output Enable Register |
| 0 = PWM channel 1 output to pin Disabled. | ||
| 1 = PWM channel 1 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [2] | POEN2 | PWM Channel 2 Output Enable Register |
| 0 = PWM channel 2 output to pin Disabled. | ||
| 1 = PWM channel 2 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [3] | POEN3 | PWM Channel 3 Output Enable Register |
| 0 = PWM channel 3 output to pin Disabled. | ||
| 1 = PWM channel 3 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [4] | POEN4 | PWM Channel 4 Output Enable Register |
| 0 = PWM channel 4 output to pin Disabled. | ||
| 1 = PWM channel 4 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [5] | POEN5 | PWM Channel 5 Output Enable Register |
| 0 = PWM channel 5 output to pin Disabled. | ||
| 1 = PWM channel 5 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. |
Definition at line 3315 of file Mini55Series.h.
| __IO uint32_t CLK_T::PWRCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | XTLEN | External HXT Or LXT Crystal Oscillator Enable Control (Write Protect) |
| The default clock source is from HIRC. | ||
| These two bits are default set to "00" and the XTAL1 and XTAL2 pins are GPIO. | ||
| 00 = XTAL1 and XTAL2 are GPIO, disable both LXT & HXT (default). | ||
| 01 = HXT Enabled. | ||
| 10 = LXT Enabled. | ||
| 11 = XTAL1 is external clock input pin, XTAL2 is GPIO. | ||
| Note: To enable external XTAL function, P5_ALT[1:0] and P5_MFP[1:0] bits must also be set in P5_MFP. | ||
| [2] | HIRCEN | Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect) |
| 0 = Internal high speed RC oscillator (HIRC) Disabled. | ||
| 1 = Internal high speed RC oscillator (HIRC) Enabled. | ||
| Note: The default of HIRCEN bit is 1. | ||
| [3] | LIRCEN | 10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protest) |
| 0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. | ||
| 1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. | ||
| [4] | PDWKDLY | Wake-Up Delay Counter Enable Control (Write Protect) |
| When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. | ||
| The delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal (HXT), 4096 clock cycles for 32.768 kHz external low speed crystal (LXT), and 16 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC). | ||
| 0 = Clock cycles delay Disabled. | ||
| 1 = Clock cycles delay Enabled. | ||
| [5] | PDWKIEN | Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: The interrupt will occur when both PDWKIF and PDWKIEN are high. | ||
| [6] | PDWKIF | Power-Down Mode Wake-Up Interrupt Status |
| Set by "Power-down wake-up event", which indicates that resume from Power-down mode" | ||
| The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wake-up occurred. | ||
| Note: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. Write 1 to clear the bit to 0. | ||
| [7] | PDEN | System Power-Down Enable Bit (Write Protect) |
| When chip wakes up from Power-down mode, this bit is cleared by hardware. | ||
| User needs to set this bit again for next Power-down. | ||
| In Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT), 32.768 kHz external low speed crystal oscillator (LXT), and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode. | ||
| In Power-down mode, the system clock is disabled, and ignored the clock source selection. | ||
| The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator. | ||
| 0 = Chip operating normally or chip in Idle mode because of WFI command. | ||
| 1 = Chip enters Power-down mode instantly or waits CPU sleep command WFI. | ||
| [9] | PDLXT | Enable LXT In Power-Down Mode |
| This bit controls the crystal oscillator active or not in Power-down mode. | ||
| 0 = No effect to Power-down mode. | ||
| 1 = If XTLEN[1:0] = 10, LXT is still active in Power-down mode. | ||
| [11:10] | HXTGAIN | HXT Gain Selection |
| 00 = Full gain for the frequency up to 24MHz. | ||
| 01 = 3/4 gain for the frequency up to 16MHz. | ||
| 10 = 1/2 gain for the frequency up to 12MHz. | ||
| 11 = 1/4 gain for the frequency up to 4MHz. |
Definition at line 875 of file Mini55Series.h.
| __IO uint32_t HDIV_T::QUOTIENT |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | QUOTIENT | Quotient Result |
| This register holds the quotient result of divider after calculation complete. |
Definition at line 2046 of file Mini55Series.h.
| __IO uint32_t SYS_T::REGLCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | REGWRPROT | Register Write-Protection Disable Index (Read Only) |
| 0 = Write-protection Enabled for writing protected registers. | ||
| Any write to the protected register is ignored. | ||
| 1 = Write-protection Disabled for writing protected registers. | ||
| The Protected registers are: | ||
| SYS_IPRST0, SYS_BODCTL, SYS_LDOCR, SYS_PORCTL, CLK_PWRCTL, CLK_APBCLK, CLK_CLKSEL0, CLK_CLKSEL1, NMI_SEL, FMC_ISPCTL, FMC_ISPTRG, WDT_CTL | ||
| Note: The bits which are write-protected will be noted as" (Write Protect)" beside the description. | ||
| [7:0] | REGPROTDIS | Register Write-Protection Code (Write Only) |
| Some registers have write-protection function. | ||
| Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. | ||
| After this sequence is completed, the REGWRPROT bit will be set to 1 and write-protection registers can be normal write. |
Definition at line 5486 of file Mini55Series.h.
| __IO uint32_t HDIV_T::REM |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | REM | Remainder Result |
| The remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension (REM[31:16]) to 32-bit integer. |
Definition at line 2058 of file Mini55Series.h.
| __IO uint32_t SYS_T::RSTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PORF | Power-On Reset Flag |
| The PORF flag is set by the "reset signal", which is from the Power-On Reset (POR) controller or bit CHIPRST (SYS_IPRST0[0]), to indicate the previous reset source. | ||
| 0 = No reset from POR or CHIPRST. | ||
| 1 = The Power-on-Reset (POR) or CHIPRST had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [1] | PINRF | Reset Pin Reset Flag |
| The PINRF flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source. | ||
| 0 = No reset from pin /RESET pin. | ||
| 1 = The /RESET pin had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [2] | WDTRF | Watchdog Reset Flag |
| The RSTS_WDT flag is set by the "reset signal" from the Watchdog timer to indicate the previous reset source. | ||
| 0 = No reset from Watchdog timer. | ||
| 1 = The Watchdog timer had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [4] | BODRF | Brown-Out Detector Reset Flag |
| The BODRF flag is set by the "reset signal" from the Brown-out Detector to indicate the previous reset source. | ||
| 0 = No reset from BOD. | ||
| 1 = The BOD had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [5] | SYSRF | MCU Reset Flag |
| The SYSRF flag is set by the "reset signal" from the Cortex-M0 core to indicate the previous reset source. | ||
| 0 = No reset from Cortex-M0. | ||
| 1 = The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2]), Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [7] | CPURF | CPU Reset Flag |
| The CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC). | ||
| 0 = No reset from CPU. | ||
| 1 = Cortex-M0 core and FMC are reset by software setting CPURST to 1. | ||
| Note: Software can write 1 to clear this bit to zero. |
Definition at line 5113 of file Mini55Series.h.
| __I uint32_t SPI_T::RX |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | RX | Data Receive Register (Read Only) |
| The Data Receive Registers hold the value of received data of the last executed transfer. | ||
| Valid bits depend on the transmit bit length field in the SPI_CTL register. | ||
| For example, if DWIDTH is set to 0x08, bit RX0[7:0] holds the received data. | ||
| The values of the other bits are unknown. | ||
| The Data Receive Registers are read-only registers. |
Definition at line 4731 of file Mini55Series.h.
| __IO uint32_t ADC_T::SEQCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SEQEN | ADC Sequential Mode Enable |
| When ADC sequential mode is enabled, two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0, 1] or channel[1, 2] or channel[0, 2] defined by SEQ_MODE[1:0]. | ||
| 0 = ADC sequential mode Disabled. | ||
| 1 = ADC sequential mode Enabled. | ||
| [1] | SEQTYPE | ADC Sequential Mode Type |
| 0 = ADC delay time is only inserted before the first conversion. | ||
| The second conversion starts immediately after the first conversion is completed. | ||
| (for 2/3-shunt type). | ||
| 1 = ADC delay time is inserted before each conversion. (for 1-shunt type) | ||
| [3:2] | MODESEL | ADC Sequential Mode Selection |
| 00 = Issue ADC_INT after Channel 0 then Channel 1 conversion finishes when SEQEN =1. | ||
| 01 = Issue ADC_INT after Channel 1 then Channel 2 conversion finishes when SEQEN =1. | ||
| 10 = Issue ADC_INT after Channel 0 then Channel 2 conversion finishes when SEQEN =1. | ||
| 11 = Reserved | ||
| [9:8] | TRG1TYPE | ADC Sequential Mode Trigger1 Type |
| 00 = Rising of the selected PWM | ||
| 01 = center of the selected PWM | ||
| 10 = Falling of the selected PWM | ||
| 11 = Period of the selected PWM | ||
| [11:10] | TRG1SRC | ADC Sequential Mode Trigger1 Source |
| 00 = PWM0 | ||
| 01 = PWM2 | ||
| 10 = PWM4 | ||
| 11 = Reserved | ||
| [17:16] | TRG2TYPE | ADC Sequential Mode Trigger2 Type |
| 00 = Rising of the selected PWM | ||
| 01 = center of the selected PWM | ||
| 10 = Falling of the selected PWM | ||
| 11 = Period of the selected PWM | ||
| [19:18] | TRG2SRC | ADC Sequential Mode Trigger2 Source |
| 00 = PWM0 | ||
| 01 = PWM2 | ||
| 10 = PWM4 | ||
| 11 = Reserved |
Definition at line 601 of file Mini55Series.h.
| __I uint32_t ADC_T::SEQDAT0 |
| Bits | Field | Descriptions |
|---|---|---|
| [9:0] | RESULT | A/D PWM Sequential Mode Conversion Result |
| This field contains conversion result of ADC. | ||
| [16] | OV | Over Run Flag |
| 0 = Data in RESULT [9:0] is recent conversion result. | ||
| 1 = Data in RESULT [9:0] overwritten. | ||
| If converted data in RESULT [9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. | ||
| It is cleared by hardware after the ADC_DAT register is read. | ||
| [17] | VALID | Valid Flag |
| 0 = Data in RESULT [9:0] bits not valid. | ||
| 1 = Data in RESULT. ADC_TRGDLY [9:0] bits valid. | ||
| This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read. |
Definition at line 622 of file Mini55Series.h.
| __I uint32_t ADC_T::SEQDAT1 |
| Bits | Field | Descriptions |
|---|---|---|
| [9:0] | RESULT | A/D PWM Sequential Mode Conversion Result |
| This field contains conversion result of ADC. | ||
| [16] | OV | Over Run Flag |
| 0 = Data in RESULT [9:0] is recent conversion result. | ||
| 1 = Data in RESULT [9:0] overwritten. | ||
| If converted data in RESULT [9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. | ||
| It is cleared by hardware after the ADC_DAT register is read. | ||
| [17] | VALID | Valid Flag |
| 0 = Data in RESULT [9:0] bits not valid. | ||
| 1 = Data in RESULT. ADC_TRGDLY [9:0] bits valid. | ||
| This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read. |
Definition at line 643 of file Mini55Series.h.
| __IO uint32_t SPI_T::SLVCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [8] | SLV3WIRE | Slave 3-Wire Mode Enable Bit (Slave Only) |
| The SPI controller work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI. | ||
| 0 = The controller is 4-wire bi-direction interface. | ||
| 1 = The controller is 3-wire bi-direction interface in Slave mode. | ||
| The controller will be ready to transmit/receive data after the SPIEN bit is set to 1. | ||
| Note: In Slave 3-wire mode, the SSLTEN bit (SPI_SSCTL[4]) shall be set as 1. | ||
| [9] | SLVABT | Slave 3-Wire Mode Abort Control Bit (Slave Only) |
| In normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in DWIDTH. | ||
| If the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event. | ||
| 0 = No force the transfer done when the SLV3WIRE bit is set to 1. | ||
| 1 = Force the transfer done when the SLV3WIRE bit is set to 1. | ||
| Note: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. | ||
| [10] | SLVSTIEN | Slave 3-Wire Mode Start Interrupt Enable (Slave Only) |
| It is used to enable interrupt when the transfer has started in Slave 3-wire mode. | ||
| If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLV3WIRE bit to force the transfer done. | ||
| 0 = Transaction start interrupt Disabled. | ||
| 1 = Transaction start interrupt Enabled. | ||
| Note 1: It will be cleared to 0 as the current transfer is done or the SLVSTIF bit is cleared to 0. | ||
| [11] | SLVSTIF | Slave 3-Wire Mode Start Interrupt Status (Slave Only) |
| This bit dedicates if a transaction has started in Slave 3-wire mode. | ||
| 0 = Slave does not detect any SPI bus clock transfer since the SLVSTIEN bit was set to 1. | ||
| 1 = The transfer has started in Slave 3-wire mode. | ||
| Note 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit. | ||
| Note 2: It is a mutual mirror bit of SPI_STATUS[11]. | ||
| [16] | SSINAIEN | Slave Select Inactive Interrupt Option (Slave Only) |
| 0 = As the slave select signal goes to inactive level, the UNITIF bit will NOT be set to 1. | ||
| 1 = As the slave select signal goes to inactive level, the UNITIF bit will be set to 1. | ||
| Note: This setting is only available if the SPI controller is configured as level trigger in slave device. | ||
| [31] | DIVMOD | Clock Configuration Backward Compatible Option |
| 0 = The clock configuration is backward compatible. | ||
| 1 = The clock configuration is not backward compatible. | ||
| Note: Refer to the description of SPI_CLKDIV register for details. |
Definition at line 4795 of file Mini55Series.h.
| __IO uint32_t SPI_T::SSCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SS | Slave Select Control Bits (Master Only) |
| If AUTOSS bit is 0, | ||
| 0 = Set the SPISS line to inactive state. | ||
| 1 = Set the proper SPISS line to active state. | ||
| If AUTOSS bit is 1, | ||
| 0 = Keep the SPISS line at inactive state. | ||
| 1 = Select the SPISS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. | ||
| The active state of SPISS is specified in SSACTPOL bit. | ||
| [2] | SSACTPOL | Slave Select Active Level (Slave Only) |
| It defines the active status of slave select signal (SPISS). | ||
| If SSLTEN bit is 1: | ||
| 0 = The slave select signal SPISS is active at low-level. | ||
| 1 = The slave select signal SPISS is active at high-level. | ||
| If SSLTEN bit is 0: | ||
| 0 = The slave select signal SPISS is active at Falling-edge. | ||
| 1 = The slave select signal SPISS is active at Rising-edge. | ||
| [3] | AUTOSS | Automatic Slave Selection Function Enable Bit (Master Only) |
| 0 = SPISS pin signal will be asserted/de-asserted by setting /clearing SS bit. | ||
| 1 = SPISS pin signal will be generated automatically, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting SPIEN, and will be de-asserted after each transmit/receive is finished. | ||
| [4] | SSLTEN | Slave Select Level Trigger Enable Bit (Slave Only) |
| 0 = The input slave select signal is edge-trigger. | ||
| 1 = The input slave select signal is level-trigger. | ||
| [5] | LTF | Level Trigger Flag (Read Only, Slave Only) |
| When the SSLTEN bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not. | ||
| 0 = The transaction number or the transferred bit length of one transaction does not meet the specified requirements. | ||
| 1 = The transaction number and the transferred bit length met the specified requirements which defined in DWIDTH. |
Definition at line 4711 of file Mini55Series.h.
| __IO uint32_t ACMP_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ACMPIF0 | Analog Comparator 0 Flag |
| This bit is set by hardware whenever the comparator 0 output changes state. | ||
| This will generate an interrupt if ACMPIE(ACMP_CTL0[1]) = 1. | ||
| 0 = Analog comparator 0 output does not change. | ||
| 1 = Analog comparator 0 output changed. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [1] | ACMPIF1 | Analog Comparator 1 Flag |
| This bit is set by hardware whenever the comparator 1 output changes state. | ||
| This will generate an interrupt if ACMPIE(ACMP_CTL1[1]) = 1. | ||
| 0 = Analog comparator 1 output does not change. | ||
| 1 = Analog comparator 1 output changed. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [2] | ACMPO0 | Analog Comparator 0 Output |
| Synchronized to the APB clock to allow reading by software. | ||
| Cleared when the comparator 0 is disabled ACMPEN(ACMP_CTL0[0]) = 0. | ||
| 0 = Analog comparator 0 outputs 0. | ||
| 1 = Analog comparator 0 outputs 1. | ||
| [3] | ACMPO1 | Analog Comparator 1 Output |
| Synchronized to the APB clock to allow reading by software. | ||
| Cleared when the comparator 1 is disabled ACMPEN(ACMP_CTL1[0]) = 0. | ||
| 0 = Analog comparator 1 outputs 0. | ||
| 1 = Analog comparator 1 outputs 1. |
Definition at line 237 of file Mini55Series.h.
| __IO uint32_t ADC_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADIF | A/D Conversion End Flag |
| A status flag that indicates the end of A/D conversion. ADIF is set to 1 When A/D conversion ends. | ||
| Software can write 1 to clear this bit to zero. | ||
| [1] | ADCMPF0 | Compare Flag 0 |
| When the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1. | ||
| Software can write 1 to clear this bit to zero. | ||
| 0 = Conversion result in ADC_DAT does not meet the ADC_CMP0 setting. | ||
| 1 = Conversion result in ADC_DAT meets the ADC_CMP0 setting. | ||
| [2] | ADCMPF1 | Compare Flag 1 |
| When the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1. | ||
| Software can write 1 to clear this bit to zero. | ||
| 0 = Conversion result in ADC_DAT does not meet the ADC_CMP1 setting. | ||
| 1 = Conversion result in ADC_DAT meets the ADC_CMP1 setting. | ||
| [3] | BUSY | BUSY/IDLE (Read Only) |
| This bit is mirror of as SWTRG bit in ADC_CTL | ||
| 0 = A/D converter is in idle state. | ||
| 1 = A/D converter is busy at conversion. | ||
| [6:4] | CHANNEL | Current Conversion Channel (Read Only) |
| This filed reflects the current conversion channel when BUSY=1. | ||
| When BUSY=0, it shows the number of the next converted channel. | ||
| [8] | VALID | Data Valid Flag (Read Only) |
| It is a mirror of VALID bit in ADC_DAT register. | ||
| [16] | OV | OV Flag (Read Only) |
| It is a mirror to OV bit in ADC_DAT register. |
Definition at line 512 of file Mini55Series.h.
| __IO uint32_t CLK_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | XTLSTB | HXT Or LXT Clock Source Stable Flag |
| 0 = HXT or LXT clock is not stable or disabled. | ||
| 1 = HXT or LXT clock is stable. | ||
| [3] | LIRCSTB | LIRC Clock Source Stable Flag (Read Only) |
| 0 = LIRC clock is not stable or disabled. | ||
| 1 = LIRC clock is stable. | ||
| [4] | HIRCSTB | HIRC Clock Source Stable Flag (Read Only) |
| 0 = HIRC clock is not stable or disabled. | ||
| 1 = HIRC clock is stable. | ||
| [7] | CLKSFAIL | Clock Switch Fail Flag |
| 0 = Clock switching success. | ||
| 1 = Clock switching failed. | ||
| Note1: This bit is updated when software switches system clock source. | ||
| If switch target clock is stable, this bit will be set to 0. | ||
| If switch target clock is not stable, this bit will be set to 1. | ||
| Note2: This bit is read only. | ||
| After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. |
Definition at line 969 of file Mini55Series.h.
| __I uint32_t HDIV_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | DIVBYZERO | Divisor Zero Warning |
| 0 = The divisor is not 0. | ||
| 1 = The divisor is 0. | ||
| Note: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever HDIV_DIVISOR is written. | ||
| This register is read only. |
Definition at line 2073 of file Mini55Series.h.
| __I uint32_t I2C_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | STATUS | I2C Status Register |
| The three least significant bits are always 0. | ||
| The five most significant bits contain the status code. | ||
| There are 26 possible status codes. | ||
| When STATUS contains F8H, no serial interrupt is requested. | ||
| All the other STATUS values correspond to defined I2C states. | ||
| When each of these states is entered, a status interrupt is requested (SI = 1). | ||
| A valid status code is present in STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software. | ||
| In addition, the states 00H stands for a Bus Error. | ||
| A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame. | ||
| Examples of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. |
Definition at line 2192 of file Mini55Series.h.
| __IO uint32_t SPI_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXTHIF | Receive FIFO Threshold Interrupt Status (Read Only) |
| 0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH. | ||
| 1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. | ||
| Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI controller will generate a SPI interrupt request. | ||
| [2] | RXOVIF | Receive FIFO Overrun Status |
| When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. | ||
| 0 = No overrun in receive FIFO. | ||
| 1 = Overrun in receive FIFO. | ||
| Note: This bit will be cleared by writing 1 to itself. | ||
| [4] | TXTHIF | Transmit FIFO Threshold Interrupt Status (Read Only) |
| 0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. | ||
| 1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. | ||
| Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request. | ||
| [11] | SLVSTIF | Slave Start Interrupt Status (Slave Only) |
| It is used to dedicate that the transfer has started in slave 3-wire mode. | ||
| 0 = Slave does not detect any SPI bus clock transfer since the SSTA_INTEN bit was set to 1. | ||
| The transfer is not started. | ||
| 1 = The transfer has started in Slave 3-wire mode. | ||
| Note 1: It will be cleared as transfer done or by writing one to this bit. | ||
| Note 2: It's a mutual mirror bit of SPI_SLVCTL[11]. | ||
| [15:12] | RXCNT | Receive FIFO Data Count (Read Only) |
| Indicates the valid data count of receive FIFO buffer. | ||
| [16] | UNITIF | SPI Unit-Transfer Interrupt Flag |
| 0 = The transfer does not finish yet. | ||
| 1 = The SPI controller has finished one unit transfer. | ||
| Note 1: This bit will be cleared by writing 1 to itself. | ||
| Note 2: It's a mutual mirror bit of SPI_CTL[16]. | ||
| [20] | SLVTOIF | Time-Out Interrupt Flag |
| 0 = No receive FIFO time-out event. | ||
| 1 = The receive FIFO buffer is not empty and it does not be read over 64 SPI clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. | ||
| When the received FIFO buffer is read by software, the time-out status will be cleared automatically. | ||
| Note: This bit will be cleared by writing 1 to itself. | ||
| [24] | RXEMPTY | Receive FIFO Buffer Empty Indicator (Read Only) |
| 0 = The receive FIFO buffer is not empty. | ||
| 1 = The receive FIFO buffer is empty. | ||
| Note: It's a mutual mirror bit of SPI_CTL[24]. | ||
| [25] | RXFULL | Receive FIFO Buffer Full Indicator (Read Only) |
| 0 = The receive FIFO buffer is not full. | ||
| 1 = The receive FIFO buffer is full. | ||
| Note: It's a mutual mirror bit of SPI_CTL[25]. | ||
| [26] | TXEMPTY | Transmit FIFO Buffer Empty Indicator (Read Only) |
| 0 = The transmit FIFO buffer is not empty. | ||
| 1 = The transmit FIFO buffer is empty. | ||
| Note: It's a mutual mirror bit of SPI_CTL[26]. | ||
| [27] | TXFULL | Transmit FIFO Buffer Full Indicator (Read Only) |
| 0 = The transmit FIFO buffer is not full. | ||
| 1 = The transmit FIFO buffer is full. | ||
| Note: It's a mutual mirror bit of SPI_CTL[27]. | ||
| [31:28] | TXCNT | Transmit FIFO Data Count (Read Only) |
| Indicates the valid data count of transmit FIFO buffer. |
Definition at line 4889 of file Mini55Series.h.
| __IO uint32_t I2C_T::STATUS1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WKIF | I2C Wake-Up Interrupt Flag |
| When chip is woken up from Power-Down mode by I2C, this bit is set to 1. | ||
| Software can write 1 to clear this bit. | ||
| [1] | FULL | I2C TWO LEVEL FIFO FULL |
| This bit indicates TX FIFO full or not when the FIFOEN = 1. | ||
| [2] | EMPTY | I2C TWO LEVEL FIFO EMPTY |
| This bit indicates RX FIFO empty or not when the FIFOEN = 1. | ||
| [3] | OVIF | I2C OVER RUN Status Bit |
| This bit indicates the received FIFO is over run when the FIFOEN = 1. | ||
| [4] | URIF | I2C UNDER RUN Status Bit |
| This bit indicates the transmitted FIFO is under run when the FIFOEN = 1. |
Definition at line 2389 of file Mini55Series.h.
| __IO uint32_t I2C_T::TOCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TOIF | Time-Out Flag |
| This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. | ||
| Note: Software can write 1 to clear this bit. | ||
| [1] | TOCDIV4 | Time-Out Counter Input Clock Divided By 4 |
| 0 = Time-out counter input clock divided by 4 Disabled. | ||
| 1 = Time-out counter input clock divided by 4 Enabled. | ||
| Note: When enabled, the time-out period is extended 4 times. | ||
| [2] | TOCEN | Time-Out Counter Enabled |
| 0 = Time-out counter Disabled. | ||
| 1 = Time-out counter Enabled. | ||
| Note: When the 14-bit time-out counter is enabled, it will start counting when SI is clear. | ||
| Setting 1to the SI flag will reset counter and re-start up counting after SI is cleared. |
Definition at line 2227 of file Mini55Series.h.
| __IO uint32_t UART_T::TOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | TOIC | Time-Out Interrupt Comparator |
| The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. | ||
| Once the content of time-out counter (TOUT_CNT) is equal to that of time-out interrupt comparator (TOIC), a receiver time-out interrupt (RXTOINT) is generated if RXTOIEN (UART_INTEN [4]). | ||
| A new incoming data word or RX FIFO empty clears RXTOINT. | ||
| In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255. | ||
| So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. | ||
| [15:8] | DLY | TX Delay Time Value |
| This field is used to program the transfer delay time between the last stop bit and next start bit. |
Definition at line 6523 of file Mini55Series.h.
| __IO uint32_t ADC_T::TRGDLY |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DELAY | PWM Trigger Delay Timer |
| Set this field will delay ADC start conversion time after PWM trigger. | ||
| PWM trigger delay time is (4 * DELAY) * system clock. |
Definition at line 529 of file Mini55Series.h.
| __O uint32_t SPI_T::TX |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | TX | Data Transmit Register |
| The Data Transmit Registers hold the data to be transmitted in the next transfer. | ||
| Valid bits depend on the transmit bit length field in the CNTRL register. | ||
| For example, if DWIDTH is set to 0x08, the bit TX0[7:0] will be transmitted in next transfer. |
Definition at line 4749 of file Mini55Series.h.
| __IO uint32_t ACMP_T::VREF |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | CRVCTL | Internal Reference Selection |
| Comparator reference voltage = AVDD * (1 / 6 + CRVCTL[3:0] / 24). | ||
| [7] | IREFSEL | CRV Module Output Selection |
| 0 = Band-gap voltage. | ||
| 1 = Internal comparator reference voltage. |
Definition at line 252 of file Mini55Series.h.


Amount In Wallet: {{amountInWallet}}$
Buy Crypto: {{selectedBuyCryptoAmount}}$
Sell Crypto: {{selectedSellCryptoAmount}}$
Amount In Wallet: {{amountInWallet}}$ view_quilt View deposits
| Amount | Transaction Id | Transaction Type | Coin Bought/Sold | Coin Amount | Payment Gateway | Status | Date |
|---|---|---|---|---|---|---|---|
| {{item.amount | currency}} | {{item.txid || item.id}} | {{item.type}} | {{item.coin}} | {{item.crypto_amount}} | {{item.gateway}} | {{item.status}} | {{item.created_at | date:'MM-dd-yy, h:mm a'}} |


This example is a quick exercise to illustrate how the default, static and fixed to top navbar work. It includes the responsive CSS and HTML, so it also adapts to your viewport and device.
To see the difference between static and fixed top navbars, just scroll.
| Id | Name | Amount Left | Amount Free | Price | Coupon | Date | Edit | Delete | Book | |
|---|---|---|---|---|---|---|---|---|---|---|
| 1 | Mark | Otto | @mdo | Mark | Otto | @mdo | Mark | Otto | @mdo | Mark |
| 2 | Mark | Otto | @mdo | Mark | Otto | @112121 | 2323 | 232323 | @mdo | Mark |
| 3 | Mark | Otto | @mdo | Mark | Otto | @mdo | Mark | Otto | @mdo | Mark |
| Id | Name | Amount Left | Amount Free | Price | |
|---|---|---|---|---|---|
| 1 | Mark | Otto | @mdo | Mark | Otto |
| 2 | Mark | Otto | @mdo | Mark | Otto |
| 3 | Mark | Otto | @mdo | Mark | Otto |


Translating from VIVO to the Organization Ontology
For those familiar with representing organizations using the VIVO Ontology, we provide a guide for translating assertions in the VIVO Ontology to assertions in the Organization Ontology 1.
Translating Types
The VIVO Ontology organization types are presented in Table 17 with instructions for translating each. The Organization Ontology separates the concept of what the organization “is” (company, organization part, etc) from what the organization “does” (hospital, library, etc). In many cases, the VIVO Ontology combined these and information about one or the other (“is”, “does”) is missing.
For example, consider vivo:Museum. This assertion of type is actually an assertion of purpose. The type of organization (organization part, nonprofit) is missing. We can assert the museum is an organization, and has a disposition of museum. We may be able to bring additional information to bear and assert a a specific type 2.
Table 17 provides a guide for translating Organizational types to assertions in the Organization Ontology.
VIVO Type |
Organization Ontology Assertions |
|---|---|
Association |
Unknown type. Assert Organization only. Type is often nonprofit. Disposition is association. |
Center |
Unknown type. Assert organization only. Type is often an organization part. Unknown dispositions. Often research. |
College |
Unknown type. Assert organization only. At a US university, an organizational part. At a US university, dispositions of education, service, research |
Company |
Type is Company Disposition is often commerce |
Consortium |
Unknown type. Assert Organization only. Type is often nonprofit Disposition is often association |
CoreLaboratory |
Type is organization part Dispositions are laboratory and service provider |
Department |
Type is organizational part Unknown dispositions |
Division |
Type is organizational part Unknown dispositions |
ExtensionUnit |
Type is organizational part Disposition is agricultural extension |
ERO_00000565 |
Type is organizational part Disposition is technology transfer |
Foundation |
Type may be nonprofit Type may be organizational part May be affiliated with another organization Disposition is philanthropy Disposition may be funder |
FundingOrganization |
Unknown type. Assert organization only. Disposition is funder |
GovernmentAgency |
Type is government organization or organizational part Disposition is unknown |
Hospital |
Unknown type. Assert organization only. Disposition is hospital. |
Institute |
Unknown type. Assert organization only. Disposition is unknown. Often research. |
Laboratory |
Unknown type. Assert organization only. Disposition is laboratory. |
Library |
Unknown type. Assert organization only. Disposition is library. |
Museum |
Unknown type. Assert organization only. Disposition is library. |
Program |
Type is organizational part. Disposition is unknown. |
Publisher |
Type is unknown. Assert organization only. Often type is company. But all others possible. Disposition is publisher. |
ResearchOrganization |
Unknown type. Assert organization only. Disposition is research. |
School |
Type is unknown. Assert organization only. At US university, an organizational part. Disposition is often education. |
ServiceProvidingLaboratory |
Type is unknown. Assert organization only. Dispositions are laboratory and service provider. |
StudentOrganization |
Type is organizational part Disposition is unknown Quality is student led. |
Team |
Type is unknown. Assert organization only. Disposition is unknown 3 |
University |
Type is unknown. Assert organization only. Disposition is university Dispositions are typically education, research, service |
A Cross Index
Table 10 provides a complete cross-reference for all terms in the VIVO 1 Ontology to terms in the Organization Ontology. This is not a translation table. The cross indicates which terms in the Organization Ontology have been linked via annotation property ORG_1000001 - vivo 1 ontology reference with one or more terms in the VIVO 1 Ontology. This “linking” indicates only that the terms are similar in their meaning and/or usage.
Some VIVO 1 terms map to multiple Organization Ontology terms. For example, a ServiceProvidingLaboratory in VIVO 1 is an organizaition with a service providing disposition and a laboratory disposition in the Organization Ontology.
See Table 10.
VIVO 1 Term URI |
See ontology term |
|---|---|
Footnotes
- 1
We intend to provide SPARQL CONSTRUCT queries for automatica translation of VIVO Ontology organization assertions to Organization Ontology assertions in the future. Consider this guide as advice to the adventurous, or to collaborators who would like to draft, test, and contribute such queries.
- 2
Note that additional information is needed. The Metropolitan Museum of Art in New York City is a nonprofit organization. The Florida Museum of Natural History in Gainesville, Florida, is an organizational part of the University of Florida. In the VIVO Ontology, both would be asserted to be type vivo:Museum. In the Organization Ontology, the first would be asserted to be nonprofit, the second organization part. Both would be asserted to have disposition museum.
- 3
Team may mean “sports team” or “project team” or other. A sports team may be formal, such as Manchester United Football Club, or informal as in “my weekly bowling team.” A project team may be considered part of an organization, or informally organized to move work forward.


Sunday School is offered for children age 3 through High School for one hour each Sunday from September through May. Preschool (3's and 4's), 7th/8th Grade, and High School meet in self-contained classes. Grades K-6 meet in Fellowship Hall for singing and prayers at Sunday School Opening, and then travel by age groups to a different workshop each week.
Over a five-week period, children rotate through five workshops such as arts & crafts, science & nature, cooking, video, games, storytelling, and more. We use our own curriculum for our Workshop Rotational Sunday School and our teachers are our parents! Congregational members, staff, grandparents, and youth are teachers too.


Issue 37
Welcome to Haskell Weekly! Haskell is an advanced, purely functional programming language. This is a weekly summary of what’s going on in its community. You can subscribe to the email newsletter or the Atom feed.
Want to contribute to Haskell Weekly? Send us a message on Twitter or open an issue on GitHub.
News from the Haskell community
-
The GHC team is happy to at last announce the 8.0.2 release of the Glasgow Haskell Compiler. This is the second release of the 8.0 series and fixes nearly two-hundred bugs. This release is the result of six months of effort by the GHC development community.
-
Fast Haskell: Competing with C at parsing XML
In this post we’re going to look at parsing XML in Haskell, how it compares with an efficient C parser, and steps you can take in Haskell to build a fast library from the ground up. We’re going to get fairly detailed and get our hands dirty.
-
Glance is a visual syntax for the programming language Haskell. The goal of this project is to increase programmer happiness and productivity by allowing programmers to create and understand programs in new and different ways. Currently, the Glance executable produces a visual representation of your code in the form of an SVG image when given a textual Haskell source file. In the future, I hope to create a visual editor for Haskell.
-
This blog post introduces graql-haskell, which is a library that lets you interface with the Grakn knowledge graph using Haskell. It is ideal for applications like data science — using Grakn as the database, Haskell for data processing and Graql as the intermediary between the two.
-
An interview with Haskell developer Edward Kmett
For the most part I look for something that should exist for some deep underlying mathematical reason that doesn’t yet exist in code in a reusable form and try to figure out how to bring it about.
-
Visible type application in GHC 8
GHC 8.0 introduced a new GHC extension named TypeApplications which allows us to give explicit type arguments to a polymorphic function.
-
Nested monadic loops may cause space leaks
These nested loops happen often in server-side programming. About a year ago, when I worked for Signal Vine, this happened to my code: the inner loop was a big streaming computation; the outer loop was something that would restart the inner loop should it fail.  To find out, let’s trace the program execution on the STG level.
-
Linearity, uniqueness, and Haskell
There is a group of people working on a proposal for adding linear types to Haskell. In this blog post I will attempt to put this proposal in some context. I will explain what linearity is and how it relates to its close cousin uniqueness typing, and I will compare the proposal to some other ways of doing things. My hope is that this will make the work more accessible.
Package of the week
This week’s package of the week is Bench, a more powerful alternative to the time command. It is a command-line tool to benchmark a command using Criterion.
Send us a message on Twitter to nominate next week’s package!


[ht::head {Map and Time Series Displays}] <%nochildlist%> When you are viewing a LiDAR data file entry (e.g., LVIS Costa Rica) choose the [ht::menu {LiDAR Data} {LiDAR Map and Chart}] menu for an interactive map and timeseries chart of the data. If the LiDAR data file contains waveforms (as the example above does) there will also be an image of the waveform for a given point displayed. [ht::cimg images/chart.png {LiDAR Map and Chart} {border=0 width=800}] Clicking on the time series image will show the approximate location in the map of that point in the LiDAR data and will also create and show the waveform at that point.
The CSV link will give a CSV file of the displayed waveform.
The Settings section allows you to hide the map and choose other fields to display in the time series: [ht::cimg images/chartsettings.png {Chart Settings} {border=0}] The Waveform Background menu allows you to show the waveform fully expanded to the size of the time series chart. Normally the waveform is shown at the actual height as measured. [ht::foot]


This is a project for the course IS601 Web Systems and Development offered at the New Jersey Institute of Technology, taught by Professor Williams. Throughout this website we will discuss how the internet works. The internet is defined as a loosely organized international collaboration of autonomous, interconnected networks, which support host to host communication through voluntary adherence to open protocols and procedures.


@Transactional
Annotate methods with @Transactional
and all database queries and changes
will occur in a single transaction.
The transaction will use the default database, be put into the "thread local scope" and will commit if the methods completes successfully.
@Transactional
public void process(OffsetDateTime startOffset) {
...
customer.save();
contact.save();
}
Transaction.current()
Use Transaction.current()
to return the current transaction from "thread local scope"
of the default database.
@Transactional
public void process(OffsetDateTime startOffset) {
...
Transaction txn = Transaction.current();
...
}
use database.currentTransaction()
to return the current transaction for a given database
that is typically not the default database.
Database otherDb = DB.byName("other");
Transaction txn = otherDb.currentTransaction();
beginTransaction()
As an alternative to @Transactional we can use beginTransaction()
to
start an explicit transaction. The transaction is put into the "thread local scope" and used
by any subsequent queries, save, delete etc.
We should use a try with resources block to ensure that the transaction is closed if any error occurs in the block.
try (Transaction transaction = DB.beginTransaction()) {
// do stuff...
Customer customer = ...
customer.save();
Order order = ...
order.save();
transaction.commit();
}
Kotlin transaction.use { }
Kotlin use
is used similarly to try with resources to ensure
the transaction is closed.
DB.beginTransaction().use { transaction ->
// do stuff...
val customer = ...
customer.save();
val order = ...
order.save();
transaction.commit()
}
commit(), rollback(), end()
Often with a try with resources block we don't need explicit calls to
transaction.rollback()
or transaction.end()
like the
example for beginTransaction() above.
rollback()
will rollback the transaction and commonly we use that
in a catch block.
end()
will rollback the transaction if it has not already been committed.
We primarily use end()
in a finally block.
Transaction transaction = DB.beginTransaction()
try {
// do stuff...
Customer customer = ...
customer.save();
Order order = ...
order.save();
transaction.commit();
} catch (SomeException e) {
transaction.rollback();
} finally {
transaction.end(); // rollback if not committed
}
commitAndContinue()
Occasionally in larger transactions we get to a point where we would like
to commit the changes to this point but then carry on processing with
subsequent changes potentially failing.
We use transaction.commitAndContinue()
for this.
setRollbackOnly()
We use transaction.setRollbackOnly()
such that a transaction
will not commit but only rollback.
We can make use of this when some processing has a sort of "preview" mode where we process changes but then do not commit. This can also be useful in some testing scenarios.
createTransaction()
database.createTransaction()
will create a transaction but it will
NOT be put in "thread local scope". We generally use this when we have
a transaction that we want to pass between threads.
For example: start a transaction, obtain a row lock, if that is successful pass the transaction to a task to execute via a background thread.
When we use createTransaction()
we must explicitly use the transaction
in queries and saving etc. We explicitly specify the transaction with query beans
via ... and model.save(transaction) etc.
try (Transaction transaction = DB.getDefault().createTransaction()) {
...
var customer = new QCustomer(transaction) // explicit transaction
.name.eq("Rob")
.findOne();
...
customer.update(transaction); // explicit transaction
}
Implicit transactions
When no transactions are specified explicitly Ebean will create a transaction to perform the action.
Query - read only transaction
For queries Ebean will look to use a read only transaction. If a Read Only DataSource
has
be configured Ebean will look to use that by default.
Insert, Update, Delete
For all persist requests like save, insert, update, delete Ebean will create a transaction and perform
a COMMIT
at the end of the operation.


Top Ten
- Top 5 Places I've been
- Rome, Italy
- Zurich, Switzerland
- Florence, Italy
- London, England
- San Francisco, USA
- Top 10 Video Games
- Persona Series
- Silent Hill 2
- Zero Escape Series
- Ghost Trick
- Last of Us
- Shadow Hearts Covenant
- Final Fantasy VI
- Ico
- Bioshock Infinite
- UnderTale


Bruce Perens: How Many Open Source Licenses Do You Need? (itmanagement.earthweb.com)
submitted 12 hours ago by jammag
Bruce Perens: How Many Open Source Licenses Do You Need? (itmanagement.earthweb.com)
submitted 12 hours ago by jammag
So were Jeff / Joel / Uncle Bob discussing happiness and fitness ? (blog.dhananjaynene.com)
submitted 12 hours ago by dnene
Sony Vaio FW Series: A Developer's Review (antoniocangiano.com)
submitted 13 hours ago by acangiano
How to fake momentum in three easy steps (blog.labnotes.org)
submitted 14 hours ago by homoiconic
BeOS was developed properly, from the ground up. (pinderkent.phumblog.com)
submitted 14 hours ago by SPINKTRONIX
Red Hat Enlists Community in Fight Against Patent Trolls (osnews.com)
submitted 14 hours ago by LudoA
Type-safe prototype-based programming with first-class selectors and namespaces in OCaml (eigenclass.org)
submitted 15 hours ago by gst
"Poderosa is a tabbed terminal emulator for Windows." Great if you use Cygwin. (en.poderosa.org)
submitted 15 hours ago by zouhair
pymake: A Mostly GNU-compatible `make`, Written in Python (benjamin.smedbergs.us)
submitted 15 hours ago by juri
How to add a new column into the table between the available columns? (sql-ex.ru)
submitted 16 hours ago by msi
Can Asus' touch device give us a taste of the future of Windows? (sciandtechnology.blogspot.com)
submitted 16 hours ago by guardknight
What are some good ways/concepts of internal string representation? (groups.google.com)
submitted 16 hours ago by queus
How to disable asp.net button with JQuery (isolutionteam.co.uk)
submitted 17 hours ago by naveedkamboh
Has anyone ever used an air pressure sensor and an inner tube as a bump sensor for a robot? (self.programming)
submitted 17 hours ago by PossumTucker
"Hardware manufacturers embrace Linux" - music to my ears. (mybroadband.co.za)
submitted 17 hours ago by PossumTucker
Auto Scrolling Effect with javascript and DHTML. (9lessons.blogspot.com)
submitted 17 hours ago by foxscan
Writing a Good Technical RÃ©sumÃ©/CV (blog.looplabel.net) (blog.looplabel.net)
submitted 17 hours ago by looplabel


This package contains the LOW level Database code, such as managing JDBC connections and the DB Pool


ClassDep
ClassDep
is used to analyze a set of classes and determine on
what other classes they directly or indirectly depend.
classdep.jar
,
that can be used to run ClassDep
. The advantage of using
this JAR file is that it automatically loads tools.jar
from your Java(TM) 2 SDK installation, if required.


func ConfigBlock(reader blockledger.Reader) *cb.Block
ConfigBlock retrieves the last configuration block from the given ledger. Panics on failure.
BlockWriter efficiently writes the blockchain to disk. To safely use BlockWriter, only one thread should interact with it. BlockWriter will spawn additional committing go routines and handle locking so that these other go routines safely interact with the calling one.
type BlockWriter struct {
// contains filtered or unexported fields
}
func (bw *BlockWriter) CreateNextBlock(messages []*cb.Envelope) *cb.Block
CreateNextBlock creates a new block with the next block number, and the given contents.
func (bw *BlockWriter) WriteBlock(block *cb.Block, encodedMetadataValue []byte)
WriteBlock should be invoked for blocks which contain normal transactions. It sets the target block as the pending next block, and returns before it is committed. Before returning, it acquires the committing lock, and spawns a go routine which will annotate the block with metadata and signatures, and write the block to the ledger then release the lock. This allows the calling thread to begin assembling the next block before the commit phase is complete.
func (bw *BlockWriter) WriteConfigBlock(block *cb.Block, encodedMetadataValue []byte)
WriteConfigBlock should be invoked for blocks which contain a config transaction. This call will block until the new config has taken effect, then will return while the block is written asynchronously to disk.
ChainSupport holds the resources for a particular channel.
type ChainSupport struct { msgprocessor.Processor *BlockWriter consensus.Chain crypto.LocalSigner // contains filtered or unexported fields }
func (cs *ChainSupport) Append(block *cb.Block) error
Append appends a new block to the ledger in its raw form, unlike WriteBlock that also mutates its metadata.
func (cs *ChainSupport) Block(number uint64) *cb.Block
Block returns a block with the following number, or nil if such a block doesn't exist.
func (cs *ChainSupport) BlockCutter() blockcutter.Receiver
BlockCutter returns the blockcutter.Receiver instance for this channel.
func (cs *ChainSupport) ChainID() string
ChainID passes through to the underlying configtx.Validator
func (cs *ChainSupport) ConfigProto() *cb.Config
ConfigProto passes through to the underlying configtx.Validator
func (cs *ChainSupport) ProposeConfigUpdate(configtx *cb.Envelope) (*cb.ConfigEnvelope, error)
ProposeConfigUpdate passes through to the underlying configtx.Validator
func (cs *ChainSupport) Reader() blockledger.Reader
func (cs *ChainSupport) Sequence() uint64
Sequence passes through to the underlying configtx.Validator
func (cs *ChainSupport) Signer() crypto.LocalSigner
Signer returns the crypto.Localsigner for this channel.
func (cs *ChainSupport) Validate(configEnv *cb.ConfigEnvelope) error
Validate passes through to the underlying configtx.Validator
func (cs *ChainSupport) VerifyBlockSignature(sd []*cb.SignedData, envelope *cb.ConfigEnvelope) error
VerifyBlockSignature verifies a signature of a block. It has an optional argument of a configuration envelope which would make the block verification to use validation rules based on the given configuration in the ConfigEnvelope. If the config envelope passed is nil, then the validation rules used are the ones that were applied at commit of previous blocks.
Registrar serves as a point of access and control for the individual channel resources.
type Registrar struct {
// contains filtered or unexported fields
}
func NewRegistrar( config localconfig.TopLevel, ledgerFactory blockledger.Factory, signer crypto.LocalSigner, metricsProvider metrics.Provider, callbacks ...channelconfig.BundleActor) *Registrar
NewRegistrar produces an instance of a *Registrar.
func (r *Registrar) BroadcastChannelSupport(msg *cb.Envelope) (*cb.ChannelHeader, bool, *ChainSupport, error)
BroadcastChannelSupport returns the message channel header, whether the message is a config update and the channel resources for a message or an error if the message is not a message which can be processed directly (like CONFIG and ORDERER_TRANSACTION messages)
func (r *Registrar) ChannelsCount() int
ChannelsCount returns the count of the current total number of channels.
func (r *Registrar) CreateBundle(channelID string, config *cb.Config) (channelconfig.Resources, error)
CreateBundle calls channelconfig.NewBundle
func (r *Registrar) CreateChain(chainName string)
CreateChain makes the Registrar create a chain with the given name.
func (r *Registrar) GetChain(chainID string) *ChainSupport
GetChain retrieves the chain support for a chain if it exists.
func (r *Registrar) Initialize(consenters map[string]consensus.Consenter)
func (r *Registrar) NewChannelConfig(envConfigUpdate *cb.Envelope) (channelconfig.Resources, error)
NewChannelConfig produces a new template channel configuration based on the system channel's current config.
func (r *Registrar) SystemChannelID() string
SystemChannelID returns the ChannelID for the system channel.


--- layout: archive title: Zulip Chat Archive permalink: /stream/113488-general/topic/Newbie.20error.html ---
I've got the following code
import algebra.ring data.finsupp variables {R : Type*} [ring R] section free_module definition free_module (S : Type*) := finsupp S R variables {S : Type*} instance : module R (free_module S) := sorry end free_module
And this is the error
don't know how to synthesize placeholder context: R : Type u_1, _inst_1 : ring R, S : Type u_2 ⊢ Type ?
Aah, I should point out that the red squiggles are under free_module
in the line with sorry
Shouldn't R
be explicit in free_module
? It is not inferrable
I think the error means that it can't figure out in which universe free_module S
lives
Aah, Ok, is that the problem. I thought it was automatically included, since I declared it a variable
Or should I then use ()
instead of {}
it isn't a parameter
it is included, but the later use might refer to a different R
Ok... well, that fixed my problem. Thanks a lot!
no, don't use parameter
you won't be able to use it once you leave the section
Hmm, what do you mean?
I now have
import algebra.ring data.finsupp variables {R : Type*} [ring R] section free_module definition free_module (R : Type*) [ring R] (S : Type*) := finsupp S R variables {S : Type*} instance : module R (free_module R S) := begin split, -- tactic fails end end free_module
Is that wrong?
never mind
that isn't wrong
Ok, I don't mind learning a better way (-;
So, why is split
failing? I expected to get 4 goals, according to the 4 axioms of a module
constructor
but you don't want to use it since it extends
something
maybe if you really want to stay in tactic mode, do refine {..}
Well, I don't want to stay in tactic mode. It is just that I have no clue how to do things in term mode. And tactic mode helps me a bit (-;
So what would be the proper way to prove this instance
?
instance : module R (free_module R S) := { smul := _, smul_add := _ }
etc
Ok, thanks! I'll try to do that.
Lol, this is already in finsupp
: to_module
lol
The errors continue:
import algebra.ring data.finsupp variables {R : Type*} [decidable_eq R] [ring R] section free_module definition free_module (R : Type*) [ring R] (S : Type*) := finsupp S R variables {S : Type*} [decidable_eq S] instance : add_comm_monoid (free_module R S) := finsupp.add_comm_monoid instance : module R (free_module R S) := finsupp.to_module end free_module section generators variables {M : Type*} [module R M] definition natural_map (S : set M) : free_module R S → M := λ x, x.sum (λ s r, r • s) definition generated_submodule (S : set M) := set.range (natural_map S) -- fails definition is_finitely_generated (M : Type*) [module R M] : Prop := ∃ S : finset M, generated_submodule {x | x ∈ S} = set.univ M -- fails end generators
Errors:
generators.lean:19:57: error failed to synthesize type class instance for M : Type u_2, S : set M ⊢ module ?m_1 M generators.lean:19:57: error don't know how to synthesize placeholder context: M : Type u_2, S : set M ⊢ Type ?
But I am telling it that M is a module over R, so why can't it unify ?m_1
with R
?
You started a new section so Lean has forgotten about the variable R
wait
that doesn't seem to be true
It seems to be because you don't ever mention R so the type class inference doesn't kick in
definition generated_submodule (S : set M) [module R M] := set.range (natural_map S) -- works
Type class inference is a strange thing
include R
I would still not say I had completely got the hang of it
include R definition generated_submodule (S : set M) := set.range (natural_map S) -- works
Kenny's fix
What does include
do?
I thought this was for including variable names in tactic proofs
As for the equality failing
set.univ : Π {α : Type u}, set α
set.univ
doesn't take M
, it guesses it.
definition is_finitely_generated (M : Type*) [module R M] : Prop := ∃ S : finset M, generated_submodule {x | x ∈ S} = set.univ -- works
Recently I realised that I pretty fully understood most Lean errors
i.e. I can look at the error and actually figure out what is wrong with my code, in many cases
type mismatch at application generated_submodule {x : M | x ∈ S} = set.univ M term set.univ M has type Prop : Type but is expected to have type set M : Type ?
says "the right hand side is supposed to have type set M
but it has type Prop
so you have not written what you meant to write -- it doesn't typecheck."
You are attempting to assert that two sets are equal
so the correct type is set M
so the problem is that set.univ M
has type Prop instead of type set M
and now you look at what set.univ
actually does by hovering your mouse over set.univ
and you see your error
I would urge you @Johan Commelin to learn to read errors so you can find out the problem.
Sometimes the problem is that type class inference has failed. Type class inference is just something you have to get the hang of and I had to ask and ask here about it -- see my typeclass inference woes thread
But for other errors, try and make it so that there is exactly one error (i.e put sorry everywhere else) and then try and read the error.
And then hope that you can fix it
Ok, thanks! I hope to get the hang of it as well...
set.univ : set M
should help
Or perhaps @set.univ M
Last updated: Apr 24 2020 at 19:02 UTC


WITNESS LIST Judiciary Committee February 28, 2005-2:00P HB 564 For: Rye, Dale (Williamson County Attorney) On: Higginbotham, Judge Don (County Courts at Law, Williamson County, TX) HB 679 Against: Wallace, Michael W. (Self) On: Spalding, Judy M. (State Commission on Judicial Conduct) HB 835 For: Bradley, John (Self and Williamson County) On: Stubblefield, Judge Bill (Self) Registering, but not testifying: For: McCown, Jana K. (Williamson County District Attorney) HB 968 For: Spataro, Susan A. (Self and Travis County District Judges (Criminal Branch), Travis Commissioner's Court, Travis County Auditor) Registering, but not testifying: For: Bacon, April (Self) HB 1119 For: Lee, Randal (Cass County District Attorney) HB 1142 Registering, but not testifying: For: Mendez, Mark (Tarrant County Commissioners Court) HB 1189 For: Pardue, Craig (Dallas County) Rolater, Asst. Dist, John (Bill Hill, Dallas County Criminal District Attorney) HB 1190 For: Brigance, John (Trust Financial Services Division, Texas Bankers Association) Karisch, Glenn M. (Self and Real Estate, Probate and Trust Law Section of the State Bar of Texas) Pargaman, William (Real Estate, Probate and Trust Law Section of the State Bar of Texas) Against: Herman, Guy (Self) HB 1192 For: Douglas, Terry (Texas Justice Court Judges Association) Woolley, Leah (Texas Justice Court Judges Assoc.) Against: Mathews, Cindy (JPCA- Justices of the Peace and Constables Association) Vasquez Program Ma, Michael (Texas Conference of Urban Counties) Registering, but not testifying: For: Pareya, David (Texas Justice Court Judges Assn.) Ralech, Paul (Justice Court Judges Association) Against: Mayfield, Connie (Self) Phillips, Kaye (Self) Trammell, DeLynn (Self)