llvm-mca - LLVM Machine Code Analyzer¶
SYNOPSIS¶
llvm-mca [options] [input]
DESCRIPTION¶
llvm-mca is a performance analysis tool that uses information available in LLVM (e.g. scheduling models) to statically measure the performance of machine code in a specific CPU.
Performance is measured in terms of throughput as well as processor resource consumption. The tool currently works for processors with an out-of-order backend, for which there is a scheduling model available in LLVM.
The main goal of this tool is not just to predict the performance of the code when run on the target, but also help with diagnosing potential performance issues.
Given an assembly code sequence, llvm-mca estimates the Instructions Per Cycle (IPC), as well as hardware resource pressure. The analysis and reporting style were inspired by the IACA tool from Intel.
For example, you can compile code with clang, output assembly, and pipe it directly into llvm-mca for analysis:
$ clang foo.c -O2 -target x86_64-unknown-unknown -S -o - | llvm-mca -mcpu=btver2
Or for Intel syntax:
$ clang foo.c -O2 -target x86_64-unknown-unknown -mllvm -x86-asm-syntax=intel -S -o - | llvm-mca -mcpu=btver2
OPTIONS¶
If input
is “-
” or omitted, llvm-mca reads from standard
input. Otherwise, it will read from the specified filename.
If the -o
option is omitted, then llvm-mca will send its output
to standard output if the input is from standard input. If the -o
option specifies “-
“, then the output will also be sent to standard output.
-
-help
¶
Print a summary of command line options.
-
-mtriple
=<target triple>
¶ Specify a target triple string.
-
-march
=<arch>
¶ Specify the architecture for which to analyze the code. It defaults to the host default target.
-
-mcpu
=<cpuname>
¶ Specify the processor for which to analyze the code. By default, the cpu name is autodetected from the host.
-
-output-asm-variant
=<variant id>
¶ Specify the output assembly variant for the report generated by the tool. On x86, possible values are [0, 1]. A value of 0 (vic. 1) for this flag enables the AT&T (vic. Intel) assembly format for the code printed out by the tool in the analysis report.
-
-dispatch
=<width>
¶ Specify a different dispatch width for the processor. The dispatch width defaults to field ‘IssueWidth’ in the processor scheduling model. If width is zero, then the default dispatch width is used.
-
-register-file-size
=<size>
¶ Specify the size of the register file. When specified, this flag limits how many physical registers are available for register renaming purposes. A value of zero for this flag means “unlimited number of physical registers”.
-
-iterations
=<number of iterations>
¶ Specify the number of iterations to run. If this flag is set to 0, then the tool sets the number of iterations to a default value (i.e. 100).
-
-noalias
=<bool>
¶ If set, the tool assumes that loads and stores don’t alias. This is the default behavior.
-
-lqueue
=<load queue size>
¶ Specify the size of the load queue in the load/store unit emulated by the tool. By default, the tool assumes an unbound number of entries in the load queue. A value of zero for this flag is ignored, and the default load queue size is used instead.
-
-squeue
=<store queue size>
¶ Specify the size of the store queue in the load/store unit emulated by the tool. By default, the tool assumes an unbound number of entries in the store queue. A value of zero for this flag is ignored, and the default store queue size is used instead.
-
-timeline
¶
Enable the timeline view.
-
-timeline-max-iterations
=<iterations>
¶ Limit the number of iterations to print in the timeline view. By default, the timeline view prints information for up to 10 iterations.
-
-timeline-max-cycles
=<cycles>
¶ Limit the number of cycles in the timeline view. By default, the number of cycles is set to 80.
-
-resource-pressure
¶
Enable the resource pressure view. This is enabled by default.
-
-register-file-stats
¶
Enable register file usage statistics.
-
-dispatch-stats
¶
Enable extra dispatch statistics. This view collects and analyzes instruction dispatch events, as well as static/dynamic dispatch stall events. This view is disabled by default.
-
-scheduler-stats
¶
Enable extra scheduler statistics. This view collects and analyzes instruction issue events. This view is disabled by default.
-
-retire-stats
¶
Enable extra retire control unit statistics. This view is disabled by default.
-
-instruction-info
¶
Enable the instruction info view. This is enabled by default.
-
-all-stats
¶
Print all hardware statistics. This enables extra statistics related to the dispatch logic, the hardware schedulers, the register file(s), and the retire control unit. This option is disabled by default.
-
-all-views
¶
Enable all the view.
-
-instruction-tables
¶
Prints resource pressure information based on the static information available from the processor model. This differs from the resource pressure view because it doesn’t require that the code is simulated. It instead prints the theoretical uniform distribution of resource pressure for every instruction in sequence.
EXIT STATUS¶
llvm-mca returns 0 on success. Otherwise, an error message is printed to standard error, and the tool returns 1.
USING MARKERS TO ANALYZE SPECIFIC CODE BLOCKS¶
llvm-mca allows for the optional usage of special code comments to
mark regions of the assembly code to be analyzed. A comment starting with
substring LLVM-MCA-BEGIN
marks the beginning of a code region. A comment
starting with substring LLVM-MCA-END
marks the end of a code region. For
example:
# LLVM-MCA-BEGIN My Code Region
...
# LLVM-MCA-END
Multiple regions can be specified provided that they do not overlap. A code region can have an optional description. If no user-defined region is specified, then llvm-mca assumes a default region which contains every instruction in the input file. Every region is analyzed in isolation, and the final performance report is the union of all the reports generated for every code region.
Inline assembly directives may be used from source code to annotate the assembly text:
int foo(int a, int b) {
__asm volatile("# LLVM-MCA-BEGIN foo");
a += 42;
__asm volatile("# LLVM-MCA-END");
a *= b;
return a;
}
HOW LLVM-MCA WORKS¶
llvm-mca takes assembly code as input. The assembly code is parsed
into a sequence of MCInst with the help of the existing LLVM target assembly
parsers. The parsed sequence of MCInst is then analyzed by a Pipeline
module
to generate a performance report.
The Pipeline module simulates the execution of the machine code sequence in a loop of iterations (default is 100). During this process, the pipeline collects a number of execution related statistics. At the end of this process, the pipeline generates and prints a report from the collected statistics.
Here is an example of a performance report generated by the tool for a
dot-product of two packed float vectors of four elements. The analysis is
conducted for target x86, cpu btver2.  The total number of simulated micro opcodes (uOps) is also 900.
The report is structured in three main sections. The first section collects a few performance numbers; the goal of this section is to give a very quick overview of the performance throughput. Important performance indicators are IPC, uOps Per Cycle, and Block RThroughput (Block Reciprocal Throughput).
IPC is computed dividing the total number of simulated instructions by the total number of cycles. In the absence of loop-carried data dependencies, the observed IPC tends to a theoretical maximum which can be computed by dividing the number of instructions of a single iteration by the Block RThroughput.
Field ‘uOps Per Cycle’ is computed dividing the total number of simulated micro opcodes by the total number of cycles. A delta between Dispatch Width and this field is an indicator of a performance issue. In the absence of loop-carried data dependencies, the observed ‘uOps Per Cycle’ should tend to a theoretical maximum throughput which can be computed by dividing the number of uOps of a single iteration by the Block RThroughput.
Field uOps Per Cycle is bounded from above by the dispatch width. That is because the dispatch width limits the maximum size of a dispatch group. Both IPC and ‘uOps Per Cycle’ are limited by the amount of hardware parallelism. The availability of hardware resources affects the resource pressure distribution, and it limits the number of instructions that can be executed in parallel every cycle. A delta between Dispatch Width and the theoretical maximum uOps per Cycle (computed by dividing the number of uOps of a single iteration by the Block RTrhoughput) is an indicator of a performance bottleneck caused by the lack of hardware resources. In general, the lower the Block RThroughput, the better.
In this example, uOps per iteration/Block RThroughput
is 1.50. Since there
are no loop-carried dependencies, the observed uOps Per Cycle is expected to
approach 1.50 when the number of iterations tends to infinity. The delta between
the Dispatch Width (2.00), and the theoretical maximum uOp throughput (1.50) is
an indicator of a performance bottleneck caused by the lack of hardware
resources, and the Resource pressure view can help to identify the problematic
resource usage.
The second section of the report shows the latency and reciprocal throughput of every instruction in the sequence. That section also reports extra information related to the number of micro opcodes, and opcode properties (i.e., ‘MayLoad’, ‘MayStore’, and ‘HasSideEffects’).
The third section is the Resource pressure view. This view reports the average number of resource cycles consumed every iteration by instructions for every processor resource unit available on the target. Information is structured in two tables. The first table reports the number of resource cycles spent on average every iteration. The second table correlates the resource cycles to the machine instruction in the sequence. For example, every iteration of the instruction vmulps always executes on resource unit [6] (JFPU1 - floating point pipeline #1), consuming an average of 1 resource cycle per iteration. Note that on AMD Jaguar, vector floating-point multiply can only be issued to pipeline JFPU1, while horizontal floating-point additions can only be issued to pipeline JFPU0.
The resource pressure view helps with identifying bottlenecks caused by high usage of specific hardware resources. Situations with resource pressure mainly concentrated on a few resources should, in general, be avoided. Ideally, pressure should be uniformly distributed between multiple resources.
Timeline View¶
The timeline view produces a detailed report of each instruction’s state
transitions through an instruction pipeline. This view is enabled by the
command line option -timeline
. As instructions transition through the
various stages of the pipeline, their states are depicted in the view report.
These states are represented by the following characters:
- D : Instruction dispatched.
- e : Instruction executing.
- E : Instruction executed.
- R : Instruction retired.
- = : Instruction already dispatched, waiting to be executed.
- - : Instruction executed, waiting to be retired.
Below is the timeline view for a subset of the dot-product example located in
test/tools/llvm-mca/X86/BtVer2/dot-product.s
and processed by
llvm-mca using the following command:
$ llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=3 -timeline dot-product.s
Timeline view:
012345
Index<PHONE_NUMBER>
[0,0] DeeER. . . vmulps %xmm0, %xmm1, %xmm2
[0,1] D==eeeER . . vhaddps %xmm2, %xmm2, %xmm3
[0,2] .D====eeeER . vhaddps %xmm3, %xmm3, %xmm4
[1,0] .DeeE-----R . vmulps %xmm0, %xmm1, %xmm2
[1,1] . D=eeeE---R . vhaddps %xmm2, %xmm2, %xmm3
[1,2] . D====eeeER . vhaddps %xmm3, %xmm3, %xmm4
[2,0] . DeeE-----R . vmulps %xmm0, %xmm1, %xmm2
[2,1] . D====eeeER . vhaddps %xmm2, %xmm2, %xmm3
[2,2] . D======eeeER vhaddps %xmm3, %xmm3, %xmm4
Average Wait times (based on the timeline view):
[0]: Executions
[1]: Average time spent waiting in a scheduler's queue
[2]: Average time spent waiting in a scheduler's queue while ready
[3]: Average time elapsed from WB until retire stage
[0] [1] [2] [3]
0. 3 1.0 1.0 3.3 vmulps %xmm0, %xmm1, %xmm2
1. 3 3.3 0.7 1.0 vhaddps %xmm2, %xmm2, %xmm3
2. 3 5.7 0.0 0.0 vhaddps %xmm3, %xmm3, %xmm4
The timeline view is interesting because it shows instruction state changes during execution. It also gives an idea of how the tool processes instructions executed on the target, and how their timing information might be calculated.
The timeline view is structured in two tables. The first table shows instructions changing state over time (measured in cycles); the second table (named Average Wait times) reports useful timing statistics, which should help diagnose performance bottlenecks caused by long data dependencies and sub-optimal usage of hardware resources.
An instruction in the timeline view is identified by a pair of indices, where
the first index identifies an iteration, and the second index is the
instruction index (i.e., where it appears in the code sequence). Since this
example was generated using 3 iterations: -iterations=3
, the iteration
indices range from 0-2 inclusively.
Excluding the first and last column, the remaining columns are in cycles. Cycles are numbered sequentially starting from 0.
From the example output above, we know the following:
- Instruction [1,0] was dispatched at cycle 1.
- Instruction [1,0] started executing at cycle 2.
- Instruction [1,0] reached the write back stage at cycle 4.
- Instruction [1,0] was retired at cycle 10.
Instruction [1,0] (i.e., vmulps from iteration #1) does not have to wait in the scheduler’s queue for the operands to become available. By the time vmulps is dispatched, operands are already available, and pipeline JFPU1 is ready to serve another instruction. So the instruction can be immediately issued on the JFPU1 pipeline. That is demonstrated by the fact that the instruction only spent 1cy in the scheduler’s queue.
There is a gap of 5 cycles between the write-back stage and the retire event. That is because instructions must retire in program order, so [1,0] has to wait for [0,2] to be retired first (i.e., it has to wait until cycle 10).
In the example, all instructions are in a RAW (Read After Write) dependency chain. Register %xmm2 written by vmulps is immediately used by the first vhaddps, and register %xmm3 written by the first vhaddps is used by the second vhaddps. Long data dependencies negatively impact the ILP (Instruction Level Parallelism).
In the dot-product example, there are anti-dependencies introduced by instructions from different iterations. However, those dependencies can be removed at register renaming stage (at the cost of allocating register aliases, and therefore consuming physical registers).
Table Average Wait times helps diagnose performance issues that are caused by the presence of long latency instructions and potentially long data dependencies which may limit the ILP. Note that llvm-mca, by default, assumes at least 1cy between the dispatch event and the issue event.
When the performance is limited by data dependencies and/or long latency instructions, the number of cycles spent while in the ready state is expected to be very small when compared with the total number of cycles spent in the scheduler’s queue. The difference between the two counters is a good indicator of how large of an impact data dependencies had on the execution of the instructions. When performance is mostly limited by the lack of hardware resources, the delta between the two counters is small. However, the number of cycles spent in the queue tends to be larger (i.e., more than 1-3cy), especially when compared to other low latency instructions.
Extra Statistics to Further Diagnose Performance Issues¶
The -all-stats
command line option enables extra statistics and performance
counters for the dispatch logic, the reorder buffer, the retire control unit,
and the register file.
Below is an example of -all-stats
output generated by llvm-mca
for 300 iterations of the dot-product example discussed in the previous
sections.
Dynamic Dispatch Stall Cycles:
RAT - Register unavailable: 0
RCU - Retire tokens unavailable: 0
SCHEDQ - Scheduler full: 272 (44.6%)
LQ - Load queue full: 0
SQ - Store queue full: 0
GROUP - Static restrictions on the dispatch group: 0
Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
[# dispatched], [# cycles]
0, 24 (3.9%)
1, 272 (44.6%)
2, 314 (51.5%)
Schedulers - number of cycles where we saw N instructions issued:
[# issued], [# cycles]
0, 7 (1.1%)
1, 306 (50.2%)
2, 297 (48.7%)
Scheduler's queue usage:
[1] Resource name.
[2] Average number of used buffer entries.
[3] Maximum number of used buffer entries.
[4] Total number of buffer entries.
[1] [2] [3] [4]
JALU01 0 0 20
JFPU01 17 18 18
JLSAGU 0 0 12
Retire Control Unit - number of cycles where we saw N instructions retired:
[# retired], [# cycles]
0, 109 (17.9%)
1, 102 (16.7%)
2, 399 (65.4%)
Total ROB Entries: 64
Max Used ROB Entries: 35 ( 54.7% )
Average Used ROB Entries per cy: 32 ( 50.0% )
Register File statistics:
Total number of mappings created: 900
Max number of mappings used: 35
* Register File #1 -- JFpuPRF:
Number of physical registers: 72
Total number of mappings created: 900
Max number of mappings used: 35
* Register File #2 -- JIntegerPRF:
Number of physical registers: 64
Total number of mappings created: 0
Max number of mappings used: 0
If we look at the Dynamic Dispatch Stall Cycles table, we see the counter for SCHEDQ reports 272 cycles. This counter is incremented every time the dispatch logic is unable to dispatch a full group because the scheduler’s queue is full.
Looking at the Dispatch Logic table, we see that the pipeline was only able to
dispatch two micro opcodes 51.5% of the time. The dispatch group was limited to
one micro opcode 44.6% of the cycles, which corresponds to 272 cycles. The
dispatch statistics are displayed by either using the command option
-all-stats
or -dispatch-stats
.
The next table, Schedulers, presents a histogram displaying a count, representing the number of instructions issued on some number of cycles. In this case, of the 610 simulated cycles, single instructions were issued 306 times (50.2%) and there were 7 cycles where no instructions were issued.
The Scheduler’s queue usage table shows that the average and maximum number of buffer entries (i.e., scheduler queue entries) used at runtime. Resource JFPU01 reached its maximum (18 of 18 queue entries). Note that AMD Jaguar implements three schedulers:
- JALU01 - A scheduler for ALU instructions.
- JFPU01 - A scheduler floating point operations.
- JLSAGU - A scheduler for address generation.
The dot-product is a kernel of three floating point instructions (a vector multiply followed by two horizontal adds). That explains why only the floating point scheduler appears to be used.
A full scheduler queue is either caused by data dependency chains or by a
sub-optimal usage of hardware resources. Sometimes, resource pressure can be
mitigated by rewriting the kernel using different instructions that consume
different scheduler resources. Schedulers with a small queue are less resilient
to bottlenecks caused by the presence of long data dependencies. The scheduler
statistics are displayed by using the command option -all-stats
or
-scheduler-stats
.
The next table, Retire Control Unit, presents a histogram displaying a count,
representing the number of instructions retired on some number of cycles. In
this case, of the 610 simulated cycles, two instructions were retired during the
same cycle 399 times (65.4%) and there were 109 cycles where no instructions
were retired. The retire statistics are displayed by using the command option
-all-stats
or -retire-stats
.
The last table presented is Register File statistics. Each physical register
file (PRF) used by the pipeline is presented in this table. In the case of AMD
Jaguar, there are two register files, one for floating-point registers (JFpuPRF)
and one for integer registers (JIntegerPRF). The table shows that of the 900
instructions processed, there were 900 mappings created. Since this dot-product
example utilized only floating point registers, the JFPuPRF was responsible for
creating the 900 mappings. However, we see that the pipeline only used a
maximum of 35 of 72 available register slots at any given time. We can conclude
that the floating point PRF was the only register file used for the example, and
that it was never resource constrained. The register file statistics are
displayed by using the command option -all-stats
or
-register-file-stats
.
In this example, we can conclude that the IPC is mostly limited by data dependencies, and not by resource pressure.
Instruction Flow¶
This section describes the instruction flow through the default pipeline of llvm-mca, as well as the functional units involved in the process.
The default pipeline implements the following sequence of stages used to process instructions.
- Dispatch (Instruction is dispatched to the schedulers).
- Issue (Instruction is issued to the processor pipelines).
- Write Back (Instruction is executed, and results are written back).
- Retire (Instruction is retired; writes are architecturally committed).
The default pipeline only models the out-of-order portion of a processor. Therefore, the instruction fetch and decode stages are not modeled. Performance bottlenecks in the frontend are not diagnosed. llvm-mca assumes that instructions have all been decoded and placed into a queue before the simulation start. Also, llvm-mca does not model branch prediction.
Instruction Dispatch¶
During the dispatch stage, instructions are picked in program order from a queue of already decoded instructions, and dispatched in groups to the simulated hardware schedulers.
The size of a dispatch group depends on the availability of the simulated
hardware resources. The processor dispatch width defaults to the value
of the IssueWidth
in LLVM’s scheduling model.
An instruction can be dispatched if:
- The size of the dispatch group is smaller than processor’s dispatch width.
- There are enough entries in the reorder buffer.
- There are enough physical registers to do register renaming.
- The schedulers are not full.
Scheduling models can optionally specify which register files are available on
the processor. llvm-mca uses that information to initialize register
file descriptors. Users can limit the number of physical registers that are
globally available for register renaming by using the command option
-register-file-size
. A value of zero for this option means unbounded. By
knowing how many registers are available for renaming, the tool can predict
dispatch stalls caused by the lack of physical registers.
The number of reorder buffer entries consumed by an instruction depends on the number of micro-opcodes specified for that instruction by the target scheduling model. The reorder buffer is responsible for tracking the progress of instructions that are “in-flight”, and retiring them in program order. The number of entries in the reorder buffer defaults to the value specified by field MicroOpBufferSize in the target scheduling model.
Instructions that are dispatched to the schedulers consume scheduler buffer entries. llvm-mca queries the scheduling model to determine the set of buffered resources consumed by an instruction. Buffered resources are treated like scheduler resources.
Instruction Issue¶
Each processor scheduler implements a buffer of instructions. An instruction has to wait in the scheduler’s buffer until input register operands become available. Only at that point, does the instruction becomes eligible for execution and may be issued (potentially out-of-order) for execution. Instruction latencies are computed by llvm-mca with the help of the scheduling model.
llvm-mca’s scheduler is designed to simulate multiple processor schedulers. The scheduler is responsible for tracking data dependencies, and dynamically selecting which processor resources are consumed by instructions. It delegates the management of processor resource units and resource groups to a resource manager. The resource manager is responsible for selecting resource units that are consumed by instructions. For example, if an instruction consumes 1cy of a resource group, the resource manager selects one of the available units from the group; by default, the resource manager uses a round-robin selector to guarantee that resource usage is uniformly distributed between all units of a group.
llvm-mca’s scheduler internally groups instructions into three sets:
- WaitSet: a set of instructions whose operands are not ready.
- ReadySet: a set of instructions ready to execute.
- IssuedSet: a set of instructions executing.
Depending on the operands availability, instructions that are dispatched to the scheduler are either placed into the WaitSet or into the ReadySet.
Every cycle, the scheduler checks if instructions can be moved from the WaitSet to the ReadySet, and if instructions from the ReadySet can be issued to the underlying pipelines. The algorithm prioritizes older instructions over younger instructions.
Write-Back and Retire Stage¶
Issued instructions are moved from the ReadySet to the IssuedSet. There, instructions wait until they reach the write-back stage. At that point, they get removed from the queue and the retire control unit is notified.
When instructions are executed, the retire control unit flags the instruction as “ready to retire.”
Instructions are retired in program order. The register file is notified of the retirement so that it can free the physical registers that were allocated for the instruction during the register renaming stage.
Load/Store Unit and Memory Consistency Model¶
To simulate an out-of-order execution of memory operations, llvm-mca utilizes a simulated load/store unit (LSUnit) to simulate the speculative execution of loads and stores.
Each load (or store) consumes an entry in the load (or store) queue. Users can
specify flags -lqueue
and -squeue
to limit the number of entries in the
load and store queues respectively. The queues are unbounded by default.
The LSUnit implements a relaxed consistency model for memory loads and stores. The rules are:
- A younger load is allowed to pass an older load only if there are no intervening stores or barriers between the two loads.
- A younger load is allowed to pass an older store provided that the load does not alias with the store.
- A younger store is not allowed to pass an older store.
- A younger store is not allowed to pass an older load.
By default, the LSUnit optimistically assumes that loads do not alias (-noalias=true) store operations. Under this assumption, younger loads are always allowed to pass older stores. Essentially, the LSUnit does not attempt to run any alias analysis to predict when loads and stores do not alias with each other.
Note that, in the case of write-combining memory, rule 3 could be relaxed to
allow reordering of non-aliasing store operations. That being said, at the
moment, there is no way to further relax the memory model (-noalias
is the
only option). Essentially, there is no option to specify a different memory
type (e.g., write-back, write-combining, write-through; etc.) and consequently
to weaken, or strengthen, the memory model.
Other limitations are:
- The LSUnit does not know when store-to-load forwarding may occur.
- The LSUnit does not know anything about cache hierarchy and memory types.
- The LSUnit does not know how to identify serializing operations and memory fences.
The LSUnit does not attempt to predict if a load or store hits or misses the L1 cache. It only knows if an instruction “MayLoad” and/or “MayStore.” For loads, the scheduling model provides an “optimistic” load-to-use latency (which usually matches the load-to-use latency for when there is a hit in the L1D).
llvm-mca does not know about serializing operations or memory-barrier like instructions. The LSUnit conservatively assumes that an instruction which has both “MayLoad” and unmodeled side effects behaves like a “soft” load-barrier. That means, it serializes loads without forcing a flush of the load queue. Similarly, instructions that “MayStore” and have unmodeled side effects are treated like store barriers. A full memory barrier is a “MayLoad” and “MayStore” instruction with unmodeled side effects. This is inaccurate, but it is the best that we can do at the moment with the current information available in LLVM.
A load/store barrier consumes one entry of the load/store queue. A load/store barrier enforces ordering of loads/stores. A younger load cannot pass a load barrier. Also, a younger store cannot pass a store barrier. A younger load has to wait for the memory/load barrier to execute. A load/store barrier is “executed” when it becomes the oldest entry in the load/store queue(s). That also means, by construction, all of the older loads/stores have been executed.
In conclusion, the full set of load/store consistency rules are:
- A store may not pass a previous store.
- A store may not pass a previous load (regardless of
-noalias
). - A store has to wait until an older store barrier is fully executed.
- A load may pass a previous load.
- A load may not pass a previous store unless
-noalias
is set. - A load has to wait until an older load barrier is fully executed.


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| Packages that use XMLBeanInfo | |
| org.apache.commons.betwixt | This package contains the main betwixt introspection code. |
| org.apache.commons.betwixt.registry | This package contains various plugins that can be used with XMLIntrospector
to customize it's caching behaviour (or programmatically modify the XmlBeanInfo finding). |
| org.apache.commons.betwixt.schema | WARNING: EXPERIMENTAL
Contains classes that generate XML (w3c) schema
from Betwixt descriptors. |
| Uses of XMLBeanInfo in org.apache.commons.betwixt |
| Methods in org.apache.commons.betwixt that return XMLBeanInfo | |
XMLBeanInfo |
XMLIntrospector.introspect(java.lang.Object bean)
Create a standard XMLBeanInfo by introspection
The actual introspection depends only on the BeanInfo
associated with the bean. |
XMLBeanInfo |
XMLIntrospector.introspect(org.apache.commons.beanutils.DynaClass dynaClass)
Creates XMLBeanInfo by reading the DynaProperties of a DynaBean. |
XMLBeanInfo |
XMLIntrospector.introspect(java.lang.Class aClass,
org.xml.sax.InputSource source)
Introspects the given Class using the dot betwixt
document in the given InputSource . |
XMLBeanInfo |
XMLIntrospector.introspect(java.lang.Class aClass)
Create a standard XMLBeanInfo by introspection. |
XMLBeanInfo |
XMLIntrospector.introspect(java.beans.BeanInfo beanInfo)
Create a standard XMLBeanInfo by introspection. |
protected XMLBeanInfo |
XMLIntrospector.createXMLBeanInfo(org.apache.commons.beanutils.DynaClass dynaClass)
Creates XMLBeanInfo for the given DynaClass. |
protected XMLBeanInfo |
XMLIntrospector.findByXMLDescriptor(java.lang.Class aClass)
Attempt to lookup the XML descriptor for the given class using the classname + ".betwixt" using the same ClassLoader used to load the class or return null if it could not be loaded |
protected XMLBeanInfo |
XMLIntrospector.createXMLBeanInfo(java.beans.BeanInfo beanInfo)
Factory method to create XMLBeanInfo instances |
| Uses of XMLBeanInfo in org.apache.commons.betwixt.registry |
| Methods in org.apache.commons.betwixt.registry that return XMLBeanInfo | |
XMLBeanInfo |
NoCacheRegistry.get(java.lang.Class forThisClass)
Always return null. |
XMLBeanInfo |
DefaultXMLBeanInfoRegistry.get(java.lang.Class forThisClass)
Get XMLBeanInfo from cache. |
XMLBeanInfo |
XMLBeanInfoRegistry.get(java.lang.Class forThisClass)
Get the XMLBeanInfo for the given class. |
| Methods in org.apache.commons.betwixt.registry with parameters of type XMLBeanInfo | |
void |
NoCacheRegistry.put(java.lang.Class forThisClass,
XMLBeanInfo beanInfo)
Do nothing (this implementation does not cache) |
void |
DefaultXMLBeanInfoRegistry.put(java.lang.Class forThisClass,
XMLBeanInfo beanInfo)
Put into cache |
void |
XMLBeanInfoRegistry.put(java.lang.Class forThisClass,
XMLBeanInfo beanInfo)
Associate a class with it's XMLBeanInfo . |
| Uses of XMLBeanInfo in org.apache.commons.betwixt.schema |
| Methods in org.apache.commons.betwixt.schema that return XMLBeanInfo | |
XMLBeanInfo |
Schema.introspect(java.lang.Class type)
Introspects the given type giving an XMLBeanInfo . |
| Methods in org.apache.commons.betwixt.schema with parameters of type XMLBeanInfo | |
Schema |
SchemaTranscriber.generate(XMLBeanInfo xmlBeanInfo)
Generates an XML Schema model from the given XMLBeanInfo |
|
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| PREV NEXT | FRAMES NO FRAMES |


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When Type Inference Doesn't Cut It
David Kanenwisher • March 8, 2020
kotlinIn order to learn Kotlin I've been working my way through a goofy program called "adventure-venture". I honestly don't have a clear idea of what it does but so far it has adventurers in a tavern that want to talk to each other. I'm also trying to understand event based systems so the adventurers interact with the world through events.
In the process of trying to get the adventurers to talk to each other I've been refactoring the way the system works. When I refactor I like to try and keep all of the tests passing as I advance forward with the refactoring. That way it's clear when I am changing behavior and when I am not. It's in this way that I discovered a situation where I can't rely on type inference.
I got my code to the point where I had these two tests:
@Test
fun `it can dispatch an empty event object`() {
val dispatcher = Dispatcher()
var passedValue = EmptyEvent()
dispatcher.eventSubscribe { event -> passedValue = event }
assertEquals("", passedValue.name)
}
@Test
fun `it can dispatch an emitted event object`() {
val dispatcher = Dispatcher()
var passedValue = EmittedEvent("emittedSound")
dispatcher.eventSubscribe { event -> passedValue = event }
assertEquals("emittedSound", passedValue.name)
}
Notice that in the first test I have var passedValue = EmptyEvent()
and in the second test I have a similar line var passedValue = EmittedEvent("emittedSound")
. Why not just leave them like this then? Well, they don't compile because dispatcher.eventSubscribe
expects a lambda of type (Event) -> Unit
. I thought I had this covered by creating the Event
interface and making each implement this interface. No dice, I starting getting Type mismatch
errors from Intellij on this line:
dispatcher.eventSubscribe { event -> passedValue = event }
After staring at my code a bit a thought occurred to me. The type of event
above is Event
while the type of passedValue
is either EmptyEvent
or EmittedEvent
. This means I must not be able to assign a more specific type, EmptyEvent
or EmittedEvent
, to a less specific type Event
. This lead to me think I need to declare the type as Event
so that passedValue
can always hold an Event
.
I added explicit type information to passedValue
by changing it to passedValue: Event
like so:
@Test
fun `it can dispatch an empty event object`() {
val dispatcher = Dispatcher()
var passedValue: Event = EmptyEvent()
dispatcher.eventSubscribe { event -> passedValue = event }
assertEquals("", passedValue.name)
}
@Test
fun `it can dispatch an emitted event object`() {
val dispatcher = Dispatcher()
var passedValue: Event = EmittedEvent("emittedSound")
dispatcher.eventSubscribe { event -> passedValue = event }
assertEquals("emittedSound", passedValue.name)
}
That did the trick and my tests start passing. I do wonder if generics could help out here but I haven't played with them much yet.
How about you? Let me know if you've learned anything interesting about Kotlin's type inference by dropping me a line on the contact page.


Welcome to the NoDQ Wrestling PodCast website. This website is for demonstration purposes only. Please see the github page for more info.


{% extends "module/sequence_item_base.html" %} {% load staticfiles bootstrap3 %} {% block main_content %}
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About us
An electronic Ticket (eTiquet) is a web application that allows drivers to store their personal information in a QR Code for verification during checkpoints.
It is a handy and convenient alternative for a physical driver's license because you can bring it anywhere with the comfort that the holder's personal data are safe. The electronic ticket permits any driver the right to drive any vehicle in accordance with the restrictions stated in their profile. One tap and scan, and the ticketing officers can verify the driver's license authenticity and check the profile of the riders and as well as in giving violations intended for the drivers.


| Score | Browser | When |
|---|
Please note that all data shown above are unconfirmed test results. They could be fake or belong to a different browser than the one listed.
deviceType:mobile osName:Windows
deviceManufacturer:Samsung -osName:Android
osName:Android osVersion:4.4
browserName:Chrome osName:"Mac OS X"
deviceModel:iPhone
engineName:Gecko -browserName:Firefox
score:500+
Created by Niels Leenheer.
Please note that the HTML5 test is not affiliated with the W3C or the HTML5 working group.
HTML5 Logo by W3C.
Browser detection by WhichBrowser.


Similarity(Cosine Distance) of Following News =
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title
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Extract healthcare data from MySQL server, conducted data ETL and data profiling on AWS server using PySpark
Performed data visualization of healthcare data to build baselines of member and provider behavior outlier detection
Used Autoencoder model to reduce the dimensions of provider medical claim data. Built outlier detection model using HDBSCAN to flag healthcare providers with abnormal behavior.
Trained Word2Vec, Doc2Vec (gensim) model on 9 GB member claim sequence data. Deployed “Sequence to Sequence” model to reduce the dimension and vectorize members’ medical record data.
Trained Convolutional Autoencoder, Variational Autoencoder and neural image caption generator model to vectorize medical claim record data. Compared the performance of different model using t-SNE and k-Nearest Neighbor.
Assembled provider outlier detection and member clustering algorithm to a scoring system for a medical insurance company.
AUG 2018 - PresentSan Diego,CA
Data Scientist Intern
ECALCHARGE INC
Parsed and extracted electrical vehicle driving history raw data from data provided by car manufacturer on AWS
Cleansed missing values and outliers and used regression to impute the missing driving event in the data using Python
Performed data visualization of driving patterns to find informational features
Performed feature engineering and feature selection, used PCA to reduce the dimensionality and reduce
Applied k-means clustering to identify similar driving patterns, used elbow method to find optimal number of clusters.
JUN 2017 - AUG 2017Berkeley,CA
Education
Northern Arizona University
Master of Science
ELECTRICAL ENGINEERING
Pattern Recognition, Large Scale Data Structures, Statistical Computing, Image Processing
Academic research in biomedical signal processing and automated classification system design using kernel method and multiobjective optimization method
SEP 2016 - JULY 2018GPA:3.9/4
SOUTHWEST JIAOTONG UNIVERSITY (SWJTU)
Master of Science
ELECTRICAL ENGINEERING
Sept 2015 - Jan 2018
ECOLE CENTRALE MARSEILLE ( double degrees program with SWJTU)
Diplôme d’Ingénieur (equivalent to Master Degree)
ELECTRICAL ENGINEERING
SEPT 2013 – MAY 2015
SOUTHWEST JIAOTONG UNIVERSITY (SWJTU)
Bachelor
ELECTRICAL ENGINEERING
SEP 2011 - JUNE 2015
Projects
ADVANCED WARNING AND CLASSIFICATION SYSTEM FOR ECG SIGNAL
Designed ECG signal acquisition system with body sensor and wireless transmission module
Implemented ECG signal preprocessing and segmentation algorithm using wavelet decomposition. Extracted features from ECG signal and performed feature selection
Designed a two-staged hierarchical classification system including weighted k-Nearest Neighbor and a designed clustering algorithm for advanced warning of cardiovascular disease.
Improved the system performance with a designed feature space reshaping algorithm and Multi-Objective Particle Swarm Optimization.
AUG 2016 – AUG 2018
MUSIC PLAYER CHURN PREDICTION
Used Shell Script and Spark parse user behavior log file(16GB), cleaned log file, resampled unbalanced classes, visualized data and performed Exploratory Data Analysis using PySpark and Pandas
Performed Feature Engineering (including frequency, recency, acceleration, etc.), generated user churn label and performed classification using random forest and multi-layer perceptron achieving AUC of 0.89
FEB 2018 – MARCH 2018
YELP DATASET CHALLENGE: NLP & SENTIMENT ANALYSIS
Cleansed and filtered review metadata(3.28GB) and joined it with relevant tables using Python(Pandas)
Used NLP techniques (e.g. TFIDF Vectorizer) to extract features from unstructured review text data with sklearn, nltk
Clustered the reviews with KMeans clustering and fitted Naive Bayes Classifier to predict user sentiment
Built a restaurant recommender system using Collaborative Filtering and Matrix Factorization based on user's ratings
JAN 2018 – FEB 2018
LENDING CLUB RISK ADJUSTED INTEREST RATE PREDICTION
Extracted 12 features from raw lending club loan data containing different types, such as categorical, numerical and time series data, imputed missing data using multivariate imputation by chained equation (MICE) algorithm
Performed feature selection through exploratory analysis
Fitted linear regression model with regularization to control for multicollinearity and also built decision tree, random forest, boosting decision tree to predict interest rate for each loan
Achieved 0.3 RMSE by boosting decision tree model on test data set.
DEC 2017 – JAN 2018
KAGGLE ICEBERG IMAGE CLASSIFICATION CHALLENGE
Performed image denoising and image augmentation on the SAR images using OpenCV and Python(Keras)
Applied Convolutional Neural Network on the training images and tested performance using Keras
DEC 2017 – JAN 2018
Publications
1. J. Chen and A. Razi, "A predictive framework for ECG signal processing using controlled nonlinear transformation," 2018 IEEE EMBS International Conference on Biomedical & Health Informatics (BHI), Las Vegas, NV, 2018, pp. 161-165.
J. Chen and A. Razi, “Remote ECG Monitoring Kit to Predict Patient-Specific Heart Abnormalities”, Journal on Systemics, Cybernetics and Informatics (JSCI) Volume 15 - Number 4 - Year 2017, pp. 82-89


{% extends "bookme/base.html" %} {% block header %}
This is a template for a simple marketing or informational website. It includes a large callout called the hero unit and three supporting pieces of content. Use it as a starting point to create something more unique.


lxclipboard - clipboard utility for LXSession and LXDE
lxclipboard
lxclipboard is a clipboard utility, to be able to do copy/paste operation between GTK+ applications. lxcliboard is only useful when lxsession is not compile with clipboard build-in support. If lxsession is compile with clipboard build-in lxclipboard functionality will be automatically launched, without the need to launch lxclipboard.
William Jon McCann<EMAIL_ADDRESS>Matthias Clasen
Anders Carlsson
Rodrigo Moya
Nick Schermer<EMAIL_ADDRESS>Julien Lavergne<EMAIL_ADDRESS>Man page written to conform with Debian by Julien Lavergne.


avg-technologies
Businessmodel of AVG Technologies
Customer Segments
AVG has a segmented market business model, with customers that have slightly different needs. The company targets its offerings at consumers and small and medium businesses (SMBs).
Value Proposition
AVG offers four primary value propositions: price, accessibility, risk reduction, and brand/status.
The company offers a price value proposition. It provides a free version of its software so that users can preview its features. The premium version is low-cost compared to that of many competitors.
The company enables accessibility. Starting in 2011, it began expanding its offerings to mobile products, particularly tablets and smartphones. In 2014 it unveiled AVG Zen, a connected solution across PC and mobile platforms, and acquired Location Labs, a mobile security solution vendor. AVG now has over 102 million customers using its product on their mobile devices.
The company reduces risk by providing multiple layers of protection in its products. They include the following:
- Protection against known malicious computer programs
- Protection against known malicious computer program families (heuristic analysis)
- Protection against unknown malicious computer programs (behavior analysis)
- Protection against web exploits
- Protection against known malicious or phishing web addresses
- Protection against network attacks The company has established a powerful brand as a result of its success. It now has 202 million+ active users and operates in over a dozen offices worldwide. Its prominent business clients include Overton’s, the world’s largest water sports company, and Big Thought, the Immanuel Broadcasting Network, and the AARP Tax Aide Foundation. Lastly, it has won many honors, including “Security Vendor of the Year“ from the European IT & Software Excellence Awards (2016), many Virus Bulletin 100 Awards, and recognition as one of CRM’s “20 Coolest Cloud Security Vendors“ (2016).
Channels
AVG’s main channel is its website, which accounted for 82% of revenues in 2015. It also utilizes resellers and distributors, who account for the majority of SMB sales, and retail chains such as Best Buy, Office Max, Office Depot, Staples, and Wal-Mart. The company promotes its offering through its social media pages and advertising.
Customer Relationships
AVG’s customer relationship is primarily of a self-service, automated nature. Customers utilize the product while having limited interaction with employees. The company’s website includes self-help resources such as videos and answers to frequently asked questions. It also enables paid customers to renew or upgrade their subscriptions and register their licenses. That said, there is a personal assistance component in the form of general phone and e-mail support for all customers and premium technical support for paid users. Premium service plans are as follows:
- Simple Fix – One-time call for basic help ($79 per call)
- Complete Fix – One-time call for advanced help ($119 per call)
- Total Care –Unlimited calls for an entire year ($199 per year) ### Key Activities
AVG’s business model entails designing and developing its software products for customers.
Key Partners
AVG maintains the following partnership programs:
Reseller Program – Includes companies that purchase and sell AVG’s products to expand its customer base. Benefits of the program include the following:
- High initial discounts
- Competitive end-user pricing
- No minimum sales volume requirements
- Priority access to 24/7 phone and e-mail technical support
- Access to a Reseller Center that includes marketing resources (brochures, leaflets, posters, logos, testimonials, etc.), license management tools, and an online ordering system
-
Informational newsletters providing updates abut the software and the company Affiliates Program – Includes organizations that promote AVG’s solutions through their platforms (website, mobile apps, etc.). Benefits of the program include the following:
- 5 – 30% commission on all sales resulting from a lead (paid within 45 days)
- 60-day referral period
- Promotional tools such as text links, banners, and a product catalog
- Exclusive campaigns, offers, and promotions
- Affiliate partner-specific newsletters
- Regular bonuses and incentives ### Key Resources
AVG’s main resource is its staff of engineering employees that design and develop its software. The company also depends on its customer service staff (52 full-time and 339 contract employees as of December 2015) to provide varying levels of support. They operate from 15 call centers located in the U.S., India, the Philippines, Czech Republic, Canada, Poland, Portugal, Brazil, the United Kingdom, Norway, and Serbia.
Cost Structure
AVG has a cost-driven structure, aiming to minimize expenses through significant automation and low-price value propositions. Its biggest cost driver is sales/marketing expenses, a fixed cost. Other major drivers are in the areas of research/development and administration, both fixed costs, and cost of revenues, a variable expense that includes fees paid to third-party distributors of AVG’s mobile and search solutions, fees for third party technology service providers, costs of electronic downloads, commissions to payment providers, and costs of packaging and licenses.
Revenue Streams
AVG has two revenue streams:
Subscription Revenues – Revenues generated from sales of fixed-term software licenses and access to software-as-a-service products
Platform-Derived Revenues – Revenues generated from AVG’s search solution, third-party advertisers, and the sale of threat analysis data


{% from 'lib/interval.html' import interval_input -%}
{% extends 'lib/layout.html' %}
{% block scripts %}
{% endblock %}
{% block body -%}
Currently keeping track of {{ post_count }} of your posts, roughly {{ g.viewer.account.estimate_eligible_for_delete() }} of which currently match your expiration rules.
{% if g.viewer.account.service == 'twitter' and g.viewer.account.reported_post_count and post_count < g.viewer.account.reported_post_count * 3/4 and g.viewer.account.reported_post_count > 3200 -%} {% endif %}Twitter's API only lets us access up to 3200 of your most recent tweets. If you have more tweets than that, you can request a tweet archive from your account settings, and upload it here.
{% if tweet_archive_failed %} {% endif %} {% if g.viewer.account.twitter_archives %}


To start a new project, simply clone the app-base from Github:
git clone https://github.com/ionic-team/stencil-starter.git my-app
cd my-app
git remote rm origin
npm install
Then, to start a live-reload server, run:
npm start
Changes made while the live-reload server will automatically be reflected. Let's make a small edit to our component. Open src/components/my-name/my-name.tsx
in your editor
We can ignore most of the content here, but we'll look at our render
method. Inside the return statement, let's modify what we have.
render() {
return (
<p>
Hello, my props are {this.first} and {this.last}
</p>
);
}
When we save, we'll have our component updated with the new changes. To learn more about what's going on in this component, check out
To do a production build, run the following command
npm run build
This will generate a minified distribution of your stencil components.


{% render_field form.username class="form-control mb-4" placholder="any_username"%}
{% render_field form.email class="form-control mb-4"<EMAIL_ADDRESS>{% render_field form.age class="form-control mb-4" placholder="Your Age..."%}
{% render_field form.contact_number class="form-control mb-4" placholder="(Country Code) (Phone Number)"%}
{% render_field form.profession class="form-control mb-4" placholder="ex. Graphics Designer"%}
{% render_field form.bio class="form-control mb-4" placeholder="Writer your bio here..."%}
{% for skill in formskills %}
- {{skill}}
{% endfor %}
{% render_field form.linkedin class="form-control mb-4" placholder="https://linkedin.com/in/"%}
{% render_field form.facebook class="form-control mb-4" placholder="https://facebook.com/"%}
{% render_field form.github class="form-control mb-4" placholder="https://github.com/"%}


This is a site based off of the theme of Italy. I just recently took a trip there for about two weeks with my family. This is a collection of pictures I took and a little about the places we went. I am really glad I had the experience and I think it opened my eyes to new places I want to go, and opportunities for my future. I would highly recommend a trip to Italy, the sights are unbeatable, as is the food!
Thank you for viewing my site!


Open Loop
Closed Loop
PID Control
Amplitude
V
Frequency
Hz
Frequency
Hz
Proportional
Integral
Derivative
BeagleBone Black Oscilloscope
RUN


ChatApp
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MERAKI
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Here's a very fast, straightforward solution from Alex Schwedner:
#include <fstream.h> #include <stdlib.h> struct fraction { int numerator; int denominator; }; bool rprime(int a, int b){ int r = a % b; while(r != 0){ a = b; b = r; r = a % b; } return(b == 1); } int fraccompare (struct fraction *p, struct fraction *q) { return p->numerator * q->denominator - p->denominator *q->numerator; } int main(){ int found = 0; struct fraction fract[25600]; ifstream filein("frac1.in"); int n; filein >> n; filein.close(); for(int bot = 1; bot <= n; ++bot){ for(int top = 0; top <= bot; ++top){ if(rprime(top,bot)){ fract[found].numerator = top; fract[found++].denominator = bot; } } } qsort(fract, found, sizeof (struct fraction), fraccompare); ofstream fileout("frac1.out"); for(int i = 0; i < found; ++i) fileout << fract[i].numerator << '/' << fract[i].denominator << endl; fileout.close(); exit (0); }
Here's a super fast solution from Russ:
We notice that we can start with 0/1 and 1/1 as our ``endpoints'' and recursively generate the middle points by adding numerators and denominators.
0/1 1/1 1/2 1/3 2/3 1/4 2/5 3/5 3/4 1/5 2/7 3/8 3/7 4/7 5/8 5/7 4/5Each fraction is created from the one up to its right and the one up to its left. This idea lends itself easily to a recursion that we cut off when we go too deep.
#include <stdio.h> #include <stdlib.h> #include <string.h> #include <assert.h> int n; FILE *fout; /* print the fractions of denominator <= n between n1/d1 and n2/d2 */ void genfrac(int n1, int d1, int n2, int d2) { if(d1+d2 > n) /* cut off recursion */ return; genfrac(n1,d1, n1+n2,d1+d2); fprintf(fout, "%d/%d\n", n1+n2, d1+d2); genfrac(n1+n2,d1+d2, n2,d2); } void main(void) { FILE *fin; fin = fopen("frac1.in", "r"); fout = fopen("frac1.out", "w"); assert(fin != NULL && fout != NULL); fscanf(fin, "%d", &n); fprintf(fout, "0/1\n"); genfrac(0,1, 1,1); fprintf(fout, "1/1\n"); }


From:Goradia Pallavi To:Kalmus Steve ; Moore Jan Sent:2017-01-11T04:37:38.0000000Z Subject:RE: TW Red Rock Cashflow
Steve,
The last cash flow you sent on Aug 20, 2001 showed we would spend $41.5 million on the Red Rock Expansion in 2001. This cash flow shows $30 million to be spent in 2001. We will be include the difference of $ 72 million and 2001 forecast in the 2002 Capital Plan as a carryover. Please confirm the 2001 cash flow.
Palu
-----Original Message-----
From: Geaccone, Tracy
Sent: Monday, September 17, 2001 9:58 AM
To: Goradia, Pallavi
Subject: FW: TW Red Rock Cashflow
How does this fit in with our 2002 Capital Plan?
-----Original Message-----
From: Kleb, Steve
Sent: Monday, September 17, 2001 9:20 AM
To: Geaccone, Tracy; Moore, Jan
Cc: Studzinski, Betty
Subject: FW: TW Red Rock Cashflow
FYI
-----Original Message-----
From: Kalmus, Steve
Sent: Friday, September 14, 2001 3:43 PM
To: Kleb, Steve
Cc: Eisenstein, Arnold L.; Hubbard, Dave
Subject: TW Red Rock Cashflow
Steve,
Here is my updated cashflow for the TW Red Rock project. Please use this for your year end projections.
Thanks,
Steve Kalmus
<< File: TW Red Rock Cashflow updated thru Sept. 14.xls >>
***********
EDRM Enron Email Data Set has been produced in EML, PST and NSF format by ZL Technologies, Inc. This Data Set is licensed under a Creative Commons Attribution 3.0 United States License <http://creativecommons.org/licenses/by/3.0/us/> . To provide attribution, please cite to "ZL Technologies, Inc. (http://www.zlti.com)."
***********
California


Hello! My name is Ana. I am a JavaScript software developer and a student at Code Fellows. I moved to the US five years ago from the city called Kazan which is located in Russia and right now I live in Seattle with my fiance and our cat Frodo. I looooove coding, traveling, making jewelry and learning new things. On this page, you can find information about my education, my projects and how to contact me.
- Code Fellows
Seattle, WACertificate - Advanced Software Development in Full-Stack JavaScript
- TISBI University of management
Kazan, RussiaBachelor’s degree in Finance
- College of folk arts
Kazan, RussiaAssociate's degree in Jewelry art
- Banking school
Kazan, RussiaAssociate's degree in Accounting
- Code 101 Shelter
- Awesome project 2
- Even more awesome project 3


Get Started
Everything you'll need is located under the lightbox/ directory. Include the javascript and css files in your HTML document and you're all set up:
<link href="lightbox/lightbox.min.css" rel="stylesheet">

Usage
Add the data-lightbox attribute to an  tag and set its href to the content you want to be opened in the lightbox. When opening an image, you can send its alt text using the data-image-alt attribute:

Image

Modal

Vimeo

Youtube

Welcome!

Sign in to your account.

<form>
<input type="email" name="email" placeholder="e-mail account">
<input type="password" name="password" placeholder="password">
<input class="btn" type="submit" name="submit" value="Sign In">
</form>

Gallery
Set the data-lightbox attribute to "gallery" on all  tags under the same parent element and any previous or next items will be found automatically:


#include <CPrintProgressBar.h>
Public Member Functions | |
| CPrintProgressBar (int const barLength=30) | |
| Public Member Functions inherited from ion::IProgressBar | |
| void | BeginProgress () |
| void | SetProgress (float const progress) |
| void | SetProgress (double const progress) |
| void | EndProgress () |
| CTask * | NewTask (float const value) |
Protected Member Functions | |
| void | Start () |
| void | Render () |
| void | Finish () |
| Protected Member Functions inherited from ion::IProgressBar | |
| IProgressBar () | |
Protected Attributes | |
| int | LastProgress = -1 |
| int | BarLength |
| Protected Attributes inherited from ion::IProgressBar | |
| float | Progress |
| bool | Started |
|
inline |
|
inlineprotectedvirtual |
Implements ion::IProgressBar.
|
inlineprotectedvirtual |
Implements ion::IProgressBar.
|
inlineprotectedvirtual |
Implements ion::IProgressBar.
|
protected |
|
protected |
Generated on Sun May 6 2018 for ionEngine v0.4.5


177417
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d
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q
(forwards)
e
(backwards) to move cubes.
Toggle help axes.
New Game:
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Project on Github.


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This Mix from MR.bortolotti


| Home | Trees | Indices | Help |
|
|---|
|
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Manager for Mixin documents on couch database
|
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|
|||
|
|||
|
|||
|
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|
|
Returns mixin documents matching the filter provided Args:
|
Add new mixins to the database Args:
|
Updates the OCCI description field of the mixin which document OCCI_ID is equal to OCCI_ID contained in data (Should only be done by the creator of the mixin document) Args:
|
Delete mixin documents that is related to the scheme + term contained in the description provided Args:
|
Dissociates entities from a mixin Args:
|
| Home | Trees | Indices | Help |
|
|---|
| Generated by Epydoc 3.0.1 on Thu Oct 25 18:47:47 2012 | http://epydoc.sourceforge.net |


James McAvoy Reveals He’s Been Told He’s ‘Too Short For A Role’
by Brent FurdykJames McAvoy is taking a break from the silver screen to return to the stage, currently starring in a new production of “Cyrano de Bergerac” in London’s West End.
Discussing his latest project with The Telegraph, the conversation turned to his many movie roles, with McAvoy getting candid about the importance of physical appearance when being cast in a movie.
“Sometimes you’re made to feel like you’re not good-looking enough to get a role,” he admits. “I was told once by an actress that it was an interesting choice, my casting, because nobody would usually believe that I would be with somebody like her. That was a kick in the nuts! I was like, ‘All right, now I’ve got to pretend that I really like you for eight more weeks. This is going to be really tough, because you’re so far up yourself.’ It got really interesting, that relationship.”
The same hold true when it comes to height. “And as a shorter man, I sometimes get told I’m too short for a role,” says McAvoy of his five-seven stature. “Or even when I get a role, I’m made to feel like, well, of course, we’re going to have to do something about that.”
During the interview, McAvoy — who’s starred in four “X-Men” movies — weighs in about Martin Scorsese’s controversial declaration that movies based on comic books are “not cinema.”
“I would hope he’s watched every single one of them to make that statement,” McAvoy fires back. “Some of them are s**t and some of them have really moved me. I think that you’ve got to take it on a film-by-film basis.”
However, he adds, “I’m not offended by it. He’s Martin Scorsese — he can say what he likes. And he’s not going to break the machine by saying it.”


--- layout: post title: Research on why and how adopts Rails categories: - sightings author: David published: true date: 2007-07-08 22:36:00.000000000 +01:00 ---
Michel Barbosa has completed his bachelor thesis Delivery of the Key Adoption Factors and Key Characteristics of Companies Using Ruby on Rails. It presents research he has done and conclusions the why and who of switchers.
I’m happy to see that “Joy in Development” was a key adoption factor for 92% of the people interviewed.


|
External stressors from people, our children, and tolerating daily inconvenieces like traffic can cause us to eat food that tenses up the body and cause more stress. This in turn starts a vicious cycle that makes us want to eat the foods listed above that “relax” us.
Many of these foods are processed, high in salt, and are caloric like meat, eggs, cheese, dairy products (milk/yoghurt/cream), baked goods, and deep-fried foods. It would be useful to do an assessment of how often you eat these foods as they most likely are influencing your stress levels.
What is Mindless Eating?
This is when you buy fast food, eat on the way to work or at your desk, eat too quickly, and in general, not truly thinking what you are putting into your mouth. Sound familiar? Most of us are guilty of this.
So what can you do? Eat with awareness. Order food and buy ingredients with health in mind and as your number one priority. Learn and observe the impact of different foods on your digestion and mood. Remember that what you eat directly affects your general well-being.
What Should We Do and Eat?
Our bodies need real, unprocessed foods. Increase your daily intake of:
- Fresh seasonal fruits and vegetables
- Nuts, seeds, fresh and dried beans
- Tofu and sea vegetables
- Whole grains like brown and black rice, buckwheat and millet (and their noodle, bread and snack products)
Drink plenty of water and fresh juice, and limit coffee and sweetened teas. Get more sleep and do more exercise.
How to Start
Today, start by increasing your intake of real whole foods. An easy way to begin is to try or add one new vegetable every week.  Slow down and savor every bite of food. A little more awareness of your eating habits and making small changes is the start of making big impacts on your stress levels and overall mood!
|


BREAKING Call of Duty down: Servers crash leaving gamers unable to connect worldwide
We'll be bringing you the very latest updates, pictures and video on this breaking news story
by Neil MurphyCall of Duty is down for players around the world after the servers crashed.
Reports of problems have spiked in the past hour, according to website Downdetector.com
It is believed the down time is due to the roll out of a new patch.
We'll be bringing you the very latest updates, pictures and video on this breaking news story.
Please check back regularly for updates on this developing story here at Mirror.co.uk .
For the latest news and breaking news visit Mirror.co.uk/news .
Get all the big headlines, pictures, analysis, opinion and video on the stories that matter to you.
Follow us on Twitter @DailyMirror - the official Daily Mirror & Mirror Online Twitter account - real news in real time.
We're also on Facebook /dailymirror - your must-see news, features, videos and pictures throughout the day from the Daily Mirror, Sunday Mirror and Mirror Online.


React will, starting with the next minor version, warn when deprecated lifecycle methods are used. You can learn more about this deprecation in this blog post.
This PR adds a warning for an infinite useEffect loop caused by calling setState without defining a dependency array or one of the dependencies changes on every render.


@* * Copyright 2021 HM Revenue & Customs * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. *@ @import iht.utils.ProgressiveDisclosureHelper._ @import iht.config.AppConfig @this( appConfig: AppConfig ) @(location: String)(implicit request:Request[_], messages: Messages)


HTML tables allow web developers to arrange data into rows and columns.
The HTML
 element represents tabular data — that is, information presented in a two-dimensional table comprised of rows and columns of cells containing data.
The
 element defines a row of cells in a table.
The  element defines a cell as header of a group of table cells. The exact nature of this group is defined by the scope and headers attributes.
The  element defines a cell of a table that contains data.

 Person	 Age

 Chris	 38

 Denis	 45

| Person | Age |
|---|---|
| Chris | 38 |
| Denis | 45 |
styling of css properties for table.
table {
border: 1px solid #333;
border-collapse: collapse;
}
th, td {
padding: 5px;
text-align: center;
}
| Person | Age |
|---|---|
| Chris | 38 |
| Denis | 45 |
The rowspan attribute contains a integer value that indicates for how many rows the cell extends. Its default value is 1. For vertical spanning use rowsapn
Whereas, the colspan attribute contains a integer value that indicates for how many colspan the cell extends. Its default value is 1. For horizontal spanning use colspan

 Category	 Items	 Price

 Fruits	 Apples	 $ 5

 Oranges	 $ 7

 Total	 $ 12

| Category | Items | Price |
|---|---|---|
| Fruits | Apples | $ 5 |
| Oranges | $ 7 | |
| Total | $ 12 |


This important commercial port is located towards the western end of Cyprus' southern coast. It is a popular tourist location and a lively city. The town has a castle, many restaurants and tourist shops.
The new marina (opened 2014) offers good yachting services and is a pleasant spot to spend the winter.
Position 34° 42.50' N, 33° 10.06' E.
Both marinas offer full clearance procedures.
Call Limassol VTS on VHF channel 09 or 16 on approach.
All the authorities are in one building in the commercial harbour.
Last updated November 2015..
Anchoring
Although it is permitted to anchor in the western corner of the commercial harbour, most yachts prefer the fishing harbour in front of the town if they can find space. Here yachts can possibly berth alongside, or, alternatively, berth bows-to at the pier immediately to the east.
Good anchorages can also be found between the marina and the commercial harbour. The one to the west offer the best protection and good holding in sand. The one to the east is more convenient for the town and has excellent hold in mud.
Marinas
St. Raphael Marina in the northern part of the bay is a little remote from the town, being built in deep water and accessed by a causeway.
The newer Limassol Marina, has installed three navigational aids in the waters outside the Marina to help sailors safely approach or exit the Marina.
When approaching from the East, leave the Safe Water Mark to PORT and the Green Lateral Mark to STARBOARD. Then pass between the Green and the Red Lateral Marks to reach the Lighthouse and the entrance to the Marina. When approaching from the South, you will cross the Limassol Commercial Port entrance and shipping channel. Before doing so you will need to get permission from VTS (Limassol Vessel Traffic Services) on VHF Channel 09. After crossing, you may leave the Safe Water Mark to STARBOARD and the Red Lateral Mark to PORT on your way to the Marina entrance.
Located on the breakwater walls on each side of the Marina entrance itself are a Lighthouse , Green Starboard Mark and a Red Port Mark. Rules concerning speed and navigation while in the Marina apply from this point onwards.
A useful report by a boat that wintered here 2014/15 can be found here.
Last updated November 2015.


@Version(value="1.2.2")
See: Description
| Interface | Description |
|---|---|
| AuthenticationFeedbackHandler |
The
AuthenticationFeedbackHandler may be implemented by
AuthenticationHandler services to request being informed on the
success or failure of authentication. |
| AuthenticationHandler |
The
AuthenticationHandler interface defines the service API used
by the authentication implementation to support plugin various ways of
extracting credentials from the request. |
| AuthenticationInfoPostProcessor |
Service interface which allows bundles to modify the AuthenticationInfo object
after authentication has been performed.
|
| Class | Description |
|---|---|
| AbstractAuthenticationFormServlet |
The
AbstractAuthenticationFormServlet provides a basic
implementation of a simple servlet to render a login form for authentication
purposes. |
| AbstractAuthenticationHandler | Deprecated
since Bundle 1.0.8;
AuthenticationHandler implementations
should extend DefaultAuthenticationFeedbackHandler
directly and use the utility methods in the AuthUtil
class. |
| AuthenticationInfo |
The
AuthenticationInfo conveys any authentication credentials
and/or details extracted by the
AuthenticationHandler.extractCredentials(javax.servlet.http.HttpServletRequest, javax.servlet.http.HttpServletResponse)
method from the request. |
| DefaultAuthenticationFeedbackHandler |
| Enum | Description |
|---|---|
| AuthenticationHandler.FAILURE_REASON_CODES |
This enum indicates the supported detailed login failure reason codes:
invalid_login : indicates username/password mismatch.
password_expired : indicates password has expired or was never set and
change initial password is enabled
account_locked : the account was disabled or locked
account_not_found : the account was not found (not the same as username password mismatch)
|
AuthenticationHandler
interface with the
AbstractAuthenticationHandler
being an abstract base implementation from which concrete
implementations may inherit.Copyright © 2018 The Apache Software Foundation. All rights reserved.


Test 123
+
= {{ a + b }}
Enter your name:
Hello {{ name }}
Click to toggle
Show this paragraph 1
Greetings: {{greeting}}
Click checkbox to toggle
Show this paragraph 2


§425-2 Forms to be furnished by director. The registration, annual and other statements required by this part shall be filed on forms to be furnished by the director of commerce and consumer affairs. [L 1969, c 247, pt of §1; am L 1980, c 270, §2; am L 1982, c 204, §8; am L 1983, c 124, §17]


| Time for Outcome | Qty:17 | |
| 00:15:10 | Amount:₹170 | |
| TXN ID:ASDF2005121564863152 | View Selected Spot |
|
Paid through Retailer2 Wallet
|
||
|
Selection Date & Time
20.07.2021 | 11:45:50
|
||
| Selection spot | Qty | (₹) Amount |
| Spot A | 10 | 100 |
| Spot E | 5 | 50 |
| Spot G | 2 | 20 |
| Total | 17 | 170 |
| Time for Outcome | Qty:17 | |
| 00:15:10 | Amount:₹170 | |
| TXN ID:ASDF2005121564863152 | View Selected Spot |
|
Paid through Retailer2 Wallet
|
||
|
Selection Date & Time
20.07.2021 | 11:45:50
|
||
| Selection spot | Qty | (₹) Amount |
| Spot A | 10 | 100 |
| Spot E | 5 | 50 |
| Spot G | 2 | 20 |
| Total | 17 | 170 |
| Outcome Time | Qty:17 | |
| 12:00:00 | Amount:₹170 | |
| TXN ID:ASDF2005121564863152 | View Selected Spot | |
|
Congrats! You have Won ₹450/-
|
|
Paid through Retailer2 Wallet
|
||
|
Selection Date & Time
20.07.2021 | 11:45:50
|
||
| Selection spot | Qty | (₹) Amount |
| Spot A | 10 | 100 |
| Spot E | 5 | 50 |
| Spot G | 2 | 20 |
| Total | 17 | 170 |
|
Congrats! You have Won ₹450/-
|
| Outcome Time | Qty:17 | |
| 12:00:00 | Amount:₹170 | |
| TXN ID:ASDF2005121564863152 | View Selected Spot | |
| Outcome: Spot K | ||
|
Better Luck Next Time...
|
|
Paid through Retailer2 Wallet
|
||
|
Selection Date & Time
20.07.2021 | 11:45:50
|
||
| Selection spot | Qty | (₹) Amount |
| Spot A | 10 | 100 |
| Spot E | 5 | 50 |
| Spot G | 2 | 20 |
| Total | 17 | 170 |
|
Better Luck Next Time...
|


| 004:167 Khan | : |
Verily, those who disbelieve [by concealing the truth about Prophet Muhammad SAW and his message of true Islamic Monotheism written with them in the Taurat (Torah) and the Injeel (Gospel)] and prevent (mankind) from the Path of Allah (Islamic Monotheism), they have certainly strayed far away. (See V.7:157) |
| 004:167 Maulana | : |
Those who disbelieve and hinder (others) from Allah's way, they indeed have erred, going far astray. |
| 004:167 Pickthal | : |
Lo! those who disbelieve and hinder (others) from the way of Allah, they verily have wandered far astray. |
| 004:167 Rashad | : |
Surely, those who disbelieve and repel from the way of GOD have strayed far astray. |
| 004:167 Sarwar | : |
Those who have rejected the faith and have obstructed people from the way of God, have certainly gone far away from the right path. |
| 004:167 Shakir | : |
Surely (as for) those who disbelieve and hinder (men) from Allah's way, they indeed have strayed off into a remote |
| 004:167 Sherali | : |
Those who disbelieve and hinder others from the way of ALLAH, have certainly strayed far away. |
| 004:167 Yusufali | : |
Those who reject Faith and keep off (men) from the way of Allah, have verily strayed far, far away from the Path. |
Concepts/Themes Covered: أركان الإسلام > التوحيد > توحيد الله تعالي > الوعيد Pillars of Islam> Islamic> Oneness of Allah> The Threat أركان الإسلام > التوحيد > الكافرون > صفات الكفار Pillars of Islam> Islamic> The Disbelievers> The Characteristics of the Disbelievers
This tool uses eight English parallel translations for the Holy Quran imported from Mr. Clay Smith. You can also visit Qurany Concepts for browsing the Quran themes or topics. If you want to search the Holy Quran for keywords, please visit Qurany Keywords.


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Popular Areas in country jam 2007 polaris amphitheatre
Abandoned music amphitheater photos: Polaris Amphitheater, post ...
Jul 5, 2011 . Polaris/Germain Amphitheater played host to a whole bunch of big names before closing in 2007. . I continued to work for the company all over the country until I left just a couple years ago for another career. . why don't bands like Phish, the Dead, Pearl Jam and other co-op and buy up these places and .
http://www.donewaiting.com/2011/07/05/photos-polaris-amphitheater-post-mortem/
Cheap Luke Bryan Tickets 2013 - Luke Bryan Concert ... - SeatGeek
Verizon Wireless Amphitheatre Charlotte Charlotte, NC. FROM $448. Tickets. May 3. Fri TBD, Country Megaticket with Rascal Flatts, Brad Paisley, Kenny .
http://seatgeek.com/luke-bryan-tickets/
Def Leppard Tour History - 2007 Tour Dates
2007 | Def Leppard Downstage Thrust Tour Dates .
http://www.deflepparduk.com/tour2007.html
Zac Brown Band Tickets - Ticketmaster
Results 1 - 10 of 12 . Red Rocks Amphitheatre Morrison , CO . Zac Brown Band brought great country jam music to Oakland last night at the beautiful Fox .
http://www.ticketmaster.com/Zac-Brown-Band-tickets/artist/1016048
Def Leppard 2007 Tour Dates! | Hard Rock Hideout
Apr 17, 2007 . Sun 07/08/07 Columbus, OH Germain Amphitheater . Sat 09/08/07 Grand Junction, CO Rock Jam . JOE BONAMASSA On BLACK COUNTRY COMMUNION - "As Far As I'm Concerned, My Involvement Is Pretty Much Done .
http://hardrockhideout.com/2007/04/17/def-leppard-2007-tour-dates/
Charlie Daniels Concert Ticket Stubs
Volunteer Jam VIII - The Charlie Daniels Band - Nashville Municipal . Volunteer Jam - Hank Williams, Jr., The Charlie Daniels Band - Polaris Amphitheatre . The Charlie Daniels Band with Cross Cut Saw - Belmont Country Club (Ashburn, VA) - July . The Outlaws - DTE Energy Music Theatre (Clarkston, MI) - July 7, 2007 .
http://www.lookatstubs.com/bands/charlie_daniels.htm


package main
import "fmt"
func main() {
var arr1 [2][2]int = [2][2]int{
{2, 3},
{4, 5},
}
var arr2 [2][2]int = [2][2]int{
{2, 3},
{4, 5},
}
fmt.Println("Element in first array =", arr1)
fmt.Println("Element in second array =", arr2)
var sum [2][2]int
for i := 0; i < 2; i++ {
for j := 0; j < 2; j++ {
sum[i][j] = arr1[i][j] + arr2[i][j]
}
}
fmt.Println("Sum of first and second array element`s =", sum)
}
Element in first array = [[2 3] [4 5]]
Element in second array = [[2 3] [4 5]]
Sum of first and second array element`s = [[4 6] [8 10]]
In this program, we compute the sum of two array:
arr1 and arr2;
After that store the result of sum in sum array.
And then as an output we display the element`s of arr1, arr2 and sum array.


- New: List of Patreon contributors added into "About" menu dialog
- New: List of various contributors added into "About" menu dialog
- New: Show links on right-click menu
- New: Option to close Platnite after when game is started
- New: German localization (thanks to PhrozenByte)
- New: French localization (thanks to ArtexJay)
- New: Don't add shortcuts when updating
- New: Cover image aspect ratio configurable via theme profiles (GameCoverViewRation variable)
- New: Automatically set sorting name without "The" at the start of titles
- New: Added various help links and tooltips
- New: {PlayniteDir} variable can be used in game action paths
- Fix: Various metadata download fixes and improvements
- Fix: Updated localizations
- Fix: Slow startup time with large game library
- Fix: Restored Modern theme look to original 3.0 release
- Fix: Leaking Chromium processes
- Fix: Database path changes not visible in settings
- Fix: Crash when manual metadata download fails
- Fix: Crash when downloading metadata from igdb
- Fix: Crash when database is not opened
- Fix: Cannot enter spaces into game details fields
- Fix: Auto update failing
- Fix: Tweak database open error messaging


The "Virtual Host" refers to the practice of maintaining more than
one server on one machine, as differentiated by their apparent
hostname. For example, it is often desirable for companies sharing a
web server to have their own domains, with web servers accessible as
www.company1.com
and www.company2.com
,
without requiring the user to know any extra path information.
Apache was one of the first servers to support virtual hosts right
out of the box, but since the base HTTP
(HyperText
Transport Protocol) standard does not allow any method for the server
to determine the hostname it is being addressed as, Apache's virtual
host support has required a separate IP address for each
server. Documentation on using this approach (which still works very
well) is available.
While the approach described above works, with the available IP
address space growing smaller, and the number of domains increasing,
it is not the most elegant solution, and is hard to implement on some
machines. The HTTP/1.1
protocol contains a method for the
server to identify what name it is being addressed as. Apache 1.1 and
later support this approach as well as the traditional
IP-address-per-hostname method.
The benefits of using the new virtual host support is a practically unlimited number of servers, ease of configuration and use, and requires no additional hardware or software. The main disadvantage is that the user's browser must support this part of the protocol. The latest versions of many browsers (including Netscape Navigator 2.0 and later) do, but many browsers, especially older ones, do not. This can cause problems, although a possible solution is addressed below.
Using the new virtual hosts is quite easy, and superficially looks
like the old method. You simply add to one of the Apache configuration
files (most likely httpd.conf
or srm.conf
)
code similar to the following:
<VirtualHost www.apache.org> ServerName www.apache.org DocumentRoot /usr/web/apache </VirtualHost>
Of course, any additional directives can (and should) be placed
into the <VirtualHost>
section. To make this work,
all that is needed is to make sure that the www.apache.org
DNS entry points to the same IP address as the main
server. Optionally, you could simply use that IP address in the
<VirtualHost> entry.
Additionally, many servers may wish to be accessible by more than
one name. For example, the Apache server might want to be accessible
as apache.org
, or ftp.apache.org
, assuming
the IP addresses pointed to the same server. In fact, one might want it
so that all addresses at apache.org
were picked up by the
server. This is possible with the ServerAlias
directive, placed inside the <VirtualHost> section. For
example:
ServerAlias apache.org *.apache.org
Note that you can use *
and ?
as wild-card
characters.
You also might need ServerAlias if you are serving local users who
do not always include the domain name. For example, if local users are
familiar with typing "www" or "www.physics" then you will need to add
ServerAlias www www.physics
. It isn't possible for the
server to know what domain the client uses for their name resolution
because the client doesn't provide that information in the request.
Host:
header through all IP interfaces, even those which
are configured to use different IP interfaces. For example, if the
configuration for www.foo.com
contained a virtual host
section for www.bar.com
, and www.bar.com
was
a separate IP interface, such that
non-Host:
-header-supporting browsers can use it, as
before with Apache 1.0. If a request is made to
www.foo.com
and the request includes the header
Host: www.bar.com
, a page from www.bar.com
will be sent.
This is a security concern if you are controlling access to a
particular server based on IP-layer controls, such as from within a
firewall or router. Let's say www.bar.com
in the above
example was instead an intra-net server called
private.foo.com
, and the router used by foo.com only let
internal users access private.foo.com
. Obviously,
Host:
header functionality now allows someone who has
access to www.foo.com
to get
private.foo.com
, if they send a Host:
private.foo.com
header. It is important to note that this
condition exists only if you only implement this policy at the IP
layer - all security controls used by Apache (i.e., allow, deny from, etc.) are
consistently respected.
As mentioned earlier, a majority of browsers do not send the required data for the new virtual hosts to work properly. These browsers will always be sent to the main server's pages. There is a workaround, albeit a slightly cumbersome one:
To continue the www.apache.org
example (Note: Apache's
web server does not actually function in this manner), we might use the
new ServerPath
directive in the www.apache.org
virtual host, for example:
ServerPath /apache
What does this mean? It means that a request for any file beginning
with "/apache
" will be looked for in the Apache
docs. This means that the pages can be accessed as
http://www.apache.org/apache/
for all browsers, although
new browsers can also access it as
http://www.apache.org/
.
In order to make this work, put a link on your main server's page
to http://www.apache.org/apache/
(Note: Do not use
http://www.apache.org/
- this would create an endless
loop). Then, in the virtual host's pages, be sure to use either purely
relative links (e.g., "file.html
" or
"../icons/image.gif
" or links containing the prefacing
/apache/
(e.g., "http://www.apache.org/apache/file.html
" or
"/apache/docs/1.1/index.html
").
This requires a bit of
discipline, but adherence to these guidelines will, for the most part,
ensure that your pages will work with all browsers, new and old. When
a new browser contacts http://www.apache.org/
, they will
be directly taken to the Apache pages. Older browsers will be able to
click on the link from the main server, go to
http://www.apache.org/apache/
, and then access the
pages.


Ian White
O.js is a Javascript web application framework and object manipulation library that makes it easy to combine prototypical inheritance (extend) and object composition (mixin).
O.js is still experimental. All the things may (and probably will) change.
BODY
:
<body> ... <script src="/path/to/js/jquery.js"></script> <!-- Right about here should do the trick --> <script src="/path/to/js/O.js"></script> </body>Heads up! O.js also works with your favorite browser-based AMD script loaders, like RequireJS.


#!/usr/bin/env python
# -*- coding: utf-8 -*-
"""
A graph representing the struct structures created in memory"
"""
[docs]class Graph(object):
"""A general-purpose graph class"""
def __init__(self, graph_dict=None):
""" initializes a graph object
If no dictionary or None is given, an empty dictionary will be used
"""
if graph_dict == None:
graph_dict = {}
self.__graph_dict = graph_dict
[docs] def vertices(self):
""" returns the vertices of a graph """
return list(self.__graph_dict.keys())
[docs] def edges(self):
""" returns the edges of a graph """
return self.__generate_edges()
[docs] def add_vertex(self, vertex):
""" If the vertex "vertex" is not in
self.__graph_dict, a key "vertex" with an empty
list as a value is added to the dictionary.
Otherwise nothing has to be done.
"""
if vertex not in self.__graph_dict:
self.__graph_dict[vertex] = []
[docs] def add_edge(self, edge):
""" assumes that edge is of type set, tuple or list;
between two vertices can be multiple edges!
"""
edge = set(edge)
vertex1 = edge.pop()
if edge:
# not a loop
vertex2 = edge.pop()
else:
# a loop
vertex2 = vertex1
if vertex1 in self.__graph_dict:
self.__graph_dict[vertex1].append(vertex2)
else:
self.__graph_dict[vertex1] = [vertex2]
def __generate_edges(self):
""" A static method generating the edges of the
graph "graph". Edges are represented as sets
with one (a loop back to the vertex) or two
vertices
"""
edges = []
for vertex in self.__graph_dict:
for neighbour in self.__graph_dict[vertex]:
if {neighbour, vertex} not in edges:
edges.append({vertex, neighbour})
return edges
def __str__(self):
res = "vertices: "
for k in self.__graph_dict:
res += str(k) + " "
res += "\nedges: "
for edge in self.__generate_edges():
res += str(edge) + " "
return res
[docs] def find_isolated_vertices(self):
""" returns a list of isolated vertices. """
graph = self.__graph_dict
isolated = []
for vertex in graph:
print(isolated, vertex)
if not graph[vertex]:
isolated += [vertex]
return isolated
[docs] def find_path(self, start_vertex, end_vertex, path=[]):
""" find a path from start_vertex to end_vertex
in graph """
graph = self.__graph_dict
path = path + [start_vertex]
if start_vertex == end_vertex:
return path
if start_vertex not in graph:
return None
for vertex in graph[start_vertex]:
if vertex not in path:
extended_path = self.find_path(vertex,
end_vertex,
path)
if extended_path:
return extended_path
return None
[docs] def find_all_paths(self, start_vertex, end_vertex, path=[]):
""" find all paths from start_vertex to
end_vertex in graph """
graph = self.__graph_dict
path = path + [start_vertex]
if start_vertex == end_vertex:
return [path]
if start_vertex not in graph:
return []
paths = []
for vertex in graph[start_vertex]:
if vertex not in path:
extended_paths = self.find_all_paths(vertex,
end_vertex,
path)
for p in extended_paths:
paths.append(p)
return paths
[docs] def is_connected(self,
vertices_encountered=None,
start_vertex=None):
""" determines if the graph is connected """
if vertices_encountered is None:
vertices_encountered = set()
gdict = self.__graph_dict
vertices = list(gdict.keys()) # "list" necessary in Python 3
if not start_vertex:
# chosse a vertex from graph as a starting point
start_vertex = vertices[0]
vertices_encountered.add(start_vertex)
if len(vertices_encountered) != len(vertices):
for vertex in gdict[start_vertex]:
if vertex not in vertices_encountered:
if self.is_connected(vertices_encountered, vertex):
return True
else:
return True
return False
[docs] def vertex_degree(self, vertex):
""" The degree of a vertex is the number of edges connecting
it, i.e. the number of adjacent vertices. Loops are counted
double, i.e. every occurence of vertex in the list
of adjacent vertices. """
adj_vertices = self.__graph_dict[vertex]
degree = len(adj_vertices) + adj_vertices.count(vertex)
return degree
[docs] def degree_sequence(self):
""" calculates the degree sequence """
seq = []
for vertex in self.__graph_dict:
seq.append(self.vertex_degree(vertex))
seq.sort(reverse=True)
return tuple(seq)
[docs] @staticmethod
def is_degree_sequence(sequence):
""" Method returns True, if the sequence "sequence" is a
degree sequence, i.e. a non-increasing sequence.
Otherwise False is returned.
"""
# check if the sequence sequence is non-increasing:
return all(x >= y for x, y in zip(sequence, sequence[1:]))
[docs] def delta(self):
""" the minimum degree of the vertices """
min = 100000000
for vertex in self.__graph_dict:
vertex_degree = self.vertex_degree(vertex)
if vertex_degree < min:
min = vertex_degree
return min
[docs] def Delta(self):
""" the maximum degree of the vertices """
max = 0
for vertex in self.__graph_dict:
vertex_degree = self.vertex_degree(vertex)
if vertex_degree > max:
max = vertex_degree
return max
[docs] def density(self):
""" method to calculate the density of a graph """
g = self.__graph_dict
V = len(g.keys())
E = len(self.edges())
return 2.0 * E / (V * (V - 1))
[docs] def diameter(self):
""" calculates the diameter of the graph """
v = self.vertices()
pairs = [(v[i], v[j]) for i in range(len(v)) for j in range(i + 1, len(v) - 1)]
smallest_paths = []
for (s, e) in pairs:
paths = self.find_all_paths(s, e)
smallest = sorted(paths, key=len)[0]
smallest_paths.append(smallest)
smallest_paths.sort(key=len)
# longest path is at the end of list,
# i.e. diameter corresponds to the length of this path
diameter = len(smallest_paths[-1])
return diameter
[docs] @staticmethod
def erdoes_gallai(dsequence):
""" Checks if the condition of the Erdoes-Gallai inequality
is fullfilled
"""
if sum(dsequence) % 2:
# sum of sequence is odd
return False
if Graph.is_degree_sequence(dsequence):
for k in range(1, len(dsequence) + 1):
left = sum(dsequence[:k])
right = k * (k - 1) + sum([min(x, k) for x in dsequence[k:]])
if left > right:
return False
else:
# sequence is increasing
return False
return True


Wednesday 23rd Febuary 2017
Images, artists, country -- award:
The Song, Vadim Gousmanov, Russia -- Master
DON KICHOT, Mateusz Lenart, Poland -- Excellence
Uncharted 3 tribute artwork, Cyril Terpent, France
Save Dan, Jude Smith, Canada
Industrial Racing, Jan van de Klooster, France
Flying High, Charlotte Hintzmann, Germany


We went to Nakuru national park.
We had lunch at Travelers Inn on the old Nairobi Nakuru road.
We went back to Epashikino hotel


FIRE BIRDS A film review by Robert Dorsett Copyright 1990 Robert Dorsett
The previews of FIRE BIRDS make it out to be another TOP GUN: when I first saw them, my reaction was "is that legal?" The plots seemed to be almost identical. Well, I was wrong: the plots are slightly different, and TOP GUN is the better movie. I kid you not.
FIRE BIRDS is a confused (or, in the words of one patron in the audience, "stupid") movie that pitches AH-64 Apaches against the Villain of the Week, the "drug cartel." Its central characters are two rather egocentric, immature men, one a pilot (played by Nicholas Cage), the other his instructor (played by Tommy Lee Jones). No, kids, Sean Young doesn't play a terribly noteworthy role, except, perhaps, to give women someone to identify with (I am starting to understand the bean counters in Hollywood, and strongly suspect this to be the case). All three pilots are Good. Damned Good. The Best. You know the type. :-)
The story (let's see if I got this right) has a group of Apache pilots being trained to provide air support for a Gesta--uh, DEA, raid against some kind of summit conference of Drug Lords. Cage plays the young bronco, Young the love interest. Besides personality problems, Cage has a problem flying with a night vision gizmo (which turns out to be utterly irrelevant), and develops a competition of wits with his instructor, who has just turned 40.
The two bright spots in the movie are the character of Jones, as well as his performance; and the nice photography. Unlike TOP GUN, the dogfights in this movie can actually be followed. If one ignores the absurdity of pushing the old Apache (or any helicopter) as a fighter (the movie got extensive support from the Army and McDonnell Douglas, so its PR aspect is undoubtedly well considered), most of the combat sequences are pretty fun.
Problem is, though, one has to wade through some of the stupidest, corniest dialog of all time, in order to get to the good parts. For this reason, I give this movie a 6/10 rating.
In terms of letter grades, here's how it stocks against the other "Summer Blockbusters" so far: CADILLAC MAN C+ FIRE BIRDS C BIRD ON A WIRE D Some may question my assigning letter grades to these flicks, but this *is* a competition to see who makes the most money, and grades *are* a commonly-used means assigning relative standards of mediocrity. :-) Not even the shallowest movie-goer can call these Works of Art. Although some have tried their best-- a few on this very newsgroup! :-) :-)
--- Robert Dorsett, disappointed in the summer's crop of movies so far. Internet<EMAIL_ADDRESS>UUCP: ...cs.utexas.edu!rascal.ics.utexas.edu!rdd
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