| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [23] | RHIEN7 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [24] | RHIEN8 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [25] | RHIEN9 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [26] | RHIEN10 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [27] | RHIEN11 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [28] | RHIEN12 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [29] | RHIEN13 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [30] | RHIEN14 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [31] | RHIEN15 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
| TIMER_T::INTEN |
[0x000c] Timer Interrupt Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CNTIEN | Timer Interrupt Enable Bit |
| 0 = Timer Interrupt Disabled. | ||
| 1 = Timer Interrupt Enabled. | ||
| Note: If this bit is enabled, when the timer interrupt flag CNTIF (TIMERx_INTSTS[0]) is set to 1, the timer interrupt signal is generated and informed to CPU. | ||
| [1] | CAPIEN | Timer External Capture Interrupt Enable Bit |
| 0 = Tx_EXT (x= 0~3) pin detection Interrupt Disabled. | ||
| 1 = Tx_EXT (x= 0~3) pin detection Interrupt Enabled. | ||
| Note: CAPIEN is used to enable timer external interrupt | ||
| If CAPIEN is enabled, the timer will rise an interrupt when CAPIF (TIMERx_INTSTS[1]) is 1. |
| WDT_T::INTEN |
| WWDT_T::INTEN |
[0x0008] Window Watchdog Timer Interrupt Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WWDTIE | WWDT Interrupt Enable Bit |
| Setting this bit will enable the Window Watchdog timer interrupt function. | ||
| 0 = Watchdog timer interrupt function Disabled. | ||
| 1 = Watchdog timer interrupt function Enabled. |
| RTC_T::INTEN |
[0x0028] RTC Interrupt Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ALMIEN | Alarm Interrupt Enable Bit |
| 0 = RTC Alarm interrupt Disabled. | ||
| 1 = RTC Alarm interrupt Enabled. | ||
| [1] | TICKIEN | Time Tick Interrupt Enable Bit |
| 0 = RTC Time Tick interrupt Disabled. | ||
| 1 = RTC Time Tick interrupt Enabled. | ||
| [2] | SNPDIEN | Snoop Detection Interrupt Enable Bit |
| 0 = Snoop detected interrupt Disabled. | ||
| 1 = Snoop detected interrupt Enabled. |
| UART_T::INTEN |
[0x000c] UART Interrupt Enable Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDAIEN | Receive Data Available Interrupt Enable Bit |
| 0 = Receive data available interrupt Disabled. | ||
| 1 = Receive data available interrupt Enabled. | ||
| [1] | THREIEN | Transmit Holding Register Empty Interrupt Enable Bit |
| 0 = Transmit holding register empty interrupt Disabled. | ||
| 1 = Transmit holding register empty interrupt Enabled. | ||
| [2] | RLSIEN | Receive Line Status Interrupt Enable Bit |
| 0 = Receive Line Status interrupt Disabled. | ||
| 1 = Receive Line Status interrupt Enabled. | ||
| [3] | MODEMIEN | Modem Status Interrupt Enable Bit |
| 0 = Modem status interrupt Disabled. | ||
| 1 = Modem status interrupt Enabled. | ||
| [4] | RXTOIEN | RX Time-out Interrupt Enable Bit |
| 0 = RX time-out interrupt Disabled. | ||
| 1 = RX time-out interrupt Enabled. | ||
| [5] | BUFERRIEN | Buffer Error Interrupt Enable Bit |
| 0 = Buffer error interrupt Disabled. | ||
| 1 = Buffer error interrupt Enabled. | ||
| [6] | WKUPIEN | Wake-up Interrupt Enable Bit |
| 0 = Wake-up system function Disabled. | ||
| 1 = Wake-up system function Enabled, when the system is in Power-down mode, one of the wake-up event will wake-up system from Power-down mode. | ||
| Note: Hardware will clear one of the wake-up status bits in UART_WKUPSTS when the wake-up operation finishes and system clock work stable | ||
| [7] | ABRIEN | Auto-baud Rate Interrupt Enable Bit |
| 0 = Auto-baud rate interrupt Disabled. | ||
| 1 = Auto-baud rate interrupt Enabled. | ||
| [8] | LINIEN | LIN Bus Interrupt Enable Bit |
| 0 = LIN bus interrupt Disabled. | ||
| 1 = LIN bus interrupt Enabled. | ||
| Note: This bit is used for LIN function mode. | ||
| [9] | TXENDIEN | Transmitter Empty Interrupt Enable Bit |
| 0 = Transmit Empty interrupt Disabled. | ||
| 1 = Transmit Empty interrupt Enabled. | ||
| Note: If the bit is enabled, there is interrupt event when the TXENDF (UART_FSR[11]) is activated. |
| SC_T::INTEN |
[0x0018] SC Interrupt Enable Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDAIEN | Receive Data Reach Interrupt Enable Bit |
| This field is used to enable received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt. | ||
| 0 = Receive data reach trigger level interrupt Disabled. | ||
| 1 = Receive data reach trigger level interrupt Enabled. | ||
| [1] | TBEIEN | Transmit Buffer Empty Interrupt Enable Bit |
| This field is used to enable transmit buffer empty interrupt. | ||
| 0 = Transmit buffer empty interrupt Disabled. | ||
| 1 = Transmit buffer empty interrupt Enabled. | ||
| [2] | TERRIEN | Transfer Error Interrupt Enable Bit |
| This field is used to enable transfer error interrupt | ||
| The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]). | ||
| 0 = Transfer error interrupt Disabled. | ||
| 1 = Transfer error interrupt Enabled. | ||
| [3] | TMR0IEN | Timer0 Interrupt Enable Bit |
| This field is used to enable TMR0 interrupt. | ||
| 0 = Timer0 interrupt Disabled. | ||
| 1 = Timer0 interrupt Enabled. | ||
| [4] | TMR1IEN | Timer1 Interrupt Enable Bit |
| This field is used to enable the TMR1 interrupt. | ||
| 0 = Timer1 interrupt Disabled. | ||
| 1 = Timer1 interrupt Enabled. | ||
| [5] | TMR2IEN | Timer2 Interrupt Enable Bit |
| This field is used to enable TMR2 interrupt. | ||
| 0 = Timer2 interrupt Disabled. | ||
| 1 = Timer2 interrupt Enabled. | ||
| [6] | BGTIEN | Block Guard Time Interrupt Enable Bit |
| This field is used to enable block guard time interrupt. | ||
| 0 = Block guard time Disabled. | ||
| 1 = Block guard time Enabled. | ||
| [7] | CDIEN | Card Detect Interrupt Enable Bit |
| This field is used to enable card detect interrupt. The card detect status is CINSERT(SC_STATUS[12]) | ||
| 0 = Card detect interrupt Disabled. | ||
| 1 = Card detect interrupt Enabled. | ||
| [8] | INITIEN | Initial End Interrupt Enable Bit |
| This field is used to enable activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation ((DACTEN SC_ALTCTL[2]) = 1) and warm reset (WARSTEN (SC_ALTCTL [4])) sequence interrupt. | ||
| 0 = Initial end interrupt Disabled. | ||
| 1 = Initial end interrupt Enabled. | ||
| [9] | RXTOIEN | Receiver Buffer Time-out Interrupt Enable Bit |
| This field is used to enable receiver buffer time-out interrupt. | ||
| 0 = Receiver buffer time-out interrupt Disabled. | ||
| 1 = Receiver buffer time-out interrupt Enabled. | ||
| [10] | ACERRIEN | Auto Convention Error Interrupt Enable Bit |
| This field is used to enable auto-convention error interrupt. | ||
| 0 = Auto-convention error interrupt Disabled. | ||
| 1 = Auto-convention error interrupt Enabled. |
| PWM_T::INTEN0 |
[0x00e0] PWM0 Interrupt Enable Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ZIEN0 | PWM0 Zero Point Interrupt Enable Bit 0 |
| 0 = PWM0 counter0_1 zero point interrupt Disabled. | ||
| 1 = PWM0 counter0_1 zero point interrupt Enabled. | ||
| Note: Odd channels will read always 0 at complementary mode. | ||
| [2] | ZIEN2 | PWM0 Zero Point Interrupt Enable Bit 2 |
| 0 = PWM0 counter2_3 zero point interrupt Disabled. | ||
| 1 = PWM0 counter2_3 zero point interrupt Enabled. | ||
| Note: Odd channels will read always 0 at complementary mode. | ||
| [4] | ZIEN4 | PWM0 Zero Point Interrupt Enable Bit 4 |
| 0 = PWM0 counter4_5 zero point interrupt Disabled. | ||
| 1 = PWM0 counter4_5 zero point interrupt Enabled. | ||
| Note: Odd channels will read always 0 at complementary mode. | ||
| [8] | PIEN0 | PWM0 Period Point Interrupt Enable Bit 0 |
| 0 = PWM0 counter0_1 period point interrupt Disabled. | ||
| 1 = PWM0 counter0_1 period point interrupt Enabled. | ||
| Note: When operating in up-down counter type, period point means center point. | ||
| [10] | PIEN2 | PWM0 Period Point Interrupt Enable Bit 2 |
| 0 = PWM0 counter2_3 period point interrupt Disabled. | ||
| 1 = PWM0 counter2_3 period point interrupt Enabled. | ||
| Note: When operating in up-down counter type, period point means center point. | ||
| [12] | PIEN4 | PWM0 Period Point Interrupt Enable Bit 4 |
| 0 = PWM0 counter4_5 period point interrupt Disabled. | ||
| 1 = PWM0 counter4_5 period point interrupt Enabled. | ||
| Note: When operating in up-down counter type, period point means center point. | ||
| [21:16] | CMPUIENn | PWM0 Compare Up Count Interrupt Enable Bits |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = Compare up count interrupt Disabled. | ||
| 1 = Compare up count interrupt Enabled. | ||
| Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. | ||
| [29:24] | CMPDIENn | PWM0 Compare Down Count Interrupt Enable Bits |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = Compare down count interrupt Disabled. | ||
| 1 = Compare down count interrupt Enabled. | ||
| Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. |
| PWM_T::INTEN1 |
[0x00e4] PWM0 Interrupt Enable Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BRKEIEN0_1 | PWM0 Edge-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect) |
| 0 = Edge-detect Brake interrupt for channel0/1 Disabled. | ||
| 1 = Edge-detect Brake interrupt for channel0/1 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [1] | BRKEIEN2_3 | PWM0 Edge-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect) |
| 0 = Edge-detect Brake interrupt for channel2/3 Disabled. | ||
| 1 = Edge-detect Brake interrupt for channel2/3 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [2] | BRKEIEN4_5 | PWM0 Edge-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect) |
| 0 = Edge-detect Brake interrupt for channel4/5 Disabled. | ||
| 1 = Edge-detect Brake interrupt for channel4/5 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [8] | BRKLIEN0_1 | PWM0 Level-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect) |
| 0 = Level-detect Brake interrupt for channel0/1 Disabled. | ||
| 1 = Level-detect Brake interrupt for channel0/1 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [9] | BRKLIEN2_3 | PWM0 Level-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect) |
| 0 = Level-detect Brake interrupt for channel2/3 Disabled. | ||
| 1 = Level-detect Brake interrupt for channel2/3 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [10] | BRKLIEN4_5 | PWM0 Level-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect) |
| 0 = Level-detect Brake interrupt for channel4/5 Disabled. | ||
| 1 = Level-detect Brake interrupt for channel4/5 Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| PDMA_CH_T::INTENn |
[0x0020] PDMA channel n Interrupt Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TABTIEN | PDMA Read/Write Target Abort Interrupt Enable Bit |
| 0 = Target abort interrupt Disabled during PDMA transfer. | ||
| 1 = Target abort interrupt Enabled during PDMA transfer. | ||
| [1] | TDIEN | PDMA Transfer Done Interrupt Enable Bit |
| 0 = Interrupt Disabled when PDMA transfer is done. | ||
| 1 = Interrupt Enabled when PDMA transfer is done. | ||
| [6] | TOUTIEN | Time-out Interrupt Enable Bit |
| 0 = Time-out interrupt Disabled. | ||
| 1 = Time-out interrupt Enabled. | ||
| [8] | PCNTIEN | Periodic Count Interrupt Enable Bit |
| This field indicates how many data transferred to generate interrupt periodically. | ||
| 0 = Periodic transfer count interrupt Disabled. | ||
| 1 = Periodic transfer count interrupt Enabled. |
| GPIO_T::INTSRC |
[0x0020] Pn Interrupt Source Flag
| Bits | Field | Descriptions |
|---|---|---|
| [0] | INTSRC0 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [1] | INTSRC1 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [2] | INTSRC2 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [3] | INTSRC3 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [4] | INTSRC4 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [5] | INTSRC5 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [6] | INTSRC6 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [7] | INTSRC7 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [8] | INTSRC8 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [9] | INTSRC9 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [10] | INTSRC10 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [11] | INTSRC11 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [12] | INTSRC12 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [13] | INTSRC13 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [14] | INTSRC14 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [15] | INTSRC15 | Port A-f Pin[N] Interrupt Source Flag |
| Write Operation : | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation : | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
| GPIO_T::INTSTS |
[0x0028] Pn Interrupt Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FLISTS0 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [1] | FLISTS1 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [2] | FLISTS2 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [3] | FLISTS3 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [4] | FLISTS4 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [5] | FLISTS5 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [6] | FLISTS6 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [7] | FLISTS7 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [8] | FLISTS8 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [9] | FLISTS9 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [10] | FLISTS10 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [11] | FLISTS11 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [12] | FLISTS12 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [13] | FLISTS13 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [14] | FLISTS14 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [15] | FLISTS15 | Port A-f Pin[N] Falling Edge Interrupt Status |
| If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No falling edge interrupt at Px.n. | ||
| 1 = Px.n generates an falling edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [16] | RHISTS0 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [17] | RHISTS1 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [18] | RHISTS2 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [19] | RHISTS3 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [20] | RHISTS4 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [21] | RHISTS5 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [22] | RHISTS6 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [23] | RHISTS7 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [24] | RHISTS8 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [25] | RHISTS9 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [26] | RHISTS10 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [27] | RHISTS11 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [28] | RHISTS12 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [29] | RHISTS13 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [30] | RHISTS14 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [31] | RHISTS15 | Port A-f Pin[N] Rising Edge Interrupt Status |
| If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])). | ||
| 0 = No rising edge interrupt at Px.n. | ||
| 1 = Px.n generates an rising edge interrupt. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
| TIMER_T::INTSTS |
[0x0010] Timer Interrupt Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CNTIF | Timer Interrupt Status |
| This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. | ||
| 0 = No effect. | ||
| 1 = CNT (TIMERx_CNT[23:0]) value matches the CMPDAT (TIMERx_CMP[23:0]) value. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [1] | CAPIF | Timer External Capture Interrupt Flag |
| This bit indicates the timer external capture interrupt flag status. | ||
| 0 = Tx_EXT (x= 0~3) pin interrupt did not occur. | ||
| 1 = Tx_EXT (x= 0~3) pin interrupt occurred. | ||
| Note1: This bit is cleared by writing 1 to it. | ||
| Note2: When CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting, this bit will set to 1 by hardware. | ||
| Note3: If a new incoming capture event detected before CPU clearing the CAPIF status, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. | ||
| [4] | TWKF | Timer Wake-up Flag |
| This bit indicates the interrupt wake-up flag status of timer. | ||
| 0 = Timer does not cause CPU wake-up. | ||
| 1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [5] | CAPDATOF | Capture Data Overflow Flag |
| This status is to indicate there is a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status. | ||
| If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. | ||
| 0 = New incoming capture event didnu2019t detect before CPU clearing CAPIF (TIMERx_INTSTS[1]) status. | ||
| 1 = New incoming capture event detected before CPU clearing CAPIF (TIMERx_INTSTS[1]) status. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [6] | CAPFEDF | Capture Falling Edge Detected Flag |
| This flag indicates the edge detected on Tx_EXT pin is rising edge or falling edge. | ||
| 0 = Rising edge detected on Tx_EXT pin. | ||
| 1 = Falling edge detected on Tx_EXT pin. | ||
| Note1: The timer updates this flag when it updates the Timer Capture Data (TMR_CAP[23:0]) value. | ||
| Note2: When a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status, Timer will keep this bit unchanged. |
| RTC_T::INTSTS |
[0x002c] RTC Interrupt Indicator Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ALMIF | RTC Alarm Interrupt Flag |
| When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1 | ||
| Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode. | ||
| 0 = Alarm condition is not matched. | ||
| 1 = Alarm condition is matched. | ||
| Note: Write 1 to clear this bit. | ||
| [1] | TICKIF | RTC Time Tick Interrupt Flag |
| When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1 | ||
| Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode. | ||
| 0 = Tick condition does not occur. | ||
| 1 = Tick condition occur. | ||
| Note: Write 1 to clear to clear this bit. | ||
| [2] | SNPDIF | Snoop Detect Interrupt Flag |
| When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1 | ||
| Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled. | ||
| 0 = No snoop event is detected. | ||
| 1 = Snoop event is detected. | ||
| Note: Write 1 to clear this bit. |
| UART_T::INTSTS |
[0x0010] UART Interrupt Status Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDAIF | Receive Data Available Interrupt Flag (Read Only) |
| When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_ISR[0]) will be set | ||
| If RDAIEN (UART_IER [0]) is enabled, the RDA interrupt will be generated. | ||
| 0 = No RDA interrupt flag is generated. | ||
| 1 = RDA interrupt flag is generated. | ||
| Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_TLCTL[9:8]) | ||
| [1] | THREIF | Transmit Holding Register Empty Interrupt Flag (Read Only) |
| This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register | ||
| If THREIEN (UART_IER[1]) is enabled, the THRE interrupt will be generated. | ||
| 0 = No THRE interrupt flag is generated. | ||
| 1 = THRE interrupt flag is generated. | ||
| Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty) | ||
| [2] | RLSIF | Receive Line Interrupt Flag (Read Only) |
| This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FSR[6]), FEF(UART_FSR[5]) and PEF(UART_FSR[4]), is set) | ||
| If RLSIEN (UART_IER [2]) is enabled, the RLS interrupt will be generated. | ||
| 0 = No RLS interrupt flag is generated. | ||
| 1 = RLS interrupt flag is generated. | ||
| Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit" | ||
| At the same time, the bit of ADDRDETF (UART_TRSR[0]) is also set. | ||
| Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FSR[6]), FEF(UART_FSR[5]) and PEF(UART_FSR[4]) are cleared. | ||
| Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FSR[6]) , FEF(UART_FSR[5]) and PEF(UART_FSR[4]) and ADDRDETF (UART_TRSR[0]) are cleared. | ||
| [3] | MODEMIF | MODEM Interrupt Flag (Read Only) Channel |
| This bit is set when the nCTS pin has state change (CTSDETF (UART_MCSR[18]) = 1) | ||
| If MODEMIEN (UART_IER [3]) is enabled, the Modem interrupt will be generated. | ||
| 0 = No Modem interrupt flag is generated. | ||
| 1 = Modem interrupt flag is generated. | ||
| Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MCSR[18]). | ||
| [4] | RXTOIF | Rime-out Interrupt Flag (Read Only) |
| This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC | ||
| If RXTOIEN (UART_IER [4]) is enabled, the Tout interrupt will be generated. | ||
| 0 = No Time-out interrupt flag is generated. | ||
| 1 = Time-out interrupt flag is generated. | ||
| Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it | ||
| [5] | BUFERRIF | Buffer Error Interrupt Flag (Read Only) |
| This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FSR[8]) or RXOVIF (UART_FSR[0]) is set) | ||
| When BUFERRIF (UART_ISR[5])is set, the transfer is not correct | ||
| If BFERRIEN (UART_IER [5]) is enabled, the buffer error interrupt will be generated. | ||
| 0 = No buffer error interrupt flag is generated. | ||
| 1 = Buffer error interrupt flag is generated. | ||
| Note: This bit is read only | ||
| This bit is cleared if both of RXOVIF(UART_FSR[0]) and TXOVIF(UART_FSR[8]) are cleared to 0 by writing 1 to RXOVIF(UART_FSR[0]) and TXOVIF(UART_FSR[8]). | ||
| [6] | WKUPIF | Wake-up Interrupt Flag (Read Only) |
| This bit is set if chip wake-up from power-down state by one of UART controller wake-up event. | ||
| 0 = Chip stays in power-down state. | ||
| 1 = Chip wake-up from power-down state by one of UART controller wake-up event. | ||
| Note1: If WKDATEN (UART_IER[6]) is enabled, the wake-up interrupt is generated. | ||
| Note2: This bit is read only, but can be cleared by writing '1' to one of UART_WKUPSTS[4:0] (THRTOWKSTS or THRWKSTS or CTSWKSTS or DATWKSTS or ADRWKSTS). | ||
| [7] | ABRIF | Auto-baud Rate Interrupt Status Flag (Read Only) |
| This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_IER[7]) is set then the auto-baud rate interrupt will be generated. | ||
| 0 = No Auto-Baud Rate interrupt is generated. | ||
| 1 = Auto-Baud Rate interrupt is generated. | ||
| Note1: This bit is read only, but can be cleared by writing 1 to ABRDTOIF (UART_TRSR[2]) or ABRDIF (UART_TRSR[1]). | ||
| Note2: This bit is cleared when both the ABRDTOIF and ABRDIF are cleared. | ||
| [8] | LINIF | LIN Interrupt Status Flag (Read Only) |
| This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LINIEN(UART_IER[8]) is set then the LIN interrupt will be generated. | ||
| 0 = No LIN interrupt is generated. | ||
| 1 = LIN interrupt is generated. | ||
| Note1: This bit is read only, but can be cleared by it by writing 1 to BITEF (UART_TRSR[5]), LINTXIF (UART_TRSR[3]) or LINRXIF (UART_TRSR[4]). | ||
| Note2: This bit is cleared when both the BITEF, LINTXIF and LINRXIF are cleared. |
| SC_T::INTSTS |
[0x001c] SC Interrupt Status Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDAIF | Receive Data Reach Interrupt Status Flag (Read Only) |
| This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag. | ||
| Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]) | ||
| If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically. | ||
| [1] | TBEIF | Transmit Buffer Empty Interrupt Status Flag (Read Only) |
| This field is used for transmit buffer empty interrupt status flag. | ||
| Note: This field is the status flag of transmit buffer empty state | ||
| If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically. | ||
| [2] | TERRIF | Transfer Error Interrupt Status Flag (Read Only) |
| This field is used for transfer error interrupt status flag | ||
| The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30]). | ||
| Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]) | ||
| So, if software wants to clear this bit, software must write 1 to each field. | ||
| [3] | TMR0IF | Timer0 Interrupt Status Flag (Read Only) |
| This field is used for TMR0 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [4] | TMR1IF | Timer1 Interrupt Status Flag (Read Only) |
| This field is used for TMR1 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [5] | TMR2IF | Timer2 Interrupt Status Flag (Read Only) |
| This field is used for TMR2 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [6] | BGTIF | Block Guard Time Interrupt Status Flag (Read Only) |
| This field is used for block guard time interrupt status flag. | ||
| Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled. | ||
| Note2: This bit is read only, but it can be cleared by writing u201C1u201D to it. | ||
| [7] | CDIF | Card Detect Interrupt Status Flag (Read Only) |
| This field is used for card detect interrupt status flag | ||
| The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]). | ||
| Note: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])] | ||
| So if software wants to clear these bits, software must write 1 to these field. | ||
| [8] | INITIF | Initial End Interrupt Status Flag (Read Only) |
| This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [9] | RXTOIF | Receiver Buffer Time-out Interrupt Status Flag (Read Only) |
| This field is used for receiver buffer time-out interrupt status flag. | ||
| Note: This field is the status flag of receiver buffer time-out state | ||
| If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer, | ||
| [10] | ACERRIF | Auto Convention Error Interrupt Status Flag (Read Only) |
| This field indicates auto convention sequence error | ||
| If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. |
| I2C_T::INTSTS |
[0x0004] I2C Interrupt Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | INTSTS | I2C STATUS's Interrupt Status |
| When a new I2C state is present in the I2C_STATUS register, the INTSTS flag is set by hardware | ||
| If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.This bit must be cleared by software writing 1 . | ||
| Note: If software wants to skip clearing INTSTS, it can also write 1 to SI (I2C_CTL [4]) bit and must set INTEN (I2C_CTL [7]) bit | ||
| INISTS will be cleared when SI is cleared. | ||
| [1] | TOIF | Time-out Status |
| 0 = No Time-out flag. | ||
| 1 = Time-out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set. | ||
| Note: This bit can be cleared by writing 1 to it. | ||
| [7] | WKAKDONE | Wake-up Address Frame Acknowledge Bit Done |
| 0 = The ACK bit cycle of address match frame is not done. | ||
| 1 = The ACK bit cycle of address match frame is done in power-down. | ||
| Note: This bit can be cleared by writing 1 to it. |
| PWM_T::INTSTS0 |
[0x00e8] PWM0 Interrupt Flag Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ZIF0 | PWM0 Zero Point Interrupt Flag 0 |
| This bit is set by hardware when PWM0_CH0 counter reaches zero, software can write 1 to clear this bit to zero. | ||
| [2] | ZIF2 | PWM0 Zero Point Interrupt Flag 2 |
| This bit is set by hardware when PWM0_CH2 counter reaches zero, software can write 1 to clear this bit to zero. | ||
| [4] | ZIF4 | PWM0 Zero Point Interrupt Flag 4 |
| This bit is set by hardware when PWM0_CH4 counter reaches zero, software can write 1 to clear this bit to zero. | ||
| [8] | PIF0 | PWM0 Period Point Interrupt Flag 0 |
| This bit is set by hardware when PWM0_CH0 counter reaches PWM0_PERIOD0, software can write 1 to clear this bit to zero. | ||
| [10] | PIF2 | PWM0 Period Point Interrupt Flag 2 |
| This bit is set by hardware when PWM0_CH2 counter reaches PWM0_PERIOD2, software can write 1 to clear this bit to zero. | ||
| [12] | PIF4 | PWM0 Period Point Interrupt Flag 4 |
| This bit is set by hardware when PWM0_CH4 counter reaches PWM0_PERIOD4, software can write 1 to clear this bit to zero. | ||
| [21:16] | CMPUIFn | PWM0 Compare Up Count Interrupt Flag |
| Flag is set by hardware when PWM0 counter up count and reaches PWM0_CMPDATn, software can clear this bit by writing 1 to it | ||
| Each bit n controls the corresponding PWM0 channel n. | ||
| Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. | ||
| Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. | ||
| [29:24] | CMPDIFn | PWM0 Compare Down Count Interrupt Flag |
| Each bit n controls the corresponding PWM0 channel n. | ||
| Flag is set by hardware when PWM0 counter down count and reaches PWM0_CMPDATn, software can clear this bit by writing 1 to it. | ||
| Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. | ||
| Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. |
| PWM_T::INTSTS1 |
[0x00ec] PWM0 Interrupt Flag Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BRKEIF0 | PWM0 Channel0 Edge-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel0 edge-detect brake event do not happened. | ||
| 1 = When PWM0 channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [1] | BRKEIF1 | PWM0 Channel1 Edge-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel1 edge-detect brake event do not happened. | ||
| 1 = When PWM0 channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [2] | BRKEIF2 | PWM0 Channel2 Edge-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel2 edge-detect brake event do not happened. | ||
| 1 = When PWM0 channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [3] | BRKEIF3 | PWM0 Channel3 Edge-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel3 edge-detect brake event do not happened. | ||
| 1 = When PWM0 channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [4] | BRKEIF4 | PWM0 Channel4 Edge-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel4 edge-detect brake event do not happened. | ||
| 1 = When PWM0 channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [5] | BRKEIF5 | PWM0 Channel5 Edge-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel5 edge-detect brake event do not happened. | ||
| 1 = When PWM0 channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [8] | BRKLIF0 | PWM0 Channel0 Level-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel0 level-detect brake event do not happened. | ||
| 1 = When PWM0 channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [9] | BRKLIF1 | PWM0 Channel1 Level-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel1 level-detect brake event do not happened. | ||
| 1 = When PWM0 channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [10] | BRKLIF2 | PWM0 Channel2 Level-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel2 level-detect brake event do not happened. | ||
| 1 = When PWM0 channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [11] | BRKLIF3 | PWM0 Channel3 Level-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel3 level-detect brake event do not happened. | ||
| 1 = When PWM0 channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [12] | BRKLIF4 | PWM0 Channel4 Level-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel4 level-detect brake event do not happened. | ||
| 1 = When PWM0 channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [13] | BRKLIF5 | PWM0 Channel5 Level-detect Brake Interrupt Flag (Write Protect) |
| 0 = PWM0 channel5 level-detect brake event do not happened. | ||
| 1 = When PWM0 channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [16] | BRKESTS0 | PWM0 Channel0 Edge-detect Brake Status (Read Only) |
| 0 = PWM0 channel0 edge-detect brake state is released. | ||
| 1 = When PWM0 channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel0 at brake state, writing 1 to clear. | ||
| [17] | BRKESTS1 | PWM0 Channel1 Edge-detect Brake Status (Read Only) |
| 0 = PWM0 channel1 edge-detect brake state is released. | ||
| 1 = When PWM0 channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel1 at brake state, writing 1 to clear. | ||
| [18] | BRKESTS2 | PWM0 Channel2 Edge-detect Brake Status (Read Only) |
| 0 = PWM0 channel2 edge-detect brake state is released. | ||
| 1 = When PWM0 channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel2 at brake state, writing 1 to clear. | ||
| [19] | BRKESTS3 | PWM0 Channel3 Edge-detect Brake Status (Read Only) |
| 0 = PWM0 channel3 edge-detect brake state is released. | ||
| 1 = When PWM0 channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel3 at brake state, writing 1 to clear. | ||
| [20] | BRKESTS4 | PWM0 Channel4 Edge-detect Brake Status (Read Only) |
| 0 = PWM0 channel4 edge-detect brake state is released. | ||
| 1 = When PWM0 channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel4 at brake state, writing 1 to clear. | ||
| [21] | BRKESTS5 | PWM0 Channel5 Edge-detect Brake Status (Read Only) |
| 0 = PWM0 channel5 edge-detect brake state is released. | ||
| 1 = When PWM0 channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel5 at brake state, writing 1 to clear. | ||
| [24] | BRKLSTS0 | PWM0 Channel0 Level-detect Brake Status (Read Only) |
| 0 = PWM0 channel0 level-detect brake state is released. | ||
| 1 = When PWM0 channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel0 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware | ||
| When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
| The PWM0 waveform will start output from next full PWM0 period. | ||
| [25] | BRKLSTS1 | PWM0 Channel1 Level-detect Brake Status (Read Only) |
| 0 = PWM0 channel1 level-detect brake state is released. | ||
| 1 = When PWM0 channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel1 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware | ||
| When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
| The PWM0 waveform will start output from next full PWM0 period. | ||
| [26] | BRKLSTS2 | PWM0 Channel2 Level-detect Brake Status (Read Only) |
| 0 = PWM0 channel2 level-detect brake state is released. | ||
| 1 = When PWM0 channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel2 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware | ||
| When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
| The PWM0 waveform will start output from next full PWM0 period. | ||
| [27] | BRKLSTS3 | PWM0 Channel3 Level-detect Brake Status (Read Only) |
| 0 = PWM0 channel3 level-detect brake state is released. | ||
| 1 = When PWM0 channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel3 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware | ||
| When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
| The PWM0 waveform will start output from next full PWM0 period. | ||
| [28] | BRKLSTS4 | PWM0 Channel4 Level-detect Brake Status (Read Only) |
| 0 = PWM0 channel4 level-detect brake state is released. | ||
| 1 = When PWM0 channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel4 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware | ||
| When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
| The PWM0 waveform will start output from next full PWM0 period. | ||
| [29] | BRKLSTS5 | PWM0 Channel5 Level-detect Brake Status (Read Only) |
| 0 = PWM0 channel5 level-detect brake state is released. | ||
| 1 = When PWM0 channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel5 at brake state. | ||
| Note: This bit is read only and auto cleared by hardware | ||
| When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished | ||
| The PWM0 waveform will start output from next full PWM0 period. |
| PDMA_CH_T::INTSTSn |
[0x0024] PDMA channel n Interrupt Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TABTIF | PDMA Read/Write Target Abort Interrupt Status Flag |
| 0 = No bus ERROR response received. | ||
| 1 = Bus ERROR response received. | ||
| Note1: This bit is cleared by writing 1 to it. | ||
| Note2: This bit indicates bus master received error response or not, if bus master received error response, it means that target abort is happened | ||
| PDMA controller will stop transfer and respond this event to user then go to IDLE state | ||
| When target abort occurred, user must reset PDMA controller, and then transfer those data again. | ||
| [1] | TDIF | Transfer Done Interrupt Status Flag |
| This bit indicates that PDMA has finished all transfer. | ||
| 0 = Not finished yet. | ||
| 1 = Done. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [6] | TOUTIF | Time-out Interrupt Status Flag |
| This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC. | ||
| 0 = No time-out flag. | ||
| 1 = Time-out flag. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [8] | PCNTIF | Periodic Count Interrupt Status Flag |
| This flag indicates PCNTITH (PDMA_CNTn[30:16], n=1~4) data has been transferred. | ||
| Note: This bit is cleared by writing 1 to it. |
| GPIO_T::INTTYPE |
[0x0018] Pn Interrupt Trigger Type Control
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TYPE0 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [1] | TYPE1 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [2] | TYPE2 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [3] | TYPE3 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [4] | TYPE4 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [5] | TYPE5 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [6] | TYPE6 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [7] | TYPE7 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [8] | TYPE8 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [9] | TYPE9 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [10] | TYPE10 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [11] | TYPE11 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [12] | TYPE12 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [13] | TYPE13 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [14] | TYPE14 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [15] | TYPE15 | Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
| SYS_T::IPRST1 |
[0x0008] Peripheral Reset Control Resister1
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CHIPRST | Chip One-shot Reset (Write Protect) |
| Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. | ||
| The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. | ||
| About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 | ||
| 0 = Chip normal operation. | ||
| 1 = Chip one-shot reset. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [1] | CPURST | Processor Core One-shot Reset (Write Protect) |
| Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. | ||
| 0 = Processor core normal operation. | ||
| 1 = Processor core one-shot reset. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [2] | PDMARST | PDMA Controller Reset (Write Protect) |
| Setting this bit to 1 will generate a reset signal to the PDMA | ||
| User needs to set this bit to 0 to release from reset state. | ||
| 0 = PDMA controller normal operation. | ||
| 1 = PDMA controller reset. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
| SYS_T::IPRST2 |
[0x000c] Peripheral Reset Control Resister2
| Bits | Field | Descriptions |
|---|---|---|
| [1] | GPIORST | GPIO Controller Reset |
| 0 = GPIO module normal operation. | ||
| 1 = GPIO module reset. | ||
| [2] | TMR0RST | Timer0 Controller Reset |
| 0 = Timer0 module normal operation. | ||
| 1 = Timer0 module reset. | ||
| [3] | TMR1RST | Timer1 Controller Reset |
| 0 = Timer1 module normal operation. | ||
| 1 = Timer1 module reset. | ||
| [4] | TMR2RST | Timer2 Controller Reset |
| 0 = Timer2 module normal operation. | ||
| 1 = Timer2 module reset. | ||
| [5] | TMR3RST | Timer3 Controller Reset |
| 0 = Timer3 module normal operation. | ||
| 1 = Timer3 module reset. | ||
| [8] | I2C0RST | I2C0 Controller Reset |
| 0 = I2C0 module normal operation. | ||
| 1 = I2C0 module reset. | ||
| [9] | I2C1RST | I2C1 Controller Reset |
| 0 = I2C1 module normal operation. | ||
| 1 = I2C1 module reset. | ||
| [12] | SPI0RST | SPI0 Controller Reset |
| 0 = SPI0 module normal operation. | ||
| 1 = SPI0 module reset. | ||
| [13] | SPI1RST | SPI1 Controller Reset |
| 0 = SPI1 module normal operation. | ||
| 1 = SPI1 module reset. | ||
| [14] | SPI2RST | SPI2 Controller Reset |
| 0 = SPI2 module normal operation. | ||
| 1 = SPI2 module reset. | ||
| [15] | SPI3RST | SPI3 Controller Reset |
| 0 = SPI3 module normal operation. | ||
| 1 = SPI3 module reset. | ||
| [16] | UART0RST | UART0 Controller Reset |
| 0 = UART0 module normal operation. | ||
| 1 = UART0 module reset. | ||
| [17] | UART1RST | UART1 Controller Reset |
| 0 = UART1 module normal operation. | ||
| 1 = UART1 module reset. | ||
| [20] | PWM0RST | PWM0 Controller Reset |
| 0 = PWM0 module normal operation. | ||
| 1 = PWM0 module reset. | ||
| [22] | ACMP01RST | Comparator Controller Reset |
| 0 = Comparator module normal operation. | ||
| 1 = Comparator module reset. | ||
| [28] | ADCRST | ADC Controller Reset |
| 0 = ADC module normal operation. | ||
| 1 = ADC module reset. | ||
| [30] | SC0RST | SmartCard 0 Controller Reset |
| 0 = SmartCard module normal operation. | ||
| 1 = SmartCard module reset. | ||
| [31] | SC1RST | SmartCard1 Controller Reset |
| 0 = SmartCard module normal operation. | ||
| 1 = SmartCard module reset. |
| SYS_T::IRC0TCTL |
[0x0080] HIRC0 Trim Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | FREQSEL | Trim Frequency Selection |
| This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC0) auto trim. | ||
| During auto trim operation, if clock error detected with CESTOPEN (SYS_IRC0TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 000 automatically. | ||
| 000 = Disable HIRC0 auto trim function. | ||
| 001 = Enable HIRC0 auto trim function and trim HIRC to 11.0592 MHz. | ||
| 010 = Enable HIRC0 auto trim function and trim HIRC to 12 MHz. | ||
| 011 = Enable HIRC0 auto trim function and trim HIRC to 12.288 MHz. | ||
| 100 = Enable HIRC0 auto trim function and trim HIRC to 16 MHz. | ||
| Note: HIRC0 auto trim cannot work normally at power down mode | ||
| These bits must be cleared before entering power down mode. | ||
| [5:4] | LOOPSEL | Trim Calculation Loop Selection |
| This field defines that trim value calculation is based on how many 32.768 kHz clock. | ||
| 00 = Trim value calculation is based on average difference in 4 32.768 kHz clock. | ||
| 01 = Trim value calculation is based on average difference in 8 32.768 kHz clock. | ||
| 10 = Trim value calculation is based on average difference in 16 32.768 kHz clock. | ||
| 11 = Trim value calculation is based on average difference in 32 32.768 kHz clock. | ||
| Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. | ||
| [7:6] | RETRYCNT | Trim Value Update Limitation Count |
| This field defines that how many times the auto trim circuit will try to update the HIRC0 trim value before the frequency of HIRC0 locked. | ||
| Once the HIRC0 locked, the internal trim value update counter will be reset. | ||
| If the trim value update counter reached this limitation value and frequency of HIRC0 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00. | ||
| 00 = Trim retry count limitation is 64 loops. | ||
| 01 = Trim retry count limitation is 128 loops. | ||
| 10 = Trim retry count limitation is 256 loops. | ||
| 11 = Trim retry count limitation is 512 loops. | ||
| [8] | CESTOPEN | Clock Error Stop Enable Bit |
| This bit is used to control if stop the HIRC0 trim operation when 32.768 kHz clock error is detected. | ||
| If set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation was stopped | ||
| If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation is continuously. | ||
| 0 = The trim operation is keep going if clock is inaccuracy. | ||
| 1 = The trim operation is stopped if clock is inaccuracy. |
| SYS_T::IRC0TIEN |
[0x0084] HIRC0 Trim Interrupt Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [1] | TFAILIEN | Trim Failure Interrupt Enable Bit |
| This bit controls if an interrupt will be triggered while HIRC0 trim value update limitation count reached and HIRC0 frequency still not locked on target frequency set by FREQSEL (SYS_IRC0TCTL[1:0]). | ||
| If this bit is high and TFAILIF (SYS_IRC0TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached. | ||
| 0 = Disable TFAILIF (SYS_IRC0TSTS[1]) status to trigger an interrupt to CPU. | ||
| 1 = Enable TFAILIF (SYS_IRC0TSTS[1]) status to trigger an interrupt to CPU. | ||
| [2] | CLKEIEN | Clock Error Interrupt Enable Bit |
| This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. | ||
| If this bit is set to1, and CLKERRIF (SYS_IRC0TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. | ||
| 0 = Disable CLKERRIF (SYS_IRC0TSTS[2]) status to trigger an interrupt to CPU. | ||
| 1 = Enable CLKERRIF (SYS_IRC0TSTS[2]) status to trigger an interrupt to CPU. |
| SYS_T::IRC0TISTS |
[0x0088] HIRC0 Trim Interrupt Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FREQLOCK | HIRC0 Frequency Lock Status |
| This bit indicates the HIRC0 frequency is locked. | ||
| This is a status bit and doesn't trigger any interrupt. | ||
| 0 = The internal high-speed oscillator frequency doesn't lock at frequency set by FREQSEL (SYS_IRC0TCTL[2:0]). | ||
| 1 = The internal high-speed oscillator frequency locked at frequency set by FREQSEL (SYS_IRC0TCTL[2:0]). | ||
| [1] | TFAILIF | Trim Failure Interrupt Status |
| This bit indicates that HIRC0 trim value update limitation count reached and the HIRC0 clock frequency still doesn't be locked | ||
| Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically. | ||
| If this bit is set and TFAILIEN (SYS_IRC0TIEN[1]) is high, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached | ||
| Write 1 to clear this to 0. | ||
| 0 = Trim value update limitation count does not reach. | ||
| 1 = Trim value update limitation count reached and HIRC frequency still not locked. | ||
| [2] | CLKERRIF | Clock Error Interrupt Status |
| When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal high speed RC oscillator (HIRC0) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy | ||
| Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_IRC0TCTL[8]) is set to 1. | ||
| If this bit is set and CLKEIEN (SYS_IRC0TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy | ||
| Write 1 to clear this to 0. | ||
| 0 = Clock frequency is accuracy. | ||
| 1 = Clock frequency is inaccuracy. |
| SYS_T::IRC1TCTL |
[0x0090] HIRC1 Trim Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | FREQSEL | Trim Frequency Selection |
| This field indicates the target frequency of 36 MHz internal high speed RC oscillator (HIRC1) auto trim. | ||
| During auto trim operation, if clock error detected with CESTOPEN (SYS_IRC1TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. | ||
| 00 = Disable HIRC1 auto trim function. | ||
| 01 = Reserved | ||
| 10 = Enable HIRC1 auto trim function and trim HIRC to 36 MHz. | ||
| 11 = Reserved. | ||
| Note: HIRC1 auto trim cannot work normally at power down mode | ||
| These bits must be cleared before entering power down mode. | ||
| [5:4] | LOOPSEL | Trim Calculation Loop Selection |
| This field defines that trim value calculation is based on how many 32.768 kHz clock. | ||
| 00 = Trim value calculation is based on average difference in 4 32.768 kHz clock. | ||
| 01 = Trim value calculation is based on average difference in 8 32.768 kHz clock. | ||
| 10 = Trim value calculation is based on average difference in 16 32.768 kHz clock. | ||
| 11 = Trim value calculation is based on average difference in 32 32.768 kHz clock. | ||
| Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. | ||
| [7:6] | RETRYCNT | Trim Value Update Limitation Count |
| This field defines that how many times the auto trim circuit will try to update the HIRC1 trim value before the frequency of HIRC1 locked. | ||
| Once the HIRC1 locked, the internal trim value update counter will be reset. | ||
| If the trim value update counter reached this limitation value and frequency of HIRC1 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00. | ||
| 00 = Trim retry count limitation is 64 loops. | ||
| 01 = Trim retry count limitation is 128 loops. | ||
| 10 = Trim retry count limitation is 256 loops. | ||
| 11 = Trim retry count limitation is 512 loops. | ||
| [8] | CESTOPEN | Clock Error Stop Enable Bit |
| This bit is used to control if stop the HIRC1 trim operation when 32.768 kHz clock error is detected. | ||
| If set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation was stopped | ||
| If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation is continuously. | ||
| 0 = The trim operation is keep going if clock is inaccuracy. | ||
| 1 = The trim operation is stopped if clock is inaccuracy. |
| SYS_T::IRC1TIEN |
[0x0094] HIRC1 Trim Interrupt Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [1] | TFAILIEN | Trim Failure Interrupt Enable Bit |
| This bit controls if an interrupt will be triggered while HIRC1 trim value update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL (SYS_IRC1TCTL[1:0]). | ||
| If this bit is high and TFAILIF (SYS_IRC1TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached. | ||
| 0 = Disable TFAILIF (SYS_IRC1TSTS[1]) status to trigger an interrupt to CPU. | ||
| 1 = Enable TFAILIF (SYS_IRC1TSTS[1]) status to trigger an interrupt to CPU. | ||
| [2] | CLKEIEN | Clock Error Interrupt Enable Bit |
| This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. | ||
| If this bit is set to1, and CLKERRIF (SYS_IRC1TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. | ||
| 0 = Disable CLKERRIF (SYS_IRC1TSTS[2]) status to trigger an interrupt to CPU. | ||
| 1 = Enable CLKERRIF (SYS_IRC1TSTS[2]) status to trigger an interrupt to CPU. |
| SYS_T::IRC1TISTS |
[0x0098] HIRC1 Trim Interrupt Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FREQLOCK | HIRC1 Frequency Lock Status |
| This bit indicates the HIRC1 frequency is locked. | ||
| This is a status bit and doesn't trigger any interrupt. | ||
| 0 = The internal high-speed oscillator frequency doesn't lock at 36 MHz yet. | ||
| 1 = The internal high-speed oscillator frequency locked at 36 MHz. | ||
| [1] | TFAILIF | Trim Failure Interrupt Status |
| This bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn't be locked | ||
| Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically. | ||
| If this bit is set and TFAILIEN (SYS_IRC1TIEN[1]) is high, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached | ||
| Write 1 to clear this to 0. | ||
| 0 = Trim value update limitation count does not reach. | ||
| 1 = Trim value update limitation count reached and HIRC1 frequency still not locked. | ||
| [2] | CLKERRIF | Clock Error Interrupt Status |
| When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 36 MHz internal high speed RC oscillator (HIRC1) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy | ||
| Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_IRC1TCTL[8]) is set to 1. | ||
| If this bit is set and CLKEIEN (SYS_IRC1TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy | ||
| Write 1 to clear this to 0. | ||
| 0 = Clock frequency is accuracy. | ||
| 1 = Clock frequency is inaccuracy. |
| UART_T::IRDA |
[0x0030] UART IrDA Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [1] | TXEN | IrDA Receiver/Transmitter Selection Enable Bit |
| 0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) | ||
| 1 = IrDA Transmitter Enabled and Receiver Disabled. | ||
| [5] | TXINV | IrDA Inverse Transmitting Output Signal |
| 0 = None inverse transmitting signal. (Default) | ||
| 1 = Inverse transmitting output signal. | ||
| [6] | RXINV | IrDA Inverse Receive Input Signal |
| 0 = None inverse receiving input signal. | ||
| 1 = Inverse receiving input signal. (Default) |
| INT_T::IRQ0_SRC |
| INT_T::IRQ10_SRC |
| INT_T::IRQ11_SRC |
| INT_T::IRQ12_SRC |
| INT_T::IRQ13_SRC |
| INT_T::IRQ14_SRC |
| INT_T::IRQ15_SRC |
| INT_T::IRQ16_SRC |
| INT_T::IRQ17_SRC |
| INT_T::IRQ18_SRC |
| INT_T::IRQ19_SRC |
| INT_T::IRQ1_SRC |
| INT_T::IRQ20_SRC |
| INT_T::IRQ21_SRC |
| INT_T::IRQ22_SRC |
| INT_T::IRQ23_SRC |
| INT_T::IRQ24_SRC |
| INT_T::IRQ25_SRC |
| INT_T::IRQ26_SRC |
| INT_T::IRQ27_SRC |
| INT_T::IRQ28_SRC |
| INT_T::IRQ29_SRC |
| INT_T::IRQ2_SRC |
| INT_T::IRQ30_SRC |
| INT_T::IRQ31_SRC |
| INT_T::IRQ3_SRC |
| INT_T::IRQ4_SRC |
| INT_T::IRQ5_SRC |
| INT_T::IRQ6_SRC |
| INT_T::IRQ7_SRC |
| INT_T::IRQ8_SRC |
| INT_T::IRQ9_SRC |
| FMC_T::ISPADDR |
[0x0004] ISP Address Register
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | ISPADDR | ISP Address |
| The Nano103 series is equipped with embedded flash | ||
| ISPADDR [1:0] must be kept 00 for ISP 32-bit operation. | ||
| For both CRC-32 Checksum Calculation and Flash All-One Verification commands, this field is the flash starting address for checksum calculation and 512 bytes address alignment is necessary. |
| FMC_T::ISPCMD |
[0x000c] ISP CMD Register
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CMD | ISP CMD |
| ISP command table is shown below: | ||
| 0x00 = FLASH 32-bit Read. | ||
| 0x04 = Read Unique ID. | ||
| 0x08 = Read All-One Verification Result. | ||
| 0x0B = Read Company ID. | ||
| 0x0C = Read Device ID. | ||
| 0x0D = Read CRC-32 Checksum. | ||
| 0x21 = FLASH 32-bit Program. | ||
| 0x22 = FLASH Page Erase. | ||
| 0x26 = FLASH Mass Erase. | ||
| 0x28 = Run All-One Verification. | ||
| 0x2D = Run CRC-32 Checksum Calculation. | ||
| 0x2E = Vector Remap. | ||
| The other commands are invalid. |
| FMC_T::ISPCTL |
[0x0000] ISP Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPEN | ISP Enable Bit (Write Protect) |
| ISP function enable bit. Set this bit to enable ISP function. | ||
| 0 = ISP function Disabled. | ||
| 1 = ISP function Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [1] | BS | Boot Select (Write Protect) |
| Set/clear this bit to select next booting from LDROM/APROM, respectively | ||
| This bit also functions as chip booting status flag, which can be used to check where chip booted from. | ||
| This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. | ||
| 0 = Booting from APROM. | ||
| 1 = Booting from LDROM. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [3] | APUEN | APROM Update Enable Bit (Write Protect) |
| 0 = APROM cannot be updated when the chip runs in APROM booting without IAP mode. | ||
| 1 = APROM can be updated when the chip runs in APROM booting without IAP mode | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [4] | CFGUEN | CONFIG Update Enable Bit (Write Protect) |
| 0 = CONFIG cannot be updated. | ||
| 1 = CONFIG can be updated. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [5] | LDUEN | LDROM Update Enable Bit (Write Protect) |
| LDROM update enable bit. | ||
| 0 = LDROM cannot be updated. | ||
| 1 = LDROM can be updated. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| In LDROM booting without IAP mode, LDROM cannot be updated even if LDUEN=1. | ||
| [6] | ISPFF | ISP Fail Flag (Write Protect) |
| This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
| This bit needs to be cleared by writing 1 to it. | ||
| (1) APROM writes to itself if APUEN is set to 0. | ||
| (2) LDROM writes to itself if LDUEN is set to 0. | ||
| (3) CONFIG is erased/programmed if CFGUEN is set to 0. | ||
| (6) Page Erase command at LOCK mode with ICE connection | ||
| (7) Erase or Program command at brown-out detected | ||
| (8) Destination address is illegal, such as over an available range. | ||
| (9) Invalid ISP commands | ||
| (10) KPROM is erased/programmed if KEYLOCK is set to 1 | ||
| (11) APROM(not include Data Flash) is erased/programmed if KEYLOCK is set to 1 | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
| FMC_T::ISPDAT |
[0x0008] ISP Data Register
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | ISPDAT | ISP Data |
| Write data to this register before ISP program operation. | ||
| Read data from this register after ISP read operation. | ||
| For Run CRC-32 Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment | ||
| For ISP Read CRC-32 Checksum command, ISPDAT is the checksum result | ||
| If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect. |
| FMC_T::ISPSTS |
[0x0040] ISP Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPBUSY | ISP Busy Flag (Read Only) |
| Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. | ||
| This bit is the mirror of ISPGO(FMC_ISPTRG[0]). | ||
| 0 = ISP operation is finished. | ||
| 1 = ISP is progressed. | ||
| [2:1] | CBS | Boot Selection of CONFIG (Read Only) |
| This bit is initiated with the CBS (CONFIG0 [7:6]) after any reset is happened except CPU reset (CPURF(SYS_RSTSTS[7]) is 1) or system reset (SYSRF(SYS_RSTSTS[5]) is happened. | ||
| 00 = LDROM with IAP mode. | ||
| 01 = LDROM without IAP mode. | ||
| 10 = APROM with IAP mode. | ||
| 11 = APROM without IAP mode. | ||
| [5] | PGFF | Flash Program with Fast Verification Flag(Read Only) |
| This bit is set if data is mismatched at ISP programming verification | ||
| This bit is clear by performing ISP flash erase or ISP read CID operation | ||
| 0 = Flash Program is success. | ||
| 1 = Flash Program is fail. Program data is different with data in the flash memory. | ||
| [6] | ISPFF | ISP Fail Flag (Write Protect) |
| This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] | ||
| This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
| (1) APROM writes to itself if APUEN is set to 0. | ||
| (2) LDROM writes to itself if LDUEN is set to 0. | ||
| (3) CONFIG is erased/programmed if CFGUEN is set to 0. | ||
| (4) Page Erase command at LOCK mode with ICE connection | ||
| (5) Erase or Program command at brown-out detected | ||
| (6) Destination address is illegal, such as over an available range. | ||
| (7) Invalid ISP commands | ||
| (8) KPROM is erased/programmed if KEYLOCK is set to 1 | ||
| (9) APROM(not include Data Flash) is erased/programmed if KEYLOCK is set to 1 | ||
| Note: This bit is write-protected. Refer to the SYS_REGLCTL register. | ||
| [7] | ALLONE | Flash All-one Verification Flag |
| This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1. | ||
| 0 = All of flash bits are 1 after "Run Flash All-One Verification" complete. | ||
| 1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete. | ||
| [29:9] | VECMAP | Vector Page Mapping Address (Read Only) |
| All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF} | ||
| VECMAP [20:19] = 00 system vector address is mapped to flash memory. | ||
| VECMAP [20:19] = 10 system vector address is mapped to SRAM memory. | ||
| VECMAP [18:12] should be 0. |
| FMC_T::ISPTRG |
[0x0010] ISP Trigger Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPGO | ISP Start Trigger (Write Protect) |
| Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. | ||
| 0 = ISP operation is finished. | ||
| 1 = ISP is progressed. | ||
| Note:This bit is write protected. Refer to the SYS_REGLCTL register. |
| SYS_T::IVREFCTL |
[0x006c] Internal Voltage Reference Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BGPEN | Band-gap Enable Control (Write Protect) |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Band-gap is the reference voltage of internal reference voltage | ||
| User must enable band-gap if want to enable internal 1.5, 1.8V or 2.5V reference voltage. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [1] | REGEN | Regulator Enable Control (Write Protect) |
| Enable internal 1.5, 1.8V or 2.5V reference voltage. | ||
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [3:2] | SEL25 | Regulator Output Voltage Selection (Write Protect) |
| Select internal reference voltage level. | ||
| 00 = 1.5V. | ||
| 01 = 1.8V. | ||
| 10 = 2.5V. | ||
| 11 = 2.5V. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [4] | EXTMODE | Regulator External Mode (Write Protect) |
| Users can output regulator output voltage in VREF pin if EXT_MODE is high. | ||
| 0 = No connection with external VREF pin. | ||
| 1 = Connect to external VREF pin | ||
| Connect a 1uF to 10uF capacitor to AVSS will let internal voltage reference be more stable. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [11:8] | VREFTRIM | Internal Voltage Reference Trim (Write Protect) |
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
| FMC_T::KECNT |
[0x0064] KEY-Unmatched Counting Register
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | KECNT | Error Key Entry Counter at Each Power-on (Read Only) |
| KECNT is increased when entry keys is wrong in Security Key protection. | ||
| KECNT is cleared to 0 if key comparison is matched or system power-on. | ||
| [13:8] | KEMAX | Maximum Number for Error Key Entry at Each Power-on (Read Only). |
| KEMAX is the maximum error key entry number at each power-on. | ||
| When KEMAXROM of KPROM is erased or programmed, KEMAX will also be updated. | ||
| KEMAX is used to limit KECNT(FMC_KECNT[5:0]) maximum counting. | ||
| The FORBID (FMC_KEYSTS [3]) will be set to 1 when KECNT is more than KEMAX. |
| FMC_T::KEY0 |
| FMC_T::KEY1 |
| FMC_T::KEY2 |
| FMC_T::KEYSTS |
[0x0060] KEY Comparison Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | KEYBUSY | KEY Comparison Busy (Read Only) |
| 0 = KEY comparison is finished. | ||