Place & Route TRACE Report
Loading design for application trce from file fpgasdr_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-7000HE
Package: TQFP144
Performance: 4
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) <IP_ADDRESS>6
Mon Apr 06 13:42:51 2020
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o FPGASDR_impl1.twr -gui -msgset C:/Users/user/lattice/1BitADCFPGASDR/promote.xml FPGASDR_impl1.ncd FPGASDR_impl1.prf
Design file: fpgasdr_impl1.ncd
Preference file: fpgasdr_impl1.prf
Device,speed: LCMXO2-7000HE,4
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "osc_clk" 88.670000 MHz (4096 errors)
4096 items scored, 4096 timing errors detected.
Warning: 69.459MHz is the maximum frequency for this preference.
CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET "osc_clk" (0 errors) 18 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
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================================================================================
Preference: FREQUENCY NET "osc_clk" 88.670000 MHz ;
4096 items scored, 4096 timing errors detected.
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Error: The following path exceeds requirements by 3.119ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i63 (to osc_clk +)
Delay: 14.269ns (60.5% logic, 39.5% route), 35 logic levels.
Constraint Details:
14.269ns physical path delay SLICE_2431 to SLICE_55 exceeds
11.278ns delay constraint less
-0.038ns skew and
0.166ns DIN_SET requirement (totaling 11.150ns) by 3.119ns
Physical Path Details:
Data path SLICE_2431 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R22C2D.CLK to R22C2D.Q0 SLICE_2431 (from osc_clk)
ROUTE 4 1.101 R22C2D.Q0 to R21C2A.B0 o_Rx_DV
CTOF_DEL --- 0.495 R21C2A.B0 to R21C2A.F0 SLICE_2475
ROUTE 4 0.790 R21C2A.F0 to R21C4C.C0 n8257
CTOF_DEL --- 0.495 R21C4C.C0 to R21C4C.F0 SLICE_2449
ROUTE 5 0.648 R21C4C.F0 to R21C5B.D1 n12533
CTOF_DEL --- 0.495 R21C5B.D1 to R21C5B.F1 SLICE_2387
ROUTE 49 1.051 R21C5B.F1 to R22C5A.A0 n2563
CTOF_DEL --- 0.495 R22C5A.A0 to R22C5A.F0 SLICE_2411
ROUTE 1 2.045 R22C5A.F0 to R18C2D.C0 n2358
C0TOFCO_DE --- 1.023 R18C2D.C0 to R18C2D.FCO SLICE_84
ROUTE 1 0.000 R18C2D.FCO to R18C3A.FCI n10981
FCITOFCO_D --- 0.162 R18C3A.FCI to R18C3A.FCO SLICE_83
ROUTE 1 0.000 R18C3A.FCO to R18C3B.FCI n10982
FCITOFCO_D --- 0.162 R18C3B.FCI to R18C3B.FCO SLICE_82
ROUTE 1 0.000 R18C3B.FCO to R18C3C.FCI n10983
FCITOFCO_D --- 0.162 R18C3C.FCI to R18C3C.FCO SLICE_81
ROUTE 1 0.000 R18C3C.FCO to R18C3D.FCI n10984
FCITOFCO_D --- 0.162 R18C3D.FCI to R18C3D.FCO SLICE_80
ROUTE 1 0.000 R18C3D.FCO to R18C4A.FCI n10985
FCITOFCO_D --- 0.162 R18C4A.FCI to R18C4A.FCO SLICE_79
ROUTE 1 0.000 R18C4A.FCO to R18C4B.FCI n10986
FCITOFCO_D --- 0.162 R18C4B.FCI to R18C4B.FCO SLICE_78
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10987
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_77
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10988
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_76
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10989
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_75
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10990
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_74
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10991
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_73
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10992
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_72
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10993
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_71
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10994
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_70
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10995
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_69
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10996
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_68
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10997
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_67
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10998
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_66
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10999
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_65
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n11000
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_64
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n11001
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_63
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n11002
FCITOFCO_D --- 0.162 R18C8B.FCI to R18C8B.FCO SLICE_62
ROUTE 1 0.000 R18C8B.FCO to R18C8C.FCI n11003
FCITOFCO_D --- 0.162 R18C8C.FCI to R18C8C.FCO SLICE_61
ROUTE 1 0.000 R18C8C.FCO to R18C8D.FCI n11004
FCITOFCO_D --- 0.162 R18C8D.FCI to R18C8D.FCO SLICE_60
ROUTE 1 0.000 R18C8D.FCO to R18C9A.FCI n11005
FCITOFCO_D --- 0.162 R18C9A.FCI to R18C9A.FCO SLICE_59
ROUTE 1 0.000 R18C9A.FCO to R18C9B.FCI n11006
FCITOFCO_D --- 0.162 R18C9B.FCI to R18C9B.FCO SLICE_58
ROUTE 1 0.000 R18C9B.FCO to R18C9C.FCI n11007
FCITOFCO_D --- 0.162 R18C9C.FCI to R18C9C.FCO SLICE_57
ROUTE 1 0.000 R18C9C.FCO to R18C9D.FCI n11008
FCITOFCO_D --- 0.162 R18C9D.FCI to R18C9D.FCO SLICE_56
ROUTE 1 0.000 R18C9D.FCO to R18C10A.FCI n11009
FCITOF1_DE --- 0.643 R18C10A.FCI to R18C10A.F1 SLICE_55
ROUTE 1 0.000 R18C10A.F1 to R18C10A.DI1 n2817 (to osc_clk)
--------
14.269 (60.5% logic, 39.5% route), 35 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2431:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.161 OSC.OSC to R22C2D.CLK osc_clk
--------
4.161 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R18C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.083ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_Byte_i5 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i63 (to osc_clk +)
Delay: 14.233ns (60.7% logic, 39.3% route), 35 logic levels.
Constraint Details:
14.233ns physical path delay SLICE_2289 to SLICE_55 exceeds
11.278ns delay constraint less
-0.038ns skew and
0.166ns DIN_SET requirement (totaling 11.150ns) by 3.083ns
Physical Path Details:
Data path SLICE_2289 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R22C2C.CLK to R22C2C.Q0 SLICE_2289 (from osc_clk)
ROUTE 4 1.065 R22C2C.Q0 to R21C2A.A0 o_Rx_Byte_5
CTOF_DEL --- 0.495 R21C2A.A0 to R21C2A.F0 SLICE_2475
ROUTE 4 0.790 R21C2A.F0 to R21C4C.C0 n8257
CTOF_DEL --- 0.495 R21C4C.C0 to R21C4C.F0 SLICE_2449
ROUTE 5 0.648 R21C4C.F0 to R21C5B.D1 n12533
CTOF_DEL --- 0.495 R21C5B.D1 to R21C5B.F1 SLICE_2387
ROUTE 49 1.051 R21C5B.F1 to R22C5A.A0 n2563
CTOF_DEL --- 0.495 R22C5A.A0 to R22C5A.F0 SLICE_2411
ROUTE 1 2.045 R22C5A.F0 to R18C2D.C0 n2358
C0TOFCO_DE --- 1.023 R18C2D.C0 to R18C2D.FCO SLICE_84
ROUTE 1 0.000 R18C2D.FCO to R18C3A.FCI n10981
FCITOFCO_D --- 0.162 R18C3A.FCI to R18C3A.FCO SLICE_83
ROUTE 1 0.000 R18C3A.FCO to R18C3B.FCI n10982
FCITOFCO_D --- 0.162 R18C3B.FCI to R18C3B.FCO SLICE_82
ROUTE 1 0.000 R18C3B.FCO to R18C3C.FCI n10983
FCITOFCO_D --- 0.162 R18C3C.FCI to R18C3C.FCO SLICE_81
ROUTE 1 0.000 R18C3C.FCO to R18C3D.FCI n10984
FCITOFCO_D --- 0.162 R18C3D.FCI to R18C3D.FCO SLICE_80
ROUTE 1 0.000 R18C3D.FCO to R18C4A.FCI n10985
FCITOFCO_D --- 0.162 R18C4A.FCI to R18C4A.FCO SLICE_79
ROUTE 1 0.000 R18C4A.FCO to R18C4B.FCI n10986
FCITOFCO_D --- 0.162 R18C4B.FCI to R18C4B.FCO SLICE_78
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10987
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_77
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10988
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_76
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10989
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_75
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10990
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_74
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10991
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_73
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10992
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_72
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10993
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_71
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10994
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_70
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10995
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_69
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10996
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_68
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10997
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_67
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10998
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_66
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10999
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_65
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n11000
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_64
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n11001
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_63
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n11002
FCITOFCO_D --- 0.162 R18C8B.FCI to R18C8B.FCO SLICE_62
ROUTE 1 0.000 R18C8B.FCO to R18C8C.FCI n11003
FCITOFCO_D --- 0.162 R18C8C.FCI to R18C8C.FCO SLICE_61
ROUTE 1 0.000 R18C8C.FCO to R18C8D.FCI n11004
FCITOFCO_D --- 0.162 R18C8D.FCI to R18C8D.FCO SLICE_60
ROUTE 1 0.000 R18C8D.FCO to R18C9A.FCI n11005
FCITOFCO_D --- 0.162 R18C9A.FCI to R18C9A.FCO SLICE_59
ROUTE 1 0.000 R18C9A.FCO to R18C9B.FCI n11006
FCITOFCO_D --- 0.162 R18C9B.FCI to R18C9B.FCO SLICE_58
ROUTE 1 0.000 R18C9B.FCO to R18C9C.FCI n11007
FCITOFCO_D --- 0.162 R18C9C.FCI to R18C9C.FCO SLICE_57
ROUTE 1 0.000 R18C9C.FCO to R18C9D.FCI n11008
FCITOFCO_D --- 0.162 R18C9D.FCI to R18C9D.FCO SLICE_56
ROUTE 1 0.000 R18C9D.FCO to R18C10A.FCI n11009
FCITOF1_DE --- 0.643 R18C10A.FCI to R18C10A.F1 SLICE_55
ROUTE 1 0.000 R18C10A.F1 to R18C10A.DI1 n2817 (to osc_clk)
--------
14.233 (60.7% logic, 39.3% route), 35 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2289:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.161 OSC.OSC to R22C2C.CLK osc_clk
--------
4.161 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R18C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.061ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i62 (to osc_clk +)
Delay: 14.211ns (60.3% logic, 39.7% route), 35 logic levels.
Constraint Details:
14.211ns physical path delay SLICE_2431 to SLICE_55 exceeds
11.278ns delay constraint less
-0.038ns skew and
0.166ns DIN_SET requirement (totaling 11.150ns) by 3.061ns
Physical Path Details:
Data path SLICE_2431 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R22C2D.CLK to R22C2D.Q0 SLICE_2431 (from osc_clk)
ROUTE 4 1.101 R22C2D.Q0 to R21C2A.B0 o_Rx_DV
CTOF_DEL --- 0.495 R21C2A.B0 to R21C2A.F0 SLICE_2475
ROUTE 4 0.790 R21C2A.F0 to R21C4C.C0 n8257
CTOF_DEL --- 0.495 R21C4C.C0 to R21C4C.F0 SLICE_2449
ROUTE 5 0.648 R21C4C.F0 to R21C5B.D1 n12533
CTOF_DEL --- 0.495 R21C5B.D1 to R21C5B.F1 SLICE_2387
ROUTE 49 1.051 R21C5B.F1 to R22C5A.A0 n2563
CTOF_DEL --- 0.495 R22C5A.A0 to R22C5A.F0 SLICE_2411
ROUTE 1 2.045 R22C5A.F0 to R18C2D.C0 n2358
C0TOFCO_DE --- 1.023 R18C2D.C0 to R18C2D.FCO SLICE_84
ROUTE 1 0.000 R18C2D.FCO to R18C3A.FCI n10981
FCITOFCO_D --- 0.162 R18C3A.FCI to R18C3A.FCO SLICE_83
ROUTE 1 0.000 R18C3A.FCO to R18C3B.FCI n10982
FCITOFCO_D --- 0.162 R18C3B.FCI to R18C3B.FCO SLICE_82
ROUTE 1 0.000 R18C3B.FCO to R18C3C.FCI n10983
FCITOFCO_D --- 0.162 R18C3C.FCI to R18C3C.FCO SLICE_81
ROUTE 1 0.000 R18C3C.FCO to R18C3D.FCI n10984
FCITOFCO_D --- 0.162 R18C3D.FCI to R18C3D.FCO SLICE_80
ROUTE 1 0.000 R18C3D.FCO to R18C4A.FCI n10985
FCITOFCO_D --- 0.162 R18C4A.FCI to R18C4A.FCO SLICE_79
ROUTE 1 0.000 R18C4A.FCO to R18C4B.FCI n10986
FCITOFCO_D --- 0.162 R18C4B.FCI to R18C4B.FCO SLICE_78
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10987
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_77
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10988
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_76
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10989
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_75
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10990
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_74
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10991
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_73
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10992
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_72
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10993
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_71
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10994
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_70
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10995
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_69
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10996
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_68
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10997
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_67
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10998
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_66
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10999
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_65
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n11000
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_64
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n11001
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_63
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n11002
FCITOFCO_D --- 0.162 R18C8B.FCI to R18C8B.FCO SLICE_62
ROUTE 1 0.000 R18C8B.FCO to R18C8C.FCI n11003
FCITOFCO_D --- 0.162 R18C8C.FCI to R18C8C.FCO SLICE_61
ROUTE 1 0.000 R18C8C.FCO to R18C8D.FCI n11004
FCITOFCO_D --- 0.162 R18C8D.FCI to R18C8D.FCO SLICE_60
ROUTE 1 0.000 R18C8D.FCO to R18C9A.FCI n11005
FCITOFCO_D --- 0.162 R18C9A.FCI to R18C9A.FCO SLICE_59
ROUTE 1 0.000 R18C9A.FCO to R18C9B.FCI n11006
FCITOFCO_D --- 0.162 R18C9B.FCI to R18C9B.FCO SLICE_58
ROUTE 1 0.000 R18C9B.FCO to R18C9C.FCI n11007
FCITOFCO_D --- 0.162 R18C9C.FCI to R18C9C.FCO SLICE_57
ROUTE 1 0.000 R18C9C.FCO to R18C9D.FCI n11008
FCITOFCO_D --- 0.162 R18C9D.FCI to R18C9D.FCO SLICE_56
ROUTE 1 0.000 R18C9D.FCO to R18C10A.FCI n11009
FCITOF0_DE --- 0.585 R18C10A.FCI to R18C10A.F0 SLICE_55
ROUTE 1 0.000 R18C10A.F0 to R18C10A.DI0 n2818 (to osc_clk)
--------
14.211 (60.3% logic, 39.7% route), 35 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2431:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.161 OSC.OSC to R22C2D.CLK osc_clk
--------
4.161 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R18C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.025ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_Byte_i5 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i62 (to osc_clk +)
Delay: 14.175ns (60.5% logic, 39.5% route), 35 logic levels.
Constraint Details:
14.175ns physical path delay SLICE_2289 to SLICE_55 exceeds
11.278ns delay constraint less
-0.038ns skew and
0.166ns DIN_SET requirement (totaling 11.150ns) by 3.025ns
Physical Path Details:
Data path SLICE_2289 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R22C2C.CLK to R22C2C.Q0 SLICE_2289 (from osc_clk)
ROUTE 4 1.065 R22C2C.Q0 to R21C2A.A0 o_Rx_Byte_5
CTOF_DEL --- 0.495 R21C2A.A0 to R21C2A.F0 SLICE_2475
ROUTE 4 0.790 R21C2A.F0 to R21C4C.C0 n8257
CTOF_DEL --- 0.495 R21C4C.C0 to R21C4C.F0 SLICE_2449
ROUTE 5 0.648 R21C4C.F0 to R21C5B.D1 n12533
CTOF_DEL --- 0.495 R21C5B.D1 to R21C5B.F1 SLICE_2387
ROUTE 49 1.051 R21C5B.F1 to R22C5A.A0 n2563
CTOF_DEL --- 0.495 R22C5A.A0 to R22C5A.F0 SLICE_2411
ROUTE 1 2.045 R22C5A.F0 to R18C2D.C0 n2358
C0TOFCO_DE --- 1.023 R18C2D.C0 to R18C2D.FCO SLICE_84
ROUTE 1 0.000 R18C2D.FCO to R18C3A.FCI n10981
FCITOFCO_D --- 0.162 R18C3A.FCI to R18C3A.FCO SLICE_83
ROUTE 1 0.000 R18C3A.FCO to R18C3B.FCI n10982
FCITOFCO_D --- 0.162 R18C3B.FCI to R18C3B.FCO SLICE_82
ROUTE 1 0.000 R18C3B.FCO to R18C3C.FCI n10983
FCITOFCO_D --- 0.162 R18C3C.FCI to R18C3C.FCO SLICE_81
ROUTE 1 0.000 R18C3C.FCO to R18C3D.FCI n10984
FCITOFCO_D --- 0.162 R18C3D.FCI to R18C3D.FCO SLICE_80
ROUTE 1 0.000 R18C3D.FCO to R18C4A.FCI n10985
FCITOFCO_D --- 0.162 R18C4A.FCI to R18C4A.FCO SLICE_79
ROUTE 1 0.000 R18C4A.FCO to R18C4B.FCI n10986
FCITOFCO_D --- 0.162 R18C4B.FCI to R18C4B.FCO SLICE_78
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10987
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_77
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10988
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_76
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10989
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_75
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10990
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_74
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10991
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_73
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10992
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_72
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10993
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_71
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10994
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_70
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10995
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_69
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10996
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_68
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10997
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_67
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10998
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_66
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10999
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_65
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n11000
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_64
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n11001
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_63
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n11002
FCITOFCO_D --- 0.162 R18C8B.FCI to R18C8B.FCO SLICE_62
ROUTE 1 0.000 R18C8B.FCO to R18C8C.FCI n11003
FCITOFCO_D --- 0.162 R18C8C.FCI to R18C8C.FCO SLICE_61
ROUTE 1 0.000 R18C8C.FCO to R18C8D.FCI n11004
FCITOFCO_D --- 0.162 R18C8D.FCI to R18C8D.FCO SLICE_60
ROUTE 1 0.000 R18C8D.FCO to R18C9A.FCI n11005
FCITOFCO_D --- 0.162 R18C9A.FCI to R18C9A.FCO SLICE_59
ROUTE 1 0.000 R18C9A.FCO to R18C9B.FCI n11006
FCITOFCO_D --- 0.162 R18C9B.FCI to R18C9B.FCO SLICE_58
ROUTE 1 0.000 R18C9B.FCO to R18C9C.FCI n11007
FCITOFCO_D --- 0.162 R18C9C.FCI to R18C9C.FCO SLICE_57
ROUTE 1 0.000 R18C9C.FCO to R18C9D.FCI n11008
FCITOFCO_D --- 0.162 R18C9D.FCI to R18C9D.FCO SLICE_56
ROUTE 1 0.000 R18C9D.FCO to R18C10A.FCI n11009
FCITOF0_DE --- 0.585 R18C10A.FCI to R18C10A.F0 SLICE_55
ROUTE 1 0.000 R18C10A.F0 to R18C10A.DI0 n2818 (to osc_clk)
--------
14.175 (60.5% logic, 39.5% route), 35 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2289:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.161 OSC.OSC to R22C2C.CLK osc_clk
--------
4.161 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R18C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.019ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i63 (to osc_clk +)
Delay: 14.169ns (62.3% logic, 37.7% route), 37 logic levels.
Constraint Details:
14.169ns physical path delay SLICE_2431 to SLICE_55 exceeds
11.278ns delay constraint less
-0.038ns skew and
0.166ns DIN_SET requirement (totaling 11.150ns) by 3.019ns
Physical Path Details:
Data path SLICE_2431 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R22C2D.CLK to R22C2D.Q0 SLICE_2431 (from osc_clk)
ROUTE 4 1.101 R22C2D.Q0 to R21C2A.B0 o_Rx_DV
CTOF_DEL --- 0.495 R21C2A.B0 to R21C2A.F0 SLICE_2475
ROUTE 4 0.790 R21C2A.F0 to R21C4C.C0 n8257
CTOF_DEL --- 0.495 R21C4C.C0 to R21C4C.F0 SLICE_2449
ROUTE 5 0.769 R21C4C.F0 to R21C5C.C1 n12533
CTOF_DEL --- 0.495 R21C5C.C1 to R21C5C.F1 SLICE_2389
ROUTE 52 1.102 R21C5C.F1 to R21C3D.A0 n13056
CTOF_DEL --- 0.495 R21C3D.A0 to R21C3D.F0 SLICE_2414
ROUTE 1 1.583 R21C3D.F0 to R18C2B.C1 n2361
C1TOFCO_DE --- 0.889 R18C2B.C1 to R18C2B.FCO SLICE_86
ROUTE 1 0.000 R18C2B.FCO to R18C2C.FCI n10979
FCITOFCO_D --- 0.162 R18C2C.FCI to R18C2C.FCO SLICE_85
ROUTE 1 0.000 R18C2C.FCO to R18C2D.FCI n10980
FCITOFCO_D --- 0.162 R18C2D.FCI to R18C2D.FCO SLICE_84
ROUTE 1 0.000 R18C2D.FCO to R18C3A.FCI n10981
FCITOFCO_D --- 0.162 R18C3A.FCI to R18C3A.FCO SLICE_83
ROUTE 1 0.000 R18C3A.FCO to R18C3B.FCI n10982
FCITOFCO_D --- 0.162 R18C3B.FCI to R18C3B.FCO SLICE_82
ROUTE 1 0.000 R18C3B.FCO to R18C3C.FCI n10983
FCITOFCO_D --- 0.162 R18C3C.FCI to R18C3C.FCO SLICE_81
ROUTE 1 0.000 R18C3C.FCO to R18C3D.FCI n10984
FCITOFCO_D --- 0.162 R18C3D.FCI to R18C3D.FCO SLICE_80
ROUTE 1 0.000 R18C3D.FCO to R18C4A.FCI n10985
FCITOFCO_D --- 0.162 R18C4A.FCI to R18C4A.FCO SLICE_79
ROUTE 1 0.000 R18C4A.FCO to R18C4B.FCI n10986
FCITOFCO_D --- 0.162 R18C4B.FCI to R18C4B.FCO SLICE_78
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10987
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_77
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10988
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_76
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10989
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_75
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10990
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_74
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10991
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_73
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10992
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_72
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10993
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_71
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10994
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_70
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10995
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_69
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10996
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_68
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10997
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_67
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10998
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_66
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10999
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_65
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n11000
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_64
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n11001
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_63
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n11002
FCITOFCO_D --- 0.162 R18C8B.FCI to R18C8B.FCO SLICE_62
ROUTE 1 0.000 R18C8B.FCO to R18C8C.FCI n11003
FCITOFCO_D --- 0.162 R18C8C.FCI to R18C8C.FCO SLICE_61
ROUTE 1 0.000 R18C8C.FCO to R18C8D.FCI n11004
FCITOFCO_D --- 0.162 R18C8D.FCI to R18C8D.FCO SLICE_60
ROUTE 1 0.000 R18C8D.FCO to R18C9A.FCI n11005
FCITOFCO_D --- 0.162 R18C9A.FCI to R18C9A.FCO SLICE_59
ROUTE 1 0.000 R18C9A.FCO to R18C9B.FCI n11006
FCITOFCO_D --- 0.162 R18C9B.FCI to R18C9B.FCO SLICE_58
ROUTE 1 0.000 R18C9B.FCO to R18C9C.FCI n11007
FCITOFCO_D --- 0.162 R18C9C.FCI to R18C9C.FCO SLICE_57
ROUTE 1 0.000 R18C9C.FCO to R18C9D.FCI n11008
FCITOFCO_D --- 0.162 R18C9D.FCI to R18C9D.FCO SLICE_56
ROUTE 1 0.000 R18C9D.FCO to R18C10A.FCI n11009
FCITOF1_DE --- 0.643 R18C10A.FCI to R18C10A.F1 SLICE_55
ROUTE 1 0.000 R18C10A.F1 to R18C10A.DI1 n2817 (to osc_clk)
--------
14.169 (62.3% logic, 37.7% route), 37 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2431:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.161 OSC.OSC to R22C2D.CLK osc_clk
--------
4.161 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R18C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 2.983ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_Byte_i5 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i63 (to osc_clk +)
Delay: 14.133ns (62.4% logic, 37.6% route), 37 logic levels.
Constraint Details:
14.133ns physical path delay SLICE_2289 to SLICE_55 exceeds
11.278ns delay constraint less
-0.038ns skew and
0.166ns DIN_SET requirement (totaling 11.150ns) by 2.983ns
Physical Path Details:
Data path SLICE_2289 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R22C2C.CLK to R22C2C.Q0 SLICE_2289 (from osc_clk)
ROUTE 4 1.065 R22C2C.Q0 to R21C2A.A0 o_Rx_Byte_5
CTOF_DEL --- 0.495 R21C2A.A0 to R21C2A.F0 SLICE_2475
ROUTE 4 0.790 R21C2A.F0 to R21C4C.C0 n8257
CTOF_DEL --- 0.495 R21C4C.C0 to R21C4C.F0 SLICE_2449
ROUTE 5 0.769 R21C4C.F0 to R21C5C.C1 n12533
CTOF_DEL --- 0.495 R21C5C.C1 to R21C5C.F1 SLICE_2389
ROUTE 52 1.102 R21C5C.F1 to R21C3D.A0 n13056
CTOF_DEL --- 0.495 R21C3D.A0 to R21C3D.F0 SLICE_2414
ROUTE 1 1.583 R21C3D.F0 to R18C2B.C1 n2361
C1TOFCO_DE --- 0.889 R18C2B.C1 to R18C2B.FCO SLICE_86
ROUTE 1 0.000 R18C2B.FCO to R18C2C.FCI n10979
FCITOFCO_D --- 0.162 R18C2C.FCI to R18C2C.FCO SLICE_85
ROUTE 1 0.000 R18C2C.FCO to R18C2D.FCI n10980
FCITOFCO_D --- 0.162 R18C2D.FCI to R18C2D.FCO SLICE_84
ROUTE 1 0.000 R18C2D.FCO to R18C3A.FCI n10981
FCITOFCO_D --- 0.162 R18C3A.FCI to R18C3A.FCO SLICE_83
ROUTE 1 0.000 R18C3A.FCO to R18C3B.FCI n10982
FCITOFCO_D --- 0.162 R18C3B.FCI to R18C3B.FCO SLICE_82
ROUTE 1 0.000 R18C3B.FCO to R18C3C.FCI n10983
FCITOFCO_D --- 0.162 R18C3C.FCI to R18C3C.FCO SLICE_81
ROUTE 1 0.000 R18C3C.FCO to R18C3D.FCI n10984
FCITOFCO_D --- 0.162 R18C3D.FCI to R18C3D.FCO SLICE_80
ROUTE 1 0.000 R18C3D.FCO to R18C4A.FCI n10985
FCITOFCO_D --- 0.162 R18C4A.FCI to R18C4A.FCO SLICE_79
ROUTE 1 0.000 R18C4A.FCO to R18C4B.FCI n10986
FCITOFCO_D --- 0.162 R18C4B.FCI to R18C4B.FCO SLICE_78
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10987
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_77
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10988
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_76
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10989
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_75
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10990
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_74
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10991
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_73
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10992
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_72
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10993
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_71
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10994
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_70
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10995
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_69
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10996
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_68
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10997
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_67
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10998
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_66
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10999
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_65
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n11000
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_64
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n11001
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_63
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n11002
FCITOFCO_D --- 0.162 R18C8B.FCI to R18C8B.FCO SLICE_62
ROUTE 1 0.000 R18C8B.FCO to R18C8C.FCI n11003
FCITOFCO_D --- 0.162 R18C8C.FCI to R18C8C.FCO SLICE_61
ROUTE 1 0.000 R18C8C.FCO to R18C8D.FCI n11004
FCITOFCO_D --- 0.162 R18C8D.FCI to R18C8D.FCO SLICE_60
ROUTE 1 0.000 R18C8D.FCO to R18C9A.FCI n11005
FCITOFCO_D --- 0.162 R18C9A.FCI to R18C9A.FCO SLICE_59
ROUTE 1 0.000 R18C9A.FCO to R18C9B.FCI n11006
FCITOFCO_D --- 0.162 R18C9B.FCI to R18C9B.FCO SLICE_58
ROUTE 1 0.000 R18C9B.FCO to R18C9C.FCI n11007
FCITOFCO_D --- 0.162 R18C9C.FCI to R18C9C.FCO SLICE_57
ROUTE 1 0.000 R18C9C.FCO to R18C9D.FCI n11008
FCITOFCO_D --- 0.162 R18C9D.FCI to R18C9D.FCO SLICE_56
ROUTE 1 0.000 R18C9D.FCO to R18C10A.FCI n11009
FCITOF1_DE --- 0.643 R18C10A.FCI to R18C10A.F1 SLICE_55
ROUTE 1 0.000 R18C10A.F1 to R18C10A.DI1 n2817 (to osc_clk)
--------
14.133 (62.4% logic, 37.6% route), 37 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2289:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.161 OSC.OSC to R22C2C.CLK osc_clk
--------
4.161 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R18C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 2.961ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i62 (to osc_clk +)
Delay: 14.111ns (62.1% logic, 37.9% route), 37 logic levels.
Constraint Details:
14.111ns physical path delay SLICE_2431 to SLICE_55 exceeds
11.278ns delay constraint less
-0.038ns skew and
0.166ns DIN_SET requirement (totaling 11.150ns) by 2.961ns
Physical Path Details:
Data path SLICE_2431 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R22C2D.CLK to R22C2D.Q0 SLICE_2431 (from osc_clk)
ROUTE 4 1.101 R22C2D.Q0 to R21C2A.B0 o_Rx_DV
CTOF_DEL --- 0.495 R21C2A.B0 to R21C2A.F0 SLICE_2475
ROUTE 4 0.790 R21C2A.F0 to R21C4C.C0 n8257
CTOF_DEL --- 0.495 R21C4C.C0 to R21C4C.F0 SLICE_2449
ROUTE 5 0.769 R21C4C.F0 to R21C5C.C1 n12533
CTOF_DEL --- 0.495 R21C5C.C1 to R21C5C.F1 SLICE_2389
ROUTE 52 1.102 R21C5C.F1 to R21C3D.A0 n13056
CTOF_DEL --- 0.495 R21C3D.A0 to R21C3D.F0 SLICE_2414
ROUTE 1 1.583 R21C3D.F0 to R18C2B.C1 n2361
C1TOFCO_DE --- 0.889 R18C2B.C1 to R18C2B.FCO SLICE_86
ROUTE 1 0.000 R18C2B.FCO to R18C2C.FCI n10979
FCITOFCO_D --- 0.162 R18C2C.FCI to R18C2C.FCO SLICE_85
ROUTE 1 0.000 R18C2C.FCO to R18C2D.FCI n10980
FCITOFCO_D --- 0.162 R18C2D.FCI to R18C2D.FCO SLICE_84
ROUTE 1 0.000 R18C2D.FCO to R18C3A.FCI n10981
FCITOFCO_D --- 0.162 R18C3A.FCI to R18C3A.FCO SLICE_83
ROUTE 1 0.000 R18C3A.FCO to R18C3B.FCI n10982
FCITOFCO_D --- 0.162 R18C3B.FCI to R18C3B.FCO SLICE_82
ROUTE 1 0.000 R18C3B.FCO to R18C3C.FCI n10983
FCITOFCO_D --- 0.162 R18C3C.FCI to R18C3C.FCO SLICE_81
ROUTE 1 0.000 R18C3C.FCO to R18C3D.FCI n10984
FCITOFCO_D --- 0.162 R18C3D.FCI to R18C3D.FCO SLICE_80
ROUTE 1 0.000 R18C3D.FCO to R18C4A.FCI n10985
FCITOFCO_D --- 0.162 R18C4A.FCI to R18C4A.FCO SLICE_79
ROUTE 1 0.000 R18C4A.FCO to R18C4B.FCI n10986
FCITOFCO_D --- 0.162 R18C4B.FCI to R18C4B.FCO SLICE_78
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10987
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_77
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10988
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_76
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10989
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_75
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10990
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_74
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10991
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_73
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10992
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_72
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10993
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_71
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10994
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_70
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10995
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_69
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10996
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_68
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10997
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_67
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10998
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_66
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10999
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_65
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n11000
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_64
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n11001
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_63
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n11002
FCITOFCO_D --- 0.162 R18C8B.FCI to R18C8B.FCO SLICE_62
ROUTE 1 0.000 R18C8B.FCO to R18C8C.FCI n11003
FCITOFCO_D --- 0.162 R18C8C.FCI to R18C8C.FCO SLICE_61
ROUTE 1 0.000 R18C8C.FCO to R18C8D.FCI n11004
FCITOFCO_D --- 0.162 R18C8D.FCI to R18C8D.FCO SLICE_60
ROUTE 1 0.000 R18C8D.FCO to R18C9A.FCI n11005
FCITOFCO_D --- 0.162 R18C9A.FCI to R18C9A.FCO SLICE_59
ROUTE 1 0.000 R18C9A.FCO to R18C9B.FCI n11006
FCITOFCO_D --- 0.162 R18C9B.FCI to R18C9B.FCO SLICE_58
ROUTE 1 0.000 R18C9B.FCO to R18C9C.FCI n11007
FCITOFCO_D --- 0.162 R18C9C.FCI to R18C9C.FCO SLICE_57
ROUTE 1 0.000 R18C9C.FCO to R18C9D.FCI n11008
FCITOFCO_D --- 0.162 R18C9D.FCI to R18C9D.FCO SLICE_56
ROUTE 1 0.000 R18C9D.FCO to R18C10A.FCI n11009
FCITOF0_DE --- 0.585 R18C10A.FCI to R18C10A.F0 SLICE_55
ROUTE 1 0.000 R18C10A.F0 to R18C10A.DI0 n2818 (to osc_clk)
--------
14.111 (62.1% logic, 37.9% route), 37 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2431:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.161 OSC.OSC to R22C2D.CLK osc_clk
--------
4.161 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R18C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 2.957ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i61 (to osc_clk +)
Delay: 14.107ns (60.1% logic, 39.9% route), 34 logic levels.
Constraint Details:
14.107ns physical path delay SLICE_2431 to SLICE_56 exceeds
11.278ns delay constraint less
-0.038ns skew and
0.166ns DIN_SET requirement (totaling 11.150ns) by 2.957ns
Physical Path Details:
Data path SLICE_2431 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R22C2D.CLK to R22C2D.Q0 SLICE_2431 (from osc_clk)
ROUTE 4 1.101 R22C2D.Q0 to R21C2A.B0 o_Rx_DV
CTOF_DEL --- 0.495 R21C2A.B0 to R21C2A.F0 SLICE_2475
ROUTE 4 0.790 R21C2A.F0 to R21C4C.C0 n8257
CTOF_DEL --- 0.495 R21C4C.C0 to R21C4C.F0 SLICE_2449
ROUTE 5 0.648 R21C4C.F0 to R21C5B.D1 n12533
CTOF_DEL --- 0.495 R21C5B.D1 to R21C5B.F1 SLICE_2387
ROUTE 49 1.051 R21C5B.F1 to R22C5A.A0 n2563
CTOF_DEL --- 0.495 R22C5A.A0 to R22C5A.F0 SLICE_2411
ROUTE 1 2.045 R22C5A.F0 to R18C2D.C0 n2358
C0TOFCO_DE --- 1.023 R18C2D.C0 to R18C2D.FCO SLICE_84
ROUTE 1 0.000 R18C2D.FCO to R18C3A.FCI n10981
FCITOFCO_D --- 0.162 R18C3A.FCI to R18C3A.FCO SLICE_83
ROUTE 1 0.000 R18C3A.FCO to R18C3B.FCI n10982
FCITOFCO_D --- 0.162 R18C3B.FCI to R18C3B.FCO SLICE_82
ROUTE 1 0.000 R18C3B.FCO to R18C3C.FCI n10983
FCITOFCO_D --- 0.162 R18C3C.FCI to R18C3C.FCO SLICE_81
ROUTE 1 0.000 R18C3C.FCO to R18C3D.FCI n10984
FCITOFCO_D --- 0.162 R18C3D.FCI to R18C3D.FCO SLICE_80
ROUTE 1 0.000 R18C3D.FCO to R18C4A.FCI n10985
FCITOFCO_D --- 0.162 R18C4A.FCI to R18C4A.FCO SLICE_79
ROUTE 1 0.000 R18C4A.FCO to R18C4B.FCI n10986
FCITOFCO_D --- 0.162 R18C4B.FCI to R18C4B.FCO SLICE_78
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10987
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_77
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10988
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_76
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10989
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_75
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10990
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_74
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10991
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_73
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10992
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_72
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10993
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_71
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10994
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_70
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10995
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_69
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10996
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_68
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10997
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_67
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10998
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_66
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10999
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_65
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n11000
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_64
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n11001
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_63
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n11002
FCITOFCO_D --- 0.162 R18C8B.FCI to R18C8B.FCO SLICE_62
ROUTE 1 0.000 R18C8B.FCO to R18C8C.FCI n11003
FCITOFCO_D --- 0.162 R18C8C.FCI to R18C8C.FCO SLICE_61
ROUTE 1 0.000 R18C8C.FCO to R18C8D.FCI n11004
FCITOFCO_D --- 0.162 R18C8D.FCI to R18C8D.FCO SLICE_60
ROUTE 1 0.000 R18C8D.FCO to R18C9A.FCI n11005
FCITOFCO_D --- 0.162 R18C9A.FCI to R18C9A.FCO SLICE_59
ROUTE 1 0.000 R18C9A.FCO to R18C9B.FCI n11006
FCITOFCO_D --- 0.162 R18C9B.FCI to R18C9B.FCO SLICE_58
ROUTE 1 0.000 R18C9B.FCO to R18C9C.FCI n11007
FCITOFCO_D --- 0.162 R18C9C.FCI to R18C9C.FCO SLICE_57
ROUTE 1 0.000 R18C9C.FCO to R18C9D.FCI n11008
FCITOF1_DE --- 0.643 R18C9D.FCI to R18C9D.F1 SLICE_56
ROUTE 1 0.000 R18C9D.F1 to R18C9D.DI1 n2819 (to osc_clk)
--------
14.107 (60.1% logic, 39.9% route), 34 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2431:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.161 OSC.OSC to R22C2D.CLK osc_clk
--------
4.161 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R18C9D.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 2.925ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_Byte_i5 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i62 (to osc_clk +)
Delay: 14.075ns (62.3% logic, 37.7% route), 37 logic levels.
Constraint Details:
14.075ns physical path delay SLICE_2289 to SLICE_55 exceeds
11.278ns delay constraint less
-0.038ns skew and
0.166ns DIN_SET requirement (totaling 11.150ns) by 2.925ns
Physical Path Details:
Data path SLICE_2289 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R22C2C.CLK to R22C2C.Q0 SLICE_2289 (from osc_clk)
ROUTE 4 1.065 R22C2C.Q0 to R21C2A.A0 o_Rx_Byte_5
CTOF_DEL --- 0.495 R21C2A.A0 to R21C2A.F0 SLICE_2475
ROUTE 4 0.790 R21C2A.F0 to R21C4C.C0 n8257
CTOF_DEL --- 0.495 R21C4C.C0 to R21C4C.F0 SLICE_2449
ROUTE 5 0.769 R21C4C.F0 to R21C5C.C1 n12533
CTOF_DEL --- 0.495 R21C5C.C1 to R21C5C.F1 SLICE_2389
ROUTE 52 1.102 R21C5C.F1 to R21C3D.A0 n13056
CTOF_DEL --- 0.495 R21C3D.A0 to R21C3D.F0 SLICE_2414
ROUTE 1 1.583 R21C3D.F0 to R18C2B.C1 n2361
C1TOFCO_DE --- 0.889 R18C2B.C1 to R18C2B.FCO SLICE_86
ROUTE 1 0.000 R18C2B.FCO to R18C2C.FCI n10979
FCITOFCO_D --- 0.162 R18C2C.FCI to R18C2C.FCO SLICE_85
ROUTE 1 0.000 R18C2C.FCO to R18C2D.FCI n10980
FCITOFCO_D --- 0.162 R18C2D.FCI to R18C2D.FCO SLICE_84
ROUTE 1 0.000 R18C2D.FCO to R18C3A.FCI n10981
FCITOFCO_D --- 0.162 R18C3A.FCI to R18C3A.FCO SLICE_83
ROUTE 1 0.000 R18C3A.FCO to R18C3B.FCI n10982
FCITOFCO_D --- 0.162 R18C3B.FCI to R18C3B.FCO SLICE_82
ROUTE 1 0.000 R18C3B.FCO to R18C3C.FCI n10983
FCITOFCO_D --- 0.162 R18C3C.FCI to R18C3C.FCO SLICE_81
ROUTE 1 0.000 R18C3C.FCO to R18C3D.FCI n10984
FCITOFCO_D --- 0.162 R18C3D.FCI to R18C3D.FCO SLICE_80
ROUTE 1 0.000 R18C3D.FCO to R18C4A.FCI n10985
FCITOFCO_D --- 0.162 R18C4A.FCI to R18C4A.FCO SLICE_79
ROUTE 1 0.000 R18C4A.FCO to R18C4B.FCI n10986
FCITOFCO_D --- 0.162 R18C4B.FCI to R18C4B.FCO SLICE_78
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10987
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_77
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10988
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_76
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10989
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_75
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10990
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_74
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10991
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_73
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10992
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_72
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10993
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_71
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10994
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_70
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10995
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_69
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10996
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_68
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10997
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_67
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10998
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_66
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10999
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_65
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n11000
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_64
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n11001
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_63
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n11002
FCITOFCO_D --- 0.162 R18C8B.FCI to R18C8B.FCO SLICE_62
ROUTE 1 0.000 R18C8B.FCO to R18C8C.FCI n11003
FCITOFCO_D --- 0.162 R18C8C.FCI to R18C8C.FCO SLICE_61
ROUTE 1 0.000 R18C8C.FCO to R18C8D.FCI n11004
FCITOFCO_D --- 0.162 R18C8D.FCI to R18C8D.FCO SLICE_60
ROUTE 1 0.000 R18C8D.FCO to R18C9A.FCI n11005
FCITOFCO_D --- 0.162 R18C9A.FCI to R18C9A.FCO SLICE_59
ROUTE 1 0.000 R18C9A.FCO to R18C9B.FCI n11006
FCITOFCO_D --- 0.162 R18C9B.FCI to R18C9B.FCO SLICE_58
ROUTE 1 0.000 R18C9B.FCO to R18C9C.FCI n11007
FCITOFCO_D --- 0.162 R18C9C.FCI to R18C9C.FCO SLICE_57
ROUTE 1 0.000 R18C9C.FCO to R18C9D.FCI n11008
FCITOFCO_D --- 0.162 R18C9D.FCI to R18C9D.FCO SLICE_56
ROUTE 1 0.000 R18C9D.FCO to R18C10A.FCI n11009
FCITOF0_DE --- 0.585 R18C10A.FCI to R18C10A.F0 SLICE_55
ROUTE 1 0.000 R18C10A.F0 to R18C10A.DI0 n2818 (to osc_clk)
--------
14.075 (62.3% logic, 37.7% route), 37 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2289:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.161 OSC.OSC to R22C2C.CLK osc_clk
--------
4.161 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R18C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 2.921ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_Byte_i5 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i61 (to osc_clk +)
Delay: 14.071ns (60.2% logic, 39.8% route), 34 logic levels.
Constraint Details:
14.071ns physical path delay SLICE_2289 to SLICE_56 exceeds
11.278ns delay constraint less
-0.038ns skew and
0.166ns DIN_SET requirement (totaling 11.150ns) by 2.921ns
Physical Path Details:
Data path SLICE_2289 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R22C2C.CLK to R22C2C.Q0 SLICE_2289 (from osc_clk)
ROUTE 4 1.065 R22C2C.Q0 to R21C2A.A0 o_Rx_Byte_5
CTOF_DEL --- 0.495 R21C2A.A0 to R21C2A.F0 SLICE_2475
ROUTE 4 0.790 R21C2A.F0 to R21C4C.C0 n8257
CTOF_DEL --- 0.495 R21C4C.C0 to R21C4C.F0 SLICE_2449
ROUTE 5 0.648 R21C4C.F0 to R21C5B.D1 n12533
CTOF_DEL --- 0.495 R21C5B.D1 to R21C5B.F1 SLICE_2387
ROUTE 49 1.051 R21C5B.F1 to R22C5A.A0 n2563
CTOF_DEL --- 0.495 R22C5A.A0 to R22C5A.F0 SLICE_2411
ROUTE 1 2.045 R22C5A.F0 to R18C2D.C0 n2358
C0TOFCO_DE --- 1.023 R18C2D.C0 to R18C2D.FCO SLICE_84
ROUTE 1 0.000 R18C2D.FCO to R18C3A.FCI n10981
FCITOFCO_D --- 0.162 R18C3A.FCI to R18C3A.FCO SLICE_83
ROUTE 1 0.000 R18C3A.FCO to R18C3B.FCI n10982
FCITOFCO_D --- 0.162 R18C3B.FCI to R18C3B.FCO SLICE_82
ROUTE 1 0.000 R18C3B.FCO to R18C3C.FCI n10983
FCITOFCO_D --- 0.162 R18C3C.FCI to R18C3C.FCO SLICE_81
ROUTE 1 0.000 R18C3C.FCO to R18C3D.FCI n10984
FCITOFCO_D --- 0.162 R18C3D.FCI to R18C3D.FCO SLICE_80
ROUTE 1 0.000 R18C3D.FCO to R18C4A.FCI n10985
FCITOFCO_D --- 0.162 R18C4A.FCI to R18C4A.FCO SLICE_79
ROUTE 1 0.000 R18C4A.FCO to R18C4B.FCI n10986
FCITOFCO_D --- 0.162 R18C4B.FCI to R18C4B.FCO SLICE_78
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10987
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_77
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10988
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_76
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10989
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_75
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10990
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_74
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10991
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_73
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10992
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_72
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10993
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_71
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10994
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_70
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10995
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_69
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10996
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_68
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10997
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_67
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10998
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_66
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10999
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_65
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n11000
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_64
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n11001
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_63
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n11002
FCITOFCO_D --- 0.162 R18C8B.FCI to R18C8B.FCO SLICE_62
ROUTE 1 0.000 R18C8B.FCO to R18C8C.FCI n11003
FCITOFCO_D --- 0.162 R18C8C.FCI to R18C8C.FCO SLICE_61
ROUTE 1 0.000 R18C8C.FCO to R18C8D.FCI n11004
FCITOFCO_D --- 0.162 R18C8D.FCI to R18C8D.FCO SLICE_60
ROUTE 1 0.000 R18C8D.FCO to R18C9A.FCI n11005
FCITOFCO_D --- 0.162 R18C9A.FCI to R18C9A.FCO SLICE_59
ROUTE 1 0.000 R18C9A.FCO to R18C9B.FCI n11006
FCITOFCO_D --- 0.162 R18C9B.FCI to R18C9B.FCO SLICE_58
ROUTE 1 0.000 R18C9B.FCO to R18C9C.FCI n11007
FCITOFCO_D --- 0.162 R18C9C.FCI to R18C9C.FCO SLICE_57
ROUTE 1 0.000 R18C9C.FCO to R18C9D.FCI n11008
FCITOF1_DE --- 0.643 R18C9D.FCI to R18C9D.F1 SLICE_56
ROUTE 1 0.000 R18C9D.F1 to R18C9D.DI1 n2819 (to osc_clk)
--------
14.071 (60.2% logic, 39.8% route), 34 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2289:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.161 OSC.OSC to R22C2C.CLK osc_clk
--------
4.161 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R18C9D.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Warning: 69.459MHz is the maximum frequency for this preference.
================================================================================
Preference: CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET "osc_clk" ;
18 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.014ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutN4
Data Path Delay: 10.787ns (40.7% logic, 59.3% route), 3 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
10.787ns delay PWM1/SLICE_6 to PWMOutN4 (totaling 14.986ns) meets
20.000ns offset OSCH_inst to PWMOutN4 by 5.014ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R3C14B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutN4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 4.716 R3C14B.Q1 to R25C35A.D0 PWMOutP4_c
CTOF_DEL --- 0.495 R25C35A.D0 to R25C35A.F0 SLICE_2496
ROUTE 4 1.676 R25C35A.F0 to 71.PADDO PWMOutN4_c
DOPAD_DEL --- 3.448 71.PADDO to 71.PAD PWMOutN4
--------
10.787 (40.7% logic, 59.3% route), 3 logic levels.
Passed: The following path meets requirements by 5.014ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutN3
Data Path Delay: 10.787ns (40.7% logic, 59.3% route), 3 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
10.787ns delay PWM1/SLICE_6 to PWMOutN3 (totaling 14.986ns) meets
20.000ns offset OSCH_inst to PWMOutN3 by 5.014ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R3C14B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutN3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 4.716 R3C14B.Q1 to R25C35A.D0 PWMOutP4_c
CTOF_DEL --- 0.495 R25C35A.D0 to R25C35A.F0 SLICE_2496
ROUTE 4 1.676 R25C35A.F0 to 70.PADDO PWMOutN4_c
DOPAD_DEL --- 3.448 70.PADDO to 70.PAD PWMOutN3
--------
10.787 (40.7% logic, 59.3% route), 3 logic levels.
Passed: The following path meets requirements by 5.096ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_Byte_i1 (from osc_clk +)
Destination: Port Pad MYLED[6]
Data Path Delay: 10.743ns (30.2% logic, 69.8% route), 2 logic levels.
Clock Path Delay: 4.161ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.161ns delay OSCH_inst to SLICE_2465 and
10.743ns delay SLICE_2465 to MYLED[6] (totaling 14.904ns) meets
20.000ns offset OSCH_inst to MYLED[6] by 5.096ns
Physical Path Details:
Clock path OSCH_inst to SLICE_2465:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.161 OSC.OSC to R21C2D.CLK osc_clk
--------
4.161 (0.0% logic, 100.0% route), 0 logic levels.
Data path SLICE_2465 to MYLED[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R21C2D.CLK to R21C2D.Q0 SLICE_2465 (from osc_clk)
ROUTE 11 7.494 R21C2D.Q0 to 106.PADDO MYLED_c_6
DOPAD_DEL --- 2.797 106.PADDO to 106.PAD MYLED[6]
--------
10.743 (30.2% logic, 69.8% route), 2 logic levels.
Passed: The following path meets requirements by 5.858ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutN2
Data Path Delay: 9.943ns (44.2% logic, 55.8% route), 3 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
9.943ns delay PWM1/SLICE_6 to PWMOutN2 (totaling 14.142ns) meets
20.000ns offset OSCH_inst to PWMOutN2 by 5.858ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R3C14B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutN2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 4.716 R3C14B.Q1 to R25C35A.D0 PWMOutP4_c
CTOF_DEL --- 0.495 R25C35A.D0 to R25C35A.F0 SLICE_2496
ROUTE 4 0.832 R25C35A.F0 to 67.PADDO PWMOutN4_c
DOPAD_DEL --- 3.448 67.PADDO to 67.PAD PWMOutN2
--------
9.943 (44.2% logic, 55.8% route), 3 logic levels.
Passed: The following path meets requirements by 5.858ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutN1
Data Path Delay: 9.943ns (44.2% logic, 55.8% route), 3 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
9.943ns delay PWM1/SLICE_6 to PWMOutN1 (totaling 14.142ns) meets
20.000ns offset OSCH_inst to PWMOutN1 by 5.858ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R3C14B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutN1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 4.716 R3C14B.Q1 to R25C35A.D0 PWMOutP4_c
CTOF_DEL --- 0.495 R25C35A.D0 to R25C35A.F0 SLICE_2496
ROUTE 4 0.832 R25C35A.F0 to 65.PADDO PWMOutN4_c
DOPAD_DEL --- 3.448 65.PADDO to 65.PAD PWMOutN1
--------
9.943 (44.2% logic, 55.8% route), 3 logic levels.
Passed: The following path meets requirements by 6.583ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutP4
Data Path Delay: 9.218ns (42.3% logic, 57.7% route), 2 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
9.218ns delay PWM1/SLICE_6 to PWMOutP4 (totaling 13.417ns) meets
20.000ns offset OSCH_inst to PWMOutP4 by 6.583ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R3C14B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutP4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 5.318 R3C14B.Q1 to 69.PADDO PWMOutP4_c
DOPAD_DEL --- 3.448 69.PADDO to 69.PAD PWMOutP4
--------
9.218 (42.3% logic, 57.7% route), 2 logic levels.
Passed: The following path meets requirements by 6.583ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutP3
Data Path Delay: 9.218ns (42.3% logic, 57.7% route), 2 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
9.218ns delay PWM1/SLICE_6 to PWMOutP3 (totaling 13.417ns) meets
20.000ns offset OSCH_inst to PWMOutP3 by 6.583ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R3C14B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutP3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 5.318 R3C14B.Q1 to 68.PADDO PWMOutP4_c
DOPAD_DEL --- 3.448 68.PADDO to 68.PAD PWMOutP3
--------
9.218 (42.3% logic, 57.7% route), 2 logic levels.
Passed: The following path meets requirements by 7.082ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutP2
Data Path Delay: 8.719ns (44.7% logic, 55.3% route), 2 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
8.719ns delay PWM1/SLICE_6 to PWMOutP2 (totaling 12.918ns) meets
20.000ns offset OSCH_inst to PWMOutP2 by 7.082ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R3C14B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutP2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 4.819 R3C14B.Q1 to 62.PADDO PWMOutP4_c
DOPAD_DEL --- 3.448 62.PADDO to 62.PAD PWMOutP2
--------
8.719 (44.7% logic, 55.3% route), 2 logic levels.
Passed: The following path meets requirements by 7.082ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutP1
Data Path Delay: 8.719ns (44.7% logic, 55.3% route), 2 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
8.719ns delay PWM1/SLICE_6 to PWMOutP1 (totaling 12.918ns) meets
20.000ns offset OSCH_inst to PWMOutP1 by 7.082ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R3C14B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutP1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 4.819 R3C14B.Q1 to 61.PADDO PWMOutP4_c
DOPAD_DEL --- 3.448 61.PADDO to 61.PAD PWMOutP1
--------
8.719 (44.7% logic, 55.3% route), 2 logic levels.
Passed: The following path meets requirements by 8.111ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOut
Data Path Delay: 7.690ns (50.7% logic, 49.3% route), 2 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
7.690ns delay PWM1/SLICE_6 to PWMOut (totaling 11.889ns) meets
20.000ns offset OSCH_inst to PWMOut by 8.111ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R3C14B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOut:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 3.790 R3C14B.Q1 to 43.PADDO PWMOutP4_c
DOPAD_DEL --- 3.448 43.PADDO to 43.PAD PWMOut
--------
7.690 (50.7% logic, 49.3% route), 2 logic levels.
Report: 14.986ns is the minimum offset for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "osc_clk" 88.670000 MHz ; | 88.670 MHz| 69.459 MHz| 35 *
| | |
CLOCK_TO_OUT ALLPORTS 20.000000 ns | | |
CLKNET "osc_clk" ; | 20.000 ns| 14.986 ns| 3
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
n11003 | 1| 3194| 77.98%
| | |
n11004 | 1| 3142| 76.71%
| | |
n11001 | 1| 3074| 75.05%
| | |
n11002 | 1| 3073| 75.02%
| | |
n11005 | 1| 3038| 74.17%
| | |
n11000 | 1| 3004| 73.34%
| | |
n11006 | 1| 2912| 71.09%
| | |
n10999 | 1| 2806| 68.51%
| | |
n11007 | 1| 2697| 65.84%
| | |
n10998 | 1| 2679| 65.41%
| | |
n10997 | 1| 2639| 64.43%
| | |
n10996 | 1| 2569| 62.72%
| | |
n10995 | 1| 2457| 59.99%
| | |
n10994 | 1| 2411| 58.86%
| | |
n10993 | 1| 2363| 57.69%
| | |
n10992 | 1| 2213| 54.03%
| | |
n11008 | 1| 2173| 53.05%
| | |
n10991 | 1| 2125| 51.88%
| | |
n10990 | 1| 2066| 50.44%
| | |
n10989 | 1| 1921| 46.90%
| | |
n10988 | 1| 1823| 44.51%
| | |
n10987 | 1| 1747| 42.65%
| | |
n10986 | 1| 1647| 40.21%
| | |
n10985 | 1| 1467| 35.82%
| | |
n10984 | 1| 1342| 32.76%
| | |
n11009 | 1| 1273| 31.08%
| | |
n10810 | 1| 1233| 30.10%
| | |
n10811 | 1| 1215| 29.66%
| | |
n10983 | 1| 1194| 29.15%
| | |
n10812 | 1| 1151| 28.10%
| | |
n10813 | 1| 1130| 27.59%
| | |
n10814 | 1| 1098| 26.81%
| | |
n8257 | 4| 1065| 26.00%
| | |
n10815 | 1| 1049| 25.61%
| | |
n10816 | 1| 990| 24.17%
| | |
n10809 | 1| 987| 24.10%
| | |
n12533 | 5| 964| 23.54%
| | |
n10817 | 1| 942| 23.00%
| | |
n10818 | 1| 871| 21.26%
| | |
n10982 | 1| 851| 20.78%
| | |
n10819 | 1| 738| 18.02%
| | |
n10820 | 1| 720| 17.58%
| | |
n10821 | 1| 695| 16.97%
| | |
n10981 | 1| 674| 16.46%
| | |
n2817 | 1| 672| 16.41%
| | |
n10808 | 1| 639| 15.60%
| | |
n11023 | 1| 634| 15.48%
| | |
n11021 | 1| 628| 15.33%
| | |
n11020 | 1| 623| 15.21%
| | |
n11022 | 1| 620| 15.14%
| | |
n11024 | 1| 612| 14.94%
| | |
n2818 | 1| 601| 14.67%
| | |
n10822 | 1| 594| 14.50%
| | |
n11019 | 1| 592| 14.45%
| | |
n10823 | 1| 589| 14.38%
| | |
n11025 | 1| 584| 14.26%
| | |
n11026 | 1| 579| 14.14%
| | |
n11027 | 1| 533| 13.01%
| | |
n10824 | 1| 521| 12.72%
| | |
n11028 | 1| 502| 12.26%
| | |
n11029 | 1| 501| 12.23%
| | |
n10825 | 1| 494| 12.06%
| | |
n2819 | 1| 483| 11.79%
| | |
n11030 | 1| 475| 11.60%
| | |
n11031 | 1| 469| 11.45%
| | |
n11032 | 1| 464| 11.33%
| | |
n11033 | 1| 463| 11.30%
| | |
n2820 | 1| 435| 10.62%
| | |
n2563 | 49| 425| 10.38%
| | |
n13056 | 52| 418| 10.21%
| | |
n11034 | 1| 412| 10.06%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 3 clocks:
Clock Domain: uart_rx1/UartClk[2] Source: uart_rx1/SLICE_12.Q1 Loads: 29
No transfer within this clock domain is found
Clock Domain: osc_clk Source: OSCH_inst.OSC Loads: 1367
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ;
Data transfers from:
Clock Domain: uart_rx1/UartClk[2] Source: uart_rx1/SLICE_12.Q1
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ; Transfers: 9
Clock Domain: CIC1_out_clkSin Source: CIC1Sin/SLICE_2197.Q0
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ; Transfers: 10
Clock Domain: CIC1_out_clkSin Source: CIC1Sin/SLICE_2197.Q0 Loads: 153
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 4096 Score: 7336209
Cumulative negative slack: 7336209
Constraints cover 1466977 paths, 1 nets, and 16496 connections (99.99% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) <IP_ADDRESS>6
Mon Apr 06 13:42:52 2020
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o FPGASDR_impl1.twr -gui -msgset C:/Users/user/lattice/1BitADCFPGASDR/promote.xml FPGASDR_impl1.ncd FPGASDR_impl1.prf
Design file: fpgasdr_impl1.ncd
Preference file: fpgasdr_impl1.prf
Device,speed: LCMXO2-7000HE,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "osc_clk" 88.670000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET "osc_clk" (0 errors) 18 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "osc_clk" 88.670000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_tmp_i0_i53 (from osc_clk +)
Destination: FF Data in CIC1Sin/d_d_tmp_i0_i53 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Sin/SLICE_2167 to CIC1Sin/SLICE_2130 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Sin/SLICE_2167 to CIC1Sin/SLICE_2130:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R12C38B.CLK to R12C38B.Q1 CIC1Sin/SLICE_2167 (from osc_clk)
ROUTE 3 0.154 R12C38B.Q1 to R12C38D.M1 CIC1Sin/d_tmp_53 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Sin/SLICE_2167:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R12C38B.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Sin/SLICE_2130:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R12C38D.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Cos/d_tmp_i0_i2 (from osc_clk +)
Destination: FF Data in CIC1Cos/d_d_tmp_i0_i2 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R22C17A.CLK to R22C17A.Q0 CIC1Cos/SLICE_1893 (from osc_clk)
ROUTE 2 0.154 R22C17A.Q0 to R22C17C.M0 CIC1Cos/d_tmp_2 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Cos/SLICE_1893:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R22C17A.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1856:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R22C17C.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Cos/d_tmp_i0_i35 (from osc_clk +)
Destination: FF Data in CIC1Cos/d_d_tmp_i0_i35 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Cos/SLICE_1909 to CIC1Cos/SLICE_1872 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Cos/SLICE_1909 to CIC1Cos/SLICE_1872:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R22C23B.CLK to R22C23B.Q1 CIC1Cos/SLICE_1909 (from osc_clk)
ROUTE 2 0.154 R22C23B.Q1 to R22C23D.M1 CIC1Cos/d_tmp_35 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Cos/SLICE_1909:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R22C23B.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1872:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R22C23D.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_tmp_i0_i32 (from osc_clk +)
Destination: FF Data in CIC1Sin/d_d_tmp_i0_i32 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Sin/SLICE_2157 to CIC1Sin/SLICE_2120 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Sin/SLICE_2157 to CIC1Sin/SLICE_2120:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R11C30C.CLK to R11C30C.Q0 CIC1Sin/SLICE_2157 (from osc_clk)
ROUTE 2 0.154 R11C30C.Q0 to R11C30D.M0 CIC1Sin/d_tmp_32 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Sin/SLICE_2157:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R11C30C.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Sin/SLICE_2120:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R11C30D.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Cos/d_tmp_i0_i34 (from osc_clk +)
Destination: FF Data in CIC1Cos/d_d_tmp_i0_i34 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Cos/SLICE_1909 to CIC1Cos/SLICE_1872 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Cos/SLICE_1909 to CIC1Cos/SLICE_1872:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R22C23B.CLK to R22C23B.Q0 CIC1Cos/SLICE_1909 (from osc_clk)
ROUTE 2 0.154 R22C23B.Q0 to R22C23D.M0 CIC1Cos/d_tmp_34 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Cos/SLICE_1909:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R22C23B.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1872:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R22C23D.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Cos/d_tmp_i0_i12 (from osc_clk +)
Destination: FF Data in CIC1Cos/d_d_tmp_i0_i12 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Cos/SLICE_1898 to CIC1Cos/SLICE_1861 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Cos/SLICE_1898 to CIC1Cos/SLICE_1861:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R23C19B.CLK to R23C19B.Q0 CIC1Cos/SLICE_1898 (from osc_clk)
ROUTE 2 0.154 R23C19B.Q0 to R23C19D.M0 CIC1Cos/d_tmp_12 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Cos/SLICE_1898:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R23C19B.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1861:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R23C19D.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_tmp_i0_i7 (from osc_clk +)
Destination: FF Data in CIC1Sin/d_d_tmp_i0_i7 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Sin/SLICE_2144 to CIC1Sin/SLICE_2107 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Sin/SLICE_2144 to CIC1Sin/SLICE_2107:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R11C27B.CLK to R11C27B.Q0 CIC1Sin/SLICE_2144 (from osc_clk)
ROUTE 2 0.154 R11C27B.Q0 to R11C27A.M0 CIC1Sin/d_tmp_7 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Sin/SLICE_2144:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R11C27B.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Sin/SLICE_2107:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R11C27A.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Mixer1/RFInR1_13 (from osc_clk +)
Destination: FF Data in Mixer1/RFInR_14 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay Mixer1/SLICE_2223 to Mixer1/SLICE_2223 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path Mixer1/SLICE_2223 to Mixer1/SLICE_2223:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C24A.CLK to R2C24A.Q1 Mixer1/SLICE_2223 (from osc_clk)
ROUTE 2 0.154 R2C24A.Q1 to R2C24A.M0 DiffOut_c (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to Mixer1/SLICE_2223:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R2C24A.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to Mixer1/SLICE_2223:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R2C24A.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_tmp_i0_i33 (from osc_clk +)
Destination: FF Data in CIC1Sin/d_d_tmp_i0_i33 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Sin/SLICE_2157 to CIC1Sin/SLICE_2120 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Sin/SLICE_2157 to CIC1Sin/SLICE_2120:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R11C30C.CLK to R11C30C.Q1 CIC1Sin/SLICE_2157 (from osc_clk)
ROUTE 2 0.154 R11C30C.Q1 to R11C30D.M1 CIC1Sin/d_tmp_33 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Sin/SLICE_2157:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R11C30C.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Sin/SLICE_2120:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R11C30D.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_tmp_i0_i52 (from osc_clk +)
Destination: FF Data in CIC1Sin/d_d_tmp_i0_i52 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Sin/SLICE_2167 to CIC1Sin/SLICE_2130 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Sin/SLICE_2167 to CIC1Sin/SLICE_2130:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R12C38B.CLK to R12C38B.Q0 CIC1Sin/SLICE_2167 (from osc_clk)
ROUTE 3 0.154 R12C38B.Q0 to R12C38D.M0 CIC1Sin/d_tmp_52 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Sin/SLICE_2167:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R12C38B.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Sin/SLICE_2130:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R12C38D.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET "osc_clk" ;
18 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.722ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Mixer1/RFInR1_13 (from osc_clk +)
Destination: Port Pad DiffOut
Data Path Delay: 1.531ns (79.5% logic, 20.5% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to Mixer1/SLICE_2223 and
1.531ns delay Mixer1/SLICE_2223 to DiffOut (totaling 2.722ns) meets
0.000ns hold offset OSCH_inst to DiffOut by 2.722ns
Physical Path Details:
Clock path OSCH_inst to Mixer1/SLICE_2223:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R2C24A.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path Mixer1/SLICE_2223 to DiffOut:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C24A.CLK to R2C24A.Q1 Mixer1/SLICE_2223 (from osc_clk)
ROUTE 2 0.314 R2C24A.Q1 to 122.PADDO DiffOut_c
DOPAD_DEL --- 1.084 122.PADDO to 122.PAD DiffOut
--------
1.531 (79.5% logic, 20.5% route), 2 logic levels.
Passed: The following path meets requirements by 2.840ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i6 (from osc_clk +)
Destination: Port Pad MYLED[0]
Data Path Delay: 1.649ns (65.9% logic, 34.1% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to CIC1Sin/SLICE_2218 and
1.649ns delay CIC1Sin/SLICE_2218 to MYLED[0] (totaling 2.840ns) meets
0.000ns hold offset OSCH_inst to MYLED[0] by 2.840ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2218:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R8C28D.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2218 to MYLED[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C28D.CLK to R8C28D.Q0 CIC1Sin/SLICE_2218 (from osc_clk)
ROUTE 2 0.563 R8C28D.Q0 to 97.PADDO MYLED_c_0
DOPAD_DEL --- 0.953 97.PADDO to 97.PAD MYLED[0]
--------
1.649 (65.9% logic, 34.1% route), 2 logic levels.
Passed: The following path meets requirements by 2.875ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i8 (from osc_clk +)
Destination: Port Pad MYLED[2]
Data Path Delay: 1.684ns (64.5% logic, 35.5% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to CIC1Sin/SLICE_2219 and
1.684ns delay CIC1Sin/SLICE_2219 to MYLED[2] (totaling 2.875ns) meets
0.000ns hold offset OSCH_inst to MYLED[2] by 2.875ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2219:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R8C29D.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2219 to MYLED[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C29D.CLK to R8C29D.Q0 CIC1Sin/SLICE_2219 (from osc_clk)
ROUTE 2 0.598 R8C29D.Q0 to 99.PADDO MYLED_c_2
DOPAD_DEL --- 0.953 99.PADDO to 99.PAD MYLED[2]
--------
1.684 (64.5% logic, 35.5% route), 2 logic levels.
Passed: The following path meets requirements by 2.940ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i7 (from osc_clk +)
Destination: Port Pad MYLED[1]
Data Path Delay: 1.749ns (62.1% logic, 37.9% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to CIC1Sin/SLICE_2218 and
1.749ns delay CIC1Sin/SLICE_2218 to MYLED[1] (totaling 2.940ns) meets
0.000ns hold offset OSCH_inst to MYLED[1] by 2.940ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2218:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R8C28D.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2218 to MYLED[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C28D.CLK to R8C28D.Q1 CIC1Sin/SLICE_2218 (from osc_clk)
ROUTE 2 0.663 R8C28D.Q1 to 98.PADDO MYLED_c_1
DOPAD_DEL --- 0.953 98.PADDO to 98.PAD MYLED[1]
--------
1.749 (62.1% logic, 37.9% route), 2 logic levels.
Passed: The following path meets requirements by 2.956ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i9 (from osc_clk +)
Destination: Port Pad MYLED[3]
Data Path Delay: 1.765ns (61.5% logic, 38.5% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to CIC1Sin/SLICE_2219 and
1.765ns delay CIC1Sin/SLICE_2219 to MYLED[3] (totaling 2.956ns) meets
0.000ns hold offset OSCH_inst to MYLED[3] by 2.956ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2219:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R8C29D.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2219 to MYLED[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C29D.CLK to R8C29D.Q1 CIC1Sin/SLICE_2219 (from osc_clk)
ROUTE 2 0.679 R8C29D.Q1 to 100.PADDO MYLED_c_3
DOPAD_DEL --- 0.953 100.PADDO to 100.PAD MYLED[3]
--------
1.765 (61.5% logic, 38.5% route), 2 logic levels.
Passed: The following path meets requirements by 2.986ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i10 (from osc_clk +)
Destination: Port Pad MYLED[4]
Data Path Delay: 1.795ns (60.5% logic, 39.5% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to CIC1Sin/SLICE_2220 and
1.795ns delay CIC1Sin/SLICE_2220 to MYLED[4] (totaling 2.986ns) meets
0.000ns hold offset OSCH_inst to MYLED[4] by 2.986ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2220:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R8C29B.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2220 to MYLED[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C29B.CLK to R8C29B.Q0 CIC1Sin/SLICE_2220 (from osc_clk)
ROUTE 2 0.709 R8C29B.Q0 to 104.PADDO MYLED_c_4
DOPAD_DEL --- 0.953 104.PADDO to 104.PAD MYLED[4]
--------
1.795 (60.5% logic, 39.5% route), 2 logic levels.
Passed: The following path meets requirements by 2.986ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i11 (from osc_clk +)
Destination: Port Pad MYLED[5]
Data Path Delay: 1.795ns (60.5% logic, 39.5% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to CIC1Sin/SLICE_2221 and
1.795ns delay CIC1Sin/SLICE_2221 to MYLED[5] (totaling 2.986ns) meets
0.000ns hold offset OSCH_inst to MYLED[5] by 2.986ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2221:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R8C29A.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2221 to MYLED[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C29A.CLK to R8C29A.Q0 CIC1Sin/SLICE_2221 (from osc_clk)
ROUTE 2 0.709 R8C29A.Q0 to 105.PADDO MYLED_c_5
DOPAD_DEL --- 0.953 105.PADDO to 105.PAD MYLED[5]
--------
1.795 (60.5% logic, 39.5% route), 2 logic levels.
Passed: The following path meets requirements by 3.273ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ncoGen/phase_accum_i63 (from osc_clk +)
Destination: Port Pad sinGen
Data Path Delay: 2.082ns (63.3% logic, 36.7% route), 3 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to ncoGen/SLICE_725 and
2.082ns delay ncoGen/SLICE_725 to sinGen (totaling 3.273ns) meets
0.000ns hold offset OSCH_inst to sinGen by 3.273ns
Physical Path Details:
Clock path OSCH_inst to ncoGen/SLICE_725:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R12C10D.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path ncoGen/SLICE_725 to sinGen:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R12C10D.CLK to R12C10D.Q1 ncoGen/SLICE_725 (from osc_clk)
ROUTE 3 0.452 R12C10D.Q1 to R2C10B.A0 phase_accum_63
CTOF_DEL --- 0.101 R2C10B.A0 to R2C10B.F0 ncoGen/SLICE_2510
ROUTE 1 0.312 R2C10B.F0 to 142.PADDO sinGen_c
DOPAD_DEL --- 1.084 142.PADDO to 142.PAD sinGen
--------
2.082 (63.3% logic, 36.7% route), 3 logic levels.
Passed: The following path meets requirements by 3.415ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOut
Data Path Delay: 2.224ns (54.7% logic, 45.3% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to PWM1/SLICE_6 and
2.224ns delay PWM1/SLICE_6 to PWMOut (totaling 3.415ns) meets
0.000ns hold offset OSCH_inst to PWMOut by 3.415ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R3C14B.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOut:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 1.007 R3C14B.Q1 to 43.PADDO PWMOutP4_c
DOPAD_DEL --- 1.084 43.PADDO to 43.PAD PWMOut
--------
2.224 (54.7% logic, 45.3% route), 2 logic levels.
Passed: The following path meets requirements by 3.706ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutP1
Data Path Delay: 2.515ns (48.4% logic, 51.6% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to PWM1/SLICE_6 and
2.515ns delay PWM1/SLICE_6 to PWMOutP1 (totaling 3.706ns) meets
0.000ns hold offset OSCH_inst to PWMOutP1 by 3.706ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R3C14B.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutP1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 1.298 R3C14B.Q1 to 61.PADDO PWMOutP4_c
DOPAD_DEL --- 1.084 61.PADDO to 61.PAD PWMOutP1
--------
2.515 (48.4% logic, 51.6% route), 2 logic levels.
Report: 2.722ns is the maximum offset for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "osc_clk" 88.670000 MHz ; | 0.000 ns| 0.306 ns| 1
| | |
CLOCK_TO_OUT ALLPORTS 20.000000 ns | | |
CLKNET "osc_clk" ; | 0.000 ns| 2.722 ns| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 3 clocks:
Clock Domain: uart_rx1/UartClk[2] Source: uart_rx1/SLICE_12.Q1 Loads: 29
No transfer within this clock domain is found
Clock Domain: osc_clk Source: OSCH_inst.OSC Loads: 1367
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ;
Data transfers from:
Clock Domain: uart_rx1/UartClk[2] Source: uart_rx1/SLICE_12.Q1
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ; Transfers: 9
Clock Domain: CIC1_out_clkSin Source: CIC1Sin/SLICE_2197.Q0
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ; Transfers: 10
Clock Domain: CIC1_out_clkSin Source: CIC1Sin/SLICE_2197.Q0 Loads: 153
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1466977 paths, 1 nets, and 16496 connections (99.99% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 4096 (setup), 0 (hold)
Score: 7336209 (setup), 0 (hold)
Cumulative negative slack: 7336209 (7336209+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------


Here is where you define all variables necessary to make the simulation work properly
you can create different group for different types of variables, each group can gave as many variables as you want.
The following types are offered: Boolean (True or False), integer numbers, float numbers, text or CSV(Comma separated File)


I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love. I do what I love.
You can call me or ping me on facebook.


The gradient of a scalar function f(ψ,𝜃,ζ) is readily calculated from the chain rule,
|
| (102) |
Note that the gradient of a scalar function is in the covariant representation. The inverse form of this expression is obtained by dotting the above equation respectively by the three contravariant basis vectors, yielding
|
| (103) |
|
| (104) |
|
| (105) |
Using Eq. (102), the directional derivative in the direction of ∇ψ is written as
|
| (106) |


AGNEEV GHOSH
Project Portfolio
Research Experience/Academic Projects:
- Built a Medical System using Microsoft Kinect to treat a Neurological disorder (Phantom Limb Pain) at UCSD under Prof. Nadir Weibel
- Researched and analysed Multipath TCP (MPTCP) protocol for Linux kernel Implementation and proposed ideal use case scenarios.
- Implemented a novel technique for Threat Detection using Deep Packet Inspection for wire speed networks; More efficient in terms of CPU utilization and rate of threat detection as compared to existing algorithms
- Successfully carried out a project at IIT Kharagpur (India); titled Effective file search Using Hashing technique (TF-IDF score) and linked list implementation
Publications
- Title: “Title: “SQL Detection System for a safer Web Application”
Journal: IEEE Explore
Link: SQL detection system for a safer web application (IEEE)
- Title: “Title: “SQL Injection Attacks and Defensive Techniques”
Journal: International Journal of Computer Technology and Application
Link: SQL Injection Attacks and Defensive Techniques


'I hope Liberman comes to his senses and prevents elections'
Min. Regev praises Petah Tikva conference, expresses hope that Yisrael Beytenu will join right-wing coalition and prevent elections.
by Arutz Sheva StaffCulture and Sport Minister Miri Regev (Likud) praised the conference scheduled for Monday evening in Petah Tikva.
The conference, organized by Petah Tikva Mayor Rami Greenberg, will include local leaders from the Likud, as well as Yisrael Beytenu Chairman MK Avigdor Liberman.
"I spoke a few minutes ago with my friend, Rami Greenberg, mayor of Petah Tikva, who is leading a meeting of mayors from the Likud this evening, together with Liberman," she said. "He is making another effort to bring Liberman home. I hope that Liberman recovers and prevents unnecessary third elections."
"If indeed we are forced to hold third elections, I am glad that they will not be held on March 3, which is memorial day for those security forces whose place of burial is unknown. I am glad that we are preventing harm to the memories of the fallen and their bereaved families."
If a coalition is not formed by Wednesday, elections will be held on Monday, March 2, 2020.


--- layout: post title: The Lion, the Witch, and the Wardrobe post_id: 244 categories: - reviews date: 2005-12-12 21:58:00.000000000 -07:00 author: Jamis permalink: 2005/12/12/the-lion-the-witch-and-the-wardrobe.html ---
My wife and I found a babysitter this afternoon and went and saw The Chronicles of Narnia: The Lion, the Witch, and the Wardrobe. I’ve been especially curious about the film after reading afew scathing reviews lambasting it for its “religious themes”.
Well, I absolutely loved the movie. I haven’t been so moved by a film in a long time. The acting was superb, the scenery was beautiful, and the special effects were great. The religious themes are certainly there, if you look for them (but they’re in Lord of the Rings, too, if you look for them, and no one ever condemned that film for it).
I never see a film twice in the theater, but I would definitely make an exception for this one.


June 15, 2014
Inline display indicates that an element will be displayed in the same line as another element. Block display indicates that the element will be displayed on the next line down.
Uses
Inline is considered useful for small pieces of content, such as a few words. It can also be useful for images, icons, or buttons (such as navigation) that you'd like to display on the same line. In the case of inline, dimensions are meaningless. Spans are by default set to display inline.
Block is used to ensure that content appears on the next line. Dimensions (width and height) can be specified. Divs are by default set to disply block.
Example: Block
The code:
.post_images: {display:block}
The display:
Example: Inline
The code:
.post_images: {display:inline}
The display:


Sleep
In this month, we talked about:
- How much sleep is good enough and millenial's habits
- Biphasic sleep: is it better for you? And how to insert it to your daily life
- How to manage digital life and sleep
Want to know about it and more? Subscribe to our newsletter and care for yourself!
Home


Adept Installation Guide
This is a guide for installing and running the Adept Task Learning system and accompanying Adept-enabled applications.
Adept comes with two sample applications:
- Image Loader: for loading and manipulating image files.
- Novo: poses puzzles and permits manipulations for solving them.
These applications provide a simple environment for illustrating how Adept works.
They are documented in the Adept User Guide.
Table of Contents
System Requirements
Installing Adept on Windows
Installing and Enabling Adept Applications on Windows
Running Adept on Windows
Uninstalling Adept on Windows
System Requirements
Platform
Adept is supported for Windows 7 and Windows XP (Service Pack 2 or later).
Future MacOS support is dependent on JavaFX support for MacOS.
Software
The following software is required to run Adept:
- Java version 1.6.0_26 or higher
- JavaFX version 2.0.0 or higher
Windows
Installing Adept on Windows
- Run the installer.exe file.
- If JavaFX version 2.0.0 is not detected during installation,
the user is prompted to install it. Please visit the JavaFX
download page
http://www.javafx.com
and click the 'Download Now' link. Remember to agree to the license terms and select the
Windows platform.
- During the JavaFX install, if Java version 1.6.0_26 or higher is not detected, the user is prompted to install
it. Please click the OK button and follow the onscreen instructions for installing Java.
- Close your browser when the installation is complete.
- Should there be a problem with the install of JavaFX or Java while installing Adept,
they may be installed independently.
They are available at javafx.com and java.com respectively.
Installing and Enabling Adept Applications on Windows
The Image Loader and Novo applications are installed with Adept and require no further installation.
Running Adept on Windows
On the Start Menu, under Programs>SRI>Adept
, click
"Start Adept".
The Image Loader is started by clicking the Start Image Loader link in the
Adept>Applications
folder.
The Novo is started by clicking the Start Novo link in the
Adept>Applications
folder.
Adept must be run first in order for Image Loader or Novo to connect to Adept.
Uninstalling Adept on Windows
On the Start Menu, under Programs>SRI>Adept
, click
"Uninstall Adept".


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This is a upper-cased text. Set in the year 0 F.E. ("Foundation Era"), The Psychohistorians opens on Trantor, the capital of the 12,000-year-old Galactic Empire. Though the empire appears stable and powerful, it is slowly decaying in ways that parallel the decline of the Western Roman Empire.
This is a lower-cased text. Set in the year 0 F.E. ("Foundation Era"), The Psychohistorians opens on Trantor, the capital of the 12,000-year-old Galactic Empire. Though the empire appears stable and powerful, it is slowly decaying in ways that parallel the decline of the Western Roman Empire.
This is a caPitAlized teXt. Set in the yEar 0 F.E. ("Foundation Era"), The PsychohisTorians opens on Trantor, the capital of the 12,000-year-old Galactic Empire. Though the empire appears stable and powerful, it is slowly decaying in ways that parallel the decline of the Western Roman Empire.
Lorem ipsum dolor sit amet, consectetur adipisicing elit. Aperiam voluptatem similique officiis recusandae esse cum in totam quisquam perspiciatis quod! Magnam culpa vitae, tempore eos explicabo cupiditate. Deserunt, quisquam, quos!