| Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation. | ||
| But the value of AES_DADR will be updated later on. | ||
| Consequently, software can prepare the destination address for the next AES operation. | ||
| In DMA mode, software can update the next AES_DADR before triggering START. | ||
| The value of AES_SADR and AES_DADR can be the same. |
Definition at line 5104 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_IV0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5015 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_IV1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5030 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_IV2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5045 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_IV3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5060 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_KEY0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 4874 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_KEY1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 4892 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_KEY2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 4910 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_KEY3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 4928 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_KEY4 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 4946 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_KEY5 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 4964 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_KEY6 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 4982 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_KEY7 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5000 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES1_SADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SADDR | AES DMA Source Address |
| The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. | ||
| The AES_SADR keeps the source address of the data buffer where the source text is stored. | ||
| Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation. | ||
| The start of source address should be located at word boundary. | ||
| In other words, bit 1 and 0 of AES_SADR are ignored. | ||
| AES_SADR can be read and written. | ||
| Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation. | ||
| But the value of AES_SADR will be updated later on. | ||
| Consequently, software can prepare the DMA source address for the next AES operation. | ||
| In DMA mode, software can update the next AES_SADR before triggering START. | ||
| The value of AES_SADR and AES_DADR can be the same. |
Definition at line 5082 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CNT | AES Byte Count |
| The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. | ||
| The AES_CNT is 32-bit and the maximum of byte count is 4G bytes. | ||
| AES_CNT can be read and written. | ||
| Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation. | ||
| But the value of AES_CNT will be updated later on. | ||
| Consequently, software can prepare the byte count of data for the next AES operation. | ||
| According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block. | ||
| Operations that are less than one block will output unexpected result. | ||
| In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data. | ||
| In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. |
Definition at line 5394 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_DADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DADDR | AES DMA Destination Address |
| The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO. | ||
| The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored. | ||
| Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished. | ||
| The start of destination address should be located at word boundary. | ||
| In other words, bit 1 and 0 of AES_DADR are ignored. | ||
| AES_DADR can be read and written. | ||
| Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation. | ||
| But the value of AES_DADR will be updated later on. | ||
| Consequently, software can prepare the destination address for the next AES operation. | ||
| In DMA mode, software can update the next AES_DADR before triggering START. | ||
| The value of AES_SADR and AES_DADR can be the same. |
Definition at line 5373 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_IV0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5284 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_IV1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5299 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_IV2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5314 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_IV3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5329 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_KEY0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5143 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_KEY1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5161 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_KEY2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5179 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_KEY3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5197 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_KEY4 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5215 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_KEY5 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5233 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_KEY6 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5251 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_KEY7 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5269 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES2_SADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SADDR | AES DMA Source Address |
| The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. | ||
| The AES_SADR keeps the source address of the data buffer where the source text is stored. | ||
| Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation. | ||
| The start of source address should be located at word boundary. | ||
| In other words, bit 1 and 0 of AES_SADR are ignored. | ||
| AES_SADR can be read and written. | ||
| Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation. | ||
| But the value of AES_SADR will be updated later on. | ||
| Consequently, software can prepare the DMA source address for the next AES operation. | ||
| In DMA mode, software can update the next AES_SADR before triggering START. | ||
| The value of AES_SADR and AES_DADR can be the same. |
Definition at line 5351 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CNT | AES Byte Count |
| The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. | ||
| The AES_CNT is 32-bit and the maximum of byte count is 4G bytes. | ||
| AES_CNT can be read and written. | ||
| Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation. | ||
| But the value of AES_CNT will be updated later on. | ||
| Consequently, software can prepare the byte count of data for the next AES operation. | ||
| According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block. | ||
| Operations that are less than one block will output unexpected result. | ||
| In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data. | ||
| In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. |
Definition at line 5663 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_DADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DADDR | AES DMA Destination Address |
| The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO. | ||
| The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored. | ||
| Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished. | ||
| The start of destination address should be located at word boundary. | ||
| In other words, bit 1 and 0 of AES_DADR are ignored. | ||
| AES_DADR can be read and written. | ||
| Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation. | ||
| But the value of AES_DADR will be updated later on. | ||
| Consequently, software can prepare the destination address for the next AES operation. | ||
| In DMA mode, software can update the next AES_DADR before triggering START. | ||
| The value of AES_SADR and AES_DADR can be the same. |
Definition at line 5642 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_IV0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5553 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_IV1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5568 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_IV2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5583 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_IV3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IV | AES Initial Vector Word X |
| n = 0, 1..3. | ||
| x = 0, 1..3. | ||
| Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode. | ||
| Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. |
Definition at line 5598 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_KEY0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5412 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_KEY1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5430 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_KEY2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5448 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_KEY3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5466 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_KEY4 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5484 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_KEY5 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5502 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_KEY6 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5520 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_KEY7 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEY | AES Key X |
| The KEY keeps the security key for AES operation. | ||
| n = 0, 1..3. | ||
| x = 0, 1..7. | ||
| The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. | ||
| {AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation. | ||
| {AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation. | ||
| {AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation. |
Definition at line 5538 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES3_SADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SADDR | AES DMA Source Address |
| The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. | ||
| The AES_SADR keeps the source address of the data buffer where the source text is stored. | ||
| Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation. | ||
| The start of source address should be located at word boundary. | ||
| In other words, bit 1 and 0 of AES_SADR are ignored. | ||
| AES_SADR can be read and written. | ||
| Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation. | ||
| But the value of AES_SADR will be updated later on. | ||
| Consequently, software can prepare the DMA source address for the next AES operation. | ||
| In DMA mode, software can update the next AES_SADR before triggering START. | ||
| The value of AES_SADR and AES_DADR can be the same. |
Definition at line 5620 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES_CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | START | AES Engine Start |
| 0 = No effect. | ||
| 1 = Start AES engine. BUSY flag will be set. | ||
| Note: This bit is always 0 when it's read back. | ||
| [1] | STOP | AES Engine Stop |
| 0 = No effect. | ||
| 1 = Stop AES engine. | ||
| Note: This bit is always 0 when it's read back. | ||
| [2:3] | KEYSZ | AES Key Size |
| This bit defines three different key size for AES operation. | ||
| 2'b00 = 128 bits key. | ||
| 2'b01 = 192 bits key. | ||
| 2'b10 = 256 bits key. | ||
| 2'b11 = Reserved. | ||
| If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. | ||
| [5] | DMALAST | AES Last Block |
| In DMA mode, this bit must be set as beginning the last DMA cascade round. | ||
| In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. | ||
| This bit is always 0 when it's read back. Must be written again once START is triggered. | ||
| [6] | DMACSCAD | AES Engine DMA With Cascade Mode |
| 0 = DMA cascade function Disabled. | ||
| 1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. | ||
| [7] | DMAEN | AES Engine DMA Enable Control |
| 0 = AES DMA engine Disabled. | ||
| The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN. | ||
| 1 = AES DMA engine Enabled. | ||
| The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. | ||
| [8:15] | OPMODE | AES Engine Operation Modes |
| 0x00 = ECB (Electronic Codebook Mode) | ||
| 0x01 = CBC (Cipher Block Chaining Mode). | ||
| 0x02 = CFB (Cipher Feedback Mode). | ||
| 0x03 = OFB (Output Feedback Mode). | ||
| 0x04 = CTR (Counter Mode). | ||
| 0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). | ||
| 0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). | ||
| 0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). | ||
| [16] | ENCRPT | AES Encryption/Decryption |
| 0 = AES engine executes decryption operation. | ||
| 1 = AES engine executes encryption operation. | ||
| [22] | OUTSWAP | AES Engine Output Data Swap |
| 0 = Keep the original order. | ||
| 1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. | ||
| [23] | INSWAP | AES Engine Input Data Swap |
| 0 = Keep the original order. | ||
| 1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. | ||
| [24:25] | CHANNEL | AES Engine Working Channel |
| 00 = Current control register setting is for channel 0. | ||
| 01 = Current control register setting is for channel 1. | ||
| 10 = Current control register setting is for channel 2. | ||
| 11 = Current control register setting is for channel 3. | ||
| [26:30] | KEYUNPRT | Unprotect Key |
| Writing 0 to CRPT_AES_CTL [31] and "10110" to CRPT_AES_CTL [30:26] is to unprotect the AES key. | ||
| The KEYUNPRT can be read and written. | ||
| When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. | ||
| [31] | KEYPRT | Protect Key |
| Read as a flag to reflect KEYPRT. | ||
| 0 = No effect. | ||
| 1 = Protect the content of the AES key from reading. | ||
| The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx. | ||
| Once it is set, it can be cleared by asserting KEYUNPRT. | ||
| And the key content would be cleared as well. |
Definition at line 4518 of file NUC472_442.h.
| __IO uint32_t CRPT_T::AES_DATIN |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DATIN | AES Engine Input Port |
| CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. |
Definition at line 4574 of file NUC472_442.h.
| __I uint32_t CRPT_T::AES_DATOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DATOUT | AES Engine Output Port |
| CPU gets results from the AES engine through this port by checking CRPT_AES_STS. | ||
| Get data as OUTBUFEMPTY is 0. |
Definition at line 4587 of file NUC472_442.h.
| __I uint32_t CRPT_T::AES_FDBCK0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | FDBCK | AES Feedback Information |
| The feedback value is 128 bits in size. | ||
| The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode. | ||
| The AES engine outputs feedback information for IV in the next block's operation. | ||
| Software can use this feedback information to implement more than four DMA channels. | ||
| Software can store that feedback value temporarily. | ||
| After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting. |
Definition at line 4354 of file NUC472_442.h.
| __I uint32_t CRPT_T::AES_FDBCK1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | FDBCK | AES Feedback Information |
| The feedback value is 128 bits in size. | ||
| The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode. | ||
| The AES engine outputs feedback information for IV in the next block's operation. | ||
| Software can use this feedback information to implement more than four DMA channels. | ||
| Software can store that feedback value temporarily. | ||
| After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting. |
Definition at line 4371 of file NUC472_442.h.
| __I uint32_t CRPT_T::AES_FDBCK2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | FDBCK | AES Feedback Information |
| The feedback value is 128 bits in size. | ||
| The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode. | ||
| The AES engine outputs feedback information for IV in the next block's operation. | ||
| Software can use this feedback information to implement more than four DMA channels. | ||
| Software can store that feedback value temporarily. | ||
| After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting. |
Definition at line 4388 of file NUC472_442.h.
| __I uint32_t CRPT_T::AES_FDBCK3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | FDBCK | AES Feedback Information |
| The feedback value is 128 bits in size. | ||
| The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode. | ||
| The AES engine outputs feedback information for IV in the next block's operation. | ||
| Software can use this feedback information to implement more than four DMA channels. | ||
| Software can store that feedback value temporarily. | ||
| After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting. |
Definition at line 4405 of file NUC472_442.h.
| __I uint32_t CRPT_T::AES_STS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUSY | AES Engine Busy |
| 0 = The AES engine is idle or finished. | ||
| 1 = The AES engine is under processing. | ||
| [8] | INBUFEMPTY | AES Input Buffer Empty |
| 0 = There are some data in input buffer waiting for the AES engine to process. | ||
| 1 = AES input buffer is empty. | ||
| Software needs to feed data to the AES engine. | ||
| Otherwise, the AES engine will be pending to wait for input data. | ||
| [9] | INBUFFULL | AES Input Buffer Full Flag |
| 0 = AES input buffer is not full. Software can feed the data into the AES engine. | ||
| 1 = AES input buffer is full. | ||
| Software cannot feed data to the AES engine. | ||
| Otherwise, the flag INBUFERR will be set to 1. | ||
| [10] | INBUFERR | AES Input Buffer Error Flag |
| 0 = No error. | ||
| 1 = Error happens during feeding data to the AES engine. | ||
| [12] | CNTERR | AES_CNT Setting Error |
| 0 = No error in AES_CNT setting. | ||
| 1 = AES_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode. | ||
| [16] | OUTBUFEMPTY | AES Out Buffer Empty |
| 0 = AES output buffer is not empty. There are some valid data kept in output buffer. | ||
| 1 = AES output buffer is empty. | ||
| Software cannot get data from AES_DATA_OUT. | ||
| Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. | ||
| [17] | OUTBUFFULL | AES Out Buffer Full Flag |
| 0 = AES output buffer is not full. | ||
| 1 = AES output buffer is full, and software needs to get data from AES_DATA_OUT. | ||
| Otherwise, the AES engine will be pending since the output buffer is full. | ||
| [18] | OUTBUFERR | AES Out Buffer Error Flag |
| 0 = No error. | ||
| 1 = Error happens during getting the result from AES engine. | ||
| [20] | BUSERR | AES DMA Access Bus Error Flag |
| 0 = No error. | ||
| 1 = Bus error will stop DMA operation and AES engine. |
Definition at line 4562 of file NUC472_442.h.
| __IO uint32_t CLK_T::AHBCLK |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | PDMACKEN | PDMA Controller Clock Enable Control |
| 0 = PDMA engine clock Disabled. | ||
| 1 = PDMA engine clock Enabled. | ||
| [2] | ISPCKEN | Flash ISP Controller Clock Enable Control |
| 0 = Flash ISP engine clock Disabled. | ||
| 1 = Flash ISP engine clock Enabled. | ||
| [3] | EBICKEN | EBI Controller Clock Enable Control |
| 0 = EBI engine clock Disabled. | ||
| 1 = EBI engine clock Enabled. | ||
| [4] | USBHCKEN | USB HOST Controller Clock Enable Control |
| 0 = USB HOST engine clock Disabled. | ||
| 1 = USB HOST engine clock Enabled. | ||
| [5] | EMACCKEN | Ethernet Controller Clock Enable Control (NUC472 Only) |
| 0 = Ethernet Controller engine clock Disabled. | ||
| 1 = Ethernet Controller engine clock Enabled. | ||
| [6] | SDHCKEN | SDHOST Controller Clock Enable Control |
| 0 = SDHOST engine clock Disabled. | ||
| 1 = SDHOST engine clock Enabled. | ||
| [7] | CRCCKEN | CRC Generator Controller Clock Enable Control |
| 0 = CRC engine clock Disabled. | ||
| 1 = CRC engine clock Enabled. | ||
| [8] | CAPCKEN | Image Capture Interface Controller Clock Enable Control |
| 0 = CAP controller's clock Disabled. | ||
| 1 = CAP controller's clock Enabled. | ||
| [9] | SENCKEN | Sensor Clock Enable Control |
| 0 = Sensor clock Disabled. | ||
| 1 = Sensor clock Enabled. | ||
| [10] | USBDCKEN | USB 2.0 Device Clock Enable Control |
| 0 = USB device controller's clock Disabled. | ||
| 1 = USB device controller's clock Enabled. | ||
| [12] | CRPTCKEN | Cryptographic Accelerator Clock Enable Control |
| 0 = Cryptographic Accelerator clock Disabled. | ||
| 1 = Cryptographic Accelerator clock Enabled. |
Definition at line 2884 of file NUC472_442.h.
| __IO uint32_t EMAC_T::ALMSEC |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SEC | Time Stamp Counter Second Alarm |
| Time stamp counter second part alarm value. | ||
| This value is only useful when ALMEN (EMAC_TSCTL[5]) high. | ||
| If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. |
Definition at line 13233 of file NUC472_442.h.
| __IO uint32_t EMAC_T::ALMSUBSEC |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SUBSEC | Time Stamp Counter Sub-Second Alarm |
| Time stamp counter sub-second part alarm value. | ||
| This value is only useful when ALMEN (EMAC_TSCTL[5]) high. | ||
| If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. |
Definition at line 13247 of file NUC472_442.h.
| __IO uint32_t SC_T::ALTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TXRST | TX Software Reset |
| When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the TX internal state machine and pointers. | ||
| Note: This bit will be auto cleared after reset is complete. | ||
| [1] | RXRST | Rx Software Reset |
| When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the Rx internal state machine and pointers. | ||
| Note: This bit will be auto cleared after reset is complete. | ||
| [2] | DACTEN | Deactivation Sequence Generator Enable Control |
| This bit enables SC controller to initiate the card by deactivation sequence | ||
| 0 = No effect. | ||
| 1 = Deactivation sequence generator Enabled. | ||
| Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1. | ||
| Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). | ||
| So don't fill this bit, TXRST, and RXRST at the same time. | ||
| Note3: If SC_CTL [SCEN] not enabled, this filed cannot be programmed. | ||
| [3] | ACTEN | Activation Sequence Generator Enable Control |
| This bit enables SC controller to initiate the card by activation sequence | ||
| 0 = No effect. | ||
| 1 = Activation sequence generator Enabled. | ||
| Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1. | ||
| Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time. | ||
| Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [4] | WARSTEN | Warm Reset Sequence Generator Enable Control |
| This bit enables SC controller to initiate the card by warm reset sequence | ||
| 0 = No effect. | ||
| 1 = Warm reset sequence generator Enabled. | ||
| Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1. | ||
| Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time. | ||
| Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [5] | CNTEN0 | Internal Timer0 Start Enable Control |
| This bit enables Timer 0 to start counting. | ||
| Software can fill 0 to stop it and set 1 to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Start counting. | ||
| Note1: This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware. | ||
| Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). | ||
| So don't fill this bit, TXRST and RXRST at the same time. | ||
| Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [6] | CNTEN1 | Internal Timer1 Start Enable Control |
| This bit enables Timer 1 to start counting. | ||
| Software can fill 0 to stop it and set 1 to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Start counting. | ||
| Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11. | ||
| Don't filled CNTEN1 when SC_CTL([TMRSEL] = 00 or SC_CTL[TMRSEL] = 01. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware. | ||
| Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time. | ||
| Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [7] | CNTEN2 | Internal Timer2 Start Enable Control |
| This bit enables Timer 2 to start counting. | ||
| Software can fill 0 to stop it and set 1 to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Start counting. | ||
| Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11. | ||
| Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware. | ||
| Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). | ||
| So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time. | ||
| Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [8:9] | INITSEL | Initial Timing Selection |
| This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation). | ||
| Unit: SC clock | ||
| Activation: refer to SC Activation Sequence in Figure 5.19-4. | ||
| Warm-reset: refer to Warm-Reset Sequence in Figure 5.19-5 | ||
| Deactivation: refer to Deactivation Sequence in Figure 5.19-6 | ||
| [11] | ADACEN | Auto Deactivation When Card Removal |
| 0 = Auto deactivation Disabled when hardware detected the card removal. | ||
| 1 = Auto deactivation Enabled when hardware detected the card removal. | ||
| Note: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). | ||
| If this process completes, hardware will generate an interrupt INT_INIT to CPU. | ||
| [12] | RXBGTEN | Receiver Block Guard Time Function Enable Control |
| 0 = Receiver block guard time function Disabled. | ||
| 1 = Receiver block guard time function Enabled. | ||
| [13] | ACTSTS0 | Internal Timer0 Active State (Read Only) |
| This bit indicates the timer counter status of timer0. | ||
| 0 = Timer0 is not active. | ||
| 1 = Timer0 is active. | ||
| [14] | ACTSTS1 | Internal Timer1 Active State (Read Only) |
| This bit indicates the timer counter status of timer1. | ||
| 0 = Timer1 is not active. | ||
| 1 = Timer1 is active. | ||
| [15] | ACTSTS2 | Internal Timer2 Active State (Read Only) |
| This bit indicates the timer counter status of timer2. | ||
| 0 = Timer2 is not active. | ||
| 1 = Timer2 is active. |
Definition at line 21325 of file NUC472_442.h.
| __IO uint32_t UART_T::ALTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | BKFL | LIN Break Field Length |
| This field indicates a 4-bit LIN TX break field count. | ||
| Note1: This break field length is BRKFL + 1. | ||
| Note2: According to LIN spec, the reset value is 0xC (break field length = 13). | ||
| [6] | LINRXEN | LIN RX Enable Control |
| 0 = LIN RX mode Disabled. | ||
| 1 = LIN RX mode Enabled. | ||
| [7] | LINTXEN | LIN TX Break Mode Enable Control |
| The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field" depending on the setting HSEL register. | ||
| 0 = Send LIN TX header Disabled. | ||
| 1 = Send LIN TX header Enabled. | ||
| Note: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL field) transfer operation finished, this bit will be cleared automatically. | ||
| [8] | RS485NMM | RS-485 Normal Multi-Drop Operation Mode (NMM) |
| 0 = RS-485 Normal Multi-drop Operation Mode (NMM) Disabled. | ||
| 1 = RS-485 Normal Multi-drop Operation Mode (NMM) Enabled. | ||
| Note: It can't be active with RS-485_AAD operation mode. | ||
| [9] | RS485AAD | RS-485 Auto Address Detection Operation Mode (AAD) |
| 0 = RS-485 Auto Address Detection (AAD) Operation mode Disabled. | ||
| 1 = RS-485 Auto Address Detection (AAD) Operation mode Enabled. | ||
| Note: It can't be active with RS-485_NMM operation mode. | ||
| [10] | RS485AUD | RS-485 Auto Direction Mode (AUD) |
| 0 = RS-485 Auto Direction Operation (AUO) mode Disabled. | ||
| 1 = RS-485 Auto Direction Operation (AUO) mode Enabled. | ||
| Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. | ||
| [15] | ADDRDEN | RS-485 Address Detection Enable Control |
| This bit is use to enable RS-485 address detection mode. | ||
| 0 = address detection mode Disabled. | ||
| 1 = Address detection mode Enabled. | ||
| Note: This field is used for RS-485 any operation mode. | ||
| [24:31] | ADDRMV | Address Match Value |
| This field contains the RS-485 address match values. | ||
| Note: This field is used for RS-485 auto address detection mode. |
Definition at line 25635 of file NUC472_442.h.
| __IO uint32_t WDT_T::ALTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | RSTDSEL | Watchdog Timer Reset Delay Selection (Write Protect) |
| When WDT time-out happened, software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened. | ||
| Software can select a suitable value of WDT reset delay period for different WDT time-out period. | ||
| 00 = Watchdog Timer reset delay period is (1024+2) * WDT_CLK. | ||
| 01 = Watchdog Timer reset delay period is (128+2) * WDT_CLK. | ||
| 10 = Watchdog Timer reset delay period is (16+2) * WDT_CLK. | ||
| 11 = Watchdog Timer reset delay period is (1+2) * WDT_CLK. | ||
| Note: This register will be reset to 0 if WDT time-out reset happened |
Definition at line 28514 of file NUC472_442.h.
| __IO uint32_t CLK_T::APBCLK0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WDTCKEN | Watchdog Timer Clock Enable Control (Write Protect) |
| This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register REGWRPROT at address GCR_BA+0x100. | ||
| 0 = Watchdog Timer Clock Disabled. | ||
| 1 = Watchdog Timer Clock Enabled. | ||
| [1] | RTCCKEN | Real-Time-Clock APB Interface Clock Enable Control |
| This bit is used to control the RTC APB clock only, The RTC engine clock source is from the 32.768 kHz external low-speed crystal. | ||
| 0 = RTC Clock Disabled. | ||
| 1 = RTC Clock Enabled. | ||
| [2] | TMR0CKEN | Timer0 Clock Enable Control |
| 0 = Timer0 Clock Disabled. | ||
| 1 = Timer0 Clock Enabled. | ||
| [3] | TMR1CKEN | Timer1 Clock Enable Control |
| 0 = Timer1 Clock Disabled. | ||
| 1 = Timer1 Clock Enabled. | ||
| [4] | TMR2CKEN | Timer2 Clock Enable Control |
| 0 = Timer2 Clock Disabled. | ||
| 1 = Timer2 Clock Enabled. | ||
| [5] | TMR3CKEN | Timer3 Clock Enable Control |
| 0 = Timer3 Clock Disabled. | ||
| 1 = Timer3 Clock Enabled. | ||
| [6] | CLKOCKEN | Clock Output Enable Control |
| 0 = Clock Output Disabled. | ||
| 1 = Clock Output Enabled. | ||
| [7] | ACMPCKEN | Analog Comparator Clock Enable Control |
| 0 = Analog Comparator Clock Disabled. | ||
| 1 = Analog Comparator Clock Enabled. | ||
| [8] | I2C0CKEN | I2C0 Clock Enable Control |
| 0 = I2C0 Clock Disabled. | ||
| 1 = I2C0 Clock Enabled. | ||
| [9] | I2C1CKEN | I2C1 Clock Enable Control |
| 0 = I2C1 Clock Disabled. | ||
| 1 = I2C1 Clock Enabled. | ||
| [10] | I2C2CKEN | I2C2 Clock Enable Control |
| 0 = I2C2 Clock Disabled. | ||
| 1 = I2C2 Clock Enabled. | ||
| [11] | I2C3CKEN | I2C3 Clock Enable Control |
| 0 = I2C3 Clock Disabled. | ||
| 1 = I2C3 Clock Enabled. | ||
| [12] | SPI0CKEN | SPI0 Clock Enable Control |
| 0 = SPI0 Clock Disabled. | ||
| 1= SPI0 Clock Enabled. | ||
| [13] | SPI1CKEN | SPI1 Clock Enable Control |
| 0 = SPI1 Clock Disabled. | ||
| 1 = SPI1 Clock Enabled. | ||
| [14] | SPI2CKEN | SPI2 Clock Enable Control |
| 0 = SPI2 Clock Disabled. | ||
| 1 = SPI2 Clock Enabled. | ||
| [15] | SPI3CKEN | SPI3 Clock Enable Control |
| 0 = SPI3 Clock Disabled. | ||
| 1 = SPI3 Clock Enabled. | ||
| [16] | UART0CKEN | UART0 Clock Enable Control |
| 0 = UART0 clock Disabled. | ||
| 1 = UART0 clock Enabled. | ||
| [17] | UART1CKEN | UART1 Clock Enable Control |
| 0 = UART1 clock Disabled. | ||
| 1 = UART1 clock Enabled. | ||
| [18] | UART2CKEN | UART2 Clock Enable Control |
| 0 = UART2 clock Disabled. | ||
| 1 = UART2 clock Enabled. | ||
| [19] | UART3CKEN | UART3 Clock Enable Control |
| 0 = UART3 clock Disabled. | ||
| 1 = UART3 clock Enabled. | ||
| [20] | UART4CKEN | UART4 Clock Enable Control |
| 0 = UART4 clock Disabled. | ||
| 1 = UART4 clock Enabled. | ||
| [21] | UART5CKEN | UART5 Clock Enable Control |
| 0 = UART5 clock Disabled. | ||
| 1 = UART5 clock Enabled. | ||
| [24] | CAN0CKEN | CAN Bus Controller-0 Clock Enable Control |
| 0 = CAN0 clock Disabled. | ||
| 1 = CAN0 clock Enabled. | ||
| [25] | CAN1CKEN | CAN Bus Controller-1 Clock Enable Control |
| 0 = CAN1 clock Disabled. | ||
| 1 = CAN1 clock Enabled. | ||
| [26] | OTGCKEN | USB 2.0 OTG Device Controller Clock Enable Control |
| 0 = OTG clock Disabled. | ||
| 1 = OTG clock Enabled. | ||
| [28] | ADCCKEN | Analog-Digital-Converter (ADC) Clock Enable Control |
| 0 = ADC clock Disabled. | ||
| 1 = ADC clock Enabled. | ||
| [29] | I2S0CKEN | I2S0 Clock Enable Control |
| 0 = I2S Clock Disabled. | ||
| 1 = I2S Clock Enabled. | ||
| [30] | I2S1CKEN | I2S1 Clock Enable Control |
| 0 = I2S1 Clock Disabled. | ||
| 1 = I2S1 Clock Enabled. | ||
| [31] | PS2CKEN | PS/2 Clock Enable Control |
| 0 = PS/2 clock Disabled. | ||
| 1 = PS/2 clock Enabled. |
Definition at line 2984 of file NUC472_442.h.
| __IO uint32_t CLK_T::APBCLK1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SC0CKEN | SC0 Clock Enable Control |
| 0 = SC0 Clock Disabled. | ||
| 1 = SC0 Clock Enabled. | ||
| [1] | SC1CKEN | SC1 Clock Enable Control |
| 0 = SC1 Clock Disabled. | ||
| 1 = SC1 Clock Enabled. | ||
| [2] | SC2CKEN | SC2 Clock Enable Control |
| 0 = SC2 Clock Disabled. | ||
| 1 = SC2 Clock Enabled. | ||
| [3] | SC3CKEN | SC3 Clock Enable Control |
| 0 = SC3 Clock Disabled. | ||
| 1 = SC3 Clock Enabled. | ||
| [4] | SC4CKEN | SC4 Clock Enable Control |
| 0 = SC4 Clock Disabled. | ||
| 1 = SC4 Clock Enabled. | ||
| [5] | SC5CKEN | SC5 Clock Enable Control |
| 0 = SC5 Clock Disabled. | ||
| 1 = SC5 Clock Enabled. | ||
| [8] | I2C4CKEN | I2C4 Clock Enable Control |
| 0 = I2C4 Clock Disabled. | ||
| 1 = I2C4 Clock Enabled. | ||
| [16] | PWM0CH01CKEN | PWM0_01 Clock Enable Control |
| 0 = PWM0_01 Clock Disabled. | ||
| 1 = PWM0_01 Clock Enabled. | ||
| [17] | PWM0CH23CKEN | PWM0_23 Clock Enable Control |
| 0 = PWM0_23 Clock Disabled. | ||
| 1 = PWM0_23 Clock Enabled. | ||
| [18] | PWM0CH45CKEN | PWM0_45 Clock Enable Control |
| 0 = PWM0_45 Clock Disabled. | ||
| 1 = PWM0_45 Clock Enabled. | ||
| [19] | PWM1CH01CKEN | PWM1_01 Clock Enable Control |
| 0 = PWM1_01 Clock Disabled. | ||
| 1 = PWM1_01 Clock Enabled. | ||
| [20] | PWM1CH23CKEN | PWM1_23 Clock Enable Control |
| 0 = PWM1_23 Clock Disabled. | ||
| 1 = PWM1_23 Clock Enabled. | ||
| [21] | PWM1CH45CKEN | PWM1_45 Clock Enable Control |
| 0 = PWM1_45 Clock Disabled. | ||
| 1 = PWM1_45 Clock Enabled. | ||
| [22] | QEI0CKEN | Quadrature Encoder Interface (QEI0) Clock Enable Control |
| 0 = QEI0 clock Disabled. | ||
| 1 = QEI0 clock Enabled. | ||
| [23] | QEI1CKEN | Quadrature Encoder Interface (QEI1) Clock Enable Control |
| 0 = QEI1 clock Disabled. | ||
| 1 = QEI1 clock Enabled. | ||
| [26] | ECAP0CKEN | Enhance CAP (ECAP0) Clock Enable Control |
| 0 = ECAP0 clock Disabled. | ||
| 1 = ECAP0 clock Enabled. | ||
| [27] | ECAP1CKEN | Enhance CAP (ECAP1) Clock Enable Control |
| 0 = ECAP1 clock Disabled. | ||
| 1 = ECAP1 clock Enabled. | ||
| [28] | EPWM0CKEN | Enhance PWM0 (EPWM) Clock Enable Control |
| 0 = EPWM0 clock Disabled. | ||
| 1 = EPWM0 clock Enabled. | ||
| [29] | EPWM1CKEN | Enhance PWM1 (EPWM) Clock Enable Control |
| 0 = EPWM1 clock Disabled. | ||
| 1 = EPWM1 clock Enabled. | ||
| [30] | OPACKEN | OP Amplifier (OPA) Clock Enable Control |
| 0 = OPA clock Disabled. | ||
| 1 = OPA clock Enabled. | ||
| [31] | EADCCKEN | Enhance Analog-Digital-Converter (E ADC) Clock Enable Control |
| 0 = EADC clock Disabled. | ||
| 1 = EADC clock Enabled. |
Definition at line 3057 of file NUC472_442.h.
| __IO uint32_t CAN_IF_T::ARB1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | ID150 | Message Identifier 15-0 |
| ID28 - ID0, 29-bit Identifier ("Extended Frame"). | ||
| ID28 - ID18, 11-bit Identifier ("Standard Frame") |
Definition at line 978 of file NUC472_442.h.
| __IO uint32_t CAN_IF_T::ARB2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:12] | ID2816 | Message Identifier 28-16 |
| ID28 - ID0, 29-bit Identifier ("Extended Frame"). | ||
| ID28 - ID18, 11-bit Identifier ("Standard Frame") | ||
| [13] | Dir | Message Direction |
| 0 = Direction is receive. | ||
| On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted. | ||
| On reception of a Data Frame with matching identifier, that message is stored in this Message Object. | ||
| 1 = Direction is transmit. | ||
| On TxRqst, the respective Message Object is transmitted as a Data Frame. | ||
| On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one). | ||
| [14] | Xtd | Extended Identifier |
| 0 = The 11-bit ("standard") Identifier will be used for this Message Object. | ||
| 1 = The 29-bit ("extended") Identifier will be used for this Message Object. | ||
| [15] | MsgVal | Message Valid |
| 0 = The Message Object is ignored by the Message Handler. | ||
| 1 = The Message Object is configured and should be considered by the Message Handler. | ||
| Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). | ||
| This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required. |
Definition at line 1006 of file NUC472_442.h.
| __IO uint32_t EPWM_T::ASYMCMP0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | CMP | Asymmetric PWM Duty Register |
| When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle. |
Definition at line 14163 of file NUC472_442.h.
| __IO uint32_t EPWM_T::ASYMCMP2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | CMP | Asymmetric PWM Duty Register |
| When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle. |
Definition at line 14175 of file NUC472_442.h.
| __IO uint32_t EPWM_T::ASYMCMP4 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | CMP | Asymmetric PWM Duty Register |
| When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle. |
Definition at line 14187 of file NUC472_442.h.
| __IO uint32_t EPWM_T::ASYMCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ASYMEN | Asymmetric PWM Enable Control |
| 0 = Asymmetric PWM function Disabled. | ||
| 1 = Asymmetric PWM function Enabled. | ||
| Note: This control bit is only valid when PWM module is set in Centre-aligned mode. | ||
| [8:9] | ASYMMODE0 | Asymmetric PWMx0 Reload Mode Setting |
| 00 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start. | ||
| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle | ||
| 3. | ||
| PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]). | ||
| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle. | ||
| 01 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start. | ||
| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle | ||
| 3. | ||
| PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]). | ||
| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle. | ||
| 5. PWMx0 must be less than ASPWMx0 | ||
| 10 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start. | ||
| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle | ||
| 3. | ||
| PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]). | ||
| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle. | ||
| 5. PWMx0 must be greater than ASPWMx0. | ||
| 11 = Reserved. | ||
| Note1: x=0~1 for PWM unit 0~1. | ||
| Note2: This bit field is available only when ASYMEN=1. | ||
| Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle. | ||
| [16:17] | ASYMMODE2 | Asymmetric PWMx2 Reload Mode Setting |
| 00 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start. | ||
| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle | ||
| 3. | ||
| PWM compare output toggles at compare match, in the meanwhile, PWM compare register 2 is reloaded with CMP (ASPWMx2[15:00]). | ||
| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle. | ||
| 01 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start. | ||
| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle | ||
| 3. | ||
| PWM compare output toggles at compare match, in the meanwhile, PWM compare register2 is reloaded with CMP (ASPWMx2[15:00]). | ||
| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle. | ||
| 5. PWMx2 must be less than ASPWMx2 | ||
| 10 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start. | ||
| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle | ||
| 3. | ||
| PWM compare output toggles at compare match, in the meanwhile, PWM compare register 2 is reloaded with CMP (ASPWMx2[15:00]). | ||
| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle. | ||
| 5. PWMx2 must be greater than ASPWMx2. | ||
| 11 = Reserved. | ||
| Note1: x=0~1 for PWM unit 0~1. | ||
| Note2: This bit field is available only when ASYMEN=1. | ||
| Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle. | ||
| [24:25] | ASYMMODE4 | Asymmetric PWMx4 Reload Mode Setting |
| 00 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start. | ||
| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle | ||
| 3. | ||
| PWM compare output toggles at compare match, in the meanwhile, PWM compare register 4 is reloaded with CMP (ASPWMx4[15:00]). | ||
| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle. | ||
| 01 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start. | ||
| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle | ||
| 3. | ||
| PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx4[15:00]). | ||
| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle. | ||
| 5. PWMx4 must be less than ASPWMx4. | ||
| 10 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start. | ||
| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle | ||
| 3. | ||
| PWM compare output toggles at compare match, in the meanwhile, PWM compare register 4 is reloaded with CMP (ASPWMx4[15:00]). | ||
| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle. | ||
| 5. PWMx4 must be greater than ASPWMx4. | ||
| 11= Reserved. | ||
| Note1: x=0~1 for PWM unit 0~1. | ||
| Note2: This bit field is available only when ASYMEN=1. | ||
| Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle. |
Definition at line 14328 of file NUC472_442.h.
| __IO uint32_t UART_T::BAUD |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | BRD | Baud Rate Divider |
| The field indicated the baud rate divider | ||
| [24:27] | EDIVM1 | Divider X |
| The baud rate divider M = X+1. | ||
| [28] | BAUDM0 | Divider X Equal To 1 |
| 0 = Divider M = X (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must >= 8). | ||
| 1 = Divider M = 1 (the equation of M = 1, but BRD (UART_BAUD[15:0]) must >= 3). | ||
| Refer to the table below for more information. | ||
| [29] | BAUDM1 | Divider X Enable Control |
| The BRD = Baud Rate Divider, and the baud rate equation is | ||
| Baud Rate = Clock / [M * (BRD + 2)]; The default value of M is 16. | ||
| 0 = Divider X Disabled (the equation of M = 16). | ||
| 1 = Divider X Enabled (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must >= 8). | ||
| Refer to the table below for more information. | ||
| Note: In IrDA mode, this bit must disable. |
Definition at line 25573 of file NUC472_442.h.
| __IO uint32_t SDH_T::BLEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0:10] | BLKLEN | SD BLOCK LENGTH In Byte Unit |
| An 11-bit value specifies the SD transfer byte count of a block. | ||
| The actual byte count is equal to BLKLEN+1. | ||
| Note: The default SD block length is 512 bytes |
Definition at line 22477 of file NUC472_442.h.
| __IO uint32_t SYS_T::BODCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BODEN | Brown-Out Detector Enable Control (Write Protect) |
| The default value is set by flash controller user configuration register config0 bit[23] | ||
| 0 = Brown-out Detector function Disabled. | ||
| 1 = Brown-out Detector function Enabled. | ||
| This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address GCR_BA+0x100. | ||
| [1:2] | BODVL | Brown-Out Detector Threshold Voltage Selection (Write Protect) |
| The default value is set by flash controller user configuration register config0 bit[22:21] | ||
| Relationship between BODVL and Brown-out voltage listed below: | ||
| 00 = 2.2V. | ||
| 01 = 2.7V. | ||
| 10 = 3.8V. | ||
| 11 = 4.5V. | ||
| This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address GCR_BA+0x100. | ||
| [3] | BODRSTEN | Brown-Out Reset Enable Control (Write Protect) |
| While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). | ||
| While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. | ||
| BOD interrupt will keep till to the BODEN set to 0. | ||
| BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). | ||
| The default value is set by flash controller user configuration register config0 bit[20]. | ||
| 0 = Brown-out "INTERRUPT" function Enabled. | ||
| 1 = Brown-out "RESET" function Enabled. | ||
| This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address GCR_BA+0x100. | ||
| [4] | BODINTF | Brown-Out Detector Interrupt Flag |
| 0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. | ||
| 1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [5] | BODLPM | Brown-Out Detector Low Power Mode (Write Protect) |
| The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. | ||
| 0 = BOD operate in normal mode (default). | ||
| 1 = BOD Low Power mode Enabled. | ||
| This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address GCR_BA+0x100. | ||
| [6] | BODOUT | Brown-Out Detector Output Status |
| 0 = Brown-out Detector output status is 0. | ||
| It means the detected voltage is higher than BODVL setting or BODEN is 0. | ||
| 1 = Brown-out Detector output status is 1. | ||
| It means the detected voltage is lower than BODVL setting. | ||
| If the BODEN is 0, BOD function disabled , this bit always responds 0000. | ||
| [7] | LVREN | Low Voltage Reset Enable Control (Write Protect) |
| The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. | ||
| LVR function is enabled in default. | ||
| 0 = Low Voltage Reset function Disabled. | ||
| 1 = Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (default). | ||
| This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address GCR_BA+0x100. |
Definition at line 23584 of file NUC472_442.h.
| __IO uint32_t PWM_T::BRKCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BRKP0EN | Brake0 Function Enable Control |
| 0 = Brake0 detect function Disabled. | ||
| 1 = Brake0 detect function Enabled. | ||
| [1] | BRK0NFDIS | PWM Brake 0 Noise Filter Disable Control |
| 0 = Noise filter of PWM Brake 0 Enabled. | ||
| 1 = Noise filter of PWM Brake 0 Disabled. | ||
| [2] | BRK0INV | Inverse BKP0 State |
| 0 = The state of pin BKPx0 is passed to the negative edge detector. | ||
| 1 = The inversed state of pin BKPx0 is passed to the negative edge detector. | ||
| [6:7] | BRK0NFSEL | Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection |
| 00 = Filter clock = HCLK. | ||
| 01 = Filter clock = HCLK/2. | ||
| 10 = Filter clock = HCLK/4. | ||
| 11 = Filter clock = HCLK/16. | ||
| [8] | BRKP1EN | Brake1 Function Enable Control |
| 0 = Brake1 function Disabled. | ||
| 1 = Brake1 function Enabled. | ||
| [9] | BRK1NFDIS | PWM Brake 1 Noise Filter Disable Control |
| 0 = Noise filter of PWM Brake 1 Enabled. | ||
| 1 = Noise filter of PWM Brake 1 Disabled. | ||
| [10] | BRK1INV | Inverse BKP1 State |
| 0 = The state of pin BKPx1 is passed to the negative edge detector. | ||
| 1 = The inversed state of pin BKPx1 is passed to the negative edge detector. | ||
| [12:13] | BK1SEL | Brake Function 1 Source Selection |
| 00 = From external pin BKP1. | ||
| 01 = From analog comparator 0 output (CPO0). | ||
| 10 = From analog comparator 1 output (CPO1). | ||
| 11 = Reserved. | ||
| [14:15] | BRK1NFSEL | Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection |
| 00 = Filter clock = HCLK. | ||
| 01 = Filter clock = HCLK/2. | ||
| 10 = Filter clock = HCLK/4. | ||
| 11 = Filter clock = HCLK/16. | ||
| [16] | CPO0BKEN | CPO0 Digital Output As Brake0 Source Enable Control |
| 0 = CPO0 as one brake source in Brake 0 Disabled. | ||
| 1 = CPO0 as one brake source in Brake 0 Enabled. | ||
| [17] | CPO1BKEN | CPO1 Digital Output As Brake 0 Source Enable Control |
| 0 = CPO1 as one brake source in Brake 0 Disabled. | ||
| 1 = CPO1 as one brake source in Brake 0 Enabled. | ||
| [18] | CPO2BKEN | CPO2 Digital Output As Brake 0 Source Enable Control |
| 0 = CPO2 as one brake source in Brake 0 Disabled. | ||
| 1 = CPO2 as one brake source in Brake 0 Enabled. | ||
| [19] | LVDBKEN | Low-Level Detection Trigger PWM Brake Function 1 Enable Control |
| 0 = Brake Function 1 triggered by Low-level detection Disabled. | ||
| 1 = Brake Function 1 triggered by Low-level detection Enabled. | ||
| [24:29] | BKOD | PWM Brake Output Data Register |
| 0 = PWM output low when fault brake conditions asserted. | ||
| 1 = PWM output high when fault brake conditions asserted. | ||
| Note: Each bit controls the corresponding PWM channel. |
Definition at line 19411 of file NUC472_442.h.
| __IO uint32_t EPWM_T::BRKOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | BRKOUT | PWM Brake Output |
| When PWM Brake is asserted, the PWM0~5 output state before polarity control will follow PWM1 bit0~5 setting, respectively. | ||
| 0 = The PWMn output before polarity control is low when Brake is asserted. | ||
| 1 = The PWMn output before polarity control is high when Brake is asserted. | ||
| Note: n = 0~5. |
Definition at line 14233 of file NUC472_442.h.
| __IO uint32_t CAN_T::BRPE |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | BRPE | BRPE: Baud Rate Prescaler Extension |
| 0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. | ||
| The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used. |
Definition at line 1291 of file NUC472_442.h.
| __IO uint32_t CAN_T::BTIME |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | BRP | Baud Rate Prescaler |
| 0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. | ||
| The bit time is built up from a multiple of this quanta. | ||
| Valid values for the Baud Rate Prescaler are [ 0 ... 63 ]. | ||
| The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. | ||
| [6:7] | SJW | (Re)Synchronization Jump Width |
| 0x0-0x3: Valid programmed values are [0 ... 3]. | ||
| The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. | ||
| [8:11] | TSeg1 | Time Segment Before The Sample Point Minus Sync_Seg |
| 0x01-0x0F: valid values for TSeg1 are [1 ... 15]. | ||
| The actual interpretation by the hardware of this value is such that one more than the value programmed is used. | ||
| [12:14] | TSeg2 | Time Segment After Sample Point |
| 0x0-0x7: Valid values for TSeg2 are [0 ... 7]. | ||
| The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. |
Definition at line 1229 of file NUC472_442.h.
| __IO uint32_t USBD_T::BUSINTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SOFIEN | SOF Interrupt |
| This bit enables the SOF interrupt. | ||
| 0 = SOF interrupt Disabled. | ||
| 1 = SOF interrupt Enabled. | ||
| [1] | RSTIEN | Reset Status |
| This bit enables the USB-Reset interrupt. | ||
| 0 = USB-Reset interrupt Disabled. | ||
| 1 = USB-Reset interrupt Enabled. | ||
| [2] | RESUMEIEN | Resume |
| This bit enables the Resume interrupt. | ||
| 0 = Resume interrupt Disabled. | ||
| 1 = Resume interrupt Enabled. | ||
| [3] | SUSPENDIEN | Suspend Request |
| This bit enables the Suspend interrupt. | ||
| 0 = Suspend interrupt Disabled. | ||
| 1 = Suspend interrupt Enabled. | ||
| [4] | HISPDIEN | High-Speed Settle |
| This bit enables the high-speed settle interrupt. | ||
| 0 = High-speed settle interrupt Disabled. | ||
| 1 = High-speed settle interrupt Enabled. | ||
| [5] | DMADONEIEN | DMA Completion Interrupt |
| This bit enables the DMA completion interrupt | ||
| 0 = DMA completion interrupt Disabled. | ||
| 1 = DMA completion interrupt Enabled. | ||
| [6] | PHYCLKVLDIEN | Usable Clock Interrupt |
| This bit enables the usable clock interrupt. | ||
| 0 = Usable clock interrupt Disabled. | ||
| 1 = Usable clock interrupt Enabled. | ||
| [8] | VBUSDETIEN | VBUS Detection Interrupt Enable Control |
| This bit enables the VBUS floating detection interrupt. | ||
| 0 = VBUS floating detection interrupt Disabled. | ||
| 1 = VBUS floating detection interrupt Enabled. |
Definition at line 27490 of file NUC472_442.h.
| __IO uint32_t USBD_T::BUSINTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SOFIF | SOF Receive Control |
| This bit indicates when a start-of-frame packet has been received. | ||
| 0 = No start-of-frame packet has been received. | ||
| 1 = Start-of-frame packet has been received. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [1] | RSTIF | Reset Status |
| When set, this bit indicates that either the USB root port reset is end. | ||
| 0 = No USB root port reset is end. | ||
| 1 = USB root port reset is end. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [2] | RESUMEIF | Resume |
| When set, this bit indicates that a device resume has occurred. | ||
| 0 = No device resume has occurred. | ||
| 1 = Device resume has occurred. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [3] | SUSPENDIF | Suspend Request |
| This bit is set as default and it has to be cleared by writing '1' before the USB reset. | ||
| This bit is also set when a USB Suspend request is detected from the host. | ||
| 0 = No USB Suspend request is detected from the host. | ||
| 1= USB Suspend request is detected from the host. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [4] | HISPDIF | High-Speed Settle |
| 0 = No valid high-speed reset protocol is detected. | ||
| 1 = Valid high-speed reset protocol is over and the device has settled in high-speed. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [5] | DMADONEIF | DMA Completion Interrupt |
| 0 = No DMA transfer over. | ||
| 1 = DMA transfer is over. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [6] | PHYCLKVLDIF | Usable Clock Interrupt |
| 0 = Usable clock is not available. | ||
| 1 = Usable clock is available from the transceiver. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [8] | VBUSDETIF | VBUS Detection Interrupt Status |
| 0 = No VBUS is plug-in. | ||
| 1 = VBUS is plug-in. | ||
| Note: Write 1 to clear this bit to 0. |
Definition at line 27448 of file NUC472_442.h.
| __IO uint32_t RTC_T::CAL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | DAY | 1-Day Calendar Digit (0~9) |
| [4:5] | TENDAY | 10-Day Calendar Digit (0~3) |
| [8:11] | MON | 1-Month Calendar Digit (0~9) |
| [12] | TENMON | 10-Month Calendar Digit (0~1) |
| [16:19] | YEAR | 1-Year Calendar Digit (0~9) |
| [20:23] | TENYEAR | 10-Year Calendar Digit (0~9) |
Definition at line 20482 of file NUC472_442.h.
| __IO uint32_t RTC_T::CALM |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | DAY | 1-Day Calendar Digit of Alarm Setting (0~9) |
| [4:5] | TENDAY | 10-Day Calendar Digit of Alarm Setting (0~3) |
| [8:11] | MON | 1-Month Calendar Digit of Alarm Setting (0~9) |
| [12] | TENMON | 10-Month Calendar Digit of Alarm Setting (0~1) |
| [16:19] | YEAR | 1-Year Calendar Digit of Alarm Setting (0~9) |
| [20:23] | TENYEAR | 10-Year Calendar Digit of Alarm Setting (0~9) |
Definition at line 20547 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM0L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 11838 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM0M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 11822 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM10L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12178 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM10M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12162 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM11L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12212 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM11M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12196 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM12L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12246 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM12M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12230 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM13L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12280 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM13M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12264 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM14L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12314 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM14M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12298 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM15LSB |
| Bits | Field | Descriptions |
|---|---|---|
| [24:31] | OPERAND | Pause Parameter |
| In the PAUSE control frame, an OPERAND field defined and controls how much time the destination Ethernet MAC Controller paused. | ||
| The unit of the OPERAND is a slot time, the 512 bits time. |
Definition at line 12341 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM15MSB |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | OPCODE | OP Code Field of PAUSE Control Frame |
| In the PAUSE control frame, an op code field defined and is 0x0001. | ||
| [16:31] | LENGTH | LENGTH Field of PAUSE Control Frame |
| In the PAUSE control frame, a LENGTH field defined and is 0x8808. |
Definition at line 12328 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM1L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 11872 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM1M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 11856 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM2L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 11906 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM2M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 11890 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM3L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 11940 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM3M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 11924 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM4L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 11974 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM4M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 11958 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM5L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12008 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM5M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 11992 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM6L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12042 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM6M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12026 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM7L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12076 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM7M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12060 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM8L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12110 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM8M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12094 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM9L |
| Bits | Field | Descriptions |
|---|---|---|
| [16:23] | MACADDR0 | MAC Address Byte 0 |
| [24:31] | MACADDR1 | MAC Address Byte 1 |
| The CAMxL keeps the bit 15~0 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12144 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAM9M |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | MACADDR2 | MAC Address Byte 2 |
| [8:15] | MACADDR3 | MAC Address Byte 3 |
| [16:23] | MACADDR4 | MAC Address Byte 4 |
| [24:31] | MACADDR5 | MAC Address Byte 5 |
| The CAMxM keeps the bit 47~16 of MAC address. | ||
| The x can be the 0~14. | ||
| The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address. | ||
| For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. |
Definition at line 12128 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAMCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | AUP | Accept Unicast Packet |
| The AUP controls the unicast packet reception. | ||
| If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address. | ||
| 0 = EMAC receives packet depends on the CAM comparison result. | ||
| 1 = EMAC receives all unicast packets. | ||
| [1] | AMP | Accept Multicast Packet |
| The AMP controls the multicast packet reception. | ||
| If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address. | ||
| 0 = EMAC receives packet depends on the CAM comparison result. | ||
| 1 = EMAC receives all multicast packets. | ||
| [2] | ABP | Accept Broadcast Packet |
| The ABP controls the broadcast packet reception. | ||
| If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address. | ||
| 0 = EMAC receives packet depends on the CAM comparison result. | ||
| 1 = EMAC receives all broadcast packets. | ||
| [3] | COMPEN | Complement CAM Comparison Enable |
| The COMPEN controls the complement of the CAM comparison result. | ||
| If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address configured in CAM entry will be dropped. | ||
| And the incoming packet with destination MAC address does not configured in any CAM entry will be received. | ||
| 0 = The CAM comparison result does not complement. | ||
| 1 = The CAM comparison result complemented. | ||
| [4] | CMPEN | CAM Compare Enable |
| The CMPEN controls the enable of CAM comparison function for destination MAC address recognition. | ||
| If software wants to receive a packet with specific destination MAC address, configures the MAC address into CAM 12~0, then enables that CAM entry and set CMPEN to 1. | ||
| 0 = CAM comparison function for destination MAC address recognition disabled. | ||
| 1 = CAM comparison function for destination MAC address recognition enabled. |
Definition at line 11788 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CAMEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CAMxEN | CAM Entry X Enable Control |
| The CAMxEN controls the validation of CAM entry x. | ||
| The CAM entry 13, 14 and 15 are for PAUSE control frame transmission. | ||
| If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM entries all must be enabled first. | ||
| 0 = CAM entry x Disabled. | ||
| 1 = CAM entry x Enabled. |
Definition at line 11804 of file NUC472_442.h.
| __IO uint32_t RTC_T::CAMSK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | MDAY | Mask 1-Day Calendar Digit of Alarm Setting (0~9) |
| [1] | MTENDAY | Mask 10-Day Calendar Digit of Alarm Setting (0~3) |
| [2] | MMON | Mask 1-Month Calendar Digit of Alarm Setting (0~9) |
| [3] | MTENMON | Mask 10-Month Calendar Digit of Alarm Setting (0~1) |
| [4] | MYEAR | Mask 1-Year Calendar Digit of Alarm Setting (0~9) |
| [5] | MTENYEAR | Mask 10-Year Calendar Digit of Alarm Setting (0~9) |
Definition at line 20849 of file NUC472_442.h.
| __I uint32_t TIMER_T::CAP |
| Bits | Field | Descriptions |
|---|---|---|
| [0:23] | CAPDAT | Timer Capture Data Register |
| When CAPEN (TIMER_EXTCTL[3]) bit is set, CAPFUNCS (TIMER_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMER_EXTCTL[2:1]) setting, CAPIF (TIMER_EINTSTS[0]) will set to 1 and the current timer counter value (TIMER_CNT value) will be auto-loaded into this CAPDAT field. |
Definition at line 25018 of file NUC472_442.h.
| __IO uint32_t PWM_T::CAPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | CAPEN | Capture Function Enable Control |
| 0 = Capture function Disabled. RCAPDAT and FCAPDAT will not be updated. | ||
| 1 = Capture function Enabled. | ||
| Capture latched the PWM counter value and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). | ||
| Note: Each bit controls the corresponding PWM channel. | ||
| [8:13] | CAPINV | Capture Inverter Enable Control |
| 0 = Capture source inverter Disabled. | ||
| 1 = Capture source inverter Enabled. Reverse the input signal from GPIO | ||
| Note: Each bit controls the corresponding PWM channel. | ||
| [16:21] | RCRLDEN | Rising Latch Reload Enable Control |
| 0 = Rising latch reload counter Enabled. | ||
| 1 = Rising latch reload counter Enabled. | ||
| [24:29] | FCRLDEN | Falling Latch Reload Enable Control |
| 0 = Falling latch reload counter Disabled. | ||
| 1 = Falling latch | ||
| reload counter Enabled. |
Definition at line 19543 of file NUC472_442.h.
| __IO uint32_t PWM_T::CAPINEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | CAPINEN | Capture Input Enable Control |
| 0 = PWM Channel capture input path Disabled. | ||
| The input of PWM channel capture function is always regarded as 0. | ||
| 1 = PWM Channel capture input path Enabled. | ||
| The input of PWM channel capture function comes from correlative multifunction pin. | ||
| Note: Each bit controls the corresponding PWM channel. |
Definition at line 19559 of file NUC472_442.h.
| __I uint32_t PWM_T::CAPSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | CRIFOV | Rising Latch Interrupt Flag Overrun Status |
| This flag indicates if rising latch happened when the corresponding CRLIF is 1 | ||
| Note: This bit will be cleared automatically when user clear corresponding CRLIF. | ||
| [8:13] | FLIFOV | Falling Latch Interrupt Flag Overrun Status |
| This flag indicates if falling latch happened when the corresponding CFLIF is 1 | ||
| Note: This bit will be cleared automatically when user clear corresponding CFLIF. |
Definition at line 19575 of file NUC472_442.h.
| __IO uint32_t USBD_T::CEPBUFEND |
| Bits | Field | Descriptions |
|---|---|---|
| [0:11] | EADDR | Control-Endpoint End Address |
| This is the end-address of the RAM space allocated for the control-endpoint. |
Definition at line 27888 of file NUC472_442.h.
| __IO uint32_t USBD_T::CEPBUFSTART |
| Bits | Field | Descriptions |
|---|---|---|
| [0:11] | SADDR | Control-Endpoint Start Address |
| This is the start-address of the RAM space allocated for the control-endpoint. |
Definition at line 27876 of file NUC472_442.h.
| __IO uint32_t USBD_T::CEPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | NAKCLR | No Acknowledge Control |
| This bit plays a crucial role in any control transfer. | ||
| 0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase. | ||
| This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request. | ||
| 1 = This bit is set to one by the USB device controller, whenever a setup token is received. | ||
| The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit. | ||
| Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. | ||
| [1] | STALLEN | Stall Enable Control |
| When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter. | ||
| This is typically used for response to invalid/unsupported requests. | ||
| When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL. | ||
| It is automatically cleared on receipt of a next setup-token. | ||
| So, the local CPU need not write again to clear this bit. | ||
| 0 = No sends a stall handshake in response to any in or out token thereafter. | ||
| 1 = The control endpoint sends a stall handshake in response to any in or out token thereafter. | ||
| Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. | ||
| [2] | ZEROLEN | Zero Packet Length |
| This bit is valid for Auto Validation mode only. | ||
| 0 = No zero length packet to the host during Data stage to an IN token. | ||
| 1 = USB device controller can send a zero length packet to the host during Data stage to an IN token. | ||
| This bit gets cleared once the zero length data packet is sent. | ||
| So, the local CPU need not write again to clear this bit. | ||
| [3] | FLUSH | CEP-FLUSH Bit |
| 0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. | ||
| 1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. | ||
| This bit is self-cleaning. |
Definition at line 27622 of file NUC472_442.h.
| __IO uint32_t USBD_T::CEPDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DAT | Control-Endpoint Data Buffer |
| Control endpoint data buffer for the buffer transaction (read or write). | ||
| Note: Only word or byte access are supported. |
Definition at line 27572 of file NUC472_442.h.
| __IO uint32_t { ... } ::CEPDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DAT | Control-Endpoint Data Buffer |
| Control endpoint data buffer for the buffer transaction (read or write). | ||
| Note: Only word or byte access are supported. |
Definition at line 27572 of file NUC472_442.h.
| __IO uint8_t { ... } ::CEPDAT_BYTE |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | DAT | Control-Endpoint Data Buffer |
| Control endpoint data buffer for the buffer transaction (read or write). | ||
| Note: Only word or byte access are supported. |
Definition at line 27584 of file NUC472_442.h.
| __IO uint8_t USBD_T::CEPDAT_BYTE |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | DAT | Control-Endpoint Data Buffer |
| Control endpoint data buffer for the buffer transaction (read or write). | ||
| Note: Only word or byte access are supported. |
Definition at line 27584 of file NUC472_442.h.
| __I uint32_t USBD_T::CEPDATCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | DATCNT | Control-Endpoint Data Count |
| The USB device controller maintains the count of the data of control-endpoint. |
Definition at line 27773 of file NUC472_442.h.
| __IO uint32_t USBD_T::CEPINTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SETUPTKIEN | Setup Token Interrupt Enable Control |
| 0 = The SETUP token interrupt in Control Endpoint Disabled. | ||
| 1 = The SETUP token interrupt in Control Endpoint Enabled. | ||
| [1] | SETUPPKIEN | Setup Packet Interrupt |
| 0 = The SETUP packet interrupt in Control Endpoint Disabled. | ||
| 1 = The SETUP packet interrupt in Control Endpoint Enabled. | ||
| [2] | OUTTKIEN | Out Token Interrupt |
| 0 = The OUT token interrupt in Control Endpoint Disabled. | ||
| 1 = The OUT token interrupt in Control Endpoint Enabled. | ||
| [3] | INTKIEN | In Token Interrupt |
| 0 = The IN token interrupt in Control Endpoint Disabled. | ||
| 1 = The IN token interrupt in Control Endpoint Enabled. | ||
| [4] | PINGIEN | Ping Token Interrupt |
| 0 = The ping token interrupt in Control Endpoint Disabled. | ||
| 1 = The ping token interrupt Control Endpoint Enabled. | ||
| [5] | TXPKIEN | Data Packet Transmitted Interrupt |
| 0 = The data packet transmitted interrupt in Control Endpoint Disabled. | ||
| 1 = The data packet transmitted interrupt in Control Endpoint Enabled. | ||
| [6] | RXPKIEN | Data Packet Received Interrupt |
| 0 = The data received interrupt in Control Endpoint Disabled. | ||
| 1 = The data received interrupt in Control Endpoint Enabled. | ||
| [7] | NAKIEN | NAK Sent Interrupt |
| 0 = The NAK sent interrupt in Control Endpoint Disabled. | ||
| 1 = The NAK sent interrupt in Control Endpoint Enabled. | ||
| [8] | STALLIEN | STALL Sent Interrupt |
| 0 = The STALL sent interrupt in Control Endpoint Disabled. | ||
| 1 = The STALL sent interrupt in Control Endpoint Enabled. | ||
| [9] | ERRIEN | USB Error Interrupt |
| 0 = The USB Error interrupt in Control Endpoint Disabled. | ||
| 1 = The USB Error interrupt in Control Endpoint Enabled. | ||
| [10] | STSDONEIEN | Status Completion Interrupt |
| 0 = The Status Completion interrupt in Control Endpoint Disabled. | ||
| 1 = The Status Completion interrupt in Control Endpoint Enabled. | ||
| [11] | BUFFULLIEN | Buffer Full Interrupt |
| 0 = The buffer full interrupt in Control Endpoint Disabled. | ||
| 1 = The buffer full interrupt in Control Endpoint Enabled. | ||
| [12] | BUFEMPTYIEN | Buffer Empty Interrupt |
| 0 = The buffer empty interrupt in Control Endpoint Disabled. | ||
| 1= The buffer empty interrupt in Control Endpoint Enabled. |
Definition at line 27671 of file NUC472_442.h.
| __IO uint32_t USBD_T::CEPINTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SETUPTKIF | Setup Token Interrupt |
| 0 = Not a Setup token is received. | ||
| 1 = A Setup token is received. Writing 1 clears this status bit | ||
| Note: Write 1 to clear this bit to 0. | ||
| [1] | SETUPPKIF | Setup Packet Interrupt |
| This bit must be cleared (by writing 1) before the next setup packet can be received. | ||
| If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer. | ||
| 0 = Not a Setup packet has been received from the host. | ||
| 1 = A Setup packet has been received from the host. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [2] | OUTTKIF | Out Token Interrupt |
| 0 = The control-endpoint does not received an OUT token from the host. | ||
| 1 = The control-endpoint receives an OUT token from the host. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [3] | INTKIF | In Token Interrupt |
| 0 = The control-endpoint does not received an IN token from the host. | ||
| 1 = The control-endpoint receives an IN token from the host. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [4] | PINGIF | Ping Token Interrupt |
| 0 = The control-endpoint does not received a ping token from the host. | ||
| 1 = The control-endpoint receives a ping token from the host. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [5] | TXPKIF | Data Packet Transmitted Interrupt |
| 0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. | ||
| 1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [6] | RXPKIF | Data Packet Received Interrupt |
| 0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. | ||
| 1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [7] | NAKIF | NAK Sent Interrupt |
| 0 = Not a NAK-token is sent in response to an IN/OUT token. | ||
| 1 = A NAK-token is sent in response to an IN/OUT token. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [8] | STALLIF | STALL Sent Interrupt |
| 0 = Not a stall-token is sent in response to an IN/OUT token. | ||
| 1 = A stall-token is sent in response to an IN/OUT token. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [9] | ERRIF | USB Error Interrupt |
| 0 = No error had occurred during the transaction. | ||
| 1 = An error had occurred during the transaction. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [10] | STSDONEIF | Status Completion Interrupt |
| 0 = Not a USB transaction has completed successfully. | ||
| 1 = The status stage of a USB transaction has completed successfully. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [11] | BUFFULLIF | Buffer Full Interrupt |
| 0 = The control-endpoint buffer is not full. | ||
| 1 = The control-endpoint buffer is full. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [12] | BUFEMPTYIF | Buffer Empty Interrupt |
| 0 = The control-endpoint buffer is not empty. | ||
| 1 = The control-endpoint buffer is empty. | ||
| Note: Write 1 to clear this bit to 0. |
Definition at line 27735 of file NUC472_442.h.
| __I uint32_t USBD_T::CEPRXCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | RXCNT | Out-Transfer Data Count |
| The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer. |
Definition at line 27761 of file NUC472_442.h.
| __IO uint32_t USBD_T::CEPTXCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | TXCNT | In-Transfer Data Count |
| There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register. | ||
| When zero is written into this field, a zero length packet is sent to the host. | ||
| When the count written in the register is more than the MPS, the data sent will be of only MPS. |
Definition at line 27749 of file NUC472_442.h.
| __IO uint32_t PDMA_T::CHCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | CHEN | PDMA Channel Enable Control Bit[X] |
| Set this bit to 1 to enable PDMA[x] operation. | ||
| 0 = PDMA channel [x] Disabled. | ||
| 1 = PDMA channel [x] Enabled. | ||
| Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer. | ||
| Note2: Software reset (writing 0xFFFF_FFF to PDMA_STOP register) will clear this bit. | ||
| Note3: If each channel is not set as enabled, each channel cannot be active. |
Definition at line 18248 of file NUC472_442.h.
| __I uint32_t CRC_T::CHECKSUM |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CHECKSUM | CRC Checksum Bits |
| This field indicates the CRC checksum. |
Definition at line 4071 of file NUC472_442.h.
| __IO uint32_t ADC_T::CHEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0:11] | CHEN | Analog Input Channel Enable Control |
| Set CHEN (ADC_CHEN[11:0]) to enable the corresponding analog input channel (ADC0_CH1 ~ ADC0_CH11). | ||
| If DIFFEN bit is set to 1, only the even number channels need to be enabled. | ||
| 0 = ADC input channel Disabled. | ||
| 1 = ADC input channel Enabled. | ||
| [16] | ADTSEN | Internal Temperature Sensor Selection |
| 0 = Internal temperature sensor is not selected to be the analog input source of ADC. | ||
| 1 = Internal temperature sensor is selected to be the analog input source of ADC. | ||
| ADC can only work at Single mode when software selects the temperature sensor voltage as the analog input source of ADC | ||
| [17] | ADBGEN | Internal Band-Gap Selection |
| 0 = Internal band-gap is not selected to be the analog input source of ADC. | ||
| 1 = Internal band-gap is selected to be the analog input source of ADC. | ||
| ADC can only work at Single mode when software selects the band-gap voltage as the analog input source of ADC |
Definition at line 493 of file NUC472_442.h.
| __IO uint32_t CLK_T::CLKDCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SYSFDEN | System Clock Detector Enable Control |
| 0 = system clock fail interrupt disabled. | ||
| 1 = system clock fail interrupt enabled. | ||
| [1] | SYSFIEN | System Clock Detector Interrupt Enable Control |
| 0 = system clock fail interrupt disabled. | ||
| 1 = system clock fail interrupt enabled. | ||
| [2] | SYSFIF | System Clock Detect Fail Flag |
| 0 = System clock normal. | ||
| 1 = System clock abnormal (write " 1" to clear). | ||
| [8] | IRCDEN | Internal RC Clock Detector Enable Control |
| 0 = IRC clock fail interrupt disabled. | ||
| 1 = IRC clock fail interrupt enabled. | ||
| [9] | IRCFIEN | Internal RC Clock Detector Interrupt Enable Control |
| 0 = IRC clock fail interrupt disabled. | ||
| 1 = IRC clock fail interrupt enabled. | ||
| [10] | IRCFIF | Internal RC Clock Fail Flag |
| 0 = IRC clock normal. | ||
| 1 = IRC abnormal (write "1" to clear) . |
Definition at line 3538 of file NUC472_442.h.
| __IO uint32_t I2C_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | DIVIDER | I2C Clock Divided Bits |
| The I2C clock rate bits: Data Baud Rate of I2C = (system clock) / (4x (I2CLK+1)). | ||
| Note: The minimum value of I2CLK is 4. |
Definition at line 16910 of file NUC472_442.h.
| __IO uint32_t I2S_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | MCLKDIV | Master Clock Divider |
| If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. | ||
| If MCLKDIV is set to 0, MCLK is the same as external clock input. | ||
| For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1. | ||
| F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ). | ||
| F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ). | ||
| Note: F_MCLK is the frequency of MCLK, and F_i2SCLK is the frequency of the I2S_CLK | ||
| [8:16] | BCLKDIV | Bit Clock Divider |
| If I2S operates in Master mode, bit clock is provided by the NuMicro(TM) NUC442/NUC472 series. | ||
| Software can program these bits to generate sampling rate clock frequency. | ||
| F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)). | ||
| Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK |
Definition at line 17302 of file NUC472_442.h.
| __IO uint32_t PWM_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [0:2] | CLKDIV0 | PWM Counter Base-Clock Divide For PWMx_CH0 |
| (Table is the same as CLKDIV5) | ||
| [4:6] | CLKDIV1 | PWM Counter Base-Clock Divide For PWMx_CH1 |
| (Table is the same as CLKDIV5) | ||
| [8:10] | CLKDIV2 | PWM Counter Base-Clock Divide For PWMx_CH2 |
| (Table is the same as CLKDIV5) | ||
| [12:14] | CLKDIV3 | PWM Counter Base-Clock Divide For PWMx_CH3 |
| (Table is the same as CLKDIV5) | ||
| [16:18] | CLKDIV4 | PWM Counter Base-Clock Divide For PWMx_CH4 |
| (Table is the same as CLKDIV5) | ||
| [20:22] | CLKDIV5 | PWM Counter Base-Clock Divide For PWMx_CH5 |
| The base-clock of PWM counter is decided by clock pre-scalar and clock divider. | ||
| Each PWM counter has independent clock divider control register and the divided value is listed in the table below:. | ||
| 000 = 2. | ||
| 001 = 4. | ||
| 010 = 8. | ||
| 011 = 16. | ||
| 100 = 1. |
Definition at line 19096 of file NUC472_442.h.
| __IO uint32_t SPI_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | DIVIDER | Clock Divider Register |
| The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. | ||
| The frequency is obtained according to the following equation. | ||
| Note1: is the peripheral clock source, which is defined in the clock control, CLK_SEL1 register. | ||
| Note2: is the peripheral clock which is used to drive the SPI logic unit. |
Definition at line 22789 of file NUC472_442.h.
| __IO uint32_t CLK_T::CLKDIV0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | HCLKDIV | HCLK Clock Divide Number From HCLK Clock Source |
| HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). | ||
| [4:7] | USBHDIV | USB Host Clock Divide Number From PLL Clock |
| USB Host clock frequency = (PLL frequency) / (USBHDIV + 1). | ||
| [8:11] | UARTDIV | UART Clock Divide Number From UART Clock Source |
| UART clock frequency = (UART clock source frequency) / (UARTDIV + 1). | ||
| [16:23] | ADCDIV | ADC Clock Divide Number From ADC Clock Source |
| ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1). | ||
| [24:31] | SDHDIV | SDHOST Clock Divide Number From SDHOST Clock Source |
| SDHOST clock frequency = (SDHOST clock source frequency) / (SDHDIV + 1). |
Definition at line 3334 of file NUC472_442.h.
| __IO uint32_t CLK_T::CLKDIV1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | SC0DIV | SC0 Clock Divide Number From SC0 Clock Source |
| SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV+ 1). | ||
| [8:15] | SC1DIV | SC1 Clock Divide Number From SC1 Clock Source |
| SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1). | ||
| [16:23] | SC2DIV | SC2 Clock Divide Number From SC2 Clock Source |
| SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1). | ||
| [24:31] | SC3DIV | SC3 Clock Divide Number From SC3 Clock Source |
| SC3 clock frequency = (SC3 clock source frequency ) / (SC3DIV+ 1). |
Definition at line 3352 of file NUC472_442.h.
| __IO uint32_t CLK_T::CLKDIV2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | SC4DIV | SC4 Clock Divide Number From SC4 Clock Source |
| SC4 clock frequency = (SC4 clock source frequency ) / (SC4DIV + 1). | ||
| [8:15] | SC5DIV | SC5 Clock Divide Number From SC5 Clock Source |
| SC5 clock frequency = (SC5 clock source frequency ) / (SC5DIV + 1). |
Definition at line 3366 of file NUC472_442.h.
| __IO uint32_t CLK_T::CLKDIV3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | CAPDIV | Image Capture Sensor Clock Divide Number From ICAP Clock Source |
| Image sensor clock frequency = (ICAP clock source frequency) / (ICAPDIV + 1). | ||
| [8:15] | VSENSEDIV | Video Pixel Clock Divide Number From ICAP Clock Source |
| Video pixel clock frequency = (ICAP clock source frequency) / (VSENSEDIV + 1). | ||
| [16:23] | EMACDIV | Ethernet Clock Divide Number Form HCLK (NUC472 Only) |
| EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1). |
Definition at line 3382 of file NUC472_442.h.
| __IO uint32_t RTC_T::CLKFMT |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | 24HEN | 24-Hour / 12-Hour Time Scale Selection |
| Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale | ||
| 0 = 12-hour time scale with AM and PM indication selected. | ||
| 1 = 24-hour time scale selected. |
Definition at line 20496 of file NUC472_442.h.
| __IO uint32_t CLK_T::CLKOCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | FSEL | Divider Output Frequency Selection |
| The formula of output frequency is: | ||
| Fout = Fin/2(N+1). | ||
| Fin is the input clock frequency. | ||
| Fout is the frequency of divider output clock. | ||
| N is the 4-bit value of FSEL[3:0]. | ||
| [4] | CLKOEN | Clock Output Enable Control |
| 0 = Clock Output disabled. | ||
| 1 = Clock Output enabled. | ||
| [5] | DIV1EN | Frequency Divider 1 Enable Control |
| 0 = Divider output frequency is dependent on FSEL value when FDIVEN is enabled. | ||
| 1 = Divider output frequency is input clock frequency. |
Definition at line 3506 of file NUC472_442.h.