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M480 BSP V3.05.005
The Board Support Package for M480 Series
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#include <bpwm_reg.h>
Data Fields | |
| __IO uint32_t | CTL0 |
| __IO uint32_t | CTL1 |
| __IO uint32_t | CLKSRC |
| __IO uint32_t | CLKPSC |
| __IO uint32_t | CNTEN |
| __IO uint32_t | CNTCLR |
| __IO uint32_t | PERIOD |
| __IO uint32_t | CMPDAT [6] |
| __I uint32_t | CNT |
| __IO uint32_t | WGCTL0 |
| __IO uint32_t | WGCTL1 |
| __IO uint32_t | MSKEN |
| __IO uint32_t | MSK |
| __IO uint32_t | POLCTL |
| __IO uint32_t | POEN |
| __IO uint32_t | INTEN |
| __IO uint32_t | INTSTS |
| __IO uint32_t | EADCTS0 |
| __IO uint32_t | EADCTS1 |
| __IO uint32_t | SSCTL |
| __O uint32_t | SSTRG |
| __IO uint32_t | STATUS |
| __IO uint32_t | CAPINEN |
| __IO uint32_t | CAPCTL |
| __I uint32_t | CAPSTS |
| BCAPDAT_T | CAPDAT [6] |
| __IO uint32_t | CAPIEN |
| __IO uint32_t | CAPIF |
| __I uint32_t | PBUF |
| __I uint32_t | CMPBUF [6] |
Definition at line 71 of file bpwm_reg.h.
| BPWM_T::CAPCTL |
[0x0204] BPWM Capture Control Register
| Bits | Field | Descriptions |
| [0] | CAPEN0 | Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1 = Capture function Enabled Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
| [1] | CAPEN1 | Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1 = Capture function Enabled Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
| [2] | CAPEN2 | Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1 = Capture function Enabled Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
| [3] | CAPEN3 | Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1 = Capture function Enabled Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
| [4] | CAPEN4 | Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1 = Capture function Enabled Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
| [5] | CAPEN5 | Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1 = Capture function Enabled Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
| [8] | CAPINV0 | Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture source inverter Disabled. 1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
| [9] | CAPINV1 | Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture source inverter Disabled. 1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
| [10] | CAPINV2 | Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture source inverter Disabled. 1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
| [11] | CAPINV3 | Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture source inverter Disabled. 1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
| [12] | CAPINV4 | Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture source inverter Disabled. 1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
| [13] | CAPINV5 | Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture source inverter Disabled. 1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
| [16] | RCRLDEN0 | Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Rising capture reload counter Disabled. 1 = Rising capture reload counter Enabled. |
| [17] | RCRLDEN1 | Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Rising capture reload counter Disabled. 1 = Rising capture reload counter Enabled. |
| [18] | RCRLDEN2 | Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Rising capture reload counter Disabled. 1 = Rising capture reload counter Enabled. |
| [19] | RCRLDEN3 | Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Rising capture reload counter Disabled. 1 = Rising capture reload counter Enabled. |
| [20] | RCRLDEN4 | Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Rising capture reload counter Disabled. 1 = Rising capture reload counter Enabled. |
| [21] | RCRLDEN5 | Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Rising capture reload counter Disabled. 1 = Rising capture reload counter Enabled. |
| [24] | FCRLDEN0 | Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Falling capture reload counter Disabled. 1 = Falling capture reload counter Enabled. |
| [25] | FCRLDEN1 | Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Falling capture reload counter Disabled. 1 = Falling capture reload counter Enabled. |
| [26] | FCRLDEN2 | Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Falling capture reload counter Disabled. 1 = Falling capture reload counter Enabled. |
| [27] | FCRLDEN3 | Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Falling capture reload counter Disabled. 1 = Falling capture reload counter Enabled. |
| [28] | FCRLDEN4 | Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Falling capture reload counter Disabled. 1 = Falling capture reload counter Enabled. |
| [29] | FCRLDEN5 | Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Falling capture reload counter Disabled. 1 = Falling capture reload counter Enabled. |
Definition at line 2442 of file bpwm_reg.h.
| BCAPDAT_T BPWM_T::CAPDAT[6] |
[0x020C] BPWM Rising and Falling Capture Data Register 0~5
Definition at line 2444 of file bpwm_reg.h.
| BPWM_T::CAPIEN |
[0x0250] BPWM Capture Interrupt Enable Register
| Bits | Field | Descriptions |
| [5:0] | CAPRIENn | BPWM Capture Rising Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture rising edge latch interrupt Disabled. 1 = Capture rising edge latch interrupt Enabled. |
| [13:8] | CAPFIENn | BPWM Capture Falling Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Capture falling edge latch interrupt Disabled. 1 = Capture falling edge latch interrupt Enabled. |
Definition at line 2448 of file bpwm_reg.h.
| BPWM_T::CAPIF |
[0x0254] BPWM Capture Interrupt Flag Register
| Bits | Field | Descriptions |
| [0] | CAPRIF0 | BPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture rising latch condition happened. 1 = Capture rising latch condition happened, this flag will be set to high. |
| [1] | CAPRIF1 | BPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture rising latch condition happened. 1 = Capture rising latch condition happened, this flag will be set to high. |
| [2] | CAPRIF2 | BPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture rising latch condition happened. 1 = Capture rising latch condition happened, this flag will be set to high. |
| [3] | CAPRIF3 | BPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture rising latch condition happened. 1 = Capture rising latch condition happened, this flag will be set to high. |
| [4] | CAPRIF4 | BPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture rising latch condition happened. 1 = Capture rising latch condition happened, this flag will be set to high. |
| [5] | CAPRIF5 | BPWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture rising latch condition happened. 1 = Capture rising latch condition happened, this flag will be set to high. |
| [8] | CAPFIF0 | BPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture falling latch condition happened. 1 = Capture falling latch condition happened, this flag will be set to high. |
| [9] | CAPFIF1 | BPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture falling latch condition happened. 1 = Capture falling latch condition happened, this flag will be set to high. |
| [10] | CAPFIF2 | BPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture falling latch condition happened. 1 = Capture falling latch condition happened, this flag will be set to high. |
| [11] | CAPFIF3 | BPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture falling latch condition happened. 1 = Capture falling latch condition happened, this flag will be set to high. |
| [12] | CAPFIF4 | BPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture falling latch condition happened. 1 = Capture falling latch condition happened, this flag will be set to high. |
| [13] | CAPFIF5 | BPWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 0 = No capture falling latch condition happened. 1 = Capture falling latch condition happened, this flag will be set to high. |
Definition at line 2449 of file bpwm_reg.h.
| BPWM_T::CAPINEN |
[0x0200] BPWM Capture Input Enable Register
| Bits | Field | Descriptions |
| [0] | CAPINEN0 | Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM Channel capture input path Disabled The input of BPWM channel capture function is always regarded as 0. 1 = BPWM Channel capture input path Enabled The input of BPWM channel capture function comes from correlative multifunction pin. |
| [1] | CAPINEN1 | Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM Channel capture input path Disabled The input of BPWM channel capture function is always regarded as 0. 1 = BPWM Channel capture input path Enabled The input of BPWM channel capture function comes from correlative multifunction pin. |
| [2] | CAPINEN2 | Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM Channel capture input path Disabled The input of BPWM channel capture function is always regarded as 0. 1 = BPWM Channel capture input path Enabled The input of BPWM channel capture function comes from correlative multifunction pin. |
| [3] | CAPINEN3 | Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM Channel capture input path Disabled The input of BPWM channel capture function is always regarded as 0. 1 = BPWM Channel capture input path Enabled The input of BPWM channel capture function comes from correlative multifunction pin. |
| [4] | CAPINEN4 | Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM Channel capture input path Disabled The input of BPWM channel capture function is always regarded as 0. 1 = BPWM Channel capture input path Enabled The input of BPWM channel capture function comes from correlative multifunction pin. |
| [5] | CAPINEN5 | Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM Channel capture input path Disabled The input of BPWM channel capture function is always regarded as 0. 1 = BPWM Channel capture input path Enabled The input of BPWM channel capture function comes from correlative multifunction pin. |
Definition at line 2441 of file bpwm_reg.h.
| BPWM_T::CAPSTS |
[0x0208] BPWM Capture Status Register
| Bits | Field | Descriptions |
| [0] | CRIFOV0 | Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPRIF. |
| [1] | CRIFOV1 | Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPRIF. |
| [2] | CRIFOV2 | Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPRIF. |
| [3] | CRIFOV3 | Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPRIF. |
| [4] | CRIFOV4 | Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPRIF. |
| [5] | CRIFOV5 | Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPRIF. |
| [8] | CFIFOV0 | Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPFIF. |
| [9] | CFIFOV1 | Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPFIF. |
| [10] | CFIFOV2 | Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPFIF. |
| [11] | CFIFOV3 | Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPFIF. |
| [12] | CFIFOV4 | Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPFIF. |
| [13] | CFIFOV5 | Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1 Each bit n controls the corresponding BPWM channel n. Note: This bit will be cleared automatically when user clear corresponding CAPFIF. |
Definition at line 2443 of file bpwm_reg.h.
| BPWM_T::CLKPSC |
[0x0014] BPWM Clock Prescale Register
| Bits | Field | Descriptions |
| [11:0] | CLKPSC | BPWM Counter Clock Prescale
The clock of BPWM counter is decided by clock prescaler Each BPWM pair share one BPWM counter clock prescaler The clock of BPWM counter is divided by (CLKPSC+ 1) |
Definition at line 2386 of file bpwm_reg.h.
| BPWM_T::CLKSRC |
[0x0010] BPWM Clock Source Register
| Bits | Field | Descriptions |
| [2:0] | ECLKSRC0 | BPWM_CH01 External Clock Source Select
000 = BPWMx_CLK, x denotes 0 or 1. 001 = TIMER0 overflow. 010 = TIMER1 overflow. 011 = TIMER2 overflow. 100 = TIMER3 overflow. Others = Reserved. |
Definition at line 2385 of file bpwm_reg.h.
| BPWM_T::CMPBUF[6] |
[0x031c] BPWM CMPDAT 0~5 Buffer
| Bits | Field | Descriptions |
| [15:0] | CMPBUF | BPWM Comparator Buffer (Read Only)
Used as CMP active register. |
Definition at line 2457 of file bpwm_reg.h.
| BPWM_T::CMPDAT[6] |
[0x0050] BPWM Comparator Register 0~5
| Bits | Field | Descriptions |
| [15:0] | CMPDAT | BPWM Comparator Register
CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC. In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. |
Definition at line 2399 of file bpwm_reg.h.
| BPWM_T::CNT |
[0x0090] BPWM Counter Register
| Bits | Field | Descriptions |
| [15:0] | CNT | BPWM Data Register (Read Only)
User can monitor CNTR to know the current value in 16-bit period counter. |
| [16] | DIRF | BPWM Direction Indicator Flag (Read Only)
0 = Counter is Down count. 1 = Counter is UP count. |
Definition at line 2403 of file bpwm_reg.h.
| BPWM_T::CNTCLR |
[0x0024] BPWM Clear Counter Register
| Bits | Field | Descriptions |
| [0] | CNTCLR0 | Clear BPWM Counter Control Bit 0
It is automatically cleared by hardware. 0 = No effect. 1 = Clear 16-bit BPWM counter to 0000H. |
Definition at line 2391 of file bpwm_reg.h.
| BPWM_T::CNTEN |
[0x0020] BPWM Counter Enable Register
| Bits | Field | Descriptions |
| [0] | CNTEN0 | BPWM Counter 0 Enable Bit
0 = BPWM Counter and clock prescaler stop running. 1 = BPWM Counter and clock prescaler start running. |
Definition at line 2390 of file bpwm_reg.h.
| BPWM_T::CTL0 |
[0x0000] BPWM Control Register 0
| Bits | Field | Descriptions |
| [0] | CTRLD0 | Center Re-load
Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the center point of a period |
| [1] | CTRLD1 | Center Re-load
Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the center point of a period |
| [2] | CTRLD2 | Center Re-load
Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the center point of a period |
| [3] | CTRLD3 | Center Re-load
Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the center point of a period |
| [4] | CTRLD4 | Center Re-load
Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the center point of a period |
| [5] | CTRLD5 | Center Re-load
Each bit n controls the corresponding BPWM channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the center point of a period |
| [16] | IMMLDEN0 | Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n. 0 = PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. |
| [17] | IMMLDEN1 | Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n. 0 = PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. |
| [18] | IMMLDEN2 | Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n. 0 = PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. |
| [19] | IMMLDEN3 | Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n. 0 = PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. |
| [20] | IMMLDEN4 | Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n. 0 = PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. |
| [21] | IMMLDEN5 | Immediately Load Enable Bit(S)
Each bit n controls the corresponding BPWM channel n. 0 = PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. |
| [30] | DBGHALT | ICE Debug Mode Counter Halt (Write Protect)
If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. 0 = ICE debug mode counter halt Disabled. 1 = ICE debug mode counter halt Enabled. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [31] | DBGTRIOFF | ICE Debug Mode Acknowledge Disable (Write Protect)
0 = ICE debug mode acknowledgement effects BPWM output. BPWM pin will be forced as tri-state while ICE debug mode acknowledged. 1 = ICE debug mode acknowledgement Disabled. BPWM pin will keep output no matter ICE debug mode acknowledged or not. Note: This register is write protected. Refer toSYS_REGLCTL register. |
Definition at line 2380 of file bpwm_reg.h.
| BPWM_T::CTL1 |
[0x0004] BPWM Control Register 1
| Bits | Field | Descriptions |
| [1:0] | CNTTYPE0 | BPWM Counter Behavior Type 0
Each bit n controls corresponding BPWM channel n. 00 = Up counter type (supports in capture mode). 01 = Down count type (supports in capture mode). 10 = Up-down counter type. 11 = Reserved. |
Definition at line 2381 of file bpwm_reg.h.
| BPWM_T::EADCTS0 |
[0x00f8] BPWM Trigger EADC Source Select Register 0
| Bits | Field | Descriptions |
| [3:0] | TRGSEL0 | BPWM_CH0 Trigger EADC Source Select
0000 = BPWM_CH0 zero point. 0001 = BPWM_CH0 period point. 0010 = BPWM_CH0 zero or period point. 0011 = BPWM_CH0 up-count CMPDAT point. 0100 = BPWM_CH0 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = BPWM_CH1 up-count CMPDAT point. 1001 = BPWM_CH1 down-count CMPDAT point. Others reserved |
| [7] | TRGEN0 | BPWM_CH0 Trigger EADC Enable Bit
|
| [11:8] | TRGSEL1 | BPWM_CH1 Trigger EADC Source Select
0000 = BPWM_CH0 zero point. 0001 = BPWM_CH0 period point. 0010 = BPWM_CH0 zero or period point. 0011 = BPWM_CH0 up-count CMPDAT point. 0100 = BPWM_CH0 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = BPWM_CH1 up-count CMPDAT point. 1001 = BPWM_CH1 down-count CMPDAT point. Others reserved |
| [15] | TRGEN1 | BPWM_CH1 Trigger EADC Enable Bit
|
| [19:16] | TRGSEL2 | BPWM_CH2 Trigger EADC Source Select
0000 = BPWM_CH2 zero point. 0001 = BPWM_CH2 period point. 0010 = BPWM_CH2 zero or period point. 0011 = BPWM_CH2 up-count CMPDAT point. 0100 = BPWM_CH2 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = BPWM_CH3 up-count CMPDAT point. 1001 = BPWM_CH3 down-count CMPDAT point. Others reserved |
| [23] | TRGEN2 | BPWM_CH2 Trigger EADC Enable Bit
|
| [27:24] | TRGSEL3 | BPWM_CH3 Trigger EADC Source Select
0000 = BPWM_CH2 zero point. 0001 = BPWM_CH2 period point. 0010 = BPWM_CH2 zero or period point. 0011 = BPWM_CH2 up-count CMPDAT point. 0100 = BPWM_CH2 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = BPWM_CH3 up-count CMPDAT point. 1001 = BPWM_CH3 down-count CMPDAT point. Others reserved. |
| [31] | TRGEN3 | BPWM_CH3 Trigger EADC Enable Bit
|
Definition at line 2427 of file bpwm_reg.h.
| BPWM_T::EADCTS1 |
[0x00fc] BPWM Trigger EADC Source Select Register 1
| Bits | Field | Descriptions |
| [3:0] | TRGSEL4 | BPWM_CH4 Trigger EADC Source Select
0000 = BPWM_CH4 zero point. 0001 = BPWM_CH4 period point. 0010 = BPWM_CH4 zero or period point. 0011 = BPWM_CH4 up-count CMPDAT point. 0100 = BPWM_CH4 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = BPWM_CH5 up-count CMPDAT point. 1001 = BPWM_CH5 down-count CMPDAT point. Others reserved |
| [7] | TRGEN4 | BPWM_CH4 Trigger EADC Enable Bit
|
| [11:8] | TRGSEL5 | BPWM_CH5 Trigger EADC Source Select
0000 = BPWM_CH4 zero point. 0001 = BPWM_CH4 period point. 0010 = BPWM_CH4 zero or period point. 0011 = BPWM_CH4 up-count CMPDAT point. 0100 = BPWM_CH4 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = BPWM_CH5 up-count CMPDAT point. 1001 = BPWM_CH5 down-count CMPDAT point. Others reserved |
| [15] | TRGEN5 | BPWM_CH5 Trigger EADC Enable Bit
|
Definition at line 2428 of file bpwm_reg.h.
| BPWM_T::INTEN |
[0x00e0] BPWM Interrupt Enable Register
| Bits | Field | Descriptions |
| [0] | ZIEN0 | BPWM Zero Point Interrupt 0 Enable Bit
0 = Zero point interrupt Disabled. 1 = Zero point interrupt Enabled. |
| [8] | PIEN0 | BPWM Period Point Interrupt 0 Enable Bit
0 = Period point interrupt Disabled. 1 = Period point interrupt Enabled. Note: When up-down counter type period point means center point. |
| [16] | CMPUIEN0 | BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare up count interrupt Disabled. 1 = Compare up count interrupt Enabled. |
| [17] | CMPUIEN1 | BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare up count interrupt Disabled. 1 = Compare up count interrupt Enabled. |
| [18] | CMPUIEN2 | BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare up count interrupt Disabled. 1 = Compare up count interrupt Enabled. |
| [19] | CMPUIEN3 | BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare up count interrupt Disabled. 1 = Compare up count interrupt Enabled. |
| [20] | CMPUIEN4 | BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare up count interrupt Disabled. 1 = Compare up count interrupt Enabled. |
| [21] | CMPUIEN5 | BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare up count interrupt Disabled. 1 = Compare up count interrupt Enabled. |
| [24] | CMPDIEN0 | BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare down count interrupt Disabled. 1 = Compare down count interrupt Enabled. |
| [25] | CMPDIEN1 | BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare down count interrupt Disabled. 1 = Compare down count interrupt Enabled. |
| [26] | CMPDIEN2 | BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare down count interrupt Disabled. 1 = Compare down count interrupt Enabled. |
| [27] | CMPDIEN3 | BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare down count interrupt Disabled. 1 = Compare down count interrupt Enabled. |
| [28] | CMPDIEN4 | BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare down count interrupt Disabled. 1 = Compare down count interrupt Enabled. |
| [29] | CMPDIEN5 | BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = Compare down count interrupt Disabled. 1 = Compare down count interrupt Enabled. |
Definition at line 2419 of file bpwm_reg.h.
| BPWM_T::INTSTS |
[0x00e8] BPWM Interrupt Flag Register
| Bits | Field | Descriptions |
| [0] | ZIF0 | BPWM Zero Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. |
| [8] | PIF0 | BPWM Period Point Interrupt Flag 0
This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. |
| [16] | CMPUIF0 | BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
| [17] | CMPUIF1 | BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
| [18] | CMPUIF2 | BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
| [19] | CMPUIF3 | BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
| [20] | CMPUIF4 | BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
| [21] | CMPUIF5 | BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it Each bit n controls the corresponding BPWM channel n. Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
| [24] | CMPDIF0 | BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
| [25] | CMPDIF1 | BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
| [26] | CMPDIF2 | BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
| [27] | CMPDIF3 | BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
| [28] | CMPDIF4 | BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
| [29] | CMPDIF5 | BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
Definition at line 2423 of file bpwm_reg.h.
| BPWM_T::MSK |
[0x00bc] BPWM Mask Data Register
| Bits | Field | Descriptions |
| [0] | MSKDAT0 | BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled Each bit n controls the corresponding BPWM channel n. 0 = Output logic low to BPWMn. 1 = Output logic high to BPWMn. |
| [1] | MSKDAT1 | BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled Each bit n controls the corresponding BPWM channel n. 0 = Output logic low to BPWMn. 1 = Output logic high to BPWMn. |
| [2] | MSKDAT2 | BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled Each bit n controls the corresponding BPWM channel n. 0 = Output logic low to BPWMn. 1 = Output logic high to BPWMn. |
| [3] | MSKDAT3 | BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled Each bit n controls the corresponding BPWM channel n. 0 = Output logic low to BPWMn. 1 = Output logic high to BPWMn. |
| [4] | MSKDAT4 | BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled Each bit n controls the corresponding BPWM channel n. 0 = Output logic low to BPWMn. 1 = Output logic high to BPWMn. |
| [5] | MSKDAT5 | BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled Each bit n controls the corresponding BPWM channel n. 0 = Output logic low to BPWMn. 1 = Output logic high to BPWMn. |
Definition at line 2410 of file bpwm_reg.h.
| BPWM_T::MSKEN |
[0x00b8] BPWM Mask Enable Register
| Bits | Field | Descriptions |
| [0] | MSKEN0 | BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 0 = BPWM output signal is non-masked. 1 = BPWM output signal is masked and output MSKDATn data. |
| [1] | MSKEN1 | BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 0 = BPWM output signal is non-masked. 1 = BPWM output signal is masked and output MSKDATn data. |
| [2] | MSKEN2 | BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 0 = BPWM output signal is non-masked. 1 = BPWM output signal is masked and output MSKDATn data. |
| [3] | MSKEN3 | BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 0 = BPWM output signal is non-masked. 1 = BPWM output signal is masked and output MSKDATn data. |
| [4] | MSKEN4 | BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 0 = BPWM output signal is non-masked. 1 = BPWM output signal is masked and output MSKDATn data. |
| [5] | MSKEN5 | BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n. The BPWM output signal will be masked when this bit is enabled The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 0 = BPWM output signal is non-masked. 1 = BPWM output signal is masked and output MSKDATn data. |
Definition at line 2409 of file bpwm_reg.h.
| BPWM_T::PBUF |
[0x0304] BPWM PERIOD Buffer
| Bits | Field | Descriptions |
| [15:0] | PBUF | BPWM Period Buffer (Read Only)
Used as PERIOD active register. |
Definition at line 2453 of file bpwm_reg.h.
| BPWM_T::PERIOD |
[0x0030] BPWM Period Register
| Bits | Field | Descriptions |
| [15:0] | PERIOD | BPWM Period Register
Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. BPWM period time = (PERIOD+1) * BPWM_CLK period. Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. BPWM period time = 2 * PERIOD * BPWM_CLK period. |
Definition at line 2395 of file bpwm_reg.h.
| BPWM_T::POEN |
[0x00d8] BPWM Output Enable Register
| Bits | Field | Descriptions |
| [0] | POEN0 | BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM pin at tri-state. 1 = BPWM pin in output mode. |
| [1] | POEN1 | BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM pin at tri-state. 1 = BPWM pin in output mode. |
| [2] | POEN2 | BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM pin at tri-state. 1 = BPWM pin in output mode. |
| [3] | POEN3 | BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM pin at tri-state. 1 = BPWM pin in output mode. |
| [4] | POEN4 | BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM pin at tri-state. 1 = BPWM pin in output mode. |
| [5] | POEN5 | BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n. 0 = BPWM pin at tri-state. 1 = BPWM pin in output mode. |
Definition at line 2415 of file bpwm_reg.h.
| BPWM_T::POLCTL |
[0x00d4] BPWM Pin Polar Inverse Register
| Bits | Field | Descriptions |
| [0] | PINV0 | BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output Each bit n controls the corresponding BPWM channel n. 0 = BPWM output polar inverse Disabled. 1 = BPWM output polar inverse Enabled. |
| [1] | PINV1 | BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output Each bit n controls the corresponding BPWM channel n. 0 = BPWM output polar inverse Disabled. 1 = BPWM output polar inverse Enabled. |
| [2] | PINV2 | BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output Each bit n controls the corresponding BPWM channel n. 0 = BPWM output polar inverse Disabled. 1 = BPWM output polar inverse Enabled. |
| [3] | PINV3 | BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output Each bit n controls the corresponding BPWM channel n. 0 = BPWM output polar inverse Disabled. 1 = BPWM output polar inverse Enabled. |
| [4] | PINV4 | BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output Each bit n controls the corresponding BPWM channel n. 0 = BPWM output polar inverse Disabled. 1 = BPWM output polar inverse Enabled. |
| [5] | PINV5 | BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output Each bit n controls the corresponding BPWM channel n. 0 = BPWM output polar inverse Disabled. 1 = BPWM output polar inverse Enabled. |
Definition at line 2414 of file bpwm_reg.h.
| BPWM_T::SSCTL |
[0x0110] BPWM Synchronous Start Control Register
| Bits | Field | Descriptions |
| [0] | SSEN0 | BPWM Synchronous Start Function 0 Enable Bit
When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). 0 = BPWM synchronous start function Disabled. 1 = BPWM synchronous start function Enabled. |
| [9:8] | SSRC | BPWM Synchronous Start Source Select
00 = Synchronous start source come from PWM0. 01 = Synchronous start source come from PWM1. 10 = Synchronous start source come from BPWM0. 11 = Synchronous start source come from BPWM1. |
Definition at line 2432 of file bpwm_reg.h.
| BPWM_T::SSTRG |
[0x0114] BPWM Synchronous Start Trigger Register
| Bits | Field | Descriptions |
| [0] | CNTSEN | BPWM Counter Synchronous Start Enable Bit(Write Only)
BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. |
Definition at line 2433 of file bpwm_reg.h.
| BPWM_T::STATUS |
[0x0120] BPWM Status Register
| Bits | Field | Descriptions |
| [0] | CNTMAX0 | Time-base Counter 0 Equal to 0xFFFF Latched Status
0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. |
| [16] | EADCTRG0 | EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n. 0 = Indicates no EADC start of conversion trigger event has occurred. 1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
| [17] | EADCTRG1 | EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n. 0 = Indicates no EADC start of conversion trigger event has occurred. 1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
| [18] | EADCTRG2 | EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n. 0 = Indicates no EADC start of conversion trigger event has occurred. 1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
| [19] | EADCTRG3 | EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n. 0 = Indicates no EADC start of conversion trigger event has occurred. 1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
| [20] | EADCTRG4 | EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n. 0 = Indicates no EADC start of conversion trigger event has occurred. 1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
| [21] | EADCTRG5 | EADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n. 0 = Indicates no EADC start of conversion trigger event has occurred. 1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
Definition at line 2437 of file bpwm_reg.h.
| BPWM_T::WGCTL0 |
[0x00b0] BPWM Generation Register 0
| Bits | Field | Descriptions |
| [1:0] | ZPCTL0 | BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM zero point output Low. 10 = BPWM zero point output High. 11 = BPWM zero point output Toggle. BPWM can control output level when BPWM counter count to zero. |
| [3:2] | ZPCTL1 | BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM zero point output Low. 10 = BPWM zero point output High. 11 = BPWM zero point output Toggle. BPWM can control output level when BPWM counter count to zero. |
| [5:4] | ZPCTL2 | BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM zero point output Low. 10 = BPWM zero point output High. 11 = BPWM zero point output Toggle. BPWM can control output level when BPWM counter count to zero. |
| [7:6] | ZPCTL3 | BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM zero point output Low. 10 = BPWM zero point output High. 11 = BPWM zero point output Toggle. BPWM can control output level when BPWM counter count to zero. |
| [9:8] | ZPCTL4 | BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM zero point output Low. 10 = BPWM zero point output High. 11 = BPWM zero point output Toggle. BPWM can control output level when BPWM counter count to zero. |
| [11:10] | ZPCTL5 | BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM zero point output Low. 10 = BPWM zero point output High. 11 = BPWM zero point output Toggle. BPWM can control output level when BPWM counter count to zero. |
| [17:16] | PRDPCTL0 | BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM period (center) point output Low. 10 = BPWM period (center) point output High. 11 = BPWM period (center) point output Toggle. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. |
| [19:18] | PRDPCTL1 | BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM period (center) point output Low. 10 = BPWM period (center) point output High. 11 = BPWM period (center) point output Toggle. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. |
| [21:20] | PRDPCTL2 | BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM period (center) point output Low. 10 = BPWM period (center) point output High. 11 = BPWM period (center) point output Toggle. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. |
| [23:22] | PRDPCTL3 | BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM period (center) point output Low. 10 = BPWM period (center) point output High. 11 = BPWM period (center) point output Toggle. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. |
| [25:24] | PRDPCTL4 | BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM period (center) point output Low. 10 = BPWM period (center) point output High. 11 = BPWM period (center) point output Toggle. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. |
| [27:26] | PRDPCTL5 | BPWM Period (Center) Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM period (center) point output Low. 10 = BPWM period (center) point output High. 11 = BPWM period (center) point output Toggle. BPWM can control output level when BPWM counter count to (PERIOD+1). Note: This bit is center point control when BPWM counter operating in up-down counter type. |
Definition at line 2407 of file bpwm_reg.h.
| BPWM_T::WGCTL1 |
[0x00b4] BPWM Generation Register 1
| Bits | Field | Descriptions |
| [1:0] | CMPUCTL0 | BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare up point output Low. 10 = BPWM compare up point output High. 11 = BPWM compare up point output Toggle. BPWM can control output level when BPWM counter up count to CMPDAT. |
| [3:2] | CMPUCTL1 | BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare up point output Low. 10 = BPWM compare up point output High. 11 = BPWM compare up point output Toggle. BPWM can control output level when BPWM counter up count to CMPDAT. |
| [5:4] | CMPUCTL2 | BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare up point output Low. 10 = BPWM compare up point output High. 11 = BPWM compare up point output Toggle. BPWM can control output level when BPWM counter up count to CMPDAT. |
| [7:6] | CMPUCTL3 | BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare up point output Low. 10 = BPWM compare up point output High. 11 = BPWM compare up point output Toggle. BPWM can control output level when BPWM counter up count to CMPDAT. |
| [9:8] | CMPUCTL4 | BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare up point output Low. 10 = BPWM compare up point output High. 11 = BPWM compare up point output Toggle. BPWM can control output level when BPWM counter up count to CMPDAT. |
| [11:10] | CMPUCTL5 | BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare up point output Low. 10 = BPWM compare up point output High. 11 = BPWM compare up point output Toggle. BPWM can control output level when BPWM counter up count to CMPDAT. |
| [17:16] | CMPDCTL0 | BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare down point output Low. 10 = BPWM compare down point output High. 11 = BPWM compare down point output Toggle. BPWM can control output level when BPWM counter down count to CMPDAT. |
| [19:18] | CMPDCTL1 | BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare down point output Low. 10 = BPWM compare down point output High. 11 = BPWM compare down point output Toggle. BPWM can control output level when BPWM counter down count to CMPDAT. |
| [21:20] | CMPDCTL2 | BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare down point output Low. 10 = BPWM compare down point output High. 11 = BPWM compare down point output Toggle. BPWM can control output level when BPWM counter down count to CMPDAT. |
| [23:22] | CMPDCTL3 | BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare down point output Low. 10 = BPWM compare down point output High. 11 = BPWM compare down point output Toggle. BPWM can control output level when BPWM counter down count to CMPDAT. |
| [25:24] | CMPDCTL4 | BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare down point output Low. 10 = BPWM compare down point output High. 11 = BPWM compare down point output Toggle. BPWM can control output level when BPWM counter down count to CMPDAT. |
| [27:26] | CMPDCTL5 | BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n. 00 = Do nothing. 01 = BPWM compare down point output Low. 10 = BPWM compare down point output High. 11 = BPWM compare down point output Toggle. BPWM can control output level when BPWM counter down count to CMPDAT. |
Definition at line 2408 of file bpwm_reg.h.


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| DOSE: T+ 4:00 |
1 bowl |
smoked |
Cannabis |
(plant material) |
| T+ 0:00 |
5.0 mg |
smoked |
5-MeO-DiPT |
(powder / crystals) |
| T+ 0:00 |
8.0 mg |
smoked |
AMT |
(powder / crystals) |
| T+ 4:00 |
1 tablet |
oral |
MDMA |
(pill / tablet) |
| T+ 4:00 |
1 repeated |
smoked |
Cannabis |
(plant material) |
This is not your typical 'It was so good, nothing bad will happen to you,' kind of report. This is a serious warning to never take this combination of drugs (MDMA and AMT). I have took a lot of drugs over the years, but I have never been so afraid that I would die in my life.
The day started out just fine. I never saw it coming. A few hours after I woke up, I decided to smoke a bowl containing weed, around 8 mg of AMT, and around 5 mg of 5-MeO-DiPT. Although those doses were eyeballed, they were divided up from known amounts. I wasn't super wasted from this, but I did have a nice tryptamine buzz that I eventually forgot about.
Later in the day, along with a few friends we rented a hotel room to chill in for the night. Before we got there, 'H' bought a half oz. of bad pot and 3 ecstasy pills. Wanting to have fun that night turned out to be a huge mistake. I completely forgot that I had smoked research chemicals (up to four hours earlier). 'H' set a 'goldfish' right in front of me; could I say no?  While waiting for it to come on, we smoked bowl after bowl of some really bad pot.
The more the pill kicked in, the worse I felt. Normally, I would be starting to feel good right about now. But the pill was doing something to me that it had never done before. It felt so wrong. It was like my body was doing nothing to break down the chemical. It hit me harder than it ever did before. Instead of feeling on top of the world, I felt like I was about to pass out. I couldn't see straight because my eyes were twitching nonstop. After a few minutes, things got really bad and I could hardly breathe or walk. I stumbled into the bathroom to try and force myself to expell the pill, but I hadn't eaten enough. There was no turning back. I have never been so scared. For about fifteen minutes I was on the bathroom floor, hands and knees, just forcing myself to breathe. I could feel every part of me being devastated.
Luckily, the feeling of passing out became less while the roll became stronger. After about 20 minutes, I no longer felt like my body was about to give out.  Normally the roll has a numbing quality so I can't feel my mind being fried, but this time, I could. I felt so much better than the last few rolls I took, but the toll it took was way worse.
'S' ordered some food and we sat around the hotel room rambling nonstop and eating a couple bites of burger when we could. I am sure some of the people staying there knew we were wasted, one guy offered to sell us weed. We messed around the hotel all night playing games, going into the sauna, and just roaming around. I'm surprised that we didn't get kicked out for keeping somebody awake. After 'H' and 'B''s rolls started to wear off, they began drinking. I couldn't bear to drink because these drugs burned me out more than anything I had ever taken. I did drink a little the next morning to counteract the feeling of scumminess. I really don't drink unless I am desperate. By 4 AM (5-6 hours after taking the roll), everybody CRASHED. We passed right out.
I still get a strange feeling in my upper back just thinking about it. I was really lucky not to end up in the emergency room.
Experience Reports are the writings and opinions of the individual authors who submit them.
Some of the activities described are dangerous and/or illegal and none are recommended by Erowid.


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