|
NANO103 BSP V3.01.003
The Board Support Package for Nano103 Series
|
Macros | |
| #define | NULL (0) |
| NULL pointer. More... | |
| #define | TRUE (1) |
| Boolean true, define to use in API parameters or return value. More... | |
| #define | FALSE (0) |
| Boolean false, define to use in API parameters or return value. More... | |
| #define | ENABLE (1) |
| Enable, define to use in API parameters. More... | |
| #define | DISABLE (0) |
| Disable, define to use in API parameters. More... | |
| #define | BIT0 (0x00000001) |
| Bit 0 mask of an 32 bit integer. More... | |
| #define | BIT1 (0x00000002) |
| Bit 1 mask of an 32 bit integer. More... | |
| #define | BIT2 (0x00000004) |
| Bit 2 mask of an 32 bit integer. More... | |
| #define | BIT3 (0x00000008) |
| Bit 3 mask of an 32 bit integer. More... | |
| #define | BIT4 (0x00000010) |
| Bit 4 mask of an 32 bit integer. More... | |
| #define | BIT5 (0x00000020) |
| Bit 5 mask of an 32 bit integer. More... | |
| #define | BIT6 (0x00000040) |
| Bit 6 mask of an 32 bit integer. More... | |
| #define | BIT7 (0x00000080) |
| Bit 7 mask of an 32 bit integer. More... | |
| #define | BIT8 (0x00000100) |
| Bit 8 mask of an 32 bit integer. More... | |
| #define | BIT9 (0x00000200) |
| Bit 9 mask of an 32 bit integer. More... | |
| #define | BIT10 (0x00000400) |
| Bit 10 mask of an 32 bit integer. More... | |
| #define | BIT11 (0x00000800) |
| Bit 11 mask of an 32 bit integer. More... | |
| #define | BIT12 (0x00001000) |
| Bit 12 mask of an 32 bit integer. More... | |
| #define | BIT13 (0x00002000) |
| Bit 13 mask of an 32 bit integer. More... | |
| #define | BIT14 (0x00004000) |
| Bit 14 mask of an 32 bit integer. More... | |
| #define | BIT15 (0x00008000) |
| Bit 15 mask of an 32 bit integer. More... | |
| #define | BIT16 (0x00010000) |
| Bit 16 mask of an 32 bit integer. More... | |
| #define | BIT17 (0x00020000) |
| Bit 17 mask of an 32 bit integer. More... | |
| #define | BIT18 (0x00040000) |
| Bit 18 mask of an 32 bit integer. More... | |
| #define | BIT19 (0x00080000) |
| Bit 19 mask of an 32 bit integer. More... | |
| #define | BIT20 (0x00100000) |
| Bit 20 mask of an 32 bit integer. More... | |
| #define | BIT21 (0x00200000) |
| Bit 21 mask of an 32 bit integer. More... | |
| #define | BIT22 (0x00400000) |
| Bit 22 mask of an 32 bit integer. More... | |
| #define | BIT23 (0x00800000) |
| Bit 23 mask of an 32 bit integer. More... | |
| #define | BIT24 (0x01000000) |
| Bit 24 mask of an 32 bit integer. More... | |
| #define | BIT25 (0x02000000) |
| Bit 25 mask of an 32 bit integer. More... | |
| #define | BIT26 (0x04000000) |
| Bit 26 mask of an 32 bit integer. More... | |
| #define | BIT27 (0x08000000) |
| Bit 27 mask of an 32 bit integer. More... | |
| #define | BIT28 (0x10000000) |
| Bit 28 mask of an 32 bit integer. More... | |
| #define | BIT29 (0x20000000) |
| Bit 29 mask of an 32 bit integer. More... | |
| #define | BIT30 (0x40000000) |
| Bit 30 mask of an 32 bit integer. More... | |
| #define | BIT31 (0x80000000) |
| Bit 31 mask of an 32 bit integer. More... | |
| #define | BYTE0_Msk (0x000000FF) |
| Mask to get bit0~bit7 from a 32 bit integer. More... | |
| #define | BYTE1_Msk (0x0000FF00) |
| Mask to get bit8~bit15 from a 32 bit integer. More... | |
| #define | BYTE2_Msk (0x00FF0000) |
| Mask to get bit16~bit23 from a 32 bit integer. More... | |
| #define | BYTE3_Msk (0xFF000000) |
| Mask to get bit24~bit31 from a 32 bit integer. More... | |
| #define | GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) |
| #define | GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) |
| #define | GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) |
| #define | GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) |
Variables | |
| __I uint32_t | INT_T::IRQ0_SRC |
| __I uint32_t | INT_T::IRQ1_SRC |
| __I uint32_t | INT_T::IRQ2_SRC |
| __I uint32_t | INT_T::IRQ3_SRC |
| __I uint32_t | INT_T::IRQ4_SRC |
| __I uint32_t | INT_T::IRQ5_SRC |
| __I uint32_t | INT_T::IRQ6_SRC |
| __I uint32_t | INT_T::IRQ7_SRC |
| __I uint32_t | INT_T::IRQ8_SRC |
| __I uint32_t | INT_T::IRQ9_SRC |
| __I uint32_t | INT_T::IRQ10_SRC |
| __I uint32_t | INT_T::IRQ11_SRC |
| __I uint32_t | INT_T::IRQ12_SRC |
| __I uint32_t | INT_T::IRQ13_SRC |
| __I uint32_t | INT_T::IRQ14_SRC |
| __I uint32_t | INT_T::IRQ15_SRC |
| __I uint32_t | INT_T::IRQ16_SRC |
| __I uint32_t | INT_T::IRQ17_SRC |
| __I uint32_t | INT_T::IRQ18_SRC |
| __I uint32_t | INT_T::IRQ19_SRC |
| __I uint32_t | INT_T::IRQ20_SRC |
| __I uint32_t | INT_T::IRQ21_SRC |
| __I uint32_t | INT_T::IRQ22_SRC |
| __I uint32_t | INT_T::IRQ23_SRC |
| __I uint32_t | INT_T::IRQ24_SRC |
| __I uint32_t | INT_T::IRQ25_SRC |
| __I uint32_t | INT_T::IRQ26_SRC |
| __I uint32_t | INT_T::IRQ27_SRC |
| __I uint32_t | INT_T::IRQ28_SRC |
| __I uint32_t | INT_T::IRQ29_SRC |
| __I uint32_t | INT_T::IRQ30_SRC |
| __I uint32_t | INT_T::IRQ31_SRC |
| __IO uint32_t | INT_T::NMI_SEL |
| __IO uint32_t | INT_T::MCU_IRQ |
| __I uint32_t | SYS_T::PDID |
| __IO uint32_t | SYS_T::RSTSTS |
| __IO uint32_t | SYS_T::IPRST1 |
| __IO uint32_t | SYS_T::IPRST2 |
| __IO uint32_t | SYS_T::MISCCTL |
| __IO uint32_t | SYS_T::TEMPCTL |
| __IO uint32_t | SYS_T::RCCFCTL |
| __IO uint32_t | SYS_T::GPA_MFPL |
| __IO uint32_t | SYS_T::GPA_MFPH |
| __IO uint32_t | SYS_T::GPB_MFPL |
| __IO uint32_t | SYS_T::GPB_MFPH |
| __IO uint32_t | SYS_T::GPC_MFPL |
| __IO uint32_t | SYS_T::GPC_MFPH |
| __IO uint32_t | SYS_T::GPD_MFPL |
| __IO uint32_t | SYS_T::GPD_MFPH |
| __IO uint32_t | SYS_T::GPE_MFPL |
| __IO uint32_t | SYS_T::GPF_MFPL |
| __IO uint32_t | SYS_T::PORCTL |
| __IO uint32_t | SYS_T::BODCTL |
| __IO uint32_t | SYS_T::IVREFCTL |
| __IO uint32_t | SYS_T::LDOCTL |
| __IO uint32_t | SYS_T::BATDIVCTL |
| __I uint32_t | SYS_T::WKSTS |
| __IO uint32_t | SYS_T::IRC0TCTL |
| __IO uint32_t | SYS_T::IRC0TIEN |
| __IO uint32_t | SYS_T::IRC0TISTS |
| __IO uint32_t | SYS_T::IRC1TCTL |
| __IO uint32_t | SYS_T::IRC1TIEN |
| __IO uint32_t | SYS_T::IRC1TISTS |
| __IO uint32_t | SYS_T::MIRCTCTL |
| __IO uint32_t | SYS_T::MIRCTIEN |
| __IO uint32_t | SYS_T::MIRCTISTS |
| __O uint32_t | SYS_T::REGLCTL |
| __IO uint32_t | SYS_T::RPDBCLK |
| __IO uint32_t | CLK_T::PWRCTL |
| __IO uint32_t | CLK_T::AHBCLK |
| __IO uint32_t | CLK_T::APBCLK |
| __I uint32_t | CLK_T::STATUS |
| __IO uint32_t | CLK_T::CLKSEL0 |
| __IO uint32_t | CLK_T::CLKSEL1 |
| __IO uint32_t | CLK_T::CLKSEL2 |
| __IO uint32_t | CLK_T::CLKDIV0 |
| __IO uint32_t | CLK_T::CLKDIV1 |
| __IO uint32_t | CLK_T::PLLCTL |
| __IO uint32_t | CLK_T::CLKOCTL |
| __IO uint32_t | CLK_T::WKINTSTS |
| __IO uint32_t | CLK_T::APBDIV |
| __IO uint32_t | CLK_T::CLKDCTL |
| __IO uint32_t | CLK_T::CLKDIE |
| __IO uint32_t | CLK_T::CLKDSTS |
| __IO uint32_t | CLK_T::CDUPB |
| __IO uint32_t | CLK_T::CDLOWB |
| __IO uint32_t | FMC_T::ISPCTL |
| __IO uint32_t | FMC_T::ISPADDR |
| __IO uint32_t | FMC_T::ISPDAT |
| __IO uint32_t | FMC_T::ISPCMD |
| __IO uint32_t | FMC_T::ISPTRG |
| __I uint32_t | FMC_T::DFBA |
| __IO uint32_t | FMC_T::FTCTL |
| __IO uint32_t | FMC_T::ISPSTS |
| __O uint32_t | FMC_T::KEY0 |
| __O uint32_t | FMC_T::KEY1 |
| __O uint32_t | FMC_T::KEY2 |
| __IO uint32_t | FMC_T::KEYTRG |
| __IO uint32_t | FMC_T::KEYSTS |
| __I uint32_t | FMC_T::KECNT |
| __I uint32_t | FMC_T::KPCNT |
| __IO uint32_t | GPIO_T::MODE |
| __IO uint32_t | GPIO_T::DINOFF |
| __IO uint32_t | GPIO_T::DOUT |
| __IO uint32_t | GPIO_T::DATMSK |
| __I uint32_t | GPIO_T::PIN |
| __IO uint32_t | GPIO_T::DBEN |
| __IO uint32_t | GPIO_T::INTTYPE |
| __IO uint32_t | GPIO_T::INTEN |
| __IO uint32_t | GPIO_T::INTSRC |
| __IO uint32_t | GPIO_T::PUEN |
| __I uint32_t | GPIO_T::INTSTS |
| __IO uint32_t | GP_DB_T::DBCTL |
| __IO uint32_t | PDMA_CH_T::CTLn |
| __IO uint32_t | PDMA_CH_T::SAn |
| __IO uint32_t | PDMA_CH_T::DAn |
| __IO uint32_t | PDMA_CH_T::CNTn |
| __I uint32_t | PDMA_CH_T::CSAn |
| __I uint32_t | PDMA_CH_T::CDAn |
| __I uint32_t | PDMA_CH_T::CCNTn |
| __IO uint32_t | PDMA_CH_T::INTENn |
| __IO uint32_t | PDMA_CH_T::INTSTSn |
| __IO uint32_t | PDMA_CH_T::TOCn |
| __IO uint32_t | DMA_CRC_T::CTL |
| __IO uint32_t | DMA_CRC_T::DMASA |
| __IO uint32_t | DMA_CRC_T::DMABCNT |
| __I uint32_t | DMA_CRC_T::DMACSA |
| __I uint32_t | DMA_CRC_T::DMACBCNT |
| __IO uint32_t | DMA_CRC_T::DMAINTEN |
| __IO uint32_t | DMA_CRC_T::DMAISTS |
| __IO uint32_t | DMA_CRC_T::DAT |
| __IO uint32_t | DMA_CRC_T::SEED |
| __I uint32_t | DMA_CRC_T::CHECKSUM |
| __IO uint32_t | DMA_GCR_T::GCTL |
| __IO uint32_t | DMA_GCR_T::REQSEL0 |
| __IO uint32_t | DMA_GCR_T::REQSEL1 |
| __I uint32_t | DMA_GCR_T::GINTSTS |
| __IO uint32_t | TIMER_T::CTL |
| __IO uint32_t | TIMER_T::PRECNT |
| __IO uint32_t | TIMER_T::CMP |
| __IO uint32_t | TIMER_T::INTEN |
| __IO uint32_t | TIMER_T::INTSTS |
| __IO uint32_t | TIMER_T::CNT |
| __I uint32_t | TIMER_T::CAP |
| __IO uint32_t | TIMER_T::ECTL |
| __IO uint32_t | PWM_T::CTL0 |
| __IO uint32_t | PWM_T::CTL1 |
| __IO uint32_t | PWM_T::CLKSRC |
| __IO uint32_t | PWM_T::CLKPSC0_1 |
| __IO uint32_t | PWM_T::CLKPSC2_3 |
| __IO uint32_t | PWM_T::CLKPSC4_5 |
| __IO uint32_t | PWM_T::CNTEN |
| __IO uint32_t | PWM_T::CNTCLR |
| __IO uint32_t | PWM_T::PERIOD [6] |
| __IO uint32_t | PWM_T::CMPDAT [6] |
| __IO uint32_t | PWM_T::DTCTL0_1 |
| __IO uint32_t | PWM_T::DTCTL2_3 |
| __IO uint32_t | PWM_T::DTCTL4_5 |
| __I uint32_t | PWM_T::CNT [6] |
| __IO uint32_t | PWM_T::WGCTL0 |
| __IO uint32_t | PWM_T::WGCTL1 |
| __IO uint32_t | PWM_T::MSKEN |
| __IO uint32_t | PWM_T::MSK |
| __IO uint32_t | PWM_T::BNF |
| __IO uint32_t | PWM_T::FAILBRK |
| __IO uint32_t | PWM_T::BRKCTL0_1 |
| __IO uint32_t | PWM_T::BRKCTL2_3 |
| __IO uint32_t | PWM_T::BRKCTL4_5 |
| __IO uint32_t | PWM_T::POLCTL |
| __IO uint32_t | PWM_T::POEN |
| __O uint32_t | PWM_T::SWBRK |
| __IO uint32_t | PWM_T::INTEN0 |
| __IO uint32_t | PWM_T::INTEN1 |
| __IO uint32_t | PWM_T::INTSTS0 |
| __IO uint32_t | PWM_T::INTSTS1 |
| __IO uint32_t | PWM_T::ADCTS0 |
| __IO uint32_t | PWM_T::ADCTS1 |
| __IO uint32_t | PWM_T::STATUS |
| __IO uint32_t | PWM_T::CAPINEN |
| __IO uint32_t | PWM_T::CAPCTL |
| __I uint32_t | PWM_T::CAPSTS |
| __I uint32_t | PWM_T::RCAPDAT0 |
| __I uint32_t | PWM_T::FCAPDAT0 |
| __I uint32_t | PWM_T::RCAPDAT1 |
| __I uint32_t | PWM_T::FCAPDAT1 |
| __I uint32_t | PWM_T::RCAPDAT2 |
| __I uint32_t | PWM_T::FCAPDAT2 |
| __I uint32_t | PWM_T::RCAPDAT3 |
| __I uint32_t | PWM_T::FCAPDAT3 |
| __I uint32_t | PWM_T::RCAPDAT4 |
| __I uint32_t | PWM_T::FCAPDAT4 |
| __I uint32_t | PWM_T::RCAPDAT5 |
| __I uint32_t | PWM_T::FCAPDAT5 |
| __IO uint32_t | PWM_T::CAPIEN |
| __IO uint32_t | PWM_T::CAPIF |
| __IO uint32_t | PWM_T::SELFTEST |
| __I uint32_t | PWM_T::PBUF0 |
| __I uint32_t | PWM_T::PBUF2 |
| __I uint32_t | PWM_T::PBUF4 |
| __I uint32_t | PWM_T::CMPBUF0 |
| __I uint32_t | PWM_T::CMPBUF1 |
| __I uint32_t | PWM_T::CMPBUF2 |
| __I uint32_t | PWM_T::CMPBUF3 |
| __I uint32_t | PWM_T::CMPBUF4 |
| __I uint32_t | PWM_T::CMPBUF5 |
| __IO uint32_t | WDT_T::CTL |
| __IO uint32_t | WDT_T::INTEN |
| __IO uint32_t | WDT_T::STATUS |
| __O uint32_t | WWDT_T::RLDCNT |
| __IO uint32_t | WWDT_T::CTL |
| __IO uint32_t | WWDT_T::INTEN |
| __IO uint32_t | WWDT_T::STATUS |
| __I uint32_t | WWDT_T::CNT |
| __IO uint32_t | RTC_T::INIT |
| __IO uint32_t | RTC_T::RWEN |
| __IO uint32_t | RTC_T::FREQADJ |
| __IO uint32_t | RTC_T::TIME |
| __IO uint32_t | RTC_T::CAL |
| __IO uint32_t | RTC_T::CLKFMT |
| __IO uint32_t | RTC_T::WEEKDAY |
| __IO uint32_t | RTC_T::TALM |
| __IO uint32_t | RTC_T::CALM |
| __I uint32_t | RTC_T::LEAPYEAR |
| __IO uint32_t | RTC_T::INTEN |
| __IO uint32_t | RTC_T::INTSTS |
| __IO uint32_t | RTC_T::TICK |
| __IO uint32_t | RTC_T::TAMSK |
| __IO uint32_t | RTC_T::CAMSK |
| __IO uint32_t | RTC_T::SPRCTL |
| __IO uint32_t | RTC_T::SPR [5] |
| __IO uint32_t | RTC_T::LXTCTL |
| __IO uint32_t | RTC_T::LXTOCTL |
| __IO uint32_t | RTC_T::LXTICTL |
| __IO uint32_t | RTC_T::TAMPCTL |
| __IO uint32_t | RTC_T::MISCCTL |
| __IO uint32_t | UART_T::DAT |
| __IO uint32_t | UART_T::CTRL |
| __IO uint32_t | UART_T::LINE |
| __IO uint32_t | UART_T::INTEN |
| __IO uint32_t | UART_T::INTSTS |
| __IO uint32_t | UART_T::TRSR |
| __IO uint32_t | UART_T::FIFOSTS |
| __IO uint32_t | UART_T::MODEM |
| __IO uint32_t | UART_T::TOUT |
| __IO uint32_t | UART_T::BAUD |
| __IO uint32_t | UART_T::IRDA |
| __IO uint32_t | UART_T::ALTCTL |
| __IO uint32_t | UART_T::FUNCSEL |
| __IO uint32_t | UART_T::BRCOMPAT |
| __IO uint32_t | UART_T::WKUPEN |
| __IO uint32_t | UART_T::WKUPSTS |
| __IO uint32_t | SC_T::DAT |
| __IO uint32_t | SC_T::CTL |
| __IO uint32_t | SC_T::ALTCTL |
| __IO uint32_t | SC_T::EGT |
| __IO uint32_t | SC_T::RXTOUT |
| __IO uint32_t | SC_T::ETUCTL |
| __IO uint32_t | SC_T::INTEN |
| __IO uint32_t | SC_T::INTSTS |
| __IO uint32_t | SC_T::STATUS |
| __IO uint32_t | SC_T::PINCTL |
| __IO uint32_t | SC_T::TMRCTL0 |
| __IO uint32_t | SC_T::TMRCTL1 |
| __IO uint32_t | SC_T::TMRCTL2 |
| __IO uint32_t | SC_T::UARTCTL |
| __IO uint32_t | SC_T::ACTCTL |
| __IO uint32_t | I2C_T::CTL |
| __IO uint32_t | I2C_T::INTSTS |
| __I uint32_t | I2C_T::STATUS |
| __IO uint32_t | I2C_T::CLKDIV |
| __IO uint32_t | I2C_T::TOCTL |
| __IO uint32_t | I2C_T::DAT |
| __IO uint32_t | I2C_T::ADDR0 |
| __IO uint32_t | I2C_T::ADDR1 |
| __IO uint32_t | I2C_T::ADDRMSK0 |
| __IO uint32_t | I2C_T::ADDRMSK1 |
| __IO uint32_t | I2C_T::CTL2 |
| __IO uint32_t | I2C_T::STATUS2 |
| __IO uint32_t | SPI_T::CTL |
| __IO uint32_t | SPI_T::STATUS |
| __IO uint32_t | SPI_T::CLKDIV |
| __IO uint32_t | SPI_T::SSCTL |
| __I uint32_t | SPI_T::RX0 |
| __I uint32_t | SPI_T::RX1 |
| __O uint32_t | SPI_T::TX0 |
| __O uint32_t | SPI_T::TX1 |
| __IO uint32_t | SPI_T::PDMACTL |
| __IO uint32_t | SPI_T::FIFOCTL |
| __I uint32_t | ADC_T::DAT [18] |
| __IO uint32_t | ADC_T::CTL |
| __IO uint32_t | ADC_T::CHEN |
| __IO uint32_t | ADC_T::CMP0 |
| __IO uint32_t | ADC_T::CMP1 |
| __IO uint32_t | ADC_T::STATUS |
| __I uint32_t | ADC_T::PDMA |
| __IO uint32_t | ADC_T::PWD |
| __IO uint32_t | ADC_T::CALCTL |
| __IO uint32_t | ADC_T::CALWORD |
| __IO uint32_t | ADC_T::EXTSMPT0 |
| __IO uint32_t | ADC_T::EXTSMPT1 |
| __IO uint32_t | ACMP_T::CTL0 |
| __IO uint32_t | ACMP_T::STATUS |
| __IO uint32_t | ACMP_T::VREF |
NANO103 Legacy Constants
| #define BIT0 (0x00000001) |
| #define BIT1 (0x00000002) |
| #define BIT10 (0x00000400) |
| #define BIT11 (0x00000800) |
| #define BIT12 (0x00001000) |
| #define BIT13 (0x00002000) |
| #define BIT14 (0x00004000) |
| #define BIT15 (0x00008000) |
| #define BIT16 (0x00010000) |
| #define BIT17 (0x00020000) |
| #define BIT18 (0x00040000) |
| #define BIT19 (0x00080000) |
| #define BIT2 (0x00000004) |
| #define BIT20 (0x00100000) |
| #define BIT21 (0x00200000) |
| #define BIT22 (0x00400000) |
| #define BIT23 (0x00800000) |
| #define BIT24 (0x01000000) |
| #define BIT25 (0x02000000) |
| #define BIT26 (0x04000000) |
| #define BIT27 (0x08000000) |
| #define BIT28 (0x10000000) |
| #define BIT29 (0x20000000) |
| #define BIT3 (0x00000008) |
| #define BIT30 (0x40000000) |
| #define BIT31 (0x80000000) |
| #define BIT4 (0x00000010) |
| #define BIT5 (0x00000020) |
| #define BIT6 (0x00000040) |
| #define BIT7 (0x00000080) |
| #define BIT8 (0x00000100) |
| #define BIT9 (0x00000200) |
| #define BYTE0_Msk (0x000000FF) |
| #define BYTE1_Msk (0x0000FF00) |
| #define BYTE2_Msk (0x00FF0000) |
| #define BYTE3_Msk (0xFF000000) |
| #define DISABLE (0) |
| #define ENABLE (1) |
| #define FALSE (0) |
| #define GET_BYTE0 | ( | u32Param | ) | ((u32Param & BYTE0_Msk) ) |
| #define GET_BYTE1 | ( | u32Param | ) | ((u32Param & BYTE1_Msk) >> 8) |
| #define GET_BYTE2 | ( | u32Param | ) | ((u32Param & BYTE2_Msk) >> 16) |
| #define GET_BYTE3 | ( | u32Param | ) | ((u32Param & BYTE3_Msk) >> 24) |
| #define TRUE (1) |
| SC_T::ACTCTL |
[0x0040] SC Activation Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [4:0] | T1EXT | Configurable Cycles T1EXT in Hardware Activation |
| This field provide the configurable cycles to extend the Activation time T1 | ||
| The cycle scaling factor is 2048. | ||
| Extend cycles = (filled value * 2048) cycles. | ||
| Refer to SC Activation Sequence in Figure 6.15-4 SC Activation Sequence. | ||
| For example, | ||
| SCLK = 4Mhz, each cycle = 0.25us,. | ||
| Filled 20 to this field | ||
| Extend time = 20*2048*0.25us = 10.24 ms. | ||
| Note: setting 0 to this field conforms to the protocol ISO/IEC 7816-3 |
| PWM_T::ADCTS0 |
[0x00f8] PWM0 Trigger ADC Source Select Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | TRGSEL0 | PWM0_CH0 Trigger ADC Source Select |
| 0000 = PWM0_CH0 zero point. | ||
| 0001 = PWM0_CH0 period point. | ||
| 0010 = PWM0_CH0 zero or period point. | ||
| 0011 = PWM0_CH0 up-count CMPDAT point. | ||
| 0100 = PWM0_CH0 down-count CMPDAT point. | ||
| 0101 = Reserved. | ||
| 0110 = Reserved. | ||
| 0111 = Reserved. | ||
| 1000 = PWM0_CH1 up-count CMPDAT point. | ||
| 1001 = PWM0_CH1 down-count CMPDAT point. | ||
| Others reserved | ||
| [7] | TRGEN0 | PWM0_CH0 Trigger EADC Enable Bit |
| 0 = PWM0_CH0 Trigger EADC Disabled. | ||
| 1 = PWM0_CH0 Trigger EADC Enabled. | ||
| [11:8] | TRGSEL1 | PWM0_CH1 Trigger ADC Source Select |
| 0000 = PWM0_CH0 zero point. | ||
| 0001 = PWM0_CH0 period point. | ||
| 0010 = PWM0_CH0 zero or period point. | ||
| 0011 = PWM0_CH0 up-count CMPDAT point. | ||
| 0100 = PWM0_CH0 down-count CMPDAT point. | ||
| 0101 = Reserved. | ||
| 0110 = Reserved. | ||
| 0111 = Reserved. | ||
| 1000 = PWM0_CH1 up-count CMPDAT point. | ||
| 1001 = PWM0_CH1 down-count CMPDAT point. | ||
| Others reserved | ||
| [15] | TRGEN1 | PWM0_CH1 Trigger EADC Enable Bit |
| 0 = PWM0_CH1 Trigger EADC Disabled. | ||
| 1 = PWM0_CH1 Trigger EADC Enabled. | ||
| [19:16] | TRGSEL2 | PWM0_CH2 Trigger ADC Source Select |
| 0000 = PWM0_CH2 zero point. | ||
| 0001 = PWM0_CH2 period point. | ||
| 0010 = PWM0_CH2 zero or period point. | ||
| 0011 = PWM0_CH2 up-count CMPDAT point. | ||
| 0100 = PWM0_CH2 down-count CMPDAT point. | ||
| 0101 = Reserved. | ||
| 0110 = Reserved. | ||
| 0111 = Reserved. | ||
| 1000 = PWM0_CH3 up-count CMPDAT point. | ||
| 1001 = PWM0_CH3 down-count CMPDAT point. | ||
| Others reserved | ||
| [23] | TRGEN2 | PWM0_CH2 Trigger EADC Enable Bit |
| 0 = PWM0_CH2 Trigger EADC Disabled. | ||
| 1 = PWM0_CH2 Trigger EADC Enabled. | ||
| [27:24] | TRGSEL3 | PWM0_CH3 Trigger ADC Source Select |
| 0000 = PWM0_CH2 zero point. | ||
| 0001 = PWM0_CH2 period point. | ||
| 0010 = PWM0_CH2 zero or period point. | ||
| 0011 = PWM0_CH2 up-count CMPDAT point. | ||
| 0100 = PWM0_CH2 down-count CMPDAT point. | ||
| 0101 = Reserved. | ||
| 0110 = Reserved. | ||
| 0111 = Reserved. | ||
| 1000 = PWM0_CH3 up-count CMPDAT point. | ||
| 1001 = PWM0_CH3 down-count CMPDAT point. | ||
| Others reserved | ||
| [31] | TRGEN3 | PWM0_CH3 Trigger EADC Enable Bit |
| 0 = PWM0_CH3 Trigger EADC Disabled. | ||
| 1 = PWM0_CH3 Trigger EADC Enabled. |
| PWM_T::ADCTS1 |
[0x00fc] PWM0 Trigger ADC Source Select Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | TRGSEL4 | PWM0_CH4 Trigger ADC Source Select |
| 0000 = PWM0_CH4 zero point. | ||
| 0001 = PWM0_CH4 period point. | ||
| 0010 = PWM0_CH4 zero or period point. | ||
| 0011 = PWM0_CH4 up-count CMPDAT point. | ||
| 0100 = PWM0_CH4 down-count CMPDAT point. | ||
| 0101 = Reserved. | ||
| 0110 = Reserved. | ||
| 0111 = Reserved. | ||
| 1000 = PWM0_CH5 up-count CMPDAT point. | ||
| 1001 = PWM0_CH5 down-count CMPDAT point. | ||
| Others reserved | ||
| [7] | TRGEN4 | PWM0_CH4 Trigger EADC Enable Bit |
| 0 = PWM0_CH4 Trigger EADC Disabled. | ||
| 1 = PWM0_CH4 Trigger EADC Enabled. | ||
| [11:8] | TRGSEL5 | PWM0_CH5 Trigger ADC Source Select |
| 0000 = PWM0_CH4 zero point. | ||
| 0001 = PWM0_CH4 period point. | ||
| 0010 = PWM0_CH4 zero or period point. | ||
| 0011 = PWM0_CH4 up-count CMPDAT point. | ||
| 0100 = PWM0_CH4 down-count CMPDAT point. | ||
| 0101 = Reserved. | ||
| 0110 = Reserved. | ||
| 0111 = Reserved. | ||
| 1000 = PWM0_CH5 up-count CMPDAT point. | ||
| 1001 = PWM0_CH5 down-count CMPDAT point. | ||
| Others reserved | ||
| [15] | TRGEN5 | PWM0_CH5 Trigger EADC Enable Bit |
| 0 = PWM0_CH5 Trigger EADC Disabled. | ||
| 1 = PWM0_CH5 Trigger EADC Enabled. |
| I2C_T::ADDR0 |
[0x0018] I2C Slave Address Register0
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GC | General Call Function Control |
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| Note: Refer to Address Register section for more detailed information. | ||
| [7:1] | ADDR | I2C Salve Address Bits |
| The content of this register is irrelevant when the device is in Master mode | ||
| In the Slave mode, the seven most significant bits must be loaded with the device's own address | ||
| The device will react if either of the address is matched. |
| I2C_T::ADDR1 |
[0x001c] I2C Slave Address Register1
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GC | General Call Function Control |
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| Note: Refer to Address Register section for more detailed information. | ||
| [7:1] | ADDR | I2C Salve Address Bits |
| The content of this register is irrelevant when the device is in Master mode | ||
| In the Slave mode, the seven most significant bits must be loaded with the device's own address | ||
| The device will react if either of the address is matched. |
| I2C_T::ADDRMSK0 |
[0x0028] I2C Slave Address Mask Register0
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | ADDRMSK | I2C Slave Address Mask Bits |
| 0 = Mask disable (the received corresponding register bit should be exact the same as address register). | ||
| 1 = Mask enable (the received corresponding address bit is don't care). | ||
| I2C bus controllers support multiple address recognition with two address mask register | ||
| When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care | ||
| If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. |
| I2C_T::ADDRMSK1 |
[0x002c] I2C Slave Address Mask Register1
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | ADDRMSK | I2C Slave Address Mask Bits |
| 0 = Mask disable (the received corresponding register bit should be exact the same as address register). | ||
| 1 = Mask enable (the received corresponding address bit is don't care). | ||
| I2C bus controllers support multiple address recognition with two address mask register | ||
| When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care | ||
| If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. |
| CLK_T::AHBCLK |
[0x0004] AHB Devices Clock Enable Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GPIOCKEN | GPIO Controller Clock Enable Control |
| 0 = GPIO peripheral clock Disabled. | ||
| 1 = GPIO peripheral clock Enabled. | ||
| [1] | PDMACKEN | PDMA Controller Clock Enable Bit |
| 0 = PDMA peripheral clock Disabled. | ||
| 1 = PDMA peripheral clock Enabled. | ||
| [2] | ISPCKEN | Flash ISP Controller Clock Enable Bit |
| 0 = Flash ISP peripheral clock Disabled. | ||
| 1 = Flash ISP peripheral clock Enabled. | ||
| [4] | SRAMCKEN | SRAM Controller Clock Enable Control Bit |
| 0 = SRAM peripheral clock Disabled. | ||
| 1 = SRAM peripheral clock Enabled. | ||
| [5] | STCKEN | System Tick Clock Enable Control Bit |
| 0 = System Tick Clock Disabled. | ||
| 1 = System Tick Clock Enabled. |
| UART_T::ALTCTL |
[0x0034] UART Alternate Control State Register.
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | BRKFL | LIN TX Break Field Count |
| The field contains 3-bit LIN TX break field count. | ||
| Note: The break field length is BRKFL + 8. | ||
| [5:4] | LINHSEL | LIN Header Selection |
| 00 = The LIN header includes break field. | ||
| 01 = The LIN header includes break field + sync field. | ||
| 10 = The LIN header includes break field + sync field + PID field. | ||
| 11 = Reserved. | ||
| [6] | LINRXEN | LIN RX Enable Control |
| When LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (LININT) | ||
| 0 = LIN RX mode Disabled. | ||
| 1 = LIN RX mode Enabled. | ||
| [7] | LINTXEN | LIN TX Header Trigger Enable Bit |
| The LIN TX header can be break field or break and sync field or break, sync and frame ID field, it is depend on setting LINHSEL (UART_ALT_CSR[5:4]). | ||
| 0 = Send LIN TX header Disabled. | ||
| 1 = Send LIN TX header Enabled. | ||
| Note1: This bit will be cleared automatically and generate a interrupt to CPU (LININT). | ||
| Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LINHSEL (UART_ALT_CSR[5:4]) field) transfer operation finished, this bit will be cleared automatically. | ||
| Note3: If user wants to receive transmit data, it recommended to enable LINRXEN bit. | ||
| [8] | BITERREN | Bit Error Detect Enable Bit |
| 0 = Bit error detection Disabled. | ||
| 1 = Bit error detection Enabled. | ||
| Note: In LIN function mode, when bit error occurs, the BITEF (UART_TRSR[5]) flag will be asserted | ||
| If the LINIEN (UART_IER[8]) = 1, an interrupt will be generated . | ||
| [16] | RS485NMM | RS-485 Normal Multi-drop Operation Mode (NMM) |
| 0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. | ||
| 1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. | ||
| Note: It cannot be active with RS-485_AAD operation mode. | ||
| [17] | RS485AAD | RS-485 Auto Address Detection Operation Mode (AAD) |
| 0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. | ||
| 1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. | ||
| Note: It cannot be active with RS485NMM operation mode. | ||
| [18] | RS485AUD | RS-485 Auto Direction Function (AUD) |
| 0 = RS-485 Auto Direction Operation function (AUD) Disabled. | ||
| 1 = RS-485 Auto Direction Operation function (AUD) Enabled. | ||
| Note: It can be active with RS485AAD or RS485NMM operation mode. | ||
| [19] | ADDRDEN | RS-485 Address Detection Enable Bit |
| This bit is used to enable RS-485 Address Detection mode. | ||
| 0 = Address detection mode Disabled. | ||
| 1 = Address detection mode Enabled. | ||
| Note: This bit is used for RS-485 any operation mode. | ||
| [31:24] | ADRMPID | Address / PID Match Value Register |
| When in the RS-485 Function Mode, this field contains the RS-485 address match values. | ||
| When in the LIN Function mode, this field contains the LIN protected identifier field, software fills ID0~ID5 (PID [5:0]), hardware will calculate P0 and P1. | ||
| Note: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID). |
| SC_T::ALTCTL |
[0x0008] SC Alternate Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TXRST | TX Software Reset |
| When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the TX internal state machine and pointers. | ||
| Note: This bit will be auto cleared after reset is complete. | ||
| [1] | RXRST | Rx Software Reset |
| When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the Rx internal state machine and pointers. | ||
| Note: This bit will be auto cleared after reset is complete. | ||
| [2] | DACTEN | Deactivation Sequence Generator Enable Bit |
| This bit enables SC controller to initiate the card by deactivation sequence | ||
| 0 = No effect. | ||
| 1 = Deactivation sequence generator Enabled. | ||
| Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1. | ||
| Note2: This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time. | ||
| Note3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [3] | ACTEN | Activation Sequence Generator Enable Bit |
| This bit enables SC controller to initiate the card by activation sequence | ||
| 0 = No effect. | ||
| 1 = Activation sequence generator Enabled. | ||
| Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0. | ||
| Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time. | ||
| Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [4] | WARSTEN | Warm Reset Sequence Generator Enable Bit |
| This bit enables SC controller to initiate the card by warm reset sequence | ||
| 0 = No effect. | ||
| 1 = Warm reset sequence generator Enabled. | ||
| Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0. | ||
| Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time. | ||
| Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [5] | CNTEN0 | Internal Timer0 Start Enable Bit |
| This bit enables Timer 0 to start counting | ||
| Software can fill 0 to stop it and set 1 to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Start counting. | ||
| Note1: This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 11,01,10. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware. | ||
| Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [6] | CNTEN1 | Internal Timer1 Start Enable Bit |
| This bit enables Timer 1 to start counting | ||
| Software can fill 0 to stop it and set 1 to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Start counting. | ||
| Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11 | ||
| Do not fill in CNTEN1 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware. | ||
| Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [7] | CNTEN2 | Internal Timer2 Start Enable Bit |
| This bit enables Timer 2 to start counting | ||
| Software can fill 0 to stop it and set 1 to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Start counting. | ||
| Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11 | ||
| Do not fill in CNTEN2 when TMRSEL(SC_CTL[14:13])= 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware. | ||
| Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [9:8] | INITSEL | Initial Timing Selection |
| This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation). | ||
| Unit: SC clock | ||
| Activation: Refer to SC Activation Sequence in Figure 6.15-4 SC Activation Sequence. | ||
| Warm-reset: Refer to Warm-Reset Sequence in Figure 6.15-5 SC Warm Reset Sequence | ||
| Deactivation: Refer to Deactivation Sequence in Figure 6.15-6 SC Deactivation Sequence | ||
| Note: When set Activation and Warm reset in mode 11, it may have deviation at most 128 cycles. | ||
| [12] | RXBGTEN | Receiver Block Guard Time Function Enable Bit |
| 0 = Receiver block guard time function Disabled. | ||
| 1 = Receiver block guard time function Enabled. | ||
| [13] | ACTSTS0 | Internal Timer0 Active State (Read Only) |
| This bit indicates the timer counter status of timer0. | ||
| 0 = Timer0 is not active. | ||
| 1 = Timer0 is active. | ||
| Note: Timer0 is active does not always mean timer0 is counting the CNT(SC_TMRCTL0[23:0]). | ||
| [14] | ACTSTS1 | Internal Timer1 Active State (Read Only) |
| This bit indicates the timer counter status of timer1. | ||
| 0 = Timer1 is not active. | ||
| 1 = Timer1 is active. | ||
| Note: Timer1 is active does not always mean timer1 is counting the CNT(SC_TMRCTL1[7:0]). | ||
| [15] | ACTSTS2 | Internal Timer2 Active State (Read Only) |
| This bit indicates the timer counter status of timer2. | ||
| 0 = Timer2 is not active. | ||
| 1 = Timer2 is active. | ||
| Note: Timer2 is active does not always mean timer2 is counting the CNT(SC_TMRCTL2[7:0]). | ||
| [16] | OUTSEL | Smartcard Data Pin Output Mode Selection |
| Use this bit to select smartcard data pin output mode. | ||
| 0 = Quasi mode. | ||
| 1 = Open-drain mode. |
| CLK_T::APBCLK |
[0x0008] APB Devices Clock Enable Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WDTCKEN | Watchdog Timer Clock Enable Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| This bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC. | ||
| 0 = Watchdog Timer Clock Disabled. | ||
| 1 = Watchdog Timer Clock Enabled. | ||
| [1] | RTCCKEN | Real-time-clock Clock Enable Control |
| This bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT. | ||
| 0 = Real-time-clock Clock Disabled. | ||
| 1 = Real-time-clock Clock Enabled. | ||
| [2] | TMR0CKEN | Timer0 Clock Enable Control |
| 0 = Timer0 Clock Disabled. | ||
| 1 = Timer0 Clock Enabled. | ||
| [3] | TMR1CKEN | Timer1 Clock Enable Control |
| 0 = Timer1 Clock Disabled. | ||
| 1 = Timer1 Clock Enabled. | ||
| [4] | TMR2CKEN | Timer2 Clock Enable Control |
| 0 = Timer2 Clock Disabled. | ||
| 1 = Timer2 Clock Enabled. | ||
| [5] | TMR3CKEN | Timer3 Clock Enable Control |
| 0 = Timer3 Clock Disabled. | ||
| 1 = Timer3 Clock Enabled. | ||
| [6] | CLKOCKEN | ClocK Output Clock Enable Control |
| 0 = Clock Output Clock Disabled. | ||
| 1 = Clock Output Clock Enabled. | ||
| [8] | I2C0CKEN | I2C0 Clock Enable Control |
| 0 = I2C0 Clock Disabled. | ||
| 1 = I2C0 Clock Enabled. | ||
| [9] | I2C1CKEN | I2C1 Clock Enable Control |
| 0 = I2C1 Clock Disabled. | ||
| 1 = I2C1 Clock Enabled. | ||
| [11] | ACMP0CKEN | ACMP0 Clock Enable Control |
| 0 = ACMP0 Clock Disabled. | ||
| 1 = ACMP0 Clock Enabled. | ||
| [12] | SPI0CKEN | SPI0 Clock Enable Control |
| 0 = SPI0 Clock Disabled. | ||
| 1 = SPI0 Clock Enabled. | ||
| [13] | SPI1CKEN | SPI1 Clock Enable Control |
| 0 = SPI1 Clock Disabled. | ||
| 1 = SPI1 Clock Enabled. | ||
| [14] | SPI2CKEN | SPI2 Clock Enable Control |
| 0 = SPI2 Clock Disabled. | ||
| 1 = SPI2 Clock Enabled. | ||
| [15] | SPI3CKEN | SPI3 Clock Enable Control |
| 0 = SPI3 Clock Disabled. | ||
| 1 = SPI3 Clock Enabled. | ||
| [16] | UART0CKEN | UART0 Clock Enable Control |
| 0 = UART0 Clock Disabled. | ||
| 1 = UART0 Clock Enabled. | ||
| [17] | UART1CKEN | UART1 Clock Enable Control |
| 0 = UART1 Clock Disabled. | ||
| 1 = UART1 Clock Enabled. | ||
| [20] | PWM0CKEN | PWM0 Clock Enable Control |
| 0 = PWM0 Clock Disabled. | ||
| 1 = PWM0 Clock Enabled. | ||
| [28] | ADCCKEN | Analog-digital-converter (ADC) Clock Enable Control |
| 0 = ADC Clock Disabled. | ||
| 1 = ADC Clock Enabled. | ||
| [30] | SC0CKEN | SmartCard 0 Clock Enable Control |
| 0 = SmartCard 0 Clock Disabled. | ||
| 1 = SmartCard 0 Clock Enabled. | ||
| [31] | SC1CKEN | SmartCard 1 Clock Enable Control |
| 0 = SmartCard 1 Clock Disabled. | ||
| 1 = SmartCard 1 Clock Enabled. |
| CLK_T::APBDIV |
[0x0034] APB Clock Divider
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | APB0DIV | APB0 Clock Divider |
| APB0 PCLK0 can be divided from HCLK. | ||
| 000: PCLK0 = HCLK. | ||
| 001: PCLK0 = 1/2 HCLK. | ||
| 010: PCLK0 = 1/4 HCLK. | ||
| 011: PCLK0 = 1/8 HCLK. | ||
| 100: PCLK0 = 1/16 HCLK. | ||
| Others: PCLK0 = HCLK. | ||
| [6:4] | APB1DIV | APB1 Clock Divider |
| APB1 PCLK1 can be divided from HCLK. | ||
| 000: PCLK1 = HCLK. | ||
| 001: PCLK1 = 1/2 HCLK. | ||
| 010: PCLK1 = 1/4 HCLK. | ||
| 011: PCLK1 = 1/8 HCLK. | ||
| 100: PCLK1 = 1/16 HCLK. | ||
| Others: PCLK1 = HCLK. |
| SYS_T::BATDIVCTL |
[0x0074] Battery Voltage Divider Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BATDIV2EN | Battery voltage divide 2 Enable Bit |
| This bit is used to enable/disable battery voltage divider function. | ||
| 0 = Battery voltage divide 2 function Disabled (default). | ||
| 1 = Battery voltage divide 2 function Enabled. |
| UART_T::BAUD |
[0x0024] UART Baud Rate Divisor Register.
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | BRD | Baud Rate Divider |
| The field indicates the baud rate divider | ||
| This filed is used in baud rate calculation | ||
| The detail description is shown in UART Controller Baud Rate Generation. | ||
| [31] | DIV16EN | Divider 16 Enable Control |
| The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = UART_CLK/ [M * (BRD + 1)]; The default value of M is 16. | ||
| 0 = The equation of baud rate is UART_CLK / [ (BRD+1)]. | ||
| 1 = The equation of baud rate is UART_CLK / [16 * (BRD+1)]. | ||
| Note: In IrDA mode, this bit must clear to 0. |
| PWM_T::BNF |
[0x00c0] PWM0 Brake Noise Filter Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BRK0FEN | PWM0 Brake 0 Noise Filter Enable Bit |
| 0 = Noise filter of PWM0 Brake 0 Disabled. | ||
| 1 = Noise filter of PWM0 Brake 0 Enabled. | ||
| [3:1] | BRK0FCS | Brake 0 Edge Detector Filter Clock Selection |
| 000 = Filter clock = HCLK. | ||
| 001 = Filter clock = HCLK/2. | ||
| 010 = Filter clock = HCLK/4. | ||
| 011 = Filter clock = HCLK/8. | ||
| 100 = Filter clock = HCLK/16. | ||
| 101 = Filter clock = HCLK/32. | ||
| 110 = Filter clock = HCLK/64. | ||
| 111 = Filter clock = HCLK/128. | ||
| [6:4] | BRK0FCNT | Brake 0 Edge Detector Filter Count |
| The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. | ||
| [7] | BRK0PINV | Brake 0 Pin Inverse |
| 0 = The state of pin PWMx_BRAKE0 is passed to the negative edge Detector. | ||
| 1 = The inversed state of pin PWMx_BRAKE10 is passed to the negative edge Detector. | ||
| [8] | BRK1FEN | PWM0 Brake 1 Noise Filter Enable Bit |
| 0 = Noise filter of PWM0 Brake 1 Disabled. | ||
| 1 = Noise filter of PWM0 Brake 1 Enabled. | ||
| [11:9] | BRK1FCS | Brake 1 Edge Detector Filter Clock Selection |
| 000 = Filter clock = HCLK. | ||
| 001 = Filter clock = HCLK/2. | ||
| 010 = Filter clock = HCLK/4. | ||
| 011 = Filter clock = HCLK/8. | ||
| 100 = Filter clock = HCLK/16. | ||
| 101 = Filter clock = HCLK/32. | ||
| 110 = Filter clock = HCLK/64. | ||
| 111 = Filter clock = HCLK/128. | ||
| [14:12] | BRK1FCNT | Brake 1 Edge Detector Filter Count |
| The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. | ||
| [15] | BRK1PINV | Brake 1 Pin Inverse |
| 0 = The state of pin PWMx_BRAKE1 is passed to the negative edge Detector. | ||
| 1 = The inversed state of pin PWMx_BRAKE1 is passed to the negative edge Detector. | ||
| [16] | BK0SRC | Brake 0 Pin Source Select |
| For PWM0 setting: | ||
| 0 = Brake 0 pin source come from PWM0_BRAKE0. | ||
| 1 = Brake 0 pin source come from PWM1_BRAKE0. | ||
| For PWM1 setting: | ||
| 0 = Brake 0 pin source come from PWM1_BRAKE0. | ||
| 1 = Brake 0 pin source come from PWM0_BRAKE0. | ||
| [24] | BK1SRC | Brake 1 Pin Source Select |
| For PWM0 setting: | ||
| 0 = Brake 1 pin source come from PWM0_BRAKE1. | ||
| 1 = Brake 1 pin source come from PWM1_BRAKE1. | ||
| For PWM1 setting: | ||
| 0 = Brake 1 pin source come from PWM1_BRAKE1. | ||
| 1 = Brake 1 pin source come from PWM0_BRAKE1. |
| SYS_T::BODCTL |
[0x0064] Brown-out Detector Controller Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BODEN | Brown-out Detector Enable Bit (Write Protect) |
| The default value is set by flash controller user configuration register CBODEN (CONFIG0 []) | ||
| This Brown-out Detector only valid in Normal Mode. | ||
| 0 = Brown-out Detector function Disabled in Normal mode. | ||
| 1 = Brown-out Detector function Enabled in Normal mode. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: LIRC must be enabled before enable BOD. | ||
| [2] | BODIE | BOD Interrupt Enable Control (Write Protect) |
| 0 = Interrupt does not issue when BOD occurs in Normal Mode. | ||
| 1 = Interrupt issues when BOD occurs in Normal Mode. | ||
| Note1: While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. | ||
| Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [3] | BODREN | Brown-out Reset Enable Bit (Write Protect) |
| The default value is set by flash controller user configuration register CBOV(CONFIG0[]) bit . | ||
| 0 = Brown-out RESET function Disabled in Normal Mode. | ||
| 1 = Brown-out RESET function Enabled in Normal Mode. | ||
| Note1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). | ||
| Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [4] | BODIF | Brown-out Detector Interrupt Flag |
| 0 = Brown-out Detector does not detect any voltage drift at VDD down through or up through the target detected voltage after interrupt is enabled. | ||
| 1 = When Brown-out Detector detects the VDD is dropped down through the target detected voltage or the VDD is raised up through the target detected voltage, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [6] | BODOUT | Brown-out Detector Output Status |
| 0 = Brown-out Detector output status is 0. | ||
| It means the detected voltage is higher than BODVL setting or BODEN is 0. | ||
| 1 = Brown-out Detector output status is 1. | ||
| It means the detected voltage is lower than BODVL setting | ||
| If the BODEN is 0, BOD function disabled , this bit always responds 0. | ||
| Note: This bit is ready-only. | ||
| [7] | LVREN | Low Voltage Reset Enable Bit (Write Protect) |
| The LVR function resets the chip when the input power voltage is lower than LVR circuit setting | ||
| LVR function is enabled by default. | ||
| 0 = Low Voltage Reset function Disabled. | ||
| 1 = Low Voltage Reset function Enabled. | ||
| Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). | ||
| Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note3: LIRC must be enabled before enable LVR. | ||
| [8] | LPBODEN | Low Power Brown-out Detector Enable Bit (Write Protect) |
| Low Power Brown-out Detector only valid in Power Down mode. | ||
| 0 = Low Power Brown-out Detector function Disabled in Power Down mode. | ||
| 1 = Low Power Brown-out Detector function Enabled in Power Down mode. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: LIRC must be enabled before enable BOD. | ||
| [9] | LPBODVL | Low Power Brown-out Detector Threshold Voltage Selection (Write Protect) |
| Low Power Brown-out Detector only valid in Power Down mode. | ||
| 0 = Low Power Brown-Out Detector threshold voltage is 2.0V in Power Down mode. | ||
| 1 = Low Power Brown-Out Detector threshold voltage is 2.5V in Power Down mode. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [10] | LPBODIE | Low Power BOD Interrupt Enable Control (Write Protect) |
| Low Power Brown-out Detector only valid in Power Down mode. | ||
| 0 = Interrupt does not issue when LPBOD occurs in Power Down mode. | ||
| 1 = Interrupt issues when LPBOD occurs in Power Down mode | ||
| Note1: While the LPBOD function is enabled (LPBODEN high) and LPBOD interrupt function is enabled (LPBODIE high), LPBOD will assert an interrupt if BODOUT is high | ||
| Note2: This bit is write protected | ||
| Refer to the SYS_REGLCTL register. | ||
| [11] | LPBODREN | Low Power Brown-out Reset Enable Bit (Write Protect) |
| Low Power Brown-out Detector only valid in Power Down mode. | ||
| 0 = Low power Brown-out Detector RESET function Disabled in Power Down mode. | ||
| 1 = Low Power Brown-out Detector RESET function Enabled in Power Down mode. | ||
| Note1: While the Low power Brown-out Detector function is enabled (LPBODEN high) and LPBOD reset function is enabled (LPBODREN high), LPBOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). | ||
| Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [15:12] | BODVL | Brown-out Detector Threshold Voltage Selection (Write Protect) |
| The default value is set by flash controller user configuration register CBOV (CONFIG0[]). | ||
| 0000 = Brown-Out Detector threshold voltage is 1.7V. | ||
| 0001 = Brown-Out Detector threshold voltage is 1.8V. | ||
| 0010 = Brown-Out Detector threshold voltage is 1.9V. | ||
| 0011 = Brown-Out Detector threshold voltage is 2.0V. | ||
| 0100 = Brown-Out Detector threshold voltage is 2.1V. | ||
| 0101 = Brown-Out Detector threshold voltage is 2.2V. | ||
| 0110 = Brown-Out Detector threshold voltage is 2.3V. | ||
| 0111 = Brown-Out Detector threshold voltage is 2.4V. | ||
| 1000 = Brown-Out Detector threshold voltage is 2.5V. | ||
| 1001 = Brown-Out Detector threshold voltage is 2.6V. | ||
| 1010 = Brown-Out Detector threshold voltage is 2.7V. | ||
| 1011 = Brown-Out Detector threshold voltage is 2.8V. | ||
| 1100 = Brown-Out Detector threshold voltage is 2.9V. | ||
| 1101 = Brown-Out Detector threshold voltage is 3.0V. | ||
| 1110 = Brown-Out Detector threshold voltage is 3.1V. | ||
| 1111 = Reserved. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [19:16] | LPBOD20TRIM | Low power BOD 2.0 TRIM Value (Write Protect) |
| This value is used to control BOD20 detect voltage level in power-down mode, nominal 2.0 V | ||
| Higher trim value, higher detection voltage. | ||
| Note: These bits are write protected. Refer to the SYS_REGLCTL register. | ||
| [23:20] | LPBOD25TRIM | Low power BOD 2.5 TRIM Value (Write Protect) |
| This value is used to control LPBOD25 detect voltage level in power-down mode, nominal 2.5 V | ||
| Higher trim value, higher detection voltage. | ||
| Note: These bits are write protected. Refer to the SYS_REGLCTL register. | ||
| [26:24] | BODDGSEL | Brown-out Detector Output De-glitch Time Select (Write Protect) |
| 000 = BOD output is sampled by RC10K clock. | ||
| 001 = 4 system clock (HCLK). | ||
| 010 = 8 system clock (HCLK). | ||
| 011 = 16 system clock (HCLK). | ||
| 100 = 32 system clock (HCLK). | ||
| 101 = 64 system clock (HCLK). | ||
| 110 = 128 system clock (HCLK). | ||
| 111 = 256 system clock (HCLK). | ||
| Note: These bits are write protected. Refer to the SYS_REGLCTL register. | ||
| [30:28] | LVRDGSEL | LVR Output De-glitch Time Select (Write Protect) |
| 000 = Without de-glitch function. | ||
| 001 = 4 system clock (HCLK). | ||
| 010 = 8 system clock (HCLK). | ||
| 011 = 16 system clock (HCLK). | ||
| 100 = 32 system clock (HCLK). | ||
| 101 = 64 system clock (HCLK). | ||
| 110 = 128 system clock (HCLK). | ||
| 111 = 256 system clock (HCLK). | ||
| Note: These bits are write protected. Refer to the SYS_REGLCTL register. |
| UART_T::BRCOMPAT |
[0x003c] UART Baud Rate Compensation Register.
| Bits | Field | Descriptions |
|---|---|---|
| [8:0] | BRCOMPAT | Baud Rate Compensation Patten |
| These 9 bits are used to define the relative bit is compensated or not | ||
| BRCOMPAT[7:0] is used to define the compensation of D[7:0] and BRCOMPAT{[8] is used to define the parity bit. | ||
| [31] | BRCOMPDEC | Baud Rate Compensation Decrease |
| 0 = Positive (increase one module clock) compensation for each compensated bit. | ||
| 1 = Negative (decrease one module clock) compensation for each compensated bit. |
| PWM_T::BRKCTL0_1 |
[0x00c8] PWM0 Brake Edge Detect Control Register 0_1
| Bits | Field | Descriptions |
|---|---|---|
| [4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) |
| 0 = BKP0 pin as edge-detect brake source Disabled. | ||
| 1 = BKP0 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) |
| 0 = BKP1 pin as edge-detect brake source Disabled. | ||
| 1 = BKP1 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [7] | SYSEEN | Enable System Fail As Edge-detect Brake Source (Write Protect) |
| 0 = System Fail condition as edge-detect brake source Disabled. | ||
| 1 = System Fail condition as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [12] | BRKP0LEN | Enable BKP0 Pin As Level-detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [13] | BRKP1LEN | Enable BKP1 Pin As Level-detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [15] | SYSLEN | Enable System Fail As Level-detect Brake Source (Write Protect) |
| 0 = System Fail condition as level-detect brake source Disabled. | ||
| 1 = System Fail condition as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [17:16] | BRKAEVEN | PWM0 Brake Action Select for Even Channel (Write Protect) |
| 00 = PWM0 even channel brake function not affect channel output. | ||
| 01 = PWM0 even channel output tri-state when brake happened. | ||
| 10 = PWM0 even channel output low level when brake happened. | ||
| 11 = PWM0 even channel output high level when brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [19:18] | BRKAODD | PWM0 Brake Action Select for Odd Channel (Write Protect) |
| 00 = PWM0 odd channel brake function not affect channel output. | ||
| 01 = PWM0 odd channel output tri-state when brake happened. | ||
| 10 = PWM0 odd channel output low level when brake happened. | ||
| 11 = PWM0 odd channel output high level when brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| PWM_T::BRKCTL2_3 |
[0x00cc] PWM0 Brake Edge Detect Control Register 2_3
| Bits | Field | Descriptions |
|---|---|---|
| [4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) |
| 0 = BKP0 pin as edge-detect brake source Disabled. | ||
| 1 = BKP0 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) |
| 0 = BKP1 pin as edge-detect brake source Disabled. | ||
| 1 = BKP1 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [7] | SYSEEN | Enable System Fail As Edge-detect Brake Source (Write Protect) |
| 0 = System Fail condition as edge-detect brake source Disabled. | ||
| 1 = System Fail condition as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [12] | BRKP0LEN | Enable BKP0 Pin As Level-detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [13] | BRKP1LEN | Enable BKP1 Pin As Level-detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [15] | SYSLEN | Enable System Fail As Level-detect Brake Source (Write Protect) |
| 0 = System Fail condition as level-detect brake source Disabled. | ||
| 1 = System Fail condition as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [17:16] | BRKAEVEN | PWM0 Brake Action Select for Even Channel (Write Protect) |
| 00 = PWM0 even channel brake function not affect channel output. | ||
| 01 = PWM0 even channel output tri-state when brake happened. | ||
| 10 = PWM0 even channel output low level when brake happened. | ||
| 11 = PWM0 even channel output high level when brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [19:18] | BRKAODD | PWM0 Brake Action Select for Odd Channel (Write Protect) |
| 00 = PWM0 odd channel brake function not affect channel output. | ||
| 01 = PWM0 odd channel output tri-state when brake happened. | ||
| 10 = PWM0 odd channel output low level when brake happened. | ||
| 11 = PWM0 odd channel output high level when brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| PWM_T::BRKCTL4_5 |
[0x00d0] PWM0 Brake Edge Detect Control Register 4_5
| Bits | Field | Descriptions |
|---|---|---|
| [4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) |
| 0 = BKP0 pin as edge-detect brake source Disabled. | ||
| 1 = BKP0 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) |
| 0 = BKP1 pin as edge-detect brake source Disabled. | ||
| 1 = BKP1 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [7] | SYSEEN | Enable System Fail As Edge-detect Brake Source (Write Protect) |
| 0 = System Fail condition as edge-detect brake source Disabled. | ||
| 1 = System Fail condition as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [12] | BRKP0LEN | Enable BKP0 Pin As Level-detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [13] | BRKP1LEN | Enable BKP1 Pin As Level-detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [15] | SYSLEN | Enable System Fail As Level-detect Brake Source (Write Protect) |
| 0 = System Fail condition as level-detect brake source Disabled. | ||
| 1 = System Fail condition as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [17:16] | BRKAEVEN | PWM0 Brake Action Select for Even Channel (Write Protect) |
| 00 = PWM0 even channel brake function not affect channel output. | ||
| 01 = PWM0 even channel output tri-state when brake happened. | ||
| 10 = PWM0 even channel output low level when brake happened. | ||
| 11 = PWM0 even channel output high level when brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [19:18] | BRKAODD | PWM0 Brake Action Select for Odd Channel (Write Protect) |
| 00 = PWM0 odd channel brake function not affect channel output. | ||
| 01 = PWM0 odd channel output tri-state when brake happened. | ||
| 10 = PWM0 odd channel output low level when brake happened. | ||
| 11 = PWM0 odd channel output high level when brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| RTC_T::CAL |
[0x0010] RTC Calendar Loading Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | DAY | 1-Day Calendar Digit (0~9) |
| [5:4] | TENDAY | 10-Day Calendar Digit (0~3) |
| [11:8] | MON | 1-Month Calendar Digit (0~9) |
| [12] | TENMON | 10-Month Calendar Digit (0~1) |
| [19:16] | YEAR | 1-Year Calendar Digit (0~9) |
| [23:20] | TENYEAR | 10-Year Calendar Digit (0~9) |
| ADC_T::CALCTL |
[0x0068] A/D Calibration Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CALEN | Calibration Function Enable Bit |
| Enable this bit to turn on the calibration function block. | ||
| 0 = Bypass calibration functional block. | ||
| 1 = Enabled calibration functional block. | ||
| [1] | CALSTART | Calibration Functional Block Start |
| 0 = Stops calibration functional block. | ||
| 1 = Starts calibration functional block. | ||
| Note: This bit is set by software and cleared by hardware; don't write 1 to this bit while CALEN (ADC_CALCTL[0]) = 0. | ||
| [2] | CALDONE | Calibrate Functional Block Done |
| 0 = Not yet. | ||
| 1 = Selected calibration functional block complete. | ||
| Note: This bit is set by hardware and auto cleared by hardware, This bit can also be cleared by software writing 1. | ||
| [3] | CALSEL | Calibration Functional Block Selection |
| 0 = Load calibration functional block. | ||
| 1 = Calibration functional block. |
| RTC_T::CALM |
[0x0020] RTC Calendar Alarm Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | DAY | 1-Day Calendar Digit of Alarm Setting (0~9) |
| [5:4] | TENDAY | 10-Day Calendar Digit of Alarm Setting (0~3) |
| [11:8] | MON | 1-Month Calendar Digit of Alarm Setting (0~9) |
| [12] | TENMON | 10-Month Calendar Digit of Alarm Setting (0~1) |
| [19:16] | YEAR | 1-Year Calendar Digit of Alarm Setting (0~9) |
| [23:20] | TENYEAR | 10-Year Calendar Digit of Alarm Setting (0~9) |
| ADC_T::CALWORD |
[0x006c] A/D Calibration Load word Register
| Bits | Field | Descriptions |
|---|---|---|
| [6:0] | CALWORD | Calibration Word Bits |
| Write to this register with the previous calibration word before load calibration action, read this register after calibration done. | ||
| Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the loaded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. |
| RTC_T::CAMSK |
[0x0038] RTC Calendar Alarm Mask Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | MDAY | Mask 1-Day Calendar Digit of Alarm Setting (0~9) |
| [1] | MTENDAY | Mask 10-Day Calendar Digit of Alarm Setting (0~3) |
| [2] | MMON | Mask 1-Month Calendar Digit of Alarm Setting (0~9) |
| [3] | MTENMON | Mask 10-Month Calendar Digit of Alarm Setting (0~1) |
| [4] | MYEAR | Mask 1-Year Calendar Digit of Alarm Setting (0~9) |
| [5] | MTENYEAR | Mask 10-Year Calendar Digit of Alarm Setting (0~9) |
| TIMER_T::CAP |
[0x0018] Timer Capture Data Register
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CAPDAT | Timer Capture Data Register |
| When CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 0, and the transition on Tx_EXT pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. | ||
| When CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 1, and the transition on Tx_EXT pin matched the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. | ||
| Note: When edge transition defined by CAPEDGE (TIMERx_CTL[19:18]) is detected on Tx_EXT (x = 0 ~ 3) before CPU clears the CAPIF (TIMERxISR[1]) status, the timer keeps this value unchanged and CAPDATOF (TIMERx_INTSTS[5]) is set to 1. |
| PWM_T::CAPCTL |
[0x0204] PWM0 Capture Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CAPENn | Capture Function Enable Bits |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. | ||
| 1 = Capture function Enabled | ||
| Capture latched the PWM0 counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). | ||
| [13:8] | CAPINVn | Capture Inverter Enable Bits |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = Capture source inverter Disabled. | ||
| 1 = Capture source inverter Enabled. Reverse the input signal from GPIO. | ||
| [21:16] | RCRLDENn | Rising Capture Reload Enable Bits |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = Rising capture reload counter Disabled. | ||
| 1 = Rising capture reload counter Enabled. | ||
| [29:24] | FCRLDENn | Falling Capture Reload Enable Bits |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = Falling capture reload counter Disabled. | ||
| 1 = Falling capture reload counter Enabled. |
| PWM_T::CAPIEN |
[0x0250] PWM0 Capture Interrupt Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CAPRIENn | PWM0 Capture Rising Latch Interrupt Enable Bits |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = Capture rising edge latch interrupt Disabled. | ||
| 1 = Capture rising edge latch interrupt Enabled. | ||
| [13:8] | CAPFIENn | PWM0 Capture Falling Latch Interrupt Enable Bits |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = Capture falling edge latch interrupt Disabled. | ||
| 1 = Capture falling edge latch interrupt Enabled. |
| PWM_T::CAPIF |
[0x0254] PWM0 Capture Interrupt Flag Register
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CAPRIFn | PWM0 Capture Rising Latch Interrupt Flag |
| This bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = No capture rising latch condition happened. | ||
| 1 = Capture rising latch condition happened, this flag will be set to high. | ||
| [13:8] | CAPFIFn | PWM0 Capture Falling Latch Interrupt Flag |
| This bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = No capture falling latch condition happened. | ||
| 1 = Capture falling latch condition happened, this flag will be set to high. |
| PWM_T::CAPINEN |
[0x0200] PWM0 Capture Input Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CAPINENn | Capture Input Enable Bits |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = PWM0 Channel capture input path Disabled | ||
| The input of PWM0 channel capture function is always regarded as 0. | ||
| 1 = PWM0 Channel capture input path Enabled | ||
| The input of PWM0 channel capture function comes from correlative multifunction pin. |
| PWM_T::CAPSTS |
[0x0208] PWM0 Capture Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CRIFOVn | Capture Rising Interrupt Flag Overrun Status (Read Only) |
| This flag indicates if rising latch happened when the corresponding CAPRIF is 1 | ||
| Each bit n controls the corresponding PWM0 channel n. | ||
| Note: This bit will be cleared automatically when user clear corresponding CAPRIF. | ||
| [13:8] | CFIFOVn | Capture Falling Interrupt Flag Overrun Status (Read Only) |
| This flag indicates if falling latch happened when the corresponding CAPFIF is 1 | ||
| Each bit n controls the corresponding PWM0 channel n. | ||
| Note: This bit will be cleared automatically when user clear corresponding CAPFIF. |
| PDMA_CH_T::CCNTn |
[0x001c] PDMA channel n Current Transfer Count Register
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CCNT | PDMA Current Count Bits (Read Only) |
| This field indicates the current remained transfer count of PDMA. | ||
| Note: This field value will be cleared to 0 when user sets SWRST (PDMA_CTLn[1],n=1~4) to 1. |
| PDMA_CH_T::CDAn |
| CLK_T::CDLOWB |
[0x0048] Clock Frequency Detector Lower Boundary Register
| Bits | Field | Descriptions |
|---|---|---|
| [10:0] | LOWERBD | HXT Clock Frequency Detector Lower Boundary |
| The bits define the low value of frequency monitor window. | ||
| When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. |
| CLK_T::CDUPB |
[0x0044] Clock Frequency Detector Upper Boundary Register
| Bits | Field | Descriptions |
|---|---|---|
| [10:0] | UPERBD | HXT Clock Frequency Detector Upper Boundary |
| The bits define the high value of frequency monitor window. | ||
| When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. |
| DMA_CRC_T::CHECKSUM |
| ADC_T::CHEN |
[0x004c] A/D Channel Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CHEN0 | Analog Input Channel 0 Enable Bit (Convert Input Voltage From PA.0 ) |
| 0 = Channel 0 Disabled. | ||
| 1 = Channel 0 Enabled. | ||
| Note: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored. | ||
| [1] | CHEN1 | Analog Input Channel 1 Enable Bit (Convert Input Voltage From PA.1 ) |
| 0 = Channel 1 Disabled. | ||
| 1 = Channel 1 Enabled. | ||
| [2] | CHEN2 | Analog Input Channel 2 Enable Bit (Convert Input Voltage From PA.2 ) |
| 0 = Channel 2 Disabled. | ||
| 1 = Channel 2 Enabled. | ||
| [3] | CHEN3 | Analog Input Channel 3 Enable Bit (Convert Input Voltage From PA.3 ) |
| 0 = Channel 3 Disabled. | ||
| 1 = Channel 3 Enabled. | ||
| [4] | CHEN4 | Analog Input Channel 4 Enable Bit (Convert Input Voltage From PA.4 ) |
| 0 = Channel 4 Disabled. | ||
| 1 = Channel 4 Enabled. | ||
| [5] | CHEN5 | Analog Input Channel 5 Enable Bit (Convert Input Voltage From PA.5 ) |
| 0 = Channel 5 Disabled. | ||
| 1 = Channel 5 Enabled. | ||
| [6] | CHEN6 | Analog Input Channel 6 Enable Bit (Convert Input Voltage From PA.6 ) |
| 0 = Channel 6 Disabled. | ||
| 1 = Channel 6 Enabled. | ||
| [7] | CHEN7 | Analog Input Channel 7 Enable Bit (Convert Input Voltage From PA.7 ) |
| 0 = Channel 7 Disabled. | ||
| 1 = Channel 7 Enabled. | ||
| [12] | CHEN12 | Analog Input Channel 12 Enable Bit (Convert VBG) |
| 0 = Channel 12 Disabled. | ||
| 1 = Channel 12 Enabled. | ||
| [13] | CHEN13 | Analog Input Channel 13 Enable Bit (Convert VBAT) |
| 0 = Channel 13 Disabled. | ||
| 1 = Channel 13 Enabled. | ||
| [14] | CHEN14 | Analog Input Channel 14 Enable Bit (Convert VTEMP) |
| 0 = Channel 14 Disabled. | ||
| 1 = Channel 14 Enabled. | ||
| [15] | CHEN15 | Analog Input Channel 15 Enable Bit (Convert Int_VREF) |
| 0 = Channel 15 Disabled. | ||
| 1 = Channel 15 Enabled. | ||
| [16] | CHEN16 | Analog Input Channel 16 Enable Bit (Convert AVDD) |
| 0 = Channel 16 Disabled. | ||
| 1 = Channel 16 Enabled. | ||
| [17] | CHEN17 | Analog Input Channel 17 Enable Bit (Convert AVSS) |
| 0 = Channel 17 Disabled. | ||
| 1 = Channel 17 Enabled. |
| CLK_T::CLKDCTL |
[0x0038] Clock Fail Detector Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXTFDEN | HXT Clock Fail Detector Enable Bit |
| 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail Detector Disabled. | ||
| 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail Detector Enabled. | ||
| [1] | LXTFDEN | LXT Clock Fail Detector Enable Bit |
| 0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail Detector Disabled. | ||
| 1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail Detector Enabled. | ||
| [2] | HXTFQDEN | HXT Clock Frequency Monitor Enable Bit |
| 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled. | ||
| 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled. |
| CLK_T::CLKDIE |
[0x003c] Clock Fail Detector Interrupt Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXTFIEN | HXT Clock Fail Interrupt Enable Bit |
| 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. | ||
| 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. | ||
| [1] | LXTFIEN | LXT Clock Fail Interrupt Enable Bit |
| 0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. | ||
| 1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. | ||
| [2] | HXTFQIEN | HXT Clock Frequency Monitor Interrupt Enable Bit |
| 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled. | ||
| 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled. |
| I2C_T::CLKDIV |
| SPI_T::CLKDIV |
[0x0008] SPI Clock Divider Register
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DIVIDER | Clock Divider |
| The value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_CLK | ||
| The desired frequency is obtained according to the following equation: | ||
| Where | ||
| is the SPI peripheral clock source | ||
| It is defined in the CLK_SEL2[21:20] in Clock control section (CLK_BA + 0x18). |
| CLK_T::CLKDIV0 |
[0x001c] Clock Divider Number Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | HCLKDIV | HCLK Clock Divide Number From HCLK Clock Source |
| HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). | ||
| [11:8] | UART0DIV | UART0 Clock Divide Number From UART Clock Source |
| The UART0 clock frequency = (UART0 Clock Source frequency) / (UART0DIV + 1). | ||
| [15:12] | UART1DIV | UART1 Clock Divide Number From UART Clock Source |
| The UART1 clock frequency = (UART1 Clock Source frequency) / (UART1DIV + 1). | ||
| [23:16] | ADCDIV | ADC Clock Divide Number From ADC Clock Source |
| ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1). | ||
| [31:28] | SC0DIV | SC0 Clock Divide Number From SC0 Clock Source |
| SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). |
| CLK_T::CLKDIV1 |
[0x0020] Clock Divider Number Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | SC1DIV | SC 1 Clock Divide Number From SC 1 Clock Source |
| The SC 1 clock frequency = (SC 1 Clock Source frequency) / (SC1DIV + 1). | ||
| [11:8] | TMR0DIV | Timer0 Clock Divide Number From Timer0 Clock Source |
| The Timer0 clock frequency = (Timer0 Clock Source frequency) / (TMR0DIV + 1). | ||
| [15:12] | TMR1DIV | Timer1 Clock Divide Number From Timer1 Clock Source |
| The Timer1 clock frequency = (Timer1 Clock Source frequency) / (TMR1DIV + 1). | ||
| [19:16] | TMR2DIV | Timer2 Clock Divide Number From Timer2 Clock Source |
| The Timer2 clock frequency = (Timer2 Clock Source frequency) / (TMR2DIV + 1). | ||
| [23:20] | TMR3DIV | Timer3 Clock Divide Number From Timer3 Clock Source |
| The Timer3 clock frequency = (Timer3 Clock Source frequency) / (TMR3DIV + 1). |
| CLK_T::CLKDSTS |
[0x0040] Clock Fail Detector Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXTFIF | HXT Clock Fail Interrupt Flag |
| 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock is normal. | ||
| 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock stops. | ||
| Note: Write 1 to clear the bit to 0. | ||
| [1] | LXTFIF | LXT Clock Fail Interrupt Flag |
| 0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. | ||
| 1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. | ||
| Note: Write 1 to clear the bit to 0. | ||
| [2] | HXTFQIF | HXT Clock Frequency Monitor Interrupt Flag |
| 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock is normal. | ||
| 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. | ||
| Note: Write 1 to clear the bit to 0. |
| RTC_T::CLKFMT |
[0x0014] RTC Time Scale Selection Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | 24HEN | 24-hour / 12-hour Time Scale Selection |
| Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale | ||
| 0 = 12-hour time scale with AM and PM indication selected. | ||
| 1 = 24-hour time scale selected. |
| CLK_T::CLKOCTL |
[0x0028] Clock Output Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | FREQSEL | Clock Output Frequency Selection |
| The formula of output frequency is | ||
| Fout = Fin/2(N+1). | ||
| Fin is the input clock frequency. | ||
| Fout is the frequency of divider output clock. | ||
| N is the 4-bit value of FREQSEL[3:0]. | ||
| [4] | CLKOEN | Clock Output Enable Bit |
| 0 = Clock Output function Disabled. | ||
| 1 = Clock Output function Enabled. | ||
| [5] | DIV1EN | Clock Output Divide One Enable Bit |
| 0 = Clock Output will output clock with source frequency divided by FREQSEL. | ||
| 1 = Clock Output will output clock with source frequency. |
| PWM_T::CLKPSC0_1 |
[0x0014] PWM0 Clock Pre-Scale Register 0_1
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | CLKPSC | PWM0 Counter Clock Pre-scale |
| The clock of PWM0 counter is decided by clock prescaler | ||
| Each PWM0 pair share one PWM0 counter clock prescaler | ||
| The clock of PWM0 counter is divided by (CLKPSC+ 1) |
| PWM_T::CLKPSC2_3 |
[0x0018] PWM0 Clock Pre-Scale Register 2_3
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | CLKPSC | PWM0 Counter Clock Pre-scale |
| The clock of PWM0 counter is decided by clock prescaler | ||
| Each PWM0 pair share one PWM0 counter clock prescaler | ||
| The clock of PWM0 counter is divided by (CLKPSC+ 1) |
| PWM_T::CLKPSC4_5 |
[0x001c] PWM0 Clock Pre-Scale Register 4_5
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | CLKPSC | PWM0 Counter Clock Pre-scale |
| The clock of PWM0 counter is decided by clock prescaler | ||
| Each PWM0 pair share one PWM0 counter clock prescaler | ||
| The clock of PWM0 counter is divided by (CLKPSC+ 1) |
| CLK_T::CLKSEL0 |
[0x0010] Clock Source Select Control Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | HCLKSEL | HCLK Clock Source Selection (Write Protect) |
| Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. | ||
| 000 = Clock source from HXT. | ||
| 001 = Clock source from LXT. | ||
| 010 = Clock source from PLL. | ||
| 011 = Clock source from LIRC. | ||
| 100= Clock source from HIRC1 or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| Others = Clock source from MIRC. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [3] | HIRCSEL | HIRC Source Selection |
| 0 = Clock source from HIRC0 (12~16MHz). | ||
| 1 = Clock source from HIRC1 (36MHz). | ||
| [4] | ISPSEL | ISP Clock Source Selection |
| 0 = Clock source from HIRC1 or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| 1 = Clock source from MIRC. |
| CLK_T::CLKSEL1 |
[0x0014] Clock Source Select Control Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | UART0SEL | UART0 Clock Source Selection |
| 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
| 010 = Clock source from PLL. | ||
| 011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| Others = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
| [4] | PWM0SEL | PWM0 Clock Source Selection |
| 0 = Clock source from PLL. | ||
| 1 = Clock source from PCLK0. | ||
| [10:8] | TMR0SEL | Timer0 Clock Source Selection |
| 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
| 010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). | ||
| 011 = Clock source from external clock pin. | ||
| 100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| 101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
| Others = Clock source from HCLK. | ||
| [14:12] | TMR1SEL | Timer1 Clock Source Selection |
| 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
| 010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). | ||
| 011 = Clock source from external clock pin. | ||
| 100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| 101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
| Others = Clock source from HCLK. | ||
| [21:19] | ADCSEL | ADC Clock Source Selection |
| 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
| 010 = Clock source from PLL. | ||
| 011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| 100 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
| Others = Clock source from HCLK. | ||
| [25:24] | SPI0SEL | SPI0 Clock Source Selection |
| 00 = Clock source from PLL. | ||
| 01 = Clock source from HCLK. | ||
| 10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| [27:26] | SPI2SEL | SPI2 Clock Source Selection |
| 00 = Clock source from PLL. | ||
| 01 = Clock source from HCLK. | ||
| 10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| [29:28] | WDTSEL | WDT Clock Source Selection |
| 00 = reserved. | ||
| 01 = Clock source from LXT. | ||
| 10 = Clock source from HCLK/2048. | ||
| 11 = Clock source from LIRC | ||
| [31:30] | WWDTSEL | WDT Clock Source Selection |
| 00 = reserved. | ||
| 01 = reserved. | ||
| 10 = Clock source from HCLK/2048. | ||
| 11 = Clock source from LIRC |
| CLK_T::CLKSEL2 |
[0x0018] Clock Source Select Control Register 2
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | UART1SEL | UART1 Clock Source Selection |
| 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
| 010 = Clock source from PLL. | ||
| 011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| Others = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
| [6:4] | CLKOSEL | Clock Divider Clock Source Selection |
| 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
| 010 = Clock source from HCLK. | ||
| 011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| Others = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
| [10:8] | TMR2SEL | Timer2 Clock Source Selection |
| 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
| 010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). | ||
| 011 = Clock source from external clock pin. | ||
| 100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| 101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC) | ||
| Others = Clock source from HCLK. | ||
| [14:12] | TMR3SEL | Timer3 Clock Source Selection |
| 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
| 010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). | ||
| 011 = Clock source from external clock pin. | ||
| 100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| 101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
| Others = Clock source from HCLK. | ||
| [18:16] | SC0SEL | SC0 Clock Source Selection |
| 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 001 = Clock source from PLL. | ||
| 010 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| 011 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
| Others = Clock source from HCLK. | ||
| [22:20] | SC1SEL | SC1 Clock Source Selection |
| 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 001 = Clock source from PLL. | ||
| 010 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| 011 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). | ||
| Others = Clock source from HCLK. | ||
| [25:24] | SPI1SEL | SPI1 Clock Source Selection |
| 00 = Clock source from PLL. | ||
| 01 = Clock source from HCLK. | ||
| 10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. | ||
| [27:26] | SPI3SEL | SPI3 Clock Source Selection |
| 00 = Clock source from PLL. | ||
| 01 = Clock source from HCLK. | ||
| 10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. |
| PWM_T::CLKSRC |
[0x0010] PWM0 Clock Source Register
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | ECLKSRC0 | PWM0_CH01 External Clock Source Select |
| 000 = PWMx_CLK, x denotes 0 or 1. | ||
| 001 = TIMER0 overflow. | ||
| 010 = TIMER1 overflow. | ||
| 011 = TIMER2 overflow. | ||
| 100 = TIMER3 overflow. | ||
| Others = Reserved. | ||
| [10:8] | ECLKSRC2 | PWM0_CH23 External Clock Source Select |
| 000 = PWMx_CLK, x denotes 0 or 1. | ||
| 001 = TIMER0 overflow. | ||
| 010 = TIMER1 overflow. | ||
| 011 = TIMER2 overflow. | ||
| 100 = TIMER3 overflow. | ||
| Others = Reserved. | ||
| [18:16] | ECLKSRC4 | PWM0_CH45 External Clock Source Select |
| 000 = PWMx_CLK, x denotes 0 or 1. | ||
| 001 = TIMER0 overflow. | ||
| 010 = TIMER1 overflow. | ||
| 011 = TIMER2 overflow. | ||
| 100 = TIMER3 overflow. | ||
| Others = Reserved. |
| TIMER_T::CMP |
[0x0008] Timer Compare Register
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CMPDAT | Timer Compared Value |
| CMPDAT is a 24-bit compared value register | ||
| When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1. | ||
| Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). | ||
| Note1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state. | ||
| Note2: When the timer is operating in Continuous Counting mode (OPMODE (TIMERx_CTL[5:4] is 11), the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. | ||
| Note3: When the timer is not operating in Continuous Counting mode (OPMODE (TIMERx_CTL[5:4] is not 11), the 24-bit up counter will restart counting from 0 and use the newest CMPDAT value as the timer compared value when user writes a new value into the CMPDAT field | ||
| In addition, the prescale counter will be reloaded. |
| ADC_T::CMP0 |
[0x0050] A/D Compare Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCMPEN | A/D Compare Enable Bit |
| Set 1 to this bit to enable comparing CMPDAT (ADC_CMPx[27:16]) with specified channel conversion results when converted data is loaded into the ADC_DATx register. | ||
| 0 = Compare function Disabled. | ||
| 1 = Compare function Enabled. | ||
| Note: When this bit is set to 1 and CMPMCNT (ADC_CMPx[11:8]) is 0, the ADCMPFx (ADC_STATUS[2:1]) will be set once the match is hit. | ||
| [1] | ADCMPIE | A/D Compare Interrupt Enable Bit |
| If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT (ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE(ADC_CMPx[1]) is set to 1, a compare interrupt request will generate. | ||
| 0 = Compare function interrupt Disabled. | ||
| 1 = Compare function interrupt Enabled. | ||
| [2] | CMPCOND | Compare Condition |
| 0 = Set the compare condition as that when a A/D conversion result is less than the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. | ||
| 1 = Set the compare condition as that when a A/D conversion result is more than or equal to the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. | ||
| Note: When the internal counter reaches the value to (CMPMATCNT +1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set. | ||
| [7:3] | CMPCH | Compare Channel Selection |
| Set this field to select which channel's result to be compared. | ||
| Note: Valid setting of this field is channel 0~17, but channel 8~12 are reserved. | ||
| [11:8] | CMPMCNT | Compare Match Count |
| When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1. | ||
| Note: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set. | ||
| [27:16] | CMPDAT | Comparison Data |
| The 12 bits data is used to compare with conversion result of specified channel | ||
| Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software. |
| ADC_T::CMP1 |
[0x0054] A/D Compare Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCMPEN | A/D Compare Enable Bit |
| Set 1 to this bit to enable comparing CMPDAT (ADC_CMPx[27:16]) with specified channel conversion results when converted data is loaded into the ADC_DATx register. | ||
| 0 = Compare function Disabled. | ||
| 1 = Compare function Enabled. | ||
| Note: When this bit is set to 1 and CMPMCNT (ADC_CMPx[11:8]) is 0, the ADCMPFx (ADC_STATUS[2:1]) will be set once the match is hit. | ||
| [1] | ADCMPIE | A/D Compare Interrupt Enable Bit |
| If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT (ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE(ADC_CMPx[1]) is set to 1, a compare interrupt request will generate. | ||
| 0 = Compare function interrupt Disabled. | ||
| 1 = Compare function interrupt Enabled. | ||
| [2] | CMPCOND | Compare Condition |
| 0 = Set the compare condition as that when a A/D conversion result is less than the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. | ||
| 1 = Set the compare condition as that when a A/D conversion result is more than or equal to the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. | ||
| Note: When the internal counter reaches the value to (CMPMATCNT +1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set. | ||
| [7:3] | CMPCH | Compare Channel Selection |
| Set this field to select which channel's result to be compared. | ||
| Note: Valid setting of this field is channel 0~17, but channel 8~12 are reserved. | ||
| [11:8] | CMPMCNT | Compare Match Count |
| When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1. | ||
| Note: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set. | ||
| [27:16] | CMPDAT | Comparison Data |
| The 12 bits data is used to compare with conversion result of specified channel | ||
| Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software. |
| PWM_T::CMPBUF0 |
| PWM_T::CMPBUF1 |
| PWM_T::CMPBUF2 |
| PWM_T::CMPBUF3 |
| PWM_T::CMPBUF4 |
| PWM_T::CMPBUF5 |
| PWM_T::CMPDAT |
[0x0050] PWM0 Comparator Register 0,1,2,3,4,5
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CMPDAT | PWM0 Comparator Register |
| CMPDAT use to compare with CNTR to generate PWM0 waveform, interrupt and trigger ADC. | ||
| In independent mode, CMPDAT0~5 denote as 6 independent PWM0_CH0~5 compared point. | ||
| In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM0_CH0 and PWM0_CH1, PWM0_CH2 and PWM0_CH3, PWM0_CH4 and PWM0_CH5. |
| TIMER_T::CNT |
[0x0014] Timer Counter Data Register
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CNT | Timer Counter Data (Read) |
| This field can reflect the internal 24-bit timer counter value or external event input counter value from Tx (x=0~3) pin. | ||
| Counter Reset (Write) | ||
| User can write any value to TIEMRx_CNT to reset internal 24-bit timer up-counter and 8-bit pre-scale counter | ||
| This reset operation wouldn't affect any other timer control registers and circuit | ||
| After reset completed, the 24-bit timer up-counter and 8-bit pre-scale counter restart the counting based on the TIMERx_CTL register setting. | ||
| [31] | RSTACT | Reset Active |
| This bit indicates if the counter reset operation active. | ||
| When user write this register, timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0 | ||
| At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress | ||
| Once the counter reset operation done, timer clear this bit to 0 automatically. | ||
| 0 = Reset operation is done. | ||
| 1 = Reset operation triggered by writing TIMERx_CNT is in progress. | ||
| Note: This bit is read only. Write operation wouldn't take any effect. |
| PWM_T::CNT |
[0x0090] PWM0 Counter Register 0,2,4
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CNT | PWM0 Data Register (Read Only) |
| User can monitor CNTR to know the current value in 16-bit period counter. | ||
| [16] | DIRF | PWM0 Direction Indicator Flag (Read Only) |
| 0 = Counter is Down count. | ||
| 1 = Counter is UP count. |
| WWDT_T::CNT |
| PWM_T::CNTCLR |
[0x0024] PWM0 Clear Counter Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CNTCLR0 | Clear PWM0 Counter Control Bit 0 |
| It is automatically cleared by hardware. | ||
| 0 = No effect. | ||
| 1 = Clear 16-bit PWM0 counter to 0000H. | ||
| [2] | CNTCLR2 | Clear PWM0 Counter Control Bit 2 |
| It is automatically cleared by hardware. | ||
| 0 = No effect. | ||
| 1 = Clear 16-bit PWM0 counter to 0000H. | ||
| [4] | CNTCLR4 | Clear PWM0 Counter Control Bit 4 |
| It is automatically cleared by hardware. | ||
| 0 = No effect. | ||
| 1 = Clear 16-bit PWM0 counter to 0000H. |
| PWM_T::CNTEN |
[0x0020] PWM0 Counter Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CNTEN0 | PWM0 Counter Enable Bit 0 |
| 0 = PWM0 Counter0_1 and clock prescaler0 Stop Running. | ||
| 1 = PWM0 Counter0_1 and clock prescaler0 Start Running. | ||
| [2] | CNTEN2 | PWM0 Counter Enable Bit 2 |
| 0 = PWM0 Counter2_3 and clock prescaler2 Stop Running. | ||
| 1 = PWM0 Counter2_3 and clock prescaler2 Start Running. | ||
| [4] | CNTEN4 | PWM0 Counter Enable Bit 4 |
| 0 = PWM0 Counter4_5 and clock prescaler4 Stop Running. | ||
| 1 = PWM0 Counter4_5 and clock prescaler4 Start Running. |
| PDMA_CH_T::CNTn |
[0x000c] PDMA channel n Transfer Count Register
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | TCNT | PDMA Transfer Count Bits |
| This field indicates a 16-bit transfer count number of PDMA. | ||
| [31:16] | PCNTITH | PDMA Periodic Count Interrupt Threshold |
| This field indicates how many data transferred to generate periodic interrupt | ||
| Note: write 0 to this field to disable this function. |
| PDMA_CH_T::CSAn |
| DMA_CRC_T::CTL |
[0x0000] CRC Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CRCEN | CRC Channel Enable Bit |
| 0 = No effect. | ||
| 1 = CRC operation Enabled. | ||
| When operating in CRC DMA mode (TRIGEN (CRC_CTL[23]) = 1), if user clears this bit, the PDMA operation will be continuous until all CRC DMA operation is done, and the TRIGEN bit will keep 1 until all CRC DMA operation done | ||
| But in this case, the CRCTDIF (CRC_DMAINTSTS[1]) flag will be inactive, user can read CRC checksum result only if TRIGEN clears to 0 | ||
| When operating in CRC DMA mode (TRIGEN (CRC_CTL[23]) = 1), if user wants to stop the transfer immediately, user can write 1 to CRCRST (CRC_CTL[1]) bit to stop the transmission. | ||
| [1] | CRCRST | CRC Engine Reset Bit |
| 0 = No effect. | ||
| 1 = Reset the internal CRC state machine and internal buffer | ||
| The others contents of CRC_CTL register will not be cleared. | ||
| Note1: This bit will be cleared automatically. | ||
| Note2: When operating in CPU mode, setting this bit will reload the seed value from CRC_SEED register as checksum initial value. | ||
| [23] | TRIGEN | Trigger Enable Bit |
| This bit is used to trigger the CRC DMA transfer. | ||
| 0 = No effect. | ||
| 1 = CRC DMA data read or write transfer Enabled. | ||
| Note1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_DAT register. | ||
| Note2: When CRC DMA transfer completed, this bit will be cleared automatically. | ||
| Note3: If the bus error occurs when CRC DMA transfer data, all CRC DMA transfer will be stopped | ||
| User must reset all DMA channel before trigger DMA again. | ||
| [24] | DATREV | Write Data Bit Order Reverse |
| This bit is used to enable the bit order reverse function for writing data value in CRC_DTA register. | ||
| 0 = Bit order reverse for CRC data write in Disabled. | ||
| 1 = Bit order reverse for CRC data write in Enabled (per byte). | ||
| Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC data write in is 0x55DD33BB. | ||
| [25] | CHKSREV | Checksum Bit Order Reverse |
| This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. | ||
| 0 = Bit order reverse for CRC checksum Disabled. | ||
| 1 = Bit order reverse for CRC checksum Enabled. | ||
| Note: If the checksum result is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB | ||
| [26] | DATFMT | Write Data 1's Complement |
| This bit is used to enable the 1's complement function for write data value in CRC_DTA register. | ||
| 0 = 1's complement for CRC writes data in Disabled. | ||
| 1 = 1's complement for CRC writes data in Enabled. | ||
| [27] | CHKSFMT | Checksum 1's Complement |
| This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. | ||
| 0 = 1's complement for CRC checksum Disabled. | ||
| 1 = 1's complement for CRC checksum Enabled. | ||
| [29:28] | DATLEN | CPU Write Data Length |
| This field indicates the CPU write data length only when operating in CPU mode. | ||
| 00 = The write data length is 8-bit mode. | ||
| 01 = The write data length is 16-bit mode. | ||
| 10 = The write data length is 32-bit mode. | ||
| 11 = Reserved. | ||
| Note1: This field is only valid when operating in CPU mode. | ||
| Note2: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA [7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA [15:0]. | ||
| [31:30] | CRCMODE | CRC Polynomial Mode |
| This field indicates the CRC operation polynomial mode. | ||
| 00 = CRC-CCITT Polynomial Mode. | ||
| 01 = CRC-8 Polynomial Mode. | ||
| 10 = CRC-16 Polynomial Mode. | ||
| 11 = CRC-32 Polynomial Mode. |
| TIMER_T::CTL |
[0x0000] Timer Control and Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CNTEN | Timer Counting Enable Bit |
| 0 = Stops/Suspends counting. | ||
| 1 = Starts counting. | ||
| Note1: In stop status, set CNTEN to 1 enables 24-bit counter keeps up counting from the last stop counting value. | ||
| Note2: This bit is auto-cleared by hardware in one-shot mode (OPMODE (TIMERx_CTL[5:4]) = 00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated. | ||
| Note3: Writing this bit 1 will not take any effect if RSTCNT (TIMERx_CTL[1]) is also set to 1 at the same time. | ||
| [1] | RSTCNT | Timer Counter Reset Bit |
| Setting this bit will reset the internal 8-bit prescale counter, 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[0]) to 0. | ||
| 0 = No effect. | ||
| 1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit. | ||
| Note: This bit will be auto cleared and takes at least 3 TIMERx_CLK clock cycles. | ||
| [2] | WKEN | Wake-up Function Enable Bit |
| If this bit is set to 1, while CNTIF (TIMERx_INTSTS[0]) or CAPIF (TIMERx_INTSTS[1]) is 1, the timer interrupt signal will generate a wake-up trigger event to CPU. | ||
| 0 = Wake-up function Disabled if timer interrupt signal generated. | ||
| 1 = Wake-up function Enabled if timer interrupt signal generated. | ||
| [3] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Bit |
| 0 = ICE debug mode acknowledgement affects TIMER counting. | ||
| Timer counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| Timer counter will keep going no matter CPU is held by ICE or not. | ||
| [5:4] | OPMODE | Timer Counting Mode Selection |
| 00 = The Timer controller is operated in One-shot mode. | ||
| 01 = The Timer controller is operated in Periodic mode. | ||
| 10 = The Timer controller is operated in Toggle-output mode. | ||
| 11 = The Timer controller is operated in Continuous Counting mode. | ||
| [7] | ACTSTS | Timer Active Status Bit (Read Only) |
| This bit indicates the 24-bit up counter status. | ||
| 0 = 24-bit up counter is not active. | ||
| 1 = 24-bit up counter is active. | ||
| [8] | TRGADC | Trigger ADC Enable Bit |
| If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC. | ||
| 0 = Timer interrupt trigger ADC Disabled. | ||
| 1 = Timer interrupt trigger ADC Enabled. | ||
| Note: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger ADC. | ||
| If TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger ADC. | ||
| [10] | TRGPDMA | Timer Trigger PDMA Enable Bit |
| If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA. | ||
| 0 = Timer interrupt trigger PWM Disabled. | ||
| 1 = Timer interrupt trigger PWM Enabled. | ||
| Note: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger PWM. | ||
| If TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger PWM. | ||
| [11] | TRGSSEL | Trigger Source Selection |
| If this bit is set to 1, capture interrupt can trigger ADC, PDMA and PWM | ||
| Otherwise, time-out interrupt can trigger ADC, PDMA and PWM. | ||
| 0 = Time-out interrupt is used to trigger ADC, PDMA and PWM. | ||
| 1 = Capture interrupt is used to trigger ADC, PDMA and PWM. | ||
| [12] | EXTCNTEN | Event Counter Mode Enable Bit |
| This bit is for external counting pin function enabled. | ||
| 0 = Event counter mode Disabled. | ||
| 1 = Event counter mode Enabled. | ||
| Note: When timer is used as an event counter, this bit should be set to 1 and HCLK as timer clock source. | ||
| [13] | CNTPHASE | Timer External Count Phase |
| This bit indicates the detection phase of external counting pin Tx (x= 0~3). | ||
| 0 = A Falling edge of external counting pin will be counted. | ||
| 1 = A Rising edge of external counting pin will be counted. | ||
| [14] | CNTDBEN | Timer Counter Pin De-bounce Enable Bit |
| 0 = Tx (x= 0~3) pin de-bounce Disabled. | ||
| 1 = Tx (x= 0~3) pin de-bounce Enabled. | ||
| Note: If this bit is set to 1, the edge detection of Tx pin is detected with de-bounce circuit. | ||
| [16] | CAPEN | Timer External Capture Pin Enable Bit |
| This bit enables the Tx_EXT pin. | ||
| 0 = Tx_EXT (x= 0~3) pin Disabled. | ||
| 1 = Tx_EXT (x= 0~3) pin Enabled. | ||
| Note1: For TIMERx_CTL, if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPEN will be forced to low and the TC pin transition is ignored (where x = 0 or 2). | ||
| Note2: For TIMERx+1_CTL, if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPEN will be forced to high (where x = 0 or 2). | ||
| [17] | CAPFUNCS | Capture Function Selection |
| 0 = External Capture Mode Enabled. | ||
| 1 = External Reset Mode Enabled. | ||
| Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value. | ||
| Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value. | ||
| Note3: For TIMERx+1_CTL (x = 0 or 2), if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPFUNCS will be forced to low. | ||
| [19:18] | CAPEDGE | Timer External Capture Pin Edge Detection |
| For timer counter reset function and free-counting mode of timer capture function, the configurations are: | ||
| 00 = A Falling edge on Tx_EXT (x= 0~3) pin will be detected. | ||
| 01 = A Rising edge on Tx_EXT (x= 0~3) pin will be detected. | ||
| 10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected. | ||
| 11 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected. | ||
| For trigger-counting mode of timer capture function, the configurations are: | ||
| 00 = 1st falling edge on TC pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting. | ||
| 01 = 1st rising edge on TC pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting. | ||
| 10 = Falling edge on TC pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting. | ||
| 11 = Rising edge on TC pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting. | ||
| Note: For TIMERx+1_CTL, if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPEDGE will be forced to 11 (where x = 0 or 2). | ||
| [20] | CAPCNTMD | Timer Capture Counting Mode Selection |
| This bit indicates the behavior of 24-bit up-counting timer while CAPEN (TIMERx_CTL[16]) is set to high. | ||
| If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by OPMODE (TIMERx_CTL[5:4]) field | ||
| When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and the transition of TC pin matches the CAPEDGE (TIMERx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TIMERx_CAP. | ||
| If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at 0 | ||
| When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting | ||
| And then if the transition of external pin matches the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting | ||
| And its value will be saved into register TIMERx_CAP. | ||
| 0 = Capture with free-counting timer mode. | ||
| 1 = Capture with trigger-counting timer mode. | ||
| Note: For TIMERx+1_CTL, if INTRTGEN (TIMERx_CTL[24]) is set, the CAPCNTMD will be forced to high, the capture with Trigger-counting Timer mode (where x = 0 or 2). | ||
| [22] | CAPDBEN | Timer External Capture Pin De-bounce Enable Bit |
| 0 = Tx_EXT (x= 0~3) pin de-bounce Disabled. | ||
| 1 = Tx_EXT (x= 0~3) pin de-bounce Enabled. | ||
| Note1: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit. | ||
| Note2: For Timer 1 and 3, when INTRTGEN (TIMERx_CTL[24]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low. | ||
| [23] | CMPCTL | Timer Compared Mode Selection |
| 0 = The behavior selection in one-shot, periodic or Toggle-output mode Disabled. | ||
| When user updates CMPDAT (TIMERx_CMP) while timer is running in One-shot, Periodic or Toggle-output mode, CNT (TIMERx_CNT) will be reset to default value. | ||
| 1 = The behavior selection in one-shot, periodic or Toggle-output mode Enabled. | ||
| When user updates CMPDAT (TIMERx_CMP) while timer is running in One-shot, Periodic or Toggle-output mode, the limitations as bellows list, | ||
| If updated CMPDAT (TIMERx_CMP) value > CNT (TIMERx_CNT), CMPDAT (TIMERx_CMP) will be updated and CNT (TIMERx_CNT) keep running continually. | ||
| If updated CMPDAT (TIMERx_CMP) value = CNT (TIMERx_CNT), timer time-out interrupt will be asserted immediately. | ||
| If updated CMPDAT (TIMERx_CMP) value < CNT (TIMERx_CNT), CNT (TIMERx_CNT) will be reset to default value | ||
| At the same time, prescale counter reloaded. | ||
| [24] | INTRTGEN | Inter-timer Trigger Function Enable Bit |
| If INTRTGEN is set to 1 TIMERx (x = 0 or 2), TIMERx and Timerx=1 are operating at inter-timer trigger mode. | ||
| When Inter-timer Trigger function is enabled, TIMERx is operating at event counting mode to count the input event from Tx pin and TIMERx+1 is operating at external capture trigger-counting mode. | ||
| 0 = Inter-timer trigger function Disabled. | ||
| 1 = Inter-timer trigger function Enabled. | ||
| Note: In TIMERx+1_CTL, this bit is always 0. | ||
| [25] | INTRTGMD | Inter-timer Trigger Mode Selection |
| This bit controls the TIMERx (x = 0 or 2) operating behavior when INTRTGEN (TIMERx_CTL[24]) is set to 1. | ||
| If INTRTGMD is set to 0 and INTRTGEN (TIMERx_CTL[24]) is set to 1, the TIMERx is operating at event counting mode to count the all input events from Tx pin. | ||
| If INTRTGMD and INTRTGEN (TIMERx_CTL[24]) are both set to 1, TIMERx is operating at event counting mode and the number of first incoming events (defined by EVNTDPCNT (TIMERx_ECTL[31:24])) are ignored. | ||
| 0 = TIMERx count the all input events from Tx pin. | ||
| 1 = TIMERx ignored the number of first incoming events based on EVNTDPCNT (TIMERx_ECTL[31:24]). | ||
| Note: In TIMERx+1_CTL, this bit is always 0. | ||
| [28] | TRGPWM | Trigger PWM Enable Bit |
| If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM. | ||
| 0 = Timer interrupt trigger PWM Disabled. | ||
| 1 = Timer interrupt trigger PWM Enabled. | ||
| Note: If TRGSSEL (TIMERx_CTL[11]) = 0, time-out interrupt signal will trigger PWM. | ||
| If TRGSSEL (TIMERx_CTL[11]) = 1, capture interrupt signal will trigger PWM. |
| WDT_T::CTL |
[0x0000] Watchdog Timer Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WTR | Clear Watchdog Timer (Write Protect) |
| Please refer to open lock sequence to program it. | ||
| Setting this bit will clear the Watchdog timer. | ||
| 0 = No effect. | ||
| 1 = Reset the contents of the Watchdog timer. | ||
| Note: This bit will be auto cleared after 1 PCLK clock cycle. | ||
| [1] | WTRE | Watchdog Timer Reset Function Enable Bit (Write Protect) |
| Please refer to open lock sequence to program it. | ||
| Setting this bit will enable the Watchdog timer reset function. | ||
| 0 = Watchdog timer reset function Disabled. | ||
| 1 = Watchdog timer reset function Enabled. | ||
| [2] | WTWKE | Watchdog Timer Wake-up Function Enable Bit (Write Protect) |
| Please refer to open lock sequence to program it. | ||
| 0 = Watchdog timer Wake-up CPU function Disabled. | ||
| 1 = Wake-up function Enabled so that Watchdog timer time-out can wake up CPU from Power-down mode. | ||
| [3] | WTE | Watchdog Timer Enable Bit (Write Protect) |
| Please refer to open lock sequence to program it. | ||
| 0 = Watchdog timer Disabled (this action will reset the internal counter). | ||
| 1 = Watchdog timer Enabled. | ||
| [6:4] | WTIS | Watchdog Timer Interval Selection (Write Protect) |
| Please refer to open lock sequence to program it. | ||
| The three bits select the time-out interval for the Watchdog timer. This count is free running counter. | ||
| Please refer to Table 6.11-1. | ||
| [9:8] | WTRDSEL | Watchdog Timer Reset Delay Selection |
| When watchdog timeout happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened | ||
| Software can select a suitable value of watchdog reset delay period for different watchdog timeout period. | ||
| 00 = Watchdog reset delay period is 1026 watchdog clock. | ||
| 01 = Watchdog reset delay period is 130 watchdog clock. | ||
| 10 = Watchdog reset delay period is 18 watchdog clock. | ||
| 11 = Watchdog reset delay period is 3 watchdog clock. | ||
| Note: This bit will be reset if watchdog reset happened | ||
| [31] | DBGEN | WDT Debug Mode Enable Control (Write Protect) |
| 0 = WDT stopped counting if system is in Debug mode. | ||
| 1 = WDT still counted even system is in Debug mode. |
| WWDT_T::CTL |
[0x0004] Window Watchdog Timer Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WWDTEN | Window Watchdog Enable Bit |
| Set this bit to enable Window Watchdog timer. | ||
| 0 = Window Watchdog timer function Disabled. | ||
| 1 = Window Watchdog timer function Enabled. | ||
| [11:8] | PERIODSEL | WWDT Pre-scale Period Select |
| These three bits select the pre-scale for the WWDT counter period. | ||
| Please refer toTable 6.12-1 WWDT Prescaler Value Selection. | ||
| [21:16] | WINCMP | WWDT Window Compare Bits |
| Set this register to adjust the valid reload window. | ||
| Note: WWDTRLD register can only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal. | ||
| [31] | DBGEN | WWDT Debug Enable Bit |
| 0 = WWDT stopped count if system is in Debug mode. | ||
| 1 = WWDT still counted even system is in Debug mode. |
| SC_T::CTL |
[0x0004] SC Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SCEN | SC Engine Enable Bit |
| Set this bit to 1 to enable SC operation | ||
| If this bit is cleared, SC will force all transition to IDLE state | ||
| Note1: SCEN must be set to 1 before filling in other registers, or smart card will not work properly. | ||
| Note2: If SCEN is activated, all function can work correctly | ||
| If SCEN is not activated, when CPU write data to SMC, only Flip-flop which works in PCLK domain will turn on for two PCLK cycle, Flip-flop working in SCLK domain will not be turn on. | ||
| [1] | RXOFF | RX Transition Disable Bit |
| 0 = The receiver Enabled. | ||
| 1 = The receiver Disabled. | ||
| Note1: If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored. | ||
| Note2: After hardware activation and hardware warm reset are done, RXOFF is set to 0 automatically. | ||
| [2] | TXOFF | TX Transition Disable Bit |
| 0 = The transceiver Enabled. | ||
| 1 = The transceiver Disabled. | ||
| [3] | AUTOCEN | Auto Convention Enable Bit |
| 0 = Auto-convention Disabled. | ||
| 1 = Auto-convention Enabled | ||
| When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11. | ||
| If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F | ||
| After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically | ||
| If the first data is not 0x3B or 0x3F, hardware will generate an interrupt INT_ACON_ERR (if ACERRIEN (SC_INTEN[10]) = 1 to CPU. | ||
| [5:4] | CONSEL | Convention Selection |
| 00 = Direct convention. | ||
| 01 = Reserved. | ||
| 10 = Reserved. | ||
| 11 = Inverse convention. | ||
| Note: If AUTOCEN(SC_CTL[3]) is enabled, this field is ignored. | ||
| [7:6] | RXTRGLV | Rx Buffer Trigger Level |
| When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if [RDAIEN](SC_INTEN[0]) is enabled, an interrupt will be generated). | ||
| 00 = INTR_RDA Trigger Level with 01 Bytes. | ||
| 01 = INTR_RDA Trigger Level with 02 Bytes. | ||
| 10 = INTR_RDA Trigger Level with 03 Bytes. | ||
| 11 = Reserved. | ||
| [12:8] | BGT | Block Guard Time (BGT) |
| Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions | ||
| This field indicates the counter for the bit length of block guard time | ||
| According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it. | ||
| Note: The real block guard time is BGT + 1. | ||
| [14:13] | TMRSEL | Timer Selection |
| 00 = All internal timer function Disabled. | ||
| 11 = Internal 24 bit timer and two 8 bit timers Enabled | ||
| Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]. | ||
| Other configurations are reserved | ||
| [15] | NSB | Stop Bit Length |
| This field indicates the length of stop bit. | ||
| 0 = The stop bit length is 2 ETU. | ||
| 1= The stop bit length is 1 ETU. | ||
| Note: The default stop bit length is 2. SMC and UART adopt NSB to program the stop bit length. | ||
| [18:16] | RXRTY | RX Error Retry Count Number |
| This field indicates the maximum number of receiver retries that are allowed when parity error has occurred | ||
| Note1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number. | ||
| Note2: This field cannot be changed when RX_ERETRY_EN enabled | ||
| The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value. | ||
| [19] | RXRTYEN | RX Error Retry Enable Bit |
| This bit enables receiver retry function when parity error has occurred. | ||
| 0 = RX error retry function Disabled. | ||
| 1 = RX error retry function Enabled. | ||
| Note: Software must fill in the RXRTY value before enabling this bit. | ||
| [22:20] | TXRTY | TX Error Retry Count Number |
| This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. | ||
| Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. | ||
| Note2: This field cannot be changed when TXRTYEN enabled | ||
| The change flow is to disable TXRTYEN first and then fill in new retry value. | ||
| [23] | TXRTYEN | TX Error Retry Enable Bit |
| This bit enables transmitter retry function when parity error has occurred. | ||
| 0 = TX error retry function Disabled. | ||
| 1 = TX error retry function Enabled. | ||
| [25:24] | CDDBSEL | Card Detect De-bounce Selection |
| This field indicates the card detect de-bounce selection. | ||
| 00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks. | ||
| Other configurations are reserved. | ||
| [30] | SYNC | SYNC Flag Indicator(Read Only) |
| Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.SYNC flag is | ||
| 0 = synchronizing is completion, user can write new data to RXRTY and TXRTY. | ||
| 1 = Last value is synchronizing. |
| I2C_T::CTL |
[0x0000] I2C Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | I2CEN | I2C Function Enable Bit |
| 0 = I2C function Disabled. | ||
| 1 = I2C function Enabled. | ||
| [1] | AA | Assert Acknowledge Control Bit |
| When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when | ||
| 1.)A slave is acknowledging the address sent from master, | ||
| 2.) The receiver devices are acknowledging the data sent by transmitter | ||
| When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. | ||
| [2] | STO | I2C STOP Control Bit |
| In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected | ||
| This bit will be cleared by hardware automatically. | ||
| [3] | STA | I2C START Command |
| Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. | ||
| [4] | SI | I2C Status |
| When a new state is present in the I2C_STATUS register, if the INTEN bit is set, the I2C interrupt is requested | ||
| It must write one by software to this bit after the INTSTS (I2C_INTSTS[0]) is set to 1 and the I2C protocol function will go ahead until the STOP is active or the I2CEN is disabled. | ||
| 0 = I2C's Status disabled and the I2C protocol function will go ahead. | ||
| 1 = I2C's Status active. | ||
| Note: If software wants to skip clearing INTSTS (I2C_INTSTS[0]), it also can write 1 to SI bit and must set INTEN bit | ||
| That INTSTS (I2C_INTSTS[0]) will be cleared when SI is cleared. | ||
| [7] | INTEN | Interrupt Enable Bit |
| 0 = I2C interrupt Disabled. | ||
| 1 = I2C interrupt Enabled. |
| SPI_T::CTL |
[0x0000] SPI Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GOBUSY | SPI Transfer Control Bit and Busy Status |
| 0 = Writing this bit 0 will stop data transfer if SPI is transferring. | ||
| 1 = In Master mode, writing 1 to this bit will start the SPI data transfer; In Slave mode, writing '1' to this bit indicates that the slave is ready to communicate with a master. | ||
| If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1' | ||
| As the transfer is finished, this bit will be cleared automatically | ||
| Software can read this bit to check if the SPI is in busy status. | ||
| In FIFO mode, this bit will be controlled by hardware | ||
| Software should not modify this bit | ||
| In slave mode, this bit always returns 1 when software reads this register | ||
| In master mode, this bit reflects the busy or idle status of SPI. | ||
| Note: | ||
| 1.When FIFO mode is disabled, all configurations should be set before writing 1 to the GOBUSY bit in the SPI_CTL register. | ||
| 2 | ||
| When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer. | ||
| [1] | RXNEG | Receive on Negative Edge |
| 0 = The received data is latched on the rising edge of SPI_CLK. | ||
| 1 = The received data is latched on the falling edge of SPI_CLK. | ||
| Note: Refer to Edge section. | ||
| [2] | TXNEG | Transmit on Negative Edge |
| 0 = The transmitted data output is changed on the rising edge of SPI_CLK. | ||
| 1 = The transmitted data output is changed on the falling edge of SPI_CLK. | ||
| Note: Refer to Edge section. | ||
| [7:3] | DWIDTH | Data Width |
| This field specifies how many bits can be transmitted / received in one transaction | ||
| The minimum bit length is 8 bits and can be up to 32 bits. | ||
| 01000 = 8 bits are transmitted in one transaction. | ||
| 01001 = 9 bits are transmitted in one transaction. | ||
| 01010 = 10 bits are transmitted in one transaction. | ||
| --— | ||
| 11111 = 31 bits are transmitted in one transaction. | ||
| 00000 = 32 bits are transmitted in one transaction. | ||
| [10] | LSB | Send LSB First |
| 0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH (SPI_CTL[7:3]), is transmitted/received first. | ||
| 1 = The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (SPI_RX0/1). | ||
| Note: Refer to LSB first section. | ||
| [11] | CLKPOL | Clock Polarity |
| 0 = The default level of SPI_CLK is low. | ||
| 1 = The default level of SPI_CLK is high. | ||
| Note: Refer to Clock Parity section. | ||
| [15:12] | SUSPITV | Suspend Interval (Master Only) |
| These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer | ||
| The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKPOL = 0 | ||
| If CLKPOL = 1, the interval is from the rising clock edge to the falling clock edge. | ||
| The default value is 0x3 | ||
| The desired suspend interval is obtained according to the following equation: )(SP_]YCLE[3]0) + 0.5) * period of SPI_CLK | ||
| For example, | ||
| SUSPITV = 0x0 .... 0.5 SPI_CLK clock cycle. | ||
| SUSPITV = 0x1 .... 1.5 SPI_CLK clock cycle. | ||
| ...... | ||
| SUSPITV = 0xE .... 14.5 SPI_CLK clock cycle. | ||
| SUSPITV = 0xF .... 15.5 SPI_CLK clock cycle. | ||
| [17] | UNITIEN | Unit Transfer Interrupt Enable Bit |
| 0 = SPI unit transfer interrupt Disabled. | ||
| 1 = SPI unit transfer interrupt Enabled. | ||
| [18] | SLAVE | Slave Mode Selection |
| 0 = SPI controller set as Master mode. | ||
| 1 = SPI controller set as Slave mode. | ||
| Note: Refer to Slave Selection section | ||
| [19] | REORDER | Byte Reorder Function Enable Bit |
| 0 = Byte reorder function Disabled. | ||
| 1 = Enable byte reorder function and insert a byte suspend interval among each byte | ||
| The setting of DWIDTH must be configured as 00b ( 32 bits/ word) | ||
| Note: The suspend interval is defined in SUSPITV. Refer to Byte Reorder section. | ||
| Note: Byte Suspend is only used in SPI Byte Reorder mode. | ||
| [21] | FIFOM | FIFO Mode Enable Bit |
| 0 = FIFO mode Disabled (in Normal mode). | ||
| 1 = FIFO mode Enabled. | ||
| Note: Refer to FIFO Mode section. | ||
| [22] | TWOBIT | 2-bit Transfer Mode Enable Bit |
| 0 = 2-bit transfer mode Disabled. | ||
| 1 = 2-bit transfer mode Enabled. | ||
| Refer to Two Bit Transfer Mode section | ||
| Note: automatically | ||
| [28] | DUALDIR | Dual I/O Mode Direction Control |
| 0 = Date read in the Dual I/O Mode function. | ||
| 1 = Data write in the Dual I/O Mode function. | ||
| Refer to Dual I/O Mode section. | ||
| [29] | DUALIOEN | Dual I/O Mode Enable Bit |
| 0 = Dual I/O Mode function Disabled. | ||
| 1 = Dual I/O Mode function Enabled. | ||
| Refer to Dual I/O Mode section. | ||
| [30] | WKSSEN | Wake-up by Slave Select Enable Bit |
| 0 = Wake-up function Disabled. | ||
| 1 = Wake-up function Enabled. | ||
| Note: The Slave select wake-up function is only available in SPI Slave mode | ||
| When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_SS port | ||
| After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. | ||
| [31] | WKCLKEN | Wake-up by SPI Clock Enable Bit |
| 0 = Wake-up function Disabled. | ||
| 1 = Wake-up function Enabled. | ||
| Note: When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port | ||
| After the system wake-up, this bit must be cleared by user to disable the wake-up requirement. |
| ADC_T::CTL |
[0x0048] A/D Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCEN | A/D Converter Enable Bit |
| 0 = A/D Converter Disabled. | ||
| 1 = A/D Converter Enabled. | ||
| Note: Before starting A/D conversion function, this bit should be set to 1 | ||
| Clear it to 0 to disable A/D converter analog circuit to save power consumption. | ||
| [1] | ADCIEN | A/D Interrupt Enable Bit |
| A/D conversion end interrupt request is generated if ADCIEN (ADC_CTL[1]) bit is set to 1. | ||
| 0 = A/D interrupt function Disabled. | ||
| 1 = A/D interrupt function Enabled. | ||
| [3:2] | ADMD | A/D Converter Operation Mode |
| 00 = Single conversion. | ||
| 01 = Reserved. | ||
| 10 = Single-cycle scan. | ||
| 11 = Continuous scan. | ||
| [5:4] | HWTRGSEL | Hardware Trigger Source Select Bit |
| In hardware trigger mode, ADC starts to convert by the external trigger from STADC pin or PWM trigger. | ||
| 00= A/D conversion is started by external STADC pin. | ||
| 01= Reserved. | ||
| 10= Reserved. | ||
| 11= A/D conversion is started by PWM0 trigger. | ||
| Note: Software should disable HWTRGEN (ADC_CTL[8]) and clear SWTRG (ADC_CTL[11]) before change HWTRGSEL (ADC_CTL[5:4]). | ||
| [7:6] | HWTRGCOND | Hardware External Trigger Condition |
| These two bits decide external pin STADC trigger event is level or edge | ||
| The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state. | ||
| 00 = Low level. | ||
| 01 = High level. | ||
| 10 = Falling edge. | ||
| 11 = Rising edge. | ||
| [8] | HWTRGEN | Hardware External Trigger Enable Bit |
| Enable or disable triggering of A/D conversion by external STADC pin | ||
| If external trigger is enabled, ADC starts to convert by the selected hardware trigger source. | ||
| 0= External trigger Disabled. | ||
| 1= External trigger Enabled. | ||
| [9] | PTEN | PDMA Transfer Enable Bit |
| When A/D conversion is completed, the converted data is loaded into ADC_DATx, software can enable this bit to generate a PDMA data transfer request. | ||
| 0 = PDMA data transfer Disabled. | ||
| 1 = PDMA data transfer in ADC_DATx Enabled. | ||
| Note: When PDMA transfer enable, software must set ADCIEN (ADC_CTL[1]) = 0 to disable interrupt | ||
| PDMA can access ADC_DATx registers by block or single transfer mode. | ||
| [10] | DIFF | Differential Mode Selection |
| 0 = ADC is operated in single-ended mode. | ||
| 1 = ADC is operated in differential mode. | ||
| Note: Calibration should calibrated each time when switching between single-ended and differential mode. | ||
| [11] | SWTRG | Software Trigger A/D Conversion Start |
| 0 = Conversion stopped and A/D converter enter idle state. | ||
| 1 = Conversion starts. | ||
| ADC can be start to convert from three sources: software write, external pin STADC and PWM trigger | ||
| SWTRG (ADC_CTL[11]) is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels | ||
| In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset. | ||