Transitioning to remote learning means that we need to transition how learning happens. One way that I have chosen to do this over the next 6 weeks is through a collaborative paper. The learning goals behind this assignment is threefold:
The diversity of pathogens is astounding. All major groups of organisms have evolved a pathogenic habits and pathogens and parasites may be the most common habitat across all species!
In this course on ecology and evolution of infectious disease, we have largely focusing on biological concepts. In doing so, we have and will continue to superficially study species as they pertain to the biological concept. As examples, you learned a little bit about plague transmission when we read and discussed epizootics in prairie dog colonies, we would have learned just a little bit about Phocine Distemper Virus when learning about spatial dynamics of disease, and you will learn just a little bit about Batrachochytrium dendrobatidis (causing the disease, chytridiomycosis) in two weeks.
Beyond learning the biological concepts, I would like for you to deeply learn about the natural history of organisms—especially ones you’re interested in. To do so, I invite you to embark on this Collaborative Paper where you explore the biology and natural history of two species of interest.
The pathogens on which you choose to focus will be up to the pairs. I would like for one or both to be pathogens of non-human species.
Find pathogens that inspire the two of you and dive into them! I would like the following information to be sought and written about by you for each of the two species:
Given the extraordinary diversity of pathogens, the details of the biology of each will be different. Nevertheless, here are some guidelines of what to include in each of the aforementioned:
Lastly, I would like a section on the comparative biology—specifically ecology and evolution—of the two pathogens. This should be synthetic and reflective. This is the only section to which I will assign length parameters, and I ask that it is no shorter than 1 and no more than 2.5 pages, single spaced.
Single-spaced please. Given that most pathogens are grossly understudied (I mean, there are multitudes of careers in disease biology if any of you are interested—and this line of study is obviously relevant), there will be varying amount of information on the natural history, transmission dynamics, evolutionary biology, and ecological relevance, so I do not include length guidelines for those sections. As I mentioned in the previous section about the comparative biology section at the end, I ask that it is no shorter than 1 and no more than 2.5 pages.
| Person 1 | Person 2 |
|---|---|
| James | Brigid |
| Xinying | Jackie |
| Kirsten | Jack |
| Kaylie | Hannah R. |
| Hayley | Delaney |
| Stanley | Matt |
| Alan | Jamie |
| Thomas | Beck |
| Jordan | Abby |
| Kate | David |
| Megan | Youmian |
| Hannah K. | Kiana |
You’ll notice on the detailed calendar (link) that I am asking for a first draft due in three weeks from Monday (due 24 April). I will give you feedback as soon as I can. To incentivize getting the draft in earlier so I can get feedback to you sooner and not have all dozen papers at once, for every weekday early you turn it in, I will add an extra 1% to the paper grade (but not over 100%). For example, if you turn it in on Friday, 17 April, you will have 5% added to your final grade. You will them have until the exam period (15 May) to turn in the final draft.


I was notified a few days after the first two Amazon interviews that they wanted to have a third interview. They had to reschedule once due to a timing conflict but I had the third interview last Thursday (1/24). The agenda was the same as the other interviews and began with questions about a Rails project I’ve done recently. Next was some questions about binary search trees (glad I studied those). I was able to answer these questions and figured out the number of leaf nodes and total nodes in a complete BST of height h by writing out an example.
The programming portion was next and I got on collabedit again. The first question was to write a function to tell if two strings are anagrams of each other. I knew this one! I actually reviewed the solutions the day before so I told the interviewer it was a familiar problem and he had me solve it anyways. I mentioned three solutions:
Sort the strings using a basic sort such as quicksort to avoid using additional space - O(nlogn) time. If the sorted strings are the same they are anagrams.
Allocate an array that is the size of the total possible characters in the character set (ASCII or Unicode). For the first string, increment the characters location in the array every time it is seen, then decrement it for the second string. Check to see if the array is zeroed out and if so, its an anagram. This is similiar to counting sort.
If we constrict the requirements to only allowing unique lowercase ASCII characters it becomes more feasible to do a bitwise solution. Using an 32-bit int, we can bit shift over by that character’s value (subtract ‘a’ from character to get bits 0-25). Then flip the bits back if the second string also has any of the bits from the first string. At the end just check to see if the int is equal to 0 and the result is an anagram.
I implemented version 2. of the anagram code with ASCII in Java and then he asked me another problem. Given a value k, what is a good approach for returning the max k values from an unsorted array. So if k=1 we return the max, k=2 we return the max and the second max etc. I thought about this by starting with k=1. It will take at least O(n) time to return just 1, but as k grows the compute time will grow rapidly. I started thinking of data structures to use beginning with a BST (probably because it was fresh in my mind). This would work because the elements are sorted but the tree traversals would get ugly and complicated. I then decided on using a max-heap because it takes n time to assemble and can easily reorganize to provide the next element.
I asked some questions about Amazon and then the interview was over. After much anticipation I received an offer yesterday and spoke with a recruiter about all the details (and perks!). I have already accepted so I will moving to Seattle for the summer. The team I will be working on is called eCPS which focuses on scalability and reliable with web services. The website has more details here.
Some lessons that I learned:
Practice programming problems! Tons of these on StackOverflow, Careercup, Glassdoor etc.
Take Steve Yegge’s advice and warm up the day of. Do some really common interview problems like recursive tree traversals, hash tables, and string manipulation.
Tell the interviewers if you’ve solved the problem before! People want honest teammates.
Work on programming projects in your free time. I’m pretty sure I only got an interview because I taught myself Rails and wrote some projects with it for fun.
Anyways, I hope this helps someone else with getting the job they want! I’d be glad to answer any questions via email: jcluck@gwmail.gwu.edu.


Place & Route TRACE Report
Loading design for application trce from file fpgasdr_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-7000HE
Package: TQFP144
Performance: 4
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) <IP_ADDRESS>6
Mon Apr 06 16:34:28 2020
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o FPGASDR_impl1.twr -gui -msgset C:/Users/user/lattice/1BitADCFPGASDR/promote.xml FPGASDR_impl1.ncd FPGASDR_impl1.prf
Design file: fpgasdr_impl1.ncd
Preference file: fpgasdr_impl1.prf
Device,speed: LCMXO2-7000HE,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "osc_clk" 88.670000 MHz (4096 errors)
4096 items scored, 4096 timing errors detected.
Warning: 66.007MHz is the maximum frequency for this preference.
CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET "osc_clk" (0 errors) 18 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "osc_clk" 88.670000 MHz ;
4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 3.872ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i63 (to osc_clk +)
Delay: 15.021ns (57.5% logic, 42.5% route), 35 logic levels.
Constraint Details:
15.021ns physical path delay SLICE_2432 to SLICE_55 exceeds
11.278ns delay constraint less
-0.037ns skew and
0.166ns DIN_SET requirement (totaling 11.149ns) by 3.872ns
Physical Path Details:
Data path SLICE_2432 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R21C8A.CLK to R21C8A.Q0 SLICE_2432 (from osc_clk)
ROUTE 4 1.298 R21C8A.Q0 to R21C16C.C0 o_Rx_DV
CTOF_DEL --- 0.495 R21C16C.C0 to R21C16C.F0 SLICE_2476
ROUTE 4 1.160 R21C16C.F0 to R19C17D.C0 n8250
CTOF_DEL --- 0.495 R19C17D.C0 to R19C17D.F0 SLICE_2435
ROUTE 5 0.675 R19C17D.F0 to R19C15B.D1 n12533
CTOF_DEL --- 0.495 R19C15B.D1 to R19C15B.F1 SLICE_2394
ROUTE 52 1.080 R19C15B.F1 to R19C16C.B0 n13057
CTOF_DEL --- 0.495 R19C16C.B0 to R19C16C.F0 SLICE_2414
ROUTE 1 2.174 R19C16C.F0 to R19C2D.C0 n2358
C0TOFCO_DE --- 1.023 R19C2D.C0 to R19C2D.FCO SLICE_84
ROUTE 1 0.000 R19C2D.FCO to R19C3A.FCI n10981
FCITOFCO_D --- 0.162 R19C3A.FCI to R19C3A.FCO SLICE_83
ROUTE 1 0.000 R19C3A.FCO to R19C3B.FCI n10982
FCITOFCO_D --- 0.162 R19C3B.FCI to R19C3B.FCO SLICE_82
ROUTE 1 0.000 R19C3B.FCO to R19C3C.FCI n10983
FCITOFCO_D --- 0.162 R19C3C.FCI to R19C3C.FCO SLICE_81
ROUTE 1 0.000 R19C3C.FCO to R19C3D.FCI n10984
FCITOFCO_D --- 0.162 R19C3D.FCI to R19C3D.FCO SLICE_80
ROUTE 1 0.000 R19C3D.FCO to R19C4A.FCI n10985
FCITOFCO_D --- 0.162 R19C4A.FCI to R19C4A.FCO SLICE_79
ROUTE 1 0.000 R19C4A.FCO to R19C4B.FCI n10986
FCITOFCO_D --- 0.162 R19C4B.FCI to R19C4B.FCO SLICE_78
ROUTE 1 0.000 R19C4B.FCO to R19C4C.FCI n10987
FCITOFCO_D --- 0.162 R19C4C.FCI to R19C4C.FCO SLICE_77
ROUTE 1 0.000 R19C4C.FCO to R19C4D.FCI n10988
FCITOFCO_D --- 0.162 R19C4D.FCI to R19C4D.FCO SLICE_76
ROUTE 1 0.000 R19C4D.FCO to R19C5A.FCI n10989
FCITOFCO_D --- 0.162 R19C5A.FCI to R19C5A.FCO SLICE_75
ROUTE 1 0.000 R19C5A.FCO to R19C5B.FCI n10990
FCITOFCO_D --- 0.162 R19C5B.FCI to R19C5B.FCO SLICE_74
ROUTE 1 0.000 R19C5B.FCO to R19C5C.FCI n10991
FCITOFCO_D --- 0.162 R19C5C.FCI to R19C5C.FCO SLICE_73
ROUTE 1 0.000 R19C5C.FCO to R19C5D.FCI n10992
FCITOFCO_D --- 0.162 R19C5D.FCI to R19C5D.FCO SLICE_72
ROUTE 1 0.000 R19C5D.FCO to R19C6A.FCI n10993
FCITOFCO_D --- 0.162 R19C6A.FCI to R19C6A.FCO SLICE_71
ROUTE 1 0.000 R19C6A.FCO to R19C6B.FCI n10994
FCITOFCO_D --- 0.162 R19C6B.FCI to R19C6B.FCO SLICE_70
ROUTE 1 0.000 R19C6B.FCO to R19C6C.FCI n10995
FCITOFCO_D --- 0.162 R19C6C.FCI to R19C6C.FCO SLICE_69
ROUTE 1 0.000 R19C6C.FCO to R19C6D.FCI n10996
FCITOFCO_D --- 0.162 R19C6D.FCI to R19C6D.FCO SLICE_68
ROUTE 1 0.000 R19C6D.FCO to R19C7A.FCI n10997
FCITOFCO_D --- 0.162 R19C7A.FCI to R19C7A.FCO SLICE_67
ROUTE 1 0.000 R19C7A.FCO to R19C7B.FCI n10998
FCITOFCO_D --- 0.162 R19C7B.FCI to R19C7B.FCO SLICE_66
ROUTE 1 0.000 R19C7B.FCO to R19C7C.FCI n10999
FCITOFCO_D --- 0.162 R19C7C.FCI to R19C7C.FCO SLICE_65
ROUTE 1 0.000 R19C7C.FCO to R19C7D.FCI n11000
FCITOFCO_D --- 0.162 R19C7D.FCI to R19C7D.FCO SLICE_64
ROUTE 1 0.000 R19C7D.FCO to R19C8A.FCI n11001
FCITOFCO_D --- 0.162 R19C8A.FCI to R19C8A.FCO SLICE_63
ROUTE 1 0.000 R19C8A.FCO to R19C8B.FCI n11002
FCITOFCO_D --- 0.162 R19C8B.FCI to R19C8B.FCO SLICE_62
ROUTE 1 0.000 R19C8B.FCO to R19C8C.FCI n11003
FCITOFCO_D --- 0.162 R19C8C.FCI to R19C8C.FCO SLICE_61
ROUTE 1 0.000 R19C8C.FCO to R19C8D.FCI n11004
FCITOFCO_D --- 0.162 R19C8D.FCI to R19C8D.FCO SLICE_60
ROUTE 1 0.000 R19C8D.FCO to R19C9A.FCI n11005
FCITOFCO_D --- 0.162 R19C9A.FCI to R19C9A.FCO SLICE_59
ROUTE 1 0.000 R19C9A.FCO to R19C9B.FCI n11006
FCITOFCO_D --- 0.162 R19C9B.FCI to R19C9B.FCO SLICE_58
ROUTE 1 0.000 R19C9B.FCO to R19C9C.FCI n11007
FCITOFCO_D --- 0.162 R19C9C.FCI to R19C9C.FCO SLICE_57
ROUTE 1 0.000 R19C9C.FCO to R19C9D.FCI n11008
FCITOFCO_D --- 0.162 R19C9D.FCI to R19C9D.FCO SLICE_56
ROUTE 1 0.000 R19C9D.FCO to R19C10A.FCI n11009
FCITOF1_DE --- 0.643 R19C10A.FCI to R19C10A.F1 SLICE_55
ROUTE 1 0.000 R19C10A.F1 to R19C10A.DI1 n2817 (to osc_clk)
--------
15.021 (57.5% logic, 42.5% route), 35 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2432:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.162 OSC.OSC to R21C8A.CLK osc_clk
--------
4.162 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R19C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.818ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i63 (to osc_clk +)
Delay: 14.967ns (59.0% logic, 41.0% route), 37 logic levels.
Constraint Details:
14.967ns physical path delay SLICE_2432 to SLICE_55 exceeds
11.278ns delay constraint less
-0.037ns skew and
0.166ns DIN_SET requirement (totaling 11.149ns) by 3.818ns
Physical Path Details:
Data path SLICE_2432 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R21C8A.CLK to R21C8A.Q0 SLICE_2432 (from osc_clk)
ROUTE 4 1.298 R21C8A.Q0 to R21C16C.C0 o_Rx_DV
CTOF_DEL --- 0.495 R21C16C.C0 to R21C16C.F0 SLICE_2476
ROUTE 4 1.160 R21C16C.F0 to R19C17D.C0 n8250
CTOF_DEL --- 0.495 R19C17D.C0 to R19C17D.F0 SLICE_2435
ROUTE 5 0.675 R19C17D.F0 to R19C15B.D1 n12533
CTOF_DEL --- 0.495 R19C15B.D1 to R19C15B.F1 SLICE_2394
ROUTE 52 1.335 R19C15B.F1 to R19C10C.C0 n13057
CTOF_DEL --- 0.495 R19C10C.C0 to R19C10C.F0 SLICE_2418
ROUTE 1 1.675 R19C10C.F0 to R19C2B.C1 n2361
C1TOFCO_DE --- 0.889 R19C2B.C1 to R19C2B.FCO SLICE_86
ROUTE 1 0.000 R19C2B.FCO to R19C2C.FCI n10979
FCITOFCO_D --- 0.162 R19C2C.FCI to R19C2C.FCO SLICE_85
ROUTE 1 0.000 R19C2C.FCO to R19C2D.FCI n10980
FCITOFCO_D --- 0.162 R19C2D.FCI to R19C2D.FCO SLICE_84
ROUTE 1 0.000 R19C2D.FCO to R19C3A.FCI n10981
FCITOFCO_D --- 0.162 R19C3A.FCI to R19C3A.FCO SLICE_83
ROUTE 1 0.000 R19C3A.FCO to R19C3B.FCI n10982
FCITOFCO_D --- 0.162 R19C3B.FCI to R19C3B.FCO SLICE_82
ROUTE 1 0.000 R19C3B.FCO to R19C3C.FCI n10983
FCITOFCO_D --- 0.162 R19C3C.FCI to R19C3C.FCO SLICE_81
ROUTE 1 0.000 R19C3C.FCO to R19C3D.FCI n10984
FCITOFCO_D --- 0.162 R19C3D.FCI to R19C3D.FCO SLICE_80
ROUTE 1 0.000 R19C3D.FCO to R19C4A.FCI n10985
FCITOFCO_D --- 0.162 R19C4A.FCI to R19C4A.FCO SLICE_79
ROUTE 1 0.000 R19C4A.FCO to R19C4B.FCI n10986
FCITOFCO_D --- 0.162 R19C4B.FCI to R19C4B.FCO SLICE_78
ROUTE 1 0.000 R19C4B.FCO to R19C4C.FCI n10987
FCITOFCO_D --- 0.162 R19C4C.FCI to R19C4C.FCO SLICE_77
ROUTE 1 0.000 R19C4C.FCO to R19C4D.FCI n10988
FCITOFCO_D --- 0.162 R19C4D.FCI to R19C4D.FCO SLICE_76
ROUTE 1 0.000 R19C4D.FCO to R19C5A.FCI n10989
FCITOFCO_D --- 0.162 R19C5A.FCI to R19C5A.FCO SLICE_75
ROUTE 1 0.000 R19C5A.FCO to R19C5B.FCI n10990
FCITOFCO_D --- 0.162 R19C5B.FCI to R19C5B.FCO SLICE_74
ROUTE 1 0.000 R19C5B.FCO to R19C5C.FCI n10991
FCITOFCO_D --- 0.162 R19C5C.FCI to R19C5C.FCO SLICE_73
ROUTE 1 0.000 R19C5C.FCO to R19C5D.FCI n10992
FCITOFCO_D --- 0.162 R19C5D.FCI to R19C5D.FCO SLICE_72
ROUTE 1 0.000 R19C5D.FCO to R19C6A.FCI n10993
FCITOFCO_D --- 0.162 R19C6A.FCI to R19C6A.FCO SLICE_71
ROUTE 1 0.000 R19C6A.FCO to R19C6B.FCI n10994
FCITOFCO_D --- 0.162 R19C6B.FCI to R19C6B.FCO SLICE_70
ROUTE 1 0.000 R19C6B.FCO to R19C6C.FCI n10995
FCITOFCO_D --- 0.162 R19C6C.FCI to R19C6C.FCO SLICE_69
ROUTE 1 0.000 R19C6C.FCO to R19C6D.FCI n10996
FCITOFCO_D --- 0.162 R19C6D.FCI to R19C6D.FCO SLICE_68
ROUTE 1 0.000 R19C6D.FCO to R19C7A.FCI n10997
FCITOFCO_D --- 0.162 R19C7A.FCI to R19C7A.FCO SLICE_67
ROUTE 1 0.000 R19C7A.FCO to R19C7B.FCI n10998
FCITOFCO_D --- 0.162 R19C7B.FCI to R19C7B.FCO SLICE_66
ROUTE 1 0.000 R19C7B.FCO to R19C7C.FCI n10999
FCITOFCO_D --- 0.162 R19C7C.FCI to R19C7C.FCO SLICE_65
ROUTE 1 0.000 R19C7C.FCO to R19C7D.FCI n11000
FCITOFCO_D --- 0.162 R19C7D.FCI to R19C7D.FCO SLICE_64
ROUTE 1 0.000 R19C7D.FCO to R19C8A.FCI n11001
FCITOFCO_D --- 0.162 R19C8A.FCI to R19C8A.FCO SLICE_63
ROUTE 1 0.000 R19C8A.FCO to R19C8B.FCI n11002
FCITOFCO_D --- 0.162 R19C8B.FCI to R19C8B.FCO SLICE_62
ROUTE 1 0.000 R19C8B.FCO to R19C8C.FCI n11003
FCITOFCO_D --- 0.162 R19C8C.FCI to R19C8C.FCO SLICE_61
ROUTE 1 0.000 R19C8C.FCO to R19C8D.FCI n11004
FCITOFCO_D --- 0.162 R19C8D.FCI to R19C8D.FCO SLICE_60
ROUTE 1 0.000 R19C8D.FCO to R19C9A.FCI n11005
FCITOFCO_D --- 0.162 R19C9A.FCI to R19C9A.FCO SLICE_59
ROUTE 1 0.000 R19C9A.FCO to R19C9B.FCI n11006
FCITOFCO_D --- 0.162 R19C9B.FCI to R19C9B.FCO SLICE_58
ROUTE 1 0.000 R19C9B.FCO to R19C9C.FCI n11007
FCITOFCO_D --- 0.162 R19C9C.FCI to R19C9C.FCO SLICE_57
ROUTE 1 0.000 R19C9C.FCO to R19C9D.FCI n11008
FCITOFCO_D --- 0.162 R19C9D.FCI to R19C9D.FCO SLICE_56
ROUTE 1 0.000 R19C9D.FCO to R19C10A.FCI n11009
FCITOF1_DE --- 0.643 R19C10A.FCI to R19C10A.F1 SLICE_55
ROUTE 1 0.000 R19C10A.F1 to R19C10A.DI1 n2817 (to osc_clk)
--------
14.967 (59.0% logic, 41.0% route), 37 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2432:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.162 OSC.OSC to R21C8A.CLK osc_clk
--------
4.162 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R19C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.814ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i62 (to osc_clk +)
Delay: 14.963ns (57.3% logic, 42.7% route), 35 logic levels.
Constraint Details:
14.963ns physical path delay SLICE_2432 to SLICE_55 exceeds
11.278ns delay constraint less
-0.037ns skew and
0.166ns DIN_SET requirement (totaling 11.149ns) by 3.814ns
Physical Path Details:
Data path SLICE_2432 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R21C8A.CLK to R21C8A.Q0 SLICE_2432 (from osc_clk)
ROUTE 4 1.298 R21C8A.Q0 to R21C16C.C0 o_Rx_DV
CTOF_DEL --- 0.495 R21C16C.C0 to R21C16C.F0 SLICE_2476
ROUTE 4 1.160 R21C16C.F0 to R19C17D.C0 n8250
CTOF_DEL --- 0.495 R19C17D.C0 to R19C17D.F0 SLICE_2435
ROUTE 5 0.675 R19C17D.F0 to R19C15B.D1 n12533
CTOF_DEL --- 0.495 R19C15B.D1 to R19C15B.F1 SLICE_2394
ROUTE 52 1.080 R19C15B.F1 to R19C16C.B0 n13057
CTOF_DEL --- 0.495 R19C16C.B0 to R19C16C.F0 SLICE_2414
ROUTE 1 2.174 R19C16C.F0 to R19C2D.C0 n2358
C0TOFCO_DE --- 1.023 R19C2D.C0 to R19C2D.FCO SLICE_84
ROUTE 1 0.000 R19C2D.FCO to R19C3A.FCI n10981
FCITOFCO_D --- 0.162 R19C3A.FCI to R19C3A.FCO SLICE_83
ROUTE 1 0.000 R19C3A.FCO to R19C3B.FCI n10982
FCITOFCO_D --- 0.162 R19C3B.FCI to R19C3B.FCO SLICE_82
ROUTE 1 0.000 R19C3B.FCO to R19C3C.FCI n10983
FCITOFCO_D --- 0.162 R19C3C.FCI to R19C3C.FCO SLICE_81
ROUTE 1 0.000 R19C3C.FCO to R19C3D.FCI n10984
FCITOFCO_D --- 0.162 R19C3D.FCI to R19C3D.FCO SLICE_80
ROUTE 1 0.000 R19C3D.FCO to R19C4A.FCI n10985
FCITOFCO_D --- 0.162 R19C4A.FCI to R19C4A.FCO SLICE_79
ROUTE 1 0.000 R19C4A.FCO to R19C4B.FCI n10986
FCITOFCO_D --- 0.162 R19C4B.FCI to R19C4B.FCO SLICE_78
ROUTE 1 0.000 R19C4B.FCO to R19C4C.FCI n10987
FCITOFCO_D --- 0.162 R19C4C.FCI to R19C4C.FCO SLICE_77
ROUTE 1 0.000 R19C4C.FCO to R19C4D.FCI n10988
FCITOFCO_D --- 0.162 R19C4D.FCI to R19C4D.FCO SLICE_76
ROUTE 1 0.000 R19C4D.FCO to R19C5A.FCI n10989
FCITOFCO_D --- 0.162 R19C5A.FCI to R19C5A.FCO SLICE_75
ROUTE 1 0.000 R19C5A.FCO to R19C5B.FCI n10990
FCITOFCO_D --- 0.162 R19C5B.FCI to R19C5B.FCO SLICE_74
ROUTE 1 0.000 R19C5B.FCO to R19C5C.FCI n10991
FCITOFCO_D --- 0.162 R19C5C.FCI to R19C5C.FCO SLICE_73
ROUTE 1 0.000 R19C5C.FCO to R19C5D.FCI n10992
FCITOFCO_D --- 0.162 R19C5D.FCI to R19C5D.FCO SLICE_72
ROUTE 1 0.000 R19C5D.FCO to R19C6A.FCI n10993
FCITOFCO_D --- 0.162 R19C6A.FCI to R19C6A.FCO SLICE_71
ROUTE 1 0.000 R19C6A.FCO to R19C6B.FCI n10994
FCITOFCO_D --- 0.162 R19C6B.FCI to R19C6B.FCO SLICE_70
ROUTE 1 0.000 R19C6B.FCO to R19C6C.FCI n10995
FCITOFCO_D --- 0.162 R19C6C.FCI to R19C6C.FCO SLICE_69
ROUTE 1 0.000 R19C6C.FCO to R19C6D.FCI n10996
FCITOFCO_D --- 0.162 R19C6D.FCI to R19C6D.FCO SLICE_68
ROUTE 1 0.000 R19C6D.FCO to R19C7A.FCI n10997
FCITOFCO_D --- 0.162 R19C7A.FCI to R19C7A.FCO SLICE_67
ROUTE 1 0.000 R19C7A.FCO to R19C7B.FCI n10998
FCITOFCO_D --- 0.162 R19C7B.FCI to R19C7B.FCO SLICE_66
ROUTE 1 0.000 R19C7B.FCO to R19C7C.FCI n10999
FCITOFCO_D --- 0.162 R19C7C.FCI to R19C7C.FCO SLICE_65
ROUTE 1 0.000 R19C7C.FCO to R19C7D.FCI n11000
FCITOFCO_D --- 0.162 R19C7D.FCI to R19C7D.FCO SLICE_64
ROUTE 1 0.000 R19C7D.FCO to R19C8A.FCI n11001
FCITOFCO_D --- 0.162 R19C8A.FCI to R19C8A.FCO SLICE_63
ROUTE 1 0.000 R19C8A.FCO to R19C8B.FCI n11002
FCITOFCO_D --- 0.162 R19C8B.FCI to R19C8B.FCO SLICE_62
ROUTE 1 0.000 R19C8B.FCO to R19C8C.FCI n11003
FCITOFCO_D --- 0.162 R19C8C.FCI to R19C8C.FCO SLICE_61
ROUTE 1 0.000 R19C8C.FCO to R19C8D.FCI n11004
FCITOFCO_D --- 0.162 R19C8D.FCI to R19C8D.FCO SLICE_60
ROUTE 1 0.000 R19C8D.FCO to R19C9A.FCI n11005
FCITOFCO_D --- 0.162 R19C9A.FCI to R19C9A.FCO SLICE_59
ROUTE 1 0.000 R19C9A.FCO to R19C9B.FCI n11006
FCITOFCO_D --- 0.162 R19C9B.FCI to R19C9B.FCO SLICE_58
ROUTE 1 0.000 R19C9B.FCO to R19C9C.FCI n11007
FCITOFCO_D --- 0.162 R19C9C.FCI to R19C9C.FCO SLICE_57
ROUTE 1 0.000 R19C9C.FCO to R19C9D.FCI n11008
FCITOFCO_D --- 0.162 R19C9D.FCI to R19C9D.FCO SLICE_56
ROUTE 1 0.000 R19C9D.FCO to R19C10A.FCI n11009
FCITOF0_DE --- 0.585 R19C10A.FCI to R19C10A.F0 SLICE_55
ROUTE 1 0.000 R19C10A.F0 to R19C10A.DI0 n2818 (to osc_clk)
--------
14.963 (57.3% logic, 42.7% route), 35 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2432:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.162 OSC.OSC to R21C8A.CLK osc_clk
--------
4.162 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R19C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.766ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q phase_inc_carrGen_i0_i5 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i63 (to osc_clk +)
Delay: 14.879ns (60.4% logic, 39.6% route), 33 logic levels.
Constraint Details:
14.879ns physical path delay SLICE_84 to SLICE_55 exceeds
11.278ns delay constraint less
-0.001ns skew and
0.166ns DIN_SET requirement (totaling 11.113ns) by 3.766ns
Physical Path Details:
Data path SLICE_84 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R19C2D.CLK to R19C2D.Q1 SLICE_84 (from osc_clk)
ROUTE 4 1.426 R19C2D.Q1 to R18C4B.A0 phase_inc_carrGen_5
C0TOFCO_DE --- 1.023 R18C4B.A0 to R18C4B.FCO SLICE_131
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10808
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_130
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10809
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_129
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10810
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_128
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10811
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_127
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10812
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_126
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10813
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_125
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10814
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_124
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10815
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_123
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10816
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_122
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10817
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_121
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10818
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_120
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10819
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_119
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10820
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_118
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n10821
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_117
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n10822
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_116
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n10823
FCITOF1_DE --- 0.643 R18C8B.FCI to R18C8B.F1 SLICE_115
ROUTE 1 1.278 R18C8B.F1 to R18C15A.C0 n1056
CTOF_DEL --- 0.495 R18C15A.C0 to R18C15A.F0 SLICE_2482
ROUTE 1 1.001 R18C15A.F0 to R19C15B.B0 n7813
CTOF_DEL --- 0.495 R19C15B.B0 to R19C15B.F0 SLICE_2394
ROUTE 1 2.188 R19C15B.F0 to R19C7A.C0 n2324
C0TOFCO_DE --- 1.023 R19C7A.C0 to R19C7A.FCO SLICE_67
ROUTE 1 0.000 R19C7A.FCO to R19C7B.FCI n10998
FCITOFCO_D --- 0.162 R19C7B.FCI to R19C7B.FCO SLICE_66
ROUTE 1 0.000 R19C7B.FCO to R19C7C.FCI n10999
FCITOFCO_D --- 0.162 R19C7C.FCI to R19C7C.FCO SLICE_65
ROUTE 1 0.000 R19C7C.FCO to R19C7D.FCI n11000
FCITOFCO_D --- 0.162 R19C7D.FCI to R19C7D.FCO SLICE_64
ROUTE 1 0.000 R19C7D.FCO to R19C8A.FCI n11001
FCITOFCO_D --- 0.162 R19C8A.FCI to R19C8A.FCO SLICE_63
ROUTE 1 0.000 R19C8A.FCO to R19C8B.FCI n11002
FCITOFCO_D --- 0.162 R19C8B.FCI to R19C8B.FCO SLICE_62
ROUTE 1 0.000 R19C8B.FCO to R19C8C.FCI n11003
FCITOFCO_D --- 0.162 R19C8C.FCI to R19C8C.FCO SLICE_61
ROUTE 1 0.000 R19C8C.FCO to R19C8D.FCI n11004
FCITOFCO_D --- 0.162 R19C8D.FCI to R19C8D.FCO SLICE_60
ROUTE 1 0.000 R19C8D.FCO to R19C9A.FCI n11005
FCITOFCO_D --- 0.162 R19C9A.FCI to R19C9A.FCO SLICE_59
ROUTE 1 0.000 R19C9A.FCO to R19C9B.FCI n11006
FCITOFCO_D --- 0.162 R19C9B.FCI to R19C9B.FCO SLICE_58
ROUTE 1 0.000 R19C9B.FCO to R19C9C.FCI n11007
FCITOFCO_D --- 0.162 R19C9C.FCI to R19C9C.FCO SLICE_57
ROUTE 1 0.000 R19C9C.FCO to R19C9D.FCI n11008
FCITOFCO_D --- 0.162 R19C9D.FCI to R19C9D.FCO SLICE_56
ROUTE 1 0.000 R19C9D.FCO to R19C10A.FCI n11009
FCITOF1_DE --- 0.643 R19C10A.FCI to R19C10A.F1 SLICE_55
ROUTE 1 0.000 R19C10A.F1 to R19C10A.DI1 n2817 (to osc_clk)
--------
14.879 (60.4% logic, 39.6% route), 33 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.198 OSC.OSC to R19C2D.CLK osc_clk
--------
4.198 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R19C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.760ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i62 (to osc_clk +)
Delay: 14.909ns (58.8% logic, 41.2% route), 37 logic levels.
Constraint Details:
14.909ns physical path delay SLICE_2432 to SLICE_55 exceeds
11.278ns delay constraint less
-0.037ns skew and
0.166ns DIN_SET requirement (totaling 11.149ns) by 3.760ns
Physical Path Details:
Data path SLICE_2432 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R21C8A.CLK to R21C8A.Q0 SLICE_2432 (from osc_clk)
ROUTE 4 1.298 R21C8A.Q0 to R21C16C.C0 o_Rx_DV
CTOF_DEL --- 0.495 R21C16C.C0 to R21C16C.F0 SLICE_2476
ROUTE 4 1.160 R21C16C.F0 to R19C17D.C0 n8250
CTOF_DEL --- 0.495 R19C17D.C0 to R19C17D.F0 SLICE_2435
ROUTE 5 0.675 R19C17D.F0 to R19C15B.D1 n12533
CTOF_DEL --- 0.495 R19C15B.D1 to R19C15B.F1 SLICE_2394
ROUTE 52 1.335 R19C15B.F1 to R19C10C.C0 n13057
CTOF_DEL --- 0.495 R19C10C.C0 to R19C10C.F0 SLICE_2418
ROUTE 1 1.675 R19C10C.F0 to R19C2B.C1 n2361
C1TOFCO_DE --- 0.889 R19C2B.C1 to R19C2B.FCO SLICE_86
ROUTE 1 0.000 R19C2B.FCO to R19C2C.FCI n10979
FCITOFCO_D --- 0.162 R19C2C.FCI to R19C2C.FCO SLICE_85
ROUTE 1 0.000 R19C2C.FCO to R19C2D.FCI n10980
FCITOFCO_D --- 0.162 R19C2D.FCI to R19C2D.FCO SLICE_84
ROUTE 1 0.000 R19C2D.FCO to R19C3A.FCI n10981
FCITOFCO_D --- 0.162 R19C3A.FCI to R19C3A.FCO SLICE_83
ROUTE 1 0.000 R19C3A.FCO to R19C3B.FCI n10982
FCITOFCO_D --- 0.162 R19C3B.FCI to R19C3B.FCO SLICE_82
ROUTE 1 0.000 R19C3B.FCO to R19C3C.FCI n10983
FCITOFCO_D --- 0.162 R19C3C.FCI to R19C3C.FCO SLICE_81
ROUTE 1 0.000 R19C3C.FCO to R19C3D.FCI n10984
FCITOFCO_D --- 0.162 R19C3D.FCI to R19C3D.FCO SLICE_80
ROUTE 1 0.000 R19C3D.FCO to R19C4A.FCI n10985
FCITOFCO_D --- 0.162 R19C4A.FCI to R19C4A.FCO SLICE_79
ROUTE 1 0.000 R19C4A.FCO to R19C4B.FCI n10986
FCITOFCO_D --- 0.162 R19C4B.FCI to R19C4B.FCO SLICE_78
ROUTE 1 0.000 R19C4B.FCO to R19C4C.FCI n10987
FCITOFCO_D --- 0.162 R19C4C.FCI to R19C4C.FCO SLICE_77
ROUTE 1 0.000 R19C4C.FCO to R19C4D.FCI n10988
FCITOFCO_D --- 0.162 R19C4D.FCI to R19C4D.FCO SLICE_76
ROUTE 1 0.000 R19C4D.FCO to R19C5A.FCI n10989
FCITOFCO_D --- 0.162 R19C5A.FCI to R19C5A.FCO SLICE_75
ROUTE 1 0.000 R19C5A.FCO to R19C5B.FCI n10990
FCITOFCO_D --- 0.162 R19C5B.FCI to R19C5B.FCO SLICE_74
ROUTE 1 0.000 R19C5B.FCO to R19C5C.FCI n10991
FCITOFCO_D --- 0.162 R19C5C.FCI to R19C5C.FCO SLICE_73
ROUTE 1 0.000 R19C5C.FCO to R19C5D.FCI n10992
FCITOFCO_D --- 0.162 R19C5D.FCI to R19C5D.FCO SLICE_72
ROUTE 1 0.000 R19C5D.FCO to R19C6A.FCI n10993
FCITOFCO_D --- 0.162 R19C6A.FCI to R19C6A.FCO SLICE_71
ROUTE 1 0.000 R19C6A.FCO to R19C6B.FCI n10994
FCITOFCO_D --- 0.162 R19C6B.FCI to R19C6B.FCO SLICE_70
ROUTE 1 0.000 R19C6B.FCO to R19C6C.FCI n10995
FCITOFCO_D --- 0.162 R19C6C.FCI to R19C6C.FCO SLICE_69
ROUTE 1 0.000 R19C6C.FCO to R19C6D.FCI n10996
FCITOFCO_D --- 0.162 R19C6D.FCI to R19C6D.FCO SLICE_68
ROUTE 1 0.000 R19C6D.FCO to R19C7A.FCI n10997
FCITOFCO_D --- 0.162 R19C7A.FCI to R19C7A.FCO SLICE_67
ROUTE 1 0.000 R19C7A.FCO to R19C7B.FCI n10998
FCITOFCO_D --- 0.162 R19C7B.FCI to R19C7B.FCO SLICE_66
ROUTE 1 0.000 R19C7B.FCO to R19C7C.FCI n10999
FCITOFCO_D --- 0.162 R19C7C.FCI to R19C7C.FCO SLICE_65
ROUTE 1 0.000 R19C7C.FCO to R19C7D.FCI n11000
FCITOFCO_D --- 0.162 R19C7D.FCI to R19C7D.FCO SLICE_64
ROUTE 1 0.000 R19C7D.FCO to R19C8A.FCI n11001
FCITOFCO_D --- 0.162 R19C8A.FCI to R19C8A.FCO SLICE_63
ROUTE 1 0.000 R19C8A.FCO to R19C8B.FCI n11002
FCITOFCO_D --- 0.162 R19C8B.FCI to R19C8B.FCO SLICE_62
ROUTE 1 0.000 R19C8B.FCO to R19C8C.FCI n11003
FCITOFCO_D --- 0.162 R19C8C.FCI to R19C8C.FCO SLICE_61
ROUTE 1 0.000 R19C8C.FCO to R19C8D.FCI n11004
FCITOFCO_D --- 0.162 R19C8D.FCI to R19C8D.FCO SLICE_60
ROUTE 1 0.000 R19C8D.FCO to R19C9A.FCI n11005
FCITOFCO_D --- 0.162 R19C9A.FCI to R19C9A.FCO SLICE_59
ROUTE 1 0.000 R19C9A.FCO to R19C9B.FCI n11006
FCITOFCO_D --- 0.162 R19C9B.FCI to R19C9B.FCO SLICE_58
ROUTE 1 0.000 R19C9B.FCO to R19C9C.FCI n11007
FCITOFCO_D --- 0.162 R19C9C.FCI to R19C9C.FCO SLICE_57
ROUTE 1 0.000 R19C9C.FCO to R19C9D.FCI n11008
FCITOFCO_D --- 0.162 R19C9D.FCI to R19C9D.FCO SLICE_56
ROUTE 1 0.000 R19C9D.FCO to R19C10A.FCI n11009
FCITOF0_DE --- 0.585 R19C10A.FCI to R19C10A.F0 SLICE_55
ROUTE 1 0.000 R19C10A.F0 to R19C10A.DI0 n2818 (to osc_clk)
--------
14.909 (58.8% logic, 41.2% route), 37 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2432:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.162 OSC.OSC to R21C8A.CLK osc_clk
--------
4.162 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R19C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.747ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i63 (to osc_clk +)
Delay: 14.896ns (59.2% logic, 40.8% route), 37 logic levels.
Constraint Details:
14.896ns physical path delay SLICE_2432 to SLICE_55 exceeds
11.278ns delay constraint less
-0.037ns skew and
0.166ns DIN_SET requirement (totaling 11.149ns) by 3.747ns
Physical Path Details:
Data path SLICE_2432 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R21C8A.CLK to R21C8A.Q0 SLICE_2432 (from osc_clk)
ROUTE 4 1.298 R21C8A.Q0 to R21C16C.C0 o_Rx_DV
CTOF_DEL --- 0.495 R21C16C.C0 to R21C16C.F0 SLICE_2476
ROUTE 4 1.160 R21C16C.F0 to R19C17D.C0 n8250
CTOF_DEL --- 0.495 R19C17D.C0 to R19C17D.F0 SLICE_2435
ROUTE 5 0.675 R19C17D.F0 to R19C15D.D1 n12533
CTOF_DEL --- 0.495 R19C15D.D1 to R19C15D.F1 SLICE_2389
ROUTE 49 1.264 R19C15D.F1 to R19C10C.D0 n2563
CTOF_DEL --- 0.495 R19C10C.D0 to R19C10C.F0 SLICE_2418
ROUTE 1 1.675 R19C10C.F0 to R19C2B.C1 n2361
C1TOFCO_DE --- 0.889 R19C2B.C1 to R19C2B.FCO SLICE_86
ROUTE 1 0.000 R19C2B.FCO to R19C2C.FCI n10979
FCITOFCO_D --- 0.162 R19C2C.FCI to R19C2C.FCO SLICE_85
ROUTE 1 0.000 R19C2C.FCO to R19C2D.FCI n10980
FCITOFCO_D --- 0.162 R19C2D.FCI to R19C2D.FCO SLICE_84
ROUTE 1 0.000 R19C2D.FCO to R19C3A.FCI n10981
FCITOFCO_D --- 0.162 R19C3A.FCI to R19C3A.FCO SLICE_83
ROUTE 1 0.000 R19C3A.FCO to R19C3B.FCI n10982
FCITOFCO_D --- 0.162 R19C3B.FCI to R19C3B.FCO SLICE_82
ROUTE 1 0.000 R19C3B.FCO to R19C3C.FCI n10983
FCITOFCO_D --- 0.162 R19C3C.FCI to R19C3C.FCO SLICE_81
ROUTE 1 0.000 R19C3C.FCO to R19C3D.FCI n10984
FCITOFCO_D --- 0.162 R19C3D.FCI to R19C3D.FCO SLICE_80
ROUTE 1 0.000 R19C3D.FCO to R19C4A.FCI n10985
FCITOFCO_D --- 0.162 R19C4A.FCI to R19C4A.FCO SLICE_79
ROUTE 1 0.000 R19C4A.FCO to R19C4B.FCI n10986
FCITOFCO_D --- 0.162 R19C4B.FCI to R19C4B.FCO SLICE_78
ROUTE 1 0.000 R19C4B.FCO to R19C4C.FCI n10987
FCITOFCO_D --- 0.162 R19C4C.FCI to R19C4C.FCO SLICE_77
ROUTE 1 0.000 R19C4C.FCO to R19C4D.FCI n10988
FCITOFCO_D --- 0.162 R19C4D.FCI to R19C4D.FCO SLICE_76
ROUTE 1 0.000 R19C4D.FCO to R19C5A.FCI n10989
FCITOFCO_D --- 0.162 R19C5A.FCI to R19C5A.FCO SLICE_75
ROUTE 1 0.000 R19C5A.FCO to R19C5B.FCI n10990
FCITOFCO_D --- 0.162 R19C5B.FCI to R19C5B.FCO SLICE_74
ROUTE 1 0.000 R19C5B.FCO to R19C5C.FCI n10991
FCITOFCO_D --- 0.162 R19C5C.FCI to R19C5C.FCO SLICE_73
ROUTE 1 0.000 R19C5C.FCO to R19C5D.FCI n10992
FCITOFCO_D --- 0.162 R19C5D.FCI to R19C5D.FCO SLICE_72
ROUTE 1 0.000 R19C5D.FCO to R19C6A.FCI n10993
FCITOFCO_D --- 0.162 R19C6A.FCI to R19C6A.FCO SLICE_71
ROUTE 1 0.000 R19C6A.FCO to R19C6B.FCI n10994
FCITOFCO_D --- 0.162 R19C6B.FCI to R19C6B.FCO SLICE_70
ROUTE 1 0.000 R19C6B.FCO to R19C6C.FCI n10995
FCITOFCO_D --- 0.162 R19C6C.FCI to R19C6C.FCO SLICE_69
ROUTE 1 0.000 R19C6C.FCO to R19C6D.FCI n10996
FCITOFCO_D --- 0.162 R19C6D.FCI to R19C6D.FCO SLICE_68
ROUTE 1 0.000 R19C6D.FCO to R19C7A.FCI n10997
FCITOFCO_D --- 0.162 R19C7A.FCI to R19C7A.FCO SLICE_67
ROUTE 1 0.000 R19C7A.FCO to R19C7B.FCI n10998
FCITOFCO_D --- 0.162 R19C7B.FCI to R19C7B.FCO SLICE_66
ROUTE 1 0.000 R19C7B.FCO to R19C7C.FCI n10999
FCITOFCO_D --- 0.162 R19C7C.FCI to R19C7C.FCO SLICE_65
ROUTE 1 0.000 R19C7C.FCO to R19C7D.FCI n11000
FCITOFCO_D --- 0.162 R19C7D.FCI to R19C7D.FCO SLICE_64
ROUTE 1 0.000 R19C7D.FCO to R19C8A.FCI n11001
FCITOFCO_D --- 0.162 R19C8A.FCI to R19C8A.FCO SLICE_63
ROUTE 1 0.000 R19C8A.FCO to R19C8B.FCI n11002
FCITOFCO_D --- 0.162 R19C8B.FCI to R19C8B.FCO SLICE_62
ROUTE 1 0.000 R19C8B.FCO to R19C8C.FCI n11003
FCITOFCO_D --- 0.162 R19C8C.FCI to R19C8C.FCO SLICE_61
ROUTE 1 0.000 R19C8C.FCO to R19C8D.FCI n11004
FCITOFCO_D --- 0.162 R19C8D.FCI to R19C8D.FCO SLICE_60
ROUTE 1 0.000 R19C8D.FCO to R19C9A.FCI n11005
FCITOFCO_D --- 0.162 R19C9A.FCI to R19C9A.FCO SLICE_59
ROUTE 1 0.000 R19C9A.FCO to R19C9B.FCI n11006
FCITOFCO_D --- 0.162 R19C9B.FCI to R19C9B.FCO SLICE_58
ROUTE 1 0.000 R19C9B.FCO to R19C9C.FCI n11007
FCITOFCO_D --- 0.162 R19C9C.FCI to R19C9C.FCO SLICE_57
ROUTE 1 0.000 R19C9C.FCO to R19C9D.FCI n11008
FCITOFCO_D --- 0.162 R19C9D.FCI to R19C9D.FCO SLICE_56
ROUTE 1 0.000 R19C9D.FCO to R19C10A.FCI n11009
FCITOF1_DE --- 0.643 R19C10A.FCI to R19C10A.F1 SLICE_55
ROUTE 1 0.000 R19C10A.F1 to R19C10A.DI1 n2817 (to osc_clk)
--------
14.896 (59.2% logic, 40.8% route), 37 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2432:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.162 OSC.OSC to R21C8A.CLK osc_clk
--------
4.162 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R19C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.742ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i63 (to osc_clk +)
Delay: 14.891ns (58.0% logic, 42.0% route), 35 logic levels.
Constraint Details:
14.891ns physical path delay SLICE_2432 to SLICE_55 exceeds
11.278ns delay constraint less
-0.037ns skew and
0.166ns DIN_SET requirement (totaling 11.149ns) by 3.742ns
Physical Path Details:
Data path SLICE_2432 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R21C8A.CLK to R21C8A.Q0 SLICE_2432 (from osc_clk)
ROUTE 4 1.298 R21C8A.Q0 to R21C16C.C0 o_Rx_DV
CTOF_DEL --- 0.495 R21C16C.C0 to R21C16C.F0 SLICE_2476
ROUTE 4 1.495 R21C16C.F0 to R19C14A.A0 n8250
CTOF_DEL --- 0.495 R19C14A.A0 to R19C14A.F0 SLICE_2372
ROUTE 44 0.854 R19C14A.F0 to R19C16C.C1 n13064
CTOF_DEL --- 0.495 R19C16C.C1 to R19C16C.F1 SLICE_2414
ROUTE 1 0.436 R19C16C.F1 to R19C16C.C0 n7753
CTOF_DEL --- 0.495 R19C16C.C0 to R19C16C.F0 SLICE_2414
ROUTE 1 2.174 R19C16C.F0 to R19C2D.C0 n2358
C0TOFCO_DE --- 1.023 R19C2D.C0 to R19C2D.FCO SLICE_84
ROUTE 1 0.000 R19C2D.FCO to R19C3A.FCI n10981
FCITOFCO_D --- 0.162 R19C3A.FCI to R19C3A.FCO SLICE_83
ROUTE 1 0.000 R19C3A.FCO to R19C3B.FCI n10982
FCITOFCO_D --- 0.162 R19C3B.FCI to R19C3B.FCO SLICE_82
ROUTE 1 0.000 R19C3B.FCO to R19C3C.FCI n10983
FCITOFCO_D --- 0.162 R19C3C.FCI to R19C3C.FCO SLICE_81
ROUTE 1 0.000 R19C3C.FCO to R19C3D.FCI n10984
FCITOFCO_D --- 0.162 R19C3D.FCI to R19C3D.FCO SLICE_80
ROUTE 1 0.000 R19C3D.FCO to R19C4A.FCI n10985
FCITOFCO_D --- 0.162 R19C4A.FCI to R19C4A.FCO SLICE_79
ROUTE 1 0.000 R19C4A.FCO to R19C4B.FCI n10986
FCITOFCO_D --- 0.162 R19C4B.FCI to R19C4B.FCO SLICE_78
ROUTE 1 0.000 R19C4B.FCO to R19C4C.FCI n10987
FCITOFCO_D --- 0.162 R19C4C.FCI to R19C4C.FCO SLICE_77
ROUTE 1 0.000 R19C4C.FCO to R19C4D.FCI n10988
FCITOFCO_D --- 0.162 R19C4D.FCI to R19C4D.FCO SLICE_76
ROUTE 1 0.000 R19C4D.FCO to R19C5A.FCI n10989
FCITOFCO_D --- 0.162 R19C5A.FCI to R19C5A.FCO SLICE_75
ROUTE 1 0.000 R19C5A.FCO to R19C5B.FCI n10990
FCITOFCO_D --- 0.162 R19C5B.FCI to R19C5B.FCO SLICE_74
ROUTE 1 0.000 R19C5B.FCO to R19C5C.FCI n10991
FCITOFCO_D --- 0.162 R19C5C.FCI to R19C5C.FCO SLICE_73
ROUTE 1 0.000 R19C5C.FCO to R19C5D.FCI n10992
FCITOFCO_D --- 0.162 R19C5D.FCI to R19C5D.FCO SLICE_72
ROUTE 1 0.000 R19C5D.FCO to R19C6A.FCI n10993
FCITOFCO_D --- 0.162 R19C6A.FCI to R19C6A.FCO SLICE_71
ROUTE 1 0.000 R19C6A.FCO to R19C6B.FCI n10994
FCITOFCO_D --- 0.162 R19C6B.FCI to R19C6B.FCO SLICE_70
ROUTE 1 0.000 R19C6B.FCO to R19C6C.FCI n10995
FCITOFCO_D --- 0.162 R19C6C.FCI to R19C6C.FCO SLICE_69
ROUTE 1 0.000 R19C6C.FCO to R19C6D.FCI n10996
FCITOFCO_D --- 0.162 R19C6D.FCI to R19C6D.FCO SLICE_68
ROUTE 1 0.000 R19C6D.FCO to R19C7A.FCI n10997
FCITOFCO_D --- 0.162 R19C7A.FCI to R19C7A.FCO SLICE_67
ROUTE 1 0.000 R19C7A.FCO to R19C7B.FCI n10998
FCITOFCO_D --- 0.162 R19C7B.FCI to R19C7B.FCO SLICE_66
ROUTE 1 0.000 R19C7B.FCO to R19C7C.FCI n10999
FCITOFCO_D --- 0.162 R19C7C.FCI to R19C7C.FCO SLICE_65
ROUTE 1 0.000 R19C7C.FCO to R19C7D.FCI n11000
FCITOFCO_D --- 0.162 R19C7D.FCI to R19C7D.FCO SLICE_64
ROUTE 1 0.000 R19C7D.FCO to R19C8A.FCI n11001
FCITOFCO_D --- 0.162 R19C8A.FCI to R19C8A.FCO SLICE_63
ROUTE 1 0.000 R19C8A.FCO to R19C8B.FCI n11002
FCITOFCO_D --- 0.162 R19C8B.FCI to R19C8B.FCO SLICE_62
ROUTE 1 0.000 R19C8B.FCO to R19C8C.FCI n11003
FCITOFCO_D --- 0.162 R19C8C.FCI to R19C8C.FCO SLICE_61
ROUTE 1 0.000 R19C8C.FCO to R19C8D.FCI n11004
FCITOFCO_D --- 0.162 R19C8D.FCI to R19C8D.FCO SLICE_60
ROUTE 1 0.000 R19C8D.FCO to R19C9A.FCI n11005
FCITOFCO_D --- 0.162 R19C9A.FCI to R19C9A.FCO SLICE_59
ROUTE 1 0.000 R19C9A.FCO to R19C9B.FCI n11006
FCITOFCO_D --- 0.162 R19C9B.FCI to R19C9B.FCO SLICE_58
ROUTE 1 0.000 R19C9B.FCO to R19C9C.FCI n11007
FCITOFCO_D --- 0.162 R19C9C.FCI to R19C9C.FCO SLICE_57
ROUTE 1 0.000 R19C9C.FCO to R19C9D.FCI n11008
FCITOFCO_D --- 0.162 R19C9D.FCI to R19C9D.FCO SLICE_56
ROUTE 1 0.000 R19C9D.FCO to R19C10A.FCI n11009
FCITOF1_DE --- 0.643 R19C10A.FCI to R19C10A.F1 SLICE_55
ROUTE 1 0.000 R19C10A.F1 to R19C10A.DI1 n2817 (to osc_clk)
--------
14.891 (58.0% logic, 42.0% route), 35 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2432:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.162 OSC.OSC to R21C8A.CLK osc_clk
--------
4.162 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R19C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.710ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i61 (to osc_clk +)
Delay: 14.859ns (57.0% logic, 43.0% route), 34 logic levels.
Constraint Details:
14.859ns physical path delay SLICE_2432 to SLICE_56 exceeds
11.278ns delay constraint less
-0.037ns skew and
0.166ns DIN_SET requirement (totaling 11.149ns) by 3.710ns
Physical Path Details:
Data path SLICE_2432 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R21C8A.CLK to R21C8A.Q0 SLICE_2432 (from osc_clk)
ROUTE 4 1.298 R21C8A.Q0 to R21C16C.C0 o_Rx_DV
CTOF_DEL --- 0.495 R21C16C.C0 to R21C16C.F0 SLICE_2476
ROUTE 4 1.160 R21C16C.F0 to R19C17D.C0 n8250
CTOF_DEL --- 0.495 R19C17D.C0 to R19C17D.F0 SLICE_2435
ROUTE 5 0.675 R19C17D.F0 to R19C15B.D1 n12533
CTOF_DEL --- 0.495 R19C15B.D1 to R19C15B.F1 SLICE_2394
ROUTE 52 1.080 R19C15B.F1 to R19C16C.B0 n13057
CTOF_DEL --- 0.495 R19C16C.B0 to R19C16C.F0 SLICE_2414
ROUTE 1 2.174 R19C16C.F0 to R19C2D.C0 n2358
C0TOFCO_DE --- 1.023 R19C2D.C0 to R19C2D.FCO SLICE_84
ROUTE 1 0.000 R19C2D.FCO to R19C3A.FCI n10981
FCITOFCO_D --- 0.162 R19C3A.FCI to R19C3A.FCO SLICE_83
ROUTE 1 0.000 R19C3A.FCO to R19C3B.FCI n10982
FCITOFCO_D --- 0.162 R19C3B.FCI to R19C3B.FCO SLICE_82
ROUTE 1 0.000 R19C3B.FCO to R19C3C.FCI n10983
FCITOFCO_D --- 0.162 R19C3C.FCI to R19C3C.FCO SLICE_81
ROUTE 1 0.000 R19C3C.FCO to R19C3D.FCI n10984
FCITOFCO_D --- 0.162 R19C3D.FCI to R19C3D.FCO SLICE_80
ROUTE 1 0.000 R19C3D.FCO to R19C4A.FCI n10985
FCITOFCO_D --- 0.162 R19C4A.FCI to R19C4A.FCO SLICE_79
ROUTE 1 0.000 R19C4A.FCO to R19C4B.FCI n10986
FCITOFCO_D --- 0.162 R19C4B.FCI to R19C4B.FCO SLICE_78
ROUTE 1 0.000 R19C4B.FCO to R19C4C.FCI n10987
FCITOFCO_D --- 0.162 R19C4C.FCI to R19C4C.FCO SLICE_77
ROUTE 1 0.000 R19C4C.FCO to R19C4D.FCI n10988
FCITOFCO_D --- 0.162 R19C4D.FCI to R19C4D.FCO SLICE_76
ROUTE 1 0.000 R19C4D.FCO to R19C5A.FCI n10989
FCITOFCO_D --- 0.162 R19C5A.FCI to R19C5A.FCO SLICE_75
ROUTE 1 0.000 R19C5A.FCO to R19C5B.FCI n10990
FCITOFCO_D --- 0.162 R19C5B.FCI to R19C5B.FCO SLICE_74
ROUTE 1 0.000 R19C5B.FCO to R19C5C.FCI n10991
FCITOFCO_D --- 0.162 R19C5C.FCI to R19C5C.FCO SLICE_73
ROUTE 1 0.000 R19C5C.FCO to R19C5D.FCI n10992
FCITOFCO_D --- 0.162 R19C5D.FCI to R19C5D.FCO SLICE_72
ROUTE 1 0.000 R19C5D.FCO to R19C6A.FCI n10993
FCITOFCO_D --- 0.162 R19C6A.FCI to R19C6A.FCO SLICE_71
ROUTE 1 0.000 R19C6A.FCO to R19C6B.FCI n10994
FCITOFCO_D --- 0.162 R19C6B.FCI to R19C6B.FCO SLICE_70
ROUTE 1 0.000 R19C6B.FCO to R19C6C.FCI n10995
FCITOFCO_D --- 0.162 R19C6C.FCI to R19C6C.FCO SLICE_69
ROUTE 1 0.000 R19C6C.FCO to R19C6D.FCI n10996
FCITOFCO_D --- 0.162 R19C6D.FCI to R19C6D.FCO SLICE_68
ROUTE 1 0.000 R19C6D.FCO to R19C7A.FCI n10997
FCITOFCO_D --- 0.162 R19C7A.FCI to R19C7A.FCO SLICE_67
ROUTE 1 0.000 R19C7A.FCO to R19C7B.FCI n10998
FCITOFCO_D --- 0.162 R19C7B.FCI to R19C7B.FCO SLICE_66
ROUTE 1 0.000 R19C7B.FCO to R19C7C.FCI n10999
FCITOFCO_D --- 0.162 R19C7C.FCI to R19C7C.FCO SLICE_65
ROUTE 1 0.000 R19C7C.FCO to R19C7D.FCI n11000
FCITOFCO_D --- 0.162 R19C7D.FCI to R19C7D.FCO SLICE_64
ROUTE 1 0.000 R19C7D.FCO to R19C8A.FCI n11001
FCITOFCO_D --- 0.162 R19C8A.FCI to R19C8A.FCO SLICE_63
ROUTE 1 0.000 R19C8A.FCO to R19C8B.FCI n11002
FCITOFCO_D --- 0.162 R19C8B.FCI to R19C8B.FCO SLICE_62
ROUTE 1 0.000 R19C8B.FCO to R19C8C.FCI n11003
FCITOFCO_D --- 0.162 R19C8C.FCI to R19C8C.FCO SLICE_61
ROUTE 1 0.000 R19C8C.FCO to R19C8D.FCI n11004
FCITOFCO_D --- 0.162 R19C8D.FCI to R19C8D.FCO SLICE_60
ROUTE 1 0.000 R19C8D.FCO to R19C9A.FCI n11005
FCITOFCO_D --- 0.162 R19C9A.FCI to R19C9A.FCO SLICE_59
ROUTE 1 0.000 R19C9A.FCO to R19C9B.FCI n11006
FCITOFCO_D --- 0.162 R19C9B.FCI to R19C9B.FCO SLICE_58
ROUTE 1 0.000 R19C9B.FCO to R19C9C.FCI n11007
FCITOFCO_D --- 0.162 R19C9C.FCI to R19C9C.FCO SLICE_57
ROUTE 1 0.000 R19C9C.FCO to R19C9D.FCI n11008
FCITOF1_DE --- 0.643 R19C9D.FCI to R19C9D.F1 SLICE_56
ROUTE 1 0.000 R19C9D.F1 to R19C9D.DI1 n2819 (to osc_clk)
--------
14.859 (57.0% logic, 43.0% route), 34 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2432:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.162 OSC.OSC to R21C8A.CLK osc_clk
--------
4.162 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R19C9D.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.708ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q phase_inc_carrGen_i0_i5 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i62 (to osc_clk +)
Delay: 14.821ns (60.2% logic, 39.8% route), 33 logic levels.
Constraint Details:
14.821ns physical path delay SLICE_84 to SLICE_55 exceeds
11.278ns delay constraint less
-0.001ns skew and
0.166ns DIN_SET requirement (totaling 11.113ns) by 3.708ns
Physical Path Details:
Data path SLICE_84 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R19C2D.CLK to R19C2D.Q1 SLICE_84 (from osc_clk)
ROUTE 4 1.426 R19C2D.Q1 to R18C4B.A0 phase_inc_carrGen_5
C0TOFCO_DE --- 1.023 R18C4B.A0 to R18C4B.FCO SLICE_131
ROUTE 1 0.000 R18C4B.FCO to R18C4C.FCI n10808
FCITOFCO_D --- 0.162 R18C4C.FCI to R18C4C.FCO SLICE_130
ROUTE 1 0.000 R18C4C.FCO to R18C4D.FCI n10809
FCITOFCO_D --- 0.162 R18C4D.FCI to R18C4D.FCO SLICE_129
ROUTE 1 0.000 R18C4D.FCO to R18C5A.FCI n10810
FCITOFCO_D --- 0.162 R18C5A.FCI to R18C5A.FCO SLICE_128
ROUTE 1 0.000 R18C5A.FCO to R18C5B.FCI n10811
FCITOFCO_D --- 0.162 R18C5B.FCI to R18C5B.FCO SLICE_127
ROUTE 1 0.000 R18C5B.FCO to R18C5C.FCI n10812
FCITOFCO_D --- 0.162 R18C5C.FCI to R18C5C.FCO SLICE_126
ROUTE 1 0.000 R18C5C.FCO to R18C5D.FCI n10813
FCITOFCO_D --- 0.162 R18C5D.FCI to R18C5D.FCO SLICE_125
ROUTE 1 0.000 R18C5D.FCO to R18C6A.FCI n10814
FCITOFCO_D --- 0.162 R18C6A.FCI to R18C6A.FCO SLICE_124
ROUTE 1 0.000 R18C6A.FCO to R18C6B.FCI n10815
FCITOFCO_D --- 0.162 R18C6B.FCI to R18C6B.FCO SLICE_123
ROUTE 1 0.000 R18C6B.FCO to R18C6C.FCI n10816
FCITOFCO_D --- 0.162 R18C6C.FCI to R18C6C.FCO SLICE_122
ROUTE 1 0.000 R18C6C.FCO to R18C6D.FCI n10817
FCITOFCO_D --- 0.162 R18C6D.FCI to R18C6D.FCO SLICE_121
ROUTE 1 0.000 R18C6D.FCO to R18C7A.FCI n10818
FCITOFCO_D --- 0.162 R18C7A.FCI to R18C7A.FCO SLICE_120
ROUTE 1 0.000 R18C7A.FCO to R18C7B.FCI n10819
FCITOFCO_D --- 0.162 R18C7B.FCI to R18C7B.FCO SLICE_119
ROUTE 1 0.000 R18C7B.FCO to R18C7C.FCI n10820
FCITOFCO_D --- 0.162 R18C7C.FCI to R18C7C.FCO SLICE_118
ROUTE 1 0.000 R18C7C.FCO to R18C7D.FCI n10821
FCITOFCO_D --- 0.162 R18C7D.FCI to R18C7D.FCO SLICE_117
ROUTE 1 0.000 R18C7D.FCO to R18C8A.FCI n10822
FCITOFCO_D --- 0.162 R18C8A.FCI to R18C8A.FCO SLICE_116
ROUTE 1 0.000 R18C8A.FCO to R18C8B.FCI n10823
FCITOF1_DE --- 0.643 R18C8B.FCI to R18C8B.F1 SLICE_115
ROUTE 1 1.278 R18C8B.F1 to R18C15A.C0 n1056
CTOF_DEL --- 0.495 R18C15A.C0 to R18C15A.F0 SLICE_2482
ROUTE 1 1.001 R18C15A.F0 to R19C15B.B0 n7813
CTOF_DEL --- 0.495 R19C15B.B0 to R19C15B.F0 SLICE_2394
ROUTE 1 2.188 R19C15B.F0 to R19C7A.C0 n2324
C0TOFCO_DE --- 1.023 R19C7A.C0 to R19C7A.FCO SLICE_67
ROUTE 1 0.000 R19C7A.FCO to R19C7B.FCI n10998
FCITOFCO_D --- 0.162 R19C7B.FCI to R19C7B.FCO SLICE_66
ROUTE 1 0.000 R19C7B.FCO to R19C7C.FCI n10999
FCITOFCO_D --- 0.162 R19C7C.FCI to R19C7C.FCO SLICE_65
ROUTE 1 0.000 R19C7C.FCO to R19C7D.FCI n11000
FCITOFCO_D --- 0.162 R19C7D.FCI to R19C7D.FCO SLICE_64
ROUTE 1 0.000 R19C7D.FCO to R19C8A.FCI n11001
FCITOFCO_D --- 0.162 R19C8A.FCI to R19C8A.FCO SLICE_63
ROUTE 1 0.000 R19C8A.FCO to R19C8B.FCI n11002
FCITOFCO_D --- 0.162 R19C8B.FCI to R19C8B.FCO SLICE_62
ROUTE 1 0.000 R19C8B.FCO to R19C8C.FCI n11003
FCITOFCO_D --- 0.162 R19C8C.FCI to R19C8C.FCO SLICE_61
ROUTE 1 0.000 R19C8C.FCO to R19C8D.FCI n11004
FCITOFCO_D --- 0.162 R19C8D.FCI to R19C8D.FCO SLICE_60
ROUTE 1 0.000 R19C8D.FCO to R19C9A.FCI n11005
FCITOFCO_D --- 0.162 R19C9A.FCI to R19C9A.FCO SLICE_59
ROUTE 1 0.000 R19C9A.FCO to R19C9B.FCI n11006
FCITOFCO_D --- 0.162 R19C9B.FCI to R19C9B.FCO SLICE_58
ROUTE 1 0.000 R19C9B.FCO to R19C9C.FCI n11007
FCITOFCO_D --- 0.162 R19C9C.FCI to R19C9C.FCO SLICE_57
ROUTE 1 0.000 R19C9C.FCO to R19C9D.FCI n11008
FCITOFCO_D --- 0.162 R19C9D.FCI to R19C9D.FCO SLICE_56
ROUTE 1 0.000 R19C9D.FCO to R19C10A.FCI n11009
FCITOF0_DE --- 0.585 R19C10A.FCI to R19C10A.F0 SLICE_55
ROUTE 1 0.000 R19C10A.F0 to R19C10A.DI0 n2818 (to osc_clk)
--------
14.821 (60.2% logic, 39.8% route), 33 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.198 OSC.OSC to R19C2D.CLK osc_clk
--------
4.198 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R19C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 3.689ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_DV_40 (from osc_clk +)
Destination: FF Data in phase_inc_carrGen_i0_i62 (to osc_clk +)
Delay: 14.838ns (59.1% logic, 40.9% route), 37 logic levels.
Constraint Details:
14.838ns physical path delay SLICE_2432 to SLICE_55 exceeds
11.278ns delay constraint less
-0.037ns skew and
0.166ns DIN_SET requirement (totaling 11.149ns) by 3.689ns
Physical Path Details:
Data path SLICE_2432 to SLICE_55:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R21C8A.CLK to R21C8A.Q0 SLICE_2432 (from osc_clk)
ROUTE 4 1.298 R21C8A.Q0 to R21C16C.C0 o_Rx_DV
CTOF_DEL --- 0.495 R21C16C.C0 to R21C16C.F0 SLICE_2476
ROUTE 4 1.160 R21C16C.F0 to R19C17D.C0 n8250
CTOF_DEL --- 0.495 R19C17D.C0 to R19C17D.F0 SLICE_2435
ROUTE 5 0.675 R19C17D.F0 to R19C15D.D1 n12533
CTOF_DEL --- 0.495 R19C15D.D1 to R19C15D.F1 SLICE_2389
ROUTE 49 1.264 R19C15D.F1 to R19C10C.D0 n2563
CTOF_DEL --- 0.495 R19C10C.D0 to R19C10C.F0 SLICE_2418
ROUTE 1 1.675 R19C10C.F0 to R19C2B.C1 n2361
C1TOFCO_DE --- 0.889 R19C2B.C1 to R19C2B.FCO SLICE_86
ROUTE 1 0.000 R19C2B.FCO to R19C2C.FCI n10979
FCITOFCO_D --- 0.162 R19C2C.FCI to R19C2C.FCO SLICE_85
ROUTE 1 0.000 R19C2C.FCO to R19C2D.FCI n10980
FCITOFCO_D --- 0.162 R19C2D.FCI to R19C2D.FCO SLICE_84
ROUTE 1 0.000 R19C2D.FCO to R19C3A.FCI n10981
FCITOFCO_D --- 0.162 R19C3A.FCI to R19C3A.FCO SLICE_83
ROUTE 1 0.000 R19C3A.FCO to R19C3B.FCI n10982
FCITOFCO_D --- 0.162 R19C3B.FCI to R19C3B.FCO SLICE_82
ROUTE 1 0.000 R19C3B.FCO to R19C3C.FCI n10983
FCITOFCO_D --- 0.162 R19C3C.FCI to R19C3C.FCO SLICE_81
ROUTE 1 0.000 R19C3C.FCO to R19C3D.FCI n10984
FCITOFCO_D --- 0.162 R19C3D.FCI to R19C3D.FCO SLICE_80
ROUTE 1 0.000 R19C3D.FCO to R19C4A.FCI n10985
FCITOFCO_D --- 0.162 R19C4A.FCI to R19C4A.FCO SLICE_79
ROUTE 1 0.000 R19C4A.FCO to R19C4B.FCI n10986
FCITOFCO_D --- 0.162 R19C4B.FCI to R19C4B.FCO SLICE_78
ROUTE 1 0.000 R19C4B.FCO to R19C4C.FCI n10987
FCITOFCO_D --- 0.162 R19C4C.FCI to R19C4C.FCO SLICE_77
ROUTE 1 0.000 R19C4C.FCO to R19C4D.FCI n10988
FCITOFCO_D --- 0.162 R19C4D.FCI to R19C4D.FCO SLICE_76
ROUTE 1 0.000 R19C4D.FCO to R19C5A.FCI n10989
FCITOFCO_D --- 0.162 R19C5A.FCI to R19C5A.FCO SLICE_75
ROUTE 1 0.000 R19C5A.FCO to R19C5B.FCI n10990
FCITOFCO_D --- 0.162 R19C5B.FCI to R19C5B.FCO SLICE_74
ROUTE 1 0.000 R19C5B.FCO to R19C5C.FCI n10991
FCITOFCO_D --- 0.162 R19C5C.FCI to R19C5C.FCO SLICE_73
ROUTE 1 0.000 R19C5C.FCO to R19C5D.FCI n10992
FCITOFCO_D --- 0.162 R19C5D.FCI to R19C5D.FCO SLICE_72
ROUTE 1 0.000 R19C5D.FCO to R19C6A.FCI n10993
FCITOFCO_D --- 0.162 R19C6A.FCI to R19C6A.FCO SLICE_71
ROUTE 1 0.000 R19C6A.FCO to R19C6B.FCI n10994
FCITOFCO_D --- 0.162 R19C6B.FCI to R19C6B.FCO SLICE_70
ROUTE 1 0.000 R19C6B.FCO to R19C6C.FCI n10995
FCITOFCO_D --- 0.162 R19C6C.FCI to R19C6C.FCO SLICE_69
ROUTE 1 0.000 R19C6C.FCO to R19C6D.FCI n10996
FCITOFCO_D --- 0.162 R19C6D.FCI to R19C6D.FCO SLICE_68
ROUTE 1 0.000 R19C6D.FCO to R19C7A.FCI n10997
FCITOFCO_D --- 0.162 R19C7A.FCI to R19C7A.FCO SLICE_67
ROUTE 1 0.000 R19C7A.FCO to R19C7B.FCI n10998
FCITOFCO_D --- 0.162 R19C7B.FCI to R19C7B.FCO SLICE_66
ROUTE 1 0.000 R19C7B.FCO to R19C7C.FCI n10999
FCITOFCO_D --- 0.162 R19C7C.FCI to R19C7C.FCO SLICE_65
ROUTE 1 0.000 R19C7C.FCO to R19C7D.FCI n11000
FCITOFCO_D --- 0.162 R19C7D.FCI to R19C7D.FCO SLICE_64
ROUTE 1 0.000 R19C7D.FCO to R19C8A.FCI n11001
FCITOFCO_D --- 0.162 R19C8A.FCI to R19C8A.FCO SLICE_63
ROUTE 1 0.000 R19C8A.FCO to R19C8B.FCI n11002
FCITOFCO_D --- 0.162 R19C8B.FCI to R19C8B.FCO SLICE_62
ROUTE 1 0.000 R19C8B.FCO to R19C8C.FCI n11003
FCITOFCO_D --- 0.162 R19C8C.FCI to R19C8C.FCO SLICE_61
ROUTE 1 0.000 R19C8C.FCO to R19C8D.FCI n11004
FCITOFCO_D --- 0.162 R19C8D.FCI to R19C8D.FCO SLICE_60
ROUTE 1 0.000 R19C8D.FCO to R19C9A.FCI n11005
FCITOFCO_D --- 0.162 R19C9A.FCI to R19C9A.FCO SLICE_59
ROUTE 1 0.000 R19C9A.FCO to R19C9B.FCI n11006
FCITOFCO_D --- 0.162 R19C9B.FCI to R19C9B.FCO SLICE_58
ROUTE 1 0.000 R19C9B.FCO to R19C9C.FCI n11007
FCITOFCO_D --- 0.162 R19C9C.FCI to R19C9C.FCO SLICE_57
ROUTE 1 0.000 R19C9C.FCO to R19C9D.FCI n11008
FCITOFCO_D --- 0.162 R19C9D.FCI to R19C9D.FCO SLICE_56
ROUTE 1 0.000 R19C9D.FCO to R19C10A.FCI n11009
FCITOF0_DE --- 0.585 R19C10A.FCI to R19C10A.F0 SLICE_55
ROUTE 1 0.000 R19C10A.F0 to R19C10A.DI0 n2818 (to osc_clk)
--------
14.838 (59.1% logic, 40.9% route), 37 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_2432:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.162 OSC.OSC to R21C8A.CLK osc_clk
--------
4.162 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_55:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R19C10A.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Warning: 66.007MHz is the maximum frequency for this preference.
================================================================================
Preference: CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET "osc_clk" ;
18 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.279ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOut
Data Path Delay: 10.522ns (37.1% logic, 62.9% route), 2 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
10.522ns delay PWM1/SLICE_6 to PWMOut (totaling 14.721ns) meets
20.000ns offset OSCH_inst to PWMOut by 5.279ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R12C25B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOut:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R12C25B.CLK to R12C25B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 6.622 R12C25B.Q1 to 43.PADDO PWMOutP4_c
DOPAD_DEL --- 3.448 43.PADDO to 43.PAD PWMOut
--------
10.522 (37.1% logic, 62.9% route), 2 logic levels.
Passed: The following path meets requirements by 5.772ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q o_Rx_Byte_i1 (from osc_clk +)
Destination: Port Pad MYLED[6]
Data Path Delay: 10.066ns (32.3% logic, 67.7% route), 2 logic levels.
Clock Path Delay: 4.162ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.162ns delay OSCH_inst to SLICE_2468 and
10.066ns delay SLICE_2468 to MYLED[6] (totaling 14.228ns) meets
20.000ns offset OSCH_inst to MYLED[6] by 5.772ns
Physical Path Details:
Clock path OSCH_inst to SLICE_2468:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.162 OSC.OSC to R21C11D.CLK osc_clk
--------
4.162 (0.0% logic, 100.0% route), 0 logic levels.
Data path SLICE_2468 to MYLED[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R21C11D.CLK to R21C11D.Q0 SLICE_2468 (from osc_clk)
ROUTE 11 6.817 R21C11D.Q0 to 106.PADDO MYLED_c_6
DOPAD_DEL --- 2.797 106.PADDO to 106.PAD MYLED[6]
--------
10.066 (32.3% logic, 67.7% route), 2 logic levels.
Passed: The following path meets requirements by 6.313ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ncoGen/phase_accum_i63 (from osc_clk +)
Destination: Port Pad sinGen
Data Path Delay: 9.525ns (46.1% logic, 53.9% route), 3 logic levels.
Clock Path Delay: 4.162ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.162ns delay OSCH_inst to ncoGen/SLICE_725 and
9.525ns delay ncoGen/SLICE_725 to sinGen (totaling 13.687ns) meets
20.000ns offset OSCH_inst to sinGen by 6.313ns
Physical Path Details:
Clock path OSCH_inst to ncoGen/SLICE_725:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.162 OSC.OSC to R21C25D.CLK osc_clk
--------
4.162 (0.0% logic, 100.0% route), 0 logic levels.
Data path ncoGen/SLICE_725 to sinGen:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R21C25D.CLK to R21C25D.Q1 ncoGen/SLICE_725 (from osc_clk)
ROUTE 3 4.144 R21C25D.Q1 to R2C9A.D0 phase_accum_63
CTOF_DEL --- 0.495 R2C9A.D0 to R2C9A.F0 ncoGen/SLICE_2511
ROUTE 1 0.986 R2C9A.F0 to 142.PADDO sinGen_c
DOPAD_DEL --- 3.448 142.PADDO to 142.PAD sinGen
--------
9.525 (46.1% logic, 53.9% route), 3 logic levels.
Passed: The following path meets requirements by 6.471ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutN1
Data Path Delay: 9.330ns (47.1% logic, 52.9% route), 3 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
9.330ns delay PWM1/SLICE_6 to PWMOutN1 (totaling 13.529ns) meets
20.000ns offset OSCH_inst to PWMOutN1 by 6.471ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R12C25B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutN1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R12C25B.CLK to R12C25B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 3.259 R12C25B.Q1 to R25C38B.C0 PWMOutP4_c
CTOF_DEL --- 0.495 R25C38B.C0 to R25C38B.F0 SLICE_2495
ROUTE 4 1.676 R25C38B.F0 to 65.PADDO PWMOutN4_c
DOPAD_DEL --- 3.448 65.PADDO to 65.PAD PWMOutN1
--------
9.330 (47.1% logic, 52.9% route), 3 logic levels.
Passed: The following path meets requirements by 6.471ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutN2
Data Path Delay: 9.330ns (47.1% logic, 52.9% route), 3 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
9.330ns delay PWM1/SLICE_6 to PWMOutN2 (totaling 13.529ns) meets
20.000ns offset OSCH_inst to PWMOutN2 by 6.471ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R12C25B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutN2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R12C25B.CLK to R12C25B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 3.259 R12C25B.Q1 to R25C38B.C0 PWMOutP4_c
CTOF_DEL --- 0.495 R25C38B.C0 to R25C38B.F0 SLICE_2495
ROUTE 4 1.676 R25C38B.F0 to 67.PADDO PWMOutN4_c
DOPAD_DEL --- 3.448 67.PADDO to 67.PAD PWMOutN2
--------
9.330 (47.1% logic, 52.9% route), 3 logic levels.
Passed: The following path meets requirements by 6.772ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutP2
Data Path Delay: 9.029ns (43.2% logic, 56.8% route), 2 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
9.029ns delay PWM1/SLICE_6 to PWMOutP2 (totaling 13.228ns) meets
20.000ns offset OSCH_inst to PWMOutP2 by 6.772ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R12C25B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutP2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R12C25B.CLK to R12C25B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 5.129 R12C25B.Q1 to 62.PADDO PWMOutP4_c
DOPAD_DEL --- 3.448 62.PADDO to 62.PAD PWMOutP2
--------
9.029 (43.2% logic, 56.8% route), 2 logic levels.
Passed: The following path meets requirements by 6.806ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutP1
Data Path Delay: 8.995ns (43.4% logic, 56.6% route), 2 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
8.995ns delay PWM1/SLICE_6 to PWMOutP1 (totaling 13.194ns) meets
20.000ns offset OSCH_inst to PWMOutP1 by 6.806ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R12C25B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutP1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R12C25B.CLK to R12C25B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 5.095 R12C25B.Q1 to 61.PADDO PWMOutP4_c
DOPAD_DEL --- 3.448 61.PADDO to 61.PAD PWMOutP1
--------
8.995 (43.4% logic, 56.6% route), 2 logic levels.
Passed: The following path meets requirements by 7.315ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutN3
Data Path Delay: 8.486ns (51.8% logic, 48.2% route), 3 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
8.486ns delay PWM1/SLICE_6 to PWMOutN3 (totaling 12.685ns) meets
20.000ns offset OSCH_inst to PWMOutN3 by 7.315ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R12C25B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutN3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R12C25B.CLK to R12C25B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 3.259 R12C25B.Q1 to R25C38B.C0 PWMOutP4_c
CTOF_DEL --- 0.495 R25C38B.C0 to R25C38B.F0 SLICE_2495
ROUTE 4 0.832 R25C38B.F0 to 70.PADDO PWMOutN4_c
DOPAD_DEL --- 3.448 70.PADDO to 70.PAD PWMOutN3
--------
8.486 (51.8% logic, 48.2% route), 3 logic levels.
Passed: The following path meets requirements by 7.315ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutN4
Data Path Delay: 8.486ns (51.8% logic, 48.2% route), 3 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to PWM1/SLICE_6 and
8.486ns delay PWM1/SLICE_6 to PWMOutN4 (totaling 12.685ns) meets
20.000ns offset OSCH_inst to PWMOutN4 by 7.315ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R12C25B.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutN4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R12C25B.CLK to R12C25B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 3.259 R12C25B.Q1 to R25C38B.C0 PWMOutP4_c
CTOF_DEL --- 0.495 R25C38B.C0 to R25C38B.F0 SLICE_2495
ROUTE 4 0.832 R25C38B.F0 to 71.PADDO PWMOutN4_c
DOPAD_DEL --- 3.448 71.PADDO to 71.PAD PWMOutN4
--------
8.486 (51.8% logic, 48.2% route), 3 logic levels.
Passed: The following path meets requirements by 7.638ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i10 (from osc_clk +)
Destination: Port Pad MYLED[4]
Data Path Delay: 8.163ns (39.8% logic, 60.2% route), 2 logic levels.
Clock Path Delay: 4.199ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
4.199ns delay OSCH_inst to CIC1Sin/SLICE_2222 and
8.163ns delay CIC1Sin/SLICE_2222 to MYLED[4] (totaling 12.362ns) meets
20.000ns offset OSCH_inst to MYLED[4] by 7.638ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2222:
Name Fanout Delay (ns) Site Resource
ROUTE 999 4.199 OSC.OSC to R9C21D.CLK osc_clk
--------
4.199 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2222 to MYLED[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R9C21D.CLK to R9C21D.Q0 CIC1Sin/SLICE_2222 (from osc_clk)
ROUTE 2 4.914 R9C21D.Q0 to 104.PADDO MYLED_c_4
DOPAD_DEL --- 2.797 104.PADDO to 104.PAD MYLED[4]
--------
8.163 (39.8% logic, 60.2% route), 2 logic levels.
Report: 14.721ns is the minimum offset for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "osc_clk" 88.670000 MHz ; | 88.670 MHz| 66.007 MHz| 35 *
| | |
CLOCK_TO_OUT ALLPORTS 20.000000 ns | | |
CLKNET "osc_clk" ; | 20.000 ns| 14.721 ns| 2
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
n10999 | 1| 3888| 94.92%
| | |
n11000 | 1| 3881| 94.75%
| | |
n11001 | 1| 3867| 94.41%
| | |
n11002 | 1| 3810| 93.02%
| | |
n10998 | 1| 3760| 91.80%
| | |
n11003 | 1| 3710| 90.58%
| | |
n11004 | 1| 3591| 87.67%
| | |
n10997 | 1| 3404| 83.11%
| | |
n10996 | 1| 3392| 82.81%
| | |
n10995 | 1| 3383| 82.59%
| | |
n10994 | 1| 3381| 82.54%
| | |
n11005 | 1| 3379| 82.50%
| | |
n10993 | 1| 3364| 82.13%
| | |
n10992 | 1| 3353| 81.86%
| | |
n10991 | 1| 3322| 81.10%
| | |
n10990 | 1| 3208| 78.32%
| | |
n10989 | 1| 3107| 75.85%
| | |
n11006 | 1| 3087| 75.37%
| | |
n10988 | 1| 2958| 72.22%
| | |
n10987 | 1| 2860| 69.82%
| | |
n10986 | 1| 2797| 68.29%
| | |
n11007 | 1| 2638| 64.40%
| | |
n10985 | 1| 2433| 59.40%
| | |
n10984 | 1| 2239| 54.66%
| | |
n11008 | 1| 2021| 49.34%
| | |
n8250 | 4| 2017| 49.24%
| | |
n10983 | 1| 1955| 47.73%
| | |
n10982 | 1| 1474| 35.99%
| | |
n12533 | 5| 1457| 35.57%
| | |
n10981 | 1| 1160| 28.32%
| | |
n11009 | 1| 1155| 28.20%
| | |
o_Rx_DV | 4| 695| 16.97%
| | |
n10810 | 1| 691| 16.87%
| | |
n13057 | 52| 667| 16.28%
| | |
n10809 | 1| 649| 15.84%
| | |
n2563 | 49| 635| 15.50%
| | |
n2817 | 1| 606| 14.79%
| | |
n10811 | 1| 585| 14.28%
| | |
n13064 | 44| 567| 13.84%
| | |
n10812 | 1| 555| 13.55%
| | |
n2818 | 1| 549| 13.40%
| | |
n10815 | 1| 527| 12.87%
| | |
n10814 | 1| 510| 12.45%
| | |
n10813 | 1| 499| 12.18%
| | |
n10808 | 1| 497| 12.13%
| | |
n10816 | 1| 483| 11.79%
| | |
o_Rx_Byte_6 | 6| 467| 11.40%
| | |
n2819 | 1| 458| 11.18%
| | |
n10819 | 1| 449| 10.96%
| | |
n10817 | 1| 448| 10.94%
| | |
n10818 | 1| 446| 10.89%
| | |
n10980 | 1| 444| 10.84%
| | |
n10820 | 1| 429| 10.47%
| | |
n10821 | 1| 429| 10.47%
| | |
n10822 | 1| 429| 10.47%
| | |
o_Rx_Byte_7 | 4| 429| 10.47%
| | |
o_Rx_Byte_5 | 4| 426| 10.40%
| | |
n10823 | 1| 415| 10.13%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 3 clocks:
Clock Domain: uart_rx1/UartClk[2] Source: uart_rx1/SLICE_12.Q1 Loads: 29
No transfer within this clock domain is found
Clock Domain: osc_clk Source: OSCH_inst.OSC Loads: 1369
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ;
Data transfers from:
Clock Domain: uart_rx1/UartClk[2] Source: uart_rx1/SLICE_12.Q1
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ; Transfers: 9
Clock Domain: CIC1_out_clkSin Source: CIC1Sin/SLICE_2199.Q0
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ; Transfers: 10
Clock Domain: CIC1_out_clkSin Source: CIC1Sin/SLICE_2199.Q0 Loads: 153
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 4096 Score: 10296979
Cumulative negative slack: 10296979
Constraints cover 1466856 paths, 1 nets, and 16495 connections (99.99% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) <IP_ADDRESS>6
Mon Apr 06 16:34:29 2020
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o FPGASDR_impl1.twr -gui -msgset C:/Users/user/lattice/1BitADCFPGASDR/promote.xml FPGASDR_impl1.ncd FPGASDR_impl1.prf
Design file: fpgasdr_impl1.ncd
Preference file: fpgasdr_impl1.prf
Device,speed: LCMXO2-7000HE,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "osc_clk" 88.670000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET "osc_clk" (0 errors) 18 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "osc_clk" 88.670000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.303ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/v_comb_66 (from osc_clk +)
Destination: FF Data in CIC1Sin/d_out_i0_i7 (to osc_clk +)
FF CIC1Sin/d_out_i0_i6
Delay: 0.279ns (47.7% logic, 52.3% route), 1 logic levels.
Constraint Details:
0.279ns physical path delay CIC1Sin/SLICE_2186 to CIC1Sin/SLICE_2220 meets
-0.024ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.024ns) by 0.303ns
Physical Path Details:
Data path CIC1Sin/SLICE_2186 to CIC1Sin/SLICE_2220:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C23B.CLK to R9C23B.Q0 CIC1Sin/SLICE_2186 (from osc_clk)
ROUTE 17 0.146 R9C23B.Q0 to R9C23D.CE CIC1Sin/v_comb (to osc_clk)
--------
0.279 (47.7% logic, 52.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Sin/SLICE_2186:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R9C23B.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Sin/SLICE_2220:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R9C23D.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Cos/v_comb_66 (from osc_clk +)
Destination: FF Data in CIC1Cos/d_out_i0_i9 (to osc_clk +)
FF CIC1Cos/d_out_i0_i8
Delay: 0.280ns (47.5% logic, 52.5% route), 1 logic levels.
Constraint Details:
0.280ns physical path delay CIC1Cos/SLICE_1935 to SLICE_2192 meets
-0.024ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.024ns) by 0.304ns
Physical Path Details:
Data path CIC1Cos/SLICE_1935 to SLICE_2192:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C25B.CLK to R9C25B.Q0 CIC1Cos/SLICE_1935 (from osc_clk)
ROUTE 15 0.147 R9C25B.Q0 to R9C25D.CE CIC1Cos/v_comb (to osc_clk)
--------
0.280 (47.5% logic, 52.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Cos/SLICE_1935:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R9C25B.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_2192:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R9C25D.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Cos/d6_i0_i33 (from osc_clk +)
Destination: FF Data in CIC1Cos/d_d6_i0_i33 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Cos/SLICE_1588 to CIC1Cos/SLICE_1724 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Cos/SLICE_1588 to CIC1Cos/SLICE_1724:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R22C39B.CLK to R22C39B.Q0 CIC1Cos/SLICE_1588 (from osc_clk)
ROUTE 2 0.154 R22C39B.Q0 to R22C39D.M0 CIC1Cos/d6_33 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Cos/SLICE_1588:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R22C39B.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1724:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R22C39D.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Mixer1/RFInR1_13 (from osc_clk +)
Destination: FF Data in Mixer1/RFInR_14 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay Mixer1/SLICE_2225 to Mixer1/SLICE_2225 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path Mixer1/SLICE_2225 to Mixer1/SLICE_2225:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C19A.CLK to R2C19A.Q1 Mixer1/SLICE_2225 (from osc_clk)
ROUTE 2 0.154 R2C19A.Q1 to R2C19A.M0 DiffOut_c (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to Mixer1/SLICE_2225:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R2C19A.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to Mixer1/SLICE_2225:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R2C19A.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Cos/d_tmp_i0_i3 (from osc_clk +)
Destination: FF Data in CIC1Cos/d_d_tmp_i0_i3 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R23C35A.CLK to R23C35A.Q1 CIC1Cos/SLICE_1893 (from osc_clk)
ROUTE 2 0.154 R23C35A.Q1 to R23C35D.M1 CIC1Cos/d_tmp_3 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Cos/SLICE_1893:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R23C35A.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1856:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R23C35D.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Cos/d_tmp_i0_i2 (from osc_clk +)
Destination: FF Data in CIC1Cos/d_d_tmp_i0_i2 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R23C35A.CLK to R23C35A.Q0 CIC1Cos/SLICE_1893 (from osc_clk)
ROUTE 2 0.154 R23C35A.Q0 to R23C35D.M0 CIC1Cos/d_tmp_2 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Cos/SLICE_1893:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R23C35A.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1856:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R23C35D.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Cos/d6_i0_i34 (from osc_clk +)
Destination: FF Data in CIC1Cos/d_d6_i0_i34 (to osc_clk +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay CIC1Cos/SLICE_1588 to CIC1Cos/SLICE_1724 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path CIC1Cos/SLICE_1588 to CIC1Cos/SLICE_1724:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R22C39B.CLK to R22C39B.Q1 CIC1Cos/SLICE_1588 (from osc_clk)
ROUTE 2 0.154 R22C39B.Q1 to R22C39D.M1 CIC1Cos/d6_34 (to osc_clk)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Cos/SLICE_1588:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R22C39B.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1724:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.425 OSC.OSC to R22C39D.CLK osc_clk
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.307ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Cos/d5_i67 (from osc_clk +)
Destination: FF Data in CIC1Cos/d_tmp_i0_i67 (to osc_clk +)
Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels.
Constraint Details:
0.288ns physical path delay CIC1Cos/SLICE_1108 to CIC1Cos/SLICE_1925 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.307ns
Physical Path Details:
Data path CIC1Cos/SLICE_1108 to CIC1Cos/SLICE_1925:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C31A.CLK to R15C31A.Q1 CIC1Cos/SLICE_1108 (from osc_clk)
ROUTE 3 0.155 R15C31A.Q1 to R15C31D.M1 CIC1Cos/d5_67 (to osc_clk)
--------
0.288 (46.2% logic, 53.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Cos/SLICE_1108:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R15C31A.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R15C31D.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.307ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Cos/d5_i66 (from osc_clk +)
Destination: FF Data in CIC1Cos/d_tmp_i0_i66 (to osc_clk +)
Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels.
Constraint Details:
0.288ns physical path delay CIC1Cos/SLICE_1108 to CIC1Cos/SLICE_1925 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.307ns
Physical Path Details:
Data path CIC1Cos/SLICE_1108 to CIC1Cos/SLICE_1925:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R15C31A.CLK to R15C31A.Q0 CIC1Cos/SLICE_1108 (from osc_clk)
ROUTE 3 0.155 R15C31A.Q0 to R15C31D.M0 CIC1Cos/d5_66 (to osc_clk)
--------
0.288 (46.2% logic, 53.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CIC1Cos/SLICE_1108:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R15C31A.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R15C31D.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.307ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SinCos1/FF_55 (from osc_clk +)
Destination: FF Data in SinCos1/FF_27 (to osc_clk +)
Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels.
Constraint Details:
0.288ns physical path delay SinCos1/SLICE_2275 to SinCos1/SLICE_2275 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.307ns
Physical Path Details:
Data path SinCos1/SLICE_2275 to SinCos1/SLICE_2275:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C4B.CLK to R9C4B.Q1 SinCos1/SLICE_2275 (from osc_clk)
ROUTE 3 0.155 R9C4B.Q1 to R9C4B.M0 SinCos1/mx_ctrl_r_1 (to osc_clk)
--------
0.288 (46.2% logic, 53.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SinCos1/SLICE_2275:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R9C4B.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SinCos1/SLICE_2275:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.443 OSC.OSC to R9C4B.CLK osc_clk
--------
1.443 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET "osc_clk" ;
18 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.857ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Mixer1/RFInR1_13 (from osc_clk +)
Destination: Port Pad DiffOut
Data Path Delay: 1.666ns (73.0% logic, 27.0% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to Mixer1/SLICE_2225 and
1.666ns delay Mixer1/SLICE_2225 to DiffOut (totaling 2.857ns) meets
0.000ns hold offset OSCH_inst to DiffOut by 2.857ns
Physical Path Details:
Clock path OSCH_inst to Mixer1/SLICE_2225:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R2C19A.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path Mixer1/SLICE_2225 to DiffOut:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C19A.CLK to R2C19A.Q1 Mixer1/SLICE_2225 (from osc_clk)
ROUTE 2 0.449 R2C19A.Q1 to 122.PADDO DiffOut_c
DOPAD_DEL --- 1.084 122.PADDO to 122.PAD DiffOut
--------
1.666 (73.0% logic, 27.0% route), 2 logic levels.
Passed: The following path meets requirements by 2.875ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i6 (from osc_clk +)
Destination: Port Pad MYLED[0]
Data Path Delay: 1.684ns (64.5% logic, 35.5% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to CIC1Sin/SLICE_2220 and
1.684ns delay CIC1Sin/SLICE_2220 to MYLED[0] (totaling 2.875ns) meets
0.000ns hold offset OSCH_inst to MYLED[0] by 2.875ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2220:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R9C23D.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2220 to MYLED[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C23D.CLK to R9C23D.Q0 CIC1Sin/SLICE_2220 (from osc_clk)
ROUTE 2 0.598 R9C23D.Q0 to 97.PADDO MYLED_c_0
DOPAD_DEL --- 0.953 97.PADDO to 97.PAD MYLED[0]
--------
1.684 (64.5% logic, 35.5% route), 2 logic levels.
Passed: The following path meets requirements by 3.016ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i11 (from osc_clk +)
Destination: Port Pad MYLED[5]
Data Path Delay: 1.825ns (59.5% logic, 40.5% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to CIC1Sin/SLICE_2223 and
1.825ns delay CIC1Sin/SLICE_2223 to MYLED[5] (totaling 3.016ns) meets
0.000ns hold offset OSCH_inst to MYLED[5] by 3.016ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2223:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R9C22D.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2223 to MYLED[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C22D.CLK to R9C22D.Q0 CIC1Sin/SLICE_2223 (from osc_clk)
ROUTE 2 0.739 R9C22D.Q0 to 105.PADDO MYLED_c_5
DOPAD_DEL --- 0.953 105.PADDO to 105.PAD MYLED[5]
--------
1.825 (59.5% logic, 40.5% route), 2 logic levels.
Passed: The following path meets requirements by 3.158ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i7 (from osc_clk +)
Destination: Port Pad MYLED[1]
Data Path Delay: 1.967ns (55.2% logic, 44.8% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to CIC1Sin/SLICE_2220 and
1.967ns delay CIC1Sin/SLICE_2220 to MYLED[1] (totaling 3.158ns) meets
0.000ns hold offset OSCH_inst to MYLED[1] by 3.158ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2220:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R9C23D.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2220 to MYLED[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C23D.CLK to R9C23D.Q1 CIC1Sin/SLICE_2220 (from osc_clk)
ROUTE 2 0.881 R9C23D.Q1 to 98.PADDO MYLED_c_1
DOPAD_DEL --- 0.953 98.PADDO to 98.PAD MYLED[1]
--------
1.967 (55.2% logic, 44.8% route), 2 logic levels.
Passed: The following path meets requirements by 3.261ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i9 (from osc_clk +)
Destination: Port Pad MYLED[3]
Data Path Delay: 2.070ns (52.5% logic, 47.5% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to CIC1Sin/SLICE_2221 and
2.070ns delay CIC1Sin/SLICE_2221 to MYLED[3] (totaling 3.261ns) meets
0.000ns hold offset OSCH_inst to MYLED[3] by 3.261ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2221:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R9C22B.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2221 to MYLED[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C22B.CLK to R9C22B.Q1 CIC1Sin/SLICE_2221 (from osc_clk)
ROUTE 2 0.984 R9C22B.Q1 to 100.PADDO MYLED_c_3
DOPAD_DEL --- 0.953 100.PADDO to 100.PAD MYLED[3]
--------
2.070 (52.5% logic, 47.5% route), 2 logic levels.
Passed: The following path meets requirements by 3.289ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CIC1Sin/d_out_i0_i8 (from osc_clk +)
Destination: Port Pad MYLED[2]
Data Path Delay: 2.098ns (51.8% logic, 48.2% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to CIC1Sin/SLICE_2221 and
2.098ns delay CIC1Sin/SLICE_2221 to MYLED[2] (totaling 3.289ns) meets
0.000ns hold offset OSCH_inst to MYLED[2] by 3.289ns
Physical Path Details:
Clock path OSCH_inst to CIC1Sin/SLICE_2221:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R9C22B.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path CIC1Sin/SLICE_2221 to MYLED[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C22B.CLK to R9C22B.Q0 CIC1Sin/SLICE_2221 (from osc_clk)
ROUTE 2 1.012 R9C22B.Q0 to 99.PADDO MYLED_c_2
DOPAD_DEL --- 0.953 99.PADDO to 99.PAD MYLED[2]
--------
2.098 (51.8% logic, 48.2% route), 2 logic levels.
Passed: The following path meets requirements by 3.495ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutP3
Data Path Delay: 2.304ns (52.8% logic, 47.2% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to PWM1/SLICE_6 and
2.304ns delay PWM1/SLICE_6 to PWMOutP3 (totaling 3.495ns) meets
0.000ns hold offset OSCH_inst to PWMOutP3 by 3.495ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R12C25B.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutP3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R12C25B.CLK to R12C25B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 1.087 R12C25B.Q1 to 68.PADDO PWMOutP4_c
DOPAD_DEL --- 1.084 68.PADDO to 68.PAD PWMOutP3
--------
2.304 (52.8% logic, 47.2% route), 2 logic levels.
Passed: The following path meets requirements by 3.495ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutP4
Data Path Delay: 2.304ns (52.8% logic, 47.2% route), 2 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to PWM1/SLICE_6 and
2.304ns delay PWM1/SLICE_6 to PWMOutP4 (totaling 3.495ns) meets
0.000ns hold offset OSCH_inst to PWMOutP4 by 3.495ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R12C25B.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutP4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R12C25B.CLK to R12C25B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 1.087 R12C25B.Q1 to 69.PADDO PWMOutP4_c
DOPAD_DEL --- 1.084 69.PADDO to 69.PAD PWMOutP4
--------
2.304 (52.8% logic, 47.2% route), 2 logic levels.
Passed: The following path meets requirements by 3.510ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutN3
Data Path Delay: 2.319ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to PWM1/SLICE_6 and
2.319ns delay PWM1/SLICE_6 to PWMOutN3 (totaling 3.510ns) meets
0.000ns hold offset OSCH_inst to PWMOutN3 by 3.510ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R12C25B.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutN3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R12C25B.CLK to R12C25B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 0.818 R12C25B.Q1 to R25C38B.C0 PWMOutP4_c
CTOF_DEL --- 0.101 R25C38B.C0 to R25C38B.F0 SLICE_2495
ROUTE 4 0.183 R25C38B.F0 to 70.PADDO PWMOutN4_c
DOPAD_DEL --- 1.084 70.PADDO to 70.PAD PWMOutN3
--------
2.319 (56.8% logic, 43.2% route), 3 logic levels.
Passed: The following path meets requirements by 3.510ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PWM1/PWMOut_15 (from osc_clk +)
Destination: Port Pad PWMOutN4
Data Path Delay: 2.319ns (56.8% logic, 43.2% route), 3 logic levels.
Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels.
Constraint Details:
1.191ns delay OSCH_inst to PWM1/SLICE_6 and
2.319ns delay PWM1/SLICE_6 to PWMOutN4 (totaling 3.510ns) meets
0.000ns hold offset OSCH_inst to PWMOutN4 by 3.510ns
Physical Path Details:
Clock path OSCH_inst to PWM1/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 999 1.191 OSC.OSC to R12C25B.CLK osc_clk
--------
1.191 (0.0% logic, 100.0% route), 0 logic levels.
Data path PWM1/SLICE_6 to PWMOutN4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R12C25B.CLK to R12C25B.Q1 PWM1/SLICE_6 (from osc_clk)
ROUTE 6 0.818 R12C25B.Q1 to R25C38B.C0 PWMOutP4_c
CTOF_DEL --- 0.101 R25C38B.C0 to R25C38B.F0 SLICE_2495
ROUTE 4 0.183 R25C38B.F0 to 71.PADDO PWMOutN4_c
DOPAD_DEL --- 1.084 71.PADDO to 71.PAD PWMOutN4
--------
2.319 (56.8% logic, 43.2% route), 3 logic levels.
Report: 2.857ns is the maximum offset for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "osc_clk" 88.670000 MHz ; | 0.000 ns| 0.303 ns| 1
| | |
CLOCK_TO_OUT ALLPORTS 20.000000 ns | | |
CLKNET "osc_clk" ; | 0.000 ns| 2.857 ns| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 3 clocks:
Clock Domain: uart_rx1/UartClk[2] Source: uart_rx1/SLICE_12.Q1 Loads: 29
No transfer within this clock domain is found
Clock Domain: osc_clk Source: OSCH_inst.OSC Loads: 1369
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ;
Data transfers from:
Clock Domain: uart_rx1/UartClk[2] Source: uart_rx1/SLICE_12.Q1
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ; Transfers: 9
Clock Domain: CIC1_out_clkSin Source: CIC1Sin/SLICE_2199.Q0
Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ; Transfers: 10
Clock Domain: CIC1_out_clkSin Source: CIC1Sin/SLICE_2199.Q0 Loads: 153
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1466856 paths, 1 nets, and 16495 connections (99.99% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 4096 (setup), 0 (hold)
Score: 10296979 (setup), 0 (hold)
Cumulative negative slack: 10296979 (10296979+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------


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Before Change
// Cast to the right dtype
batch = self.cast(batch)
// Second, wrap as variable
batch = type(batch)([Variable(_batch, requires_grad=requires_grad, volatile=volatile)
for _batch in batch])
return batch
def next_iteration(self):
self._iteration_count += 1
After Change
batch = self.cast(batch)
// Second, wrap as variable
variable_batch = []
for batch_num, _batch in enumerate(batch):
if thu.is_tensor(_batch):
variable_batch.append(Variable(batch, requires_grad=requires_grad,
volatile=volatile))
elif pyu.is_listlike(_batch):
variable_batch.append([Variable(__batch, requires_grad=requires_grad,
volatile=volatile)
for __batch in _batch])
else:
raise RuntimeError(f"Was Expecting batch at index {batch_num} to be either a "
f"tensor or a list of tensors. Got {type(_batch)} instead.")
batch = type(batch)(variable_batch)
return batch
def next_iteration(self):