| 1 = KEY comparison is busy. | ||
| [1] | KEYLOCK | KEY LOCK Flag |
| This bit is set to 1 if KEYMATCH (FMC_KEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection | ||
| This bit also can be set to 1 while | ||
| l CPU write 1 to KEYLOCK(FMC_KEYSTS[1]) or | ||
| l KEYFLAG(FMC_KEYSTS[4]) is 1 at power-on or reset or | ||
| l KEYENROM is programmed a non-0xFF value or | ||
| l Time-out event or | ||
| l FORBID(FMC_KEYSTS[3]) is 1 | ||
| 0 = KPROM and APROM (not include Data Flash) is not in write protection. | ||
| 1 = KPROM and APROM (not include Data Flash) is in write protection. | ||
| CONFIG write protect is depended on CFGFLAG | ||
| [2] | KEYMATCH | KEY Match Flag(Read Only) |
| This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched | ||
| This bit is also cleared to 0 while | ||
| l CPU writing 1 to KEYLOCK(FMC_KEYSTS[1]) or | ||
| l Time-out event or | ||
| l KPROM is erased or | ||
| l KEYENROM is programmed to a non-0xFF value. | ||
| l Chip is in Power-down mode. | ||
| 0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting. | ||
| 1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting. | ||
| [3] | FORBID | KEY Comparison Forbidden Flag(Read Only) |
| This bit is set to 1 whenKECNT(FMC_KECNT[4:0])is more than KEMAX (FMC_KECNT[12:8]) orKPCNT (FMC_KPCNT [2:0])is more than KPMAX (FMC_KPCNT [10:8]). | ||
| 0 = KEY comparison is not forbidden. | ||
| 1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger. | ||
| [4] | KEYFLAG | KEY Protection Enable Flag(Read Only) |
| This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset | ||
| This bit is cleared to 0 by hardware while KPROM is erased | ||
| This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value. | ||
| 0 = Security Key protection Disabled. | ||
| 1 = Security KeyprotectionEnabled. | ||
| [5] | CFGFLAG | CONFIG Write-protection Enable Flag(Read Only) |
| This bit is set while the KEYENROM [0] is 0 at power-on or reset | ||
| This bit is cleared to 0 by hardware while KPROM is erased | ||
| This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. | ||
| 0 = CONFIG write-protection Disabled. | ||
| 1 = CONFIG write-protection Enabled. |
| FMC_T::KEYTRG |
[0x005c] KEY Comparison Trigger Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | KEYGO | KEY Comparison Start Trigger (Write Protection) |
| Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished. | ||
| This trigger operation is valid while FORBID (FMC_KEYSTS [3]) is 0. | ||
| 0 = KEY comparison operation is finished. | ||
| 1 = KEY comparison is progressed. | ||
| Note:This bit is write-protected. Refer to the SYS_REGLCTL register. | ||
| [1] | TCEN | Time-out Counting Enable Bit (Write Protection) |
| 0 = Time-out counting Disabled. | ||
| 1 = Time-out counting Enabled if key is matched after key comparison finish. | ||
| 10 minutes is at least for time-out, and average is about 20 minutes. | ||
| Note:This bit is write-protected. Refer to the SYS_REGLCTL register. |
| FMC_T::KPCNT |
[0x0068] KEY-Unmatched Power-on Counting Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | KPCNT | Power-on Counter for Error Key Entry(Read Only). |
| KPCNT is the power-on counting for error key entry in Security Key protection. | ||
| KPCNT is cleared to 0 if key comparison is matched. | ||
| [11:8] | KPMAX | Power-on Maximum Number for Error Key Entry (Read Only). |
| KPMAX is the power-on maximum number for error key entry. | ||
| When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated. | ||
| KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting. | ||
| The FORBID(FMC_KEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX. |
| SYS_T::LDOCTL |
[0x0070] LDO Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [1] | FASTWK | Fast Wakeup Control Bit (Write Protect) |
| 0 = Fast Wakeup from Power-Down mode Disabled. | ||
| 1 = Fast Wakeup from Power-Down mode Enabled | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [3:2] | LDOLVL | LDO Output Voltage Select (Write Protect) |
| 00 = 1.2V. | ||
| 01 = 1.6V. | ||
| 10 = 1.8V. | ||
| 11 = 1.8V. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [4] | LPRMEN | Low-Power Run Mode Enable Bit (Write Protect) |
| 0 = Low-Power run mode Enabled. | ||
| 1 = Low-Power run mode Disabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [5] | FMCLVEN | Flash memory Low voltage Mode Enable Bit (Write Protect) |
| 0 = Flash memory low voltage(1.2V) mode Enabled. | ||
| 1 = Flash memory low voltage(1.2V) mode Disabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
| RTC_T::LEAPYEAR |
| UART_T::LINE |
[0x0008] UART Transfer Line Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | WLS | Word Length Selection |
| This field sets UART word length. | ||
| 00 = 5 bits. | ||
| 01 = 6 bits. | ||
| 10 = 7 bits. | ||
| 11 = 8 bits. | ||
| [2] | NSB | Number of STOP Bit |
| 0 = One STOP bit is generated in the transmitted data. | ||
| 1 = When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data | ||
| When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data. | ||
| [3] | PBE | Parity Bit Enable Bit |
| 0 = No parity bit generated Disabled. | ||
| 1 = Parity bit generated Enabled. | ||
| Note: Parity bit is generated on each outgoing character and is checked on each incoming data. | ||
| [4] | EPE | Even Parity Enable Bit |
| 0 = Odd number of logic 1's is transmitted and checked in each word. | ||
| 1 = Even number of logic 1's is transmitted and checked in each word. | ||
| Note: This bit has effect only when PBE (UART_TLCTL[3]) is set. | ||
| [5] | SPE | Stick Parity Enable Bit |
| 0 = Stick parity Disabled. | ||
| 1 = Stick parity Enabled. | ||
| Note: If PBE (UART_TLCTL[3]) and EPE (UART_TLCTL[4]) are logic 1, the parity bit is transmitted and checked as logic 0 | ||
| If PBE (UART_TLCTL[3]) is 1 and EPE (UART_TLCTL[4]) is 0 then the parity bit is transmitted and checked as 1. | ||
| [6] | BCB | Break Control Bit |
| 0 = Break Control Disabled. | ||
| 1 = Break Control Enabled. | ||
| Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0) | ||
| This bit acts only on TX line and has no effect on the transmitter logic. | ||
| [9:8] | RFITL | RX FIFO Interrupt Trigger Level |
| When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_IER [0]) enabled, and an interrupt will be generated). | ||
| 0000 = RX FIFO Interrupt Trigger Level is 1 byte. | ||
| 0001 = RX FIFO Interrupt Trigger Level is 4 bytes. | ||
| 0010 = RX FIFO Interrupt Trigger Level is 8 bytes. | ||
| 0011 = RX FIFO Interrupt Trigger Level is 14 bytes. | ||
| Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to 0. | ||
| [13:12] | RTSTRGLV | nRTS Trigger Level for Auto-flow Control Use |
| 00 = nRTS Trigger Level is 1 byte. | ||
| 01 = nRTS Trigger Level is 4 bytes. | ||
| 10 = nRTS Trigger Level is 8 bytes. | ||
| 11 = nRTS Trigger Level is 14 bytes. | ||
| Note: This field is used for auto nRTS flow control. |
| RTC_T::LXTCTL |
| RTC_T::LXTICTL |
[0x0108] X32KI Pin Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | OPMODE | IO Operation Mode |
| 00 = X32KI (PF.7) is input only mode, without pull-up resistor. | ||
| 01 = X32KI (PF.7) is output push pull mode. | ||
| 10 = X32KI (PF.7) is open drain mode. | ||
| 11 = X32KI (PF.7) is input only mode with internal pull up. | ||
| [2] | DOUT | IO Output Data |
| 0 = X32KI (PF.7) output low. | ||
| 1 = X32KI (PF.7) output high. | ||
| [3] | CTLSEL | IO Pin State Backup Selection |
| When low speed 32 kHz oscillator is disabled, X32KI (PF.7) pin can be used as GPIO function | ||
| User can program CTLSEL bit to decide X32KI (PF.7) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register. | ||
| 0 = X32KI (PF.7) pin I/O function is controlled by GPIO module | ||
| It becomes floating state when system power is turned off. | ||
| 1 = X32KI (PF.7) pin I/O function is controlled by VBAT power domain, X32KI (PF.7) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1 | ||
| I/O pin keeps the previous state after system power is turned off. | ||
| Note:CTLSEL (this bit) will automatically be set by hardware to 1 when system power is off and RTC Active Status = 1. |
| RTC_T::LXTOCTL |
[0x0104] X32KO Pin Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | OPMODE | GPF0 Operation Mode |
| 00 = X32KO (PF.6) is input only mode, without pull-up resistor. | ||
| 01 = X32KO (PF.6) is output push pull mode. | ||
| 10 = X32KO (PF.6) is open drain mode. | ||
| 11 = X32KO (PF.6) is input only mode with internal pull up. | ||
| [2] | DOUT | IO Output Data |
| 0 = X32KO (PF.6) output low. | ||
| 1 = X32KO (PF.6) output high. | ||
| [3] | CTLSEL | IO Pin State Backup Selection |
| When low speed 32 kHz oscillator is disabled, X32KO (PF.6) pin can be used as GPIO function | ||
| User can program CTLSEL bit to decide X32KO (PF.6) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register. | ||
| 0 = X32KO (PF.6) pin I/O function is controlled by GPIO module | ||
| It becomes floating when system power is turned off. | ||
| 1 = X32KO (PF.6) pin I/O function is controlled by VBAT power domain, X32KO (PF.6) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1 | ||
| I/O pin keeps the previous state after system power is turned off. | ||
| Note:CTLSEL (this bit) will automatically be set by hardware to 1 when system power is off and RTC Active Status = 1. |
| INT_T::MCU_IRQ |
[0x0084] MCU Interrupt Request Source Register
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | MCU_IRQ | MCU IRQ Source Bits |
| The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0 | ||
| There are two modes to generate interrupt to Cortex-M0, the normal mode. | ||
| The MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the Cortex-M0. | ||
| When the MCU_IRQ[n] is "0", setting MCU_IRQ[n] "1" will generate an interrupt to Cortex-M0 NVIC[n]. | ||
| When the MCU_IRQ[n] is "1" (means an interrupt is asserted), setting the MCU_bit[n] will clear the interrupt | ||
| Set MCU_IRQ[n] u201C0u201D: no any effect |
| SYS_T::MIRCTCTL |
[0x00a0] MIRC Trim Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | FREQSEL | Trim Frequency Selection |
| This field indicates the target frequency of 4 MHz internal medium speed RC oscillator (MIRC) auto trim. | ||
| During auto trim operation, if clock error detected with CESTOPEN (SYS_MIRCTCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. | ||
| 00 = Disable MIRC auto trim function. | ||
| 01 = Reserved. | ||
| 10 = Enable MIRC auto trim function and trim HIRC to 4 MHz. | ||
| 11 = Reserved. | ||
| Note: MIRC auto trim cannot work normally at power down mode | ||
| These bits must be cleared before entering power down mode. | ||
| [5:4] | LOOPSEL | Trim Calculation Loop Selection |
| This field defines that trim value calculation is based on how many 32.768 kHz clock. | ||
| 00 = Trim value calculation is based on average difference in 4 32.768 kHz clock. | ||
| 01 = Trim value calculation is based on average difference in 8 32.768 kHz clock. | ||
| 10 = Trim value calculation is based on average difference in 16 32.768 kHz clock. | ||
| 11 = Trim value calculation is based on average difference in 32 32.768 kHz clock. | ||
| Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. | ||
| [7:6] | RETRYCNT | Trim Value Update Limitation Count |
| This field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked. | ||
| Once the MIRC locked, the internal trim value update counter will be reset. | ||
| If the trim value update counter reached this limitation value and frequency of MIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00. | ||
| 00 = Trim retry count limitation is 64 loops. | ||
| 01 = Trim retry count limitation is 128 loops. | ||
| 10 = Trim retry count limitation is 256 loops. | ||
| 11 = Trim retry count limitation is 512 loops. | ||
| [8] | CESTOPEN | Clock Error Stop Enable Bit |
| This bit is used to control if stop the MIRC trim operation when 32.768 kHz clock error is detected. | ||
| If set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation was stopped | ||
| If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation is continuously. | ||
| 0 = The trim operation is keep going if clock is inaccuracy. | ||
| 1 = The trim operation is stopped if clock is inaccuracy. |
| SYS_T::MIRCTIEN |
[0x00a4] MIRC Trim Interrupt Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [1] | TFAILIEN | Trim Failure Interrupt Enable Bit |
| This bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL (SYS_MIRCTCTL[1:0]). | ||
| If this bit is high and TFAILIF (SYS_MIRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached. | ||
| 0 = Disable TFAILIF (SYS_MIRCTSTS[1]) status to trigger an interrupt to CPU. | ||
| 1 = Enable TFAILIF (SYS_MIRCTSTS[1]) status to trigger an interrupt to CPU. | ||
| [2] | CLKEIEN | Clock Error Interrupt Enable Bit |
| This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. | ||
| If this bit is set to1, and CLKERRIF (SYS_MIRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. | ||
| 0 = Disable CLKERRIF (SYS_MIRCTSTS[2]) status to trigger an interrupt to CPU. | ||
| 1 = Enable CLKERRIF (SYS_MIRCTSTS[2]) status to trigger an interrupt to CPU. |
| SYS_T::MIRCTISTS |
[0x00a8] MIRC Trim Interrupt Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FREQLOCK | MIRC Frequency Lock Status |
| This bit indicates the MIRC frequency is locked. | ||
| This is a status bit and doesn't trigger any interrupt. | ||
| 0 = The internal medium-speed oscillator frequency doesn't lock at 4 MHz yet. | ||
| 1 = The internal medium-speed oscillator frequency locked at 4 MHz. | ||
| [1] | TFAILIF | Trim Failure Interrupt Status |
| This bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency still doesn't be locked | ||
| Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00 by hardware automatically. | ||
| If this bit is set and TFAILIEN (SYS_MIRCTIEN[1]) is high, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached | ||
| Write 1 to clear this to 0. | ||
| 0 = Trim value update limitation count does not reach. | ||
| 1 = Trim value update limitation count reached and MIRC frequency still not locked. | ||
| [2] | CLKERRIF | Clock Error Interrupt Status |
| When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 4 MHz internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy | ||
| Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_MIRCTCTL[8]) is set to 1. | ||
| If this bit is set and CLKEIEN (SYS_MIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy | ||
| Write 1 to clear this to 0. | ||
| 0 = Clock frequency is accuracy. | ||
| 1 = Clock frequency is inaccuracy. |
| SYS_T::MISCCTL |
[0x0014] Miscellaneous Control Resister
| Bits | Field | Descriptions |
|---|---|---|
| [6] | POR33DIS | POR 33 Disable |
| 0 = POR33 is enable in normal operation. | ||
| 1 = POR33 is disable in normal operation. | ||
| [7] | POR18DIS | POR 18 Disable |
| 0 = POR18 is enable in normal operation. | ||
| 1 = POR18 is disable in normal operation. |
| RTC_T::MISCCTL |
| GPIO_T::MODE |
[0x0000] Pn I/O Mode Control
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | MODE0 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [3:2] | MODE1 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [5:4] | MODE2 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [7:6] | MODE3 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [9:8] | MODE4 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [11:10] | MODE5 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [13:12] | MODE6 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [15:14] | MODE7 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [17:16] | MODE8 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [19:18] | MODE9 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [21:20] | MODE10 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [23:22] | MODE11 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [25:24] | MODE12 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [27:26] | MODE13 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [29:28] | MODE14 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [31:30] | MODE15 | Port A-f I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Reserved. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
| UART_T::MODEM |
[0x001c] UART Modem Control Status Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RTSACTLV | nRTS Pin Active Level |
| This bit defines the active level state of nRTS pin output. | ||
| 0 =n RTS pin output is high level active. | ||
| 1 = nRTS pin output is low level active. (Default) | ||
| [1] | RTSSTS | nRTS Pin State (Read Only) |
| This bit mirror from nRTS pin output of voltage logic status. | ||
| 0 = nRTS pin output is low level voltage logic state. | ||
| 1 = nRTS pin output is high level voltage logic state. | ||
| [16] | CTSACTLV | nCTS Trigger Level |
| This bit defines the active level state of nCTS pin input. | ||
| 0 = nCTS pin input is high level active. | ||
| 1 = nCTS pin input is low level active. (Default) | ||
| [17] | CTSSTS | nCTS Pin Status (Read Only) |
| This bit mirror from nCTS pin input of voltage logic status. | ||
| 0 = nCTS pin input is low level voltage logic state. | ||
| 1 = nCTS pin input is high level voltage logic state. | ||
| Note: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected. | ||
| [18] | CTSDETF | Detect nCTS State Change Flag (Read Only) |
| This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_IER[3]). | ||
| 0 = nCTS input has not change state. | ||
| 1 = nCTS input has change state. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. |
| PWM_T::MSK |
| PWM_T::MSKEN |
[0x00b8] PWM0 Mask Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | MSKENn | PWM0 Mask Enable Bits |
| Each bit n controls the corresponding PWM0 channel n. | ||
| The PWM0 output signal will be masked when this bit is enabled | ||
| The corresponding PWM0 channel n will output MSKDATn (PWM0_MSK[5:0]) data. | ||
| 0 = PWM0 output signal is non-masked. | ||
| 1 = PWM0 output signal is masked and output MSKDATn data. |
| INT_T::NMI_SEL |
| PWM_T::PBUF0 |
| PWM_T::PBUF2 |
| PWM_T::PBUF4 |
| SYS_T::PDID |
[0x0000] Part Device Identification Number Register
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | PDID | Part Device Identification Number (Read Only) |
| This register reflects device part number code | ||
| Software can read this register to identify which device is used. |
| ADC_T::PDMA |
| SPI_T::PDMACTL |
[0x0038] SPI PDMA Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TXPDMAEN | Transmit PDMA Enable Bit |
| 0 = Transmit PDMA function Disabled. | ||
| 1 = Transmit PDMA function Enabled. | ||
| Refer to PDMA section for more detail information. | ||
| SPI_CTL Note: | ||
| 1 | ||
| Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode. | ||
| 2 | ||
| If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period. | ||
| Hardware will clear this bit to 0 automatically after PDMA transfer done. | ||
| [1] | RXPDMAEN | Receiving PDMA Enable Bit |
| 0 = Receiver PDMA function Disabled. | ||
| 1 = Receiver PDMA function Enabled. | ||
| Refer to PDMA section for more detail information. | ||
| Note: | ||
| Hardware will clear this bit to 0 automatically after PDMA transfer done. | ||
| In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock | ||
| [2] | PDMARST | PDMA Reset |
| It is used to reset the SPI PDMA function into default state. | ||
| 0 = After reset PDMA function or in normal operation. | ||
| 1 = Reset PDMA function. | ||
| Note: it is auto cleared to 0 after the reset function has done. |
| PWM_T::PERIOD |
[0x0030] PWM0 Period Register 0,2,4
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PERIOD | PWM0 Period Register |
| Up-Count mode: In this mode, PWM0 counter counts from 0 to PERIOD, and restarts from 0. | ||
| Down-Count mode: In this mode, PWM0 counter counts from PERIOD to 0, and restarts from PERIOD. | ||
| PWM0 period time = (PERIOD+1) * PWM0_CLK period. | ||
| Up-Down-Count mode: In this mode, PWM0 counter counts from 0 to PERIOD, then decrements to 0 and repeats again. | ||
| PWM0 period time = 2 * PERIOD * PWM0_CLK period. |
| GPIO_T::PIN |
[0x0010] Pn Pin Value
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PIN0 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [1] | PIN1 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [2] | PIN2 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [3] | PIN3 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [4] | PIN4 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [5] | PIN5 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [6] | PIN6 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [7] | PIN7 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [8] | PIN8 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [9] | PIN9 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [10] | PIN10 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [11] | PIN11 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [12] | PIN12 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [13] | PIN13 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [14] | PIN14 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [15] | PIN15 | Port A-f Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
| SC_T::PINCTL |
[0x0024] SC Pin Control State Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PWREN | SC_PWREN Pin Signal |
| Software can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level. | ||
| Write this field to drive SC_PWR pin | ||
| Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level. | ||
| Read this field to get SC_PWR pin status. | ||
| 0 = SC_PWR pin status is low. | ||
| 1 = SC_PWR pin status is high. | ||
| Note: When operating at hardware activation, warm reset or deactivation mode, this bit will be changed automatically | ||
| Thus,do not fill in this field when operating in these modes. | ||
| [1] | SCRST | SC_RST Pin Signal |
| This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit. | ||
| Write this field to drive SC_RST pin. | ||
| 0 = Drive SC_RST pin to low. | ||
| 1 = Drive SC_RST pin to high. | ||
| Read this field to get SC_RST pin status. | ||
| 0 = SC_RST pin status is low. | ||
| 1 = SC_RST pin status is high. | ||
| Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically | ||
| Thus,do not fill in this field when operating in these modes. | ||
| [2] | CREMOVE | Card Detect Removal Status of SC_CD Pin (Read Only) |
| This bit is set whenever card has been removal. | ||
| 0 = No effect. | ||
| 1 = Card removed. | ||
| Note1: This bit is read only, but it can be cleared by writing u201C1u201D to it. | ||
| Note2: Card detect engine will start after SCEN (SC_CTL[0])set. | ||
| [3] | CINSERT | Card Detect Insert Status of SC_CD Pin (Read Only) |
| This bit is set whenever card has been inserted. | ||
| 0 = No effect. | ||
| 1 = Card insert. | ||
| Note1: This bit is read only, but it can be cleared by writing u201C1u201D to it. | ||
| Note2: The card detect engine will start after SCEN (SC_CTL[0]) set. | ||
| [4] | CDPINSTS | Card Detect Status of SC_CD Pin Status (Read Only) |
| This bit is the pin status flag of SC_CD | ||
| 0 = The SC_CD pin state at low. | ||
| 1 = The SC_CD pin state at high. | ||
| [6] | CLKKEEP | SC Clock Enable Bit |
| 0 = SC clock generation Disabled. | ||
| 1 = SC clock always keeps free running. | ||
| Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically | ||
| Thus,do not fill in this field when operating in these modes. | ||
| [7] | ADACEN | Auto Deactivation When Card Removal |
| 0 = Auto deactivation Disabled when hardware detected the card removal. | ||
| 1 = Auto deactivation Enabled when hardware detected the card removal. | ||
| Note: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set) | ||
| If this process completes, hardware will generate an interrupt INITIF to CPU. | ||
| [9] | SCDOUT | SC Data Output Pin |
| This bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit. | ||
| 0 = Drive SCDATOUT pin to low. | ||
| 1 = Drive SCDATOUT pin to high. | ||
| Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically | ||
| Thus,do not fill in this field when SC is in these modes. | ||
| [10] | CDLV | Card Detect Level |
| 0 = When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected. | ||
| 1 = When hardware detects the card detect pin from low to high, it indicates a card is detected. | ||
| Note: Software must select card detect level before activate Smart Card. | ||
| [11] | PWRINV | SC_POW Pin Inverse |
| This bit is used for inverse the SC_POW pin. | ||
| There are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]) | ||
| PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection. | ||
| 00 = SC_POW_ Pin is 0. | ||
| 01 = SC_POW _Pin is 1. | ||
| 10 = SC_POW _Pin is 1. | ||
| 11 = SC_POW_ Pin is 0. | ||
| Note:Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]). | ||
| [16] | DATSTS | SC Data Input Pin Status (Read Only) |
| This bit is the pin status of SC_DAT | ||
| 0 = The SC_DAT pin is low. | ||
| 1 = The SC_DAT pin is high. | ||
| [30] | SYNC | SYNC Flag Indicator(Read Only) |
| Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register. | ||
| 0 = Synchronizing is completion, user can write new data to SC_PINCTL register. | ||
| 1 = Last value is synchronizing. |
| CLK_T::PLLCTL |
[0x0024] PLL Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | PLLMLP | PLL Multiple |
| 000000: Reserved | ||
| 000001: X1 | ||
| 000010: X2 | ||
| 000011: X3 | ||
| 000100: X4 | ||
| ... | ||
| 010000:X16 | ||
| ... | ||
| 100000: X32 | ||
| 100100: X36 | ||
| 0thers: Reserved | ||
| PLL output frequency: PLL input frequency * PLLMLP. | ||
| PLL output frequency range: 16MHz ~ 36MHz | ||
| [13:8] | INDIV | PLL Input Source Divider |
| The PLL input clock frequency = (PLL Clock Source frequency) / (INDIV + 1). | ||
| PLL input clock frequency range: 0.8MHz ~ 2MHz | ||
| [15:14] | STBTSEL | PLL Stable Time Selection |
| 00 = 100 cycle time of input clock source. | ||
| 01 = 120 cycle time of input clock source. | ||
| 10 = 180 cycle time of input clock source. | ||
| 11 = 240 cycle time of input clock source. | ||
| [16] | PD | Power-down Mode |
| If set the PDEN bit 1 in CLK_PWRCTL register, the PLL will enter Power-down mode too | ||
| 0 = PLL is in normal mode. | ||
| 1 = PLL is in power-down mode (default). | ||
| [18:17] | PLLSRC | PLL Source Clock Select |
| 00 = PLL source clock from HXT. | ||
| 01 = PLL source clock from HIRC0 or HIRC1. | ||
| 10 = PLL source clock from MIRC | ||
| 11 = reserved. |
| PWM_T::POEN |
| PWM_T::POLCTL |
[0x00d4] PWM0 Pin Polar Inverse Register
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | PINVn | PWM0 PIN Polar Inverse Control |
| The register controls polarity state of PWM0 output | ||
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = PWM0 output polar inverse Disabled. | ||
| 1 = PWM0 output polar inverse Enabled. |
| SYS_T::PORCTL |
[0x0060] Power-On-Reset Controller Register
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | POROFF | Power-on Reset Enable Bit (Write Protect) |
| When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again | ||
| User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. | ||
| The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: | ||
| nRESET, Watchdog, BOD reset, ICE reset command and the software-chip reset function. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
| TIMER_T::PRECNT |
[0x0004] Timer Pre-Scale Counter Register
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | PSC | Prescale Counter |
| Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter | ||
| If this field is 0 (PSC = 0), then there is no scaling. | ||
| Note: If the PSC value is changed, CNT (TIMERx_CNT) is reset to 0 and prescale counter is reloaded. |
| GPIO_T::PUEN |
[0x0024] Pn Pull-Up Enable Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PUEN0 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [1] | PUEN1 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [2] | PUEN2 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [3] | PUEN3 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [4] | PUEN4 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [5] | PUEN5 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [6] | PUEN6 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [7] | PUEN7 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [8] | PUEN8 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [9] | PUEN9 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [10] | PUEN10 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [11] | PUEN11 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [12] | PUEN12 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [13] | PUEN13 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [14] | PUEN14 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [15] | PUEN15 | Port A-f Pin[N] Pull-up Enable Bit |
| Read : | ||
| 0 = Px.n internal pull-up resistor Disabled. | ||
| 1 = Px.n internal pull-up resistor Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
| ADC_T::PWD |
[0x0064] A/D Power Management Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PWUPRDY | ADC Power-up Sequence Completed and Ready for Conversion |
| 0 = ADC is not ready for conversion, it may be in power saving state or in the progress of power up. | ||
| 1 = ADC is ready for conversion. | ||
| [1] | PWDCALEN | Power Up Calibration Function Enable Bit |
| 0 = Power up without calibration. | ||
| 1 = Power up with calibration. | ||
| Note: This bit works together with CALSEL (ADC_CALCTL[3]), see the following | ||
| {PWDCALEN,CALFBSEL} Description: | ||
| PWDCALEN is 0 and CALFBSEL is 0: No need to calibrate. | ||
| PWDCALEN is 0 and CALFBSEL is 1: No need to calibrate. | ||
| PWDCALEN is 1 and CALFBSEL is 0: Load calibration word when power up. | ||
| PWDCALEN is 1 and CALFBSEL is 1: Calibrate when power up. | ||
| [3:2] | PWDMOD | ADC Power Saving Mode |
| Set this bit fields to select ADC power saving mode. | ||
| 00 = Reserved. | ||
| 01 = ADC Power-down mode. | ||
| 10 = ADC Standby mode. | ||
| 11 = Reserved. | ||
| Note1: Different power saving mode has different power down/up sequence | ||
| To avoid ADC powering up with wrong sequence, user must keep PWMOD (ADC_PWD[3:2]) consistent each time in power down and power up. | ||
| Note2: While the ADC is powered up from power saving mode (set to 00b/01b/11b) without calibration, the PWDCALEN(ADC_PWD[1]) is set to 0, and the calibration value will be reset. |
| CLK_T::PWRCTL |
[0x0000] System Power-down Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXTEN | HXT Enable Bit (Write Protect) |
| 0 = 4~32 MHz external high speed crystal (HXT) Disabled. | ||
| 1 = 4~32 MHz external high speed crystal (HXT) Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [1] | LXTEN | LXT Enable Bit (Write Protect) |
| 0 = 32.768 kHz external low speed crystal (LXT) Disabled. | ||
| 1 = 32.768 kHz external low speed crystal (LXT) Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [2] | HIRC0EN | HIRC0 Enable Bit (Write Protect) |
| 0 = 12~16 MHz internal high speed RC oscillator (HIRC0) Disabled. | ||
| 1 = 12~16 MHz internal high speed RC oscillator (HIRC0) Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [3] | LIRCEN | LIRC Enable Bit (Write Protect) |
| 0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. | ||
| 1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [4] | PDWKDLY | Enable the Wake-up Delay Counter (Write Protect) |
| When the chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait system clock stable when chip works at 4~32 MHz external high speed crystal oscillator (HXT). | ||
| 0 = Clock cycles delay Disabled. | ||
| 1 = Clock cycles delay Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [5] | PDWKIEN | Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect) |
| 0 = Power-down mode wake-up interrupt Disabled. | ||
| 1 = Power-down mode wake-up interrupt Enabled. | ||
| Note1: The interrupt (EINT0~1, GPIO,, UART0~1, WDT, ACMP01, BOD, RTC, TMR0~3, I2C0~1 or SPI0 ~3 )will occur when PDWKIEN are high. | ||
| Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [6] | PDEN | System Power-Down Enable (Write Protect) |
| When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit. | ||
| (a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set | ||
| (default) | ||
| (b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. | ||
| When chip wakes up from Power-down mode, this bit is auto cleared | ||
| Users need to set this bit again for next Power-down. | ||
| In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. | ||
| In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection | ||
| The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. | ||
| 0 = Chip operating normally or chip in idle mode because of WFI command. | ||
| 1 = Chip enters Power-down mode instant or wait CPU sleep command WFI. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [8] | HXTSLTYP | HXT Mode Selection (Write Protect) |
| 0 = High frequency crystal loop back path Disabled. It is used for external oscillator. | ||
| 1 = High frequency crystal loop back path Enabled. It is used for external crystal. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [12:10] | HXTGAIN | HXT Gain Control Bit (Write Protect) |
| Gain control is used to enlarge the gain of crystal to make sure crystal wok normally | ||
| If gain control is enabled, crystal will consume more power than gain control off. | ||
| 000= HXT frequency is lower than from 4 MHz. | ||
| 001 = HXT frequency is from 4 MHz to 8 MHz. | ||
| 010 = HXT frequency is from 8 MHz to 12 MHz. | ||
| 011= HXT frequency is from 12 MHz to 16 MHz. | ||
| 100 = HXT frequency is from 16 MHz to 24 MHz. | ||
| 101 = HXT frequency is from 24 MHz to 32 MHz. | ||
| 110 = HXT frequency is from 32 MHz to 36 MHz. | ||
| 111 = HXT frequency is higher than 36 MHz. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [13] | HIRC0FSEL | HIRC0 Output Frequency Select Bit |
| 0 = HIRC0 will output 12MHz clock. | ||
| 1 = HIRC0 will output 16MHz Clock. | ||
| [14] | HIRC0FSTOP | HIRC0 Stop Output When Frequency Changes (Write Protect) |
| 0 = HIRC0 will continue to output when HIRC frequency changes. | ||
| 1 = HIRC0 will suppress to output during first 16 clocks when HIRC frequency change. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [24] | HIRC1EN | HIRC1 Enable Bit (Write Protect) |
| 0 = 36 MHz internal high speed RC oscillator (HIRC1) Disabled. | ||
| 1 = 36 MHz internal high speed RC oscillator (HIRC1) Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [25] | MIRCEN | MIRC Enable Bit (Write Protect) |
| 0 = 4 MHz internal medium speed RC oscillator (MIRC) Disabled. | ||
| 1 = 4 MHz internal medium speed RC oscillator (MIRC) Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
| PWM_T::RCAPDAT0 |
| PWM_T::RCAPDAT1 |
| PWM_T::RCAPDAT2 |
| PWM_T::RCAPDAT3 |
| PWM_T::RCAPDAT4 |
| PWM_T::RCAPDAT5 |
| SYS_T::RCCFCTL |
[0x0028] RC Clock Filter Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HIRC0FEN | HIRC0 Clock Filter Enable Bit |
| This bit is used to enable/disable HIRC0 clock filter function. | ||
| 0 = HIRC0 clock filter function Disabled. | ||
| 1 = HIRC0 clock filter function Enabled (default). | ||
| [1] | HIRC1FEN | HIRC1 Clock Filter Enable Bit |
| This bit is used to enable/disable HIRC1 clock filter function. | ||
| 0 = HIRC1 clock filter function Disabled. | ||
| 1 = HIRC1 clock filter function Enabled (default). | ||
| [2] | MRCFEN | MRC Clock Filter Enable Bit |
| This bit is used to enable/disable MRC clock filter function. | ||
| 0 = 4MHz MRC clock filter function Disabled. | ||
| 1 = 4MHz MRC clock filter function Enabled (default). |
| SYS_T::REGLCTL |
[0x0100] Register Lock Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | REGLCTL | Register Lock Control Code (Write Only) |
| Some registers have write-protection function | ||
| Writing these registers have to disable the protected function by writing the sequence value 59h, 16h, 88h to this field | ||
| After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. | ||
| Register Lock Control Disable Index (Read Only) | ||
| 0 = Write-protection Enabled for writing protected registers | ||
| Any write to the protected register is ignored. | ||
| 1 = Write-protection Disabled for writing protected registers. |
| DMA_GCR_T::REQSEL0 |
[0x0004] PDMA Request Source Select Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [12:8] | REQSRC1 | Channel 1 Request Source Selection |
| This filed defines which peripheral is connected to PDMA channel 1 | ||
| User can configure the peripheral by setting CH1_SEL. | ||
| 00000 = Connect to SPI0_TX. | ||
| 00001 = Connect to SPI1_TX. | ||
| 00010 = Connect to UART0_TX. | ||
| 00011 = Connect to UART1_TX. | ||
| 00100 = Reserved. | ||
| 00101 = Connect to SPI3_TX. | ||
| 00110 = Reserved. | ||
| 00111 = Reserved. | ||
| 01000 = Connect to SPI2_TX. | ||
| 01001 = Connect to TMR0. | ||
| 01010 = Connect to TMR1. | ||
| 01011 = Connect to TMR2. | ||
| 01100 = Connect to TMR3. | ||
| 10000 = Connect to SPI0_RX. | ||
| 10001 = Connect to SPI1_RX. | ||
| 10010 = Connect to UART0_RX. | ||
| 10011 = Connect to UART1_RX. | ||
| 10100 = Reserved. | ||
| 10101 = Connect to SPI3_RX. | ||
| 10110 = Connect to ADC. | ||
| 10111 = Reserved. | ||
| 11000 = Connect to SPI2_RX. | ||
| 11001 = Reserved. | ||
| 11010 = Reserved. | ||
| 11011 = Reserved. | ||
| 11100 = Reserved. | ||
| Others = Disable to connected any peripheral. | ||
| [20:16] | REQSRC2 | Channel 2 Request Source Selection |
| This filed defines which peripheral is connected to PDMA channel 2 | ||
| User can configure the peripheral setting by REQSRC2. | ||
| Note: The channel configuration is the same as REQSRC1 field | ||
| Please refer to the explanation of REQSRC1. | ||
| [28:24] | REQSRC3 | Channel 3 Request Source Selection |
| This filed defines which peripheral is connected to PDMA channel 3 | ||
| User can configure the peripheral setting by REQSRC3. | ||
| Note: The channel configuration is the same as REQSRC1 field | ||
| Please refer to the explanation of REQSRC1. |
| DMA_GCR_T::REQSEL1 |
[0x0008] PDMA Request Source Select Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [4:0] | REQSRC4 | Channel 4 Request Source Selection |
| This filed defines which peripheral is connected to PDMA channel 4 | ||
| User can configure the peripheral setting by REQSRC4. | ||
| Note: The channel configuration is the same as REQSRC1 field | ||
| Please refer to the explanation of REQSRC1. |
| WWDT_T::RLDCNT |
[0x0000] Window Watchdog Timer Reload Counter Register
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | WWDT_RLD | Window Watchdog Timer Reload Counter Register |
| Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. | ||
| Note: This register can only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal. |
| SYS_T::RPDBCLK |
[0x0120] Reset Pin Debounce Clock Selection Register
| Bits | Field | Descriptions |
|---|---|---|
| [6] | RSTPDBCLK | Reset Pin Debounce Clock Selection Bit |
| Before switch clock, both clock sources must be enabled. | ||
| 0 = MIRC is selected as reset pin debounce clock. | ||
| 1 = HIRC0 is selected as reset pin debounce clock.(default) |
| SYS_T::RSTSTS |
[0x0004] System Reset Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PORF | POR Reset Flag |
| The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. | ||
| 0 = No reset from POR or CHIPRST. | ||
| 1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [1] | PINRF | NRESET Pin Reset Flag |
| The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source. | ||
| 0 = No reset from nRESET pin. | ||
| 1 = Pin nRESET had issued the reset signal to reset the system. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [2] | WDTRF | WDT Reset Flag |
| The WDT reset flag is set by the Reset Signal from the Watchdog Timer to indicate the previous reset source. | ||
| 0 = No reset from watchdog timer or window watchdog timer. | ||
| 1 = The watchdog timer had issued the reset signal to reset the system. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [3] | LVRF | LVR Reset Flag |
| The LVR reset flag is set by the Reset Signal from the Low-Voltage Reset controller to indicate the previous reset source. | ||
| 0 = No reset from LVR. | ||
| 1 = The LVR had issued the reset signal to reset the system. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [4] | BODRF | BOD Reset Flag |
| The BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source. | ||
| 0 = No reset from BOD. | ||
| 1 = The BOD had issued the reset signal to reset the system. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [5] | SYSRF | System Reset Flag |
| The system reset flag is set by the Reset Signal from the Cortex-M0 Core to indicate the previous reset source. | ||
| 0 = No reset from Cortex-M0. | ||
| 1 = The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [7] | CPURF | CPU Reset Flag |
| The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC). | ||
| 0 = No reset from CPU. | ||
| 1 = The Cortex-M0 Core and FMC are reset by software setting CPURST to 1. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [8] | LOCKRF | Lockup Reset Flag |
| 0 = No reset from Cortex-M0. | ||
| 1 = The Cortex-M0 had issued the reset signal to reset the system by Cortex-M0 lockup event. |
| RTC_T::RWEN |
[0x0004] RTC Access Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | RWEN | RTC Register Access Enable Password (Write Only) |
| Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock. | ||
| Writing other value will clear RWENF. | ||
| [16] | RWENF | RTC Register Access Enable Flag (Read Only) |
| 0 = RTC register read/write Disabled. | ||
| 1 = RTC register read/write Enabled. | ||
| This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock . | ||
| Note: RWENF will be mask to 0 during RTCBUSY = 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also. | ||
| [24] | RTCBUSY | RTC Write Busy Flag |
| 0: RTC write access enable | ||
| 1: RTC write access disable , RTC under Busy Status. | ||
| Note: BUSY By Exceed RTC IP Processing Write Counter Capacity ( 6 counts Per 1120 PCLK cycles) . |
| SPI_T::RX0 |
[0x0010] SPI Receive Data FIFO Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | RX | Receive Data Register (Read Only) |
| The received data can be read on it | ||
| If the FIFO bit is set as 1, the user also checks the RXEMPTY, SPI_STATUS[0], to check if there is any more received data or not. | ||
| Note: The SPI_RX1 is used only in TWOBIT bit (SPI_CTL[22]) is set 1 | ||
| The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode | ||
| SPI_RX0 shall be read first in TWOBIT mode. | ||
| In FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data. |
| SPI_T::RX1 |
[0x0014] SPI Receive Data FIFO Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | RX | Receive Data Register (Read Only) |
| The received data can be read on it | ||
| If the FIFO bit is set as 1, the user also checks the RXEMPTY, SPI_STATUS[0], to check if there is any more received data or not. | ||
| Note: The SPI_RX1 is used only in TWOBIT bit (SPI_CTL[22]) is set 1 | ||
| The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode | ||
| SPI_RX0 shall be read first in TWOBIT mode. | ||
| In FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data. |
| SC_T::RXTOUT |
[0x0010] SC Receive buffer Time-out Register.
| Bits | Field | Descriptions |
|---|---|---|
| [8:0] | RFTM | SC Receiver FIFO Time-out |
| The time-out counter resets and starts counting whenever the RX buffer received a new data word | ||
| Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ). | ||
| Note1:The counter unit is ETU based and the interval of time-out is RFTM + 0.5. | ||
| Note2: Filling in all 0 to this field indicates to disable this function. |
| PDMA_CH_T::SAn |
| DMA_CRC_T::SEED |
| PWM_T::SELFTEST |
| RTC_T::SPR |
[0x0040] ~ [0x0050] RTC Spare Register 0 ~ 4
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | SPARE | Spare Register |
| This field is used to store back-up information defined by user. | ||
| This field will be cleared by hardware automatically once a snooper pin event is detected. | ||
| Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled. |
| RTC_T::SPRCTL |
[0x003c] RTC Spare Functional Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SNPDEN | Snoop Detection Enable Bit |
| 0 = TAMPER pin detection is Disabled. | ||
| 1 = TAMPER pin detection is Enabled. | ||
| [1] | SNPTYPE0 | Snoop Detection Level |
| This bit controls TAMPER detect event is rising edge or falling edge. | ||
| 0 = Rising edge detection. | ||
| 1 = Falling edge detection. | ||
| [2] | SPRRWEN | Spare Register Enable Bit |
| 0 = Spare register is Disabled. | ||
| 1 = Spare register is Enabled. | ||
| Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR4 cannot be accessed | ||
| Did not change the content of the spare register, but read data all 0. | ||
| [5] | SPRCSTS | SPR Clear Flag |
| This bit indicates if the RTC_SPR0 ~RTC_SPR4 content is cleared when specify snoop event is detected. | ||
| 0 = Spare register content is not cleared. | ||
| 1 = Spare register content is cleared. | ||
| Writes 1 to clear this bit. |
| SPI_T::SSCTL |
[0x000c] SPI Slave Select Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | SS | Slave Selection Control (Master Only) |
| If AUTOSS bit (SPI_SSCTL[3]) is cleared, writing 1 to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing 0 sets the line back to inactive state (the same as SPI_CTL[1] for SPI_SS1). | ||
| If AUTOSS = 0,. | ||
| 00 = Both SPI_SS1 and SPI_SS0 are inactive. | ||
| 01 = SPI_SS1 is inactive, SPI_SS0 is active. | ||
| 10 = SPI_SS1 is active, SPI_SS0 is inactive. | ||
| 11 = Both SPI_SS1 and SPI_SS0 are active. | ||
| If AUTOSS bit is set, writing 1 to any bit location of this field will select appropriate SPI_SS0/SPI_SS1 line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time | ||
| (The active level of SPI_SS1/SPI_SS0 is specified in SSACTPOL). | ||
| If AUTOSS =1,. | ||
| 00 = Both SPI_SS1 and SPI_SS0 are inactive. | ||
| 01 = SPI_SS1 is inactive, SPI_SS0 is active on the duration of transaction. | ||
| 10 = SPI_SS1 is active on the duration of transaction, SPI_SS0 is inactive. | ||
| 11 = Both SPI_SS1 and SPI_SS0 are active on the duration of transaction. | ||
| Note: | ||
| 1. This interface can only drive one device/slave at a given time. Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer. | ||
| 2. SPI_SS0 is also defined as device/slave select input in Slave mode | ||
| And that the slave select input must be driven by edge active trigger which level depend on the SSACTPOL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software | ||
| [2] | SSACTPOL | Slave Selection Active Polarity |
| It defines the active polarity of slave selection signal (SPI_SS[1:0]). | ||
| 0 = The SPI_SS slave select signal is active Low. | ||
| 1 = The SPI_SS slave select signal is active High. | ||
| [3] | AUTOSS | Automatic Slave Selection Function Enable Bit (Master Only) |
| 0 = If this bit is set as 0, slave select signals are asserted and de-asserted by setting and clearing related bits in SS[1:0] (SPI_CTL[1:0]). | ||
| 1 = If this bit is set as 1, SPI_SS0 and SPI_SS1 signals are generated automatically | ||
| It means that device/slave select signal, which is set in SS[1:0] (SPI_CTL[1:0]) is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done. | ||
| [4] | SSLTRIG | Slave Select Level Trigger Control |
| 0 = The input slave select signal is edge-trigger. | ||
| 1 = The slave select signal will be level-trigger | ||
| It depends on SSACTPOL to decide the signal is active low or active high. | ||
| [5] | SLV3WIRE | Slave 3-wire Mode Enable Bit |
| This bit is used to ignore the slave select signal in Slave mode | ||
| The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI when it is set as a slave device. | ||
| 0 = The controller is 4-wire bi-direction interface. | ||
| 1 = The controller is 3-wire bi-direction interface in Slave mode | ||
| When this bit is set as 1, the controller start to transmit/receive data after the GOBUSY bit active and the SPI clock input. | ||
| Note 1: Refer to No Slave Select Mode. | ||
| Note 2: In no slave select signal mode, hardware will set the SSLTRIG (SPI_SSCTL[4]) as 1 automatically. | ||
| [6] | SLVTOIEN | Slave Time-out Interrupt Enable Bit |
| This bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur | ||
| 0 = Slave time-out function and interrupt both Disabled. | ||
| 1 = Slave time-out function and interrupt both Enabled. | ||
| [8] | SLVABORT | Abort in Slave Mode with No Slave Selected |
| 0 = No force the slave abort. | ||
| 1 = Force the current transfer done in no slave select mode. | ||
| Refer to No Slave Select Mode. | ||
| Note: It is auto cleared to 0 by hardware when the abort event is active. | ||
| [9] | SSTAIEN | Slave Start Interrupt Enable Bit |
| 0 = Transfer start interrupt Disabled in no slave select mode. | ||
| 1 = Transaction start interrupt Enabled in no slave select mode | ||
| It is cleared when the current transfer done or the SLVSTAIF bit cleared (write 1 clear). | ||
| Refer to No Slave Select Mode. | ||
| [16] | SSINAIEN | Slave Select Inactive Interrupt Enable Bit |
| It is used to enable the interrupt when the transfer has done in slave mode. | ||
| 0 = No any interrupt, even there is slave select inactive event. | ||
| 1 = There is interrupt event when the slave select becomes inactive from active condition | ||
| It is used to inform the user to know that the transaction has finished and the slave select into the inactive state. | ||
| [29:20] | SLVTOCNT | Slave Mode Time-out Period |
| In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active | ||
| The clock source of the time-out counter is Slave peripheral clock | ||
| If the value is 0, it indicates the slave mode time-out function is disabled. |
| CLK_T::STATUS |
[0x000c] Clock status monitor Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXTSTB | HXT Clock Source Stable Flag (Read Only) |
| 0 = 4~36 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. | ||
| 1 = 4~36 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. | ||
| [1] | LXTSTB | LXT Clock Source Stable Flag (Read Only) |
| 0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. | ||
| 1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. | ||
| [2] | PLLSTB | Internal PLL Clock Source Stable Flag (Read Only) |
| 0 = Internal PLL clock is not stable or disabled. | ||
| 1 = Internal PLL clock is stable and enabled. | ||
| [3] | LIRCSTB | LIRC Clock Source Stable Flag (Read Only) |
| 0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. | ||
| 1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. | ||
| [4] | HIRC0STB | HIRC0 Clock Source Stable Flag (Read Only) |
| 0 = 12~16 MHz internal high speed RC oscillator (HIRC0) clock is not stable or disabled. | ||
| 1 = 12~16 MHz internal high speed RC oscillator (HIRC0) clock is stable and enabled. | ||
| [5] | HIRC1STB | HIRC Clock Source Stable Flag (Read Only) |
| 0 = 36 MHz internal high speed RC oscillator (HIRC1) clock is not stable or disabled. | ||
| 1 = 36 MHz internal high speed RC oscillator (HIRC1) clock is stable and enabled. | ||
| [6] | MIRCSTB | MIRC Clock Source Stable Flag (Read Only) |
| 0 = 4 MHz internal medium speed RC oscillator (MIRC) clock is not stable or disabled. | ||
| 1 = 4 MHz internal medium speed RC oscillator (MIRC) clock is stable and enabled. | ||
| [7] | CLKSFAIL | Clock Switching Fail Flag (Read Only) |
| This bit is updated when software switches system clock source | ||
| If switch target clock is stable, this bit will be set to 0 | ||
| If switch target clock is not stable, this bit will be set to 1. | ||
| 0 = Clock switching success. | ||
| 1 = Clock switching failure. |
| PWM_T::STATUS |
[0x0120] PWM0 Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CNTMAX0 | Time-base Counter 0 Equal to 0xFFFF Latched Status |
| 0 = indicates the time-base counter never reached its maximum value 0xFFFF. | ||
| 1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. | ||
| [2] | CNTMAX2 | Time-base Counter 2 Equal to 0xFFFF Latched Status |
| 0 = indicates the time-base counter never reached its maximum value 0xFFFF. | ||
| 1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. | ||
| [4] | CNTMAX4 | Time-base Counter 4 Equal to 0xFFFF Latched Status |
| 0 = indicates the time-base counter never reached its maximum value 0xFFFF. | ||
| 1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. | ||
| [21:16] | ADCTRGn | ADC Start of Conversion Status |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = Indicates no ADC start of conversion trigger event has occurred. | ||
| 1 = Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
| WDT_T::STATUS |
[0x0008] Watchdog Timer Interrupt Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WDT_IS | Watchdog Timer Time-out Interrupt Status |
| If the Watchdog timer time-out interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer time-out interrupt has occurred | ||
| If the Watchdog timer time-out interrupt is not enabled, then this bit indicates that a time-out period has elapsed. | ||
| 0 = Watchdog timer time-out interrupt did not occur. | ||
| 1 = Watchdog timer time-out interrupt occurred. | ||
| Note: This bit is read only, but can be cleared by writing 1 to it. | ||
| [1] | WDT_RST_IS | Watchdog Timer Reset Status |
| When the Watchdog timer initiates a reset, the hardware will set this bit | ||
| This flag can be read by software to determine the source of reset | ||
| Software is responsible to clear it manually by writing 1 to it | ||
| If WTRE is disabled, then the Watchdog timer has no effect on this bit. | ||
| 0 = Watchdog timer reset did not occur. | ||
| 1 = Watchdog timer reset occurred. | ||
| Note: This bit is read only, but can be cleared by writing 1 to it. | ||
| [2] | WDT_WAKE_IS | Watchdog Timer Wake-up Status |
| If Watchdog timer causes system to wake up from Power-down mode, this bit will be set to 1 | ||
| It must be cleared by software with a write 1 to this bit. | ||
| 0 = Watchdog timer does not cause system wake-up. | ||
| 1 = Wake system up from Power-down mode by Watchdog time-out. | ||
| Note1: When system in Power-down mode and watchdog time-out, hardware will set WDT_WAKE_IS and WDT_IS. | ||
| Note2: After one engine clock, this bit can be cleared by writing 1 to it |
| WWDT_T::STATUS |
[0x000c] Window Watchdog Timer Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WWDTIF | WWDT Compare Match Interrupt Flag |
| When WWCMP matches the WWDT counter, this bit is set to 1 | ||
| This bit can be cleared by writing '1' to it. | ||
| [1] | WWDTRF | WWDT Reset Flag |
| When the WWDT counter down counts to 0 or writes WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1 | ||
| This bit can be cleared by writing '1' to it. |
| SC_T::STATUS |
[0x0020] SC Transfer Status Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXOV | RX Overflow Error Status Flag (Read Only) |
| This bit is set when RX buffer overflow. | ||
| If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [1] | RXEMPTY | Receiver Buffer Empty Status Flag(Read Only) |
| This bit indicates RX buffer empty or not. | ||
| When the last byte of Rx buffer has been read by CPU, hardware sets this bit high | ||
| It will be cleared when SC receives any new data. | ||
| [2] | RXFULL | Receiver Buffer Full Status Flag (Read Only) |
| This bit indicates RX buffer full or not. | ||
| This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware. | ||
| [4] | PEF | Receiver Parity Error Status Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid parity bit. | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. | ||
| [5] | FEF | Receiver Frame Error Status Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. | ||
| [6] | BEF | Receiver Break Error Status Flag (Read Only) |
| This bit is set to logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. | ||
| [8] | TXOV | TX Overflow Error Interrupt Status Flag (Read Only) |
| If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to 1 by hardware. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [9] | TXEMPTY | Transmit Buffer Empty Status Flag (Read Only) |
| This bit indicates TX buffer empty or not. | ||
| When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high | ||
| It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty). | ||
| [10] | TXFULL | Transmit Buffer Full Status Flag (Read Only) |
| This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware. | ||
| [17:16] | RXPOINT | Receiver Buffer Pointer Status Flag (Read Only) |
| This field indicates the RX buffer pointer status flag | ||
| When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one | ||
| When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one. | ||
| [21] | RXRERR | Receiver Retry Error (Read Only) |
| This bit is set by hardware when RX has any error and retries transfer. | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2 This bit is a flag and cannot generate any interrupt to CPU. | ||
| Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). | ||
| [22] | RXOVERR | Receiver over Retry Error (Read Only) |
| This bit is set by hardware when RX transfer error retry over retry number limit. | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). | ||
| [23] | RXACT | Receiver in Active Status Flag (Read Only) |
| This bit is set by hardware when RX transfer is in active. | ||
| This bit is cleared automatically when RX transfer is finished. | ||
| [25:24] | TXPOINT | Transmit Buffer Pointer Status Flag (Read Only) |
| This field indicates the TX buffer pointer status flag | ||
| When CPU writes data into SC_DAT, TXPOINT increases one | ||
| When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one. | ||
| [29] | TXRERR | Transmitter Retry Error (Read Only) |
| This bit is set by hardware when transmitter re-transmits. | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2 This bit is a flag and cannot generate any interrupt to CPU. | ||
| [30] | TXOVERR | Transmitter over Retry Error (Read Only) |
| This bit is set by hardware when transmitter re-transmits over retry number limitation. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [31] | TXACT | Transmit in Active Status Flag (Read Only) |
| 0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed. | ||
| 1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted. |
| I2C_T::STATUS |
[0x0008] I2C Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | STATUS | I2C Status Bits (Read Only) |
| The three least significant bits are always 0 | ||
| The five most significant bits contain the status code | ||
| There are 28 possible status codes | ||
| When the content of I2C_STATUS is F8H, no serial interrupt is requested | ||
| Other I2C_STATUS values correspond to defined I2C states | ||
| When each of these states is entered, a status interrupt is requested (INTSTS = 1) | ||
| A valid status code is present in I2C_STATUS one cycle after INTSTS is set by hardware and is still present one cycle after INTSTS has been reset by software | ||
| In addition, states 00H stands for a Bus Error | ||
| A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame | ||
| Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. |
| SPI_T::STATUS |
[0x0004] SPI Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXEMPTY | Receive FIFO Buffer Empty Indicator (Read Only) |
| 0 = Received data FIFO is not empty in the FIFO mode. | ||
| 1 = Received data FIFO is empty in the FIFO mode. | ||
| [1] | RXFULL | Receive FIFO Buffer Full Indicator (Read Only) |
| 0 = Received data FIFO is not full in FIFO mode. | ||
| 1 = Received data FIFO is full in the FIFO mode. | ||
| [2] | TXEMPTY | Transmit FIFO Buffer Empty Indicator (Read Only) |
| 0 = Transmitted data FIFO is not empty in the FIFO mode. | ||
| 1 =Transmitted data FIFO is empty in the FIFO mode. | ||
| [3] | TXFULL | Transmit FIFO Buffer Full Indicator (Read Only) |
| 0 = Transmitted data FIFO is not full in the FIFO mode. | ||
| 1 = Transmitted data FIFO is full in the FIFO mode. | ||
| [4] | LTRIGF | Level Trigger Accomplish Flag (Read Only) |
| In Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. | ||
| 0 = The transferred bit length of one transaction does not meet the specified requirement. | ||
| 1 = The transferred bit length meets the specified requirement which defined in DWIDTH. | ||
| Note: This bit is READ only | ||
| As the software sets the GOBUSY bit to 1, the LTRIGF will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period | ||
| In FIFO mode, this bit is unmeaning. | ||
| [6] | SLVSTAIF | Slave Start Interrupt Flag |
| It is used to dedicate that the transfer has started in Slave mode with no slave select. | ||
| 0 = Slave started transfer no active. | ||
| 1 = Transfer has started in Slave mode with no slave select | ||
| It is automatically cleared by transfer done or writing '1'. | ||
| [7] | UNITIF | Unit Transfer Interrupt Flag |
| 0 = No transaction has been finished since this bit was cleared to 0. | ||
| 1 = SPI controller has finished one unit transfer. | ||
| Note 1: This bit will be cleared by writing 1 to it. | ||
| 0 = Transfer is not finished yet. | ||
| 1 = Transfer is done. The interrupt is requested when the UNITIEN (SPI_CTL[17]) bit is enabled. | ||
| Note 2: This bit can be cleared by writing 1 to it. | ||
| [8] | RXTHIF | RX FIFO Threshold Interrupt Flag (Read Only) |
| 0 = RX valid data counts small or equal than RXTH (SPI_FIFOCTL[27:24]). | ||
| 1 = RX valid data counts bigger than RXTH. | ||
| Note: If RXTHIEN(SPI_FIFOCTL[2]) = 1 and RXTHIF = 1, SPI will generate interrupt. | ||
| [9] | RXOVIF | Receive FIFO over Run Interrupt Flag |
| 0 = No FIFO over run. | ||
| 1 = Receive FIFO over run. | ||
| Note 1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will be dropped. | ||
| Note 2: This bit will be cleared by writing 1 to it. | ||
| [10] | TXTHIF | Transmit FIFO Threshold Interrupt Flag (Read Only) |
| 0 = TX valid data counts bigger than TXTH (SPI_FIFOCTL[31:28]). | ||
| 1 = TX valid data counts small or equal than TXTH. | ||
| [12] | RXTOIF | Receive Time-out Interrupt Flag |
| 0 = There is not timeout event on the received buffer. | ||
| 1 = Time out event active in RX FIFO is not empty. | ||
| Refer to Time Out section. | ||
| Note: This bit will be cleared by writing 1 to it. | ||
| [13] | SLVTOIF | Slave Time-out Interrupt Flag |
| If SLVTOIEN (SPI_SSCTL[6]) is set to 1, this bit will be asserted when slave time-out event occur | ||
| Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit. | ||
| 0 = Slave time-out does not occur yet. | ||
| 1 = Slave time-out has occurred. | ||
| [15] | SLVTXSKE | Slave Mode Transmit Skew Buffer Empty Status |
| This bit indicates the empty status of transmit skew buffer which is used in Slave mode. | ||
| [19:16] | RXCNT | Receive FIFO Data Counts (Read Only) |
| This bit field indicates the valid data count of receive FIFO buffer. | ||
| [23:20] | TXCNT | Transmit FIFO Data Counts (Read Only) |
| This bit field indicates the valid data count of transmit FIFO buffer. | ||
| [30] | WKSSIF | Wake-up by Slave Select Interrupt Flag |
| When chip is woken up from Power-down mode by the toggle event on SPI_SS port, this bit is set to 1 | ||
| This bit can be cleared by writing '1' to it. | ||
| [31] | WKCLKIF | Wake-up by SPI Clock Interrupt Flag |
| When chip is woken up from Power-down mode by the toggle event on SPI_CLK port, this bit is set to 1 | ||
| This bit can be cleared by writing '1' to it. |
| ADC_T::STATUS |
[0x0058] A/D Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADIF | A/D Conversion End Flag |
| A status flag that indicates the end of A/D conversion, ADIF (ADC_STATUS[0]) is set to 1 at these two conditions: | ||
| When A/D conversion ends in single mode | ||
| When A/D conversion ends on all specified channels in scan mode. | ||
| Note: This bit can be cleared to 0 by software writing 1. | ||
| [1] | ADCMPF0 | A/D Compare Flag 0 |
| When the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1. | ||
| 0 = Conversion result in ADC_DATx does not meet the CMPDAT (ADC_CMP0[27:16]) setting. | ||
| 1 = Conversion result in ADC_DATx meets the CMPDAT (ADC_CMP0[27:16]) setting. | ||
| This flag can be cleared by writing 1 to it. | ||
| Note: This flag can be cleared by software writing 1 to it, when this flag is set, the matching counter will be reset to 0,and continue to count when user writes 1 to clear ADCMPF0 (ADC_STATUS[1]). | ||
| [2] | ADCMPF1 | A/D Compare Flag 1 |
| When the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1. | ||
| 0 = Conversion result in ADC_DATx does not meet the CMPDAT (ADC_CMP1[27:16]) setting. | ||
| 1 = Conversion result in ADC_DATx meets the CMPDAT (ADC_CMP1[27:16]) setting. | ||
| Note: This flag can be cleared by software writing 1 to it, when this flag is set, the matching counter will be reset to 0,and continue to count when user writes 1 to clear ADCMPF1 (ADC_STATUS[2]). | ||
| [3] | BUSY | BUSY/IDLE (Read Only) |
| 0 = A/D converter is in idle state. | ||
| 1 = A/D converter is busy at conversion. | ||
| Note: This bit is mirror of SWTRG (ADC_CTL [11]) bit. | ||
| [8:4] | CHANNEL | Current Conversion Channel (Read Only) |
| This filed reflects the current conversion channel when BUSY (ADC_STATUS[3]) = 1 | ||
| When BUSY (ADC_STATUS[3]) = 0, it shows the number of the next converted channel. | ||
| [16] | INITRDY | ADC Initial Ready by Power-up Sequence Completed |
| 0 = ADC not powered up after system reset. | ||
| 1 = ADC has been powered up since the last system reset. | ||
| Note: This bit will be set after system reset occurred and automatically cleared by power-up event. |
| ACMP_T::STATUS |
[0x0004] Analog Comparator Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ACMPIF | Comparator Interrupt Flag |
| This bit is set by hardware whenever the comparator 0 output changes state | ||
| This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1 | ||
| Note: Write 1 to clear this bit to 0. | ||
| [1] | ACMPO | Comparator Output |
| Synchronized to the PCLK to allow reading by software | ||
| Cleared when the comparator 0 is disabled, i.e | ||
| ACMPEN (ACMP_CTL0[0]) is cleared to 0. | ||
| Note: This bit is read only. |
| I2C_T::STATUS2 |
[0x0044] I2C Status Register 2
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WKIF | Wake-up Interrupt Flag |
| 0 = Wake-up flag is inactive. | ||
| 1 = Wake-up flag is active. | ||
| Note: This bit can be cleared by writing 1 to it. | ||
| [1] | OVIF | I2C Overrun Status Bit |
| 0 = The received buffer is not overrun when the TWOLVBUF = 1. | ||
| 1 = The received buffer is overrun when the TWOLVBUF = 1. | ||
| Note: This bit can be cleared by writing 1 to it. | ||
| [2] | URIF | I2C Under run Status Bit |
| 0 = The transmitted buffer is not Under run when the TWOLVBUF = 1. | ||
| 1 = The transmitted buffer is Under run when the TWOLVBUF = 1. | ||
| Note: This bit can be cleared by writing 1 to it. | ||
| [3] | WRSTSWK | I2C Read/Write Status Bit in Address Wake-up Frame |
| 0 = Write command is recorded on the address match wake-up frame. | ||
| 1 = Read command is recorded on the address match wake-up frame. | ||
| [4] | FULL | I2C Two Level Buffer Full |
| 0 = TX buffer no full when the TWOLVBUF = 1. | ||
| 1 = TX buffer full when the TWOLVBUF = 1. | ||
| [5] | EMPTY | I2C Two Level Buffer Empty |
| 0 = RX buffer is not empty when the TWOLVBUF = 1. | ||
| 1 = RX buffer is empty when the TWOLVBUF = 1. | ||
| [6] | BUSFREE | Bus Free Status |
| The bus status in the controller. | ||
| 0 = I2C's 'Start' condition is detected on the bus. | ||
| 1 = Bus is free and released by 'STOP' condition or the controller is disabled. |
| PWM_T::SWBRK |
[0x00dc] PWM0 Software Brake Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | BRKETRGn | PWM0 Edge Brake Software Trigger (Write Only) (Write Protect) |
| Each bit n controls the corresponding PWM0 pair n. | ||
| Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM0_INTSTS1 register. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [10:8] | BRKLTRGn | PWM0 Level Brake Software Trigger (Write Only) (Write Protect) |
| Each bit n controls the corresponding PWM0 pair n. | ||
| Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM0_INTSTS1 register. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| RTC_T::TALM |
[0x001c] RTC Time Alarm Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | SEC | 1-Sec Time Digit of Alarm Setting (0~9) |
| [6:4] | TENSEC | 10-Sec Time Digit of Alarm Setting (0~5) |
| [11:8] | MIN | 1-Min Time Digit of Alarm Setting (0~9) |
| [14:12] | TENMIN | 10-Min Time Digit of Alarm Setting (0~5) |
| [19:16] | HR | 1-Hour Time Digit of Alarm Setting (0~9) |
| [21:20] | TENHR | 10-hour Time Digit of Alarm Setting (0~2) |
| When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication | ||
| (If RTC_TIME[21] is 1, it indicates PM time message.)the high bit of TENHR (RTC_TIME[21]) means AM/PM indication. |
| RTC_T::TAMPCTL |
[0x010c] TAMPER Pin Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | OPMODE | IO Operation Mode |
| 00 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is input only mode, without pull-up resistor. | ||
| 01 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is output push pull mode. | ||
| 10 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is open drain mode. | ||
| 11 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is input only mode with internal pull up. | ||
| [2] | DOUT | IO Output Data |
| 0 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) output low. | ||
| 1 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) output high. | ||
| [3] | CTLSEL | IO Pin State Backup Selection |
| When tamper function is disabled, TAMPER pin can be used as GPIO function | ||
| User can program CTLSEL bit to decide (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register. | ||
| 0 =TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by GPIO module | ||
| It becomes floating state when system power is turned off. | ||
| 1 =TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by VBAT power domain | ||
| LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1 | ||
| I/O pin state keeps previous state after system power is turned off. | ||
| Note:CTLSEL (this bit) will automatically be set by hardware to 1 when system power is off and RTC Active Status = 1. |
| RTC_T::TAMSK |
[0x0034] RTC Time Alarm Mask Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | MSEC | Mask 1-Sec Time Digit of Alarm Setting (0~9) |
| [1] | MTENSEC | Mask 10-Sec Time Digit of Alarm Setting (0~5) |
| [2] | MMIN | Mask 1-Min Time Digit of Alarm Setting (0~9) |
| [3] | MTENMIN | Mask 10-Min Time Digit of Alarm Setting (0~5) |
| [4] | MHR | Mask 1-Hour Time Digit of Alarm Setting (0~9) |
| [5] | MTENHR | Mask 10-Hour Time Digit of Alarm Setting (0~2) |
| SYS_T::TEMPCTL |
[0x0020] Temperature Sensor Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | VTEMPEN | Temperature Sensor Enable Bit |
| This bit is used to enable/disable temperature sensor function. | ||
| 0 = Temperature sensor function Disabled (default). | ||
| 1 = Temperature sensor function Enabled. |
| RTC_T::TICK |
[0x0030] RTC Time Tick Register
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | TICK | Time Tick Register |
| These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. | ||
| 000 = Time tick is 1 second. | ||
| 001 = Time tick is 1/2 second. | ||
| 010 = Time tick is 1/4 second. | ||
| 011 = Time tick is 1/8 second. | ||
| 100 = Time tick is 1/16 second. | ||
| 101 = Time tick is 1/32 second. | ||
| 110 = Time tick is 1/64 second. | ||
| 111 = Time tick is 1/128 second. | ||
| Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. |
| RTC_T::TIME |
[0x000c] RTC Time Loading Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | SEC | 1-Sec Time Digit (0~9) |
| [6:4] | TENSEC | 10-Sec Time Digit (0~5) |
| [11:8] | MIN | 1-Min Time Digit (0~9) |
| [14:12] | TENMIN | 10-Min Time Digit (0~5) |
| [19:16] | HR | 1-Hour Time Digit (0~9) |
| [21:20] | TENHR | 10-hour Time Digit (0~2) |
| When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication | ||
| (If RTC_TIME[21] is 1, it indicates PM time message.) the high bit of TENHR (RTC_TIME[21]) means AM/PM indication. |
| SC_T::TMRCTL0 |
[0x0028] SC Internal Timer 0 Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CNT | Timer 0 Counter Value (ETU Based) |
| This field indicates the internal timer operation values. | ||
| [27:24] | OPMODE | Timer 0 Operation Mode Selection |
| This field indicates the internal 24-bit timer operation selection. | ||
| Refer toTable 6.15-3 Timer Operation Mode for programming Timer0. | ||
| [31] | SYNC | SYNC Flag Indicator(Read Only) |
| Due to synchronization, software should check this bit when writing a new value to the SC_TMRCTL0 register. | ||
| 0 = Synchronizing is completion, user can write new data to SC_TMRCTL0 register. | ||
| 1 = Last value is synchronizing. |
| SC_T::TMRCTL1 |
[0x002c] SC Internal Timer 1 Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CNT | Timer 1 Counter Value (ETU Based) |
| This field indicates the internal timer operation values. | ||
| [27:24] | OPMODE | Timer 1 Operation Mode Selection |
| This field indicates the internal 8-bit timer operation selection. | ||
| Refer toTable 6.15-3 Timer Operation Mode for programming Timer1. | ||
| [31] | SYNC | SYNC Flag Indicator(Read Only) |
| Due to synchronization, software should check this bit when writing a new value to the SC_TMRCTL1 register. | ||
| 0 = Synchronizing is completion, user can write new data to SC_TMRCTL1 register. | ||
| 1 = Last value is synchronizing. |
| SC_T::TMRCTL2 |
[0x0030] SC Internal Timer 2 Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CNT | Timer 2 Counter Value (ETU Based) |
| This field indicates the internal timer operation values. | ||
| [27:24] | OPMODE | Timer 2 Operation Mode Selection |
| This field indicates the internal 8-bit timer operation selection | ||
| Refer to Table 6.15-3 Timer Operation Mode for programming Timer2. | ||
| [31] | SYNC | SYNC Flag Indicator(Read Only) |
| Due to synchronization, software should check this bit when writing a new value to SC_TMRCTL2 register. | ||
| 0 = Synchronizing is completion, user can write new data to SC_TMRCTL2 register. | ||
| 1 = Last value is synchronizing. |
| PDMA_CH_T::TOCn |
[0x0028] PDMA channel n Time-out Counter Register
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | TOC | PDMA Time-out Period Counter |
| Each PDMA channel contains an internal counter | ||
| This internal counter will reload and start counting when completing each peripheral request service | ||
| The internal counter loads the value of TOC (PDAM_TOCn[15:0], n=1~4) and starts counting down when setting TOUTEN (PDMA_CTLn[12], n=1~4) | ||
| PDMA will request interrupt when this internal counter reaches 0 and TOUTIEN (PDMA_INTENn[6], n=1~4) is 1 | ||
| [18:16] | TPSC | PDMA Time-out Counter Clock Source Prescaler |
| 000 = PDMA time-out clock source is HCLK/28. | ||
| 001 = PDMA time-out clock source is HCLK/29. | ||
| 010 = PDMA time-out clock source is HCLK/210. | ||
| 011 = PDMA time-out clock source is HCLK/211. | ||
| 100 = PDMA time-out clock source is HCLK/212. | ||
| 101 = PDMA time-out clock source is HCLK/213. | ||
| 110 = PDMA time-out clock source is HCLK/214. | ||
| 111 = PDMA time-out clock source is HCLK/215. |
| I2C_T::TOCTL |
[0x0010] I2C Time-out Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TOCEN | Time-out Counter Enable Bit |
| When this bit is set to enabled and clock be stretched, the 14 bits time-out counter will start counting. | ||
| 0 = Time-out counter Disabled. | ||
| 1 = Time-out counter Enabled. | ||
| [1] | TOCDIV4 | Time-out Counter Input Clock Divider by 4 |
| When enabled, the time-out period is extended 4 times. | ||
| 0 = Time-out counter input clock divider by 4 Disabled. | ||
| 1 = Time-out counter input clock divider by 4 Enabled. |
| UART_T::TOUT |
[0x0020] UART Time-Out Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [8:0] | TOIC | Time-out Comparator |
| The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word | ||
| Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TMCTL[8:0])), a receiver time-out interrupt (RXTOIF(UART_ISR[4])) is generated if RXTOIEN (UART_IER [4]) enabled | ||
| A new incoming data word or RX FIFO empty will clear RXTOIF(UART_ISR[4]) | ||
| In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255 | ||
| So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. | ||
| Note1: Fill all 0 to this field indicates to disable this function. | ||
| Note2: The real time-out value is TOIC + 1. | ||
| Note3: The counting clock is baud rate clock. | ||
| Note4: The UART data format is start bit + 8 data bits + parity bit + stop bit, although software can configure this field by any value but it is recommend to fill this field great than 0xA. | ||
| [23:16] | DLY | TX Delay Time Value |
| This field is used to programming the transfer delay time between the last stop bit and next start bit | ||
| The unit is bit time. | ||
| Note1: Fill all 0 to this field indicates to disable this function. | ||
| Note2: The real delay value is DLY. | ||
| Note3: The counting clock is baud rate clock. |
| UART_T::TRSR |
[0x0014] UART Transfer Status Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADDRDETF | RS-485 Address Byte Detection Status Flag (Read Only) |
| 0 = Receiver detects a data that is not an address bit (bit 9 ='0'). | ||
| 1 = Receiver detects a data that is an address bit (bit 9 ='1'). | ||
| Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALT_CSR[19]) is set to 1 to enable Address detection mode . | ||
| Note2: This bit is read only, but can be cleared by writing '1' to it. | ||
| [1] | ABRDIF | Auto-baud Rate Interrupt (Read Only) |
| This bit is set to logic 1 when auto-baud rate detect function finished. | ||
| 0 = No Auto- Baud Rate interrupt is generated. | ||
| 1= Auto-Baud Rate interrupt is generated. | ||
| Note: This bit is read only, but can be cleared by writing 1 to it. | ||
| [2] | ABRDTOIF | Auto-baud Rate Time-out Interrupt (Read Only) |
| 0 = Auto-baud rate counter is underflow. | ||
| 1 = Auto-baud rate counter is overflow. | ||
| Note1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow. | ||
| Note2: This bit is read only, but can be cleared by writing 1 to it. | ||
| [3] | LINTXIF | LIN TX Interrupt Flag (Read Only) |
| This bit is set to logic 1 when LIN transmitted header field | ||
| The header may be break field or break field + sync field or break field + sync field + PID field, it can be choose by setting LINHSEL (UART_ALT_CSR[5:4]) register. | ||
| 0 = No LIN Transmit interrupt is generated. | ||
| 1 = LIN Transmit interrupt is generated. | ||
| Note: This bit is read only, but can be cleared by writing 1 to it. | ||
| [4] | LINRXIF | LIN RX Interrupt Flag (Read Only) |
| This bit is set to logic 1 when received LIN header field | ||
| The header may be break field or break field + sync field or break field + sync field + PID field, and it can be choose by setting LINHSEL (UART_ALT_CSR[5:4]) register. | ||
| 0 = No LIN Rx interrupt is generated. | ||
| 1 = LIN Rx interrupt is generated. | ||
| Note: This bit is read only, but can be cleared by writing 1 to it. | ||
| [5] | BITEF | Bit Error Detect Status Flag (Read Only) |
| At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BITEF will be set. | ||
| When occur bit error, hardware will generate an interrupt to CPU (LININT). | ||
| 0 = No Bit error interrupt is generated. | ||
| 1 = Bit error interrupt is generated. | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2: This bit is only valid when enabling the bit error detection function (BITERREN (UART_ALT_CSR[8]) = 1). | ||
| [7] | RXBUSY | Receive Busy Status (Read Only) |
| 0 = The receiver machine stays in idle state. | ||
| 1 = The receiver machine stays in no Idle state. | ||
| Note: The user can use this to check the busy status in receiver mode | ||
| If the user want to enter the power down, this bit shall be confirm in Idle state and there is 2 UART clock latency for receiver pin. | ||
| [8] | SLVSYNCF | LIN RX SYNC Error Flag (Read Only) |
| This bit is set to logic 1 when LIN received incorrect SYNC field. | ||
| User can choose the header by setting LINHSEL (UART_ALT_CSR[5:4]) register. | ||
| 0 = No LIN Rx sync error is generated. | ||
| 1 = LIN Rx sync error is generated. | ||
| Note: This bit is read only, but can be cleared by writing 1 to LINRXIF. |
| SPI_T::TX0 |
[0x0020] SPI Transmit Data FIFO Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | TX | Transmit Data Register (Write Only) |
| The Data Transmit Registers hold the data to be transmitted in the next transfer | ||
| The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register. | ||
| For example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer | ||
| If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer. | ||
| Note: | ||
| 1. | ||
| The SPI_TX1 is used only when TWOBIT bit (SPI_CTL[22]) is set 1 | ||
| The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode | ||
| SPI_TX0 shall be written first in TWOBIT mode. | ||
| In FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_TX1 is the second channel's transmitted data. | ||
| 2. | ||
| If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1 |
| SPI_T::TX1 |
[0x0024] SPI Transmit Data FIFO Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | TX | Transmit Data Register (Write Only) |
| The Data Transmit Registers hold the data to be transmitted in the next transfer | ||
| The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register. | ||
| For example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer | ||
| If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer. | ||
| Note: | ||
| 1 | ||
| The SPI_TX1 is used only when TWOBIT bit (SPI_CTL[22]) is set 1 | ||
| The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode | ||
| SPI_TX0 shall be written first in TWOBIT mode. | ||
| In FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_TX1 is the second channel's transmitted data. | ||
| 2 | ||
| If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1 |
| SC_T::UARTCTL |
[0x0034] SC UART Mode Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | UARTEN | UART Mode Enable Bit |
| 0 = Smart Card mode. | ||
| 1 = UART mode. | ||
| Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0. | ||
| Note2: When operating in Smart Card mode, user must set UARTEN(SC_UARTCTL [0]) = 00. | ||
| Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine. | ||
| [5:4] | WLS | Word Length Selection |
| 00 = Word length is 8 bits. | ||
| 01 = Word length is 7 bits. | ||
| 10 = Word length is 6 bits. | ||
| 11 = Word length is 5 bits. | ||
| Note: In smart card mode, this WLS must be '00' | ||
| [6] | PBOFF | Parity Bit Disable Control |
| 0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. | ||
| 1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. | ||
| Note: In smart card mode, this field must be '0' (default setting is with parity bit) | ||
| [7] | OPE | Odd Parity Enable Bit |
| 0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
| 1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
| Note: This bit has effect only when PBOFF bit is '0'. |
| ACMP_T::VREF |
[0x0008] Analog Comparator Reference Voltage Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | CRVCTL | Comparator Reference Voltage Setting |
| CRV = CRV source voltage * (1/6+CRVCTL/24). | ||
| [4] | CRVEN | CRV Enable Bit |
| 0 = CRV Disabled. | ||
| 1 = CRV Enabled. | ||
| [5] | CRVSSEL | CRV Source Voltage Selection |
| 0 = VDDA is selected as CRV source voltage. | ||
| 1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage. |
| RTC_T::WEEKDAY |
| PWM_T::WGCTL0 |
[0x00b0] PWM0 Waveform Generation Control Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | ZPCTLn | PWM0 Zero Point Control |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 00 = Do nothing. | ||
| 01 = PWM0 zero point output Low. | ||
| 10 = PWM0 zero point output High. | ||
| 11 = PWM0 zero point output Toggle. | ||
| PWM0 can control output level when PWM0 counter count to zero. | ||
| [27:16] | PRDPCTLn | PWM0 Period (Center) Point Control |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 00 = Do nothing. | ||
| 01 = PWM0 period (center) point output Low. | ||
| 10 = PWM0 period (center) point output High. | ||
| 11 = PWM0 period (center) point output Toggle. | ||
| PWM0 can control output level when PWM0 counter count to (PERIODn+1). | ||
| Note: This bit is center point control when PWM0 counter operating in up-down counter type. |
| PWM_T::WGCTL1 |
[0x00b4] PWM0 Waveform Generation Control Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | CMPUCTLn | PWM0 Compare Up Point Control |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 00 = Do nothing. | ||
| 01 = PWM0 compare up point output Low. | ||
| 10 = PWM0 compare up point output High. | ||
| 11 = PWM0 compare up point output Toggle. | ||
| PWM0 can control output level when PWM0 counter up count to CMPDAT. | ||
| Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. | ||
| [27:16] | CMPDCTLn | PWM0 Compare Down Point Control |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 00 = Do nothing. | ||
| 01 = PWM0 compare down point output Low. | ||
| 10 = PWM0 compare down point output High. | ||
| 11 = PWM0 compare down point output Toggle. | ||
| PWM0 can control output level when PWM0 counter down count to CMPDAT. | ||
| Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. |
| CLK_T::WKINTSTS |
[0x0030] Wake-up Interrupt Status
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PDWKIF | Wake-up Interrupt Status in Chip Power-down Mode |
| This bit indicates that some event resumes chip from Power-down mode | ||
| The status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred. | ||
| Write 1 to clear this bit. |
| SYS_T::WKSTS |
[0x007c] System Wakeup Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ACMPWK | ACMP Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with ACMP wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [1] | I2C1WK | I2C1 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with I2C1 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [2] | I2C0WK | I2C0 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with I2C0 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [3] | TMR3WK | TMR3 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested withTMR3 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [4] | TMR2WK | TMR2 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested withTMR2 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [5] | TMR1WK | TMR1 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested withTMR1 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [6] | TMR0WK | TMR0 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested withTMR0 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [7] | WDTWK | WDT Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with WDT wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [8] | BODWK | BOD Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with BOD wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [9] | SPI3WK | SPI3 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with SPI3 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [10] | SPI2WK | SPI2 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with SPI2 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [11] | SPI1WK | SPI1 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with SPI1 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [12] | SPI0WK | SPI0 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with SPI0 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [13] | UART1WK | UART1 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with UART1 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [14] | UART0WK | UART0 Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with UART0 wakeup event | ||
| This flag is cleared when Power-down mode is entered. | ||
| [15] | RTCWK | RTC Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with a RTC alarm or tick time happened | ||
| This flag is cleared when Power-down mode is entered. | ||
| [16] | GPIOWK | GPIO Wake-up Flag (Read Only) |
| This flag indicates that wakeup of device from Power-down mode was requested with GPIO wakeup event | ||
| This flag is cleared when Power-down mode is entered. |
| UART_T::WKUPEN |
[0x0040] UART Wake-up Enable Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WKCTSEN | nCTS Wake-up Enable Bit |
| When the system is in power-down mode, an external nCTS change will wake-up system from power-down mode. | ||
| 0 = nCTS wake-up function Disabled. | ||
| 1 = nCTS wake-up function Enabled. | ||
| [1] | WKDATEN | Incoming Data Wake-up Enable Bit |
| 0 = Incoming data wake-up function Disabled. | ||
| 1 = Incoming data wake-up function Enabled when the system is in power-down mode, incoming data will wake-up system from power-down mode. | ||
| Note: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable | ||
| [2] | WKTHREN | FIFO Threshold Reach Wake-up Enable Bit |
| 0 = Received FIFO threshold reach wake-up function Disabled. | ||
| 1 = Received FIFO threshold reach wake-up function Enabled when the system is in power-down mode. | ||
| Note: It is suggest the function is enabled in UART mode and the UART clock is selected in 32K. | ||
| [3] | WKTHRTOEN | FIFO Threshold Reach Time Out Wake-up Enable Bit |
| 0 = Received FIFO threshold no reach and time out wake-up function Disabled. | ||
| 1 = Received FIFO threshold no reach and time out wake-up function Enabled when the system is in power-down mode. | ||
| Note: It is suggest the function is enabled when the WKTHREN (UART_WKUPEN[2]) is set to 1. | ||
| [4] | WKADRMEN | RS-485 Address Match Wake-up Enable Bit |
| 0 = RS-485 ADD mode address match wake-up function Disabled. | ||
| 1 = RS-485 AAD mode address match wake-up function Enabled when the system is in power-down mode. |
| UART_T::WKUPSTS |
[0x0044] UART Wake-up Status Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CTSWKSTS | nCTS Wake-up Flag (Read Only) |
| 0 = Chip stays in power-down state. | ||
| 1 = Chip wake-up from power-down state by nCTS wake-up. | ||
| Note1: If WKCTSEN (UART_ WKUPEN [0])is enabled, the wake-up function is generated. | ||
| Note2: This bit is read only, but can be cleared by writing '1' to it. | ||
| [1] | DATWKSTS | Data Wake-up Flag (Read Only) |
| This bit is set if chip wake-up from power-down state by data wake-up. | ||
| 0 = Chip stays in power-down state. | ||
| 1 = Chip wake-up from power-down state by data wake-up. | ||
| Note1: If WKDATEN (UART_ WKUPEN [1]) is enabled, the wake-up function is generated. | ||
| Note2: This bit is read only, but can be cleared by writing '1' to it | ||
| [2] | THRWKSTS | Threshold Wake-up Flag (Read Only) |
| 0 = Chip stays in power-down state. | ||
| 1 = Chip wake-up from power-down state by FIFO threshold wake-up. | ||
| Note1: If WKTHREN (UART_ WKUPEN [2])is enabled, the wake-up function is generated. | ||
| Note2: This bit is read only, but can be cleared by writing '1' to it. | ||
| [3] | THRTOWKSTS | Threshold Wake-up Time Out Flag (Read Only) |
| 0 = Chip stays in power-down state. | ||
| 1 = Chip wake-up from power-down state by FIFO threshold time out wake-up. | ||
| Note1: If WKTHRTOEN (UART_ WKUPEN [3])is enabled, the wake-up function is generated. | ||
| Note2: This bit is read only, but can be cleared by writing '1' to it. | ||
| [4] | ADRWKSTS | RS-485 Address Byte Detection Wake-up Flag (Read Only) |
| 0 = Chip stays in power-down state. | ||
| 1 = Chip wake-up from power-down state by Receiver detects a data that is an address bit (bit 9 ='1'). | ||