|
NolzProceduralProject
COP2001 Project Summer A 2019
|
This file is the header file which defines the function prototypes for the COP2001 Procedural Project. More...
Go to the source code of this file.
Classes | |
| struct | Production_Record |
| struct | Product |
| struct | User |
| struct | Statistics |
Functions | |
| void | authenticate (std::vector< User > &) |
| This function only allows the user to continue to the program if the username and password matches with is stored in the users vector. More... | |
| void | load_existing_data (std::vector< Product > &, std::vector< Production_Record > &, Statistics &, std::vector< User > &) |
| The function loads existing data into the respective vectors if the files exists. More... | |
| bool | prompt_menu_choice (std::vector< Product > &, std::vector< Production_Record > &, Statistics &, std::vector< User > &) |
| This function prompts the user to enter a number to run a corresponding function from the menu printed to the screen. More... | |
| void | show_catalog (std::vector< Product > &) |
| Prints the catalog to the console, and prints that the catalog is empty if no products have been added. More... | |
| void | produce_items (std::vector< Product > &, std::vector< Production_Record > &, Statistics &) |
| Allows the user to track the production of each product within the catalog by writing to the production.txt file. More... | |
| void | add_employee_account (std::vector< User > &) |
| Allows an administrator to add an employee account. More... | |
| std::string | encrypt_string (std::string str) |
| Encrypts user passwords combined with a pseudo-random long long. More... | |
| void | add_new_product (std::vector< Product > &) |
| Allows the user to add a new product to the catalog by writing to the catalog.txt file. More... | |
| std::string | add_music_player () |
| This function adds a music player to the catalog. More... | |
| std::string | add_movie_player () |
| This function adds a movie player to the catalog. More... | |
| void | display_production_statistics (const Statistics &, std::vector< Product > &, const std::vector< Production_Record > &) |
| Displays productions statistics to the user. More... | |
| void | find_production_number (const std::vector< Production_Record > &) |
| User inputs a serial number and the respective production number is output. More... | |
| void | selection_sort (std::vector< Product > &) |
| Sorts the products within the product line alphabetically by comparing the manufacturer strings. More... | |
This file is the header file which defines the function prototypes for the COP2001 Procedural Project.
The function prototypes are stored here and are defined within main.cpp.
| void add_employee_account | ( | std::vector< User > & | ) |
Allows an administrator to add an employee account.
This function allows existing users to add an employee account. The passwords are "encrypted" with a cipher using encrypt_string(str), then a unique pseudo-random salt value is prepended. This string is then hashed using SHA256.
| users | - Reference vector of type User, which holds username, salt, password, and access level. |
| std::string add_movie_player | ( | ) |
This function adds a movie player to the catalog.
This function is called from the add_new_product function and returns the specifications of that product. The user is prompted to enter the monitor type, then prompted to enter the screen's specifications. These two inputs are concatenated and returned to the add_new_product function.
| std::string add_music_player | ( | ) |
This function adds a music player to the catalog.
This function is called from the add_new_product function and returns the specifications of that product. The user is first prompted to enter the supported file formats and then is prompted to enter the media type.
| void add_new_product | ( | std::vector< Product > & | ) |
Allows the user to add a new product to the catalog by writing to the catalog.txt file.
This function allows the user to add a new product to the catalog. The user is prompted to enter the manufacturer, product name, item type, and depending on item type either addMusicPlayer or addMoviePlayer is called to add product specifications. If the user confirms the information they entered is correct, then the new product is added to the products vector and written to catalog.txt.
| products | - Reference vector of type Product, which holds manufacturer, product name, item type code, product specs, and product_info which concatenates all info together. |
| void authenticate | ( | std::vector< User > & | ) |
This function only allows the user to continue to the program if the username and password matches with is stored in the users vector.
If the users vector is empty, then add_employee_account is called, which creates the first user with access level set to "admin". The user is required to authenticate if the vector is not empty, which prompts the user for the username and password. The username contains first syllable of first name and all of last in all lowercase, and the Password must contain at least one uppercase, one lowercase, and one digit with no spaces or special characters.
| users | - Reference vector of type User, which holds username, salt, password, and access level. |
| void display_production_statistics | ( | const Statistics & | , |
| std::vector< Product > & | , | ||
| const std::vector< Production_Record > & | |||
| ) |
Displays productions statistics to the user.
This function will eventually print production statistics to the user, like total number of units tracked, as well as number of units tracked for each item type.
| stats | - Instance of struct named statistics holding counts for production and serial numbers. |
| products | - Vector of type Product holding the details of each product in the product line. |
| prod_record | - Vector of type Production_Record which holds a record of each unit produced in the factory. |
| std::string encrypt_string | ( | std::string | str | ) |
Encrypts user passwords combined with a pseudo-random long long.
This function shifts the ASCII value of each password character and operates on the password string which is prepended with a pseuo-random salt value.
| str | - String composed of salt and encrypted password. |
| void find_production_number | ( | const std::vector< Production_Record > & | ) |
User inputs a serial number and the respective production number is output.
If the production_records vector is empty then the user is notified. Otherwise, the user is prompted to enter a serial number, which is then compared to the serial number substring of each element of the production_records vector. If the element is found, then the production number is found by adding 1 to the index where it was found. If it is not found, then the user is notified and returned to the menu within run_program.
| prod_record | - Reference vector of type Production_Record, which holds production number, product, and serial number. |
| void load_existing_data | ( | std::vector< Product > & | , |
| std::vector< Production_Record > & | , | ||
| Statistics & | , | ||
| std::vector< User > & | |||
| ) |
The function loads existing data into the respective vectors if the files exists.
If the corresponding files exist, then the lines from catalog.txt are added to the products vector, and the lines from production.txt are added to the production_records vector. The respective serial numbers are incremented depending on the substr containing the item_type_code.
| products | - Reference vector of type Product, which holds manufacturer, product name, item type code, product specs, and product_info which concatenates all info together. |
| prod_record | - Reference vector of type Production_Record, which holds production number, product, and serial number. |
| stats | - Instance of type Statistics, which holds the next production number, and serial numbers for each type. |
| users | - Reference vector of type User, which holds username, salt, password, and access level. |
| void produce_items | ( | std::vector< Product > & | , |
| std::vector< Production_Record > & | , | ||
| Statistics & | |||
| ) |
Allows the user to track the production of each product within the catalog by writing to the production.txt file.
This function calls the show_catalog function to prompt the user to enter the number corresponding to the product they wish to track. Then. the user is prompted to enter the number of units produced. Each item tracked is added to the production_records vector and written to a file named production.txt.
| products | - Reference vector of type Product, which holds manufacturer, product name, item type code, product specs, and product_info which concatenates all info together. |
| prod_record | - Reference vector of type Production_Record, which holds production number, product, and serial number. |
| stats | - Instance of type Statistics, which holds the next production number, and serial numbers for each type. |
| bool prompt_menu_choice | ( | std::vector< Product > & | , |
| std::vector< Production_Record > & | , | ||
| Statistics & | , | ||
| std::vector< User > & | |||
| ) |
This function prompts the user to enter a number to run a corresponding function from the menu printed to the screen.
This function is called within main, which returns either true or false then assigned to the flag bool, program_is_running. The function is called continuously within main until the user enters 6 which returns false and the loop is broken.
| products | - Reference vector of type Product, which holds manufacturer, product name, item type code, product specs, and product_info which concatenates all info together. |
| prod_record | - Reference vector of type Production_Record, which holds production number, product, and serial number. |
| stats | - Instance of type Statistics, which holds the next production number, and serial numbers for each type. |
| users | - Reference vector of type User, which holds username, salt, password, and access level. |
| void selection_sort | ( | std::vector< Product > & | ) |
Sorts the products within the product line alphabetically by comparing the manufacturer strings.
This function uses a selection sort to put the products vector in ascending order (A - z). This function is called after a new product is added.
| products | - A vector of type Product which holds the product line information. |
| void show_catalog | ( | std::vector< Product > & | ) |
Prints the catalog to the console, and prints that the catalog is empty if no products have been added.
Uses a for loop to iterate through the products within the catalog if the vector is not empty, and print these elements to the console. It also prints out a number in front of each element to allow the user to choose a product within the function named produce_items.
| products | - Reference vector of type Product, which holds manufacturer, product name, item type code, product specs, and product_info which concatenates all info together. |


Game of Life
Gen:
0
Start
Pause
Reset
Random
?
Rule:
Conway's Game of Life
Wire World
© April, 2019,
archibate


|
Enocean
1.0
|
Public Member Functions | |
| String | encodeTelegram () |
| encodeTelegram provides an example telegram hex for this packet type. More... | |
| String | encodeTelegramData () |
| encodeTelegramData provides an example data hex for this packet type. More... | |
| void | decodeTelegramData (String hexTelegram) |
| decodeTelegramData splits telegram in parts More... | |
| void | dumpData () |
| dumpData Print Data, useful for logs and testing More... | |
| String | toString () |
| int | getSmartAckCommandNr () |
| void | setSmartAckCommandNr (int smartAckCommandNr) |
| int | getSmartAckCommandData () |
| void | setSmartAckCommandData (int smartAckCommandData) |
| Public Member Functions inherited from TelegramHeader | |
| Timestamp | getCreationDate () |
| String | encodeTelegram () |
| String | encodeTelegramHeader () |
| void | decodeTelegram (String hexTelegram) |
| void | decodeTelegramHeader (String hexTelegram) |
| String | getFullTelegram () |
| Long | getData () |
| int | getSyncByte () |
| int | getDataLength () |
| int | getOptionalLenght () |
| int | getCrcHeader () |
| int | getCrcData () |
| void | dumpHeader () |
| print Header in pretty print More... | |
| void | persist () |
| Create an entity manager and persist the current object. More... | |
| void | dump () |
| Used for debugging purposes. More... | |
Private Attributes | |
| Long | id |
| int | smartAckCommandNr |
| int | smartAckCommandData |
Additional Inherited Members | |
| Package Functions inherited from TelegramHeader | |
| void | setData (Long data) |
| void | setSyncByte (int syncByte) |
| void | setDataLength (int dataLength) |
| void | setOptionalLenght (int optionalLenght) |
| void | setCrcData (int crcData) |
| Package Attributes inherited from TelegramHeader | |
| int | dataLength |
| int | crcData |
Definition at line 13 of file SmartAckCommand.java.
| void decodeTelegramData | ( | String | hexTelegram | ) |
decodeTelegramData splits telegram in parts
| hexTelegram | in hex String |
Implements EncodeDecode.
Definition at line 46 of file SmartAckCommand.java.
| void dumpData | ( | ) |
dumpData Print Data, useful for logs and testing
Implements EncodeDecode.
Definition at line 61 of file SmartAckCommand.java.
| String encodeTelegram | ( | ) |
encodeTelegram provides an example telegram hex for this packet type.
Implements EncodeDecode.
Definition at line 28 of file SmartAckCommand.java.
| String encodeTelegramData | ( | ) |
encodeTelegramData provides an example data hex for this packet type.
Implements EncodeDecode.
Definition at line 37 of file SmartAckCommand.java.
| int getSmartAckCommandData | ( | ) |
Definition at line 80 of file SmartAckCommand.java.
| int getSmartAckCommandNr | ( | ) |
Definition at line 72 of file SmartAckCommand.java.
| void setSmartAckCommandData | ( | int | smartAckCommandData | ) |
Definition at line 84 of file SmartAckCommand.java.
| void setSmartAckCommandNr | ( | int | smartAckCommandNr | ) |
Definition at line 76 of file SmartAckCommand.java.
| String toString | ( | ) |
|
private |
Definition at line 18 of file SmartAckCommand.java.
|
private |
Definition at line 21 of file SmartAckCommand.java.
|
private |
Definition at line 20 of file SmartAckCommand.java.


MICHAEL ROGERS
Full Stack
Web Developer
About Me
Dad. Developer. Coffee enthusiast. I'm a California native, curently living in the Sacramento Valley and studying to become a full stack web developer. Coding and development fuel my passion for learning and ignite my creativity. I see each step in the process as an all consuming puzzle that I just can't put down.
Contact Info
Email<EMAIL_ADDRESS>Git: Mrogers23458
LinkedIn: Mrogers23458


© 2016 Dispensa 63 All rights reserved. Website design and development by Evonove.
P.IVA {{settings.options.WebsiteSettings.vat}}.


public interface ProxyTrust extends Remote
ProxyTrustVerifier
trust verifier for use with
Security.verifyObjectTrust
; given a service proxy,
ProxyTrustVerifier
obtains from it a bootstrap proxy (which
must be an instance of both ProxyTrust
and
RemoteMethodControl
), and after verifying
that the bootstrap proxy (or a derivative) is trusted by the client, calls
the getProxyVerifier
method of the bootstrap proxy (or
derivative) to obtain a verifier, and then uses that
verifier to determine if the original service proxy can be trusted. Other
trust verifiers may also make use of ProxyTrust
.| Modifier and Type | Method and Description |
|---|---|
TrustVerifier |
getProxyVerifier()
Returns a
TrustVerifier which can be used to verify that
a proxy can be trusted as a proxy for the service; that is, the
isTrustedObject method of the
returned verifier can be called with a candidate proxy. |
TrustVerifier getProxyVerifier() throws RemoteException
TrustVerifier
which can be used to verify that
a proxy can be trusted as a proxy for the service; that is, the
isTrustedObject
method of the
returned verifier can be called with a candidate proxy. The verifier
should be able to verify all proxies for the service, including
proxies for resources (such as leases and registrations).TrustVerifier
which can be used to verify that
a proxy can be trusted as a proxy for the serviceRemoteException
- if a communication-related exception occurs


With ten calls to drawOval()
.
Or,
better yet, with a call to drawOval()
inside of a loop body
that is iterated 10 times.
Here is a start on an applet that uses a loop to draw ten red circles.
import java.applet.Applet; import java.awt.*; // assume that the drawing area is 300 by 150 public class tenCircles extends Applet { final int width = 300, height = 150; public void paint ( Graphics gr ) { int count = _________________; while ( _________________ ) { _________________ } } }
It is often a good idea to think about what you are doing one piece at a time. When there is a loop in a program, it it often helpful to start with it.
The program skeleton has most of what is needed. It has:
paint()
method.


nano
`Prev `__
N
`Next `__
--------------
**nano**: /nan´oh/, n.
[CMU: from nanosecond] A brief period of time. “Be with you in a nano”
means you really will be free shortly, i.e., implies what mainstream
people mean by “in a jiffy” (whereas the hackish use of ‘jiffy’ is quite
different — see `*jiffy* <../J/jiffy.html>`__).
--------------
+-------------------------+----------------------------+--------------------------+
| `Prev `__ | `Up <../N.html>`__ | `Next `__ |
+-------------------------+----------------------------+--------------------------+
| NANA | `Home <../index.html>`__ | nano- |
+-------------------------+----------------------------+--------------------------+


To view the properties of a file or a directory, select the file or directory that you are interested in and, do any one of the following:
Local File -> Properties
menu item
from the menu bar
Ctrl + Shift + I (Command + Shift + I on
Mac OS X)
on your key board
Properties
from the context
menu
When you do any of the above actions, the
Properties
dialog box is displayed containing the following information:
Name
Displays name of the file or directory of which you are
viewing the properties.
Full Path
Displays full path of this file or directory.
Type
Displays type of this file.
Size
Displays size of this file or directory. If the selected
object is a directory, it will be processed recursively to display the
total size of all files and sub directories underneath it.
If you are viewing properties of a directory and, have a filter setup, the size will only be calculated for files that match your filter criteria.
Contains
Displays total number of files and sub directories in the
selected directory.
This field is displayed if and only if the selected object is a directory. If you have a filter setup, the count will include only those files that match your filter criteria.
Last Modified
Displays the date and time this file was last modified.
Attributes
Displays attributes of the selected file or directory. These
attributes include, whether or not this file is readable, writable or
hidden.
Close
Clicking on this button closes the properties dialog.
Help
Clicking on this button displays this help topic.


syracuse interface workshop
Arsalan Kahnemuyipour and Jaklin Kornfilt have organized an interface workshop at Syracuse University. You can download the program with abstracts here.
More …Arsalan Kahnemuyipour and Jaklin Kornfilt have organized an interface workshop at Syracuse University. You can download the program with abstracts here.
More …Workshop on Mixed Models on May 3rd and May 4th 2010
[The slides from the workshop are now posted on Florian’s blog. Thanks everyone who participated for making this an interesting event!]
The gripp reading group at McGill and the CRLMB are organizing a statistics workshop on logit mixed models.
The workshop will feature lectures and tutorials on ordinary and multilevel/mixed models by Florian Jaeger (University of Rochester), Maureen Gillespie (Northeastern), and Peter Graff (MIT).
Sponsors: CRLMB, prosody.lab, the Mcgill Infant
Development Cluster, the PoP lab, the Auditory Cognitive Neuroscience
training grant, Digging into Data (SSHRC/NSF), and BRAMS.
The program for Mosaic 2, the meeting of semanticists active in Canada, is now online. It will take place on June 1st at McGill, as a satellite workshop to the cla/acl meeting at Concordia.
If you plan on attending, please register here.
TheCNS annual meeting in Montréal is looming. Here are some links to prosody-related posters from the website. This list is not intended to be complete in any way, it’s just what I saw while gleaning through the list in the last 15min:
More …This looks pretty interesting: Brams scientific day
BRAMS is pleased to announce a full-day symposium on Auditory Cognitive Neuroscience. This event will double as the 2010 BRAMS Scientific Day, and will be held on April 16th 2010. The symposium will be held one day before the Cognitive Neuroscience Society meeting in the Jeanne Timmins auditorium of the Montreal Neurological Institute.
Brams is the International Laboratory for Brain, Music and Sound Research. Prosody.lab is currently running a study on Euroopean and Québec French in their fancy lab-space over at Université de Montréal.
Extended Deadline: 16th of April, 2010
The Phonlex project (From Phonology to the Lexicon: liaison and cognition in
contemporary French) brings together 4 linguistic and psycholinguistic
research teams in Toulouse, Grenoble and Paris. These teams have been
investigating various dimensions of French liaison: phonological and
phonetic aspects, regional variation, the synchronic and diachronic
dimension, oral developmental issues as well as liaison in written production.
These topics will constitute the core of our conference. However, French
liaison is not an isolated sandhi phenomenon within the languages of the
world and we therefore welcome papers which discuss the wider issue of
word-segmentation and adjustments at word-boundaries.
The deadline for abstract submission for on linguistic lnterfaces is approaching.
Date: 02-Dec-2010 - 04-Dec-2010
Location: Belfast, Northern Ireland, United Kingdom
Deadline for abstract submission: April 30
A full description of our knowledge of language must include reference to several different components, each with its own particular properties. These components must interact with each other, and with a lexicon, which we may think of as a system of stored associations between pieces of information pertaining to many of the above components. In recent years, the study of the interaction between these different levels of linguistic knowledge has attracted increasing interest. The nature and extent of the interaction of different linguistic modules is a central question to be addressed by a modern theory of linguistic knowledge.
The program of the workshop on prosodic development, organized by Pilar Prieto is now available online.
The main goal of this one-day workshop is to discuss different aspects of the children’s prosodic development in different languages. Discussions will address specific questions regarding the influence of language-specific distributional and frequency properties on language development and also the influence of general production and perception constraints. One of the goals will be to try to bridge the gap between perception and production studies in prosodic development.
A call for frontiers of prosody, a conference to take place in Leiden, Netherlands, was just posted:
We welcome the submission of work which uses behavioral and neuroimaging methods to address the role of prosodic information in production and comprehension, including individual variation and effects that can be attributed to typologically different prosodic systems.
Deadline for abstract submission: August 15, 2010
Workshop: November 19-20, 2010 in Leiden, Netherlands
AMLaP is an international conference which has established itself as the premier European venue for interdisciplinary research into how people process language. The aim of the conference is to bring together psychological, computational, and theoretical perspectives on the cognitive mechanisms which underlie any aspect of human language processing. Submissions which integrate experimental psycholinguistic evidence with formal or computational models of psychological processes are especially encouraged.
6th - 8th September 2010, York, UK
Submission Dates: Abstract submission will open May 1st. Abstracts due by May 28th.


Provides additional color infrastructure so SVG and XSL-FO implementations can store additional color information and do things like specialized color conversions.


Creative Computing
Joel Gethin Lewis
Week 2: Lecture 4: Deciding
What I'm going to talk about now:
- Group meditation.
- Questions?
- Deciding - logic in humans and computers.
- Looping - doing things many times, but using logic to stop.
- Moving from two spatial dimensions to three.
- Some artists working in three dimensions.
- Feedback.
- Homework Assignment - exercises from Code as Creative Medium - Conditional Testing and Iteration as well as introduction to p5.js
Are you recording Joel? Have you taken the register first?
2. Deciding - logic in humans and computers
- Boolean algebra, named after George Boole. The Boolean data type is a common to most programming languages - only two values - True (1) or False (0). One is true, nothing is false.
- Boolean operators allow you to combine or invert boolean data types - the three basic ones are AND, OR and NOT.
- Control flow in programming is how you control the flow of which part of the program is executed next.
- Conditional statements, such as if statements are very common.
3. Looping - doing things many times, but using logic to stop
- Loops such as while loops and for loops are also very common.
- Let's try writing some loops in p5.js on the editor to print things out.
4. Moving from two spatial dimensions to three
4. Moving from two spatial dimensions to three (continued)
- One way of storing three dimensional information is using point clouds.
- The output of three dimensional scanners is often in point clouds - a grid of positions, each with a depth value - think of Pin Art toys from the 1980's.
- Another way of storing three dimensional data is to use Voxels (from the initial letters of volume and element, with the insertion of -x- for ease of pronunciation).
- Voxels can be a super efficient way of storing three dimension information - used for everything from MRI scanners to Minecraft.
- Creative uses of points in space: Motorstudio Design Room / Hermès × Tokujin Yoshioka / Shining360 by Claire Hentschker.
4. Moving from two spatial dimensions to three (continued)
- Another way of storing three dimensional information is using a series of polygons.
- Polygons are geometric objects with at least three straight lines and angles.
- Polygons are plane figures - i.e. they are flat.
- Some examples: squares, triangles and pentagons.
- Triangles are often used in three dimensional software and games - for more information about why this is so see this Computerphile video about A Universe of Triangles.
4. Moving from two spatial dimensions to three (continued)
- A Polyhedron is a three dimensional shape made of multiple polygons.
- The Platonic Solids are a set of three dimensional shapes that have been known about since Ancient Greece and possibly back to Neolithic times.
- Paul Bourke maintains an amazing list of algorithms and code for dealing with: Geometry, Surfaces, Curves, Polyhedra, Fractals, Chaos, Self similarity, Photographic reconstruction, Domes, Planetariums, Fisheye, Spherical mirror, Stereographics and 3D Projection. It's always my first place to check if I've got a geometric question.
5. Artists working in three dimensions.
6. Feedback
- What's working?
- What's not working?
- What am I missing?
- Lets talk now or you can Slack me in private.


--- title: Asylo's SGX SDK backend dependencies overview: Details about Asylo's repository rules for including the SGX SDK backend dependencies. home_location: https://asylo.dev/docs/reference/api/bazel/sgx_deps.bzl.v1.html layout: skylark-docs redirect_from: /docs/reference/api/bazel/sgx_deps.bzl.html number_of_entries: 1 ---
The file sgx_deps.bzl
defines the Bazel repository rules needed to declare a dependency on the SGX backend in your WORKSPACE
file. You may include its macros (e.g., sgx_deps
) with the following line in your WORKSPACE
file:
load("@com_google_asylo//asylo/bazel:sgx_deps.bzl", "sgx_deps")
The rule used to depend on the Asylo SGX backend toolchain and supporting libraries.
| Argument | Type | Description |
|---|---|---|
installation_path |
string |
[optional] The absolute path to the installed Asylo toolchain for building SGX targets. The default value for this path comes either from the user installation path in |


Las Ramblas is the best-known landmark in Barcelona. This thriving pedestrian thoroughfare cuts through the old town, winding down from the Plaça de Catalunya to the Columbus monument. The centre is filled with bustling stalls creating an open-air market with souvenir and newspaper kiosks, and of course the world-famous flower stalls line the pedestrian walkway.
You always can visit Twitter
Fishermen were naturally the first to settle during the 18th century on the seafront land now known as Barceloneta. Even now if you delve into the dim, narrow back streets, there is still an old village feel to the place, with old women shouting to one another across balconies and old men sitting on the street outside the door to their house. However Barceloneta now also has a different side, a cosmopolitan, tourist-driven life of its own, bars and cafes booming out music day and night.
You can find out more... Tripadvisor
El Born in Barcelona is more than an artistic and eclectic neighborhood, it has ties to a noble past. In medieval days, it became home to the aristocracy, and the center of trade due to its proximity to the sea which gave a name to most streets. Partially destroyed during the secession war in the XVIII century, it came back to the center of Barcelona´s life with a share of innocuous antagonism for ¨the establishment¨. El Born is a unique and historical destination worthy touring in Barcelona, and before you sequester yourself on other stuff, make sure you do these essential things to do at El Born.
Check it out in... Barcelona Eat Local


Map TRACE Report
Loading design for application trce from file ds18b20_impl1_map.ncd.
Design name: ds18b20_top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-4000HC
Package: CSBGA132
Performance: 5
Loading device for application trce from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.10_x64/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) <IP_ADDRESS>.2
Fri Feb 19 19:37:31 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o ds18b20_impl1.tw1 -gui -msgset C:/fpga/ds18b20/promote.xml ds18b20_impl1_map.ncd ds18b20_impl1.prf
Design file: ds18b20_impl1_map.ncd
Preference file: ds18b20_impl1.prf
Device,speed: LCMXO2-4000HC,5
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "sys_clk_c" 103.756000 MHz (4096 errors)
4096 items scored, 4096 timing errors detected.
Warning: 7.421MHz is the maximum frequency for this preference.
FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz (4096 errors)
4096 items scored, 4096 timing errors detected.
Warning: 12.967MHz is the maximum frequency for this preference.
FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz (119 errors)
208 items scored, 119 timing errors detected.
Warning: 27.149MHz is the maximum frequency for this preference.
FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz (1022 errors)
1337 items scored, 1022 timing errors detected.
Warning: 9.016MHz is the maximum frequency for this preference.
FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz (1969 errors)
2003 items scored, 1969 timing errors detected.
Warning: 4.761MHz is the maximum frequency for this preference.
FREQUENCY NET "m_DS18B20Z/clk_1mhz" 293.858000 MHz (59 errors)
59 items scored, 59 timing errors detected.
Warning: 32.174MHz is the maximum frequency for this preference.
Report Type: based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "sys_clk_c" 103.756000 MHz ;
4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 5.634ns (weighted slack = -125.116ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_min_low_i3 (from m_clock/clk_1ms +)
Destination: FF Data in m_OLED12832/char_i3 (to sys_clk_c +)
Delay: 5.918ns (41.0% logic, 59.0% route), 5 logic levels.
Constraint Details:
5.918ns physical path delay m_clock/SLICE_358 to m_OLED12832/SLICE_192 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 9.638ns)
0.434ns delay constraint less
0.150ns DIN_SET requirement (totaling 0.284ns) by 5.634ns
Physical Path Details:
Data path m_clock/SLICE_358 to m_OLED12832/SLICE_192:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 *SLICE_358.CLK to */SLICE_358.Q0 m_clock/SLICE_358 (from m_clock/clk_1ms)
ROUTE 11 e 1.030 */SLICE_358.Q0 to */SLICE_409.B1 time_min_low_3
CTOOFX_DEL --- 0.661 */SLICE_409.B1 to *LICE_409.OFX0 m_OLED12832/i24294/SLICE_409
ROUTE 1 e 1.030 *LICE_409.OFX0 to */SLICE_626.A1 m_OLED12832/n27213
CTOF_DEL --- 0.452 */SLICE_626.A1 to */SLICE_626.F1 m_OLED12832/SLICE_626
ROUTE 1 e 0.401 */SLICE_626.F1 to */SLICE_626.B0 m_OLED12832/char_167_N_690_3
CTOF_DEL --- 0.452 */SLICE_626.B0 to */SLICE_626.F0 m_OLED12832/SLICE_626
ROUTE 1 e 1.030 */SLICE_626.F0 to */SLICE_192.C1 m_OLED12832/n16_adj_1717
CTOF_DEL --- 0.452 */SLICE_192.C1 to */SLICE_192.F1 m_OLED12832/SLICE_192
ROUTE 1 e 0.001 */SLICE_192.F1 to *SLICE_192.DI1 m_OLED12832/char_167_N_359_3 (to sys_clk_c)
--------
5.918 (41.0% logic, 59.0% route), 5 logic levels.
Warning: 7.421MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ;
4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 14.239ns (weighted slack = -68.259ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/data_out_i0_i10 (from sys_clk_c +)
Destination: FF Data in m_uart_tx/uart_data_i2 (to m_uart_tx/clk_en +)
FF m_uart_tx/uart_data_i1
Delay: 15.839ns (32.4% logic, 67.6% route), 11 logic levels.
Constraint Details:
15.839ns physical path delay SLICE_349 to SLICE_319 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 8.859ns)
1.848ns delay constraint less
0.248ns LSR_SET requirement (totaling 1.600ns) by 14.239ns
Physical Path Details:
Data path SLICE_349 to SLICE_319:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 SLICE_349.CLK to SLICE_349.Q0 SLICE_349 (from sys_clk_c)
ROUTE 6 e 1.030 SLICE_349.Q0 to */SLICE_832.A0 temp_raw_data_10
CTOF_DEL --- 0.452 */SLICE_832.A0 to */SLICE_832.F0 m_bcd_8421/SLICE_832
ROUTE 8 e 1.030 */SLICE_832.F0 to */SLICE_831.B1 m_bcd_8421/n27678
CTOF_DEL --- 0.452 */SLICE_831.B1 to */SLICE_831.F1 m_bcd_8421/SLICE_831
ROUTE 2 e 1.030 */SLICE_831.F1 to */SLICE_836.D1 m_bcd_8421/n25340
CTOF_DEL --- 0.452 */SLICE_836.D1 to */SLICE_836.F1 m_bcd_8421/SLICE_836
ROUTE 1 e 1.030 */SLICE_836.F1 to */SLICE_723.C1 m_bcd_8421/n4_adj_1660
CTOF_DEL --- 0.452 */SLICE_723.C1 to */SLICE_723.F1 m_bcd_8421/SLICE_723
ROUTE 2 e 1.030 */SLICE_723.F1 to */SLICE_826.D0 m_bcd_8421/n17632
CTOF_DEL --- 0.452 */SLICE_826.D0 to */SLICE_826.F0 m_bcd_8421/SLICE_826
ROUTE 1 e 0.401 */SLICE_826.F0 to */SLICE_826.B1 m_bcd_8421/n6
CTOF_DEL --- 0.452 */SLICE_826.B1 to */SLICE_826.F1 m_bcd_8421/SLICE_826
ROUTE 3 e 1.030 */SLICE_826.F1 to SLICE_320.C0 m_bcd_8421/n25059
CTOF_DEL --- 0.452 SLICE_320.C0 to SLICE_320.F0 SLICE_320
ROUTE 3 e 1.030 SLICE_320.F0 to */SLICE_378.D1 uart_data_120_N_1204_0
CTOOFX_DEL --- 0.661 */SLICE_378.D1 to *LICE_378.OFX0 m_uart_tx/i23879/SLICE_378
ROUTE 1 e 1.030 *LICE_378.OFX0 to SLICE_616.D1 m_uart_tx/n26542
CTOF_DEL --- 0.452 SLICE_616.D1 to SLICE_616.F1 SLICE_616
ROUTE 3 e 1.030 SLICE_616.F1 to SLICE_329.D0 n26544
CTOF_DEL --- 0.452 SLICE_329.D0 to SLICE_329.F0 SLICE_329
ROUTE 14 e 1.030 SLICE_329.F0 to SLICE_319.LSR uart_data_120_N_1005_5 (to m_uart_tx/clk_en)
--------
15.839 (32.4% logic, 67.6% route), 11 logic levels.
Warning: 12.967MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ;
208 items scored, 119 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 6.168ns (weighted slack = -31.934ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/uart_data_i48 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/uart_out_48 (to m_uart_tx/clk_uart +)
Delay: 6.965ns (40.8% logic, 59.2% route), 5 logic levels.
Constraint Details:
6.965ns physical path delay SLICE_615 to m_uart_tx/SLICE_367 exceeds
(delay constraint based on source clock period of 8.859ns and destination clock period of 4.903ns)
0.947ns delay constraint less
0.150ns DIN_SET requirement (totaling 0.797ns) by 6.168ns
Physical Path Details:
Data path SLICE_615 to m_uart_tx/SLICE_367:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 SLICE_615.CLK to SLICE_615.Q1 SLICE_615 (from m_uart_tx/clk_en)
ROUTE 1 e 1.030 SLICE_615.Q1 to */SLICE_377.B1 m_uart_tx/uart_data_106
CTOOFX_DEL --- 0.661 */SLICE_377.B1 to *LICE_377.OFX0 m_uart_tx/i24307/SLICE_377
ROUTE 1 e 1.030 *LICE_377.OFX0 to */SLICE_376.A0 m_uart_tx/n27237
CTOOFX_DEL --- 0.661 */SLICE_376.A0 to *LICE_376.OFX0 m_uart_tx/i24309/SLICE_376
ROUTE 1 e 1.030 *LICE_376.OFX0 to SLICE_743.A0 m_uart_tx/n27239
CTOF_DEL --- 0.452 SLICE_743.A0 to SLICE_743.F0 SLICE_743
ROUTE 1 e 1.030 SLICE_743.F0 to */SLICE_367.C1 m_uart_tx/n25743
CTOOFX_DEL --- 0.661 */SLICE_367.C1 to *LICE_367.OFX0 m_uart_tx/SLICE_367
ROUTE 1 e 0.001 *LICE_367.OFX0 to *SLICE_367.DI0 m_uart_tx/uart_out_N_1245 (to m_uart_tx/clk_uart)
--------
6.965 (40.8% logic, 59.2% route), 5 logic levels.
Warning: 27.149MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ;
1337 items scored, 1022 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 7.300ns (weighted slack = -106.312ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/hour_set_high__i1 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/time_hour_high_i1 (to m_clock/clk_1ms +)
FF m_clock/time_hour_high_i0
Delay: 7.367ns (30.1% logic, 69.9% route), 5 logic levels.
Constraint Details:
7.367ns physical path delay m_clock/SLICE_280 to m_clock/SLICE_350 exceeds
(delay constraint based on source clock period of 7.300ns and destination clock period of 4.602ns)
0.316ns delay constraint less
0.249ns CE_SET requirement (totaling 0.067ns) by 7.300ns
Physical Path Details:
Data path m_clock/SLICE_280 to m_clock/SLICE_350:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 *SLICE_280.CLK to */SLICE_280.Q1 m_clock/SLICE_280 (from m_clock/clk_500ms)
ROUTE 2 e 1.030 */SLICE_280.Q1 to */SLICE_963.C0 m_clock/hour_set_high_1
CTOF_DEL --- 0.452 */SLICE_963.C0 to */SLICE_963.F0 m_clock/SLICE_963
ROUTE 1 e 1.030 */SLICE_963.F0 to */SLICE_812.B0 m_clock/n28
CTOF_DEL --- 0.452 */SLICE_812.B0 to */SLICE_812.F0 m_clock/SLICE_812
ROUTE 4 e 1.030 */SLICE_812.F0 to */SLICE_998.B0 m_clock/n25895
CTOF_DEL --- 0.452 */SLICE_998.B0 to */SLICE_998.F0 m_clock/SLICE_998
ROUTE 28 e 1.030 */SLICE_998.F0 to */SLICE_806.A1 m_clock/clk_1ms_enable_32
CTOF_DEL --- 0.452 */SLICE_806.A1 to */SLICE_806.F1 m_clock/SLICE_806
ROUTE 2 e 1.030 */SLICE_806.F1 to */SLICE_350.CE m_clock/clk_1ms_enable_21 (to m_clock/clk_1ms)
--------
7.367 (30.1% logic, 69.9% route), 5 logic levels.
Warning: 9.016MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ;
2003 items scored, 1969 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 13.274ns (weighted slack = -202.720ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/time_hour_low_i1 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/hour_set_low__i2 (to m_clock/clk_500ms +)
Delay: 13.504ns (31.4% logic, 68.6% route), 9 logic levels.
Constraint Details:
13.504ns physical path delay m_clock/SLICE_352 to m_clock/SLICE_284 exceeds
(delay constraint based on source clock period of 4.602ns and destination clock period of 7.300ns)
0.478ns delay constraint less
0.248ns LSR_SET requirement (totaling 0.230ns) by 13.274ns
Physical Path Details:
Data path m_clock/SLICE_352 to m_clock/SLICE_284:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 *SLICE_352.CLK to */SLICE_352.Q1 m_clock/SLICE_352 (from m_clock/clk_1ms)
ROUTE 15 e 1.030 */SLICE_352.Q1 to */SLICE_822.A0 time_hour_low_1
CTOF_DEL --- 0.452 */SLICE_822.A0 to */SLICE_822.F0 m_clock/SLICE_822
ROUTE 3 e 1.030 */SLICE_822.F0 to */SLICE_451.C1 n10387
CTOOFX_DEL --- 0.661 */SLICE_451.C1 to *LICE_451.OFX0 m_clock/i1299/SLICE_451
ROUTE 1 e 1.030 *LICE_451.OFX0 to */SLICE_818.A0 m_clock/n1153
CTOF_DEL --- 0.452 */SLICE_818.A0 to */SLICE_818.F0 m_clock/SLICE_818
ROUTE 4 e 1.030 */SLICE_818.F0 to */SLICE_281.D1 m_clock/n25510
CTOF_DEL --- 0.452 */SLICE_281.D1 to */SLICE_281.F1 m_clock/SLICE_281
ROUTE 2 e 1.030 */SLICE_281.F1 to SLICE_734.C1 m_clock/n8350
CTOF_DEL --- 0.452 SLICE_734.C1 to SLICE_734.F1 SLICE_734
ROUTE 1 e 1.030 SLICE_734.F1 to SLICE_363.C0 m_clock/n8993
CTOF_DEL --- 0.452 SLICE_363.C0 to SLICE_363.F0 SLICE_363
ROUTE 1 e 1.030 SLICE_363.F0 to */SLICE_817.C1 m_clock/n6_adj_1666
CTOF_DEL --- 0.452 */SLICE_817.C1 to */SLICE_817.F1 m_clock/SLICE_817
ROUTE 2 e 1.030 */SLICE_817.F1 to */SLICE_937.D1 m_clock/n25024
CTOF_DEL --- 0.452 */SLICE_937.D1 to */SLICE_937.F1 m_clock/SLICE_937
ROUTE 4 e 1.030 */SLICE_937.F1 to *SLICE_284.LSR m_clock/n12374 (to m_clock/clk_500ms)
--------
13.504 (31.4% logic, 68.6% route), 9 logic levels.
Warning: 4.761MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "m_DS18B20Z/clk_1mhz" 293.858000 MHz ;
59 items scored, 59 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 4.644ns (weighted slack = -27.677ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/cnt_i0_i0 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/one_wire_buffer_155 (to m_DS18B20Z/clk_1mhz +)
Delay: 5.065ns (39.0% logic, 61.0% route), 4 logic levels.
Constraint Details:
5.065ns physical path delay m_DS18B20Z/SLICE_146 to m_DS18B20Z/SLICE_340 exceeds
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
0.571ns delay constraint less
0.150ns DIN_SET requirement (totaling 0.421ns) by 4.644ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_146 to m_DS18B20Z/SLICE_340:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 *SLICE_146.CLK to */SLICE_146.Q0 m_DS18B20Z/SLICE_146 (from sys_clk_c)
ROUTE 15 e 1.030 */SLICE_146.Q0 to */SLICE_460.B1 m_DS18B20Z/cnt_0
CTOOFX_DEL --- 0.661 */SLICE_460.B1 to *LICE_460.OFX0 m_DS18B20Z/i24355/SLICE_460
ROUTE 1 e 1.030 *LICE_460.OFX0 to */SLICE_974.A1 m_DS18B20Z/one_wire_N_281
CTOF_DEL --- 0.452 */SLICE_974.A1 to */SLICE_974.F1 m_DS18B20Z/SLICE_974
ROUTE 1 e 1.030 */SLICE_974.F1 to */SLICE_340.D0 m_DS18B20Z/n10
CTOF_DEL --- 0.452 */SLICE_340.D0 to */SLICE_340.F0 m_DS18B20Z/SLICE_340
ROUTE 1 e 0.001 */SLICE_340.F0 to *SLICE_340.DI0 m_DS18B20Z/one_wire_N_277 (to m_DS18B20Z/clk_1mhz)
--------
5.065 (39.0% logic, 61.0% route), 4 logic levels.
Warning: 32.174MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "sys_clk_c" 103.756000 | | |
MHz ; | 103.756 MHz| 7.421 MHz| 5 *
| | |
FREQUENCY NET "m_uart_tx/clk_en" | | |
112.880000 MHz ; | 112.880 MHz| 12.967 MHz| 11 *
| | |
FREQUENCY NET "m_uart_tx/clk_uart" | | |
203.957000 MHz ; | 203.957 MHz| 27.149 MHz| 5 *
| | |
FREQUENCY NET "m_clock/clk_1ms" | | |
217.297000 MHz ; | 217.297 MHz| 9.016 MHz| 5 *
| | |
FREQUENCY NET "m_clock/clk_500ms" | | |
136.986000 MHz ; | 136.986 MHz| 4.761 MHz| 9 *
| | |
FREQUENCY NET "m_DS18B20Z/clk_1mhz" | | |
293.858000 MHz ; | 293.858 MHz| 32.174 MHz| 4 *
| | |
----------------------------------------------------------------------------
6 preferences(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
n26544 | 3| 4096| 36.05%
| | |
uart_data_120_N_1005_5 | 14| 3698| 32.55%
| | |
m_uart_tx/n26542 | 1| 2668| 23.48%
| | |
m_bcd_8421/n17632 | 2| 2028| 17.85%
| | |
n25294 | 4| 1868| 16.44%
| | |
m_bcd_8421/n25255 | 2| 1814| 15.97%
| | |
m_bcd_8421/n6_adj_1656 | 1| 1740| 15.32%
| | |
n27540 | 6| 1546| 13.61%
| | |
m_bcd_8421/n4_adj_1660 | 1| 1468| 12.92%
| | |
m_OLED12832/n2134 | 4| 1398| 12.31%
| | |
n659 | 269| 1398| 12.31%
| | |
m_bcd_8421/n25059 | 3| 1372| 12.08%
| | |
m_bcd_8421/n6 | 1| 1372| 12.08%
| | |
m_OLED12832/n25765 | 3| 1344| 11.83%
| | |
n27549 | 270| 1296| 11.41%
| | |
m_uart_tx/n4 | 1| 1288| 11.34%
| | |
m_clock/n25024 | 2| 1278| 11.25%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 12 clocks:
Clock Domain: m_DS18B20Z/clk_1mhz Source: m_DS18B20Z/SLICE_145.Q0 Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: sys_clk_c Source: sys_clk.PAD
Covered under: FREQUENCY NET "m_DS18B20Z/clk_1mhz" 293.858000 MHz ; Transfers: 19
Clock Domain: m_DS18B20Z/clk_1mhz Source: m_DS18B20Z/SLICE_145.Q0 Loads: 12
No transfer within this clock domain is found
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0 Loads: 15
No transfer within this clock domain is found
Data transfers from:
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0 Loads: 15
No transfer within this clock domain is found
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0 Loads: 26
No transfer within this clock domain is found
Data transfers from:
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0 Loads: 26
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_uart Source: m_uart_tx/SLICE_311.Q0 Loads: 8
No transfer within this clock domain is found
Data transfers from:
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_uart Source: m_uart_tx/SLICE_311.Q0 Loads: 8
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0 Loads: 18
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0 Loads: 18
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0 Loads: 18
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ;
Data transfers from:
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: sys_clk_c Source: sys_clk.PAD
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 12
Clock Domain: sys_clk_c Source: sys_clk.PAD Loads: 262
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ;
Data transfers from:
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 1
Timing summary (Setup):
---------------
Timing errors: 11361 Score: 577715238
Cumulative negative slack: 577715238
Constraints cover 84154 paths, 61 nets, and 7911 connections (96.11% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) <IP_ADDRESS>.2
Fri Feb 19 19:37:31 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o ds18b20_impl1.tw1 -gui -msgset C:/fpga/ds18b20/promote.xml ds18b20_impl1_map.ncd ds18b20_impl1.prf
Design file: ds18b20_impl1_map.ncd
Preference file: ds18b20_impl1.prf
Device,speed: LCMXO2-4000HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "sys_clk_c" 103.756000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz (0 errors) 208 items scored, 0 timing errors detected.
FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz (0 errors) 1337 items scored, 0 timing errors detected.
FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz (0 errors) 2003 items scored, 0 timing errors detected.
FREQUENCY NET "m_DS18B20Z/clk_1mhz" 293.858000 MHz (0 errors) 59 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "sys_clk_c" 103.756000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_recv/rx_cnt_FSM_i14 (from sys_clk_c +)
Destination: FF Data in m_uart_recv/rx_cnt_FSM_i15 (to sys_clk_c +)
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
Constraint Details:
0.332ns physical path delay SLICE_616 to SLICE_616 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
Physical Path Details:
Data path SLICE_616 to SLICE_616:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_616.CLK to SLICE_616.Q0 SLICE_616 (from sys_clk_c)
ROUTE 1 e 0.199 SLICE_616.Q0 to SLICE_616.M1 m_uart_recv/n593 (to sys_clk_c)
--------
0.332 (40.1% logic, 59.9% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/flag_1_47 (from m_uart_tx/clk_en +)
Destination: FF Data in m_uart_tx/flag_1_47 (to m_uart_tx/clk_en +)
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
Constraint Details:
0.434ns physical path delay m_uart_tx/SLICE_312 to m_uart_tx/SLICE_312 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
Physical Path Details:
Data path m_uart_tx/SLICE_312 to m_uart_tx/SLICE_312:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 *SLICE_312.CLK to */SLICE_312.Q0 m_uart_tx/SLICE_312 (from m_uart_tx/clk_en)
ROUTE 4 e 0.199 */SLICE_312.Q0 to */SLICE_312.A0 m_uart_tx/flag_1
CTOF_DEL --- 0.101 */SLICE_312.A0 to */SLICE_312.F0 m_uart_tx/SLICE_312
ROUTE 1 e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 m_uart_tx/flag_1_N_1248 (to m_uart_tx/clk_en)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
================================================================================
Preference: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ;
208 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_uart_tx/i_i0 (from m_uart_tx/clk_uart +)
Destination: FF Data in m_uart_tx/i_i1 (to m_uart_tx/clk_uart +)
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
Constraint Details:
0.434ns physical path delay m_uart_tx/SLICE_314 to m_uart_tx/SLICE_314 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
Physical Path Details:
Data path m_uart_tx/SLICE_314 to m_uart_tx/SLICE_314:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 *SLICE_314.CLK to */SLICE_314.Q0 m_uart_tx/SLICE_314 (from m_uart_tx/clk_uart)
ROUTE 33 e 0.199 */SLICE_314.Q0 to */SLICE_314.B1 m_uart_tx/i_0
CTOF_DEL --- 0.101 */SLICE_314.B1 to */SLICE_314.F1 m_uart_tx/SLICE_314
ROUTE 1 e 0.001 */SLICE_314.F1 to *SLICE_314.DI1 m_uart_tx/n741 (to m_uart_tx/clk_uart)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
================================================================================
Preference: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ;
1337 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/ms_2276__i3 (from m_clock/clk_1ms +)
Destination: FF Data in m_clock/ms_2276__i3 (to m_clock/clk_1ms +)
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
Constraint Details:
0.434ns physical path delay m_clock/SLICE_74 to m_clock/SLICE_74 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
Physical Path Details:
Data path m_clock/SLICE_74 to m_clock/SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 */SLICE_74.CLK to *k/SLICE_74.Q0 m_clock/SLICE_74 (from m_clock/clk_1ms)
ROUTE 1 e 0.199 *k/SLICE_74.Q0 to *k/SLICE_74.A0 m_clock/n13
CTOF_DEL --- 0.101 *k/SLICE_74.A0 to *k/SLICE_74.F0 m_clock/SLICE_74
ROUTE 1 e 0.001 *k/SLICE_74.F0 to */SLICE_74.DI0 m_clock/n82 (to m_clock/clk_1ms)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
================================================================================
Preference: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ;
2003 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.502ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_clock/hour_set_low__i1 (from m_clock/clk_500ms +)
Destination: FF Data in m_clock/hour_set_low__i1 (to m_clock/clk_500ms +)
Delay: 0.489ns (59.1% logic, 40.9% route), 2 logic levels.
Constraint Details:
0.489ns physical path delay m_clock/SLICE_283 to m_clock/SLICE_283 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.502ns
Physical Path Details:
Data path m_clock/SLICE_283 to m_clock/SLICE_283:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 *SLICE_283.CLK to */SLICE_283.Q0 m_clock/SLICE_283 (from m_clock/clk_500ms)
ROUTE 3 e 0.199 */SLICE_283.Q0 to */SLICE_283.D1 m_clock/hour_set_low_1
CTOOFX_DEL --- 0.156 */SLICE_283.D1 to *LICE_283.OFX0 m_clock/SLICE_283
ROUTE 2 e 0.001 *LICE_283.OFX0 to *SLICE_283.DI0 m_clock/hour_set_high_3_N_1581_1 (to m_clock/clk_500ms)
--------
0.489 (59.1% logic, 40.9% route), 2 logic levels.
================================================================================
Preference: FREQUENCY NET "m_DS18B20Z/clk_1mhz" 293.858000 MHz ;
59 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.763ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q m_DS18B20Z/state_i0_i0 (from sys_clk_c +)
Destination: FF Data in m_DS18B20Z/i140_163 (to m_DS18B20Z/clk_1mhz +)
Delay: 0.750ns (31.2% logic, 68.8% route), 2 logic levels.
Constraint Details:
0.750ns physical path delay m_DS18B20Z/SLICE_172 to m_DS18B20Z/SLICE_171 meets
(delay constraint based on source clock period of 9.638ns and destination clock period of 3.403ns)
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.763ns
Physical Path Details:
Data path m_DS18B20Z/SLICE_172 to m_DS18B20Z/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 *SLICE_172.CLK to */SLICE_172.Q0 m_DS18B20Z/SLICE_172 (from sys_clk_c)
ROUTE 57 e 0.515 */SLICE_172.Q0 to */SLICE_171.C0 m_DS18B20Z/state_0
CTOF_DEL --- 0.101 */SLICE_171.C0 to */SLICE_171.F0 m_DS18B20Z/SLICE_171
ROUTE 1 e 0.001 */SLICE_171.F0 to *SLICE_171.DI0 m_DS18B20Z/one_wire_N_288 (to m_DS18B20Z/clk_1mhz)
--------
0.750 (31.2% logic, 68.8% route), 2 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "sys_clk_c" 103.756000 | | |
MHz ; | 0.000 ns| 0.351 ns| 1
| | |
FREQUENCY NET "m_uart_tx/clk_en" | | |
112.880000 MHz ; | 0.000 ns| 0.447 ns| 2
| | |
FREQUENCY NET "m_uart_tx/clk_uart" | | |
203.957000 MHz ; | 0.000 ns| 0.447 ns| 2
| | |
FREQUENCY NET "m_clock/clk_1ms" | | |
217.297000 MHz ; | 0.000 ns| 0.447 ns| 2
| | |
FREQUENCY NET "m_clock/clk_500ms" | | |
136.986000 MHz ; | 0.000 ns| 0.502 ns| 2
| | |
FREQUENCY NET "m_DS18B20Z/clk_1mhz" | | |
293.858000 MHz ; | 0.000 ns| 0.763 ns| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 12 clocks:
Clock Domain: m_DS18B20Z/clk_1mhz Source: m_DS18B20Z/SLICE_145.Q0 Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: sys_clk_c Source: sys_clk.PAD
Covered under: FREQUENCY NET "m_DS18B20Z/clk_1mhz" 293.858000 MHz ; Transfers: 19
Clock Domain: m_DS18B20Z/clk_1mhz Source: m_DS18B20Z/SLICE_145.Q0 Loads: 12
No transfer within this clock domain is found
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0 Loads: 15
No transfer within this clock domain is found
Data transfers from:
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_clock/clk_500ms" 136.986000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0 Loads: 15
No transfer within this clock domain is found
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0 Loads: 26
No transfer within this clock domain is found
Data transfers from:
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_500ms Source: m_clock/SLICE_279.Q0
Covered under: FREQUENCY NET "m_clock/clk_1ms" 217.297000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0 Loads: 26
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_uart Source: m_uart_tx/SLICE_311.Q0 Loads: 8
No transfer within this clock domain is found
Data transfers from:
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 2
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_uart" 203.957000 MHz ; Transfers: 1
Clock Domain: m_uart_tx/clk_uart Source: m_uart_tx/SLICE_311.Q0 Loads: 8
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0 Loads: 18
No transfer within this clock domain is found
Data transfers from:
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 2
Clock Domain: sys_clk_c Source: sys_clk.PAD
Covered under: FREQUENCY NET "m_uart_tx/clk_en" 112.880000 MHz ; Transfers: 12
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0 Loads: 18
No transfer within this clock domain is found
Clock Domain: m_uart_tx/clk_en Source: m_uart_tx/SLICE_310.Q0 Loads: 18
No transfer within this clock domain is found
Clock Domain: sys_clk_c Source: sys_clk.PAD Loads: 262
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ;
Data transfers from:
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 1
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 5
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Clock Domain: m_clock/clk_1ms Source: m_clock/SLICE_278.Q0
Covered under: FREQUENCY NET "sys_clk_c" 103.756000 MHz ; Transfers: 2
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 84154 paths, 61 nets, and 8103 connections (98.44% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 11361 (setup), 0 (hold)
Score: 577715238 (setup), 0 (hold)
Cumulative negative slack: 577715238 (577715238+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------


--- layout: post status: publish published: true title: "看图说话：很Cool，很帅气" author: Leask author_login: leask author_email<EMAIL_ADDRESS>author_url: https://leaskh.com wordpress_id: 268 wordpress_url: http://leaskh.wordpress.com/2008/03/21/%e7%9c%8b%e5%9b%be%e8%af%b4%e8%af%9d%ef%bc%9a%e5%be%88cool%ef%bc%8c%e5%be%88%e5%b8%85%e6%b0%94 date: '2008-03-21 09:18:04 +0800' date_gmt: '2008-03-21 09:18:04 +0800' categories: tags: [] comments: [] ---


Store page data in browser
Client side database with indexes
3 ways to through which APIs are exposed
Geocoding
https://geocode.xyz/api
Maps
https://yandex.github.io/mapsapi-examples-old/
You can find more in google


Create
Create
Step 1:
Choose a Reddit Joke
Step 2:
Choose a Flickr Image
Step 3:
Finalize Your Meme
Selected Joke:
Submit


| Package | Description |
|---|---|
| org.apache.olingo.client.api.edm.xml | |
| org.apache.olingo.client.api.serialization | |
| org.apache.olingo.commons.api.edm.provider |
Contains representations for objects created during CSDL document parsing
|
| org.apache.olingo.commons.api.edm.provider.annotation |
Contains representations for objects created during
CSDL document parsing related to the CSDL annotations.
|
| org.apache.olingo.commons.api.edmx |
Olingo Server API - Edmx
|
| org.apache.olingo.netty.server.core | |
| org.apache.olingo.server.api |
Olingo Server API
|
| Class and Description |
|---|
| CsdlAnnotatable
Super type of all annotatable CSDL items
|
| CsdlSchema
The type Csdl schema.
|
| Class and Description |
|---|
| CsdlSchema
The type Csdl schema.
|
| Class and Description |
|---|
| CsdlAbstractEdmItem
Super type of all CsdlEdmItems
|
| CsdlAction
Represents an action CSDL item
|
| CsdlActionImport
Represents an action import CSDL item
|
| CsdlAliasInfo
Represents an alias info CSDL item
|
| CsdlAnnotatable
Super type of all annotatable CSDL items
|
| CsdlAnnotation
Represents a CSDL annotation
|
| CsdlAnnotations
The type Csdl annotations.
|
| CsdlBindingTarget
The type Csdl binding target.
|
| CsdlComplexType
The type Csdl complex type.
|
| CsdlEdmProvider
The interface Csdl edm provider.
|
| CsdlEntityContainer
The type Csdl entity container.
|
| CsdlEntityContainerInfo
The type Csdl entity container info.
|
| CsdlEntitySet
The type Csdl entity set.
|
| CsdlEntitySetPath
The type Csdl entity set path.
|
| CsdlEntityType
The type Csdl entity type.
|
| CsdlEnumMember
The type Csdl enum member.
|
| CsdlEnumType
The type Csdl enum type.
|
| CsdlFunction
The type Csdl function.
|
| CsdlFunctionImport
The type Csdl function import.
|
| CsdlMapping
Content of this class does not appear within the CSDL metadata document.
|
| CsdlNamed
The interface Csdl named.
|
| CsdlNavigationProperty
The type Csdl navigation property.
|
| CsdlNavigationPropertyBinding
The type Csdl navigation property binding.
|
| CsdlOnDelete
The type Csdl on delete.
|
| CsdlOnDeleteAction
The enum Csdl on delete action.
|
| CsdlOperation
The type Csdl operation.
|
| CsdlOperationImport
The type Csdl operation import.
|
| CsdlParameter
The type Csdl parameter.
|
| CsdlProperty
The type Csdl property.
|
| CsdlPropertyRef
The type Csdl property ref.
|
| CsdlReferentialConstraint
The type Csdl referential constraint.
|
| CsdlReturnType
The type Csdl return type.
|
| CsdlSchema
The type Csdl schema.
|
| CsdlSingleton
The type Csdl singleton.
|
| CsdlStructuralType
The type Csdl structural type.
|
| CsdlTerm
The type Csdl term.
|
| CsdlTypeDefinition
The type Csdl type definition.
|
| Class and Description |
|---|
| CsdlAbstractEdmItem
Super type of all CsdlEdmItems
|
| CsdlAnnotatable
Super type of all annotatable CSDL items
|
| CsdlAnnotation
Represents a CSDL annotation
|
| Class and Description |
|---|
| CsdlAnnotatable
Super type of all annotatable CSDL items
|
| CsdlAnnotation
Represents a CSDL annotation
|
| Class and Description |
|---|
| CsdlEdmProvider
The interface Csdl edm provider.
|
| Class and Description |
|---|
| CsdlEdmProvider
The interface Csdl edm provider.
|
Copyright © 2013–2018 The Apache Software Foundation. All rights reserved.


112 Properties
| Lot | Location | Postcode | Price | Legal Pack | Save |
|---|---|---|---|---|---|
| 1 | 9 Zetland Road, Allerton, Liverpool | L18 1HF | Guide Price: £90,000+* |
|
|
| 2 | 61a Linaker Street, Southport, Merseyside | PR8 5DQ | Guide Price: £45,000+* |
|
|
| 3 | 28 Markby Road, Birmingham | B18 4PW | Sold Prior | Save | |
| 4 | 58 Yew Tree Road, Walton, Liverpool | L9 1AL | Postponed | Save | |
| 5 | 8 Kipling Street, Bootle, Merseyside | L20 4QE | Guide Price: £35,000+* | Save | |
| 6 | 82 Cannock Road, Cannock, Staffordshire | WS11 5BY | Guide Price: £75,000+* |
|
|
| 7 | 16 Luxmore Road, Liverpool | L4 5TQ | Guide Price: £57,000+* | Save | |
| 8 | The Cottage, Rhiw, Pwllheli, Gwynedd | LL53 8AE | Guide Price: £36,000+* | Save | |
| 9 | 2 Ruscombe Road, Liverpool | L14 4AU | Guide Price: £50,000 - £55,000* |
|
|
| 10 | 357 Walton Lane, Liverpool | L4 5RL | Guide Price: £45,000+* | Save | |
| 11 | 75 Preston Road, Hockley, Birmingham | B18 4PL | Sold Prior |
|
|
| 12 | 26 Grasmere Street, Liverpool | L5 6RH | Guide Price: £40,000+* |
|
|
| 13 | Land At 2 Dorset Road, Tuebrook, Liverpool | L6 4DX | Guide Price: £15,000+* | Save | |
| 14 | 43 Wolfenden Avenue, Bootle, Merseyside | L20 0AY | Withdrawn | Save | |
| 15 | 43 Guernsey Road, Old Swan, Liverpool | L13 6RN | Guide Price: £100,000+* | Save | |
| 16 | 8 Heald Street, Garston, Liverpool | L19 2LY | Guide Price: £80,000+* | Save | |
| 17 | 25 Harebell Street, Liverpool | L5 7RL | Guide Price: £35,000 - £40,000* | Save | |
| 18 | 231a Lower House Lane, Liverpool | L11 2SF | Guide Price: £25,000+* | Save | |
| 19 | 48 Adswood Road, Huyton, Liverpool | L36 7XP | Guide Price: £65,000+* |
|
|
| 20 | 2 Bracken Walk, Kirkby, Liverpool | L32 5SR | Sold Prior | Save | |
| 21 | Land To The Rear Of 2 Hall Lane, Huyton, Liverpool | L36 6AZ | Withdrawn | Save | |
| 22 | 34 Litherland Road, Bootle, Merseyside | L20 3HZ | Guide Price: £52,000+* |
|
|
| 23 | 12 Ullet Road, Liverpool | L8 3SR | Guide Price: £850,000+* | Save | |
| 24 | 62 Cowley Street, St. Helens, Merseyside | WA10 2SW | Guide Price: £35,000+* | Save | |
| 25 | 21 Laburnum Road, Fairfield, Liverpool | L7 0HT | Guide Price: £70,000+* |
|
|
| 26 | 14/14a Rock Lane West, Birkenhead, Merseyside | CH42 1RE | Guide Price: £75,000+* | Save | |
| 27 | 12 Ovolo Road, Old Swan, Liverpool | L13 3DR | Sold Prior | Save | |
| 28 | 2 Prospect Vale, Fairfield, Liverpool | L6 8PG | Guide Price: £180,000+* | Save | |
| 29 | 92-94 Hale Road, Walton, Liverpool | L4 3RW | Guide Price: £65,000+* | Save | |
| 30 | 4 Priory Road, Liverpool | L4 2RY | Guide Price: £65,000+* | Save | |
| 31 | 3 Shelley Street, Bootle, Merseyside | L20 4LG | Guide Price: £35,000 - £40,000* | Save | |
| 32 | 25 Chapel Road, Garston, Liverpool | L19 2LE | Guide Price: £65,000+* | Save | |
| 33 | 64 Black Bull Lane, Fulwood, Preston | PR2 3JX | Sold Prior | Save | |
| 34 | 15 Victoria Court & Garage 4, 5-7 Parkfield Road, Aigburth | L17 8UL | Guide Price: £62,000+* | Save | |
| 35 | 16 Frodsham Street, Liverpool | L4 5XA | Guide Price: £35,000 - £40,000* |
|
|
| 36 | 94 Gloucester Road North, Liverpool | L6 4DT | Guide Price: £35,000+* | Save | |
| 37 | 48 Henrietta Street, Leigh, Lancashire | WN7 1LJ | Guide Price: £35,000 - £40,000* | Save | |
| 38 | 26 Aigburth Hall Road, Liverpool | L19 9EE | Guide Price: £110,000+* | Save | |
| 39 | 275/275a Hawthorne Road, Bootle, Merseyside | L20 3AP | Guide Price: £50,000+* | Save | |
| 40 | 54 Thirlmere Road, Everton, Liverpool | L5 6PP | Guide Price: £40,000 - £45,000* |
|
|
| 41 | 23a Hardshaw Street, Eccleston, St. Helens, Merseyside | WA10 1RT | Guide Price: £150,000+* | Save | |
| 42 | 209 Lower House Lane, Liverpool | L11 2SF | Guide Price: £65,000+* | Save | |
| 43 | 619 And 619a Prescot Road, Old Swan, Liverpool | L13 5XA | Guide Price: £135,000+* | Save | |
| 44 | 26 Bartlett Street, Liverpool | L15 0HW | z |
|
|
| 45 | 14 Nutgrove Avenue, St. Helens, Merseyside | WA9 5LT | Guide Price: £45,000+* |
|
|
| 46 | 38 Long Lane, Wavertree, Liverpool | L15 4HF | Guide Price: £80,000+* | Save | |
| 47 | 45 Handfield Street, Liverpool | L5 6PE | Guide Price: £30,000 - £35,000* | Save | |
| 48 | 36 Mildmay Road, Bootle, Merseyside | L20 5EN | Guide Price: £45,000+* |
|
|
| 49 | 374 Prescot Road, Old Swan, Liverpool | L13 3AP | Guide Price: £40,000+* |
|
|
| 50 | 30 Emery Street, Liverpool | L4 5UZ | Guide Price: £30,000 - £35,000* |
|
|
| 51 | 14 Orange Grove, Liverpool | L8 0TD | Guide Price: £50,000 - £60,000* | Save | |
| 52 | 27 Rydal Street, Liverpool | L5 6QP | Guide Price: £35,000 - £40,000* |
|
|
| 53 | The Beresford Arms, 158 Beresford Road, Liverpool | L8 4SQ | Postponed | Save | |
| 54 | 18 Pansy Street, Liverpool | L5 7RS | Guide Price: £30,000 - £35,000* | Save | |
| 55 | Flat 1 & 2, 112 Hawthorne Road, Bootle, Merseyside | L20 9JY | Guide Price: £60,000+* | Save | |
| 56 | 19 Washway Lane, St. Helens, Merseyside | WA11 9LL | Guide Price: £65,000+* | Save | |
| 57 | 39 Elmfield, Shevington, Wigan, Lancashire | WN6 8DL | Guide Price: £140,000+* | Save | |
| 58 | Flat 1a, 40-42 Sydenham Avenue, Liverpool | L17 3AX | Guide Price: £45,000+* | Save | |
| 59 | Flat 1b, 40-42 Sydenham Avenue, Liverpool | L17 3AX | Guide Price: £55,000+* | Save | |
| 60 | 98 Fieldton Road, Liverpool | L11 9AQ | Guide Price: £40,000+* | Save | |
| 61 | 111 Beatrice Street, Bootle, Merseyside | L20 2EG | Guide Price: £35,000 - £40,000* |
|
|
| 62 | 51 Holbeck Street, Liverpool | L4 2UR | Guide Price: £27,000+* | Save | |
| 63 | 14 Redcar Street, Liverpool | L6 0AJ | Guide Price: £35,000+* |
|
|
| 64 | 50 Grasmere Street, Liverpool | L5 6RJ | Guide Price: £40,000+* | Save | |
| 65 | Flat 2 Princes Court, 6 Croxteth Road, Liverpool | L8 3UJ | Sold Prior | Save | |
| 66 | 27 Sunningdale Road, Liverpool | L15 4HJ | Guide Price: £55,000+* | Save | |
| 67 | 31 Wendell Street, Liverpool | L8 0RG | Guide Price: £35,000+* |
|
|
| 68 | 114 Bridge Road, Litherland, Liverpool | L21 8NT | Sold Prior | Save | |
| 69 | 15 Derwent Street, Stoke-on-trent | ST1 5EN | Sold Prior | Save | |
| 70 | Flat 2, 16 Alexandra Drive, Liverpool | L17 8TD | Guide Price: £55,000+* |
|
|
| 71 | 13 Station Road, Haydock, St. Helens, Merseyside | WA11 0JJ | Guide Price: £45,000 - £50,000* | Save | |
| 72 | 36 Bannerman Street, Liverpool | L7 6JP | Guide Price: £50,000+* |
|
|
| 73 | Coach Houses 9 & 10, Hollystead House, 14 Old Mill Lane | L15 8LN | Postponed | Save | |
| 74 | 45 Creswell Street, St. Helens, Merseyside | WA10 2PN | Guide Price: £30,000 - £35,000* | Save | |
| 75 | 45 Raglan Street, Ashton-on-ribble, Preston | PR2 2AX | Guide Price: £40,000+* | Save | |
| 76 | 77 Fieldton Road, Liverpool | L11 9AF | Guide Price: £45,000+* | Save | |
| 77 | 38 Butterfield Street, Liverpool | L4 4HT | Sold Prior | Save | |
| 78 | 26 Mill Lane, Old Swan, Liverpool | L13 5TF | Guide Price: £60,000+* |
|
|
| 79 | 20 Stockbridge Street, Liverpool | L5 6PB | Guide Price: £30,000 - £35,000* | Save | |
| 80 | 34 Elm Grove, Birkenhead, Merseyside | CH42 0LA | Guide Price: £80,000+* | Save | |
| 81 | 110 Alwyn Street, Aigburth, Liverpool | L17 7DY | Guide Price: £100,000+* | Save | |
| 82 | Ruthlyn, 21 Woodfield Road, Blackpool | FY1 6AX | Guide Price: £80,000+* | Save | |
| 83 | 60 Ripon Street, Liverpool | L4 5UQ | Guide Price: £30,000+* | Save | |
| 84 | 77 September Road, Liverpool | L6 4DG | Guide Price: £50,000 - £55,000* |
|
|
| 85 | 95 Tiverton Street, Wavertree, Liverpool | L15 4LR | Guide Price: £70,000+* | Save | |
| 86 | 52 Holmes Street, Liverpool | L8 0RJ | Guide Price: £25,000 - £30,000* | Save | |
| 87 | 76 Gladstone Street, St. Helens, Merseyside | WA10 4NR | Guide Price: £35,000 - £40,000* | Save | |
| 88 | 96 Newcombe Road, Birmingham | B21 8BY | Sold Prior | Save | |
| 89 | 39 Ellesmere Road, Blackpool | FY4 3DH | Guide Price: £60,000+* | Save | |
| 90 | 2 The Parade, Northway, Wavertree, Liverpool | L15 7JU | Guide Price: £110,000+* | Save | |
| 91 | 34 Alfonso Road, Liverpool | L4 1UH | Guide Price: £35,000 - £40,000* | Save | |
| 92 | 20 Gladstone Street, St. Helens, Merseyside | WA10 4NT | Guide Price: £35,000 - £40,000* | Save | |
| 93 | 10 Warton Street, Bootle, Merseyside | L20 4PX | Guide Price: £37,000+* | Save | |
| 94 | 22 Woolrich Street, Stoke-on-trent | ST6 3PQ | Guide Price: £40,000+* | Save | |
| 95 | 72 Gleave Road, Selly Oak, Birmingham | B29 6JN | Sold Prior |
|
|
| 96 | 31 Botanic Road, Liverpool | L7 5PX | Sold Prior | Save | |
| 97 | 97 Botanic Road, Liverpool | L7 5PY | Sold Prior | Save | |
| 98 | 115 Botanic Road, Liverpool | L7 5PY | Sold Prior | Save | |
| 99 | 125 Botanic Road, Liverpool | L7 5PZ | Sold Prior | Save | |
| 100 | 8 Huntley Road, Liverpool | L6 3AJ | Sold Prior | Save | |
| 101 | 10 Huntley Road, Liverpool | L6 3AJ | Guide Price: £135,000+* | Save | |
| 102 | 63/69 Mason St, 31/33 Grinfield St And 70/72 Highgate St, Lpool | L7 | Guide Price: £900,000+* | Save | |
| 103 | 21 Garages To The Rear Of 116-164 Woolton Road, Allerton | L19 5NH | Guide Price: £100,000+* |
|
|
| 104 | 31 Newenham Crescent, Liverpool | L14 7PR | Guide Price: £65,000+* |
|
|
| 105 | Flat 3, 39 Rossett Road, Liverpool | L23 3AN | Sold Prior |
|
|
| 106 | 12 Denton Grove, Liverpool | L6 4AJ | Guide Price: £45,000+* | Save | |
| 107 | 62 Church Road West, Liverpool | L4 5UF | Guide Price: £350,000+* | Save | |
| 108 | 164 Muirhead Avenue East, Liverpool | L11 1EW | Sold Prior |
|
|
| 109 | 58 Hannan Road, Kensington, Liverpool | L6 6DB | Sold Prior | Save | |
| 110 | Former Mailing Centre, Orrell Mount, Bootle, Merseyside | L20 6NS | Sold Prior | Save | |
| 111 | 17 Valeway Avenue, Thornton-cleveleys, Lancashire | FY5 3ER | Guide Price: £100,000+* | Save | |
| 112 | 95 Snowberry Road, Liverpool | L14 8XN | Guide Price: £40,000+* | Save | |


Charts New Releases Podcasts & Videos Discover Concerts
Genre & Mood
FOLLOW
1,023 FOLLOWERS・BY UNKNOWN AUTHOR
Though the author is unknown, this playlist offers the best music can offer, from relaxing tracks to tracks that will make you get on your fit and jump as much as you can! Enjoy ^_^


AsyncAction
public protocol AsyncAction: Action
Protocol that represents an async
action.
An AsyncAction
is just an abstraction over Action
that provides a way to structure
your action.
You typically use an Async
action when you have to deal with operations that are asynchronous.
In the most common scenario, you dispatch the initial action, execute an operation in the side effect
and then dispatch a completed/failed action based on the result of the operation.
This protocol offers two main advantages:
The way in which the action payloads are defined is enforced. We introduced this pattern to allow future automatic behaviours such as automatic serialization/deserialization of the actions (that can be used for debugging, time travel and so on)
Convenient separation of the updateStae function based on the state of the action (
updatedStateForLoading(currentState: action:)
,updatedStateForCompleted(currentState: action:)
andupdatedStateForFailed(currentState: action:)
)
It is important to note that this is just a a convenience approach to something you can do anyway.
You can for instance create three actions: performOperation
, OperationCompleted
and OperationFailed
and achieve
the same result. AsyncAction
just provide a way to abstract and simplify the process
Tip & Tricks
Since the Action
protocol is very generic when it comes to the state type that should be updated, a pattern
we want to promote is to put in your application a protocol like the following:
protocol AppSyncAction: AsyncAction {
func updatedStateForLoading(currentState: inout AppState)
// same for completed and failed
}
extension AppSyncAction {
func updatedStateForLoading(currentState: State) -> State {
guard var state = state as? AppState else {
fatalError("Something went wrong")
}
self.updatedStateForLoading(currentState: &state)
return state
}
// same for completed and failed
}
In this way you can save a lot of code since you can use your actions in the following way
struct A: AppAsyncAction {
func updatedStateForLoading(currentState: inout AppState) {
state.props = action.payload
}
// same for completed and failed
}
-
The state of the action
Declaration
Swift
var state: AsyncActionState
-
The type of payload when the state is
loading
Declaration
Swift
associatedtype LoadingPayload
-
The type of payload when the state is
completed
Declaration
Swift
associatedtype CompletedPayload
-
The type of payload when the state is
failed
Declaration
Swift
associatedtype FailedPayload
-
The loading payload of the action
Declaration
Swift
var loadingPayload: LoadingPayload
-
The completed payload of the action. It has a value only when the state is
completed
Declaration
Swift
var completedPayload: CompletedPayload?
-
The failed payload of the action. It has a value only when the state is
failed
Declaration
Swift
var failedPayload: FailedPayload?
-
UpdateState function that will be used when the state of the action is
loading
Parameters
state
the current state of the application
Return Value
the new state
-
UpdateState function that will be used when the state of the action is
completed
Parameters
state
the current state of the application
Return Value
the new state
-
UpdateState function that will be used when the state of the action is
failed
Parameters
state
the current state of the application
Return Value
the new state
-
Creates a new action
Declaration
Swift
init(payload: LoadingPayload)
Parameters
payload
the payload to assign to the action
Return Value
an instance of the action where the state must be
loading
-
completedAction(payload:)
Default implementationCreates a new action in the
completed
stateDefault Implementation
Creates a new action in the
completed
stateDeclaration
Swift
func completedAction(payload: CompletedPayload) -> Self
Parameters
payload
the payload of the completed action
Return Value
a new instance of the action, where the state is
completed
. This new action will have the loading payload inerithed from the initial loading action and the provided completed payload -
failedAction(payload:)
Default implementationCreates a new action in the
failed
stateDefault Implementation
Creates a new action in the
failed
stateDeclaration
Swift
func failedAction(payload: FailedPayload) -> Self
Parameters
payload
the payload of the failed action
Return Value
a new instance of the action, where the state is
failed
. This new action will have the loading payload inerithed from the initial loading action and the provided failed payload
-
updatedState(currentState:)
Extension methodCreates a new state starting from the current state and the dispatched action.
AsyncAction
implements a default behaviour that invokesupdatedStateForLoading(currentState:)
,updatedStateForCompleted(currentState:)
orupdatedStateForFailed(currentState:)
based on the action’s stateParameters
state
the current state
Return Value
the new state
-
anySideEffect(state:dispatch:dependencies:)
Extension methodImplementation of the
ActionWithSideEffect
type erasure. We don’t invoke the side effect if the state of the action is not loading. This is because we want to trigger side effects only during the loading phase.Declaration
Swift
func anySideEffect(state: State, dispatch: @escaping StoreDispatch, dependencies: SideEffectDependencyContainer)


A player can submit as many rounds as they like, only their lowest 2 scores will count.
Side rules/notes:
- 2 People minimum per card - one must be a Borderland TC player.
- 3 People or more on card - if none of the players were on a Borderland TC before.
- Not all scores needed to be counted for any given round on any given card. Only those who wish to submit can.
- Rounds must be submitted with name, score, layout and who was on card. You can submit a round to either Jon or Tom directly or through the form on thr right.
- scores will be rounded to nearest hundredth
- Should there be a need for a tie breaker for the last roster spot(s) it will be decided by a 1 round playoff. Layout determined at random on the day of the playoff.


Its like irb with super powers
gem install pry pry-doc
ruby -e 'puts $:'
gem environment
or bundle show [gemname]
inside your rails application
rake --tasks
rake routes
or http://localhost:3000/rails/info/routes
during development in your browser
I wanted to generate some random data for an app I was testing so I opted to use the ffaker gem. I found out it was easier than I expected. All you have to do is to include the gem, possibly the version and then require the gem afterwards.
gem 'ffaker' # You don't need this line to use in pry/irb
require 'ffaker'
#### profit
10.times do
puts FFaker::Name.first_name
end
Its a lot nicer than the default error display in rails
group :development do
gem "better_errors"
end


Ron Swanson
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Ron Swanson
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Ron Swanson
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Ron Swanson
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