As you know, the fall season brings out a whole different batch of seasonal items. We are now offering specials on Alaskan King Crab legs and fresh Rock Lobster tails. With Thanksgiving and Christmas dinners in mind, we are also accepting orders on our specialty items such as "coon", frog legs, and more. Please be sure to ask us for details.
TOPSummer is always fun. Don't forget, if you're out on the lakes enjoying this great weather, catching a few fish, and you don't feel like cleaning them yourself... we offer that service to our customers! Bring in your catch and tell us what you want done and we'll do the rest. While you're here, you can order some fries, hushpuppies, desserts or anything else from our showcase.
And for those that didn't catch anything, you buy and we fry and we'll vouch for you that you did all the hard work! We even have Ocean Perch fillets!
The ice is melting and the bass are starting to run. Go get your fishing licenses renewed and join the fun!
TOP


PART II. PROGRAM FOR SEED CAPITAL ASSISTANCE
[§211F-21] Establishment. The corporation shall establish a program for seed capital assistance. [L 1990, c 110, pt of §3]


UFC 244 Preview And Picks: The Deck Is Stacked Against Darren Till
by Trent ReinsmithIn June, UFC president Dana White admitted that in hindsight, the promotion might have pushed Darren Till too far, too fast. “I think Till went back to the drawing board. He’s a young guy and after the win over (Donald) ‘Cowboy’ (Cerrone) we might have pushed him a little too soon,” White told ESPN in June. “It happens sometimes when a guy gets that much steam behind him and pump the brakes a little here. Let him get back and work on things that he needs to work on and he’s going to be around.
 That weight division is nasty. It’s like murderer’s row in that top eight. So we’ll give him some time, look for a next opponent and see what’s next for him.”
White’s remarks came after Till had been submitted by Tyron Woodley in September 2018 and knocked out by Jorge Masvidal in March of this year.
Till, who had struggled to make welterweight, decided to move to middleweight after White commented on his plight. However, Till did not want a step down in competition to go with his step up in weight. With that, Till pursed a fight against Kelvin Gastelum, who is coming off a five-round decision loss to Israel Adesanya. Adesanya earned the interim middleweight title with his victory over Gastelum and would go on to win the undisputed title with a knockout of Robert Whittaker in October. Gastelum is currently the No. 4 ranked fighter in the 185-pound division.
If the matchup, which is the co-main event of Saturday’s UFC 244 pay-per-view card, isn’t tough enough for Till, he was thrown an additional curveball during fight week. Till had issues with his visa and it seems as if he will not have a lot of time to deal with his weight cut. The UFC has scratched Till from Thursday’s media day and said he will be available following Friday’s ceremonial weigh-ins. The news of Till’s issues with his visa were first reported by @TalkMMA.
There’s also the fact that Till could earn a title shot with a win on Saturday. Paulo Costa, who seemed to be in line for a shot at the middleweight title, will be out until spring after he suffered a setback while recovering from bicep surgery according to MMA Fighting.
If Till wanted to show the UFC he can overcome adversity, a victory on Saturday will go a long way toward making that point.
UFC 244 takes place Saturday at New York's Madison Square Garden. The pay-per-view card airs on ESPN+ following prelims on ESPN2 and ESPN+.
Pick: Gastelum
More From UFC 244:


| This field indicates the TX buffer pointer status flag. | ||
| When CPU writes data into SC_DAT, TXPOINT increases one. | ||
| When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one. | ||
| [29] | TXRERR | Transmitter Retry Error (Read Only) |
| This bit is set by hardware when transmitter re-transmits. | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2 This bit is a flag and cannot generate any interrupt to CPU. | ||
| [30] | TXOVERR | Transmitter Over Retry Error (Read Only) |
| This bit is set by hardware when transmitter re-transmits over retry number limitation. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [31] | TXACT | Transmit In Active Status Flag (Read Only) |
| 0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed. | ||
| 1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted. |
Definition at line 21569 of file NUC472_442.h.
| __IO uint32_t SPI_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUSY | Busy Status (Read Only) |
| 0 = SPI controller is in Idle state. | ||
| 1 = SPI controller is in busy state. | ||
| The following listing are the bus busy conditions: | ||
| *. SPIEN = 1 and the TXEMPTY = 0. | ||
| *. For SPI Master, the TXEMPTY = 1 but the current transaction is not finished yet. | ||
| *. For SPI Slave receive mode, the SPIEN = 1 and there is serial clock input into the SPI core logic when slave select is active. | ||
| *. For SPI Slave transmit mode, the SPIEN = 1 and the transmit buffer is not empty in SPI core logic even if the slave select is inactive. | ||
| [1] | UNITIF | Unit Transfer Interrupt Status |
| 0 = No transaction has been finished since this bit was cleared to 0. | ||
| 1 = SPI controller has finished one unit transfer. | ||
| Note: This bit will be cleared by writing 1 to it. | ||
| [2] | SSACTIF | Slave Select Active Interrupt Status |
| 0 = Slave select active interrupt is clear or not occur. | ||
| 1 = Slave select active interrupt event occurred. | ||
| Note: This bit will be cleared by writing 1 to it. | ||
| [3] | SSINAIF | Slave Select Inactive Interrupt Status |
| 0 = Slave select inactive interrupt is clear or not occur. | ||
| 1 = Slave select inactive interrupt event occurred. | ||
| Note: This bit will be cleared by writing 1 to it. | ||
| [4] | SSLINE | Slave Select Line Bus Status (Read Only) |
| 0 = Indicates the slave select line bus status is 0. | ||
| 1 = Indicates the slave select line bus status is 1. | ||
| Note: If SSACTPOL, SPI_SSCTL[2], is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. | ||
| [5] | SLVTOIF | Slave Time-Out Interrupt Status |
| 0 = Slave time-out is not active. | ||
| 1 = Slave time-out is active. | ||
| Note1: If the DWIDTH is set 16, one transaction is equal 16 bits bus clock period. | ||
| This bit will be cleared by writing 1 to it. | ||
| Note2: When the Slave Select is active and the value of SLVTOCNT is not 0 and the busclock input, the slave time-out counter in SPI controller logic will be start. | ||
| When the value of time-out counter greater or equal than the value of SLVTOCNT, SPI_SSCTL[31:16], during before one transaction done, the slave time-out interrupt event will active. | ||
| [6] | SLVBEIF | Slave Mode Error 0 Interrupt Status |
| 0 = No Slave mode error 0 event. | ||
| 1 = Slave mode error 0 occurs. | ||
| Note1: If the slave select active but there is no any bus clock input, the SLVER0_INTSTS also active when the slave select goes to inactive state. | ||
| This bit will be cleared by writing 1 to it. | ||
| Note2: In Slave mode, there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state. | ||
| [7] | SLVURIF | Slave Mode Error 1 Interrupt Status |
| 0 = No Slave mode error 1 event. | ||
| 1 = Slave mode error 1 occurs. | ||
| Note: In Slave mode, transmit under-run occurs when the slave select line goes to inactive state. | ||
| This bit will be cleared by writing 1 to it. | ||
| [8] | RXEMPTY | Receive FIFO Buffer Empty Indicator (Read Only) |
| 0 = Receive FIFO buffer is not empty. | ||
| 1 = Receive FIFO buffer is empty. | ||
| [9] | RXFULL | Receive FIFO Buffer Empty Indicator (Read Only) |
| 0 = Receive FIFO buffer is not empty. | ||
| 1 = Receive FIFO buffer is empty. | ||
| [10] | RXTHIF | Receive FIFO Threshold Interrupt Status (Read Only) |
| 0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH. | ||
| 1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. | ||
| Note: If RX_INTEN = 1 and RX_INTSTS = 1, the SPI controller will generate a SPI interrupt request. | ||
| [11] | RXOVIF | Receive FIFO Overrun Status |
| 0 = No FIFO over-run event. | ||
| 1 = FIFO over-run event occurred. | ||
| Note: When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. | ||
| This bit will be cleared by writing 1 to it. | ||
| [12] | RXTOIF | Receive Time-Out Interrupt Status |
| 0 = No receive FIFO time-out event. | ||
| 1 = FIFO time-out event occurred. | ||
| Note: Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode. | ||
| When the received FIFO buffer is read by software, the time-out status will be cleared automatically. | ||
| This bit will be cleared by writing 1 to it. | ||
| [15] | SPIENSTS | SPI Enable Bit Status (Read Only) |
| 0 = Indicates the transmit control bit is disabled. | ||
| 1 = Indicates the transfer control bit is active. | ||
| Note: The clock source of SPI controller logic is peripheral clock, it is asynchronous with the system clock. | ||
| In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN in SPI controller logic for user. | ||
| [16] | TXEMPTY | Transmit FIFO Buffer Empty Indicator (Read Only) |
| 0 = Transmit FIFO buffer is not empty. | ||
| 1 = Transmit FIFO buffer is empty. | ||
| [17] | TXFULL | Transmit FIFO Buffer Full Indicator (Read Only) |
| 0 = Transmit FIFO buffer is not full. | ||
| 1 = Transmit FIFO buffer is full. | ||
| [18] | TXTHIF | Transmit FIFO Threshold Interrupt Status (Read Only) |
| 0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. | ||
| 1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. | ||
| Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request. | ||
| [19] | TXUFIF | Transmit FIFO Under-Run Interrupt Status |
| 0 =No under-run interrupt event. | ||
| 1 = Under-run interrupt occurred. | ||
| Note: When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input , the output data depends on the setting of SLVUDFPOL and this bit will be set to 1 and this bit will be cleared by writing 1 to it. | ||
| [23] | TXRXRST | FIFO CLR Status (Read Only) |
| 0 = Done the FIFO buffer clear function of TXRST or RXRST. | ||
| 1 = Doing the FIFO buffer clear function of TXRST or RXRST. | ||
| Note: Both the TXRST, RXRST, need 3 system clock + 3 peripheral clock , the status of this bit support the user to monitor the clear function is doing or done. | ||
| [24:27] | RXCNT | Receive FIFO Data Count (Read Only) |
| This bit field indicates the valid data count of receive FIFO buffer. | ||
| [28:31] | TXCNT | Transmit FIFO Data Count (Read Only) |
| This bit field indicates the valid data count of transmit FIFO buffer. |
Definition at line 23019 of file NUC472_442.h.
| __IO uint32_t WWDT_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WWDTIF | WWDT Compare Match Interrupt Flag |
| This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT value. | ||
| 0 = No effect. | ||
| 1 = WWDT counter value matches CMPDAT value. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [1] | WWDTRF | WWDT Timer-Out Reset Flag |
| This bit indicates the system has been reset by WWDT time-out reset or not. | ||
| 0 = WWDT time-out reset did not occur. | ||
| 1 = WWDT time-out reset occurred. | ||
| Note: This bit is cleared by writing 1 to it. |
Definition at line 28645 of file NUC472_442.h.
| __IO uint32_t ADC_T::STATUS0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADIF | ADC Interrupt Flag |
| A status flag that indicates the end of A/D conversion. | ||
| ADIF (ADC_STATUS0[0]) is set to 1 at these two conditions: | ||
| 1. When A/D conversion ends in Single mode | ||
| 2. When A/D conversion ends on all specified channels in Scan mode | ||
| Note: This flag can be cleared by writing 1 to it. | ||
| [1] | ADCMPF0 | Compare Flag |
| When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. | ||
| And it is cleared by writing 1 to self. | ||
| 0 = Conversion result in ADC_DATx does not meet ADCMPR0 setting. | ||
| 1 = Conversion result in ADC_DATx meets ADCMPR0 setting. | ||
| [2] | ADCMPF1 | Compare Flag |
| When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. | ||
| And it is cleared by writing 1 to self. | ||
| 0 = Conversion result in ADC_DATx does not meet ADCMPR1 setting. | ||
| 1 = Conversion result in ADC_DATx meets ADCMPR1 setting. | ||
| [3] | BUSY | BUSY/IDLE (Read Only) |
| 0 = ADC is in idle state. | ||
| 1 = ADC is doing conversion. | ||
| This bit is mirror of as SWTRG (ADC_CTL[11]) bit. | ||
| [4:7] | CHANNEL | Current Conversion Channel (Read Only) |
| This field reflects the current conversion channel when BUSY (ADC_STATUS0[3]) = 1. | ||
| When BUSY (ADC_STATUS0[3]) = 0, it shows the number of the next converted channel. |
Definition at line 572 of file NUC472_442.h.
| __I uint32_t EADC_T::STATUS0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | VALID7_0 | ADDR07~ ADDR00 Data Valid Flag (Read Only) |
| It is a mirror of VALID bit in SAMPLE0 A/D result data register EADC_AD0DAT0x. | ||
| Note: x = 0~7. | ||
| [8:15] | VALID15_8 | ADDR17~ ADDR10 Data Valid Flag (Read Only) |
| It is a mirror of VALID bit in SAMPLE1 A/D result data register EADC_AD0DAT1x. | ||
| Note: x = 0~7. | ||
| [16:23] | OV7_0 | ADDR07~ ADDR00 Overrun Flag (Read Only) |
| It is a mirror to OV bit in SAMPLE0 A/D result data register EADC_AD0DAT0x. | ||
| Note: x = 0~7. | ||
| [24:31] | OV15_8 | ADDR17~ADDR10 Overrun Flag (Read Only) |
| It is a mirror to OV bit in SAMPLE1 A/D result data register EADC_AD0DAT1x. | ||
| Note: x = 0~7. |
Definition at line 8773 of file NUC472_442.h.
| __I uint32_t ADC_T::STATUS1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:13] | VALID | Data Valid Flag (Read Only) |
| It is a mirror of VALID (ADC_DATx[17]) bit. | ||
| [16:29] | OV | Overrun Flag (Read Only) |
| It is a mirror to OV (ADC_DATx[16]) bit. |
Definition at line 586 of file NUC472_442.h.
| __IO uint32_t EADC_T::STATUS1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADIF0 | A/D ADINT0 Interrupt Flag |
| 0 = No ADINT0 interrupt pulse received. | ||
| 1 = ADINT0 interrupt pulse has been received. | ||
| Note1: This bit is cleared by writing 1 to it. | ||
| Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed | ||
| [1] | ADIF1 | A/D ADINT1 Interrupt Flag |
| 0 = No ADINT1 interrupt pulse received. | ||
| 1 = ADINT1 interrupt pulse has been received. | ||
| Note1: This bit is cleared by writing 1 to it. | ||
| Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed | ||
| [2] | ADIF2 | A/D ADINT2 Interrupt Flag |
| 0 = no ADINT2 interrupt pulse received. | ||
| 1 = ADINT2 interrupt pulse has been received. | ||
| Note1: This bit is cleared by writing 1 to it. | ||
| Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed | ||
| [3] | ADIF3 | A/D ADINT3 Interrupt Flag |
| 0 = No ADINT3 interrupt pulse received. | ||
| 1 = ADINT3 interrupt pulse has been received. | ||
| Note1: This bit is cleared by writing 1 to it. | ||
| Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed | ||
| [4] | ADCMPO0 | ADC Compare 0 Output Status |
| The 12 bits compare0 data CMPDAT EADC_CMP0 [27:16]) is used to compare with conversion result of specified SAMPLE. | ||
| Software can use it to monitor the external analog input pin voltage status. | ||
| 0 = Conversion result in ADDR less than CMPDAT (EADC_CMP0 [27:16]) setting. | ||
| 1 = Conversion result in ADDR great than or equal CMPDAT (EADC_CMP0 [27:16]) setting. | ||
| [5] | ADCMPO1 | ADC Compare 1 Output Status |
| The 12 bits compare1 data CMPDAT (EADC_CMP1 [27:16]) is used to compare with conversion result of specified SAMPLE. | ||
| Software can use it to monitor the external analog input pin voltage status. | ||
| 0 = Conversion result in ADDR less than CMPDAT EADC_CMP1 [27:16]) setting. | ||
| 1 = Conversion result in ADDR great than or equal CMPDAT (EADC_CMP1 [27:16]) setting. | ||
| [6] | ADCMPF0 | ADC Compare 0 Flag |
| When the specific SAMPLE A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. | ||
| 0 = Conversion result in ADDR does not meet EADC_CMP0 setting. | ||
| 1 = Conversion result in ADDR meets EADC_CMP0 setting. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [7] | ADCMPF1 | ADC Compare 1 Flag |
| When the specific SAMPLE A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. | ||
| 0 = Conversion result in ADDR does not meet EADC_CMP1 setting. | ||
| 1 = Conversion result in ADDR meets EADC_CMP1 setting. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [8] | BUSY0 | Busy/Idle (Read Only) |
| 0 = A/D converter 0 (ADC0) is in idle state. | ||
| 1 = A/D converter 0 (ADC0) is doing conversion. | ||
| [12:15] | CHANNEL0 | Current Conversion Channel (Read Only) |
| This filed reflects ADC0 current conversion channel when BUSY0 (EADC_STATUS1 [8]) = 1. | ||
| When BUSY0 (EADC_STATUS1 [8]) = 0, it shows the last converted channel. | ||
| 0000 = ADC0_CH0. | ||
| 0001 = ADC0_CH1. | ||
| 0010 = ADC0_CH2. | ||
| 0011 = ADC0_CH3. | ||
| 0100 = ADC0_CH4. | ||
| 0100 = ADC0_CH5. | ||
| 0110 = ADC0_CH6. | ||
| 0111 = ADC0_CH7. | ||
| 1000 = VBG. | ||
| 1001 = VTEMP. | ||
| 1010 = AVSS. | ||
| 1011 = OPA0_O. | ||
| Other = reserved. | ||
| [16] | BUSY1 | Busy/Idle |
| 0 = A/D converter 1 (ADC1) is in idle state. | ||
| 1 = A/D converter 1 (ADC1) is doing conversion. | ||
| [20:23] | CHANNEL1 | Current Conversion Channel (Read Only) |
| This filed reflects ADC1 current conversion channel when BUSY1 (EADC_STATUS1 [16]) = 1. | ||
| When BUSY1 (EADC_STATUS1 [16]) = 0, it shows the last converted channel. | ||
| 0000 = ADC1_CH0. | ||
| 0001 = ADC1_CH1. | ||
| 0010 = ADC1_CH2. | ||
| 0011 = ADC1_CH3. | ||
| 0100 = ADC1_CH4. | ||
| 0101 = ADC1_CH5. | ||
| 0110 = ADC1_CH6. | ||
| 0111 = ADC1_CH7. | ||
| 1000 = OPA1_O. | ||
| Other = reversed. | ||
| [24] | ADOVIF | All A/D Interrupt Flag Overrun Bits Check |
| 0 = None of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1. | ||
| 1 = Any one of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1. | ||
| Note: This bit will keep 1 when any ADFOVx (ADIFOVR [15:0]) Flag is equal to 1. | ||
| [25] | STOVF | For All A/D SAMPLE Start Of Conversion Overrun Flags Check |
| 0 = None of SAMPLE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1. | ||
| 1 = Any one of SAMPLE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1. | ||
| Note: This bit will keep 1 when any SPOVFx (ADSPOVFR [15:0]) Flag is equal to 1. | ||
| [26] | AVALID | For All SAMPLE A/D Result Data Register ADDR Data Valid Flag Check |
| 0 = None of SAMPLE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1. | ||
| 1 = Any one of SAMPLE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1. | ||
| Note: This bit will keep 1 when any VALIDx (EADC_ADnDATx[17]) Flag is equal to 1. | ||
| [27] | AOV | For All SAMPLE A/D Result Data Register Overrun Flags Check |
| 0 = None of SAMPLE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1. | ||
| 1 = Any one of SAMPLE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1. | ||
| Note: This bit will keep 1 when any OVx (EADC_ADnDATx[16]) Flag is equal to 1. |
Definition at line 8874 of file NUC472_442.h.
| __O uint32_t PDMA_T::STOP |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | STOP | PDMA Stop Transfer Bit [X] |
| User can stop the PDMA transfer by software reset (writing all '1' to PDMA_STOP register) or by PDMA_STOP register. | ||
| The difference between software reset and PDMA_STOP register is when software set software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit and request active flag will be cleared to '0'. | ||
| When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit and request active flag. | ||
| Software can poll channel enable bit to know if the on-going transfer is finished. | ||
| 0 = No effect. | ||
| 1 = Stop PDMA transfer[x]. | ||
| Note1: This field is Write-Only | ||
| Note2: Setting all PDMA_STOP bit to "1" will generate software reset to reset internal state machine (the embedded table will not be reset). |
Definition at line 18267 of file NUC472_442.h.
| __IO uint32_t CAP_T::STRIDE |
| Bits | Field | Descriptions |
|---|---|---|
| [0:13] | PKTSTRIDE | Packet Frame Output Pixel Stride Width |
| The output pixel stride size of packet pipe. | ||
| [16:29] | PLNSTRIDE | Planar Frame Output Pixel Stride Width |
| The output pixel stride size of planar pipe. |
Definition at line 1985 of file NUC472_442.h.
| __O uint32_t PDMA_T::SWREQ |
| Bits | Field | Descriptions |
|---|---|---|
| [0:11] | SWREQ | PDMA Software Request Bit [X] |
| Set this bit to 1 to generate a software request to PDMA [x]. | ||
| 0 = No effect. | ||
| 1 = Generate a software request. | ||
| Note1: This field is Write-Only. | ||
| Software can indicate which channel is on active by reading PDMA_TRGSTS register. | ||
| Active flag may be triggered by software request or peripheral request. | ||
| Note2: If user does not enable each PDMA channel, the software request will be ignored. |
Definition at line 18285 of file NUC472_442.h.
| __O uint32_t EADC_T::SWTRG |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | SWTRG7_0 | A/D SAMPLE07~SAMPLE00 Software Force To Start ADC Conversion |
| 0 = No effect. | ||
| 1 = Start an ADC conversion when the priority is given to SAMPLE0x. | ||
| Note: x = 0~7. | ||
| [8:15] | SWTRG15_8 | A/D SAMPLE17~SAMPLE10 Software Force To Start ADC Conversion |
| 0 = No effect. | ||
| 1 = Start an ADC conversion when the priority is given to SAMPLE1x. | ||
| Note: x = 0~7. |
Definition at line 7815 of file NUC472_442.h.
| __I uint32_t PDMA_T::TACTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | TXACTF | Transfer On Active Flag Bit [X] |
| This bit indicates which PDMA channel is on active. | ||
| 0 = PDMA channel is not finished. | ||
| 1 = PDMA channel is on active. |
Definition at line 18431 of file NUC472_442.h.
| __IO uint32_t RTC_T::TALM |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | SEC | 1-Sec Time Digit of Alarm Setting (0~9) |
| [4:6] | TENSEC | 10-Sec Time Digit of Alarm Setting (0~5) |
| [8:11] | MIN | 1-Min Time Digit of Alarm Setting (0~9) |
| [12:14] | TENMIN | 10-Min Time Digit of Alarm Setting (0~5) |
| [16:19] | HR | 1-Hour Time Digit of Alarm Setting (0~9) |
| [20:21] | TENHR | 10-Hour Time Digit of Alarm Setting (0~2) |
Definition at line 20531 of file NUC472_442.h.
| __IO uint32_t RTC_T::TAMP0PCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | OUTLV | Output Level |
| 0 = Low. | ||
| 1 = High. | ||
| [1] | OUTEN | Output Enable Control |
| 0 = Output Enabled. | ||
| 1 = Output Disabled. | ||
| [2] | TRIEN | Tri-State |
| 0 = Tri-state Disabled. | ||
| 1 = Tri-state Enabled. | ||
| [3] | TYPE | Type |
| 0 = Input Schmitt Trigger function Disabled. | ||
| 1 = Input Schmitt Trigger function Enabled. | ||
| [4] | DINOFF | Off Digital |
| 0 = Off digital Disabled. | ||
| 1 = Off digital Enabled. |
Definition at line 20738 of file NUC472_442.h.
| __IO uint32_t RTC_T::TAMP1PCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | OUTLV | Output Level |
| 0 = Low. | ||
| 1 = High. | ||
| [1] | OUTEN | Output Enable Control |
| 0 = Output Enabled. | ||
| 1 = Output Disabled. | ||
| [2] | TRIEN | Tri-State |
| 0 = Tri-state Disabled. | ||
| 1 = Tri-state Enabled. | ||
| [3] | TYPE | Type |
| 0 = Input Schmitt Trigger function Disabled. | ||
| 1 = Input Schmitt Trigger function Enabled. | ||
| [4] | DINOFF | Off Digital |
| 0 = Off digital Disabled. | ||
| 1 = Off digital Enabled. |
Definition at line 20763 of file NUC472_442.h.
| __IO uint32_t RTC_T::TAMPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TIEN | Tamper Interrupt Enable Control |
| 0 = Tamper interrupt Disabled. | ||
| 1 = Tamper interrupt Enabled. | ||
| [1] | DESTROYEN | Destroy Spare Register Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2] | TAMPEN0 | Tamper0 Detect Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [3] | TAMPEN1 | Tamper1 Detect Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [4] | TAMPDBEN0 | Tamper0 De-Bounce Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [5] | TAMPDBEN1 | Tamper1 De-Bounce Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [6] | TAMPLV0 | Tamper0 Level |
| 0 = Low. | ||
| 1 = High. | ||
| [7] | TAMPLV1 | Tamper1 Level |
| 0 = Low. | ||
| 1 = High. |
Definition at line 20691 of file NUC472_442.h.
| __IO uint32_t RTC_T::TAMPSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TAMPSTS0 | Tamper0 Sense Flag |
| 0 = No invasion. | ||
| 1 = Tamper0 detect invasion. | ||
| Note: Write 1 to clear it | ||
| [1] | TAMPSTS1 | Tamper1 Sense Flag |
| 0 = No invasion. | ||
| 1 = Tamper1 detect invasion. | ||
| Note: Write 1 to clear it |
Definition at line 20709 of file NUC472_442.h.
| __IO uint32_t RTC_T::TAMSK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | MSEC | Mask 1-Sec Time Digit of Alarm Setting (0~9) |
| [1] | MTENSEC | Mask 10-Sec Time Digit of Alarm Setting (0~5) |
| [2] | MMIN | Mask 1-Min Time Digit of Alarm Setting (0~9) |
| [3] | MTENMIN | Mask 10-Min Time Digit of Alarm Setting (0~5) |
| [4] | MHR | Mask 1-Hour Time Digit of Alarm Setting (0~9) |
| [5] | MTENHR | Mask 10-Hour Time Digit of Alarm Setting (0~2) |
Definition at line 20833 of file NUC472_442.h.
| __IO uint32_t EBI_T::TCTL[4] |
| Bits | Field | Descriptions |
|---|---|---|
| [0:2] | TALE | Bank Expand Time Of ALE |
| The ALE width (tALE) to latch the address can be controlled by TALE. | ||
| tALE = (TALE+1)*MCLK. | ||
| [3:7] | TACC | EBI Bank Data Access Time |
| TACC define data access time (tACC). | ||
| tACC = (TACC +1) * MCLK. | ||
| [8:10] | TAHD | EBI Bank Data Access Hold Time |
| TAHD define data access hold time (tAHD). | ||
| tAHD = (TAHD +1) * MCLK. | ||
| [12:15] | W2X | Bank Idle State Cycle After Write |
| When write action is finish, idle state is inserted and nCS[0] return to high if W2X is not zero. | ||
| Idle state cycle = (W2X*MCLK). | ||
| 0 = reserved. | ||
| [16:19] | R2W | Bank Idle State Cycle Between Read-Write |
| When read action is finish and next action is going to write, idle state is inserted and nCS[0] return to high if R2W is not zero. | ||
| Idle state cycle = (R2W*MCLK). | ||
| 0 = reserved. | ||
| [24:27] | R2R | Bank Idle State Cycle Between Read-Read |
| When read action is finish and next action is going to read, idle state is inserted and nCS[0] return to high if R2R is not zero. | ||
| Idle state cycle = (R2R*MCLK). | ||
| 0 = reserved. | ||
| [28] | CSEN | EBI Bank Enable Control |
| This bit is the functional enable bit for EBI. | ||
| 0 = EBI function Disabled. | ||
| 1 = EBI function Enabled. | ||
| [29] | DW16 | EBI Bank Data Width 16-Bit |
| This bit defines if the data bus is 8-bit or 16-bit. | ||
| 0 = EBI data width is 8-bit. | ||
| 1 = EBI data width is 16-bit. | ||
| [30] | SEPEN | EBI Bank Address/Data Bus Separating Enable Control |
| 0 = Address/Data Bus Separating Disabled. | ||
| 1 = Address/Data Bus Separating Enabled. |
Definition at line 11640 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES0_CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CNT | TDES/DES Byte Count |
| The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode. | ||
| The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes. | ||
| TDES_CNT can be read and written. | ||
| Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_CNT will be updated later on. | ||
| Consequently, software can prepare the byte count of data for the next TDES /DES operation. | ||
| In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data. |
Definition at line 5951 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES0_DADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DADDR | TDES/DES DMA Destination Address |
| The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO. | ||
| The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored. | ||
| Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished. | ||
| The start of destination address should be located at word boundary. | ||
| In other words, bit 1 and 0 of TDES_DADR are ignored. | ||
| TDES_DADR can be read and written. | ||
| Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_DADR will be updated later on. | ||
| Consequently, software can prepare the destination address for the next TDES/DES operation. | ||
| In DMA mode, software can update the next TDES_DADR before triggering START. | ||
| TDES_SADR and TDES_DADR can be the same in the value. |
Definition at line 5933 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES0_IVH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IVH_IVL | TDES/DES Initial Vector High/Low Word |
| Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. | ||
| IV is Nonce counter for TDES/DES engine in CTR mode. |
Definition at line 5876 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES0_IVL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IVH_IVL | TDES/DES Initial Vector High/Low Word |
| Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. | ||
| IV is Nonce counter for TDES/DES engine in CTR mode. |
Definition at line 5889 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES0_KEY1H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 5788 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES0_KEY1L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 5803 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES0_KEY2H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 5818 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES0_KEY2L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 5833 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES0_KEY3H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 5848 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES0_KEY3L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 5863 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES0_SADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SADDR | TDES/DES DMA Source Address |
| The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. | ||
| The TDES_SADR keeps the source address of the data buffer where the source text is stored. | ||
| Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation. | ||
| The start of source address should be located at word boundary. | ||
| In other words, bit 1 and 0 of TDES_SADR are ignored. | ||
| TDES_SADR can be read and written. | ||
| Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_SADR will be updated later on. | ||
| Consequently, software can prepare the DMA source address for the next TDES/DES operation. | ||
| In DMA mode, software can update the next TDES_SADR before triggering START. | ||
| TDES_SADR and TDES_DADR can be the same in the value. |
Definition at line 5911 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES1_CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CNT | TDES/DES Byte Count |
| The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode. | ||
| The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes. | ||
| TDES_CNT can be read and written. | ||
| Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_CNT will be updated later on. | ||
| Consequently, software can prepare the byte count of data for the next TDES /DES operation. | ||
| In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data. |
Definition at line 6159 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES1_DADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DADDR | TDES/DES DMA Destination Address |
| The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO. | ||
| The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored. | ||
| Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished. | ||
| The start of destination address should be located at word boundary. | ||
| In other words, bit 1 and 0 of TDES_DADR are ignored. | ||
| TDES_DADR can be read and written. | ||
| Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_DADR will be updated later on. | ||
| Consequently, software can prepare the destination address for the next TDES/DES operation. | ||
| In DMA mode, software can update the next TDES_DADR before triggering START. | ||
| TDES_SADR and TDES_DADR can be the same in the value. |
Definition at line 6141 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES1_IVH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IVH_IVL | TDES/DES Initial Vector High/Low Word |
| Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. | ||
| IV is Nonce counter for TDES/DES engine in CTR mode. |
Definition at line 6084 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES1_IVL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IVH_IVL | TDES/DES Initial Vector High/Low Word |
| Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. | ||
| IV is Nonce counter for TDES/DES engine in CTR mode. |
Definition at line 6097 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES1_KEY1H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 5996 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES1_KEY1L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6011 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES1_KEY2H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6026 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES1_KEY2L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6041 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES1_KEY3H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6056 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES1_KEY3L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6071 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES1_SADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SADDR | TDES/DES DMA Source Address |
| The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. | ||
| The TDES_SADR keeps the source address of the data buffer where the source text is stored. | ||
| Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation. | ||
| The start of source address should be located at word boundary. | ||
| In other words, bit 1 and 0 of TDES_SADR are ignored. | ||
| TDES_SADR can be read and written. | ||
| Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_SADR will be updated later on. | ||
| Consequently, software can prepare the DMA source address for the next TDES/DES operation. | ||
| In DMA mode, software can update the next TDES_SADR before triggering START. | ||
| TDES_SADR and TDES_DADR can be the same in the value. |
Definition at line 6119 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES2_CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CNT | TDES/DES Byte Count |
| The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode. | ||
| The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes. | ||
| TDES_CNT can be read and written. | ||
| Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_CNT will be updated later on. | ||
| Consequently, software can prepare the byte count of data for the next TDES /DES operation. | ||
| In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data. |
Definition at line 6341 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES2_DADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DADDR | TDES/DES DMA Destination Address |
| The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO. | ||
| The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored. | ||
| Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished. | ||
| The start of destination address should be located at word boundary. | ||
| In other words, bit 1 and 0 of TDES_DADR are ignored. | ||
| TDES_DADR can be read and written. | ||
| Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_DADR will be updated later on. | ||
| Consequently, software can prepare the destination address for the next TDES/DES operation. | ||
| In DMA mode, software can update the next TDES_DADR before triggering START. | ||
| TDES_SADR and TDES_DADR can be the same in the value. |
Definition at line 6323 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES2_IVH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IVH_IVL | TDES/DES Initial Vector High/Low Word |
| Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. | ||
| IV is Nonce counter for TDES/DES engine in CTR mode. |
Definition at line 6266 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES2_IVL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IVH_IVL | TDES/DES Initial Vector High/Low Word |
| Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. | ||
| IV is Nonce counter for TDES/DES engine in CTR mode. |
Definition at line 6279 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES2_KEY1H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6178 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES2_KEY1L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6193 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES2_KEY2H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6208 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES2_KEY2L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6223 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES2_KEY3H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6238 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES2_KEY3L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6253 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES2_SADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SADDR | TDES/DES DMA Source Address |
| The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. | ||
| The TDES_SADR keeps the source address of the data buffer where the source text is stored. | ||
| Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation. | ||
| The start of source address should be located at word boundary. | ||
| In other words, bit 1 and 0 of TDES_SADR are ignored. | ||
| TDES_SADR can be read and written. | ||
| Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_SADR will be updated later on. | ||
| Consequently, software can prepare the DMA source address for the next TDES/DES operation. | ||
| In DMA mode, software can update the next TDES_SADR before triggering START. | ||
| TDES_SADR and TDES_DADR can be the same in the value. |
Definition at line 6301 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES3_CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CNT | TDES/DES Byte Count |
| The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode. | ||
| The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes. | ||
| TDES_CNT can be read and written. | ||
| Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_CNT will be updated later on. | ||
| Consequently, software can prepare the byte count of data for the next TDES /DES operation. | ||
| In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data. |
Definition at line 6523 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES3_DADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DADDR | TDES/DES DMA Destination Address |
| The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO. | ||
| The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored. | ||
| Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished. | ||
| The start of destination address should be located at word boundary. | ||
| In other words, bit 1 and 0 of TDES_DADR are ignored. | ||
| TDES_DADR can be read and written. | ||
| Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_DADR will be updated later on. | ||
| Consequently, software can prepare the destination address for the next TDES/DES operation. | ||
| In DMA mode, software can update the next TDES_DADR before triggering START. | ||
| TDES_SADR and TDES_DADR can be the same in the value. |
Definition at line 6505 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES3_IVH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IVH_IVL | TDES/DES Initial Vector High/Low Word |
| Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. | ||
| IV is Nonce counter for TDES/DES engine in CTR mode. |
Definition at line 6448 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES3_IVL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | IVH_IVL | TDES/DES Initial Vector High/Low Word |
| Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. | ||
| IV is Nonce counter for TDES/DES engine in CTR mode. |
Definition at line 6461 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES3_KEY1H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6360 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES3_KEY1L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6375 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES3_KEY2H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6390 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES3_KEY2L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6405 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES3_KEY3H |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6420 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES3_KEY3L |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYH_KEYL | TDES/DES Key X High/Low Word |
| The key registers for TDES/DES algorithm calculation | ||
| The security key for the TDES/DES accelerator is 64 bits. | ||
| Thus, it needs two 32-bit registers to store a security key. | ||
| The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0]. |
Definition at line 6435 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES3_SADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SADDR | TDES/DES DMA Source Address |
| The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. | ||
| The TDES_SADR keeps the source address of the data buffer where the source text is stored. | ||
| Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation. | ||
| The start of source address should be located at word boundary. | ||
| In other words, bit 1 and 0 of TDES_SADR are ignored. | ||
| TDES_SADR can be read and written. | ||
| Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. | ||
| But the value of TDES_SADR will be updated later on. | ||
| Consequently, software can prepare the DMA source address for the next TDES/DES operation. | ||
| In DMA mode, software can update the next TDES_SADR before triggering START. | ||
| TDES_SADR and TDES_DADR can be the same in the value. |
Definition at line 6483 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES_CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | START | TDES/DES Engine Start |
| 0 = No effect. | ||
| 1 = Start TDES/DES engine. The flag BUSY would be set. | ||
| Note: The bit is always 0 when it's read back. | ||
| [1] | STOP | TDES/DES Engine Stop |
| 0 = No effect. | ||
| 1 = Stop TDES/DES engine. | ||
| Note: The bit is always 0 when it's read back. | ||
| [2] | TMODE | TDES/DES Engine Operating Mode |
| 0 = Set DES mode for TDES/DES engine. | ||
| 1 = Set Triple DES mode for TDES/DES engine. | ||
| [3] | 3KEYS | TDES/DES Key Number |
| 0 = Select KEY1 and KEY2 in TDES/DES engine. | ||
| 1 = Triple keys in TDES/DES engine Enabled. | ||
| [5] | DMALAST | TDES/DES Engine Start For The Last Block |
| In DMA mode, this bit must be set as beginning the last DMA cascade round. | ||
| In Non-DMA mode, this bit must be set as feeding in last block of data. | ||
| [6] | DMACSCAD | TDES/DES Engine DMA With Cascade Mode |
| 0 = DMA cascade function Disabled. | ||
| 1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. | ||
| [7] | DMAEN | TDES/DES Engine DMA Enable Control |
| 0 = TDES_DMA engine Disabled. | ||
| TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN. | ||
| 1 = TDES_DMA engine Enabled. | ||
| TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. | ||
| [8:10] | OPMODE | TDES/DES Engine Operation Mode |
| 0x00 = ECB (Electronic Codebook Mode). | ||
| 0x01 = CBC (Cipher Block Chaining Mode). | ||
| 0x02 = CFB (Cipher Feedback Mode). | ||
| 0x03 = OFB (Output Feedback Mode). | ||
| 0x04 = CTR (Counter Mode). | ||
| Others = CTR (Counter Mode). | ||
| [16] | ENCRPT | TDES/DES Encryption/Decryption |
| 0 = TDES engine executes decryption operation. | ||
| 1 = TDES engine executes encryption operation. | ||
| [21] | BLKSWAP | TDES/DES Engine Block Double Word Endian Swap |
| 0 = Keep the original order, e.g. {WORD_H, WORD_L}. | ||
| 1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}. | ||
| [22] | OUTSWAP | TDES/DES Engine Output Data Swap |
| 0 = Keep the original order. | ||
| 1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. | ||
| [23] | INSWAP | TDES/DES Engine Input Data Swap |
| 0 = Keep the original order. | ||
| 1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. | ||
| [24:25] | CHANNEL | TDES/DES Engine Working Channel |
| 00 = Current control register setting is for channel 0. | ||
| 01 = Current control register setting is for channel 1. | ||
| 10 = Current control register setting is for channel 2. | ||
| 11 = Current control register setting is for channel 3. | ||
| [26:30] | KEYUNPRT | Unprotected Key |
| Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key. | ||
| The KEYUNPRT can be read and written. | ||
| When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. | ||
| [31] | KEYPRT | Protect Key |
| Read as a flag to reflect KEYPRT. | ||
| 0 = No effect. | ||
| 1 = This bit is to protect the content of TDES key from reading. | ||
| The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L. | ||
| Once it is set, it can be cleared by asserting KEYUNPRT. | ||
| The key content would be cleared as well. |
Definition at line 5733 of file NUC472_442.h.
| __IO uint32_t CRPT_T::TDES_DATIN |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DATIN | TDES/DES Engine Input Port |
| CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS. | ||
| Feed data as INBUFFULL is 0. |
Definition at line 5964 of file NUC472_442.h.
| __I uint32_t CRPT_T::TDES_DATOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DATOUT | TDES/DES Engine Output Port |
| CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS. | ||
| Get data as OUTBUFEMPTY is 0. |
Definition at line 5977 of file NUC472_442.h.
| __I uint32_t CRPT_T::TDES_FDBCKH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | FDBCK | TDES/DES Feedback |
| The feedback value is 64 bits in size. | ||
| The TDES/DES engine uses the data from CRPT_TDES_FEEEDBACK as the data inputted to CRPT_TDES_IV for the next block in DMA cascade mode. | ||
| The feedback register is for CBC, CFB, and OFB mode. | ||
| TDES/DES engine outputs feedback information for IV in the next block's operation. | ||
| Software can use this feedback information to implement more than four DMA channels. | ||
| Software can store that feedback value temporarily. | ||
| After switching back, fill the stored feedback value to this register in the same channel operation. | ||
| Then can continue the operation with the original setting. |
Definition at line 4424 of file NUC472_442.h.
| __I uint32_t CRPT_T::TDES_FDBCKL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | FDBCK | TDES/DES Feedback |
| The feedback value is 64 bits in size. | ||
| The TDES/DES engine uses the data from CRPT_TDES_FEEEDBACK as the data inputted to CRPT_TDES_IV for the next block in DMA cascade mode. | ||
| The feedback register is for CBC, CFB, and OFB mode. | ||
| TDES/DES engine outputs feedback information for IV in the next block's operation. | ||
| Software can use this feedback information to implement more than four DMA channels. | ||
| Software can store that feedback value temporarily. | ||
| After switching back, fill the stored feedback value to this register in the same channel operation. | ||
| Then can continue the operation with the original setting. |
Definition at line 4443 of file NUC472_442.h.
| __I uint32_t CRPT_T::TDES_STS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUSY | TDES/DES Engine Busy |
| 0 = TDES/DES engine is idle or finished. | ||
| 1 = TDES/DES engine is under processing. | ||
| [8] | INBUFEMPTY | TDES/DES In Buffer Empty |
| 0 = There are some data in input buffer waiting for the TDES/DES engine to process. | ||
| 1 = TDES/DES input buffer is empty. | ||
| Software needs to feed data to the TDES/DES engine. | ||
| Otherwise, the TDES/DES engine will be pending to wait for input data. | ||
| [9] | INBUFFULL | TDES/DES In Buffer Full Flag |
| 0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine. | ||
| 1 = TDES input buffer is full. | ||
| Software cannot feed data to the TDES/DES engine. | ||
| Otherwise, the flag INBUFERR will be set to 1. | ||
| [10] | INBUFERR | TDES/DES In Buffer Error Flag |
| 0 = No error. | ||
| 1 = Error happens during feeding data to the TDES/DES engine. | ||
| [16] | OUTBUFEMPTY | TDES/DES Output Buffer Empty Flag |
| 0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer. | ||
| 1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT. | ||
| Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty. | ||
| [17] | OUTBUFFULL | TDES/DES Output Buffer Full Flag |
| 0 = TDES/DES output buffer is not full. | ||
| 1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT. | ||
| Otherwise, the TDES/DES engine will be pending since output buffer is full. | ||
| [18] | OUTBUFERR | TDES/DES Out Buffer Error Flag |
| 0 = No error. | ||
| 1 = Error happens during getting test result from TDES/DES engine. | ||
| [20] | BUSERR | TDES/DES DMA Access Bus Error Flag |
| 0 = No error. | ||
| 1 = Bus error will stop DMA operation and TDES/DES engine. |
Definition at line 5773 of file NUC472_442.h.
| __IO uint32_t PDMA_T::TDSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | TDIF | Transfer Done Flag [X] |
| This bit indicates which PDMA channel has finished transmission. | ||
| 0 = Not finished yet. | ||
| 1 = PDMA channel has finished transmission. | ||
| Note: This field is read only, but software can write 1 to clear. |
Definition at line 18402 of file NUC472_442.h.
| __IO uint32_t SYS_T::TEMPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | VTEMPEN | Temperature Sensor Enable Control |
| This bit is used to enable/disable temperature sensor function. | ||
| 0 = Temperature sensor function Disabled (default). | ||
| 1 = Temperature sensor function Enabled. | ||
| After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. | ||
| Please refer to ADC function chapter for details. |
Definition at line 23600 of file NUC472_442.h.
| __IO uint32_t CAN_T::TEST |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | Res | Reserved |
| There are reserved bits. | ||
| These bits are always read as '0' and must always be written with '0'. | ||
| [2] | Basic | Basic Mode |
| 0 = Basic Mode disabled. | ||
| 1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. | ||
| [3] | Silent | Silent Mode |
| 0 = Normal operation. | ||
| 1 = The module is in Silent Mode. | ||
| [4] | LBack | Loop Back Mode Enable Control |
| 0 = Loop Back Mode is disabled. | ||
| 1 = Loop Back Mode is enabled. | ||
| [5:6] | Tx10 | Tx[1:0]: Control Of CAN_TX Pin |
| 00 = Reset value, CAN_TX pin is controlled by the CAN Core. | ||
| 01 = Sample Point can be monitored at CAN_TX pin. | ||
| 10 = CAN_TX pin drives a dominant ('0') value. | ||
| 11 = CAN_TX pin drives a recessive ('1') value. | ||
| [7] | Rx | Monitors The Actual Value Of CAN_RX Pin (Read Only) |
| 0 = The CAN bus is dominant (CAN_RX = '0'). | ||
| 1 = The CAN bus is recessive (CAN_RX = '1'). |
Definition at line 1278 of file NUC472_442.h.
| __IO uint32_t USBD_T::TEST |
| Bits | Field | Descriptions |
|---|---|---|
| [0:2] | TESTMODE | Test Mode Selection |
| 000 = Normal Operation. | ||
| 001 = Test_J. | ||
| 010 = Test_K. | ||
| 011 = Test_SE0_NAK. | ||
| 100 = Test_Packet. | ||
| 101 = Test_Force_Enable. | ||
| 110 = Reserved. | ||
| 111 = Reserved. | ||
| Note: This field is cleared when root port reset is detected. |
Definition at line 27557 of file NUC472_442.h.
| __IO uint32_t RTC_T::TICK |
| Bits | Field | Descriptions |
|---|---|---|
| [0:2] | TICKSEL | Time Tick Bits |
| The RTC time tick period for Periodic Time Tick Interrupt request. | ||
| 000 = Time tick is 1 second. | ||
| 001 = Time tick is 1/2 second. | ||
| 010 = Time tick is 1/4 second. | ||
| 011 = Time tick is 1/8 second. | ||
| 100 = Time tick is 1/16 second. | ||
| 101 = Time tick is 1/32 second. | ||
| 110 = Time tick is 1/64 second. | ||
| 111 = Time tick is 1/128 second. | ||
| Note: These bits can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. |
Definition at line 20615 of file NUC472_442.h.
| __IO uint32_t RTC_T::TIME |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | SEC | 1-Sec Time Digit (0~9) |
| [4:6] | TENSEC | 10-Sec Time Digit (0~5) |
| [8:11] | MIN | 1-Min Time Digit (0~9) |
| [12:14] | TENMIN | 10-Min Time Digit (0~5) |
| [16:19] | HR | 1-Hour Time Digit (0~9) |
| [20:21] | TENHR | 10-Hour Time Digit (0~2) |
Definition at line 20466 of file NUC472_442.h.
| __IO uint32_t SC_T::TMRCTL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:23] | CNT | Timer 0 Counter Value (ETU Base) |
| This field indicates the internal timer operation values. | ||
| [24:27] | OPMODE | Timer 0 Operation Mode Selection |
| This field indicates the internal 24-bit timer operation selection. | ||
| Refer to <IP_ADDRESS> for programming Timer0. |
Definition at line 21654 of file NUC472_442.h.
| __IO uint32_t SC_T::TMRCTL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | CNT | Timer 1 Counter Value (ETU Base) |
| This field indicates the internal timer operation values. | ||
| [24:27] | OPMODE | Timer 1 Operation Mode Selection |
| This field indicates the internal 8-bit timer operation selection. | ||
| Refer to <IP_ADDRESS> for programming Timer1. |
Definition at line 21669 of file NUC472_442.h.
| __IO uint32_t SC_T::TMRCTL2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | CNT | Timer 2 Counter Value (ETU Base) |
| This field indicates the internal timer operation values. | ||
| [24:27] | OPMODE | Timer 2 Operation Mode Selection |
| This field indicates the internal 8-bit timer operation selection | ||
| Refer to <IP_ADDRESS> for programming Timer2 |
Definition at line 21684 of file NUC472_442.h.
| __I uint32_t SC_T::TMRDAT0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:23] | CNT0 | Timer0 Current Counter Value (Read Only) |
| This field indicates the current count values of timer0. |
Definition at line 21726 of file NUC472_442.h.
| __I uint32_t SC_T::TMRDAT1_2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | CNT1 | Timer1 Current Counter Value (Read Only) |
| This field indicates the current count values of timer1. | ||
| [8:15] | CNT2 | Timer2 Current Counter Value (Read Only) |
| This field indicates the current count values of timer2. |
Definition at line 21740 of file NUC472_442.h.
| __IO uint32_t I2C_T::TOCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TOIF | Time-Out Flag |
| This bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI (I2CON[7])) is set to 1. | ||
| Note: Write 1 to clear this bit. | ||
| [1] | TOCDIV4 | Time-Out Counter Input Clock Divided By 4 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| When Enabled, The time-out period is extend 4 times. | ||
| [2] | TOCEN | Time-Out Counter Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| When Enabled, the 14-bit time-out counter will start counting when SI (I2CON[3]) is clear. | ||
| Setting flag SI to high will reset counter and re-start up counting after SI is cleared. |
Definition at line 16932 of file NUC472_442.h.
| __IO uint32_t SDH_T::TOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:23] | TOUT | SD Response/Data-In Time-Out Value |
| A 24-bit value specifies the time-out counts of response and data input. | ||
| SD host controller will wait start bit of response or data-in until this value reached. | ||
| The time period depends on SD engine clock frequency. | ||
| Do not write a small number into this field, or you may never get response or data due to time-out. | ||
| Note: Filling 0x0 into this field will disable hardware time-out function. |
Definition at line 22493 of file NUC472_442.h.
| __IO uint32_t UART_T::TOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | TOIC | Time-Out Interrupt Comparator |
| The time-out counter resets and starts counting (the counting clock = baud rate clock) whenever the RX FIFO receives a new data word. | ||
| Once the content of time-out counter (TOUT_CNT) is equal to that of time-out interrupt comparator (TOIC), a receiver time-out interrupt (INT_TOUT) is generated if RXTOIEN (UART_INTEN[4]). | ||
| A new incoming data word or RX FIFO empty clears INT_TOUT. | ||
| In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255. | ||
| So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. | ||
| [8:15] | DLY | TX Delay Time Value |
| This field is use to programming the transfer delay time between the last stop bit and next start bit. | ||
| Note: The counter clock is baud rate clock |
Definition at line 25548 of file NUC472_442.h.
| __IO uint32_t PWM_T::TRGADCSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | PTRGF | PWM Period Point Trigger Flag |
| This bit is set to 1 by hardware when PWM counter down count to zero if corresponding PTRGEN bit is 1. | ||
| After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM. | ||
| Note1: Write 1 to clear this bit. | ||
| Note2: Each bit controls the corresponding PWM channel. | ||
| [8:13] | CTRGF | PWM Center Point Trigger Flag |
| This bit is set to 1 by hardware when PWM counter up counts to (PERIODn+1) if the corresponding CTRGEN bit is 1. | ||
| After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM. | ||
| Note1: Write 1 to clear this bit. | ||
| Note2: Each bit controls the corresponding PWM channel. | ||
| [16:21] | FTRGF | PWM Falling Edge Point Trigger Indicator |
| This bit is set to 1 by hardware when PWM output pin falling edge is detected if corresponding FETRGEN bit is 1. | ||
| After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM. | ||
| Note1: Write 1 to clear this bit. | ||
| Note2: Each bit controls the corresponding PWM channel. | ||
| [24:29] | RTRGF | PWM Rising Edge Point Trigger Indicator |
| This bit is set to 1 by hardware when PWM output pin rising edge is detected if corresponding RETRGEN bit is 1. | ||
| After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM. | ||
| Note1: Write 1 to clear this bit. | ||
| Note2: Each bit controls the corresponding PWM channel. |
Definition at line 19352 of file NUC472_442.h.
| __IO uint32_t PWM_T::TRGADCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | PTRGEN | PWM Period Point Trigger Enable Control |
| 0 = PWM period point trigger ADC function Disabled. | ||
| 1 = PWM period point trigger ADC function Enabled. | ||
| PWM can trigger ADC to start conversion when PWM counter down count to zero if this bit is set to1. | ||
| Note: Each bit controls the corresponding PWM channel. | ||
| [8:13] | CTRGEN | PWM Center Point Trigger Enable Control |
| 0 = PWM center point trigger ADC function Disabled. | ||
| 1 = PWM center point trigger ADC function Enabled. | ||
| PWM can trigger ADC to start conversion when PWM counter up count to (PERIODn+1) if this bit is set to1. | ||
| Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type. | ||
| Note2: Each bit controls the corresponding PWM channel. | ||
| [16:21] | FTRGEN | PWM Falling Edge Point Trigger Enable Control |
| 0 = PWM falling edge point trigger ADC function Disabled. | ||
| 1 = PWM falling edge point trigger ADC function Enabled. | ||
| PWM can trigger ADC to start conversion when PWM output pin falling edge is detected if this bit is set to1. | ||
| Note: Each bit controls the corresponding PWM channel. | ||
| [24:29] | RTRGEN | PWM Rising Edge Point Trigger Enable Control |
| 0 = PWM rising edge point trigger ADC function Disabled. | ||
| 1 = PWM rising edge point trigger ADC function Enabled. | ||
| PWM can trigger ADC to start conversion when PWM output pin rising edge is detected if this bit is set to1. | ||
| Note: Each bit controls the corresponding PWM channel. |
Definition at line 19322 of file NUC472_442.h.
| __I uint32_t PDMA_T::TRGSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | REQSTS | PDMA Request Active Flag [X] |
| This flag indicates whether channel[x] have a request or not. | ||
| 0 = Have no requests. | ||
| 1 = Have a request. | ||
| Note1: The request may come from software request (SWREQ) or peripheral request. | ||
| Note2: When PDMA finishes channel transfer, this bit will be cleared automatically | ||
| Note3: Software reset (setting PDMA_STOP to 0xFFFF_FFFF) will clear this bit. |
Definition at line 18302 of file NUC472_442.h.
| __IO uint32_t EMAC_T::TSADDEND |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | ADDEND | Time Stamp Counter Addend |
| This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC. | ||
| If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator with this 32-bit value in each HCLK. | ||
| Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit value kept in register EMAC_TSINC. |
Definition at line 13191 of file NUC472_442.h.
| __IO uint32_t EMAC_T::TSCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TSEN | Time Stamp Function Enable Control |
| This bit controls if the IEEE 1588 PTP time stamp function is enabled or not. | ||
| Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low to disable IEEE 1588 PTP time stamp function. | ||
| 0 = I EEE 1588 PTP time stamp function Disabled. | ||
| 1 = IEEE 1588 PTP time stamp function Enabled. | ||
| [1] | TSIEN | Time Stamp Counter Initialization Enable Control |
| Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stamp counter. | ||
| After the load operation finished, Ethernet MAC controller clear this bit to low automatically. | ||
| 0 = Time stamp counter initialization done. | ||
| 1 = Time stamp counter initialization Enabled. | ||
| [2] | TSMODE | Time Stamp Fine Update Enable Control |
| This bit chooses the time stamp counter update mode. | ||
| 0 = Time stamp counter is in coarse update mode. | ||
| 1 = Time stamp counter is in fine update mode. | ||
| [3] | TSUPDATE | Time Stamp Counter Time Update Enable Control |
| Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stamp counter. | ||
| After the add operation finished, Ethernet MAC controller clear this bit to low automatically. | ||
| 0 = No action. | ||
| 1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC. | ||
| [5] | TSALMEN | Time Stamp Alarm Enable Control |
| Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. | ||
| 0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. | ||
| 1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. |
Definition at line 13134 of file NUC472_442.h.
| __IO uint32_t EMAC_T::TSINC |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | CNTINC | Time Stamp Counter Increment |
| Time stamp counter increment value. | ||
| If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every time when it wants to increase the EMAC_TSSUBSEC value. |
Definition at line 13177 of file NUC472_442.h.
| __I uint32_t EMAC_T::TSSEC |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SEC | Time Stamp Counter Second |
| This register reflects the bit [63:32] value of 64-bit reference timing counter. | ||
| This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. |
Definition at line 13151 of file NUC472_442.h.
| __I uint32_t EMAC_T::TSSUBSEC |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SUBSEC | Time Stamp Counter Sub-Second |
| This register reflects the bit [31:0] value of 64-bit reference timing counter. | ||
| This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. |
Definition at line 13164 of file NUC472_442.h.
| __O uint32_t I2S_T::TX |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | TX | Transmit FIFO Bits |
| I2S contains 8 words (8x32 bit) data buffer for data transmit. | ||
| Write data to this register to prepare data for transmit. | ||
| The remaining word number is indicated by TXCNT(I2S_STATUS[31:28]). |
Definition at line 17457 of file NUC472_442.h.
| __O uint32_t SPI_T::TX |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | TX | Data Transmit Bits |
| The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer. | ||
| The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register. | ||
| In Master mode, the serial data in SPI bus output need 5 module clock cycle when the data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer. | ||
| For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. | ||
| If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer. |
Definition at line 23039 of file NUC472_442.h.
| __IO uint32_t PS2_T::TXDAT0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DAT | Transmit Data |
| Write data to this register starts device to host communication if bus is in IDLE state. | ||
| Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer. |
Definition at line 18808 of file NUC472_442.h.
| __IO uint32_t PS2_T::TXDAT1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DAT | Transmit Data |
| Write data to this register starts device to host communication if bus is in IDLE state. | ||
| Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer. |
Definition at line 18821 of file NUC472_442.h.
| __IO uint32_t PS2_T::TXDAT2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DAT | Transmit Data |
| Write data to this register starts device to host communication if bus is in IDLE state. | ||
| Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer. |
Definition at line 18834 of file NUC472_442.h.
| __IO uint32_t PS2_T::TXDAT3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DAT | Transmit Data |
| Write data to this register starts device to host communication if bus is in IDLE state. | ||
| Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer. |
Definition at line 18847 of file NUC472_442.h.
| __IO uint32_t EMAC_T::TXDSA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | TXDSA | Transmit Descriptor Link-List Start Address |
| The TXDSA keeps the start address of transmit descriptor link-list. | ||
| If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the current transmit descriptor start address register (EMAC_CTXDSA). | ||
| The TXDSA does not be updated by EMAC. | ||
| During the operation, EMAC will ignore the bits [1:0] of TXDSA. | ||
| This means that each TX descriptor always must locate at word boundary memory address. |
Definition at line 12357 of file NUC472_442.h.
| __IO uint32_t CAN_T::TXREQ1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | TxRqst161 | Transmission Request Bits 16-1 (Of All Message Objects) |
| 0 = This Message Object is not waiting for transmission. | ||
| 1 = The transmission of this Message Object is requested and is not yet done. | ||
| These bits are read only. |
Definition at line 1311 of file NUC472_442.h.
| __IO uint32_t CAN_T::TXREQ2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | TxRqst3217 | Transmission Request Bits 32-17 (Of All Message Objects) |
| 0 = This Message Object is not waiting for transmission. | ||
| 1 = The transmission of this Message Object is requested and is not yet done. | ||
| These bits are read only. |
Definition at line 1325 of file NUC472_442.h.
| __O uint32_t EMAC_T::TXST |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | TXST | Transmit Start Demand |
| If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled, the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted. | ||
| After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission. | ||
| The EMAC_TXST is a write only register and read from this register is undefined. | ||
| The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state. |
Definition at line 12583 of file NUC472_442.h.
| __IO uint32_t SC_T::UARTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | UARTEN | UART Mode Enable Control |
| 0 = Smart Card mode. | ||
| 1 = UART mode. | ||
| Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0. | ||
| Note2: When operating in Smart Card mode, user must set SC_UARTCTL [7:0] = 00. | ||
| Note3: When UART is enabled, hardware will generate a reset to resetFIFO and internal state machine. | ||
| [4:5] | WLS | Data Length |
| 00 = Character Data Length is 8 bits. | ||
| 01 = Character Data Length is 7 bits. | ||
| 10 = Character Data length is 6 bits. | ||
| 11 = Character Data Length is 5 bits. | ||
| Note: In smart card mode, this WLS must be '00' | ||
| [6] | PBOFF | Parity Bit Disable Control |
| 0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data. | ||
| 1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. | ||
| Note: In smart card mode, this field must be '0' (default setting is with parity bit) | ||
| [7] | OPE | Odd Parity Enable Control |
| 0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
| 1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
| Note: This bit has effect only when PBOFF bit is '0'. |
Definition at line 21714 of file NUC472_442.h.
| __IO uint32_t CAP_T::UBA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | BASEADDR | System Memory Planar U Base Address |
| Word aligns address; ignore the bits [1:0]. |
Definition at line 2160 of file NUC472_442.h.
| __IO uint32_t EMAC_T::UPDSEC |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SEC | Time Stamp Counter Second Update |
| When TSIEN (EMAC_TSCTL[1]) is high. | ||
| EMAC loads this 32-bit value to EMAC_TSSEC directly. | ||
| When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value. |
Definition at line 13205 of file NUC472_442.h.
| __IO uint32_t EMAC_T::UPDSUBSEC |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SUBSEC | Time Stamp Counter Sub-Second Update |
| When TSIEN (EMAC_TSCTL[1]) is high. | ||
| EMAC loads this 32-bit value to EMAC_TSSUBSEC directly. | ||
| When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value. |
Definition at line 13219 of file NUC472_442.h.
| __IO uint32_t SYS_T::USBPHY |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | USBROLE | USB Role Configuration (Write Protect) |
| USB role configuration can be from ROMMAP or software setting if software setting option, controlled by ROMMAP, is enabled. | ||
| 00 = Standard USB device. | ||
| 01 = Standard USB host. | ||
| 10 = ID dependent device. | ||
| 11 = On-The-Go device. | ||
| [8] | LDO33EN | LDO33 Enable Control (Write Protect) |
| 0 = USB LDO33 Disabled. | ||
| 1 = USB LDO33 Enabled. |
Definition at line 23674 of file NUC472_442.h.
| __IO uint32_t CAP_T::VBA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | BASEADDR | System Memory Planar V Base Address |
| Word aligns address; ignore the bits [1:0]. |
Definition at line 2172 of file NUC472_442.h.
| __I uint32_t SYS_T::VCID |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | VCID | Hardware Version Control (Ready Only) |
| These registers repress hardware version. | ||
| These bits are the read protected bits. | ||
| It means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address GCR_BA+0x100. |
Definition at line 23615 of file NUC472_442.h.
| __IO uint32_t ACMP_T::VREF |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | CRVCTL | Comparator Reference Voltage Setting |
| CRV = CRV source voltage * (1/6+VREF[3:0]/24). | ||
| [6] | CRVSSEL | CRV Source Voltage Selection |
| 0 = VDDA is selected as CRV source voltage. | ||
| 1 = Internal reference voltage is selected as CRV source voltage. | ||
| [7] | IREFSEL | Internal Reference Selection |
| 0 = Band-gap voltage is selected as internal reference. | ||
| 1 = CRV is selected as internal reference. |
Definition at line 306 of file NUC472_442.h.
| __IO uint32_t SYS_T::VREFCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:4] | VREFCTL | Vref control bits (Write Protect) |
| 00011=Vref is internal 2.65V | ||
| 00111=Vref is internal 2.048V | ||
| 01011=Vref is internal 3.072V | ||
| 01111=Vref is internal 4.096V | ||
| 10000=Vref is from AVDD | ||
| Others=Reserved | ||
| [8] | ADCMODESEL | ADC IP Selection (Write Protect) |
| 0 = ADC mode. | ||
| 1 = E ADC mode. | ||
| [9] | PWMSYNCMODE | PWM SYNC MODE (Write Protect) |
| 0 = PWM SYNC MODE Disabled; PWM engine clock can different with HCLK. | ||
| 1 = PWM SYNC MODE Enabled; PWM engine clock is same as HCLK. |
Definition at line 23655 of file NUC472_442.h.
| __IO uint32_t RTC_T::WEEKDAY |
| Bits | Field | Descriptions |
|---|---|---|
| [0:2] | WEEKDAY | Day Of The Week Bits |
| 000 = Sunday. | ||
| 001 = Monday. | ||
| 010 = Tuesday. | ||
| 011 = Wednesday. | ||
| 100 = Thursday. | ||
| 101 = Friday. | ||
| 110 = Saturday. | ||
| 111 = Reserved |
Definition at line 20515 of file NUC472_442.h.
| __IO uint32_t I2C_T::WKCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WKEN | I2C Wake-Up Enable Control |
| 0 = I2C wake-up function Disabled. | ||
| 1 = I2C wake-up function Enabled. |
Definition at line 17064 of file NUC472_442.h.
| __IO uint32_t I2C_T::WKSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WKIF | I2C Wake-Up Flag |
| 0 = No wake up occurred. | ||
| 1 = Wake up from Power-down mode. | ||
| Note: Software can write 1 to clear this bit. |
Definition at line 17078 of file NUC472_442.h.
| __IO uint32_t CAN_T::WU_EN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WAKUP_EN | Wake-Up Enable Control |
| 0 = The wake-up function Disabled. | ||
| 1 = The wake-up function Enabled. | ||
| Note: User can wake-up system when there is a falling edge in the CAN_Rx pin. |
Definition at line 1428 of file NUC472_442.h.
| __IO uint32_t CAN_T::WU_STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WAKUP_STS | Wake-Up Status |
| 0 = No wake-up event occurred. | ||
| 1 = Wake-up event occurred. | ||
| Note: This bit can be cleared by writing '0'. |
Definition at line 1442 of file NUC472_442.h.
| __IO uint32_t CAP_T::YBA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | BASEADDR | System Memory Planar Y Base Address |
| Word aligns address; ignore the bits [1:0]. |
Definition at line 2148 of file NUC472_442.h.


--- layout: post status: publish published: true title: Give-away for 100th Podcast Episode author: display_name: Corey Fineran login: Corey email<EMAIL_ADDRESS>url: '' author_login: Corey author_email<EMAIL_ADDRESS>wordpress_id: 6062 wordpress_url: http://ivyenvy.com/?p=6062 date: '2011-08-10 13:05:39 +0000' date_gmt: '2011-08-10 18:05:39 +0000' categories: - Ivy Envy - Live Broadcast tags: - 100th Episode - Mark and Gracie's comments: [] ---
In case you missed the news, we will be recording the 100th episode of the Ivy Envy Podcast this Saturday evening. We will celebrate the milestone by doing the show live and broadcasting both the audio and video to our website. The live show will start at 7pm and all you need to do is click on the "Live Broadcast" button, and play either the UStream (video and audio) or Mixlr (just audio) feed. We will be able to take your phone calls during the show and we'd love to hear from you and talk about the Cubs.
We will have a few neat things to give away during the show. We will announce those over the next few days. Anyone that calls in to the live-show will be eligible to win those prizes.
We do have one prize that we will take entries for ahead of time.
Mark and Gracie's will be giving away a little girl's (up to 5T) Cubs dress and hair-bow.
This would be a great addition to any little girl's Cubs wardrobe. To win the dress and hair-bow, simply "like" us on Facebook and leave a comment under the appropriate post. You can also e-mail me -<EMAIL_ADDRESS>to enter for the dress.
Thanks to Mark and Gracie's for their support. You can check out their website with photos of all of their products here and "like" them on Facebook.


nips nips2001 nips2001-171 nips2001-171-reference knowledge-graph by maker-knowledge-mining
Source: pdf
Author: Hongyuan Zha, Xiaofeng He, Chris Ding, Ming Gu, Horst D. Simon
Abstract: The popular K-means clustering partitions a data set by minimizing a sum-of-squares cost function. A coordinate descend method is then used to find local minima. In this paper we show that the minimization can be reformulated as a trace maximization problem associated with the Gram matrix of the data vectors. Furthermore, we show that a relaxed version of the trace maximization problem possesses global optimal solutions which can be obtained by computing a partial eigendecomposition of the Gram matrix, and the cluster assignment for each data vectors can be found by computing a pivoted QR decomposition of the eigenvector matrix. As a by-product we also derive a lower bound for the minimum of the sum-of-squares cost function. 1
[1] P. S. Bradley and Usama M. Fayyad. (1998). R efining Initial Points for K-Means Clustering. Proc. 15th International Conf. on Machine Learning, 91- 99.
[2] P. S. Bradley, K. Bennett and A. Demiritz. Constrained K-means Clustering. Microsoft Research, MSR-TR-2000-65, 2000.
[3] M. Girolani. (2001). Mercer Kernel Based Clustering in Feature Space. To appear in IEEE Transactions on Neural Networks.
[4] G. Golub and C. Van Loan . (1996) . Matrix Computations. Johns Hopkins University Press, 3rd Edition.
[5] Ming Gu, Hongyuan Zha, Chris Ding, Xiaofeng He and Horst Simon. (2001) . Spectral Embedding for K- Way Graph Clustering. Technical Report, Department of Computer Science and Engineering, CSE-OI-007, Pennsylvania State University.
[6] J.A. Hartigan and M.A. Wong. (1979). A K-means Clustering Algorithm. Applied Statistics, 28:100- 108.
[7] L. Lovasz and M.D. Plummer. (1986) Matching Theory. Amsterdam: North Holland.
[8] A. McCallum. Bow: A toolkit for statistical language modeling, text retrieval, classification and clustering. http : //www . CS. cmu. edu/ mccallum/bow.
[9] B. Schi:ilkopf, A. Smola and K.R. Miiller. (1998). Nonlinear Component Analysis as a Kernel Eigenvalue Problem. N eural Computation, 10: 1299- 1219.
[10] N . Slonim and N. Tishby. (2000). Document clustering using word clusters via the information bottleneck method. Proceedings of SIGIR-2000.
[11] G.W. Stewart and J.G. Sun. (1990). Matrix Perturbation Theory. Academic Press, San Diego , CA.


Maintenance at Baiyappanahalli Yard to hit train traffic
Several trains between Bengaluru and Vijayawada short-terminated
by Staff ReporterEight trains running to and from Bengaluru have been short-terminated due to remodeling work at the Baiyappanahalli Yard.
The 56504 Vjiayawada-Bengaluru Cantonment Passenger will be short-terminated between Yelahanka and Bengaluru Cantonment from November 14 to December 7. The 56503 Bengaluru Cantonment-Vijayawada Passenger will be short-terminated between the same locations from November 15 to December 8.
The 22353 Patna-Banaswadi Humsafar Express will be short-terminated between Krishnarajapuram and Banaswadi on November 14, 21, 28 and December 5. The 22354 Banaswadi-Patna Humsafar Express will also be short-terminated between the same locations on November 17 and 24 and December 1 and 8.
The 08301 Sambalpur-Banaswadi Express will be short-terminated from Krishnarajapuram to Banaswadi on November 20, 27 and December 4. The 08302 Banaswadi-Sambalpur Express will be short-terminated between Banaswadi and Krishnarajapuram on November 21, 28 and December 5.
The 12889 Tatanagar-Yesvantpur Superfast Express will be short-terminated between Krishnarajapuram and Banaswadi on November 15, 22 and 29, while the 12890 Yesvantpur-Tatanagar SF Express will be short-terminated between the same locations on November 18, 25 and December 2.


*All crowd predictions assume that the number of photos taken at a specific time and place, then uploaded to Flickr as public, is proportional to the size of overall crowds at that time/place. CrowdScore estimates the size of the predicted crowd as a percentage of the size of the largest typical crowds seen at a given location.


☆'s MHGen Talisman Editor requires JavaScript -- sorry about that!
I promise there are no trackers or anything.
Here's the source if you wanna check it out.
I hope you enjoy my work!


Dolphin utilizes data-over-sound technology to effectively exchange information between devices.
$$$


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#include <PathDependentDiscrete.h>
§ PathDependentDiscrete() [1/2]
| PathDependentDiscrete::PathDependentDiscrete |
( |
const MJArray & |
LookAtTimes_, |
|
|
double |
DeliveryTime_, |
|
|
double |
Barrier_, |
|
|
const PayOffBridge & |
ThePayOff_, |
|
|
double |
Rebate_ = 0.0 |
|
) |
| |
§ PathDependentDiscrete() [2/2]
| PathDependentDiscrete::PathDependentDiscrete |
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const MJArray & |
LookAtTimes_, |
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double |
DeliveryTime_, |
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double |
Barrier_, |
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double |
Rebate_ = 0.0 |
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§ ~PathDependentDiscrete()
| virtual PathDependentDiscrete::~PathDependentDiscrete |
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§ MaxNumberOfCashFlows()
| virtual unsigned long PathDependentDiscrete::MaxNumberOfCashFlows |
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const |
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§ PossibleCashFlowTimes()
| virtual MJArray PathDependentDiscrete::PossibleCashFlowTimes |
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const |
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§ Barrier
| double PathDependentDiscrete::Barrier |
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§ DeliveryTime
| double PathDependentDiscrete::DeliveryTime |
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§ NumberOfTimes
| unsigned long PathDependentDiscrete::NumberOfTimes |
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§ Rebate
| double PathDependentDiscrete::Rebate |
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§ ThePayOff
The documentation for this class was generated from the following file: