#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\fpga_J-2015.03M-SP1-2 #OS: Windows 8 6.2 #Hostname: LAPTOP-UCQD4H1A #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @N:CD720 : std.vhd(146) | Setting time resolution to ns @N: : CU_TOP.vhd(20) | Top entity is set to CU_TOP. File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\Clock_gen.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\Rx_async.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\Tx_async.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\fifo_256x8_pa3.vhd changed - recompiling File C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\fpga_J-2015.03M-SP1-2\lib\proasic\proasic3.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\coreuart_pkg.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\components.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\CoreUART.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\CU_TOP.vhd changed - recompiling VHDL syntax check successful! File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\Clock_gen.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\Rx_async.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\Tx_async.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\fifo_256x8_pa3.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\coreuart_pkg.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\components.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\FPGA_UART\rtl\vhdl\core\CoreUART.vhd changed - recompiling File C:\Users\rozen\Gitrepos\CU_Droptest\component\work\CU_TOP\CU_TOP.vhd changed - recompiling @N:CD231 : std1164.vhd(890) | Using onehot encoding for type mvl9plus ('U'="1000000000") @N:CD630 : CU_TOP.vhd(20) | Synthesizing work.cu_top.rtl @N:CD630 : WOLF_CONTROLLER.vhd(23) | Synthesizing work.wolf_controller.architecture_wolf_controller @N:CD231 : WOLF_CONTROLLER.vhd(84) | Using onehot encoding for type main_state (start="10000") @N:CD231 : WOLF_CONTROLLER.vhd(88) | Using onehot encoding for type uart_state (start="10000") Post processing for work.wolf_controller.architecture_wolf_controller @W:CL240 : WOLF_CONTROLLER.vhd(53) | led2 is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : WOLF_CONTROLLER.vhd(52) | led1 is not assigned a value (floating) -- simulation mismatch possible. @A:CL282 : WOLF_CONTROLLER.vhd(124) | Feedback mux created for signal uart_data_buffer_in[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : WOLF_CONTROLLER.vhd(181) | Feedback mux created for signal main_current_state[0:4] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : WOLF_CONTROLLER.vhd(124) | Feedback mux created for signal uart_current_state[0:4] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL190 : WOLF_CONTROLLER.vhd(181) | Optimizing register bit main_uart_data_out(3) to a constant 0 @W:CL190 : WOLF_CONTROLLER.vhd(181) | Optimizing register bit main_uart_data_out(4) to a constant 0 @W:CL190 : WOLF_CONTROLLER.vhd(181) | Optimizing register bit main_uart_data_out(5) to a constant 0 @W:CL190 : WOLF_CONTROLLER.vhd(181) | Optimizing register bit main_uart_data_out(6) to a constant 0 @W:CL190 : WOLF_CONTROLLER.vhd(181) | Optimizing register bit main_uart_data_out(7) to a constant 0 @W:CL279 : WOLF_CONTROLLER.vhd(181) | Pruning register bits 7 to 3 of main_uart_data_out(7 downto 0) @N:CD630 : UART_reset_monitor.vhd(23) | Synthesizing work.uart_reset_monitor.architecture_uart_reset_monitor @N:CD233 : UART_reset_monitor.vhd(53) | Using sequential encoding for type reset_state Post processing for work.uart_reset_monitor.architecture_uart_reset_monitor @A:CL282 : UART_reset_monitor.vhd(65) | Feedback mux created for signal reset_next_state[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : UART_reset_monitor.vhd(65) | Feedback mux created for signal reset_current_state[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N:CD630 : System_clock.vhd(44) | Synthesizing work.system_clock.behaviour Post processing for work.system_clock.behaviour @N:CD630 : proasic3.vhd(2198) | Synthesizing proasic3.or2.syn_black_box Post processing for proasic3.or2.syn_black_box @N:CD630 : CoreUART.vhd(34) | Synthesizing coreuart_lib.cu_top_fpga_uart_coreuart.translated @W:CD434 : CoreUART.vhd(265) | Signal rx_dout_reg in the sensitivity list is not used in the process @W:CD434 : CoreUART.vhd(265) | Signal parity_err_xhdl1 in the sensitivity list is not used in the process @W:CD604 : CoreUART.vhd(392) | OTHERS clause is not synthesized @N:CD364 : CoreUART.vhd(450) | Removed redundant assignment @N:CD630 : Rx_async.vhd(33) | Synthesizing coreuart_lib.cu_top_fpga_uart_rx_async.translated @N:CD233 : Rx_async.vhd(64) | Using sequential encoding for type receive_states @N:CD364 : Rx_async.vhd(233) | Removed redundant assignment @W:CD604 : Rx_async.vhd(253) | OTHERS clause is not synthesized @N:CD364 : Rx_async.vhd(256) | Removed redundant assignment @W:CD604 : Rx_async.vhd(318) | OTHERS clause is not synthesized @W:CD604 : Rx_async.vhd(423) | OTHERS clause is not synthesized Post processing for coreuart_lib.cu_top_fpga_uart_rx_async.translated @N:CL177 : Rx_async.vhd(443) | Sharing sequential element clear_framing_error_en_i. @N:CD630 : Tx_async.vhd(33) | Synthesizing coreuart_lib.cu_top_fpga_uart_tx_async.translated @N:CD364 : Tx_async.vhd(311) | Removed redundant assignment Post processing for coreuart_lib.cu_top_fpga_uart_tx_async.translated @W:CL190 : Tx_async.vhd(134) | Optimizing register bit fifo_read_en0 to a constant 1 @W:CL169 : Tx_async.vhd(134) | Pruning register fifo_read_en0 @N:CD630 : Clock_gen.vhd(35) | Synthesizing coreuart_lib.cu_top_fpga_uart_clock_gen.rtl @N:CD364 : Clock_gen.vhd(109) | Removed redundant assignment @N:CD364 : Clock_gen.vhd(122) | Removed redundant assignment @N:CD364 : Clock_gen.vhd(135) | Removed redundant assignment @N:CD364 : Clock_gen.vhd(148) | Removed redundant assignment @N:CD364 : Clock_gen.vhd(161) | Removed redundant assignment @N:CD364 : Clock_gen.vhd(174) | Removed redundant assignment @N:CD364 : Clock_gen.vhd(187) | Removed redundant assignment @W:CD604 : Clock_gen.vhd(198) | OTHERS clause is not synthesized Post processing for coreuart_lib.cu_top_fpga_uart_clock_gen.rtl Post processing for coreuart_lib.cu_top_fpga_uart_coreuart.translated @W:CL169 : CoreUART.vhd(439) | Pruning register overflow_reg_3 @W:CL169 : CoreUART.vhd(414) | Pruning register rx_dout_reg_empty_5 @W:CL169 : CoreUART.vhd(399) | Pruning register rx_dout_reg_5(7 downto 0) @W:CL169 : CoreUART.vhd(367) | Pruning register rx_state_4(1 downto 0) @W:CL169 : CoreUART.vhd(350) | Pruning register clear_framing_error_reg0_3 @W:CL169 : CoreUART.vhd(350) | Pruning register clear_framing_error_reg_3 @W:CL169 : CoreUART.vhd(333) | Pruning register clear_parity_reg0_3 @W:CL169 : CoreUART.vhd(333) | Pruning register clear_parity_reg_3 @W:CL169 : CoreUART.vhd(245) | Pruning register fifo_write_tx_4 @N:CD630 : CUTTER_PWM.vhd(23) | Synthesizing work.cutter_pwm.logic Post processing for work.cutter_pwm.logic @A:CL282 : CUTTER_PWM.vhd(48) | Feedback mux created for signal half_duty_new[4:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : CUTTER_PWM.vhd(48) | Feedback mux created for signal half_duty_0[4:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N:CD630 : proasic3.vhd(2858) | Synthesizing proasic3.clkint.syn_black_box Post processing for proasic3.clkint.syn_black_box Post processing for work.cu_top.rtl @W:CL189 : CUTTER_PWM.vhd(48) | Register bit half_duty_new(4) is always 0, optimizing ... @W:CL260 : CUTTER_PWM.vhd(48) | Pruning register bit 4 of half_duty_new(4 downto 0) @W:CL189 : CUTTER_PWM.vhd(48) | Register bit half_duty_0(4) is always 0, optimizing ... @W:CL260 : CUTTER_PWM.vhd(48) | Pruning register bit 4 of half_duty_0(4 downto 0) @W:CL246 : CUTTER_PWM.vhd(34) | Input port bits 3 to 0 of duty(7 downto 0) are unused @N:CL201 : Tx_async.vhd(134) | Trying to extract state machine for register xmit_state Extracted state machine for register xmit_state State machine has 6 reachable states with original encodings of:<PHONE_NUMBER>0000000000000000000000<PHONE_NUMBER>0000000000000000000001<PHONE_NUMBER>0000000000000000000010<PHONE_NUMBER>0000000000000000000011<PHONE_NUMBER>0000000000000000000100<PHONE_NUMBER>0000000000000000000101 @W:CL159 : Tx_async.vhd(45) | Input tx_dout_reg is unused @W:CL159 : Tx_async.vhd(46) | Input fifo_empty is unused @W:CL159 : Tx_async.vhd(47) | Input fifo_full is unused @N:CL201 : Rx_async.vhd(264) | Trying to extract state machine for register rx_state Extracted state machine for register rx_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL190 : UART_reset_monitor.vhd(65) | Optimizing register bit reset_counter(4) to a constant 0 @W:CL260 : UART_reset_monitor.vhd(65) | Pruning register bit 4 of reset_counter(4 downto 0) At c_vhdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 79MB peak: 81MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Jun 22 17:23:07 2017 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Jun 22 17:23:08 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Jun 22 17:23:08 2017 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File C:\Users\rozen\Gitrepos\CU_Droptest\synthesis\synwork\CU_TOP_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Jun 22 17:23:09 2017 ###########################################################] Pre-mapping Report Synopsys Microsemi Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:42:41 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) Linked File: CU_TOP_scck.rpt Printing clock summary report in "C:\Users\rozen\Gitrepos\CU_Droptest\synthesis\CU_TOP_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) @N:BN362 : rx_async.vhd(443) | Removing sequential instance fifo_write_xhdl6 of view:PrimLib.dffs(prim) in hierarchy view:coreuart_lib.CU_TOP_FPGA_UART_Rx_async(translated) because there are no references to its outputs @N:BN362 : rx_async.vhd(443) | Removing sequential instance clear_parity_en_xhdl3 of view:PrimLib.dffr(prim) in hierarchy view:coreuart_lib.CU_TOP_FPGA_UART_Rx_async(translated) because there are no references to its outputs @N:BN362 : rx_async.vhd(194) | Removing sequential instance overflow_xhdl1 of view:PrimLib.dffre(prim) in hierarchy view:coreuart_lib.CU_TOP_FPGA_UART_Rx_async(translated) because there are no references to its outputs @N:BN362 : rx_async.vhd(399) | Removing sequential instance parity_err_xhdl2 of view:PrimLib.dffre(prim) in hierarchy view:coreuart_lib.CU_TOP_FPGA_UART_Rx_async(translated) because there are no references to its outputs @N:BN362 : rx_async.vhd(218) | Removing sequential instance framing_error_i of view:PrimLib.dffre(prim) in hierarchy view:coreuart_lib.CU_TOP_FPGA_UART_Rx_async(translated) because there are no references to its outputs @N:BN362 : rx_async.vhd(264) | Removing sequential instance overflow_int of view:PrimLib.dffre(prim) in hierarchy view:coreuart_lib.CU_TOP_FPGA_UART_Rx_async(translated) because there are no references to its outputs @N:BN362 : rx_async.vhd(264) | Removing sequential instance framing_error_int of view:PrimLib.dffre(prim) in hierarchy view:coreuart_lib.CU_TOP_FPGA_UART_Rx_async(translated) because there are no references to its outputs Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 108MB peak: 109MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ------------------------------------------------------------------------------------------------------- CU_TOP|CLK 100.0 MHz 10.000 inferred Inferred_clkgroup_0 system_clock|m_time_inferred_clock[25] 100.0 MHz 10.000 inferred Inferred_clkgroup_1 ======================================================================================================= @W:MT530 : cutter_pwm.vhd(48) | Found inferred clock CU_TOP|CLK which controls 182 sequential elements including CUTTER_PWM_inst_0.pwm_out[0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : wolf_controller.vhd(108) | Found inferred clock system_clock|m_time_inferred_clock[25] which controls 13 sequential elements including WOLF_CONTROLLER_inst_0.sec_since_res[12:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Users\rozen\Gitrepos\CU_Droptest\synthesis\CU_TOP.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 46MB peak: 109MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Jun 22 17:23:11 2017 ###########################################################] Map & Optimize Report Synopsys Microsemi Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:42:41 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) @W:MO160 : rx_async.vhd(375) | Register bit rx_parity_calc is always 0, optimizing ... @N:BN362 : clock_gen.vhd(73) | Removing sequential instance baud_cntr_one of view:PrimLib.dffr(prim) in hierarchy view:coreuart_lib.CU_TOP_FPGA_UART_Clock_gen(rtl) because there are no references to its outputs Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB) @N: : cutter_pwm.vhd(48) | Found counter in view:work.CUTTER_PWM(logic) inst count_0[4:0] @N:MF176 : | Default generator successful @W:MO160 : cutter_pwm.vhd(48) | Register bit half_duty_0[3] is always 0, optimizing ... @W:MO160 : cutter_pwm.vhd(48) | Register bit half_duty_0[2] is always 0, optimizing ... @N: : clock_gen.vhd(90) | Found counter in view:coreuart_lib.CU_TOP_FPGA_UART_Clock_gen(rtl) inst baud_cntr[12:0] @N: : clock_gen.vhd(243) | Found counter in view:coreuart_lib.CU_TOP_FPGA_UART_Clock_gen(rtl) inst xmit_cntr[3:0] @N: : tx_async.vhd(238) | Found counter in view:coreuart_lib.CU_TOP_FPGA_UART_Tx_async(translated) inst xmit_bit_sel[3:0] Encoding state machine xmit_state[0:5] (view:coreuart_lib.CU_TOP_FPGA_UART_Tx_async(translated)) original code -> new code<PHONE_NUMBER>0000000000000000000000 -><PHONE_NUMBER>0000000000000000000000000001 -><PHONE_NUMBER>0000000000000000000000000010 -><PHONE_NUMBER>0000000000000000000000000011 -><PHONE_NUMBER>0000000000000000000000000100 -><PHONE_NUMBER>0000000000000000000000000101 -> 100000 @W:MO160 : tx_async.vhd(134) | Register bit xmit_state[1] is always 0, optimizing ... @N:BN362 : tx_async.vhd(299) | Removing sequential instance tx_parity of view:PrimLib.dffr(prim) in hierarchy view:coreuart_lib.CU_TOP_FPGA_UART_Tx_async(translated) because there are no references to its outputs @N: : rx_async.vhd(333) | Found counter in view:coreuart_lib.CU_TOP_FPGA_UART_Rx_async(translated) inst rx_bit_cnt[3:0] @N: : rx_async.vhd(169) | Found counter in view:coreuart_lib.CU_TOP_FPGA_UART_Rx_async(translated) inst receive_count[3:0] Encoding state machine rx_state[0:3] (view:coreuart_lib.CU_TOP_FPGA_UART_Rx_async(translated)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : rx_async.vhd(264) | No possible illegal states for state machine rx_state[0:3],safe FSM implementation is disabled @W:MO161 : rx_async.vhd(241) | Register bit last_bit[3] is always 1, optimizing ... @W:MO160 : rx_async.vhd(241) | Register bit last_bit[2] is always 0, optimizing ... @W:MO160 : rx_async.vhd(241) | Register bit last_bit[1] is always 0, optimizing ... @N:BN362 : rx_async.vhd(333) | Removing sequential instance rx_shift[8] of view:PrimLib.dffr(prim) in hierarchy view:coreuart_lib.CU_TOP_FPGA_UART_Rx_async(translated) because there are no references to its outputs @N: : system_clock.vhd(64) | Found counter in view:work.system_clock(behaviour) inst l_time[17:1] @N:MF238 : system_clock.vhd(94) | Found 8-bit incrementor, 'un1_s_time_0[7:0]' @N:MF238 : system_clock.vhd(94) | Found 7-bit incrementor, 'un1_s_time[6:0]' @N: : uart_reset_monitor.vhd(65) | Found counter in view:work.UART_reset_monitor(architecture_uart_reset_monitor) inst reset_counter[3:0] @N: : wolf_controller.vhd(108) | Found counter in view:work.WOLF_CONTROLLER(architecture_wolf_controller) inst sec_since_res[12:0] Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 110MB peak: 111MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 109MB peak: 111MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 111MB peak: 111MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 111MB peak: 112MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 112MB peak: 112MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 111MB peak: 112MB) Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 112MB peak: 112MB) Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 111MB peak: 112MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes --------------------------------------------------------------- OR2_0 / Y 164 : 150 asynchronous set/reset =============================================================== @N:FP130 : | Promoting Net OR2_0_Y on CLKINT I_11 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 111MB peak: 112MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 111MB peak: 112MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 168 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 13 clock pin(s) of sequential element(s) 0 instances converted, 13 sequential instances remain driven by gated/generated clocks ======================================== Non-Gated/Non-Generated Clocks ========================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ----------------------------------------------------------------------------------------------------------------- ClockId0002 CLK port 168 WOLF_CONTROLLER_inst_0.uart_next_state[0] ================================================================================================================= ========================================================================================== Gated/Generated Clocks =========================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 system_clock_inst_0.s_time_0[7] DFN0E1C1 13 WOLF_CONTROLLER_inst_0.sec_since_res[12] No generated or derived clock directive on output of sequential instance ============================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 111MB peak: 112MB) Writing Analyst data base C:\Users\rozen\Gitrepos\CU_Droptest\synthesis\synwork\CU_TOP_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 111MB peak: 112MB) Writing EDIF Netlist and constraint files J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 111MB peak: 112MB) Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 111MB peak: 112MB) @W:MT420 : | Found inferred clock CU_TOP|CLK with period 10.00ns. Please declare a user-defined clock on object "p:CLK" @W:MT420 : | Found inferred clock system_clock|m_time_inferred_clock[25] with period 10.00ns. Please declare a user-defined clock on object "n:system_clock_inst_0.m_time[25]" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Thu Jun 22 17:23:16 2017 # Top view: CU_TOP Library name: PA3 Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: proasic3 Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -1.170 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------- CU_TOP|CLK 100.0 MHz 81.0 MHz 10.000 12.339 -1.170 inferred Inferred_clkgroup_0 system_clock|m_time_inferred_clock[25] 100.0 MHz 109.7 MHz 10.000 9.114 0.886 inferred Inferred_clkgroup_1 ============================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CU_TOP|CLK CU_TOP|CLK | 10.000 -1.148 | 10.000 1.385 | 5.000 2.016 | 5.000 -1.170 system_clock|m_time_inferred_clock[25] CU_TOP|CLK | Diff grp - | No paths - | No paths - | No paths - system_clock|m_time_inferred_clock[25] system_clock|m_time_inferred_clock[25] | 10.000 0.886 | No paths - | No paths - | No paths - ======================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: CU_TOP|CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------- system_clock_inst_0.l_time[1] CU_TOP|CLK DFN0C1 Q MICRO_CLK_c 0.653 -1.170 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[1] CU_TOP|CLK DFN1C1 Q baud_cntr[1] 0.737 -1.148 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[0] CU_TOP|CLK DFN1C1 Q baud_cntr[0] 0.737 -1.009 system_clock_inst_0.l_time[2] CU_TOP|CLK DFN0C1 Q m_time[2] 0.527 -1.003 system_clock_inst_0.l_time[11] CU_TOP|CLK DFN0C1 Q m_time[11] 0.653 -0.935 system_clock_inst_0.l_time[10] CU_TOP|CLK DFN0E0C1 Q m_time[10] 0.653 -0.822 FPGA_UART.make_RX.rx_state[1] CU_TOP|CLK DFN1E1C1 Q rx_state[1] 0.737 -0.739 system_clock_inst_0.l_time[3] CU_TOP|CLK DFN0C1 Q m_time[3] 0.653 -0.665 FPGA_UART.make_RX.rx_state[0] CU_TOP|CLK DFN1E1C1 Q rx_state[0] 0.737 -0.600 system_clock_inst_0.l_time[6] CU_TOP|CLK DFN0C1 Q m_time[6] 0.653 -0.422 ================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------ system_clock_inst_0.flag CU_TOP|CLK DFN1C1 D flag_RNO 4.426 -1.170 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[12] CU_TOP|CLK DFN1C1 D baud_cntr_RNO[12] 9.427 -1.148 FPGA_UART.make_RX.receive_count[0] CU_TOP|CLK DFN1C1 D receive_count_RNO[0] 9.427 -0.739 FPGA_UART.make_RX.receive_count[1] CU_TOP|CLK DFN1C1 D receive_count_RNO[1] 9.461 -0.494 FPGA_UART.make_RX.receive_count[2] CU_TOP|CLK DFN1C1 D N_30 9.461 -0.494 FPGA_UART.make_RX.receive_count[3] CU_TOP|CLK DFN1C1 D N_28 9.461 -0.494 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[1] CU_TOP|CLK DFN1C1 D baud_cntr_RNO[1] 9.461 -0.182 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[11] CU_TOP|CLK DFN1C1 D baud_cntr_RNO[11] 9.427 -0.172 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[3] CU_TOP|CLK DFN1C1 D baud_cntr_RNO[3] 9.427 0.019 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[5] CU_TOP|CLK DFN1C1 D baud_cntr_RNO[5] 9.427 0.019 ========================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.574 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.426 - Propagation time: 5.596 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.170 Number of logic level(s): 3 Starting point: system_clock_inst_0.l_time[1] / Q Ending point: system_clock_inst_0.flag / D The start point is clocked by CU_TOP|CLK [falling] on pin CLK The end point is clocked by CU_TOP|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- system_clock_inst_0.l_time[1] DFN0C1 Q Out 0.653 0.653 - MICRO_CLK_c Net - - 1.526 - 7 system_clock_inst_0.l_time_RNITN5U[4] OR2B B In - 2.179 - system_clock_inst_0.l_time_RNITN5U[4] OR2B Y Out 0.627 2.807 - l_time_n4_0_o2_0 Net - - 0.322 - 1 system_clock_inst_0.l_time_RNIQFBS1[4] OR2 A In - 3.128 - system_clock_inst_0.l_time_RNIQFBS1[4] OR2 Y Out 0.363 3.491 - N_22 Net - - 1.423 - 6 system_clock_inst_0.flag_RNO NOR3B C In - 4.915 - system_clock_inst_0.flag_RNO NOR3B Y Out 0.360 5.275 - flag_RNO Net - - 0.322 - 1 system_clock_inst_0.flag DFN1C1 D In - 5.596 - ======================================================================================================= Total path delay (propagation time + setup) of 6.170 is 2.577(41.8%) logic and 3.592(58.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 10.575 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.148 Number of logic level(s): 9 Starting point: FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[1] / Q Ending point: FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[12] / D The start point is clocked by CU_TOP|CLK [rising] on pin CLK The end point is clocked by CU_TOP|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[1] DFN1C1 Q Out 0.737 0.737 - baud_cntr[1] Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI5ILP[0] OR2 B In - 1.123 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI5ILP[0] OR2 Y Out 0.646 1.769 - baud_cntr_c1 Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIPCG61[2] OR2 A In - 2.155 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIPCG61[2] OR2 Y Out 0.507 2.662 - baud_cntr_c2 Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIE8BJ1[3] OR2 A In - 3.048 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIE8BJ1[3] OR2 Y Out 0.507 3.556 - baud_cntr_c3 Net - - 0.806 - 3 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIC1N63[7] NOR2A B In - 4.362 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIC1N63[7] NOR2A Y Out 0.407 4.769 - un4_baud_cntr_10 Net - - 0.806 - 3 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI62IJ3[8] OR2A A In - 5.575 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI62IJ3[8] OR2A Y Out 0.537 6.112 - baud_cntr_c8 Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI14D04[9] OR2 A In - 6.498 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI14D04[9] OR2 Y Out 0.507 7.005 - baud_cntr_c9 Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI45084[10] OR2 A In - 7.391 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI45084[10] OR2 Y Out 0.507 7.898 - baud_cntr_c10 Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNO_0[12] OR2 B In - 8.284 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNO_0[12] OR2 Y Out 0.646 8.931 - baud_cntr_26_0 Net - - 0.322 - 1 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNO[12] AX1B B In - 9.252 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNO[12] AX1B Y Out 1.001 10.253 - baud_cntr_RNO[12] Net - - 0.322 - 1 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[12] DFN1C1 D In - 10.575 - ================================================================================================================================= Total path delay (propagation time + setup) of 11.148 is 6.578(59.0%) logic and 4.571(41.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 10.436 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.009 Number of logic level(s): 9 Starting point: FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[0] / Q Ending point: FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[12] / D The start point is clocked by CU_TOP|CLK [rising] on pin CLK The end point is clocked by CU_TOP|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[0] DFN1C1 Q Out 0.737 0.737 - baud_cntr[0] Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI5ILP[0] OR2 A In - 1.123 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI5ILP[0] OR2 Y Out 0.507 1.630 - baud_cntr_c1 Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIPCG61[2] OR2 A In - 2.016 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIPCG61[2] OR2 Y Out 0.507 2.523 - baud_cntr_c2 Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIE8BJ1[3] OR2 A In - 2.909 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIE8BJ1[3] OR2 Y Out 0.507 3.417 - baud_cntr_c3 Net - - 0.806 - 3 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIC1N63[7] NOR2A B In - 4.223 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNIC1N63[7] NOR2A Y Out 0.407 4.630 - un4_baud_cntr_10 Net - - 0.806 - 3 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI62IJ3[8] OR2A A In - 5.436 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI62IJ3[8] OR2A Y Out 0.537 5.973 - baud_cntr_c8 Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI14D04[9] OR2 A In - 6.359 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI14D04[9] OR2 Y Out 0.507 6.866 - baud_cntr_c9 Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI45084[10] OR2 A In - 7.252 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNI45084[10] OR2 Y Out 0.507 7.759 - baud_cntr_c10 Net - - 0.386 - 2 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNO_0[12] OR2 B In - 8.145 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNO_0[12] OR2 Y Out 0.646 8.792 - baud_cntr_26_0 Net - - 0.322 - 1 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNO[12] AX1B B In - 9.113 - FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr_RNO[12] AX1B Y Out 1.001 10.114 - baud_cntr_RNO[12] Net - - 0.322 - 1 FPGA_UART.make_CU_TOP_FPGA_UART_Clock_gen.baud_cntr[12] DFN1C1 D In - 10.436 - ================================================================================================================================= Total path delay (propagation time + setup) of 11.009 is 6.438(58.5%) logic and 4.571(41.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.461 - Propagation time: 5.464 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.003 Number of logic level(s): 3 Starting point: system_clock_inst_0.l_time[2] / Q Ending point: system_clock_inst_0.flag / D The start point is clocked by CU_TOP|CLK [falling] on pin CLK The end point is clocked by CU_TOP|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- system_clock_inst_0.l_time[2] DFN0C1 Q Out 0.527 0.527 - m_time[2] Net - - 1.184 - 4 system_clock_inst_0.l_time_RNITN5U[3] OR2B A In - 1.710 - system_clock_inst_0.l_time_RNITN5U[3] OR2B Y Out 0.488 2.199 - l_time_n3_0_o2_out Net - - 0.386 - 2 system_clock_inst_0.l_time_RNIQFBS1[4] OR2 B In - 2.584 - system_clock_inst_0.l_time_RNIQFBS1[4] OR2 Y Out 0.646 3.231 - N_22 Net - - 1.423 - 6 system_clock_inst_0.flag_RNO NOR3B C In - 4.654 - system_clock_inst_0.flag_RNO NOR3B Y Out 0.488 5.143 - flag_RNO Net - - 0.322 - 1 system_clock_inst_0.flag DFN1C1 D In - 5.464 - ======================================================================================================= Total path delay (propagation time + setup) of 6.003 is 2.688(44.8%) logic and 3.314(55.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.000 - Setup time: 0.574 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.426 - Propagation time: 5.361 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.935 Number of logic level(s): 4 Starting point: system_clock_inst_0.l_time[11] / Q Ending point: system_clock_inst_0.flag / D The start point is clocked by CU_TOP|CLK [falling] on pin CLK The end point is clocked by CU_TOP|CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- system_clock_inst_0.l_time[11] DFN0C1 Q Out 0.653 0.653 - m_time[11] Net - - 0.806 - 3 system_clock_inst_0.l_time_RNIRON3[10] NOR2B B In - 1.460 - system_clock_inst_0.l_time_RNIRON3[10] NOR2B Y Out 0.627 2.087 - l_m6_0_a2_5_0 Net - - 0.322 - 1 system_clock_inst_0.l_time_RNI4TT11[8] NOR3C C In - 2.409 - system_clock_inst_0.l_time_RNI4TT11[8] NOR3C Y Out 0.641 3.050 - l_m6_0_a2_5 Net - - 0.386 - 2 system_clock_inst_0.flag_RNO_0 NOR3C C In - 3.436 - system_clock_inst_0.flag_RNO_0 NOR3C Y Out 0.641 4.077 - un15_m1_0_a2_3 Net - - 0.322 - 1 system_clock_inst_0.flag_RNO NOR3B A In - 4.399 - system_clock_inst_0.flag_RNO NOR3B Y Out 0.641 5.040 - flag_RNO Net - - 0.322 - 1 system_clock_inst_0.flag DFN1C1 D In - 5.361 - ======================================================================================================= Total path delay (propagation time + setup) of 5.935 is 3.778(63.7%) logic and 2.157(36.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: system_clock|m_time_inferred_clock[25] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------ WOLF_CONTROLLER_inst_0.sec_since_res[1] system_clock|m_time_inferred_clock[25] DFN1C1 Q sec_since_res[1] 0.580 0.886 WOLF_CONTROLLER_inst_0.sec_since_res[0] system_clock|m_time_inferred_clock[25] DFN1C1 Q sec_since_res[0] 0.580 1.271 WOLF_CONTROLLER_inst_0.sec_since_res[2] system_clock|m_time_inferred_clock[25] DFN1C1 Q sec_since_res[2] 0.580 1.370 WOLF_CONTROLLER_inst_0.sec_since_res[4] system_clock|m_time_inferred_clock[25] DFN1C1 Q sec_since_res[4] 0.580 2.828 WOLF_CONTROLLER_inst_0.sec_since_res[3] system_clock|m_time_inferred_clock[25] DFN1C1 Q sec_since_res[3] 0.580 2.831 WOLF_CONTROLLER_inst_0.sec_since_res[8] system_clock|m_time_inferred_clock[25] DFN1C1 Q sec_since_res[8] 0.737 3.311 WOLF_CONTROLLER_inst_0.sec_since_res[7] system_clock|m_time_inferred_clock[25] DFN1C1 Q sec_since_res[7] 0.737 3.328 WOLF_CONTROLLER_inst_0.sec_since_res[5] system_clock|m_time_inferred_clock[25] DFN1C1 Q sec_since_res[5] 0.737 4.114 WOLF_CONTROLLER_inst_0.sec_since_res[6] system_clock|m_time_inferred_clock[25] DFN1C1 Q sec_since_res[6] 0.737 4.220 WOLF_CONTROLLER_inst_0.sec_since_res[9] system_clock|m_time_inferred_clock[25] DFN1C1 Q sec_since_res[9] 0.737 4.359 ================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------- WOLF_CONTROLLER_inst_0.sec_since_res[9] system_clock|m_time_inferred_clock[25] DFN1C1 D N_67_i 9.461 0.886 WOLF_CONTROLLER_inst_0.sec_since_res[8] system_clock|m_time_inferred_clock[25] DFN1C1 D N_66_i 9.427 1.420 WOLF_CONTROLLER_inst_0.sec_since_res[7] system_clock|m_time_inferred_clock[25] DFN1C1 D N_65_i 9.461 1.959 WOLF_CONTROLLER_inst_0.sec_since_res[6] system_clock|m_time_inferred_clock[25] DFN1C1 D N_64_i 9.427 2.914 WOLF_CONTROLLER_inst_0.sec_since_res[10] system_clock|m_time_inferred_clock[25] DFN1C1 D sec_since_res_RNO[10] 9.461 3.311 WOLF_CONTROLLER_inst_0.sec_since_res[5] system_clock|m_time_inferred_clock[25] DFN1C1 D N_62_i 9.461 3.453 WOLF_CONTROLLER_inst_0.sec_since_res[11] system_clock|m_time_inferred_clock[25] DFN1C1 D sec_since_res_n11 9.461 3.728 WOLF_CONTROLLER_inst_0.sec_since_res[12] system_clock|m_time_inferred_clock[25] DFN1E0C1 E N_61 9.392 4.143 WOLF_CONTROLLER_inst_0.sec_since_res[4] system_clock|m_time_inferred_clock[25] DFN1C1 D N_60_i 9.427 4.402 WOLF_CONTROLLER_inst_0.sec_since_res[3] system_clock|m_time_inferred_clock[25] DFN1C1 D N_59_i 9.461 4.941 ========================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 8.575 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.886 Number of logic level(s): 5 Starting point: WOLF_CONTROLLER_inst_0.sec_since_res[1] / Q Ending point: WOLF_CONTROLLER_inst_0.sec_since_res[9] / D The start point is clocked by system_clock|m_time_inferred_clock[25] [rising] on pin CLK The end point is clocked by system_clock|m_time_inferred_clock[25] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------- WOLF_CONTROLLER_inst_0.sec_since_res[1] DFN1C1 Q Out 0.580 0.580 - sec_since_res[1] Net - - 1.526 - 7 WOLF_CONTROLLER_inst_0.sec_since_res_RNIPI6E1[0] OR3C C In - 2.106 - WOLF_CONTROLLER_inst_0.sec_since_res_RNIPI6E1[0] OR3C Y Out 0.666 2.772 - N_34 Net - - 0.806 - 3 WOLF_CONTROLLER_inst_0.sec_since_res_RNI4F0D2[4] OR3B C In - 3.578 - WOLF_CONTROLLER_inst_0.sec_since_res_RNI4F0D2[4] OR3B Y Out 0.751 4.329 - N_36 Net - - 0.806 - 3 WOLF_CONTROLLER_inst_0.sec_since_res_RNIJFQB3[5] OR3B C In - 5.136 - WOLF_CONTROLLER_inst_0.sec_since_res_RNIJFQB3[5] OR3B Y Out 0.751 5.886 - N_38 Net - - 0.806 - 3 WOLF_CONTROLLER_inst_0.sec_since_res_RNO_0[9] OR3B C In - 6.693 - WOLF_CONTROLLER_inst_0.sec_since_res_RNO_0[9] OR3B Y Out 0.751 7.444 - N_41 Net - - 0.322 - 1 WOLF_CONTROLLER_inst_0.sec_since_res_RNO[9] XNOR2 A In - 7.765 - WOLF_CONTROLLER_inst_0.sec_since_res_RNO[9] XNOR2 Y Out 0.488 8.253 - N_67_i Net - - 0.322 - 1 WOLF_CONTROLLER_inst_0.sec_since_res[9] DFN1C1 D In - 8.575 - ================================================================================================================= Total path delay (propagation time + setup) of 9.114 is 4.525(49.7%) logic and 4.588(50.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 111MB peak: 112MB) Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 111MB peak: 112MB) -------------------------------------------------------------------------------- Target Part: A3P250_VQFP100_STD Report for cell CU_TOP.rtl Core Cell usage: cell count area count*area AND2 1 1.0 1.0 AND3 7 1.0 7.0 AO1 1 1.0 1.0 AO13 2 1.0 2.0 AO1A 10 1.0 10.0 AO1B 1 1.0 1.0 AOI1 5 1.0 5.0 AOI1B 7 1.0 7.0 AX1 10 1.0 10.0 AX1A 1 1.0 1.0 AX1B 6 1.0 6.0 AX1C 5 1.0 5.0 AXOI4 1 1.0 1.0 AXOI5 1 1.0 1.0 CLKINT 3 0.0 0.0 GND 9 0.0 0.0 INV 13 1.0 13.0 MX2 13 1.0 13.0 MX2A 2 1.0 2.0 MX2B 3 1.0 3.0 MX2C 2 1.0 2.0 NOR2 16 1.0 16.0 NOR2A 28 1.0 28.0 NOR2B 42 1.0 42.0 NOR3 2 1.0 2.0 NOR3A 5 1.0 5.0 NOR3B 8 1.0 8.0 NOR3C 20 1.0 20.0 OA1 3 1.0 3.0 OA1A 1 1.0 1.0 OA1B 1 1.0 1.0 OA1C 3 1.0 3.0 OAI1 1 1.0 1.0 OR2 21 1.0 21.0 OR2A 11 1.0 11.0 OR2B 9 1.0 9.0 OR3 8 1.0 8.0 OR3A 2 1.0 2.0 OR3B 4 1.0 4.0 OR3C 5 1.0 5.0 VCC 9 0.0 0.0 XA1 4 1.0 4.0 XA1B 3 1.0 3.0 XA1C 1 1.0 1.0 XAI1A 1 1.0 1.0 XNOR2 8 1.0 8.0 XO1 2 1.0 2.0 XO1A 3 1.0 3.0 XOR2 21 1.0 21.0 DFN0C1 9 1.0 9.0 DFN0E0C1 8 1.0 8.0 DFN0E1C1 8 1.0 8.0 DFN1 2 1.0 2.0 DFN1C1 42 1.0 42.0 DFN1E0 14 1.0 14.0 DFN1E0C1 35 1.0 35.0 DFN1E0P1 3 1.0 3.0 DFN1E1 10 1.0 10.0 DFN1E1C1 42 1.0 42.0 DFN1E1P1 2 1.0 2.0 DFN1P1 6 1.0 6.0 ----- ---------- TOTAL 526 505.0 IO Cell usage: cell count INBUF 3 OUTBUF 10 ----- TOTAL 13 Core Cells : 505 of 6144 (8%) IO Cells : 13 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 47MB peak: 112MB) Process took 0h:00m:04s realtime, 0h:00m:04s cputime # Thu Jun 22 17:23:16 2017 ###########################################################]


WITNESS LIST State Recreational Resources Committee March 22, 2001-8:00A HB 1789 For: Palmquist, Michael (The American Legion) On: King, Jack (Texas Parks and Wildlife Department) Stiles, Frances (Texas Parks and Wildlife Department) Registering, but not testifying: For: Patterson, Jerry (Texas Coalition of Veterans Organization) HB 2608 For: Benson, Bob (Bat Conservation International) French, Barbara (Bat Conservation International) Sybert, Brian (Sierra Club, Lone Star Chapter) On: Ewart, Ned (Texas Pest Control Association)


The Python community is amazing at sharing detailed resources and helping beginners learn to program with the language. There are so many resources out there though that it can be difficult to know how to find them.
This page aggregates the best Python resources with a brief description of how it fits one's learning purpose.
Looking for information on Python development environments? There's a whole other page for editors and IDEs.
If you're learning your first programming language these books were written with you in mind. Developers learning Python as a second or later language should skip down to the next section for "experienced developers".
If you've never programmed before check out the Getting Started page on Learn To Code with Me by Laurence Bradford. She's done an incredible job of breaking down the steps beginners should take when they're uncertain about where to begin.
To get an introduction to both Python and Django at the same time, purchase Real Python by Fletcher, Michael, and Jeremy.
Learn Python the Hard Way is a free book by Zed Shaw.
Dive into Python 3 is an open source book provided under the Creative Commons license and available in HTML or PDF form.
Python for You and Me (pym) is an online book for people completely unfamiliar with the Python programming language.
A Byte of Python is a beginner's tutorial for the Python language.
Code Academy has a Python track for people completely new to programming.
Introduction to Programming with Python goes over the basic syntax and control structures in Python. The free book has numerous code examples to go along with each topic.
The O'Reilly book Think Python: How to Think Like a Computer Scientist is available in HTML form for free on the web.
Python Practice Book is a book of Python exercises to help you learn the basic language syntax.
Looking for ideas about what projects to use to learn to code? Check out this list of 5 programming project for Python beginners.
I wrote a quick blog post on learning Python that non-technical folks trying to learn to program may find useful.
Learn Python in y minutes provides a whirlwind tour of the Python language. The guide is especially useful if you're coming in with previous software development experience and want to quickly grasp how the language is structured.
Python for you and me is an approachable book with sections for Python syntax and the major language constructs. The book also contains a short guide at the end to get programmers to write their first Flask web application.
Kenneth Reitz's The Hitchhiker’s Guide to Python contains a wealth of information both on the Python programming language and the community.
How to Develop Quality Python Code is a good read to begin learning about development environments, application dependencies and project structure.
Google's Python Class contains lecture videos and exercises for learning Python.
Check out the Real Python! Blog for a great set of relevant posts about Python web development topics.
The Python Ecosystem: An Introduction provides context for virtual machines, Python packaging, pip, virutalenv and many other topics after learning the basic Python syntax.
The Python Subreddit rolls up great Python links and has an active community ready to answer questions from beginners and advanced Python developers alike.
Good to Great Python Reads is a collection of intermediate and advanced Python articles around the web focused on nuances and details of the Python language itself.
The blog Free Python Tips provides posts on Python topics as well as news for the Python ecosystem.
Python Books is a collection of freely available books on Python, Django, and data analysis.
Kate Heddleston gave a talk at PyCon 2014 called "Full-stack Python Web Applications" with clear visuals for how numerous layers of the Python web stack fit together. There are also slides available from the talk with all the diagrams.
My EuroPython 2014 "Full Stack Python" talk goes over each topic from this guide and provides context for how the pieces fit together. The talk slides are also available.
Neckbeard Republic provides free screencasts for learning intermediate topics. I typically prefer to learn by reading. However, these videos are helpful in seeing the code on the screen instead of just looking at static code snippets.
PyVideo organizes and indexes thousands of Python videos from both major conferences and meetups.
awesome-python is an incredible list of Python frameworks, libraries and software. I wish I had this page when I was just getting started.
easy-python is like awesome-python although instead of just a Git repository this site is in the Read the Docs format.
Python Weekly is a free weekly roundup of the latest Python articles, videos, projects, and upcoming events.
PyCoder's Weekly is another great free weekly email newsletter similar to Python Weekly. The best resources are generally covered in both newsletters but they often cover different articles and projects from around the web.
Import Python is a newer newsletter thank Python Weekly and PyCoder's Weekly. So far I've found this newsletter covers different sources from other newsletters. It's well worth subscribing to all three so you don't miss anything.


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Id: 241
Name: Mr. Marklovitz
Status: Alive
Species: Human
Type:
Gender: Male
OriginName: Earth (C-137)
OriginUrl: https://rickandmortyapi.com/api/location/1
LocationName: Earth (Replacement Dimension)
LocationUrl: https://rickandmortyapi.com/api/location/20
Image: https://rickandmortyapi.com/api/character/avatar/241.jpeg
Episode: ['https://rickandmortyapi.com/api/episode/4', 'https://rickandmortyapi.com/api/episode/16']
Url: https://rickandmortyapi.com/api/character/241
Created: 2017-12-30T17:46:19.052Z


{% load static %} {% include "home/includes/head.html" %} {% include "home/includes/extras/intro.html" %}
Easily find the shoes you've always wanted!
Spot-On, a powerful and curated group who mission is to make it easier for you to find original sneakers. Orginal sneakers is dominating the market and there are high profit of it: check the stock. People who buy these aunthentic sneakers travels to other states to hunt them. Our mission to bring it to them on their finger-nails
Our search box is the core heart of our design. It has been design to take user's description of a shoes and to crawl the database to return the expected sneakers that the user is looking for. Literrally, this will save users a ton of time
Our database is a combination of nike.com API and our own database of research description of popular sneakers. We have implemented it to march with user input. But it will add any unkown input if it encouters one. This help user's search
Crawl. Imaging a baby crawling on the floor to go get a toy but supper speed mode like turbo speed. That is how I technology called, crawl works. Our mission is to delivery fast searches
Front-end
Takes care of the entire HTML and the CSS implementation. Also the document the software documentation and architecture design.
Database
Takes care of the entire database. Use SQL to modified and implements the SQL interaction. Manages and update the database
Back-end
Handles all the job at the back-end. Takes finished front-end and database work and gives it a working functionality. Also, database creation, integration and management.


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Calculates the Most Probable Number for serial dilutions to quantify the concentration (density) of microbes in a laboratory sample. Currently implements the confidence interval approach described in Jarvis (2010) <doi:10.1111/j.1365-2672.2010.04792.x>.
| Version: | 0.1.0 |
| Depends: | R (≥ 3.4.0) |
| Imports: | stats (≥ 3.4.0) |
| Suggests: | knitr (≥ 1.20), rmarkdown (≥ 1.10), testthat (≥ 2.0.0) |
| Published: | 2018-09-16 |
| Author: | Martine Ferguson [aut] (original R code), John Ihrie [cre, aut] |
| Maintainer: | John Ihrie <John.Ihrie at fda.hhs.gov> |
| License: | Unlimited |
| URL: | https://mpncalc.galaxytrakr.org/ |
| NeedsCompilation: | no |
| CRAN checks: | MPN results |
| Reference manual: | MPN.pdf |
| Vignettes: |
MPN: Most Probable Number for Serial Dilutions |
| Package source: | MPN_0.1.0.tar.gz |
| Windows binaries: | r-devel: MPN_0.1.0.zip, r-release: MPN_0.1.0.zip, r-oldrel: MPN_0.1.0.zip |
| OS X binaries: | r-release: MPN_0.1.0.tgz, r-oldrel: MPN_0.1.0.tgz |
Please use the canonical form https://CRAN.R-project.org/package=MPN to link to this page.


_The_Rage:_Carrie_2_ (R) 1/2* (out of ****)
Why a sequel to _Carrie_, and why now?
What is compelling, however, is newcomer Emily Bergl, who takes center stage as Rachel Lang, another alienated teen at Bates High School who, like one Carrie White some twenty years before her, is blessed (cursed?) with the ability to move objects with her mind, or telekinesis. But this "Carrie" has been given a '90s makeover: this tough-talking Goth chick is no one's victim, unlike her predecessor. (She even gets to lose her virginity.) Sounds like a thankless task, but Bergl, while no Sissy Spacek, holds the audience's attention and interest well, infusing Rachel with the right amount of warmth and vulnerability beneath her rough facade.
But for all the contemporary touches and new plot wrinkles writer Rafael Moreu and director Katt Shea dress _The_Rage_ in, there's no hiding the fact that this is just about the same movie that came out in 1976. Telekinetic girl is picked on by peers. Peers humiliate her in big social event (here, a party instead of the prom). Girl takes violent revenge. Even the characters are direct analogues to the original. In addition to the obvious Rachel = Carrie, Jason London (as Rachel's boyfriend Jessie) is William Katt's sensitive Tommy; Nancy Allen's uberbitch Chris has been split into Rachel Blanchard's Monica and Charlotte Ayanna's Tracy; similarly, John Travolta's blowhard Billy is replaced by Dylan Bruno's Mark and Zachery Ty Bryan's Eric; and Rachel's religious, institutionalized mother (J. Smith-Cameron) is an extremely watered-down version of Carrie's frightening, religious fanatic mother (oh so indelibly played by Piper Laurie). Amy Irving, whose Sue Snell was the sole survivor of Carrie's prom night rampage, not only gets to reprise her character (and her character's role in the story) here, she also gets to assume the guidance counselor (read: caring adult) part originally held by Betty Buckley.
With Shea and Moreu so closely following the original, needless to say there are no surprises in _The_Rage_. But even without keeping the original in mind, there's nothing shocking about the film or its climactic explosion of violence--which can be directly attributed to the attitude alteration of the protagonist. Sure, making Rachel far from a meek girl is a very '90s feminist thing to do, but it also robs her eventual bad behavior of any resonance. A lot of the power of _Carrie_'s famous prom scene is that, while some payback is clearly in order, the fury of her vengeance comes as a shock, given how weak she had been throughout the film. With Rachel, such an intense outburst is a foregone conclusion--and, accordingly, Shea ups the gore factor in the big climax. While she comes up with one especially clever domino-effect scene invoving eyeglasses and a spear gun, there's nothing particularly frightening or suspenseful as any given scene in Brian DePalma's original film.
It was undoubtedly the ties to the original _Carrie_ that got _The_Rage_ made, but, ironically, it is that connection that makes the film even worse that it already is. Not only does _The_Rage_ simply pale in comparison, the links Moreu serves up are ridiculously clunky, especially one ill-kept plot "twist" about the origin of Rachel's powers. Shea even actually goes so far as to include excerpts of the first film as random flashbacks for Sue. Worst of all, though, these ties seem completely arbitrary, serving no real purpose other than to fill time and fulfill the meager promise of the subtitle. Change a line here and there (and Irving's character name), and _The_Rage:_Carrie_2_ would be just _The_Rage_--and better for it. However, no script revisions are necessary for the film to simply be _The_Rage_; audiences will feel plenty of that once the closing crawl begins.
Michael Dequina
<EMAIL_ADDRESS>|<EMAIL_ADDRESS>Mr. Brown's Movie Site: http://welcome.to/mrbrown
CompuServe Hollywood Hotline: http://www.HollywoodHotline.com
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interface KalesTask
abstract fun run(): Unit |
abstract class KalesContextualTask : KalesTask
Defines a Kales task that is supposed to run from an existing Kales application root directory, defined by applicationRootDir, eg.: "~/projects/foo" |
|
class KalesVersionTask : KalesTask |
|
class NewApplicationTask : KalesTask
"kales new" command: Creates a new Kales application |


Mage Notigale:
The following Seeds are the main sites of enemy power nearby:
Seed of Infinity
Seed of Destruction


You've just written a masterpiece of a web app. It's fun, it's viral, and it's useful. It's clearly going to be "Sliced Bread 2.0". But what comes next is a series of unforeseen headaches. You'll outgrow your shared hosting and need to get on cloud services.  Once you serve up a handful of error pages, your praise-singing users will leave you faster than it takes to start a flamewar in #offrails. But wait! Just as Ruby helped you build your killer app, Ruby can also help you manage your infrastructure as your app grows. Read on for a list of useful gems every webapp should have.
When you make a coding mistake, you can revert to a good known commit. But when disaster wrecks havoc with your data, you better have an offsite backup ready to minimize your losses. Enter the backups gem, a DSL for describing your different data stores and offsite storage locations. Once you specify what data stores you use in your application (MySQL, PostgreSQL, Mongo, Redis, and more), and where you want to store it (rsync, S3, CloudFiles), Backup will dump and store your backups. You can specify how many backups you'd like to keep in rotation, and there's various extras like gzip compression, and notifiers for when backups are created or failed to create.
Having backups configured doesn't make you any less absent minded about running your backups. The first remedy that jumps to mind is editing your crontab. But man, it's hard to remember the format on that sucker. If only there was a Ruby wrapper around cron... Fortunately there is! Thanks to the whenever gem, you can define repetitious tasks in a Ruby script.
With the number of cloud services available today, it's becoming more common to have your entire infrastructure hosted in the cloud. Many of these services offer API's to help you tailor and control your environments programmatically. Having API's is great, but it's tough to keep them all in your head.
The fog gem is the one API to rule them all. It provides a consistent interface to several cloud services. There are specific adapters for each cloud service. By following the Fog interface, it makes it really easy to switch between different cloud services. Say you were using Amazon's S3, but wanted to switch to Rackspace's CloudFiles. If you use Fog, it's as simple as replacing your credentials and changing the service name. You can create real cloud servers, or create mock ones for testing. Even if you don't use any cloud services, fog has adapters for non-cloud servers and filesystems.
Hoptoad is a household name in the Ruby community. It catches exceptions created by your app, and sends them into a pretty web interface and other notifications. If you can't use Hoptoad because of a firewall, check out the self-hostable Errbit.
When your infrastructure isn't running smoothly, it better be raising all kinds of alarms and sirens to get someone to fix it. Two popular monitoring solutions are God, and Monit. God lets you configure which services you want to monitor in Ruby, and the Monit gem gives you an interface to query services you have registered with Monit. If you have a Ruby script that you'd like to have running like a traditional Unix daemon, check out the daemons gem. It wraps around your existing Ruby script and gives you a 'start', 'stop', 'restart' command line interface that makes it easier to monitor.
Your application is happily running in production, but all of a sudden, it decides to implode on itself for a specific user when they update their avatar. Try as you might, you just can't reproduce the bug locally. You could do some cowboy debugging on production, but you'll end up dropping your entire database on accident. Oops.
It's times like these that you'll be thankful you have a staging environment setup. If you use capistrano, make sure to check out how to use capistrano-ext gem, and its multi-stage deploy functionality. To reproduce your bug on the same data, you can use the taps gem to transfer your data from your production database to your staging database. If you're using Heroku then it's already built-in.
 It stubs out ActionMailer so that your users don't get your testing spam. It also lets you send emails to your own email address for testing.
Thor is a good foundation for writing CLI utilities in Ruby. It has interfaces for manipulating files and directories, parsing command line options, and manipulating processes.
 If you use Vagrant for managing development virtual machines, you can reuse your Chef cookbooks for production.
All of these gems help us maintain our application infrastructure in a robust way. It frees us from running one-off scripts and hacks in production and gives us a repeatable process for managing everything our app runs on. And on top of all the awesome functionality these tools provide, we can also write Ruby to interact with them and version control them alongside our code. So for your next killer webapp, don't forget to add some killer devops to go along with it.


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--- layout: post title: "Steps of scientific inquiry" date: 2017-12-22 comments: true archive: true notes: true tags: notes excerpt: Steps of scientific inquiry. ---
Steps of Scientific Inquiry
Purpose
Prove or disprove someone's hypothesis. In other words someone's prediction is correct or not. Designing the experiment should answer the following questions:
What an experiment needs?
Rule#1
: The experiment must show that a hypothesis is either
supported or not. Avoid using terms "right" and "wrong" or that the
hypotheses are "proved" or "disproved" until we are really sure about
it. A single experiment is not enough to prove anything with 100\%
certainty.
Rule#2
: The results must be measurable and objective. Use standard
units to measure different properties. Sometimes need special
equipment to measure things such as ultraviolet light and infrasonic
sounds.
Rule#3
: Experiment should be repeatable and reproducible.
Theories and Laws
Theory
, is a statement generally accepted as a summary for a
hypothesis or a group of hypothesis. You can also call a theory an
accepted hypothesis. When many have tested the same hypothesis and
come up with the same conclusion then we can call that hypothesis a
theory. A theory can still be disproved.
A Law
, is viewed as a universal fact. A scientific law is a general
statement about a group of observations that has no exceptions to the
rule. Most laws can be stated as mathematical equations, e.g. Boyele's
law and Pascal's law. In biology laws are regarded as statements about
how living things work, e.g. Mendel's law{law of segregation, law of
independent assortment}.


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1ST PLACE SPEEDRUN - Blaidan - 36m 09s 390ms
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Class: His::DataValue
- Inherits:
-
Object
- Object
- His::DataValue
- Includes:
- DataMapper::Resource
- Defined in:
- app/models/his/data_value.rb
Overview
DataValues
This is a “Obersvations Values” The DataValues table contains the actual data values. The following rules and best practices should be used in populating this table:
ValueID is the primary key, is mandatory, and cannot be NULL. This field should be
implemented as an autonumber/identity field. When data values are added to this table, a unique integer ValueID should be assigned to each data value by the database software such that the primary key constraint is not violated.
Each record in this table must be unique. This is enforced by a unique constraint across
all of the fields in this table (excluding ValueID) so that duplicate records are avoided.
The LocalDateTime, UTCOffset, and DateTimeUTC must all be populated. Care must
be taken to ensure that the correct UTCOffset is used, especially in areas that observe daylight saving time. If LocalDateTime and DateTimeUTC are given, the UTCOffset can be calculated as the difference between the two dates. If LocalDateTime and UTCOffset are given, DateTimeUTC can be calculated.
SiteID must correspond to a valid SiteID from the Sites table. When adding data for a
new site to the ODM, the Sites table should be populated prior to adding data values to the DataValues table.
VariableID must correspond to a valid VariableID from the Variables table. When
adding data for a new variable to the ODM, the Variables table should be populated prior to adding data values for the new variable to the DataValues table.
OffsetValue and OffsetTypeID are optional because not all data values have an offset.
Where no offset is used, both of these fields should be set to NULL indicating that the data values do not have an offset. Where an OffsetValue is specified, an OffsetTypeID must also be specified and it must refer to a valid OffsetTypeID in the OffsetTypes table. The OffsetTypes table should be populated prior to adding data values with a particular OffsetTypeID to the DataValues table.
CensorCode is mandatory and cannot be NULL. A default value of ???nc??? is used for this
field. Only Terms from the CensorCodeCV table should be used to populate this field.
The QualifierID field is optional because not all data values have qualifiers. Where no
qualifier applies, this field should be set to NULL. When a QualifierID is specified in this field it must refer to a valid QualifierID in the Qualifiers table. The Qualifiers table should be populated prior to adding data values with a particular QualifierID to the DataValues Table.
MethodID must correspond to a valid MethodID from the Methods table and cannot be
NULL. A default value of 0 is used in the case where no method is specified or the method used to create the observation is unknown. The Methods table should be populated prior to adding data values with a particular MethodID to the DataValues table.
SourceID must correspond to a valid SourceID from the Sources table and cannot be
NULL. The Sources table should be populated prior to adding data values with a particular SourceID to the DataValues table.
SampleID is optional and should only be populated if the data value was generated from
a physical sample that was sent to a laboratory for analysis. The SampleID must correspond to a valid SampleID in the Samples table, and the Samples table should be populated prior to adding data values with a particular SampleID to the DataValues table.
DerivedFromID is optional and should only be populated if the data value was derived
from other data values that are also stored in the ODM database.
QualityControlLevelID is mandatory, cannot be NULL, and must correspond to a valid
QualityControlLevelID in the QualityControlLevels table. A default value of -9999 is used for this field in the event that the QualityControlLevelID is unknown. The QualityControlLevels table should be populated prior to adding data values with a particular QualityControlLevelID to the DataValues table.
Class Method Summary (collapse)
Class Method Details
+ (Object) default_repository_name
57 58 59 |
# File 'app/models/his/data_value.rb', line 57 def self.default_repository_name :his end |


Before Change
app_type = task_param.name
if app_type == "net_segment.py":
from niftynet.application.segmentation_application \
import SUPPORTED_INPUT
// only choose output names that are supported by the application
// (SUPPORTED_INPUT) and have user parameter specification
elif app_type == "net_gan.py":
from niftynet.application.gan_application \
import SUPPORTED_INPUT
if not self.names:
// by default, reader tries to output all supported output names
self.names = SUPPORTED_INPUT
After Change
data_to_load = {}
for name in self._names:
for source in self._input_sources[name]:
if source not in data_param:
tf.logging.fatal(
"reader name [{}] requires [{}], however it is not "
"specified as a section in the config, "
"current input section names: {}".format(
name, source, list(data_param)))
raise ValueError
else:
data_to_load[source] = data_param[source]
self._file_list = ImageReader.load_and_merge_csv_files(data_to_load)
self.output_list = filename_to_image_list(self._file_list,
self._input_sources,
data_param)


Real Time Gas And Petrol Station Management App
© CarlbTech All Right Reserved 2017
Text in a modal
Do you want to turn on location services so GPS can use your location ?


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Blender Interior Design - Isometric Living Room (Workflow)
by Egneva DesignsEgneva Designs writes:
In this Video I will show you the complete workflow for making an Isometric interior design in BLENDER 2.80+. Video starts with basic settings for isometric rendering , modeling and texturing time-lapse and then an overview of all the steps involved in the project.


It's pig time, at last, in the Hooting Yard Advent Calendar. Here is a picture of pigs doing what pigs do best.
The snap is from the Animal Photos! website. I like the breezy gusto of that exclamation mark. Perhaps I should rename this site Hooting Yard!


In module 3 and in section II of this module, we introduced the concept of methods and variables and showed how a method could be either a class or instance method, the difference between a class and instance method being determined by the use of the static modifier. Thus, to understand class and instance variables and methods, it is first necessary to understand static modifiers.
We will now look at the meaning of the static modifier, the implications of its use, and how being associated with a class affects variables, methods, and constants. We will now discuss class (static) variables, class (static) methods, and class (static) constants.
When a variable is declared static, it is associated with the class and not an object or instance of the class, so each static or class variable is shared by all the instances of the class. Also, because the class exists from the time the program starts execution until it completes execution, static variables exist, and are accessible, during the entire life of the program.
To understand how we may take advantage of this fact, consider an application that wants to keep track of how many UMUC_Employee objects have been created and to use this number to make an employeeId for each UMUC_Employee object. The employeeId will simply be the number of UMUC_Employee objects already created. For this application, the number of UMUC_Employee objects could be kept in a static variable, and this variable could be incremented in the UMUC_Employee constructor each time a UMUC_Employee object is created. This situation is shown in the following program.
Note that the line declaring the static variable is highlighted. Move your mouse over OUTPUT to see what is printed.
/* File: UMUC_Employee.java * Author: InstructorX * Date: dd-mm-yyyy * Purpose: shows the difference between a static variable * and an instance variable */ public class UMUC_Employee { private static int numberOfEmployees = 0; private int employeeId = 0; public UMUC_Employee() { employeeId = ++numberOfEmployees; } // end method public int getEmployeeId() { return employeeId; } // end method public static void main(String args[]) { UMUC_Employee emp1 = new UMUC_Employee(); UMUC_Employee emp2 = new UMUC_Employee(); System.out.println("emp1 id is " + emp1.getEmployeeId()); // OUTPUT System.out.println("emp2 id is " + emp2.getEmployeeId()); // OUTPUT System.out.println("total number of employees is " + UMUC_Employee.numberOfEmployees); // OUTPUT } // end method } // end class
We can represent this situation by the diagram in figure 5.III-1.
Figure 5.III-1
The Relationship of Class and Instance Variables
In the program above, there is one copy of the numberOfEmployees variable, which is declared static, but there is a copy of the employeeId variable for each UMUC_Employee object. Because the numberOfEmployees variable is static, it can be used to count the number of employee objects that have been created. Figure 5.III-1 above shows that the static modifier affects a variable in the following ways:
If a variable is static, there is only one copy, and it is shared with all objects of that class. Static variables exist from the time the program begins execution until the program ends execution, so every reference to a static variable references the same static variable.
If a variable is not static, it is an instance variable, and each object has its own copy of all the variables that make up that object.
In this section, the class (or static) variable is only used internally to the class and so is encapsulated by making it private and accessing it only through methods. This process is similar to the way in which instance variables were made private in section II. But there are many valid reasons for making variables, particularly class variables, public. We will cover some of these reasons later in this module.
When we introduced class methods in module 3, we said that these methods were also called static. The static modifier means the same thing for a method that it does for a variable; it means that the method is associated with the class and not with an instance of the class. In module 3 and in section II, we discussed the following two differences between class methods and instance methods:
class methods are declared with the static modifier
Instance methods are associated with instance data for the class (e.g., an object), but class methods are not associated with any data other than the parameters passed into them.
An understanding of the use of static gives insight into these two differences. The second difference (class methods are associated with a class, not an object) is a direct result of the first (class methods are declared static). So, in reality, there is only one difference between class and instance methods—whether they are associated with the class or an object. This difference is then implemented through the use of the static modifier.
The distinction is important. When you use a static modifier with a method, it associates that method with a class and not an instance. Therefore, static methods are class methods and do not contain, and hence cannot access, instance data. For example, the following program shows a common error made by novice programmers in Java.
The line with the error is highlighted.
/* File: UMUC_InstanceError.java * Author: InstructorX * Date: dd-mm-yyyy * Purpose: show that an instance variable cannot be used * in a static method */ public class UMUC_InstanceError { private static int classVar = 0; private int instanceVar = 0; public static void main(String args[]) { classVar = 1; // Valid, because class variables can be // used in class methods. instanceVar = 1; // Invalid, because instance variables // cannot be used in class methods. } // end method } // end class
This program shows an instance variable, instanceVar, being used in the main method, which is a static method. Remember that there can be literally hundreds of instances of a class, but only one class. Therefore, the attempt to access the instance variable in the main (static) method is an error in Java because the static method cannot know which of possibly thousands of copies of the instance variable to use.
But whereas static methods cannot access instance variables, there is no logical reason why instance methods cannot access static variables. For example, consider the following program.
/* File: UMUC_Variables.java * Author: InstructorX * Date: dd-mm-yyyy * Purpose: show that a class variable can be used * in an instance method */ public class UMUC_Variables { private static int classVar = 0; private int instanceVar = 0; public void UMUC_Variables() { } // end method public void instanceMethod() { classVar = 1; // Valid, because class variables can // be used in instance methods instanceVar = 1; // Valid, because instance variables can // be used in instance methods } // end method } // end class
The method instanceMethod can access both the variables named classVar and instanceVar. The variable classVar can be accessed because there is only one class associated with any object, and hence only one classVar variable. Therefore, the reference to classVar is unambiguous. The variable instanceVar can be accessed in the method instanceMethod because instance methods are associated with instances of the class, and therefore instanceMethod knows which instance of the class to use to obtain a value of instanceVar.
When a method is declared as an instance method in Java, it is associated with an object regardless of whether or not it uses any of the data in that object. Another error novices commonly make in Java programming is to try to use instance methods called from a static method. The following program shows this error when using methods in Java.
The line with the error is highlighted.
/* File: UMUC_MethodError.java * Author: InstructorX * Date: dd-mm-yyyy * Purpose: show that an instance method cannot be called * from a static method */ public class UMUC_MethodError { public int max(int val1, int val2) { int maxValue; if (val1 > val2) maxValue = val1; else maxValue = val2; return maxValue; } // end method public static void main(String args[]) { int i1 = 7, i2 = 9, i3; i3 = max(i1, i2); // Invalid. The method max is an // instance method, and is not // accessible in a static method. System.out.println("max is " + i3); } // end method } // end class
In this program, the main method, which is static and associated with the class, attempts to call the max method, which is an instance method and associated with an object. The programmer might believe that this is correct because the max method does not use any data associated with an object instance. But this method has not been declared static, so it is associated with an object, regardless of how the programmer uses it. This is an error because the call to max in the static method now needs an object when called. This method could be corrected simply by allocating an object so that it can be used, as in the following program. The corrected code is highlighted.
/* File: UMUC_MethodError.java * Author: InstructorX * Date: dd-mm-yyyy * Purpose: show that an instance method needs an object * to be called from a static method */ public class UMUC_MethodError { public int max(int val1, int val2) { int maxValue; if (val1 > val2) maxValue = val1; else maxValue = val2; return maxValue; } // end method public static void main(String args[]) { int i1 = 7, i2 = 9, i3; UMUC_MethodError m1 = new UMUC_MethodError(); i3 = m1.max(i1, i2); // Now it is valid because it is // called with an object. System.out.println("max is " + i3); } // end method } // end class
Because the max method does not use any instance variables, however, the allocation of the object to use the max method is really a wasted step, necessitated only by the programmer declaring the method an instance method. In cases where a method does not use any data from the instance, it is usually best to simply associate the method with a class, as in the following program.
Move your mouse over OUTPUT to see what is printed.
/* File: UMUC_MethodError.java * Author: InstructorX * Date: dd-mm-yyyy * Purpose: show that a method that does not use instance data * should be a class method */ public class UMUC_MethodError { public static int max(int val1, int val2) { int maxValue; if (val1 > val2) maxValue = val1; else maxValue = val2; return maxValue; } // end method public static void main(String args[]) { int i1 = 7, i2 = 9, i3; i3 = max(i1, i2); // max is defined as a class method, // so this call is now valid. System.out.println("max is " + i3); // OUTPUT } // end method } // end class
In module 1, we saw that it is possible to create constants by declaring a variable final. For example, the constant PI could be declared in the class MyMath as:
public class MyMath { public final int PI = 3.l4159; }
This declaration of PI creates a public constant. You would almost never see this type of declaration, however, in a Java program written by an experienced Java programmer. In Java, public constants are almost always declared using the static modifier. The rationale for doing so is the same as for the use of the static modifier for class methods in the previous section.
For example, suppose a programmer wanted to use the constant PI from the MyMath class given above. To use the constant, an instance of the class MyMath would have to first be created, as shown below.
public class BadlyUsedConstant { public static void main(String args[]) { double area, radius = 2; MyMath myMath = new MyMath(); area = radius * radius * myMath.PI; } }
There is no reason to create an instance of the class MyMath except to use the constant PI. Creating the myMath object is simply confusing, serves no purpose, and wastes computer resources. It is always best in these situations to simply make public constants static variables so that they can be used in other classes without instantiating an object. For example, a correct definition of the constant PI in the class MyMath would be as follows:
public class MyMath { public static final int PI = 3.l4159; }
The variable PI can now be used as a class variable, as shown below:
public class CorrectConstant { public static void main(String args[]) { double area, radius = 2; area = radius * radius * MyMath.PI; } }
A good rule is:
Constants for a class should always be declared static in Java.
In fact, for efficiency reasons, it is usually better to use the static modifier with any final variables declared in the class (note that this does not apply to final variables declared in a method). The exceptions to this rule generally involve an unusual use of objects and are beyond the scope of this course.


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BY EDWIN JAHIEL
GET BRUCE! (1999)*** Produced and directed by Andrew J. Kuehn. Photography, Jose Luis Mignone. Editing, Maureen Nolan. Music, Michael Feinstein. Appearing : Bruce Vilanch, Bette Midler, Billy Crystal , Robin Williams, Whoopi Goldberg, Lily Tomlin, Nathan Lane, Roseanne, Carol Burnett, Florence Henderson, Rosie O'Donnell, Shirley MacLaine, Paul Reiser, George Schlatter, Raquel Welch, Sigourney Weaver, and others. A Miramax release. 93 min. R (raunchy talk and jokes)
Of the films starting with the word "get" the three most interesting have been the British "Get Carter" (1971), a tough action item with Michael Caine; "Get Out Your Handkerchiefs" (1978) the irreverent French movie with Gerard Depardieu; and "Get Shorty" (1995), the humorous, hoodlum story from Elmore Leonard, with John Travolta.
The ""get" in Get Bruce, unlike the other titles, refers to the hirings of real-life Bruce Vilanch by practitioners of film, TV and other events, that is, "celebrities" --which is one of the most irritating and overworked words in American pop culture.
A small, improvised poll turns out this fact: almost no one among ordinary folks has any idea who Bruce Vilanch is. But (a very big but) everyone in showbiz knows that this Bruce is a joke and gag writer who is in huge demand among actors, stand-up comics, sit-down comics, leaders or organizers of such public events as roasts, homages, the Academy Awards ceremonies and so on ad infinitum.
Which explains why this light-hearted documentary is studded with laugh-getting stars, clients, collaborators, admirers and --in the best showbiz tradition --"best friends" of Bruce's. Look at the credits above and you get merely a whiff of Vilanchites.
The voluminous, hirsute Bruce, ever-looking unkempt, ever wearing one of his funny t-shirts from his colossal collection, is a very funny fellow. In interviews which, like good jokes, never overstay their welcome, in amusing conversations, discussions, appearances and the like, in cinema-verite scenes, one learns a great deal not only about Vilanch but also about several of his performer-friends. There are tidbits that inform you about those persons, as well as Bruce, and that make them all more understandable. They also reveal the mechanisms behind the funny stuff.
In a few cases this gets a bit tiresome, notably when Robin Williams keeps appearing and being funny, or so he thinks. But by and large -- as in the case of the parceled out interview of Bruce's vivacious, scene-stealing adoptive Jewish mother --there is lively light shed on the speaker as well as on Vilanch. Or take the sessions in which frequent Oscar-host Billy Crystal sits down with Bruce and both get into the technicalities of what was done, changed or eliminated in the Motion Picture Academy's annual event -- which is discussed as the "nec plus ultra", as something like the Olympic Games of live appearances.
Vilanch does not merely provide jokes. He tailor-makes, very cleverly, to the style and the personality of personalities, so that we, the public, easily believe that the one-liners and others originate with the performers. In addition, Vilanch also coaches the performers with precision, skill and a vast knowledge of what works and what does not, from gestures to looks, from hair to toes, from dressing to walking, and much more.
In addition to the above addition, Bruce himself is a first-rate performer. We see him doing his shticks more than once in this not-flagging, fast-paced, even frantic assemblage of scenes and sequences. The man is a joke factory, which, if listed on the stock market, would keep paying high dividends to shareholders.
 Just about the only non-comic moment in this documentary is when he becomes lachrymose during an AIDS benefit.
Among the miscellaneous revelations in the documentary is that Bruce originated the famous appearance of then Whoopi's paramour Ted Danson, in an affair where Danson was in blackface. This created a controversy. My position is that the event was in bad taste, but what really shocked me was to hear Whoopi say that something or other was "about Ted and I." So much for the literacy and grammar of "celebrities."
"Get Bruce" is a most entertaining ninety minutes . You laugh a lot and learn a lot. But do bear in mind that this work is neither about humor (both in its narrow and wide definitions) nor about wit. Oscar Wilde or even Noel Coward are light-years away. Gags, jokes and ephemeral one-liners are its mainstay and reign supreme.
The review above was posted to the
rec.arts.movies.reviews newsgroup (de.rec.film.kritiken for German reviews).
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Related links: index of all rec.arts.movies.reviews reviews


| Package | Description |
|---|---|
| org.avaje.metric |
The main public API for Avaje Metrics.
|
| org.avaje.metric.spi |
The service provider API that needs to be implemented by implementors.
|
| Modifier and Type | Interface and Description |
|---|---|
interface |
BucketTimedMetric
Used to collect timed metrics but puts the statistics into millisecond time ranges (buckets).
|
interface |
CounterMetric
Metric based on a counter (long value) typically used to count discrete events.
|
interface |
GaugeDoubleGroup
Groups
GaugeDoubleMetric that are closely related. |
interface |
GaugeDoubleMetric
Metric based on a gauge returning double values.
|
interface |
GaugeLongGroup
Groups
GaugeLongMetric gauges that are closely related. |
interface |
GaugeLongMetric
Metric based on an underlying gauge that reports long values.
|
interface |
TimedMetric
Collects and provides statics for a timed event.
|
interface |
ValueMetric
Metric that collects long values (e.g.
|
| Modifier and Type | Method and Description |
|---|---|
static Collection<Metric> |
MetricManager.collectNonEmptyMetrics()
Return all the non-jvm registered metrics that are not empty.
|
static Collection<Metric> |
MetricManager.getJvmMetrics()
Return the core JVM metrics.
|
static Collection<Metric> |
MetricManager.getMetrics()
Return all the non-jvm registered metrics.
|
| Modifier and Type | Method and Description |
|---|---|
Collection<Metric> |
PluginMetricManager.collectNonEmptyMetrics()
Return the collection of metrics that are considered non-empty.
|
Collection<Metric> |
PluginMetricManager.getJvmMetrics()
Return a collection of the JVM metrics.
|
Collection<Metric> |
PluginMetricManager.getMetrics()
Return a collection of all the metrics.
|
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