| 15 | GPIO19INTD | RW | GPIO19 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD19FNCSEL = NCE19 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD19FNCSEL = NCE19 - nCE polarity active high INTDIS = 0x0 - Applies when PAD19FNCSEL != NCE19 and GPIO19INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD19FNCSEL != NCE19 and GPIO19INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD19FNCSEL != NCE19 and GPIO19INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD19FNCSEL != NCE19 and GPIO19INCFG = 0 - Interrupt on high to low GPIO transition |
| 14:13 | GPIO19OUTCFG | RW | GPIO19 output configuration. DIS = 0x0 - Applies when PAD19FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD19FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD19FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD19FNCSEL = GPIO - Output is tri-state IOM0CE3 = 0x0 - Applies when PAD19FNCSEL = NCE19 - IOM0 nCE, Channel 3 MSPI1CE1 = 0x1 - Applies when PAD19FNCSEL = NCE19 - MSPI1 nCE, Channel 1 IOM3CE3 = 0x2 - Applies when PAD19FNCSEL = NCE19 - IOM3 nCE, Channel 3 MSPI0CE0 = 0x3 - Applies when PAD19FNCSEL = NCE19 - MSPI0 nCE, Channel 0 INTLH = 0x0 - Applies when PAD19FNCSEL != NCE19 and GPIO19INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD19FNCSEL != NCE19 and GPIO19INCFG = 0 - Interrupt on high to low GPIO transition |
| 12 | GPIO19INCFG | RW | GPIO19 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 11 | GPIO18INTD | RW | GPIO18 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD18FNCSEL = NCE18 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD18FNCSEL = NCE18 - nCE polarity active high INTDIS = 0x0 - Applies when PAD18FNCSEL != NCE18 and GPIO18INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD18FNCSEL != NCE18 and GPIO18INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD18FNCSEL != NCE18 and GPIO18INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD18FNCSEL != NCE18 and GPIO18INCFG = 0 - Interrupt on high to low GPIO transition |
| 10:9 | GPIO18OUTCFG | RW | GPIO18 output configuration. DIS = 0x0 - Applies when PAD18FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD18FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD18FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD18FNCSEL = GPIO - Output is tri-state MSPI2CE0 = 0x0 - Applies when PAD18FNCSEL = NCE18 - MSPI2 nCE, Channel 0 IOM1CE2 = 0x1 - Applies when PAD18FNCSEL = NCE18 - IOM1 nCE, Channel 2 IOM2CE2 = 0x2 - Applies when PAD18FNCSEL = NCE18 - IOM2 nCE, Channel 2 IOM3CE2 = 0x3 - Applies when PAD18FNCSEL = NCE18 - IOM3 nCE, Channel 2 INTLH = 0x0 - Applies when PAD18FNCSEL != NCE18 and GPIO18INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD18FNCSEL != NCE18 and GPIO18INCFG = 0 - Interrupt on high to low GPIO transition |
| 8 | GPIO18INCFG | RW | GPIO18 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 7 | GPIO17INTD | RW | GPIO17 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD17FNCSEL = NCE17 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD17FNCSEL = NCE17 - nCE polarity active high INTDIS = 0x0 - Applies when PAD17FNCSEL != NCE17 and GPIO17INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD17FNCSEL != NCE17 and GPIO17INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD17FNCSEL != NCE17 and GPIO17INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD17FNCSEL != NCE17 and GPIO17INCFG = 0 - Interrupt on high to low GPIO transition |
| 6:5 | GPIO17OUTCFG | RW | GPIO17 output configuration. DIS = 0x0 - Applies when PAD17FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD17FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD17FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD17FNCSEL = GPIO - Output is tri-state IOM0CE1 = 0x0 - Applies when PAD17FNCSEL = NCE17 - IOM0 nCE, Channel 1 IOM1CE1 = 0x1 - Applies when PAD17FNCSEL = NCE17 - IOM1 nCE, Channel 1 MSPI2CE0 = 0x2 - Applies when PAD17FNCSEL = NCE17 - MSPI2 nCE, Channel 0 IOM4CE1 = 0x3 - Applies when PAD17FNCSEL = NCE17 - IOM4 nCE, Channel 1 INTLH = 0x0 - Applies when PAD17FNCSEL != NCE17 and GPIO17INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD17FNCSEL != NCE17 and GPIO17INCFG = 0 - Interrupt on high to low GPIO transition |
| 4 | GPIO17INCFG | RW | GPIO17 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 3 | GPIO16INTD | RW | GPIO16 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD16FNCSEL = NCE16 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD16FNCSEL = NCE16 - nCE polarity active high INTDIS = 0x0 - Applies when PAD16FNCSEL != NCE16 and GPIO16INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD16FNCSEL != NCE16 and GPIO16INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD16FNCSEL != NCE16 and GPIO16INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD16FNCSEL != NCE16 and GPIO16INCFG = 0 - Interrupt on high to low GPIO transition |
| 2:1 | GPIO16OUTCFG | RW | GPIO16 output configuration. DIS = 0x0 - Applies when PAD16FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD16FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD16FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD16FNCSEL = GPIO - Output is tri-state IOM0CE0 = 0x0 - Applies when PAD16FNCSEL = NCE16 - IOM0 nCE, Channel 0 MSPI2CE0 = 0x1 - Applies when PAD16FNCSEL = NCE16 - MSPI2 nCE, Channel 0 IOM2CE3 = 0x2 - Applies when PAD16FNCSEL = NCE16 - IOM2 nCE, Channel 3 IOM5CE0 = 0x3 - Applies when PAD16FNCSEL = NCE16 - IOM5 nCE, Channel 0 INTLH = 0x0 - Applies when PAD16FNCSEL != NCE16 and GPIO16INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD16FNCSEL != NCE16 and GPIO16INCFG = 0 - Interrupt on high to low GPIO transition |
| 0 | GPIO16INCFG | RW | GPIO16 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| Instance 0 Address: | 0x40010058 |
GPIO configuration controls for GPIO[31:24]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO31INTD
0x0 |
GPIO31OUTCFG
0x0 |
GPIO31INCFG
0x0 |
GPIO30INTD
0x0 |
GPIO30OUTCFG
0x0 |
GPIO30INCFG
0x0 |
GPIO29INTD
0x0 |
GPIO29OUTCFG
0x0 |
GPIO29INCFG
0x0 |
GPIO28INTD
0x0 |
GPIO28OUTCFG
0x0 |
GPIO28INCFG
0x0 |
GPIO27INTD
0x0 |
GPIO27OUTCFG
0x0 |
GPIO27INCFG
0x0 |
GPIO26INTD
0x0 |
GPIO26OUTCFG
0x0 |
GPIO26INCFG
0x0 |
GPIO25INTD
0x0 |
GPIO25OUTCFG
0x0 |
GPIO25INCFG
0x0 |
GPIO24INTD
0x0 |
GPIO24OUTCFG
0x0 |
GPIO24INCFG
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO31INTD | RW | GPIO31 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD31FNCSEL = NCE31 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD31FNCSEL = NCE31 - nCE polarity active high INTDIS = 0x0 - Applies when PAD31FNCSEL != NCE31 and GPIO31INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD31FNCSEL != NCE31 and GPIO31INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD31FNCSEL != NCE31 and GPIO31INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD31FNCSEL != NCE31 and GPIO31INCFG = 0 - Interrupt on high to low GPIO transition |
| 30:29 | GPIO31OUTCFG | RW | GPIO31 output configuration. DIS = 0x0 - Applies when PAD31FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD31FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD31FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD31FNCSEL = GPIO - Output is tri-state MSPI1CE0 = 0x0 - Applies when PAD31FNCSEL = NCE31 - MSPI1 nCE, Channel 0 MSPI2CE0 = 0x1 - Applies when PAD31FNCSEL = NCE31 - MSPI2 nCE, Channel 0 IOM2CE0 = 0x2 - Applies when PAD31FNCSEL = NCE31 - IOM2 nCE, Channel 0 IOM4CE0 = 0x3 - Applies when PAD31FNCSEL = NCE31 - IOM4 nCE, Channel 0 INTLH = 0x0 - Applies when PAD31FNCSEL != NCE31 and GPIO31INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD31FNCSEL != NCE31 and GPIO31INCFG = 0 - Interrupt on high to low GPIO transition |
| 28 | GPIO31INCFG | RW | GPIO31 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 27 | GPIO30INTD | RW | GPIO30 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD30FNCSEL = NCE30 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD30FNCSEL = NCE30 - nCE polarity active high INTDIS = 0x0 - Applies when PAD30FNCSEL != NCE30 and GPIO30INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD30FNCSEL != NCE30 and GPIO30INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD30FNCSEL != NCE30 and GPIO30INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD30FNCSEL != NCE30 and GPIO30INCFG = 0 - Interrupt on high to low GPIO transition |
| 26:25 | GPIO30OUTCFG | RW | GPIO30 output configuration. DIS = 0x0 - Applies when PAD30FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD30FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD30FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD30FNCSEL = GPIO - Output is tri-state MSPI0CE0 = 0x0 - Applies when PAD30FNCSEL = NCE30 - MSPI0 nCE, Channel 0 IOM4CE3 = 0x1 - Applies when PAD30FNCSEL = NCE30 - IOM4 nCE, Channel 3 MSPI2CE0 = 0x2 - Applies when PAD30FNCSEL = NCE30 - MSPI2 nCE, Channel 0 IOM0CE3 = 0x3 - Applies when PAD30FNCSEL = NCE30 - IOM0 nCE, Channel 3 INTLH = 0x0 - Applies when PAD30FNCSEL != NCE30 and GPIO30INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD30FNCSEL != NCE30 and GPIO30INCFG = 0 - Interrupt on high to low GPIO transition |
| 24 | GPIO30INCFG | RW | GPIO30 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 23 | GPIO29INTD | RW | GPIO29 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD29FNCSEL = NCE29 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD29FNCSEL = NCE29 - nCE polarity active high INTDIS = 0x0 - Applies when PAD29FNCSEL != NCE29 and GPIO29INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD29FNCSEL != NCE29 and GPIO29INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD29FNCSEL != NCE29 and GPIO29INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD29FNCSEL != NCE29 and GPIO29INCFG = 0 - Interrupt on high to low GPIO transition |
| 22:21 | GPIO29OUTCFG | RW | GPIO29 output configuration. DIS = 0x0 - Applies when PAD29FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD29FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD29FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD29FNCSEL = GPIO - Output is tri-state IOM3CE2 = 0x0 - Applies when PAD29FNCSEL = NCE29 - IOM3 nCE, Channel 2 MSPI2CE1 = 0x1 - Applies when PAD29FNCSEL = NCE29 - MSPI2 nCE, Channel 1 IOM5CE2 = 0x2 - Applies when PAD29FNCSEL = NCE29 - IOM5 nCE, Channel 2 IOM1CE2 = 0x3 - Applies when PAD29FNCSEL = NCE29 - IOM1 nCE, Channel 2 INTLH = 0x0 - Applies when PAD29FNCSEL != NCE29 and GPIO29INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD29FNCSEL != NCE29 and GPIO29INCFG = 0 - Interrupt on high to low GPIO transition |
| 20 | GPIO29INCFG | RW | GPIO29 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 19 | GPIO28INTD | RW | GPIO28 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD28FNCSEL = NCE28 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD28FNCSEL = NCE28 - nCE polarity active high INTDIS = 0x0 - Applies when PAD28FNCSEL != NCE28 and GPIO28INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD28FNCSEL != NCE28 and GPIO28INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD28FNCSEL != NCE28 and GPIO28INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD28FNCSEL != NCE28 and GPIO28INCFG = 0 - Interrupt on high to low GPIO transition |
| 18:17 | GPIO28OUTCFG | RW | GPIO28 output configuration. DIS = 0x0 - Applies when PAD28FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD28FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD28FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD28FNCSEL = GPIO - Output is tri-state IOM3CE1 = 0x0 - Applies when PAD28FNCSEL = NCE28 - IOM3 nCE, Channel 1 IOM4CE1 = 0x1 - Applies when PAD28FNCSEL = NCE28 - IOM4 nCE, Channel 1 IOM5CE1 = 0x2 - Applies when PAD28FNCSEL = NCE28 - IOM5 nCE, Channel 1 MSPI0CE0 = 0x3 - Applies when PAD28FNCSEL = NCE28 - MSPI0 nCE, Channel 0 INTLH = 0x0 - Applies when PAD28FNCSEL != NCE28 and GPIO28INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD28FNCSEL != NCE28 and GPIO28INCFG = 0 - Interrupt on high to low GPIO transition |
| 16 | GPIO28INCFG | RW | GPIO28 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 15 | GPIO27INTD | RW | GPIO27 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD27FNCSEL = NCE27 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD27FNCSEL = NCE27 - nCE polarity active high INTDIS = 0x0 - Applies when PAD27FNCSEL != NCE27 and GPIO27INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD27FNCSEL != NCE27 and GPIO27INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD27FNCSEL != NCE27 and GPIO27INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD27FNCSEL != NCE27 and GPIO27INCFG = 0 - Interrupt on high to low GPIO transition |
| 14:13 | GPIO27OUTCFG | RW | GPIO27 output configuration. DIS = 0x0 - Applies when PAD27FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD27FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD27FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD27FNCSEL = GPIO - Output is tri-state MSPI2CE0 = 0x0 - Applies when PAD27FNCSEL = NCE27 - MSPI2 nCE, Channel 0 IOM4CE0 = 0x1 - Applies when PAD27FNCSEL = NCE27 - IOM4 nCE, Channel 0 MSPI0CE0 = 0x2 - Applies when PAD27FNCSEL = NCE27 - MSPI0 nCE, Channel 0 IOM1CE0 = 0x3 - Applies when PAD27FNCSEL = NCE27 - IOM1 nCE, Channel 0 INTLH = 0x0 - Applies when PAD27FNCSEL != NCE27 and GPIO27INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD27FNCSEL != NCE27 and GPIO27INCFG = 0 - Interrupt on high to low GPIO transition |
| 12 | GPIO27INCFG | RW | GPIO27 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 11 | GPIO26INTD | RW | GPIO26 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD26FNCSEL = NCE26 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD26FNCSEL = NCE26 - nCE polarity active high INTDIS = 0x0 - Applies when PAD26FNCSEL != NCE26 and GPIO26INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD26FNCSEL != NCE26 and GPIO26INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD26FNCSEL != NCE26 and GPIO26INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD26FNCSEL != NCE26 and GPIO26INCFG = 0 - Interrupt on high to low GPIO transition |
| 10:9 | GPIO26OUTCFG | RW | GPIO26 output configuration. DIS = 0x0 - Applies when PAD26FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD26FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD26FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD26FNCSEL = GPIO - Output is tri-state IOM3CE3 = 0x0 - Applies when PAD26FNCSEL = NCE26 - IOM3 nCE, Channel 3 IOM4CE3 = 0x1 - Applies when PAD26FNCSEL = NCE26 - IOM4 nCE, Channel 3 IOM5CE3 = 0x2 - Applies when PAD26FNCSEL = NCE26 - IOM5 nCE, Channel 3 IOM1CE3 = 0x3 - Applies when PAD26FNCSEL = NCE26 - IOM1 nCE, Channel 3 INTLH = 0x0 - Applies when PAD26FNCSEL != NCE26 and GPIO26INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD26FNCSEL != NCE26 and GPIO26INCFG = 0 - Interrupt on high to low GPIO transition |
| 8 | GPIO26INCFG | RW | GPIO26 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 7 | GPIO25INTD | RW | GPIO25 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD25FNCSEL = NCE25 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD25FNCSEL = NCE25 - nCE polarity active high INTDIS = 0x0 - Applies when PAD25FNCSEL != NCE25 and GPIO25INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD25FNCSEL != NCE25 and GPIO25INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD25FNCSEL != NCE25 and GPIO25INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD25FNCSEL != NCE25 and GPIO25INCFG = 0 - Interrupt on high to low GPIO transition |
| 6:5 | GPIO25OUTCFG | RW | GPIO25 output configuration. DIS = 0x0 - Applies when PAD25FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD25FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD25FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD25FNCSEL = GPIO - Output is tri-state IOM3CE2 = 0x0 - Applies when PAD25FNCSEL = NCE25 - IOM3 nCE, Channel 2 MSPI1CE0 = 0x1 - Applies when PAD25FNCSEL = NCE25 - MSPI1 nCE, Channel 0 IOM5CE2 = 0x2 - Applies when PAD25FNCSEL = NCE25 - IOM5 nCE, Channel 2 IOM0CE2 = 0x3 - Applies when PAD25FNCSEL = NCE25 - IOM0 nCE, Channel 2 INTLH = 0x0 - Applies when PAD25FNCSEL != NCE25 and GPIO25INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD25FNCSEL != NCE25 and GPIO25INCFG = 0 - Interrupt on high to low GPIO transition |
| 4 | GPIO25INCFG | RW | GPIO25 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 3 | GPIO24INTD | RW | GPIO24 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD24FNCSEL = NCE24 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD24FNCSEL = NCE24 - nCE polarity active high INTDIS = 0x0 - Applies when PAD24FNCSEL != NCE24 and GPIO24INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD24FNCSEL != NCE24 and GPIO24INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD24FNCSEL != NCE24 and GPIO24INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD24FNCSEL != NCE24 and GPIO24INCFG = 0 - Interrupt on high to low GPIO transition |
| 2:1 | GPIO24OUTCFG | RW | GPIO24 output configuration. DIS = 0x0 - Applies when PAD24FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD24FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD24FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD24FNCSEL = GPIO - Output is tri-state IOM0CE1 = 0x0 - Applies when PAD24FNCSEL = NCE24 - IOM0 nCE, Channel 1 MSPI1CE0 = 0x1 - Applies when PAD24FNCSEL = NCE24 - MSPI1 nCE, Channel 0 IOM2CE1 = 0x2 - Applies when PAD24FNCSEL = NCE24 - IOM2 nCE, Channel 1 IOM5CE1 = 0x3 - Applies when PAD24FNCSEL = NCE24 - IOM5 nCE, Channel 1 INTLH = 0x0 - Applies when PAD24FNCSEL != NCE24 and GPIO24INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD24FNCSEL != NCE24 and GPIO24INCFG = 0 - Interrupt on high to low GPIO transition |
| 0 | GPIO24INCFG | RW | GPIO24 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| Instance 0 Address: | 0x4001005C |
GPIO configuration controls for GPIO[39:32]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO39INTD
0x0 |
GPIO39OUTCFG
0x0 |
GPIO39INCFG
0x0 |
GPIO38INTD
0x0 |
GPIO38OUTCFG
0x0 |
GPIO38INCFG
0x0 |
GPIO37INTD
0x0 |
GPIO37OUTCFG
0x0 |
GPIO37INCFG
0x0 |
GPIO36INTD
0x0 |
GPIO36OUTCFG
0x0 |
GPIO36INCFG
0x0 |
GPIO35INTD
0x0 |
GPIO35OUTCFG
0x0 |
GPIO35INCFG
0x0 |
GPIO34INTD
0x0 |
GPIO34OUTCFG
0x0 |
GPIO34INCFG
0x0 |
GPIO33INTD
0x0 |
GPIO33OUTCFG
0x0 |
GPIO33INCFG
0x0 |
GPIO32INTD
0x0 |
GPIO32OUTCFG
0x0 |
GPIO32INCFG
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO39INTD | RW | GPIO39 interrupt direction, nCE polarity. INTDIS = 0x0 - Applies when GPIO39INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when GPIO39INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when GPIO39INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when GPIO39INCFG = 0 - Interrupt on high to low GPIO transition |
| 30:29 | GPIO39OUTCFG | RW | GPIO39 output configuration. DIS = 0x0 - Applies when PAD39FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD39FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD39FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD39FNCSEL = GPIO - Output is tri-state INTHL = 0x1 - Applies when GPIO39INCFG = 0 - Interrupt on high to low GPIO transition |
| 28 | GPIO39INCFG | RW | GPIO39 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 27 | GPIO38INTD | RW | GPIO38 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD38FNCSEL = NCE38 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD38FNCSEL = NCE38 - nCE polarity active high INTDIS = 0x0 - Applies when PAD38FNCSEL != NCE38 and GPIO38INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD38FNCSEL != NCE38 and GPIO38INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD38FNCSEL != NCE38 and GPIO38INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD38FNCSEL != NCE38 and GPIO38INCFG = 0 - Interrupt on high to low GPIO transition |
| 26:25 | GPIO38OUTCFG | RW | GPIO38 output configuration. DIS = 0x0 - Applies when PAD38FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD38FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD38FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD38FNCSEL = GPIO - Output is tri-state IOM0CE3 = 0x0 - Applies when PAD38FNCSEL = NCE38 - IOM0 nCE, Channel 3 IOM1CE3 = 0x1 - Applies when PAD38FNCSEL = NCE38 - IOM1 nCE, Channel 3 MSPI2CE1 = 0x2 - Applies when PAD38FNCSEL = NCE38 - MSPI2 nCE, Channel 1 IOM5CE3 = 0x3 - Applies when PAD38FNCSEL = NCE38 - IOM5 nCE, Channel 3 INTLH = 0x0 - Applies when PAD38FNCSEL != NCE38 and GPIO38INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD38FNCSEL != NCE38 and GPIO38INCFG = 0 - Interrupt on high to low GPIO transition |
| 24 | GPIO38INCFG | RW | GPIO38 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 23 | GPIO37INTD | RW | GPIO37 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD37FNCSEL = NCE37 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD37FNCSEL = NCE37 - nCE polarity active high INTDIS = 0x0 - Applies when PAD37FNCSEL != NCE37 and GPIO37INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD37FNCSEL != NCE37 and GPIO37INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD37FNCSEL != NCE37 and GPIO37INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD37FNCSEL != NCE37 and GPIO37INCFG = 0 - Interrupt on high to low GPIO transition |
| 22:21 | GPIO37OUTCFG | RW | GPIO37 output configuration. DIS = 0x0 - Applies when PAD37FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD37FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD37FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD37FNCSEL = GPIO - Output is tri-state IOM3CE1 = 0x0 - Applies when PAD37FNCSEL = NCE37 - IOM3 nCE, Channel 1 IOM4CE2 = 0x1 - Applies when PAD37FNCSEL = NCE37 - IOM4 nCE, Channel 2 IOM5CE2 = 0x2 - Applies when PAD37FNCSEL = NCE37 - IOM5 nCE, Channel 2 MSPI0CE0 = 0x3 - Applies when PAD37FNCSEL = NCE37 - MSPI0 nCE, Channel 0 INTLH = 0x0 - Applies when PAD37FNCSEL != NCE37 and GPIO37INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD37FNCSEL != NCE37 and GPIO37INCFG = 0 - Interrupt on high to low GPIO transition |
| 20 | GPIO37INCFG | RW | GPIO37 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 19 | GPIO36INTD | RW | GPIO36 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD36FNCSEL = NCE36 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD36FNCSEL = NCE36 - nCE polarity active high INTDIS = 0x0 - Applies when PAD36FNCSEL != NCE36 and GPIO36INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD36FNCSEL != NCE36 and GPIO36INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD36FNCSEL != NCE36 and GPIO36INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD36FNCSEL != NCE36 and GPIO36INCFG = 0 - Interrupt on high to low GPIO transition |
| 18:17 | GPIO36OUTCFG | RW | GPIO36 output configuration. DIS = 0x0 - Applies when PAD36FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD36FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD36FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD36FNCSEL = GPIO - Output is tri-state IOM3CE1 = 0x0 - Applies when PAD36FNCSEL = NCE36 - IOM3 nCE, Channel 1 IOM4CE1 = 0x1 - Applies when PAD36FNCSEL = NCE36 - IOM4 nCE, Channel 1 IOM5CE1 = 0x2 - Applies when PAD36FNCSEL = NCE36 - IOM5 nCE, Channel 1 MSPI0CE1 = 0x3 - Applies when PAD36FNCSEL = NCE36 - MSPI0 nCE, Channel 1 INTLH = 0x0 - Applies when PAD36FNCSEL != NCE36 and GPIO36INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD36FNCSEL != NCE36 and GPIO36INCFG = 0 - Interrupt on high to low GPIO transition |
| 16 | GPIO36INCFG | RW | GPIO36 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 15 | GPIO35INTD | RW | GPIO35 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD35FNCSEL = NCE35 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD35FNCSEL = NCE35 - nCE polarity active high INTDIS = 0x0 - Applies when PAD35FNCSEL != NCE35 and GPIO35INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD35FNCSEL != NCE35 and GPIO35INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD35FNCSEL != NCE35 and GPIO35INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD35FNCSEL != NCE35 and GPIO35INCFG = 0 - Interrupt on high to low GPIO transition |
| 14:13 | GPIO35OUTCFG | RW | GPIO35 output configuration. DIS = 0x0 - Applies when PAD35FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD35FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD35FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD35FNCSEL = GPIO - Output is tri-state MSPI1CE0 = 0x0 - Applies when PAD35FNCSEL = NCE35 - MSPI1 nCE, Channel 0 IOM1CE0 = 0x1 - Applies when PAD35FNCSEL = NCE35 - IOM1 nCE, Channel 0 IOM2CE0 = 0x2 - Applies when PAD35FNCSEL = NCE35 - IOM2 nCE, Channel 0 MSPI2CE0 = 0x3 - Applies when PAD35FNCSEL = NCE35 - MSPI2 nCE, Channel 0 INTLH = 0x0 - Applies when PAD35FNCSEL != NCE35 and GPIO35INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD35FNCSEL != NCE35 and GPIO35INCFG = 0 - Interrupt on high to low GPIO transition |
| 12 | GPIO35INCFG | RW | GPIO35 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 11 | GPIO34INTD | RW | GPIO34 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD34FNCSEL = NCE34 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD34FNCSEL = NCE34 - nCE polarity active high INTDIS = 0x0 - Applies when PAD34FNCSEL != NCE34 and GPIO34INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD34FNCSEL != NCE34 and GPIO34INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD34FNCSEL != NCE34 and GPIO34INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD34FNCSEL != NCE34 and GPIO34INCFG = 0 - Interrupt on high to low GPIO transition |
| 10:9 | GPIO34OUTCFG | RW | GPIO34 output configuration. DIS = 0x0 - Applies when PAD34FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD34FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD34FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD34FNCSEL = GPIO - Output is tri-state IOM0CE3 = 0x0 - Applies when PAD34FNCSEL = NCE34 - IOM0 nCE, Channel 3 MSPI2CE0 = 0x1 - Applies when PAD34FNCSEL = NCE34 - MSPI2 nCE, Channel 0 IOM2CE3 = 0x2 - Applies when PAD34FNCSEL = NCE34 - IOM2 nCE, Channel 3 MSPI1CE1 = 0x3 - Applies when PAD34FNCSEL = NCE34 - MSPI1 nCE, Channel 1 INTLH = 0x0 - Applies when PAD34FNCSEL != NCE34 and GPIO34INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD34FNCSEL != NCE34 and GPIO34INCFG = 0 - Interrupt on high to low GPIO transition |
| 8 | GPIO34INCFG | RW | GPIO34 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 7 | GPIO33INTD | RW | GPIO33 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD33FNCSEL = NCE33 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD33FNCSEL = NCE33 - nCE polarity active high INTDIS = 0x0 - Applies when PAD33FNCSEL != NCE33 and GPIO33INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD33FNCSEL != NCE33 and GPIO33INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD33FNCSEL != NCE33 and GPIO33INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD33FNCSEL != NCE33 and GPIO33INCFG = 0 - Interrupt on high to low GPIO transition |
| 6:5 | GPIO33OUTCFG | RW | GPIO33 output configuration. DIS = 0x0 - Applies when PAD33FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD33FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD33FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD33FNCSEL = GPIO - Output is tri-state IOM0CE2 = 0x0 - Applies when PAD33FNCSEL = NCE33 - IOM0 nCE, Channel 2 MSPI1CE1 = 0x1 - Applies when PAD33FNCSEL = NCE33 - MSPI1 nCE, Channel 1 IOM2CE1 = 0x2 - Applies when PAD33FNCSEL = NCE33 - IOM2 nCE, Channel 1 IOM5CE2 = 0x3 - Applies when PAD33FNCSEL = NCE33 - IOM5 nCE, Channel 2 INTLH = 0x0 - Applies when PAD33FNCSEL != NCE33 and GPIO33INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD33FNCSEL != NCE33 and GPIO33INCFG = 0 - Interrupt on high to low GPIO transition |
| 4 | GPIO33INCFG | RW | GPIO33 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 3 | GPIO32INTD | RW | GPIO32 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD32FNCSEL = NCE32 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD32FNCSEL = NCE32 - nCE polarity active high INTDIS = 0x0 - Applies when PAD32FNCSEL != NCE32 and GPIO32INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD32FNCSEL != NCE32 and GPIO32INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD32FNCSEL != NCE32 and GPIO32INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD32FNCSEL != NCE32 and GPIO32INCFG = 0 - Interrupt on high to low GPIO transition |
| 2:1 | GPIO32OUTCFG | RW | GPIO32 output configuration. DIS = 0x0 - Applies when PAD32FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD32FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD32FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD32FNCSEL = GPIO - Output is tri-state IOM0CE1 = 0x0 - Applies when PAD32FNCSEL = NCE32 - IOM0 nCE, Channel 1 IOM1CE3 = 0x1 - Applies when PAD32FNCSEL = NCE32 - IOM1 nCE, Channel 3 MSPI1CE0 = 0x2 - Applies when PAD32FNCSEL = NCE32 - MSPI1 nCE, Channel 0 MSPI0CE1 = 0x3 - Applies when PAD32FNCSEL = NCE32 - MSPI0 nCE, Channel 1 INTLH = 0x0 - Applies when PAD32FNCSEL != NCE32 and GPIO32INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD32FNCSEL != NCE32 and GPIO32INCFG = 0 - Interrupt on high to low GPIO transition |
| 0 | GPIO32INCFG | RW | GPIO32 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| Instance 0 Address: | 0x40010060 |
GPIO configuration controls for GPIO[47:40]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO47INTD
0x0 |
GPIO47OUTCFG
0x0 |
GPIO47INCFG
0x0 |
GPIO46INTD
0x0 |
GPIO46OUTCFG
0x0 |
GPIO46INCFG
0x0 |
GPIO45INTD
0x0 |
GPIO45OUTCFG
0x0 |
GPIO45INCFG
0x0 |
GPIO44INTD
0x0 |
GPIO44OUTCFG
0x0 |
GPIO44INCFG
0x0 |
GPIO43INTD
0x0 |
GPIO43OUTCFG
0x0 |
GPIO43INCFG
0x0 |
GPIO42INTD
0x0 |
GPIO42OUTCFG
0x0 |
GPIO42INCFG
0x0 |
GPIO41INTD
0x0 |
GPIO41OUTCFG
0x0 |
GPIO41INCFG
0x0 |
GPIO40INTD
0x0 |
GPIO40OUTCFG
0x0 |
GPIO40INCFG
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO47INTD | RW | GPIO47 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD47FNCSEL = NCE47 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD47FNCSEL = NCE47 - nCE polarity active high INTDIS = 0x0 - Applies when PAD47FNCSEL != NCE47 and GPIO47INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD47FNCSEL != NCE47 and GPIO47INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD47FNCSEL != NCE47 and GPIO47INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD47FNCSEL != NCE47 and GPIO47INCFG = 0 - Interrupt on high to low GPIO transition |
| 30:29 | GPIO47OUTCFG | RW | GPIO47 output configuration. DIS = 0x0 - Applies when PAD47FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD47FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD47FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD47FNCSEL = GPIO - Output is tri-state MSPI1CE1 = 0x0 - Applies when PAD47FNCSEL = NCE47 - MSPI1 nCE, Channel 1 IOM1CE0 = 0x1 - Applies when PAD47FNCSEL = NCE47 - IOM1 nCE, Channel 0 IOM2CE1 = 0x2 - Applies when PAD47FNCSEL = NCE47 - IOM2 nCE, Channel 1 IOM3CE1 = 0x3 - Applies when PAD47FNCSEL = NCE47 - IOM3 nCE, Channel 1 INTLH = 0x0 - Applies when PAD47FNCSEL != NCE47 and GPIO47INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD47FNCSEL != NCE47 and GPIO47INCFG = 0 - Interrupt on high to low GPIO transition |
| 28 | GPIO47INCFG | RW | GPIO47 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 27 | GPIO46INTD | RW | GPIO46 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD46FNCSEL = NCE46 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD46FNCSEL = NCE46 - nCE polarity active high INTDIS = 0x0 - Applies when PAD46FNCSEL != NCE46 and GPIO46INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD46FNCSEL != NCE46 and GPIO46INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD46FNCSEL != NCE46 and GPIO46INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD46FNCSEL != NCE46 and GPIO46INCFG = 0 - Interrupt on high to low GPIO transition |
| 26:25 | GPIO46OUTCFG | RW | GPIO46 output configuration. DIS = 0x0 - Applies when PAD46FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD46FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD46FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD46FNCSEL = GPIO - Output is tri-state IOM3CE0 = 0x0 - Applies when PAD46FNCSEL = NCE46 - IOM3 nCE, Channel 0 MSPI1CE0 = 0x1 - Applies when PAD46FNCSEL = NCE46 - MSPI1 nCE, Channel 0 MSPI2CE0 = 0x2 - Applies when PAD46FNCSEL = NCE46 - MSPI2 nCE, Channel 0 MSPI0CE1 = 0x3 - Applies when PAD46FNCSEL = NCE46 - MSPI0 nCE, Channel 1 INTLH = 0x0 - Applies when PAD46FNCSEL != NCE46 and GPIO46INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD46FNCSEL != NCE46 and GPIO46INCFG = 0 - Interrupt on high to low GPIO transition |
| 24 | GPIO46INCFG | RW | GPIO46 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 23 | GPIO45INTD | RW | GPIO45 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD45FNCSEL = NCE45 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD45FNCSEL = NCE45 - nCE polarity active high INTDIS = 0x0 - Applies when PAD45FNCSEL != NCE45 and GPIO45INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD45FNCSEL != NCE45 and GPIO45INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD45FNCSEL != NCE45 and GPIO45INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD45FNCSEL != NCE45 and GPIO45INCFG = 0 - Interrupt on high to low GPIO transition |
| 22:21 | GPIO45OUTCFG | RW | GPIO45 output configuration. DIS = 0x0 - Applies when PAD45FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD45FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD45FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD45FNCSEL = GPIO - Output is tri-state IOM3CE3 = 0x0 - Applies when PAD45FNCSEL = NCE45 - IOM3 nCE, Channel 3 IOM4CE3 = 0x1 - Applies when PAD45FNCSEL = NCE45 - IOM4 nCE, Channel 3 IOM5CE0 = 0x2 - Applies when PAD45FNCSEL = NCE45 - IOM5 nCE, Channel 0 IOM1CE3 = 0x3 - Applies when PAD45FNCSEL = NCE45 - IOM1 nCE, Channel 3 INTLH = 0x0 - Applies when PAD45FNCSEL != NCE45 and GPIO45INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD45FNCSEL != NCE45 and GPIO45INCFG = 0 - Interrupt on high to low GPIO transition |
| 20 | GPIO45INCFG | RW | GPIO45 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 19 | GPIO44INTD | RW | GPIO44 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD44FNCSEL = NCE44 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD44FNCSEL = NCE44 - nCE polarity active high INTDIS = 0x0 - Applies when PAD44FNCSEL != NCE44 and GPIO44INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD44FNCSEL != NCE44 and GPIO44INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD44FNCSEL != NCE44 and GPIO44INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD44FNCSEL != NCE44 and GPIO44INCFG = 0 - Interrupt on high to low GPIO transition |
| 18:17 | GPIO44OUTCFG | RW | GPIO44 output configuration. DIS = 0x0 - Applies when PAD44FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD44FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD44FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD44FNCSEL = GPIO - Output is tri-state IOM0CE2 = 0x0 - Applies when PAD44FNCSEL = NCE44 - IOM0 nCE, Channel 2 MSPI0CE0 = 0x1 - Applies when PAD44FNCSEL = NCE44 - MSPI0 nCE, Channel 0 IOM2CE2 = 0x2 - Applies when PAD44FNCSEL = NCE44 - IOM2 nCE, Channel 2 IOM5CE2 = 0x3 - Applies when PAD44FNCSEL = NCE44 - IOM5 nCE, Channel 2 INTLH = 0x0 - Applies when PAD44FNCSEL != NCE44 and GPIO44INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD44FNCSEL != NCE44 and GPIO44INCFG = 0 - Interrupt on high to low GPIO transition |
| 16 | GPIO44INCFG | RW | GPIO44 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 15 | GPIO43INTD | RW | GPIO43 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD43FNCSEL = NCE43 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD43FNCSEL = NCE43 - nCE polarity active high INTDIS = 0x0 - Applies when PAD43FNCSEL != NCE43 and GPIO43INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD43FNCSEL != NCE43 and GPIO43INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD43FNCSEL != NCE43 and GPIO43INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD43FNCSEL != NCE43 and GPIO43INCFG = 0 - Interrupt on high to low GPIO transition |
| 14:13 | GPIO43OUTCFG | RW | GPIO43 output configuration. DIS = 0x0 - Applies when PAD43FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD43FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD43FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD43FNCSEL = GPIO - Output is tri-state IOM0CE1 = 0x0 - Applies when PAD43FNCSEL = NCE43 - IOM0 nCE, Channel 1 IOM1CE1 = 0x1 - Applies when PAD43FNCSEL = NCE43 - IOM1 nCE, Channel 1 MSPI2CE0 = 0x2 - Applies when PAD43FNCSEL = NCE43 - MSPI2 nCE, Channel 0 MSPI0CE1 = 0x3 - Applies when PAD43FNCSEL = NCE43 - MSPI0 nCE, Channel 1 INTLH = 0x0 - Applies when PAD43FNCSEL != NCE43 and GPIO43INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD43FNCSEL != NCE43 and GPIO43INCFG = 0 - Interrupt on high to low GPIO transition |
| 12 | GPIO43INCFG | RW | GPIO43 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 11 | GPIO42INTD | RW | GPIO42 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD42FNCSEL = NCE42 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD42FNCSEL = NCE42 - nCE polarity active high INTDIS = 0x0 - Applies when PAD42FNCSEL != NCE42 and GPIO42INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD42FNCSEL != NCE42 and GPIO42INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD42FNCSEL != NCE42 and GPIO42INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD42FNCSEL != NCE42 and GPIO42INCFG = 0 - Interrupt on high to low GPIO transition |
| 10:9 | GPIO42OUTCFG | RW | GPIO42 output configuration. DIS = 0x0 - Applies when PAD42FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD42FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD42FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD42FNCSEL = GPIO - Output is tri-state IOM0CE0 = 0x0 - Applies when PAD42FNCSEL = NCE42 - IOM0 nCE, Channel 0 MSPI1CE0 = 0x1 - Applies when PAD42FNCSEL = NCE42 - MSPI1 nCE, Channel 0 IOM2CE0 = 0x2 - Applies when PAD42FNCSEL = NCE42 - IOM2 nCE, Channel 0 IOM5CE0 = 0x3 - Applies when PAD42FNCSEL = NCE42 - IOM5 nCE, Channel 0 INTLH = 0x0 - Applies when PAD42FNCSEL != NCE42 and GPIO42INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD42FNCSEL != NCE42 and GPIO42INCFG = 0 - Interrupt on high to low GPIO transition |
| 8 | GPIO42INCFG | RW | GPIO42 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 7 | GPIO41INTD | RW | GPIO41 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD41FNCSEL = NCE41 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD41FNCSEL = NCE41 - nCE polarity active high INTDIS = 0x0 - Applies when PAD41FNCSEL != NCE41 and GPIO41INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD41FNCSEL != NCE41 and GPIO41INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD41FNCSEL != NCE41 and GPIO41INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD41FNCSEL != NCE41 and GPIO41INCFG = 0 - Interrupt on high to low GPIO transition |
| 6:5 | GPIO41OUTCFG | RW | GPIO41 output configuration. DIS = 0x0 - Applies when PAD41FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD41FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD41FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD41FNCSEL = GPIO - Output is tri-state MSPI2CE0 = 0x0 - Applies when PAD41FNCSEL = NCE41 - MSPI2 nCE, Channel 0 IOM1CE1 = 0x1 - Applies when PAD41FNCSEL = NCE41 - IOM1 nCE, Channel 1 MSPI1CE1 = 0x2 - Applies when PAD41FNCSEL = NCE41 - MSPI1 nCE, Channel 1 MSPI0CE1 = 0x3 - Applies when PAD41FNCSEL = NCE41 - MSPI0 nCE, Channel 1 INTLH = 0x0 - Applies when PAD41FNCSEL != NCE41 and GPIO41INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD41FNCSEL != NCE41 and GPIO41INCFG = 0 - Interrupt on high to low GPIO transition |
| 4 | GPIO41INCFG | RW | GPIO41 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 3 | GPIO40INTD | RW | GPIO40 interrupt direction, nCE polarity. INTDIS = 0x0 - Applies when GPIO40INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when GPIO40INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when GPIO40INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when GPIO40INCFG = 0 - Interrupt on high to low GPIO transition |
| 2:1 | GPIO40OUTCFG | RW | GPIO40 output configuration. DIS = 0x0 - Applies when PAD40FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD40FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD40FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD40FNCSEL = GPIO - Output is tri-state INTHL = 0x1 - Applies when GPIO40INCFG = 0 - Interrupt on high to low GPIO transition |
| 0 | GPIO40INCFG | RW | GPIO40 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| Instance 0 Address: | 0x40010064 |
GPIO configuration controls for GPIO[55:48]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO55INTD
0x0 |
GPIO55OUTCFG
0x0 |
GPIO55INCFG
0x0 |
GPIO54INTD
0x0 |
GPIO54OUTCFG
0x0 |
GPIO54INCFG
0x0 |
GPIO53INTD
0x0 |
GPIO53OUTCFG
0x0 |
GPIO53INCFG
0x0 |
GPIO52INTD
0x0 |
GPIO52OUTCFG
0x0 |
GPIO52INCFG
0x0 |
GPIO51INTD
0x0 |
GPIO51OUTCFG
0x0 |
GPIO51INCFG
0x0 |
GPIO50INTD
0x0 |
GPIO50OUTCFG
0x0 |
GPIO50INCFG
0x0 |
GPIO49INTD
0x0 |
GPIO49OUTCFG
0x0 |
GPIO49INCFG
0x0 |
GPIO48INTD
0x0 |
GPIO48OUTCFG
0x0 |
GPIO48INCFG
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO55INTD | RW | GPIO55 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD55FNCSEL = NCE55 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD55FNCSEL = NCE55 - nCE polarity active high INTDIS = 0x0 - Applies when PAD55FNCSEL != NCE55 and GPIO55INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD55FNCSEL != NCE55 and GPIO55INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD55FNCSEL != NCE55 and GPIO55INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD55FNCSEL != NCE55 and GPIO55INCFG = 0 - Interrupt on high to low GPIO transition |
| 30:29 | GPIO55OUTCFG | RW | GPIO55 output configuration. DIS = 0x0 - Applies when PAD55FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD55FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD55FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD55FNCSEL = GPIO - Output is tri-state IOM3CE0 = 0x0 - Applies when PAD55FNCSEL = NCE55 - IOM3 nCE, Channel 0 MSPI0CE0 = 0x1 - Applies when PAD55FNCSEL = NCE55 - MSPI0 nCE, Channel 0 IOM5CE1 = 0x2 - Applies when PAD55FNCSEL = NCE55 - IOM5 nCE, Channel 1 IOM4CE0 = 0x3 - Applies when PAD55FNCSEL = NCE55 - IOM4 nCE, Channel 0 INTLH = 0x0 - Applies when PAD55FNCSEL != NCE55 and GPIO55INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD55FNCSEL != NCE55 and GPIO55INCFG = 0 - Interrupt on high to low GPIO transition |
| 28 | GPIO55INCFG | RW | GPIO55 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 27 | GPIO54INTD | RW | GPIO54 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD54FNCSEL = NCE54 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD54FNCSEL = NCE54 - nCE polarity active high INTDIS = 0x0 - Applies when PAD54FNCSEL != NCE54 and GPIO54INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD54FNCSEL != NCE54 and GPIO54INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD54FNCSEL != NCE54 and GPIO54INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD54FNCSEL != NCE54 and GPIO54INCFG = 0 - Interrupt on high to low GPIO transition |
| 26:25 | GPIO54OUTCFG | RW | GPIO54 output configuration. DIS = 0x0 - Applies when PAD54FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD54FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD54FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD54FNCSEL = GPIO - Output is tri-state MSPI2CE0 = 0x0 - Applies when PAD54FNCSEL = NCE54 - MSPI2 nCE, Channel 0 IOM4CE0 = 0x1 - Applies when PAD54FNCSEL = NCE54 - IOM4 nCE, Channel 0 IOM5CE0 = 0x2 - Applies when PAD54FNCSEL = NCE54 - IOM5 nCE, Channel 0 IOM3CE0 = 0x3 - Applies when PAD54FNCSEL = NCE54 - IOM3 nCE, Channel 0 INTLH = 0x0 - Applies when PAD54FNCSEL != NCE54 and GPIO54INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD54FNCSEL != NCE54 and GPIO54INCFG = 0 - Interrupt on high to low GPIO transition |
| 24 | GPIO54INCFG | RW | GPIO54 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 23 | GPIO53INTD | RW | GPIO53 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD53FNCSEL = NCE53 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD53FNCSEL = NCE53 - nCE polarity active high INTDIS = 0x0 - Applies when PAD53FNCSEL != NCE53 and GPIO53INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD53FNCSEL != NCE53 and GPIO53INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD53FNCSEL != NCE53 and GPIO53INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD53FNCSEL != NCE53 and GPIO53INCFG = 0 - Interrupt on high to low GPIO transition |
| 22:21 | GPIO53OUTCFG | RW | GPIO53 output configuration. DIS = 0x0 - Applies when PAD53FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD53FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD53FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD53FNCSEL = GPIO - Output is tri-state IOM0CE2 = 0x0 - Applies when PAD53FNCSEL = NCE53 - IOM0 nCE, Channel 2 IOM1CE3 = 0x1 - Applies when PAD53FNCSEL = NCE53 - IOM1 nCE, Channel 3 MSPI2CE0 = 0x2 - Applies when PAD53FNCSEL = NCE53 - MSPI2 nCE, Channel 0 IOM2CE0 = 0x3 - Applies when PAD53FNCSEL = NCE53 - IOM2 nCE, Channel 0 INTLH = 0x0 - Applies when PAD53FNCSEL != NCE53 and GPIO53INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD53FNCSEL != NCE53 and GPIO53INCFG = 0 - Interrupt on high to low GPIO transition |
| 20 | GPIO53INCFG | RW | GPIO53 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 19 | GPIO52INTD | RW | GPIO52 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD52FNCSEL = NCE52 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD52FNCSEL = NCE52 - nCE polarity active high INTDIS = 0x0 - Applies when PAD52FNCSEL != NCE52 and GPIO52INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD52FNCSEL != NCE52 and GPIO52INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD52FNCSEL != NCE52 and GPIO52INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD52FNCSEL != NCE52 and GPIO52INCFG = 0 - Interrupt on high to low GPIO transition |
| 18:17 | GPIO52OUTCFG | RW | GPIO52 output configuration. DIS = 0x0 - Applies when PAD52FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD52FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD52FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD52FNCSEL = GPIO - Output is tri-state IOM0CE1 = 0x0 - Applies when PAD52FNCSEL = NCE52 - IOM0 nCE, Channel 1 IOM1CE2 = 0x1 - Applies when PAD52FNCSEL = NCE52 - IOM1 nCE, Channel 2 MSPI0CE0 = 0x2 - Applies when PAD52FNCSEL = NCE52 - MSPI0 nCE, Channel 0 IOM2CE1 = 0x3 - Applies when PAD52FNCSEL = NCE52 - IOM2 nCE, Channel 1 INTLH = 0x0 - Applies when PAD52FNCSEL != NCE52 and GPIO52INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD52FNCSEL != NCE52 and GPIO52INCFG = 0 - Interrupt on high to low GPIO transition |
| 16 | GPIO52INCFG | RW | GPIO52 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 15 | GPIO51INTD | RW | GPIO51 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD51FNCSEL = NCE51 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD51FNCSEL = NCE51 - nCE polarity active high INTDIS = 0x0 - Applies when PAD51FNCSEL != NCE51 and GPIO51INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD51FNCSEL != NCE51 and GPIO51INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD51FNCSEL != NCE51 and GPIO51INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD51FNCSEL != NCE51 and GPIO51INCFG = 0 - Interrupt on high to low GPIO transition |
| 14:13 | GPIO51OUTCFG | RW | GPIO51 output configuration. DIS = 0x0 - Applies when PAD51FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD51FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD51FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD51FNCSEL = GPIO - Output is tri-state IOM4CE2 = 0x0 - Applies when PAD51FNCSEL = NCE51 - IOM4 nCE, Channel 2 IOM1CE1 = 0x1 - Applies when PAD51FNCSEL = NCE51 - IOM1 nCE, Channel 1 IOM2CE1 = 0x2 - Applies when PAD51FNCSEL = NCE51 - IOM2 nCE, Channel 1 IOM0CE0 = 0x3 - Applies when PAD51FNCSEL = NCE51 - IOM0 nCE, Channel 0 INTLH = 0x0 - Applies when PAD51FNCSEL != NCE51 and GPIO51INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD51FNCSEL != NCE51 and GPIO51INCFG = 0 - Interrupt on high to low GPIO transition |
| 12 | GPIO51INCFG | RW | GPIO51 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 11 | GPIO50INTD | RW | GPIO50 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD50FNCSEL = NCE50 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD50FNCSEL = NCE50 - nCE polarity active high INTDIS = 0x0 - Applies when PAD50FNCSEL != NCE50 and GPIO50INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD50FNCSEL != NCE50 and GPIO50INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD50FNCSEL != NCE50 and GPIO50INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD50FNCSEL != NCE50 and GPIO50INCFG = 0 - Interrupt on high to low GPIO transition |
| 10:9 | GPIO50OUTCFG | RW | GPIO50 output configuration. DIS = 0x0 - Applies when PAD50FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD50FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD50FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD50FNCSEL = GPIO - Output is tri-state MSPI1CE0 = 0x0 - Applies when PAD50FNCSEL = NCE50 - MSPI1 nCE, Channel 0 MSPI2CE0 = 0x1 - Applies when PAD50FNCSEL = NCE50 - MSPI2 nCE, Channel 0 IOM2CE3 = 0x2 - Applies when PAD50FNCSEL = NCE50 - IOM2 nCE, Channel 3 IOM0CE0 = 0x3 - Applies when PAD50FNCSEL = NCE50 - IOM0 nCE, Channel 0 INTLH = 0x0 - Applies when PAD50FNCSEL != NCE50 and GPIO50INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD50FNCSEL != NCE50 and GPIO50INCFG = 0 - Interrupt on high to low GPIO transition |
| 8 | GPIO50INCFG | RW | GPIO50 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 7 | GPIO49INTD | RW | GPIO49 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD49FNCSEL = NCE49 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD49FNCSEL = NCE49 - nCE polarity active high INTDIS = 0x0 - Applies when PAD49FNCSEL != NCE49 and GPIO49INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD49FNCSEL != NCE49 and GPIO49INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD49FNCSEL != NCE49 and GPIO49INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD49FNCSEL != NCE49 and GPIO49INCFG = 0 - Interrupt on high to low GPIO transition |
| 6:5 | GPIO49OUTCFG | RW | GPIO49 output configuration. DIS = 0x0 - Applies when PAD49FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD49FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD49FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD49FNCSEL = GPIO - Output is tri-state IOM0CE3 = 0x0 - Applies when PAD49FNCSEL = NCE49 - IOM0 nCE, Channel 3 MSPI1CE1 = 0x1 - Applies when PAD49FNCSEL = NCE49 - MSPI1 nCE, Channel 1 IOM2CE3 = 0x2 - Applies when PAD49FNCSEL = NCE49 - IOM2 nCE, Channel 3 IOM1CE0 = 0x3 - Applies when PAD49FNCSEL = NCE49 - IOM1 nCE, Channel 0 INTLH = 0x0 - Applies when PAD49FNCSEL != NCE49 and GPIO49INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD49FNCSEL != NCE49 and GPIO49INCFG = 0 - Interrupt on high to low GPIO transition |
| 4 | GPIO49INCFG | RW | GPIO49 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 3 | GPIO48INTD | RW | GPIO48 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD48FNCSEL = NCE48 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD48FNCSEL = NCE48 - nCE polarity active high INTDIS = 0x0 - Applies when PAD48FNCSEL != NCE48 and GPIO48INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD48FNCSEL != NCE48 and GPIO48INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD48FNCSEL != NCE48 and GPIO48INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD48FNCSEL != NCE48 and GPIO48INCFG = 0 - Interrupt on high to low GPIO transition |
| 2:1 | GPIO48OUTCFG | RW | GPIO48 output configuration. DIS = 0x0 - Applies when PAD48FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD48FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD48FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD48FNCSEL = GPIO - Output is tri-state MSPI1CE0 = 0x0 - Applies when PAD48FNCSEL = NCE48 - MSPI1 nCE, Channel 0 IOM1CE2 = 0x1 - Applies when PAD48FNCSEL = NCE48 - IOM1 nCE, Channel 2 IOM2CE2 = 0x2 - Applies when PAD48FNCSEL = NCE48 - IOM2 nCE, Channel 2 MSPI2CE1 = 0x3 - Applies when PAD48FNCSEL = NCE48 - MSPI2 nCE, Channel 1 INTLH = 0x0 - Applies when PAD48FNCSEL != NCE48 and GPIO48INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD48FNCSEL != NCE48 and GPIO48INCFG = 0 - Interrupt on high to low GPIO transition |
| 0 | GPIO48INCFG | RW | GPIO48 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| Instance 0 Address: | 0x40010068 |
GPIO configuration controls for GPIO[63:56]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO63INTD
0x0 |
GPIO63OUTCFG
0x0 |
GPIO63INCFG
0x0 |
GPIO62INTD
0x0 |
GPIO62OUTCFG
0x0 |
GPIO62INCFG
0x0 |
GPIO61INTD
0x0 |
GPIO61OUTCFG
0x0 |
GPIO61INCFG
0x0 |
GPIO60INTD
0x0 |
GPIO60OUTCFG
0x0 |
GPIO60INCFG
0x0 |
GPIO59INTD
0x0 |
GPIO59OUTCFG
0x0 |
GPIO59INCFG
0x0 |
GPIO58INTD
0x0 |
GPIO58OUTCFG
0x0 |
GPIO58INCFG
0x0 |
GPIO57INTD
0x0 |
GPIO57OUTCFG
0x0 |
GPIO57INCFG
0x0 |
GPIO56INTD
0x0 |
GPIO56OUTCFG
0x0 |
GPIO56INCFG
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO63INTD | RW | GPIO63 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD63FNCSEL = NCE63 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD63FNCSEL = NCE63 - nCE polarity active high INTDIS = 0x0 - Applies when PAD63FNCSEL != NCE63 and GPIO63INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD63FNCSEL != NCE63 and GPIO63INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD63FNCSEL != NCE63 and GPIO63INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD63FNCSEL != NCE63 and GPIO63INCFG = 0 - Interrupt on high to low GPIO transition |
| 30:29 | GPIO63OUTCFG | RW | GPIO63 output configuration. DIS = 0x0 - Applies when PAD63FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD63FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD63FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD63FNCSEL = GPIO - Output is tri-state MSPI1CE0 = 0x0 - Applies when PAD63FNCSEL = NCE63 - MSPI1 nCE, Channel 0 IOM4CE1 = 0x1 - Applies when PAD63FNCSEL = NCE63 - IOM4 nCE, Channel 1 MSPI2CE0 = 0x2 - Applies when PAD63FNCSEL = NCE63 - MSPI2 nCE, Channel 0 MSPI0CE0 = 0x3 - Applies when PAD63FNCSEL = NCE63 - MSPI0 nCE, Channel 0 INTLH = 0x0 - Applies when PAD63FNCSEL != NCE63 and GPIO63INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD63FNCSEL != NCE63 and GPIO63INCFG = 0 - Interrupt on high to low GPIO transition |
| 28 | GPIO63INCFG | RW | GPIO63 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 27 | GPIO62INTD | RW | GPIO62 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD62FNCSEL = NCE62 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD62FNCSEL = NCE62 - nCE polarity active high INTDIS = 0x0 - Applies when PAD62FNCSEL != NCE62 and GPIO62INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD62FNCSEL != NCE62 and GPIO62INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD62FNCSEL != NCE62 and GPIO62INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD62FNCSEL != NCE62 and GPIO62INCFG = 0 - Interrupt on high to low GPIO transition |
| 26:25 | GPIO62OUTCFG | RW | GPIO62 output configuration. DIS = 0x0 - Applies when PAD62FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD62FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD62FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD62FNCSEL = GPIO - Output is tri-state MSPI0CE1 = 0x0 - Applies when PAD62FNCSEL = NCE62 - MSPI0 nCE, Channel 1 IOM4CE0 = 0x1 - Applies when PAD62FNCSEL = NCE62 - IOM4 nCE, Channel 0 IOM5CE0 = 0x2 - Applies when PAD62FNCSEL = NCE62 - IOM5 nCE, Channel 0 MSPI1CE1 = 0x3 - Applies when PAD62FNCSEL = NCE62 - MSPI1 nCE, Channel 1 INTLH = 0x0 - Applies when PAD62FNCSEL != NCE62 and GPIO62INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD62FNCSEL != NCE62 and GPIO62INCFG = 0 - Interrupt on high to low GPIO transition |
| 24 | GPIO62INCFG | RW | GPIO62 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 23 | GPIO61INTD | RW | GPIO61 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD61FNCSEL = NCE61 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD61FNCSEL = NCE61 - nCE polarity active high INTDIS = 0x0 - Applies when PAD61FNCSEL != NCE61 and GPIO61INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD61FNCSEL != NCE61 and GPIO61INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD61FNCSEL != NCE61 and GPIO61INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD61FNCSEL != NCE61 and GPIO61INCFG = 0 - Interrupt on high to low GPIO transition |
| 22:21 | GPIO61OUTCFG | RW | GPIO61 output configuration. DIS = 0x0 - Applies when PAD61FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD61FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD61FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD61FNCSEL = GPIO - Output is tri-state MSPI0CE0 = 0x0 - Applies when PAD61FNCSEL = NCE61 - MSPI0 nCE, Channel 0 IOM1CE3 = 0x1 - Applies when PAD61FNCSEL = NCE61 - IOM1 nCE, Channel 3 MSPI2CE0 = 0x2 - Applies when PAD61FNCSEL = NCE61 - MSPI2 nCE, Channel 0 MSPI1CE0 = 0x3 - Applies when PAD61FNCSEL = NCE61 - MSPI1 nCE, Channel 0 INTLH = 0x0 - Applies when PAD61FNCSEL != NCE61 and GPIO61INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD61FNCSEL != NCE61 and GPIO61INCFG = 0 - Interrupt on high to low GPIO transition |
| 20 | GPIO61INCFG | RW | GPIO61 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 19 | GPIO60INTD | RW | GPIO60 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD60FNCSEL = NCE60 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD60FNCSEL = NCE60 - nCE polarity active high INTDIS = 0x0 - Applies when PAD60FNCSEL != NCE60 and GPIO60INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD60FNCSEL != NCE60 and GPIO60INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD60FNCSEL != NCE60 and GPIO60INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD60FNCSEL != NCE60 and GPIO60INCFG = 0 - Interrupt on high to low GPIO transition |
| 18:17 | GPIO60OUTCFG | RW | GPIO60 output configuration. DIS = 0x0 - Applies when PAD60FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD60FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD60FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD60FNCSEL = GPIO - Output is tri-state MSPI0CE1 = 0x0 - Applies when PAD60FNCSEL = NCE60 - MSPI0 nCE, Channel 1 IOM1CE2 = 0x1 - Applies when PAD60FNCSEL = NCE60 - IOM1 nCE, Channel 2 IOM2CE2 = 0x2 - Applies when PAD60FNCSEL = NCE60 - IOM2 nCE, Channel 2 IOM0CE3 = 0x3 - Applies when PAD60FNCSEL = NCE60 - IOM0 nCE, Channel 3 INTLH = 0x0 - Applies when PAD60FNCSEL != NCE60 and GPIO60INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD60FNCSEL != NCE60 and GPIO60INCFG = 0 - Interrupt on high to low GPIO transition |
| 16 | GPIO60INCFG | RW | GPIO60 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 15 | GPIO59INTD | RW | GPIO59 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD59FNCSEL = NCE59 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD59FNCSEL = NCE59 - nCE polarity active high INTDIS = 0x0 - Applies when PAD59FNCSEL != NCE59 and GPIO59INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD59FNCSEL != NCE59 and GPIO59INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD59FNCSEL != NCE59 and GPIO59INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD59FNCSEL != NCE59 and GPIO59INCFG = 0 - Interrupt on high to low GPIO transition |
| 14:13 | GPIO59OUTCFG | RW | GPIO59 output configuration. DIS = 0x0 - Applies when PAD59FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD59FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD59FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD59FNCSEL = GPIO - Output is tri-state MSPI1CE1 = 0x0 - Applies when PAD59FNCSEL = NCE59 - MSPI1 nCE, Channel 1 IOM1CE1 = 0x1 - Applies when PAD59FNCSEL = NCE59 - IOM1 nCE, Channel 1 IOM2CE1 = 0x2 - Applies when PAD59FNCSEL = NCE59 - IOM2 nCE, Channel 1 MSPI0CE0 = 0x3 - Applies when PAD59FNCSEL = NCE59 - MSPI0 nCE, Channel 0 INTLH = 0x0 - Applies when PAD59FNCSEL != NCE59 and GPIO59INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD59FNCSEL != NCE59 and GPIO59INCFG = 0 - Interrupt on high to low GPIO transition |
| 12 | GPIO59INCFG | RW | GPIO59 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 11 | GPIO58INTD | RW | GPIO58 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD58FNCSEL = NCE58 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD58FNCSEL = NCE58 - nCE polarity active high INTDIS = 0x0 - Applies when PAD58FNCSEL != NCE58 and GPIO58INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD58FNCSEL != NCE58 and GPIO58INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD58FNCSEL != NCE58 and GPIO58INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD58FNCSEL != NCE58 and GPIO58INCFG = 0 - Interrupt on high to low GPIO transition |
| 10:9 | GPIO58OUTCFG | RW | GPIO58 output configuration. DIS = 0x0 - Applies when PAD58FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD58FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD58FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD58FNCSEL = GPIO - Output is tri-state IOM3CE3 = 0x0 - Applies when PAD58FNCSEL = NCE58 - IOM3 nCE, Channel 3 IOM1CE0 = 0x1 - Applies when PAD58FNCSEL = NCE58 - IOM1 nCE, Channel 0 MSPI0CE0 = 0x2 - Applies when PAD58FNCSEL = NCE58 - MSPI0 nCE, Channel 0 IOM5CE3 = 0x3 - Applies when PAD58FNCSEL = NCE58 - IOM5 nCE, Channel 3 INTLH = 0x0 - Applies when PAD58FNCSEL != NCE58 and GPIO58INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD58FNCSEL != NCE58 and GPIO58INCFG = 0 - Interrupt on high to low GPIO transition |
| 8 | GPIO58INCFG | RW | GPIO58 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 7 | GPIO57INTD | RW | GPIO57 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD57FNCSEL = NCE57 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD57FNCSEL = NCE57 - nCE polarity active high INTDIS = 0x0 - Applies when PAD57FNCSEL != NCE57 and GPIO57INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD57FNCSEL != NCE57 and GPIO57INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD57FNCSEL != NCE57 and GPIO57INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD57FNCSEL != NCE57 and GPIO57INCFG = 0 - Interrupt on high to low GPIO transition |
| 6:5 | GPIO57OUTCFG | RW | GPIO57 output configuration. DIS = 0x0 - Applies when PAD57FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD57FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD57FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD57FNCSEL = GPIO - Output is tri-state MSPI0CE0 = 0x0 - Applies when PAD57FNCSEL = NCE57 - MSPI0 nCE, Channel 0 IOM4CE3 = 0x1 - Applies when PAD57FNCSEL = NCE57 - IOM4 nCE, Channel 3 IOM5CE3 = 0x2 - Applies when PAD57FNCSEL = NCE57 - IOM5 nCE, Channel 3 IOM0CE1 = 0x3 - Applies when PAD57FNCSEL = NCE57 - IOM0 nCE, Channel 1 INTLH = 0x0 - Applies when PAD57FNCSEL != NCE57 and GPIO57INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD57FNCSEL != NCE57 and GPIO57INCFG = 0 - Interrupt on high to low GPIO transition |
| 4 | GPIO57INCFG | RW | GPIO57 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 3 | GPIO56INTD | RW | GPIO56 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD56FNCSEL = NCE56 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD56FNCSEL = NCE56 - nCE polarity active high INTDIS = 0x0 - Applies when PAD56FNCSEL != NCE56 and GPIO56INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD56FNCSEL != NCE56 and GPIO56INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD56FNCSEL != NCE56 and GPIO56INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD56FNCSEL != NCE56 and GPIO56INCFG = 0 - Interrupt on high to low GPIO transition |
| 2:1 | GPIO56OUTCFG | RW | GPIO56 output configuration. DIS = 0x0 - Applies when PAD56FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD56FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD56FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD56FNCSEL = GPIO - Output is tri-state IOM3CE2 = 0x0 - Applies when PAD56FNCSEL = NCE56 - IOM3 nCE, Channel 2 IOM4CE3 = 0x1 - Applies when PAD56FNCSEL = NCE56 - IOM4 nCE, Channel 3 IOM5CE2 = 0x2 - Applies when PAD56FNCSEL = NCE56 - IOM5 nCE, Channel 2 MSPI0CE1 = 0x3 - Applies when PAD56FNCSEL = NCE56 - MSPI0 nCE, Channel 1 INTLH = 0x0 - Applies when PAD56FNCSEL != NCE56 and GPIO56INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD56FNCSEL != NCE56 and GPIO56INCFG = 0 - Interrupt on high to low GPIO transition |
| 0 | GPIO56INCFG | RW | GPIO56 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| Instance 0 Address: | 0x4001006C |
GPIO configuration controls for GPIO[71:64]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| GPIO71INTD
0x0 |
GPIO71OUTCFG
0x0 |
GPIO71INCFG
0x0 |
GPIO70INTD
0x0 |
GPIO70OUTCFG
0x0 |
GPIO70INCFG
0x0 |
GPIO69INTD
0x0 |
GPIO69OUTCFG
0x0 |
GPIO69INCFG
0x0 |
GPIO68INTD
0x0 |
GPIO68OUTCFG
0x0 |
GPIO68INCFG
0x0 |
GPIO67INTD
0x0 |
GPIO67OUTCFG
0x0 |
GPIO67INCFG
0x0 |
GPIO66INTD
0x0 |
GPIO66OUTCFG
0x0 |
GPIO66INCFG
0x0 |
GPIO65INTD
0x0 |
GPIO65OUTCFG
0x0 |
GPIO65INCFG
0x0 |
GPIO64INTD
0x0 |
GPIO64OUTCFG
0x0 |
GPIO64INCFG
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | GPIO71INTD | RW | GPIO71 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD71FNCSEL = NCE71 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD71FNCSEL = NCE71 - nCE polarity active high INTDIS = 0x0 - Applies when PAD71FNCSEL != NCE71 and GPIO71INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD71FNCSEL != NCE71 and GPIO71INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD71FNCSEL != NCE71 and GPIO71INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD71FNCSEL != NCE71 and GPIO71INCFG = 0 - Interrupt on high to low GPIO transition |
| 30:29 | GPIO71OUTCFG | RW | GPIO71 output configuration. DIS = 0x0 - Applies when PAD71FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD71FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD71FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD71FNCSEL = GPIO - Output is tri-state IOM3CE3 = 0x0 - Applies when PAD71FNCSEL = NCE71 - IOM3 nCE, Channel 3 IOM4CE1 = 0x1 - Applies when PAD71FNCSEL = NCE71 - IOM4 nCE, Channel 1 IOM0CE3 = 0x2 - Applies when PAD71FNCSEL = NCE71 - IOM0 nCE, Channel 3 IOM1CE2 = 0x3 - Applies when PAD71FNCSEL = NCE71 - IOM1 nCE, Channel 2 INTLH = 0x0 - Applies when PAD71FNCSEL != NCE71 and GPIO71INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD71FNCSEL != NCE71 and GPIO71INCFG = 0 - Interrupt on high to low GPIO transition |
| 28 | GPIO71INCFG | RW | GPIO71 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 27 | GPIO70INTD | RW | GPIO70 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD70FNCSEL = NCE70 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD70FNCSEL = NCE70 - nCE polarity active high INTDIS = 0x0 - Applies when PAD70FNCSEL != NCE70 and GPIO70INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD70FNCSEL != NCE70 and GPIO70INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD70FNCSEL != NCE70 and GPIO70INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD70FNCSEL != NCE70 and GPIO70INCFG = 0 - Interrupt on high to low GPIO transition |
| 26:25 | GPIO70OUTCFG | RW | GPIO70 output configuration. DIS = 0x0 - Applies when PAD70FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD70FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD70FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD70FNCSEL = GPIO - Output is tri-state IOM3CE2 = 0x0 - Applies when PAD70FNCSEL = NCE70 - IOM3 nCE, Channel 2 MSPI2CE0 = 0x1 - Applies when PAD70FNCSEL = NCE70 - MSPI2 nCE, Channel 0 IOM5CE0 = 0x2 - Applies when PAD70FNCSEL = NCE70 - IOM5 nCE, Channel 0 MSPI1CE1 = 0x3 - Applies when PAD70FNCSEL = NCE70 - MSPI1 nCE, Channel 1 INTLH = 0x0 - Applies when PAD70FNCSEL != NCE70 and GPIO70INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD70FNCSEL != NCE70 and GPIO70INCFG = 0 - Interrupt on high to low GPIO transition |
| 24 | GPIO70INCFG | RW | GPIO70 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 23 | GPIO69INTD | RW | GPIO69 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD69FNCSEL = NCE69 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD69FNCSEL = NCE69 - nCE polarity active high INTDIS = 0x0 - Applies when PAD69FNCSEL != NCE69 and GPIO69INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD69FNCSEL != NCE69 and GPIO69INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD69FNCSEL != NCE69 and GPIO69INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD69FNCSEL != NCE69 and GPIO69INCFG = 0 - Interrupt on high to low GPIO transition |
| 22:21 | GPIO69OUTCFG | RW | GPIO69 output configuration. DIS = 0x0 - Applies when PAD69FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD69FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD69FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD69FNCSEL = GPIO - Output is tri-state IOM3CE1 = 0x0 - Applies when PAD69FNCSEL = NCE69 - IOM3 nCE, Channel 1 IOM1CE3 = 0x1 - Applies when PAD69FNCSEL = NCE69 - IOM1 nCE, Channel 3 MSPI0CE0 = 0x2 - Applies when PAD69FNCSEL = NCE69 - MSPI0 nCE, Channel 0 MSPI1CE0 = 0x3 - Applies when PAD69FNCSEL = NCE69 - MSPI1 nCE, Channel 0 INTLH = 0x0 - Applies when PAD69FNCSEL != NCE69 and GPIO69INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD69FNCSEL != NCE69 and GPIO69INCFG = 0 - Interrupt on high to low GPIO transition |
| 20 | GPIO69INCFG | RW | GPIO69 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 19 | GPIO68INTD | RW | GPIO68 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD68FNCSEL = NCE68 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD68FNCSEL = NCE68 - nCE polarity active high INTDIS = 0x0 - Applies when PAD68FNCSEL != NCE68 and GPIO68INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD68FNCSEL != NCE68 and GPIO68INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD68FNCSEL != NCE68 and GPIO68INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD68FNCSEL != NCE68 and GPIO68INCFG = 0 - Interrupt on high to low GPIO transition |
| 18:17 | GPIO68OUTCFG | RW | GPIO68 output configuration. DIS = 0x0 - Applies when PAD68FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD68FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD68FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD68FNCSEL = GPIO - Output is tri-state IOM3CE0 = 0x0 - Applies when PAD68FNCSEL = NCE68 - IOM3 nCE, Channel 0 MSPI0CE0 = 0x1 - Applies when PAD68FNCSEL = NCE68 - MSPI0 nCE, Channel 0 IOM2CE2 = 0x2 - Applies when PAD68FNCSEL = NCE68 - IOM2 nCE, Channel 2 IOM0CE2 = 0x3 - Applies when PAD68FNCSEL = NCE68 - IOM0 nCE, Channel 2 INTLH = 0x0 - Applies when PAD68FNCSEL != NCE68 and GPIO68INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD68FNCSEL != NCE68 and GPIO68INCFG = 0 - Interrupt on high to low GPIO transition |
| 16 | GPIO68INCFG | RW | GPIO68 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 15 | GPIO67INTD | RW | GPIO67 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD67FNCSEL = NCE67 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD67FNCSEL = NCE67 - nCE polarity active high INTDIS = 0x0 - Applies when PAD67FNCSEL != NCE67 and GPIO67INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD67FNCSEL != NCE67 and GPIO67INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD67FNCSEL != NCE67 and GPIO67INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD67FNCSEL != NCE67 and GPIO67INCFG = 0 - Interrupt on high to low GPIO transition |
| 14:13 | GPIO67OUTCFG | RW | GPIO67 output configuration. DIS = 0x0 - Applies when PAD67FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD67FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD67FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD67FNCSEL = GPIO - Output is tri-state IOM0CE3 = 0x0 - Applies when PAD67FNCSEL = NCE67 - IOM0 nCE, Channel 3 IOM1CE1 = 0x1 - Applies when PAD67FNCSEL = NCE67 - IOM1 nCE, Channel 1 IOM2CE3 = 0x2 - Applies when PAD67FNCSEL = NCE67 - IOM2 nCE, Channel 3 IOM5CE1 = 0x3 - Applies when PAD67FNCSEL = NCE67 - IOM5 nCE, Channel 1 INTLH = 0x0 - Applies when PAD67FNCSEL != NCE67 and GPIO67INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD67FNCSEL != NCE67 and GPIO67INCFG = 0 - Interrupt on high to low GPIO transition |
| 12 | GPIO67INCFG | RW | GPIO67 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 11 | GPIO66INTD | RW | GPIO66 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD66FNCSEL = NCE66 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD66FNCSEL = NCE66 - nCE polarity active high INTDIS = 0x0 - Applies when PAD66FNCSEL != NCE66 and GPIO66INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD66FNCSEL != NCE66 and GPIO66INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD66FNCSEL != NCE66 and GPIO66INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD66FNCSEL != NCE66 and GPIO66INCFG = 0 - Interrupt on high to low GPIO transition |
| 10:9 | GPIO66OUTCFG | RW | GPIO66 output configuration. DIS = 0x0 - Applies when PAD66FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD66FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD66FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD66FNCSEL = GPIO - Output is tri-state MSPI1CE0 = 0x0 - Applies when PAD66FNCSEL = NCE66 - MSPI1 nCE, Channel 0 IOM1CE0 = 0x1 - Applies when PAD66FNCSEL = NCE66 - IOM1 nCE, Channel 0 IOM2CE0 = 0x2 - Applies when PAD66FNCSEL = NCE66 - IOM2 nCE, Channel 0 IOM4CE1 = 0x3 - Applies when PAD66FNCSEL = NCE66 - IOM4 nCE, Channel 1 INTLH = 0x0 - Applies when PAD66FNCSEL != NCE66 and GPIO66INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD66FNCSEL != NCE66 and GPIO66INCFG = 0 - Interrupt on high to low GPIO transition |
| 8 | GPIO66INCFG | RW | GPIO66 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 7 | GPIO65INTD | RW | GPIO65 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD65FNCSEL = NCE65 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD65FNCSEL = NCE65 - nCE polarity active high INTDIS = 0x0 - Applies when PAD65FNCSEL != NCE65 and GPIO65INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD65FNCSEL != NCE65 and GPIO65INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD65FNCSEL != NCE65 and GPIO65INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD65FNCSEL != NCE65 and GPIO65INCFG = 0 - Interrupt on high to low GPIO transition |
| 6:5 | GPIO65OUTCFG | RW | GPIO65 output configuration. DIS = 0x0 - Applies when PAD65FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD65FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD65FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD65FNCSEL = GPIO - Output is tri-state IOM0CE1 = 0x0 - Applies when PAD65FNCSEL = NCE65 - IOM0 nCE, Channel 1 MSPI0CE0 = 0x1 - Applies when PAD65FNCSEL = NCE65 - MSPI0 nCE, Channel 0 IOM5CE2 = 0x2 - Applies when PAD65FNCSEL = NCE65 - IOM5 nCE, Channel 2 IOM3CE1 = 0x3 - Applies when PAD65FNCSEL = NCE65 - IOM3 nCE, Channel 1 INTLH = 0x0 - Applies when PAD65FNCSEL != NCE65 and GPIO65INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD65FNCSEL != NCE65 and GPIO65INCFG = 0 - Interrupt on high to low GPIO transition |
| 4 | GPIO65INCFG | RW | GPIO65 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 3 | GPIO64INTD | RW | GPIO64 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD64FNCSEL = NCE64 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD64FNCSEL = NCE64 - nCE polarity active high INTDIS = 0x0 - Applies when PAD64FNCSEL != NCE64 and GPIO64INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD64FNCSEL != NCE64 and GPIO64INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD64FNCSEL != NCE64 and GPIO64INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD64FNCSEL != NCE64 and GPIO64INCFG = 0 - Interrupt on high to low GPIO transition |
| 2:1 | GPIO64OUTCFG | RW | GPIO64 output configuration. DIS = 0x0 - Applies when PAD64FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD64FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD64FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD64FNCSEL = GPIO - Output is tri-state IOM0CE0 = 0x0 - Applies when PAD64FNCSEL = NCE64 - IOM0 nCE, Channel 0 IOM4CE2 = 0x1 - Applies when PAD64FNCSEL = NCE64 - IOM4 nCE, Channel 2 IOM5CE2 = 0x2 - Applies when PAD64FNCSEL = NCE64 - IOM5 nCE, Channel 2 MSPI0CE1 = 0x3 - Applies when PAD64FNCSEL = NCE64 - MSPI0 nCE, Channel 1 INTLH = 0x0 - Applies when PAD64FNCSEL != NCE64 and GPIO64INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD64FNCSEL != NCE64 and GPIO64INCFG = 0 - Interrupt on high to low GPIO transition |
| 0 | GPIO64INCFG | RW | GPIO64 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| Instance 0 Address: | 0x40010070 |
GPIO configuration controls for GPIO[73:72]. Writes to this register must be unlocked by the PADKEY register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
RSVD
0x0 |
RSVD
0x0 |
RSVD
0x0 |
RSVD
0x0 |
RSVD
0x0 |
GPIO73INTD
0x0 |
GPIO73OUTCFG
0x0 |
GPIO73INCFG
0x0 |
GPIO72INTD
0x0 |
GPIO72OUTCFG
0x0 |
GPIO72INCFG
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:28 | RSVD | RO | RESERVED |
| 27:24 | RSVD | RO | RESERVED |
| 23:20 | RSVD | RO | RESERVED |
| 19:16 | RSVD | RO | RESERVED |
| 15:12 | RSVD | RO | RESERVED |
| 11:8 | RSVD | RO | RESERVED |
| 7 | GPIO73INTD | RW | GPIO73 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD73FNCSEL = NCE73 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD73FNCSEL = NCE73 - nCE polarity active high INTDIS = 0x0 - Applies when PAD73FNCSEL != NCE73 and GPIO73INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD73FNCSEL != NCE73 and GPIO73INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD73FNCSEL != NCE73 and GPIO73INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD73FNCSEL != NCE73 and GPIO73INCFG = 0 - Interrupt on high to low GPIO transition |
| 6:5 | GPIO73OUTCFG | RW | GPIO73 output configuration. DIS = 0x0 - Applies when PAD73FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD73FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD73FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD73FNCSEL = GPIO - Output is tri-state MSPI1CE0 = 0x0 - Applies when PAD73FNCSEL = NCE73 - MSPI1 nCE, Channel 0 IOM4CE3 = 0x1 - Applies when PAD73FNCSEL = NCE73 - IOM4 nCE, Channel 3 IOM5CE3 = 0x2 - Applies when PAD73FNCSEL = NCE73 - IOM5 nCE, Channel 3 MSPI2CE0 = 0x3 - Applies when PAD73FNCSEL = NCE73 - MSPI2 nCE, Channel 0 INTLH = 0x0 - Applies when PAD73FNCSEL != NCE73 and GPIO73INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD73FNCSEL != NCE73 and GPIO73INCFG = 0 - Interrupt on high to low GPIO transition |
| 4 | GPIO73INCFG | RW | GPIO73 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| 3 | GPIO72INTD | RW | GPIO72 interrupt direction, nCE polarity. nCELOW = 0x0 - Applies when PAD72FNCSEL = NCE72 - nCE polarity active low nCEHIGH = 0x1 - Applies when PAD72FNCSEL = NCE72 - nCE polarity active high INTDIS = 0x0 - Applies when PAD72FNCSEL != NCE72 and GPIO72INCFG = 1 - No interrupt on GPIO transition INTBOTH = 0x1 - Applies when PAD72FNCSEL != NCE72 and GPIO72INCFG = 1 - Interrupt on either low to high or high to low GPIO transition INTLH = 0x0 - Applies when PAD72FNCSEL != NCE72 and GPIO72INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD72FNCSEL != NCE72 and GPIO72INCFG = 0 - Interrupt on high to low GPIO transition |
| 2:1 | GPIO72OUTCFG | RW | GPIO72 output configuration. DIS = 0x0 - Applies when PAD72FNCSEL = GPIO - Output disabled PUSHPULL = 0x1 - Applies when PAD72FNCSEL = GPIO - Output is push-pull OD = 0x2 - Applies when PAD72FNCSEL = GPIO - Output is open drain TS = 0x3 - Applies when PAD72FNCSEL = GPIO - Output is tri-state MSPI0CE0 = 0x0 - Applies when PAD72FNCSEL = NCE72 - MSPI0 nCE, Channel 0 MSPI2CE0 = 0x1 - Applies when PAD72FNCSEL = NCE72 - MSPI2 nCE, Channel 0 MSPI1CE0 = 0x2 - Applies when PAD72FNCSEL = NCE72 - MSPI1 nCE, Channel 0 IOM2CE2 = 0x3 - Applies when PAD72FNCSEL = NCE72 - IOM2 nCE, Channel 2 INTLH = 0x0 - Applies when PAD72FNCSEL != NCE72 and GPIO72INCFG = 0 - Interrupt on low to high GPIO transition INTHL = 0x1 - Applies when PAD72FNCSEL != NCE72 and GPIO72INCFG = 0 - Interrupt on high to low GPIO transition |
| 0 | GPIO72INCFG | RW | GPIO72 input enable. READ = 0x0 - Read the GPIO pin data RDZERO = 0x1 - INTD = 0 - Read-back will always be zero READEN = 0x1 - INTD = 1 - Read the GPIO pin data |
| Instance 0 Address: | 0x40010074 |
Lock state of the PINCFG and GPIO configuration registers. Write a value of 0x73 to unlock write access to the PAD and GPIO configuration registers. Write any other value to lock access to PAD and GPIO registers. This register also indicates lock status when read. When in the unlocked state (i.e. 0x73 has been written), it reads as 1. When in the locked state, it reads as 0.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PADKEY
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | PADKEY | RW | Key register value. Key = 0x73 - Key value to unlock the register. |
| Instance 0 Address: | 0x40010080 |
GPIO Input A (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RDA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | RDA | RO | GPIO31-0 read data. |
| Instance 0 Address: | 0x40010084 |
GPIO Input B (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RDB
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | RDB | RO | GPIO63-32 read data. |
| Instance 0 Address: | 0x40010088 |
GPIO Input C (73-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
RDC
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED |
| 9:0 | RDC | RO | GPIO73-64 read data. |
| Instance 0 Address: | 0x4001008C |
GPIO Output A (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WTA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTA | RW | GPIO31-0 write data. |
| Instance 0 Address: | 0x40010090 |
GPIO Output B (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| WTB
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTB | RW | GPIO63-32 write data. |
| Instance 0 Address: | 0x40010094 |
GPIO Output C (73-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| RSVD
0x0 |
WTC
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED |
| 9:0 | WTC | RW | GPIO73-64 write data. |
| Instance 0 Address: | 0x40010098 |
GPIO Output A Set (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| WTSA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTSA | WO | Set the GPIO31-0 write data. |
| Instance 0 Address: | 0x4001009C |
GPIO Output B Set (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| WTSB
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTSB | WO | Set the GPIO63-32 write data. |
| Instance 0 Address: | 0x400100A0 |
GPIO Output C Set (73-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| RSVD
0x0 |
WTSC
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED |
| 9:0 | WTSC | WO | Set the GPIO73-64 write data. |
| Instance 0 Address: | 0x400100A4 |
GPIO Output A Clear (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| WTCA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTCA | WO | Clear the GPIO31-0 write data. |
| Instance 0 Address: | 0x400100A8 |
GPIO Output B Clear (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| WTCB
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | WTCB | WO | Clear the GPIO63-32 write data. |
| Instance 0 Address: | 0x400100AC |
GPIO Output C Clear (73-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| RSVD
0x0 |
WTCB
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED |
| 9:0 | WTCB | WO | Clear the GPIO73-64 write data. |
| Instance 0 Address: | 0x400100B0 |
GPIO Enable A (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| ENA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENA | RW | GPIO31-0 output enables |
| Instance 0 Address: | 0x400100B4 |
GPIO Enable B (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| ENB
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENB | RW | GPIO63-32 output enables |
| Instance 0 Address: | 0x400100B8 |
GPIO Enable C (73-64)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| RSVD
0x0 |
ENC
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:10 | RSVD | RO | RESERVED |
| 9:0 | ENC | RW | GPIO73-64 output enables |
| Instance 0 Address: | 0x400100BC |
GPIO Enable A Set (31-0)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| ENSA
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENSA | RW | Set the GPIO31-0 output enables |
| Instance 0 Address: | 0x400100C0 |
GPIO Enable B Set (63-32)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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| ENSB
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ENSB | RW | Set the GPIO63-32 output enables |
| Instance 0 Address: | 0x400100C4 |
GPIO Enable C Set (73-64)