Electronics and electrical design checklist
Compiled and edited by Henrik Enggaard Hansen. Feedback and suggestions at Github.
- Process
- Is there a method of tracking versions/revisions?
- For system
- For schematics
- For PCBs
- For software
- Is source version control used? (Git, SVN etc.) #software
- Is offsite backup used?
- Are design decisions documented?
- Within or separate from the schematics/drawings/code?
- Is there a method of tracking versions/revisions?
- System
- What should have ESD protection? #ESD
- Are amplifier circuits stable?
- Are oscillators stable?
- Is there a simulation/simulator of the system or subsystems?
- Has the design or subsystems of it been simulated?
- What kind of interfaces and connections are necessary?
- For humans?
- For computers / control software?
- For power?
- For other subsystems?
- Are there status LEDs
- Power
- Programmable
- Subsystems
- Are multiple boards needed?
- How are subsystems connected?
- Is there a breakout board for subsystem connectors?
- Have harnesses/wiring/connectors been identified?
- Have pin-outs been defined and specified?
- What is the max current draw?
- Should any subsystems be default off? #power
- Communication
- Which busses/protocols will be used?
- Between subsystems?
- Between chips/modules?
- Has addresses been allocated?
- Which busses/protocols will be used?
- Watchdog and reset
- Can the watchdog be bypassed? #testing
- Can it be overruled? #testing
- Can it be emulated? #testing
- What interval is necessary? #safety
- Is the worst case behavior documented?
- Should reset be pulled to default on or off?
- System characteristics
- Is there a power budget?
- Estimated power dissipation of each subsystem?
- Estimated current draw of each subsystem?
- Estimated expected operating temperature?
- Power
- How is power provided?
- Is power-up well-defined?
Some subsystems might need to be unpowered before other subsystems are powered, e.g. LED drivers unpowered until the software has booted.
Certain components such as complex microprocessors, FPGAs and other complex ICs need special power sequencing to operate correctly; consult datasheets for details.- Is power-down well-defined?
- Should any subsystems be isolated?
- Which voltage levels are needed?
- Which current draws are needed?
- Is there a shared power supply?
- Can it deliver sufficient power for all connected subsystems?
- Is the ground connection made first in hot-plugging connectors?
- Is a separate earth necessary?
- Testing
- Test points on PCB for critical circuits?
- Test pads for flying probe/bed-of-nails/pogos setups?
- Has a test procedure been written?
- Are special connectors needed for testing?
- Are special peripheral circuitry needed for testing?
- Breakout boards for connectors?
- Is special equipment needed for testing?
- Should there be in-circuit testing?
- Voltage monitoring?
- Current monitoring?
- Temperature monitoring?
- Peripheral device behavior
- Is there event/data logging?
- Voltage monitoring?
- Current monitoring?
- Temperature monitoring?
- Connections/disconnects?
- Peripheral device states?
- Battery health?
- Maintainability
- Is disassembly easy?
- Is reassembly easy?
- Safety
- Fuses
- Appropriately sized?
- Fast enough for the load?
- Replaceable when board is assembled
- Replaceable when devices is assembled
- Storage for spare fuse?
- Can connections be mated in an unsafe way?
- Do connectors for different purposes share the same type of plug/socket?
- Is signal and power avoided in same connector?
Wide Band Laboratory Fire, Fermi National Accelerator Laboratory, 1987.
A misjoined connector resulted in several amps being drawn through cables rated for only 1 A. A fire started from this. Source: Wide Band Laboratory Fire
- Failure mode analysis
- Loss of ground pins on connector
- Effect of lost connection
- Between subsystems
- To computer
- System behavior when battery is fully discharged?
- Effects of voltage transients and high voltages on FETs
- Expected failure modes of failed semiconductors
- Expected effects of failed semiconductors
- Are component ratings derated by expected operating temperature/voltage/current?
- Environmental tolerance
- Vibration
- Heating
- Radiation
- Humidity
- Magnetism
- Components
- Are the necessary components in stock?
- With a margin for defects/failures/loss?
- With a margin for spill from PnP machine?
- Are voltage ratings of components sufficient? #schematic #electrical
- Are any components expected for obsoletion?
- Are there multiple sources?
- Are there alternate manufacturers?
- Are suitable alternatives identified?
- Have errata sheets been checked? #schematic #components
- Is reset active-high or active-low?
- Do any pins need biasing / pull-up / pull-down / strap?
- During initialization?
- For addresses?
- Floorplan
- Are mechanical constraints defined?
- Mounting
- Board size/shape
- Connector placement
- Human interface placement
- Can components be oriented in roughly the same way / consistency in layout?
- Are unreliable components easily accessible?
- Are interactive components placed in a logical manner? (Consistent orientation of buttons? Consistent rotation of potentiometers?)
- Are temperature sensitive components placed away from hot components?
- Should there be a ground ring?
Ground rings serve both a signal integrity and a practical purpose. For EMC it is necessary to avoid traces along edges of the PCB. Adding a ground ring is an easy way of ensuring this constraint is held. It also provides somewhat better EMI prevention. Source: Why are vias placed this way on a PCB? - Stack Exchange
- Schematic
- CAD
- Has DRC been set up and configured #CAD
- Has a grid size been picked
- Symbols
- Are explicit and informative
- Do they resemble electrical circuit symbols?
- Mark internal pull-up/-down
- Mark internal termination
- Reflect the functionality or logical structure of the component In contrast to placing pins as the physically appear on the device. Schematics should reflect functionality; board layout should reflect physical reality. Physical pin layout has its merit in making debugging easier -- however, so does having a clearer schematic.
- Pins are assigned the correct type (passive, power, in, out etc.)
- Are active-high and active-low marked consistently?
- Are power (and ground) pins consistently placed and marked?
- Do pin positions adhere to the selected grid size If the the pins are off grid, connections might not be made. Reference: EEVblog #1129 - Creating a Nice Readable Schematic (15:06)
- Functionality
- Are all pins on all ICs handled?
- Unused OPAMPS: output to negative input and positive input to ground.
- Unused comparators: All pins to common.
- Beak-out of extra pins from ICs or subsystems?
- Are mating connectors on different boards matched in pin-out?
- Have necessary inputs been ESD protected? #ESD
A typical solution would be current limiting resistors, clamping diodes.
- Multipart components are identified and utilized
- Are all pins on all ICs handled?
- Electrical
- Are reset pins pulled to high/low?
- Is reset filtered?
- Are polarized components protected/ensured against from reverse voltage?
- Pull-up on all open-collector?
- Are resistors operating within their specified voltage range?
- Is a low-impedance source driving tantalum capacitors?
It can result in premature failure. Switch-on current should also be limited. References:
- Is there sufficient bulk capacitance?
- Testing
- Are there ground connection points? (for probes etc.)
- Have necessary test points been added?
- Have configurable strap-in pins been biased?
- Have configurable strap-in pins been connected with jumpers or similar?
- Busses
- I2C
- Pull-up on SDA an SCL
I2C is open-drain and thus needs pull-up. References: Texas Instruments, Application Report, I2C Bus Pullup Resistor Calculation
- Pull-up on SDA an SCL
- JTAG
- Have datasheets been consulted for necessary pull-up/-down?
Typically TMS and TDI are pull-up and TCK is pull-down, but it changes between manufacturers and devices. Some devices have internal pull-up/-down, yet external resistors are recommended to keep start-up well-defined.
- Have datasheets been consulted for necessary pull-up/-down?
- SWD
- Have datasheets been consulted for necessary pull-up/-down?
Typically TMS and TDI are pull-up and TCK is pull-down, but it changes between manufacturers and devices. Some devices have internal pull-up/-down, yet external resistors are recommended to keep start-up well-defined.
- Have datasheets been consulted for necessary pull-up/-down?
- I2C
- Signal integrity
- Is there sufficient decoupling?
- Is there filtering between analog and digital commons?
- Are optocouplers filtered?
- Impedance on inputs from outside of board?
- Documentation and notes
- Unpopulated parts are clearly marked
- Are destinations noted if they go to other sheets
- Are connections marked with expected current draw?
- Has special PCB or layout requirements been noted? #schematic #pcb
- Impedance?
- Ground planes?
- Routing?
- Keep-out?
- References to datasheet's recommendations
- Notes explaining purpose, functionality, origin, references and caculations for circuits
- Drafting
- No overlap between text, notes references, wires, symbols etc.
- Is all text horizontal? Within reason and if there is space for it.
- Do all components have reference and value?
- Are values in a uniform format
- Are references using standard designators?
- Are references placed unambiguously?
- Decimal points avoided? Decimal points might get lots during photocopying. Reference: EEVblog #1129 - Creating a Nice Readable Schematic (44:00)
- Are all junctions dotted?
- Are no-connects marked?
- No 4-way connections 4-way junctions might get lots during photocopying. They can also be ambiguous. Reference: EEVblog #1129 - Creating a Nice Readable Schematic (1:9:40)
- No upwards pointing ground symbols?
- Are component references ordered by schematic layout?
- Are the appropriate power nets connected? (Vcc, Vss, Vdd)
- Net names on top of lines
- Are unused nets left unlabeled? If a net is labeled, it is expected to be used. It is usually clearer to leave it unlabeled. Reference: EEVblog #1129 - Creating a Nice Readable Schematic (21:20)
- All connections/markings have a purpose Connections going from and to nowhere lead to confusion.
- Sheets
- Sheets are consistently sized
- Readable when printed
- Logical layout should go left-right, top-bottom. It is a convention for input signals to "enter" on the left and progress towards right. Reference: EEVblog #1129 - Creating a Nice Readable Schematic (6:00)
- Header/block
- Name of author
- Name of reviewer
- List of revisions and changes
- Date
- Revision
- Company / organization
- Sheet/drawing number
- Final
- Has DRC passed?
- Printed circuit board
- Manufacturing
- Are gold fingers needed?
- How is the PCB panelized?
- Do layers align on panelized files?
- What stack-up is needed?
- Which finish is necessary?
- What thickness of finish?
- Is there a bill of materials?
- Ability for blind or buried vias?
- Are solder paste openings the proper size?
- Are manufacturing tolerances honored?
- Solder mask
- Silk screen
- Traces
- Holes
- Are all manufacturing requirements noted on the layout file?
- Finish, holes, thickness, solder mask
- Panelization
- Panelized PCB fits test rig
- Assembly
- Is there enough space for the minimum bending radius of the wire harnessing?
- Are fiducials needed for assembly?
- Is there a recommended/necessary order for mounting components on the board?
- Will mounting certain components make it impossible to mount others?
- Is there an assembly order for subsystems?
- Is there a testing order for subsystems?
- Footprints
- Is pin 1 marked in a consistent manner?
- Is component polarity marked in a consistent manner?
- For electrically polarized components like capacitors?
- For keyed components like connectors?
- Are high-density chips marked with pin numbers?
- Are there tick-marks for every 5/10 pin on high pin count?
- Are there square pins on components? Are the holes big enough?
- Have the footprint dimensions been cross-checked with recommended footprint for the specific component?
- Are the footprints from the datasheet defined as top view or bottom view?
- Are edge-connectors/fingers interleaved/zig-zag? Edge pins on SODIMM are interleaved in placement when comparing the two sides of the inserted board. References:
- Are there the necessary thermal pads?
- Are they exposed?
- Are they connected to the right net?
- Placement
- Are jumpers accessible?
- Are debug connectors accessible?
- Filter resistors closer to the source?
- Termination resistors closer to the target?
- Clearance
- Around mounting holes?
- For IC extraction tools?
- Are all keep-out areas honored?
- For programming tools
- For assembly tools (wrenches, screwdrivers etc.)
- For probes?
- Trace-to-trace clearance based upon voltage rating?
- Test points on PCB for hard-to-reach nets?
- Mechanical
- Is there spacing for an assembly run marking?
- Is there clearance for connectors?
- Are there mounting holes?
- Should mounting holes be electrically isolated?
- Should grounded mounting holes have via stitching?
Vias around mounting holes improve ground connection and provides some redundancy. Source: Why are vias placed this way on a PCB? - Stack Exchange
- Are hole diameters compensating for plating?
- Is the outline of the board defined?
- Is the mechanical enclosure defined?
- Is there enough space for the mating connectors? #clearance #connectors
- Is there enough vertical space for components?
- Is there a drill legend?
- Are internal corners rounded? Can they be milled?
- Electrical
- What stack-up is needed?
- Polarized components are oriented correctly
- All traces are routed?
- Are decoupling capacitors placed close to power pins of ICs?
- Are analog and digital commons joined at only one point?
- Does ERC pass?
- Are isolation barriers large enough? #mechanical #power #safety
- Are the appropriate power nets connected? (Vcc, Vss, Vdd)
- Signal integrity
- Are digital signals routed over separate (digital) ground planes?
- Do high-speed signals avoid gaps in ground planes?
- Are stubs minimized for high-speed signals?
- Are differential pair spacing based upon impedance matching?
- Are transmission lines terminated with an appropriate impedance?
- Are crystal connections short?
- Is there a guard ring around the crystal?
- Are there filters on A/D pins?
- Drivers / receivers placed close to connectors?
- EMI / RFI close to entry / exit of shielded areas?
- Are traces avoided under sensitive components?
- Are traces avoided under noisy components?
- Are vias avoided under metal-film resistors?
- Is via fencing of sensitive RF transission lines done with the proper via spacing? (< 1/20 lambda)
- Copper pour
- GND / power pins are connected and checked?
- No pour between adjacent pins on ICs?
These can be mistaken for shorts during inspection. A keep-out zone between pins can fix this without adjusting the pour clearances.
- Has all layers been checked?
- Are there thermal reliefs at appropriate places?
- Do they introduce ground loops?
- Traces
- Are trace-pad connections sufficiently obtuse (angle 90 deg or more)?
- Are the trace widths sufficient for the current draw and max heating?
- No connections between adjacent pins on ICs?
These can be mistaken for shorts during inspection.
- Are vias for internal power traces big enough?
- Is there enough space for heatsinks? #mechanical #thermal
- Has mitered bends or soft curves (r > 3 trace width) been implemented for impedance sensitive traces?
- Thermal
- Are temperature sensitive components placed away from hot components?
- Are there thermal vias in thermal pads?
- Testing
- Are there ground connection points close to analog test points?
- Silk screen
- Notes and documentation
- Is there a revision number?
- Is there a date?
- Is there blank space for a serial/assembly number?
- Are connector pin-outs labeled?
- Fuse size and type marked on PCB
- Are functional groups marked?
- Are high-density chips marked with pin numbers?
- Is functionality labeled?
- Test points
- LEDs
- Buttons
- Connectors/terminals
- Mounting holes
- Jumpers
- Drafting
- No silk screen on pads
- All text is readable from at most two directions
- Will the silk screen be legible?
- Are component references order by PCB layout?
- Is there a coordinate system?
- Final
- Does ERC pass?
- Are there any superfluous vias?
- Does LVS pass?
Layout Versus Schematic is a check to confirm that the board layout actually implements the schematic. That is: Are the traces actually connecting the proper components? Resources: Wikipedia.
- Header/block
- Name of author
- Name of reviewer
- List of revisions and changes
- Date
- Revision
- Company / organization
- Sheet/drawing number
- Board inspection
- Solder mask alignment
- Solder mask curing
- Wired harnessing
- Wire gauge compatible with termination
- Cable ties and lacing cord is noted
- Length and color is noted
- Avoid signal and power in same connector
- Avoid current flow to remote sources through earth
- Is there a breakout board for the connector?
- Wire termination is noted
- Heat shrink tubing
- Solder
- Crimp force
- Software
- Is automated software testing used? #software #procedure
- Is there a style guide?
- Are loops checked for termination conditions?
- Is power up and power down handled correctly?
- Are unused interrupts handled? (Either restart or damage control)
- Is there a difference between warm and cold reset?
- How does the devices behave if only the software is reset?
- Memories
- Are setup, hold and access times correct for external memories?
- Is memory integrity checked?
- Is memory integrity guaranteed?
- Is unused program memory/ROM spaces filled with traps or restart instructions?
- Bounds checks
- Is user/sensor input bounds checked?
- Are outputs bounds checked?
- Are calculations bounds checked?
- Are buffer overflows handled?
- Data structures and formats
- Do they include a version number or identifier?
- Are the bounds of variable size formats well-defined?
- Software characteristics
- CPU utilization
- Memory utilization
- Interrupt response time
- Interrupt execution time
- Documentation
- Usage instructions
- Assembly instructions
- Troubleshooting instructions
- Component list
- Schematic diagrams
- PCB explanation
- Design decisions
Neat resources
- PCB Layout & RoutingExcellent design flow for approaching a board layout.
- EEVblog #1129 - Creating a Nice Readable Schematic
Other checklists


#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\fpga_J-2015.03M-SP1-2 #OS: Windows 8 6.2 #Hostname: LAPTOP-UCQD4H1A #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @N:CD720 : std.vhd(146) | Setting time resolution to ns @N: : System_clock.vhd(48) | Top entity is set to system_clock. File Dependency file is up to date. It will not be rewritten. VHDL syntax check successful! Compiler output is up to date. No re-compile necessary @N:CD231 : std1164.vhd(890) | Using onehot encoding for type mvl9plus ('U'="1000000000") @N:CD630 : System_clock.vhd(48) | Synthesizing work.system_clock.behaviour Post processing for work.system_clock.behaviour At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 13 13:02:25 2017 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 13 13:02:25 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 13 13:02:25 2017 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File C:\Users\rozen\Dropbox\EE_BSC_2017\G8\vhdl\CU_Droptest\synthesis\synwork\system_clock_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 13 13:02:27 2017 ###########################################################] Pre-mapping Report Synopsys Microsemi Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:42:41 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Reading constraint file: C:\Users\rozen\Dropbox\EE_BSC_2017\G8\vhdl\CU_Droptest\constraint\CU_Main_32.sdc Linked File: system_clock_scck.rpt Printing clock summary report in "C:\Users\rozen\Dropbox\EE_BSC_2017\G8\vhdl\CU_Droptest\synthesis\system_clock_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ---------------------------------------------------------------------------------- main_clk 32.8 MHz 30.500 declared default_clkgroup system_clock|mclk 100.0 MHz 10.000 inferred Inferred_clkgroup_0 ================================================================================== @W:MT530 : system_clock.vhd(91) | Found inferred clock system_clock|mclk which controls 26 sequential elements including s_time[7:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Users\rozen\Dropbox\EE_BSC_2017\G8\vhdl\CU_Droptest\synthesis\system_clock.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 109MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 13 13:02:27 2017 ###########################################################] Map & Optimize Report Synopsys Microsemi Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:42:41 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 110MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 110MB) @N: : system_clock.vhd(68) | Found counter in view:work.system_clock(behaviour) inst l_time[17:1] @N:MF238 : system_clock.vhd(98) | Found 8-bit incrementor, 'un1_s_time[7:0]' Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 110MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 110MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 110MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 110MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 110MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ------------------------------------------------------------- reset_pad / Y 26 : 26 asynchronous set/reset ============================================================= @N:FP130 : | Promoting Net mclk_c_c on CLKBUF mclk_pad Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Buffering reset_c, fanout 26 segments 2 Added 1 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 26 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 mclk port 26 l_time[13] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Writing Analyst data base C:\Users\rozen\Dropbox\EE_BSC_2017\G8\vhdl\CU_Droptest\synthesis\synwork\system_clock_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Writing EDIF Netlist and constraint files J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) @W:MT420 : | Found inferred clock system_clock|mclk with period 10.00ns. Please declare a user-defined clock on object "p:mclk" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Thu Apr 13 13:02:28 2017 # Top view: system_clock Library name: PA3 Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: proasic3 Paths requested: 5 Constraint File(s): C:\Users\rozen\Dropbox\EE_BSC_2017\G8\vhdl\CU_Droptest\constraint\CU_Main_32.sdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -1.248 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------- system_clock|mclk 100.0 MHz 80.0 MHz 10.000 12.496 -1.248 inferred Inferred_clkgroup_0 ========================================================================================================================= @W:MT548 : cu_main_32.sdc(1) | Source for clock main_clk not found in netlist. Run the constraint checker to verify if constraints are applied correctly. Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------- system_clock|mclk system_clock|mclk | No paths - | 10.000 0.770 | 5.000 2.016 | 5.000 -1.248 ============================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: system_clock|mclk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------- l_time[16] system_clock|mclk DFN0E0C1 Q m_time_c[16] 0.653 -1.248 l_time[15] system_clock|mclk DFN0E0C1 Q m_time_c[15] 0.653 -1.135 l_time[5] system_clock|mclk DFN0C1 Q m_time_c[5] 0.653 -0.784 l_time[9] system_clock|mclk DFN0E0C1 Q m_time_c[9] 0.653 -0.657 l_time[6] system_clock|mclk DFN0C1 Q m_time_c[6] 0.653 -0.639 l_time[3] system_clock|mclk DFN0C1 Q m_time_c[3] 0.653 -0.615 l_time[4] system_clock|mclk DFN0C1 Q m_time_c[4] 0.653 -0.584 l_time[14] system_clock|mclk DFN0C1 Q m_time_c[14] 0.653 -0.346 l_time[11] system_clock|mclk DFN0C1 Q m_time_c[11] 0.653 -0.294 l_time[1] system_clock|mclk DFN0C1 Q m_time_c[1] 0.653 -0.233 ============================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------- flag system_clock|mclk DFN1C1 D flag_RNO 4.426 -1.248 l_time[17] system_clock|mclk DFN0E0C1 E l_time_RNO_0[17] 9.392 0.770 l_time[14] system_clock|mclk DFN0C1 D l_time_n13 9.287 1.298 l_time[16] system_clock|mclk DFN0E0C1 E l_time_RNI0GVI3[15] 9.392 1.738 l_time[15] system_clock|mclk DFN0E0C1 E l_time_RNO_0[15] 9.392 1.851 s_time[0] system_clock|mclk DFN0E1C1 E flag 4.392 2.016 s_time[1] system_clock|mclk DFN0E1C1 E flag 4.392 2.016 s_time[2] system_clock|mclk DFN0E1C1 E flag 4.392 2.016 s_time[3] system_clock|mclk DFN0E1C1 E flag 4.392 2.016 s_time[4] system_clock|mclk DFN0E1C1 E flag 4.392 2.016 ===================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.574 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.426 - Propagation time: 5.674 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.248 Number of logic level(s): 4 Starting point: l_time[16] / Q Ending point: flag / D The start point is clocked by system_clock|mclk [falling] on pin CLK The end point is clocked by system_clock|mclk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- l_time[16] DFN0E0C1 Q Out 0.653 0.653 - m_time_c[16] Net - - 1.184 - 4 flag_RNO_3 NOR2B B In - 1.837 - flag_RNO_3 NOR2B Y Out 0.627 2.464 - un15_l_time_0_a2_m1_0_a2_m1_e_1 Net - - 0.322 - 1 flag_RNO_1 NOR3C C In - 2.786 - flag_RNO_1 NOR3C Y Out 0.641 3.427 - un15_l_time_0_a2_m1_0_a2_m1_e_3 Net - - 0.322 - 1 flag_RNO_0 NOR3B A In - 3.749 - flag_RNO_0 NOR3B Y Out 0.641 4.390 - un15_l_time_0_a2_m1_0_a2_m1_e_5 Net - - 0.322 - 1 flag_RNO NOR3C C In - 4.712 - flag_RNO NOR3C Y Out 0.641 5.353 - flag_RNO Net - - 0.322 - 1 flag DFN1C1 D In - 5.674 - ================================================================================================== Total path delay (propagation time + setup) of 6.248 is 3.778(60.5%) logic and 2.470(39.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 5.000 - Setup time: 0.574 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.426 - Propagation time: 5.561 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.135 Number of logic level(s): 4 Starting point: l_time[15] / Q Ending point: flag / D The start point is clocked by system_clock|mclk [falling] on pin CLK The end point is clocked by system_clock|mclk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- l_time[15] DFN0E0C1 Q Out 0.653 0.653 - m_time_c[15] Net - - 1.184 - 4 flag_RNO_3 NOR2B A In - 1.837 - flag_RNO_3 NOR2B Y Out 0.514 2.351 - un15_l_time_0_a2_m1_0_a2_m1_e_1 Net - - 0.322 - 1 flag_RNO_1 NOR3C C In - 2.673 - flag_RNO_1 NOR3C Y Out 0.641 3.314 - un15_l_time_0_a2_m1_0_a2_m1_e_3 Net - - 0.322 - 1 flag_RNO_0 NOR3B A In - 3.636 - flag_RNO_0 NOR3B Y Out 0.641 4.277 - un15_l_time_0_a2_m1_0_a2_m1_e_5 Net - - 0.322 - 1 flag_RNO NOR3C C In - 4.598 - flag_RNO NOR3C Y Out 0.641 5.240 - flag_RNO Net - - 0.322 - 1 flag DFN1C1 D In - 5.561 - ================================================================================================== Total path delay (propagation time + setup) of 6.135 is 3.665(59.7%) logic and 2.470(40.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 5.000 - Setup time: 0.574 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.426 - Propagation time: 5.210 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.784 Number of logic level(s): 3 Starting point: l_time[5] / Q Ending point: flag / D The start point is clocked by system_clock|mclk [falling] on pin CLK The end point is clocked by system_clock|mclk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- l_time[5] DFN0C1 Q Out 0.653 0.653 - m_time_c[5] Net - - 1.639 - 8 l_time_RNIH0EL[13] NOR3C C In - 2.292 - l_time_RNIH0EL[13] NOR3C Y Out 0.641 2.934 - l_time_n13_0_o2_m6_0_a2_7_4 Net - - 0.322 - 1 l_time_RNI4KA61[7] NOR3C C In - 3.255 - l_time_RNI4KA61[7] NOR3C Y Out 0.641 3.896 - l_time_n13_0_o2_m6_0_a2_7_6 Net - - 0.386 - 2 flag_RNO NOR3C B In - 4.282 - flag_RNO NOR3C Y Out 0.607 4.889 - flag_RNO Net - - 0.322 - 1 flag DFN1C1 D In - 5.210 - ============================================================================================ Total path delay (propagation time + setup) of 5.784 is 3.116(53.9%) logic and 2.668(46.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.000 - Setup time: 0.574 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.426 - Propagation time: 5.083 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.657 Number of logic level(s): 3 Starting point: l_time[9] / Q Ending point: flag / D The start point is clocked by system_clock|mclk [falling] on pin CLK The end point is clocked by system_clock|mclk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------- l_time[9] DFN0E0C1 Q Out 0.653 0.653 - m_time_c[9] Net - - 1.184 - 4 l_time_RNIJJSG[9] NOR2B B In - 1.837 - l_time_RNIJJSG[9] NOR2B Y Out 0.627 2.464 - l_time_n9_0_m2_0_a2_0 Net - - 0.806 - 3 l_time_RNIRAST[12] NOR3C C In - 3.271 - l_time_RNIRAST[12] NOR3C Y Out 0.641 3.912 - l_time_n13_0_o2_m6_0_a2_7_5 Net - - 0.386 - 2 flag_RNO NOR3C A In - 4.298 - flag_RNO NOR3C Y Out 0.464 4.762 - flag_RNO Net - - 0.322 - 1 flag DFN1C1 D In - 5.083 - ============================================================================================== Total path delay (propagation time + setup) of 5.657 is 2.960(52.3%) logic and 2.697(47.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.000 - Setup time: 0.574 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.426 - Propagation time: 5.066 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.639 Number of logic level(s): 3 Starting point: l_time[6] / Q Ending point: flag / D The start point is clocked by system_clock|mclk [falling] on pin CLK The end point is clocked by system_clock|mclk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- l_time[6] DFN0C1 Q Out 0.653 0.653 - m_time_c[6] Net - - 1.279 - 5 l_time_RNIJJSG[9] NOR2B A In - 1.933 - l_time_RNIJJSG[9] NOR2B Y Out 0.514 2.447 - l_time_n9_0_m2_0_a2_0 Net - - 0.806 - 3 l_time_RNIRAST[12] NOR3C C In - 3.253 - l_time_RNIRAST[12] NOR3C Y Out 0.641 3.895 - l_time_n13_0_o2_m6_0_a2_7_5 Net - - 0.386 - 2 flag_RNO NOR3C A In - 4.281 - flag_RNO NOR3C Y Out 0.464 4.745 - flag_RNO Net - - 0.322 - 1 flag DFN1C1 D In - 5.066 - ============================================================================================ Total path delay (propagation time + setup) of 5.640 is 2.847(50.5%) logic and 2.793(49.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Finished timing report (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) -------------------------------------------------------------------------------- Target Part: A3P250_VQFP100_STD Report for cell system_clock.behaviour Core Cell usage: cell count area count*area AND2 1 1.0 1.0 AND3 6 1.0 6.0 AOI1B 7 1.0 7.0 AX1 4 1.0 4.0 AX1C 1 1.0 1.0 BUFF 1 1.0 1.0 GND 1 0.0 0.0 INV 8 1.0 8.0 NOR2B 13 1.0 13.0 NOR3A 1 1.0 1.0 NOR3B 3 1.0 3.0 NOR3C 11 1.0 11.0 OR2 1 1.0 1.0 OR2A 3 1.0 3.0 OR2B 5 1.0 5.0 OR3C 1 1.0 1.0 VCC 1 0.0 0.0 XNOR2 2 1.0 2.0 XOR2 10 1.0 10.0 DFN0C1 11 1.0 11.0 DFN0E0C1 6 1.0 6.0 DFN0E1C1 8 1.0 8.0 DFN1C1 1 1.0 1.0 ----- ---------- TOTAL 106 104.0 IO Cell usage: cell count CLKBUF 1 INBUF 1 OUTBUF 26 ----- TOTAL 28 Core Cells : 104 of 6144 (2%) IO Cells : 28 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 46MB peak: 110MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 13 13:02:28 2017 ###########################################################]


“ Users expect real time data.They want their tweets now. Their order confirmed now. They need prices accurate as of now. Their online games need to be responsive.
As a developer, you demand fire-and-forget messaging. You don't want to be blocked waiting for a result.
You want to have the result pushed to you when it is ready. Even better, when working with result sets, you want to receive individual results as they are ready. You do not want to wait for the entire set to be processed before you see the first row.
The world has moved to push; users are waiting for us to catch up. Developers have tools to push data, this is easy. Developers need tools to react to push data.”
which takes us to assinchronous code
which takes us to callbacks??!
getData(function(a){
getMoreData(a, function(b){
getMoreData(b, function(c){
getMoreData(c, function(d){
getMoreData(d, function(e){
...
});
});
});
});
});
var fs = require('fs');
var myFile = '/tmp/test';
fs.readFile(myFile, 'utf8', function(err, txt) {
if (err) return console.log(err);
txt = txt + '\nAppended something!';
fs.writeFile(myFile, txt, function(err) {
if(err) return console.log(err);
console.log('Appended text!');
});
});
var Promise = require('bluebird');
var fs = require('fs');
Promise.promisifyAll(fs);
var myFile = '/tmp/test';
fs.readFileAsync(myFile, 'utf8').then(function(txt) {
txt = txt + '\nAppended something!';
fs.writeFile(myFile, txt);
}).then(function() {
console.log('Appended text!');
}).catch(function(err) {
console.log(err);
});
let p = new Promise((resolve, reject) => {
doAsyncThing((err, value) => {
if (err) {
reject(err);
} else {
resolve(value);
}
});
});
let o = new Observable(observer => {
doAsyncThing((err, value) => {
if (err) {
observer.error(err);
} else {
observer.next(value);
observer.complete();
}
});
});
let o = new Observable(observer => {
const token = doAsyncThing((err, value) => {
if (err) {
observer.error(err);
} else {
observer.next(value);
observer.complete();
}
});
return () => {
cancelAsyncThing(token);//tear down
};
});
var total = 0;
document.getElementById("btn1").addEventListener("click", function(){
total = total + 1;
document.getElementById("result").innerHTML = total;
});
document.getElementById("btn2").addEventListener("click", function(){
total = total - 1;
document.getElementById("result").innerHTML = total;
});
let events = [+1,+1,-1,+1]
var total = events.reduce(function(total, value) {
return total + value;
}, 0);
$('#result').text(total)
import { fromEvent } from 'rxjs';
import { map } from 'rxjs/operators';
//create observable that emits click events
const source = fromEvent(document.getElementById("btn1"), 'click');
//map to string with given event timestamp
const example = source.pipe(map(event => `Event time: ${event.timeStamp}`));
//output (example): 'Event time: 7276.390000000001'
const subscribe = example.subscribe(val => console.log(val));
let mouseup$ = Rx.Observable.fromEvent(element, 'mouseup')
let mousemove$ = Rx.Observable.fromEvent(element, 'mousemove')
let mousedown$ = Rx.Observable.fromEvent(element, 'mousedown').map(event => getOffset(event))
let mousedrag$ = mousedown$.mergeMap((offsetData) =>
mousemove$.map((position) => (calculateNewPositionWithOffset(offsetData,position)))
.takeUntil(mouseup$)
)
mousedrag$.subscribe((resultPosition) => updatePosition(resultPosition));
const genericRetryStrategy = (maxRetryAttempts, scalingDuration, excludedStatusCodes) => (attempts) => {
return attempts.pipe(
mergeMap((error, i) => {
const retryAttempt = i + 1;
// if maximum number of retries have been met or response is a status code we don't wish to retry, throw error
if (retryAttempt > maxRetryAttempts || excludedStatusCodes.find(e => e === error.status)) {
return _throw(error);
}// retry after 1s, 2s, etc...
console.log(`Attempt ${retryAttempt}: retrying in ${retryAttempt * scalingDuration}ms` );
return timer(retryAttempt * scalingDuration);
}),
finalize(() => console.log('We are done!'))
);
};
fromEvent(document.getElementById("example11_input1"), "keyup").pipe(
map(evt => evt.target.value),
debounceTime(400),
tap(value => delayDrawStream1.next(value)),
switchMap(val => remoteCall(val).pipe(
retryWhen(genericRetryStrategy({
scalingDuration: 2000,
excludedStatusCodes: [500]
})),
)),
tap(value => delayDrawStream2.next(value))
).subscribe(value => this.updateResult(value));
“Reactive programming with RxJava has enabled Netflix developers to leverage server-side concurrency without the typical thread-safety and synchronization concerns. The API service layer implementation has control over concurrency primitives, which enables us to pursue system performance improvements without fear of breaking client code.
RxJava is effective on the server for us and it spreads deeper into our code the more we use it.”
const people = [{name: 'Sue', age:25},{name: 'Joe', age: 30},{name: 'Frank', age: 25}, {name: 'Sarah', age: 35}];
//emit each person
const source = Rx.Observable.from(people);
//group by age
const example = source
.groupBy(person => person.age)
//return as array of each group
.flatMap(group => group.reduce((acc, curr) => [...acc, curr], []))
/*
output:
[{age: 25, name: "Sue"},{age: 25, name: "Frank"}]
[{age: 30, name: "Joe"}]
[{age: 35, name: "Sarah"}]
*/
const subscribe = example.subscribe(val => console.log(val));
Partitions of Data
You may partition data from a single source so that it can easily be filtered and shared to many sources. Partitioning data may also be useful for aggregates as we have seen. This is commonly done with the GroupBy operator.
Online Game servers
Consider a sequence of servers. New values represent a server coming online. The value itself is a sequence of latency values allowing the consumer to see real time information of quantity and quality of servers available.
If a server went down then the inner sequence can signify that by completing.
Financial data streams
New markets or instruments may open and close during the day. These would then stream price information and could complete when the market closes.
Chat Room
Users can join a chat (outer sequence), leave messages (inner sequence) and leave a chat (completing the inner sequence).
File watcher
As files are added to a directory they could be watched for modifications (outer sequence). The inner sequence could represent changes to the file, and completing an inner sequence could represent deleting the file.
const msElapsed = (scheduler = animationFrameScheduler) => defer(() => {
const start = scheduler.now();
return interval(0, scheduler).pipe(map(() => scheduler.now() - start));
});
const velocity = (pixelsPerSeg, scheduler = animationFrameScheduler) => msElapsed(scheduler).pipe(
map(elapsed => parseInt(elapsed * (pixelsPerSeg / 1000))));
subject = new Subject().pipe(mergeMap(marble => {
return velocity(this.props.velocity).pipe(distinct(),
takeWhile(
distance => distance < this.props.distance - this.props.offset
),
tap({
next: distance => this.updateDistance(distance, marble),
complete: () => this.removeMarble(marble)
}));})).subscribe();
| Lossless (but memory intensive) | Lossy |
|---|---|
| buffer | throttle |
| window | debounce |
| pausable | sample |
| ... | ... |


[1]
Has speaker; Safari won't play embedded flash files.
[2]
Wi-Fi, Internet And E-Mail!; Battery Life Sucks A Bit!


The busy shipping season is here; How to ensure your gifts arrive on time
by Breaking News Staff— As the holiday season is upon us, mail carriers and delivery drivers are working longer and longer hours, and lines at the post office are getting longer and longer.
This morning, News Center 7’s Gabrielle Enright is in Xenia to discuss how you can ensure your gifts arrive on time.
To find out more, you can watch our broadcast live, click here.


The project aims to create effective awareness in various levels to reduce the adverse impact on environment and health arising out of the polluting technologies used in recycling e-waste in the unorganized sector.
The charter for this project is to bring together the triad of public, government and industry to adopt responsible
measures for Sustainable electronics that is responsive to environmental needs.
This needs proactive policy formation
and mass deployment that would be the focus area.
An individual should be very specific in
his choices when buying any electric or electronic equipment. Thus a person should reduce his wants. Next, if a technology gets old or
outdated, still it could be useful for some with limited utility.
Such equipments with obsolete technology should be
donated to other people who could make use of it effectively in their work. This is the concept of reuse.
Last but not
the least, if equipment has to be discarded due to non-functioning, it should be handed over only to authorized
recycling vendors for recycling, in order to avoid improper dumping.


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UTUI stands for "unit test user interface".
As of now, it is a simple interace to get PHPUnit outputs in the browser.
Currently, this interface was designed to works with composer
PHP projects.
This means,
composer.json
file.vendor/autoload.php
must be properly configured.phpunit
testing framework.
However, if you have your own autoload.php
file located in /vendor
from your project's root folder
or, you have a bootstrap
file located in your test folder and provided that you're also using phpunit
,
the interface should still work as it should.
Once you have unzipped the folder, open a terminal, cd
into the folder and run the following command:
composer install
When using the phpunit-server
,
PHP-CLI
is required. Make sure it is installed properly by doing php -v
from the command line. the PHP
version should get printed. If not, download and install it.
Permission is the only issue I ran into when developing this interface.
Make sure that PHP
has enough permission to create folders and files.
The app will create ONLY one folder called tmp
in phpunit-ui
root folder and two files:
bootstrap.php
and filesList.xml
.
If PHP cannot create that folder and these files, the interface will NOT work.
I personally solved this problem by changing the group settings (ownership) of phpunit-ui
project folder and all files within.
Since I am on Linux, assuming that phpunit-ui-master
is the unzipped folder name, I used the following command:
chown -R :www-data phpunit-ui-master
When I changed the group to www-data
the problem was gone.
Naturally, PHP should be in the www-data group.
If you still get permission issues, try deleting the tmp
folder.
On linux, after downloading phpunit-ui
from GitHub, the permissions might be all messed up.
If that is the case, once you have unzipped the phpunit-ui
folder, open a terminal and run the
following command on the newly unzipped folder:
sudo chown -R :www-data phpunit-ui-master
and then chmod -R a+rX phpunit-ui-master
and finally, chmod -R g+w phpunit-ui-master
This should give PHP enough permission to create folders.
phpunit.phar
If you are using the phpunit-server
with this interface,
you first need to download the PHAR
version of phpunit
.
Once that is done, rename the downloaded file to phpunit
, with no extension.
Then copy-paste it in the root folder of phpunit-ui
, next to the index.php
file.
phpunit.phar
It is the same procedure if you want to update phpunit.phar
.
Just overwrite the existing one with the newer version.
Note:
This interface was implemented using phpunit.phar version 7.3.x
.
Click on the icon on the navigation bar to bring up the unit-test interface. Once you're on the uni-test interface, you must select the project on which you want to conduct tests.
To do that, click on to enter the path to your project's root folder.
Once you have entered your project's root folder path and it is correct,
if your PHP test files are located the tests
folder,
they will be automatically loaded after clicking the button.
If they are not located in the tests
folder, you can use the textfield
to specify your custom
folder. e.g.
Once your project's root and tests folder are correct, after clicking the button, all your PHP test files, including those located in sub-folders will populate the files list pane.
e.g.
Once the test files are loaded, click on the button to run unit tests.
To test a single file, uncheck all files by clicking the blank square,
without a check mark:
and check only the file you want to test.
Then click on the button.
Results are displayed on the left in the output pane. Notice, these are phpunit console outputs:
To boostrap a file, a file which needs to run before the test begins, it must first be located in your project test folder.
It won't be visible since its not a test file.
To view other files in your project directory, in the filter textfield, type "/
"
without the quotes.
The files will be grey-out and you will not be able to check them like a test file. But if the file is a PHP file, you will be able to bootstrap it. e.g.
If you hover the file name with your mouse pointer, a "cogs" icon will appear and you'll be able to click on it.
Once you do that, the bootstrap.php
file will now be bootstrapped when you click the to run your test.
web interface: https://github.com/crownlessking/utui
phpunit server: https://github.com/crownlessking/phpunit-server
If you need additional help or information, do not hesitate to contact me at:
dev@crownlessking.com


I am Dibyajyoti Mondal. I am currently studying Electronics and Telecommunication Engineering At Jadavpur University. I love to code and make cool stuffs. My interest lies in the field of Software engineering and development. I am currently trying my hands on Web development.


behaviors :
coverage_path.h
divide_area :
coverage_path.h
mst_publisher :
coverage_path.h
path :
coverage_path.h
path_publisher :
coverage_path.h
reconfigure :
coverage_path.h
resolution :
coverage_path.h
swarm :
coverage_path.h
swarm_sub :
coverage_path.h
swarm_timeout :
coverage_path.h
turning_points :
coverage_path.h
vertical :
coverage_path.h
visualize :
coverage_path.h
wp_publisher :
coverage_path.h
coverage_path
Author(s): Micha Sende
autogenerated on Thu Jan 27 2022 10:04:20


You have two options for making your CLRM available: publish it on the CrowdLogger server or self publish. Use the latter when developing or when you'd rather not wait to have your CLRM placed on the CrowdLogger server.
If you want to publish your CLRM to the UMass CrowdLogger server, then send your CLRM package, along with a description of who you are and what your app does to<EMAIL_ADDRESS>If you are hosting your own instance of a CrowdLogger server, then follow these steps:
packageURL
and logoURL
point to this location (use absolute urls)metadata.json
For this step, you will need some sort of server running. Python provides a nice built-in server, so use that if you do not have a full blown server like Apache running.
If you are using a web server, create a directory in a location that is accessible via your web server. If you do not have a web server, create a directory wherever you'd like, then start up a Python server in that directory with the command: python -m SimpleHTTPServer 8080
Each CLRM you plan to self publish in the location above should be updated such that the URLs point to that location. If using the Python server, use localhost:8080
as the url base, followed by the name of your JSON package (for packageURL
) or logo (for logoURL
).
You need to create a JSON file that consists of key value pairs where there is one key for each CLRM that you would like to publish (the key should be its clrmid
) and the value should be its metadata (as a JSON object). E.g.:
{ "demo1": { "clrmid": "demo1", "name": "Demo 1", "version": "1.5", "categories": ["app"], "description": "A simple CrowdLogger Remote Module demonstration.", "packageURL": "http://localhost:8080/demo.json", "permissions": ["userdata", "ui", "storage"], "logoURL": "http://localhost:8080/demo.jpg", "minCLVersion": "2.0.2" } }
You can call this file whatever you want. For the purposes of this tutorial, I'll assume you've named it clrms.json
.
For each CLRM you have listed in clrms.json
, copy over the CLRM package. These should be named according to how they are referenced in the packageURL
fields in the metadata/clrms.json
file. If you have logos, copy them over to this directory, as well.
Open up your browser that has CrowdLogger installed and go to Settings and add your URL, including the name of the file you created in Step 2, as a new repository. E.g., for the example above, I would add: http://localhost:8080/clrms.json
.
If you visit the Apps & Studies page from the CrowdLogger Status page, you should now see your app in the library. You can force your CLRM to be reloaded from the URL if you are in developer mode (you can toggle this mode in the CrowdLogger Settings). If you have the CLRM installed, then hovering over the module's icon will produce a popup with an Update
button. Press that to download the current package from the repository.


dplearn is a set of deep learning projects based on Tensorflow. TODO: learn Tensorflow for NLP works.


Serie A boss resigns after election investigation
by The Eagle OnlineGaetano Miccichè has resigned as the president of Serie A following an investigation into his election last year.
Miccichè, also the president of Banca IMI investment bank, was chosen unanimously in March 2018 by the Italian league’s 20 clubs.
But the Italian soccer federation opened an investigation last month after Genoa owner Enrico Preziosi alleged there were irregularities with how Miccichè was elected.
In a statement on Tuesday, Miccichè said: “The rumours in today’s newspapers, relating to the closure of the investigation into my appointment 20 months ago and to its possible outcome are unacceptable and forced me to make this decision.”
Lega Serie A, which runs the Italian top flight, had been without a president for almost year before Miccichè was elected.
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ReapVille School holds special assembly, elects PTA Exco
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Malta-based striker eyes Flying Eagles call up


Hospitals
An user-friendly interface for our partner hospitals, where they can add a spate of services.
Try NowAn user-friendly interface for our partner hospitals, where they can add a spate of services.
Try NowA highly interactive dashboard that proffers a collation of hospital services from across the country.
Try NowA prognostication that provides a near to accurate outcome to get a sense of your health.
Try NowThis pandemic has literally brought everyone on their knees, the despair and despondency that shrouded the country during covid gave us the motive to calibrate technology and help people out of these unprecedented times. Team Swasthify tries to provide its users with a service-based distinction of our partner hospitals from all across the country. What really keeps us going is a belief that one day we will make the notion of "hospitals at your fingertips" true.


Rune stones are an incredibly accessible way for anyone to access the mysteries and possibilities of their life. You need to search deep inside yourself and pinpoint your most burning and urgent life questions. Once you do this, you need to focus your energy and desire on connecting with the powers of the universe. You can then use your runes to gain guidance and achieve great blessings. It's really as easy as that. Using Rune Stones is a very popular method of divination used by many throughout the world.
Let's take a look at the details of how Runes work…
The entire collection of Runes is made up of 24 stones. Each one holds a different symbol and signifies a specific message from the universe. These messages are meant to reach your psyche on a subconscious level, and help you receive some very powerful answers. You can also use Runes when in need some help with very urgent questions that require quick answers! Rune Stones are an amazing tool that will empower you and ease your decision making, even on a daily basis. When reading about the mystical meaning of each stone, focus on the emotions and feelings that arise, and see how much easier it will be to gain clarity in your life.
Now, take a look at the following example…
1- Fehu, or the Wealth and Abundance Rune
2- Uruz, or the Power Rune
3- Thurisaz, or the Protective Rune
Now that you have seen how simple and straightforward the meanings of the Runes are, you understand why you don't need any special psychic powers of years of training to use them…
You can get accurate, insightful answers just like that!
What you've just read is, of course, only a brief snippet of the vast amount of knowledge and information that each Rune symbolizes…


Lookup location using Google Maps API
location
Enter location using City, State or City, Country
Search Google
Geo-Location Details
Longitude
Range: -180 to 180
Latitude
Range: -90 to 90
Location Description
City, State or City, Country
Save Device Location


rockstar
rockstar is a Chrome extension that adds these features to Okta:- Export Objects to CSV: eg, Users, Groups, Group Members, Group Rules, Directory Users, Apps, App Users, App Groups, App Notes, Network Zones, YubiKeys, Mappings, Admins...
- User home page: Show SSO (SAML assertion...)
- People page: enhanced search
- Person page: show login/email and AD info, show user detail, enhance menus/title, manage user's admin roles, verify factors, set password
- Groups page: search using regular expressions (like wildcards)
- Active Directory page: show OU tooltips, export OUs
- Identity Providers page: show SAML certificate expiration date
- Events: Expand All and Expand Each Row
- API: API Explorer, Pretty Print JSON
- Many: enhanced menus
rockstar runs in your browser, it doesn't send your data anywhere.
Note: This extension was not created by Okta. It is not supported by Okta. It is an unofficial extension created by the community.
Setup
rockstar is available on the Chrome Web Store.Usage
- Login to Okta or Okta Admin.
- Navigate to, e.g., Directory > People or Security > Administrators, etc.
- Look for the rockstar popup window in the upper-left corner of your browser.
Trouble? Suggestions? Feedback?
The JavaScript source is on GitHub, and you can open an issue or a pull request.
Previous updates
Feb 21, 2020 - rockstar is now available on the Chrome Web Store. Please start using this version ASAP, the old bookmark will stop working soon (see below).Jan 29, 2020 - Okta pushed out a change to oktapreview.com to block scripts and
I have published a version of rockstar on the Chrome Web Store and
Please bookmark this page and stay tuned for more updates. Please contact me with any questions or comments.


{%- extends 'utils/layout.html' -%} {% block title %} Terms of Service {% endblock %} {% block content_header %}
By using any part of the CS Center website, you accept and agree to be bound by the terms of this agreement. Additionally, you agree to obey any and all rules and / or guidelines set when using any services of this website, including those that may be changed arbitrarily. Thus, all such rules and / or guidelines are incorporated into the Terms of Service through this reference.
Any and all participation in this website implies acceptance of the terms of this document. If you do not accept or agree to abide by the rules and guidelines of this document, we ask you to please refrain from using the services of this website.
This site and its components are offered for informational purposes only; this site shall not be responsible or liable for the accuracy, usefulness or availability of any information transmitted or made available via the site, and shall not be responsible or liable for any error or omissions in that information.
Note that this site is not fully compliant to the standards of the GDPR (General Data Protection Regulation of the European Union) as this server and its intended audience are not located in a relevant area and we believe that to better serve this specific audience, some of the GDPR's terms go against our ideal service.
This site implements Google reCAPTCHA v3, and your use is subject to Google's terms of service.
We respect the intellectual property rights of everyone and believe that the products of one's own labor should be solely and entirely attributed to the creator. Our policy is to never use, make publicly available, or publish any content submitted to this website by its users. If you believe that any of your rights have not been respected, please report it to us at wcics.site(at)gmail.com.


CrimPapers
Articles published on 24 July 2020
On 24 July 2020, 5 new articles were published in 4 journals.
The Gendered Nature of Criminogenic Thinking Patterns Among Justice-Involved Clients: A Pilot Study by Natalie J. Jones, Damon Mitchell, Raymond Chip Tafrate
An Examination of the Professional Override of the Level of Service Inventory–ontario Revision by Laura C. Orton, Neil R. Hogan, J. Stephen Wormith
Social Support As A Moderator Between Syndemics and Posttraumatic Stress Among Women Experiencing Adversity by Kathryn H. Howell, Lauren M. Schaefer, Amanda J. Hasselle, Idia B. Thurston
‘no Black and White Answer About How Far We Can Go’: Police Decision Making Under the Domestic Violence Disclosure Scheme by Katerina Hadjimatheou, Jamie Grace
Michael D. White and Aili Malm (2020). Cops, Cameras, Andcrisis: Thepotentialandtheperilsofpolicebody-Worncameras


---
layout: page
permalink: /events/index.html
title: Public Events
description: "A list of my upcoming and past conference engagements"
---
{% include counteventdetails.html %}
If you're interested to know where I'm going to be and what events I'm attending, look no further! I will do my best to keep this up to date.
If you're interested in having me talk or help you organise an event, please contact me using your preferred method from my footer.
{% assign events_by_year = site.data.conferences | group_by:"year" | sort:"startdate" %}
{% for year in events_by_year %}
{{year.name}}
{% for event in year.items %}
-
{% if event.enddate == nil %}
{% if event.year > 2016 %}
{{ event.startdate | date: "%e %B %Y" }}
{% else %}
{{ event.startdate | date: "%B %Y" }}
{% endif %}
{% else %}
{{ event.startdate | date: "%e" }}-{{ event.enddate | date: "%e %B %Y" }}
{% endif %}
|
{% if event.url == nil %}
{{ event.name }}{{event.name}}
{% endif %}
|
{{ event.role | join: ', ' }}
({{ event.city }}, {{ event.country }})
{% if event.title != nil %}
Session: {{event.title}}
{% endif %}
{% endfor %}
{% endfor %}


{% extends "base.html" %} {% load i18n %} {% block page_title %}terms{% endblock %} {% block content %}
Please read these terms of service carefully before using "this Website"("service") operated by django-starchart.herokuapp.com ("us", 'we", "our"). These terms will be applied fully and affect to your use of this Website. By using this Website, you agreed to accept all Terms of Service written in here. You must not use this Website if you disagree with any of these Website's Terms of Service.
Other than the content you own, under these Terms, this Website and/or its licensors own all the intellectual property rights and materials contained in this Website.
You are granted limited license only for purposes of viewing the material contained on this Website.
You are specifically restricted from all of the following:
This Website is provided “as is,” with all faults, and we express no representations or warranties, of any kind related to this Website or the materials contained on this Website. Also, nothing contained on this Website shall be interpreted as advising you.
You hereby indemnify to the fullest extent this Website from and against any and/or all liabilities, costs, demands, causes of action, damages and expenses arising in any way related to your breach of any of the provisions of these Terms.
this Website is permitted to revise these Terms at any time as it sees fit, and by using this Website you are expected to review these Terms on a regular basis.
This Website is allowed to assign, transfer, and subcontract its rights and/or obligations under these Terms without any notification. However, you are not allowed to assign, transfer, or subcontract any of your rights and/or obligations under these Terms.
These Terms constitute the entire agreement between this Website and you in relation to your use of this Website, and supersede all prior agreements and understandings.
These Terms will be governed by and interpreted in accordance with the laws of Japan, and you submit to the non-exclusive jurisdiction of the state and federal courts located in Japan for the resolution of any disputes.


Hello!
installed emoncms system of Windows 8 with wamp server . Everything ok, rewrite_mode activated . When I go to register a new user on the main page of emoncms, emoncms stops writing in red "undefined ". Php.ini is ok as the installer guide.
Anyone have any ideas ? I tried searching the forum but without success. The proposed solutions do not work
I hope it was wrong to seek ...
Thank you!
F.
Re: Emoncms on user login returns "undefined "
A good starting point is checking your browser's 'developers mode' - usually F12 starts it, and look for any errors highlighted. I don't use emoncms on Windows, but I've seen similar errors occur in Raspbian with php 'sessions'.
Paul
Re: Emoncms on user login returns "undefined "
Hi Paul!
The browser answer:
Synchronous XMLHttpRequest on the main thread is deprecated because of its detrimental effects to the end user's experience. For more help, check http://xhr.spec.whatwg.org/.
http://xx.xx.xx.xx/Lib/jquery-1.11.3.min.js Failed to load resource: the server responded with a status of 404 (Not Found)
This is the error. xx.xx.xx.xx is my public ip.
Thanks.
F.
Re: Emoncms on user login returns "undefined "
Synchronous XMLHttpRequest is a warning.
The 404 is an error, can you access that file directly? If not, its bad instalation.
Re: Emoncms on user login returns "undefined "
Hi!
Yes, i access.
Maybe is a wamp configuration? Or some file of wamp?
I have do two times installation....
F.
Re: Emoncms on user login returns "undefined "
I not have idea... :-((((
F.
Re: Emoncms on user login returns "undefined "
This happens here too on a fresh install, since it's missing the /user/register.json
Re: Emoncms on user login returns "undefined "
I found that the .htaccess file was not copied with the downloaded 9.2 files from the zip, try adding it to your emoncms root from here: https://github.com/emoncms/emoncms/blob/stable/.htaccess
Re: Emoncms on user login returns "undefined "
Hello,
After installing emoncms on an 1&1 shared server, I experience exactly the same, unless there is a specific default user and password, I cannot register a new user, and as fvolpato I get the following message even though I have refreshed the .htaccess file with the content of the one suggested ; by the way the .htaccess already existed.
Thank you for your help
[Please don't post multiple copies - see "Read this before posting". Also, please add your image to your post, because an image linked on a 3rd party site can disappear, and that helps nobody. See "Adding a picture to a post" to find out how. I've deleted the copies. Moderator (RW) ]
I apologize, I tried several times because my post did not appear, thanks for your help
Re: Emoncms on user login returns "undefined "
The problem is now fixed, at least for a shared server located at 1&1, the rewrite syntax was not correct In the .htaccess file :
As the .htaccess is located in a /emoncms subdirectory, the rewrite must specify the subdirectory name :
Re: Emoncms on user login returns "undefined "
Hi to all. Solved!
I followed the advice of jcgonzales in the previous post and I solved the problem .
Thank you!
F.
Re: Emoncms on user login returns "undefined "
I have the same issue with version 9.3 on the latest build on Jessie, edited the .htaccess file as above to no avail. Absolutely clueless here...
Cheers
Ruben


Jody Jones
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All Class Model Elements
Logical Model.CallAttendant
Logical Model.Hardware
Logical Model.Hardware.ApprovedIndicator
Logical Model.Hardware.BlockedIndicator
Logical Model.Hardware.MessageIndicator
Logical Model.Hardware.Modem
Logical Model.Hardware.RingIndicator
Logical Model.Messaging
Logical Model.Messaging.Message
Logical Model.Messaging.VoiceMail
Logical Model.Screening
Logical Model.Screening.Blacklist
Logical Model.Screening.CallLogger
Logical Model.Screening.CallScreener
Logical Model.Screening.NomoroboService
Logical Model.Screening.Whitelist
Logical Model.User Interface
Logical Model.User Interface.WebApp
RUP 4+1


ok, i know this build is just for kicks but ive tried a few idea and to no avail im not getting the results now i cant use assassin or Shadow dancer, so i was thinking ranger/monk/wm, and this build is leaning more for pvp but can be used for pvm so i can lvl up then pvp.
forgot to mention halfling also.
Weapon Master is for melee weapons only. You cannot be a sling weapon master.
I'd lean more rogue/fighter type, or a cleric slinger with zen archery. Slings don't get a lot of damage so either sneaks or cleric buffs will help with that. There was another recent post on a halfling slinger that had some useful info and I believe at least a reference if not a link to a cleric slinger (by Avado IIRC)
Steve
Edited By Stravinsky00 on 09/25/05 19:08
yes i did look at that and it wasnt for me so if i cannot go for WM then id like death/sneak attacks.
A good thing about rogue slingers is that it helps with the undead. You might want to consider some fighter lvls to get shield, wpn specialization, higher attack, etc. It also works quite well with death attack. You may not be aware of it but rapid shot works with slings. That combined with haste will get more shots off. _________________ Entropy is a joule thief


YOBINE- yohimbine hydrochloride injection, solution
Akorn Animal Health, Inc.
Yobine® contains yohimbine with the chemical name 17 alpha-hydroxy-20 alpha-yohimban-16 beta-carboxylic acid methyl ester. Yohimbine hydrochloride has a molecular weight of 390.89, and the molecular formula is C21H26N2O3•HCI. The structural formula is:
Each mL contains: Yohimbine (as the hydrochloride) 2.0 mg, methylparaben 0.9 mg, propylparaben 0.1 mg, citric acid 3.34 mg, and water for injection, pH adjusted with sodium hydroxide.
Yohimbine is an indolealkylamine alkaloid that acts primarily by blocking central alpha-2 adrenoreceptors that are stimulated by xylazine. Yohimbine is an alpha-2 adrenergic receptor antagonist that easily penetrates the blood-brain barrier. It competitively blocks and antagonizes central nervous system depression or sedation and the bradycardia and respiratory depression caused by xylazine.
Xylazine, an alpha-2 adrenergic agonist with potent sedative, analgesic and muscle relaxant properties, has been used extensively as an analgesic-sedative restraining agent. It has also been used as a preanesthetic agent for many general anesthetics. The central nervous system depressant effect, as well as other pharmacologic effects, is dose dependent.
Yohimbine is useful to counteract the sedation after standard doses of xylazine. The competitive selective blocking of the alpha-2 adrenergic receptor by yohimbine displaces xylazine from these sites and thereby rapidly cancels the effect of the xylazine.
Yohimbine, when used at the prescribed dose, will effectively reverse the effects of xylazine when it is used alone in dogs. Yohimbine abbreviates the anesthesia and chemical restraint of the xylazine.
The reversal of the sedative effects of xylazine by I.V. injection of yohimbine is rapid, usually occurring within one to three minutes, regardless of the route of administration of xylazine.
Yohimbine should be used in dogs when it is desirable to reverse the effects of xylazine. Yohimbine has been used successfully to reverse the sedative effects of xylazine and to reverse the cardiac effects of xylazine such as arrhythmia and bradycardia when xylazine is administered alone.
For intravenous injection. The usual dose is 0.5 mL/20 lb body weight (0.05 mg/lb, or 0.11 mg/kg) to reverse the sedative effects of xylazine. The carefully calculated dose of yohimbine should be given intravenously slowly.
Occasionally a dog that has been reversed will show signs of apprehensiveness but this state quickly subsides.
The safety of yohimbine in pregnant dogs or in dogs intended for breeding has not been established.
Careful consideration should be given before administering to dogs known to be epileptic or seizure prone. The drug reverses the analgesic effects of xylazine as well as the sedative effects. If the animal was given xylazine for its analgesic properties, reversal may result in return of normal pain perception.
Yobine® was tolerated in dogs at 3 times (0.15 mg/lb) and 5 times (0.25 mg/lb) the recommended dose administered without xylazine at 3 intervals of 6 hours. Dose at the 5x magnitude occasionally produced brief seizures and muscle tremors but no lasting untoward effects were observed.
AKORN
Animal Health
Manufactured by:
Akorn, Inc.
Lake Forest, IL 60045
YO00N Rev. 07/14
Principal Display Panel Text for Container Label:
NDC 59399-115-20
Yobine®
INJECTION
Yohimbine Sterile Solution 2 mg/mL
Xylazine Reversing Agent and
Antidote for Use in Dogs Only
20 mL
CAUTION: Federal law restricts this drug to use
by or on the order of a licensed veterinarian.
NADA #140-866, Approved by FDA
Principal Display Panel Text for Carton Label:
NDC 59399-115-20
Yobine®
INJECTION
Yohimbine Sterile
Solution 2 mg/mL
Xylazine Reversing Agent
and Antidote for Use
in Dogs Only
20 mL
CAUTION: Federal law restricts
this drug to use by or on the
order of a licensed veterinarian.
Akorn Animal Health Logo
NADA #140-866, Approved by FDA
|
YOBINE
yohimbine hydrochloride injection, solution | ||||||||||||||||||||
| ||||||||||||||||||||
| ||||||||||||||||||||
| ||||||||||||||||||||
| ||||||||||||||||||||
|
| Labeler - Akorn Animal Health, Inc. (078876357) |
| Establishment | |||
| Name | Address | ID/FEI | Business Operations |
|---|---|---|---|
| Akorn, Inc | 603980319 | MANUFACTURE, ANALYSIS, STERILIZE, PACK, LABEL |


Set up a workspace to store the input and output data objects. You can do this using the Workspace Browser. Open the Workspace Browser and sign in by clicking on the "Sign In" link in the upper right courner. You will see a list of workspaces available workspace on the left hand side. Since you want to create a new workspace, scroll to the bottom of this list and click on the "+create" link to create a new workspace for this FBA project. You must pick a workspace name and decide what permissions the public will have for this workspace. The public options are none, read or write. Below, shows how to create a workspace named "pseudomonas" that will be publicly readable. This can also be shared with individual users from the Workspace Browser.
Now, using IRIS, select the workspace just created, "pseudomonas" as the active workspace. First, login to the KBase system from IRIS.
From the IRIS command prompt, use the authenticate
command to login. This will bring up a login window where you can enter your KBase username and password.
Once logged in, set the "pseudomonas" workspace created as the active workspace. This is done using the kbws-workspace
command. By running the command with no argument, you will see the current workspace. By running it with "pseudomonas" as the argument, it will select "pseudomonas" as the workspace.
IRIS also contains several commands for the creation and manipulation of workspaces and data objects inside workspaces. a more detailed explaination of those tools can be found in the Workspace tutorial. The workspace commands you will use here are kbws-listobj
to view the contents of our workspace and kbws-jobs
to see our currently running jobs.
 You can either select a genome that is already in our Central Data Store (CDS) or you can use a genome that you have annotated ourselves. In this tutorial, I will use the genome of Pseudomonas stutzeri A1501 from the CDS. If you want to use a genome not in the CDS, or alter the annotation of a KBase genome, please refer to the Genome Annotation Tutorial which will guide you through the process of annotating a genome from an assembly fasta file.
To import a genome fromt the CDS into our workspace, you use the command kbfba-loadfbagenome
. To use this command, you must give it a valid KBase genome id. The easiest way to find the KBase genome id is to use the Genome Browser. Since I know what genome I am looking for, I will type the name into the search box. As I type, the displayed set of genomes will change. I can click on the scientific name of the organism and bring up more information about the genome and make sure the annotation is up to date.
You will use the "kb|g.1147" KBase genome id. Now you can return to IRIS and load the genome into our workspace by using the kbfba-loadfbagenome
command with "kb|g.1147" as it's argument. Since our workspace is still set to "pseudomonas," our genome object will be created here.
You can use the kbws-listobj
command to verify that the "kb|g.1147" genome object has been created in your workspace.
Now that you have the genome object in our workspace, you can build a draft model using our genome object. The draft model is based only on the existing gene annotations in our genome model. It is relatively simple using the kbfba-buildfbamodel
command with our genome as the argument:
Here, you may notice that the kbfba-buildfbamodel
command has not completed. Although the IRIS command prompt has returned, and you can execute more commands. Our kbfba-buildfbamodel
command is still running and can be seen on the left side of the IRIS screen, under the "Running processes" header. When the command completes, it will be removed from under the "Running processes" header and a "Command complete" message will be printed to the IRIS screen.
Once the command is completed, you can view our draft model. The easiest way to do this is to return to our Workspace Browser. Note: you may have to reload the page to refresh the workspace contents. You should now see that our genome object and model object are in our workspace. To view more information about the model, you can click on the model name to bring up a popup with additional metadata for our model object. To view the actual model data, click on the "View HTML" link in the popup. This will open a new page showing the model contents. In this view, you see several tabs with detailed information about the model. Since this is a draft model, the "Gapfilling" and "Gapgen" tabs are empty.
It is also possible to view the model in the graphical metbolic map view, GLAMM. Please refer to the GLAMM tutorial for instructions.
Generally, the draft model created by kbfba-buildfbamodel
won't grow. This is mainly due to gene annotations missing in the genome object. These annotation include key metabolic genes and transporter necessary for growth in a given media. The gap filling process compares the set of reactions in our model to a database of all known reactions and attempts to find a set of reactions that, when added to our model, allow it to grow. This set of reactions, refered to as the gapfilling solution, can then be integrated into our model, creating a new model capable of growth on the media you used for gapfilling.
The gap filling method implements a cost function associated with each reaction and transporter to help us find the solution with the minimum number of reactions and transporters added. This is because, without addional information about the genome annotation, experimental data or known biochemistry, the solution with the fewest additional reactions is more likely to be correct.
The proposed gap filling solutions are just possible solutions based on minimizing the cost function. It is necessary to examine the set of reactions in the solution to judge whether it is plausible that these reactions are found in the organism. In order to create the best model, it is necessary to gap fill on several medias that the organism is known to grow on. Here, you will start with gap filling on complete media.
You can gapfill our model using the kbfba-gapfill
command with our model as the argument. There are several important options that this program can use. The most significant are those that deal with the methods run time. Because you cannot computationally examine all possible solutions, the method uses hueristics to explore solution space and returns the best (lowest cost) solution it has found in that time.
In this case, I am going to gapfill on complete media. In the interest of time, I will only ask for one solution and have the program only run for 10min. It is better to ask for more solutions and the let the program run for at least 1hr per solution.
Because this is a long running job. The system will return a "job id" so that you can monitor its status. The "job id" is the long string listed as the "Perm ref:"
You can monitor your job's status by using the workspace command kbws-jobs
. You will see the "status" of your job change from "queued" to "running" and finally to "done." Because these are long running jobs, they are excuted on a KBase compute cluster. Depending on the load on the system it can take sometime for the job go from the queue to running. Once the job is running, it should run uninterrupted until completion. You may run several jobs simultaneously, they will be run as cluster nodes become available.
In the case of gap filling, the results are added to our model object. If you run kbws-listobj
in your workspace, you will notice that no new files have been created. Again, you can use the Workspace Browser to view the results of our gapfilling.
From the Workspace Browser you can click on our model, in this case "kb|g.1147.fbamdl.1", and you will see a popup with the updated metadata for the model. Clicking on the "View HTML" will bring us to the model viewer page. Now the "Gapfilling" tab in our model viewer has been populated with the gap filling solution(s) you requested. In some rare cases, it is possible that the program wasn't able to find a solution in the given amount of time.
Here you see that a single solution has been returned. This solution adds 12 reactions to our initial model. This gap filling solution has not actually been integrated into the model. You can now examine the list of suggested changes and decide if you believe this solution is plausible. If you choose, you can update our model by integrating this solution, or you can return to the kbfba-gapfill
command, change the parameters and find more solutions. In this case, I will accept this solution and integrate it into the model. To do this, I must note the solution id. The solution id is the composed of the "Gapfill simulation" field + "." + "solution" + "." and the "Solution" field: "5271DC9A-7D77-11E2-86C3-05287082D269.solution.0"
With our solution id, you can now return to IRIS and integrate that solution into the model. You will use the kbfba-integratesolution
command giving it our model id and our solution id:
To view our integrated model, you can return to the Workspace Browser, open our model and then use the "View HTML" link to get to the Model Viewer. Now when, you look under the "Gapfill" tab, you see that the solution you integrated has had it's status updated to "Integrated" and more reactions have been added to our model. It is important to note that no new genes have been added to our model, only reactions with no associated genes.
Now that you have a gapfilled model on complete media, you can use it in a flux balance analysis to verify that the model will grow and examine the fluxes. In this example, I will be doing this using complete media. Usually, you will want to gapfill your model using a minimal media to improve it before running the FBA.
To run the fba, you will return to IRIS and use the kbfba-runfba
command giving it our model as the only argument. There are a number of options that you can explore to alter the fba performance or change the growth media. Again, the default media is Complete media.
Again, you will return to the Workspace Browser to view the FBA results. In our workspace, there is now a new file "kb|g.1147.fbamdl.1.fba.0". (It maybe necessary to refresh your Workspace Browser window.) If you click on this FBA, you will first get a popup of the FBA metadata and then again, click on the "View HTML" link. In this case, you can see that the model grows since it has a significant positive value for the "Objective value". Since you used the default settings, the objective function was for biomass production.
In the FBA viewer, there are tabs for "Overview", "Reaction Fluxes" and "Compound Fluxes". You can explore the contents of your FBA result by click on the tabs and searching for particular compounds or reactions of interest. It is also possible to view and compare multiple FBA results in the GLAMM viewer. Please refer to the GLAMM tutorial.


hsw-cli
The command-line REST tool for the Handshake wallet.
More information: home page
- Unlock the current wallet (timeout in seconds):
hsw-cli unlock passphrase timeout
- Lock the current wallet:
hsw-cli lock
- View the current wallet's details:
hsw-cli get
- View the current wallet's balance:
hsw-cli balance
- View the current wallet's transaction history:
hsw-cli history
- Send a transaction with the specified coin amount to an address:
hsw-cli send address 1.05
- View the current wallet's pending transactions:
hsw-cli pending
- View details about a transaction:
hsw-cli tx transaction_hash


Oh, hey.
We're Baltimore's JavaScript community and we want to hang out with you. Check out our First Wednesday meetups or submit a talk idea of your own!
We really do want to hang out with you, and we've got a code of conduct that's really important to us. Please read and follow it if you want to hang out too, thanks. :D
Our Organizers
Hi, this is what we look like! We love making CCJS run. Find any of us at any event and say hello, or email us at<EMAIL_ADDRESS>any time.
Join our Slack team
Slack is where we all virtually hang out in between our in-person events. Come say hello, ask questions about JavaScript, about Baltimore in general, or anything you want!
Give us your email here (or at slack.charmcityjs.org) and we'll email you an invite so you can sign up and join us! (Didn't get an invite? Email us at<EMAIL_ADDRESS>and we'll get it fixed ASAP.)
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All site visitors can view the Exif metadata of an image in the Gallery module. Exif (Exchangeable Image File Format) is a variation of the JPEG format and is used by most digital cameras. When you take a picture Exif Metadata information is stored for each picture. This information varies between cameras but can include information such as the date, time, camera settings, shutter speed, etc.


Input a number to find its Additive Persistence
Input a number to find its Multiplicative Persistence


Hello Bike Enthusiasts,
Please put this on your
mountain bike race calendar.
Let me know if you need any
other information or if I
need to do anything else.
Thanks so much!
Celia Bertoia
Team WinS
Bozeman, MT
BOHART BASH MOUNTAIN BIKE
RACE
Team WinS (Women in Sports)
presents:
WHAT: The Bohart Bash
Mountain Bike Race
WHEN: July 11, 2004, race
start 10 AM
Registration and check in:
8:30-9:30 AM
WHERE: Bohart Ranch, 16 miles
north of Bozeman up
Bridger Canyon
PACKET PICKUP: Saturday July
10, 5-7 PM at Bangtail Bikes
$25 entry fee up until June
30th
$30 entry fee after June
30th
$10 for ages 5-11
$10 NORBA 1-day Sport
License (necessary for racing)
purchase at packet pickup or
race day if you don_t
already have one.
FEE includes: Goodie bag,
post race snacks, CASH
prizes for Expert Division,
AWARDS for top finishers,
RAFFLE DRAWING for riders
and spectators.
COURSE: 8K lap of hilly
trails through the forest of
Bohart Ranch. Expert women
do 4 laps, Expert men do 5
laps, Sport division is 3
laps, Beginner is 2 laps,
1st Timer is 1 lap, Kids_
Race (5-11) is a short loop.
SAFETY: You MUST purchase a
NORBA (National Off-Road
Bicycle Association) one-day
license for insurance
purposes. Please NO DOGS.
Everyone MUST wear helmets.
PURPOSE: This is one of the
few mountain bike races in
Montana, and it is a
fundraiser for AWARE, a nonprofit
organization to help
disadvantaged children and
adults.
CONTACT: Call Michelle Flenniken
for more details,
<EMAIL_ADDRESS>or
579-7348, or visit
www.active.com to register


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[§654-9] Other remedies not affected. The remedy provided by this chapter shall be in addition to, and shall not be deemed to affect, any other remedy. [L Sp 1949, c 7, pt of §1; RL 1955, §244-29; HRS §654-30; am L 1972, c 90, §1(g); ren HRS §654-9]