| Note 2: In Master mode, if the FIFO mode is enabled, the SPIEN bit will be set to 1 automatically after writing data into the 4-layer depth transmit FIFO. | ||
| When all data stored in transmit FIFO buffer are transferred, the SPIEN bit will back to . | ||
| [24] | RXEMPTY | Receive FIFO Buffer Empty Indicator (Read Only) |
| 0 = The receive FIFO buffer is not empty. | ||
| 1 = The receive FIFO buffer is empty. | ||
| Note: It's a mutual mirror bit of SPI_STATUS[24]. | ||
| [25] | RXFULL | Receive FIFO Buffer Full Indicator (Read Only) |
| 0 = The receive FIFO buffer is not full. | ||
| 1 = The receive FIFO buffer is full. | ||
| Note: It's a mutual mirror bit of SPI_STATUS[25] | ||
| [26] | TXEMPTY | Transmit FIFO Buffer Empty Indicator (Read Only) |
| 0 = The transmit FIFO buffer is not empty. | ||
| 1 = The transmit FIFO buffer is empty. | ||
| Note: It's a mutual mirror bit of SPI_STAUTS[26]. | ||
| [27] | TXFULL | Transmit FIFO Buffer Full Indicator (Read Only) |
| 0 = The transmit FIFO buffer is not full. | ||
| 1 = The transmit FIFO buffer is full. | ||
| Note: It's a mutual mirror bit of SPI_STATUS[27]. |
Definition at line 9061 of file Mini58Series.h.
| __IO uint32_t TIMER_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | PSC | Prescale Counter |
| Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter. | ||
| If this field is 0 (PSC = 0), then there is no scaling. | ||
| [17] | CMPCTL | Timer Compared Mode Select Bit |
| 0 = The behavior selection in one-shot or periodic mode Disabled. | ||
| When user updates CMPDAT while timer is running in one-shot or periodic mode, | ||
| CNT will be reset to default value. | ||
| 1 = The behavior selection in one-shot or periodic mode Enabled. | ||
| When user updates CMPDAT while timer is running in one-shot or periodic mode, the limitations as bellows list, | ||
| If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. | ||
| If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. | ||
| If updated CMPDAT value < CNT, CNT will be reset to default value. | ||
| [18] | TGLPINSEL | Toggle-output Pin Select Bit |
| 0 = Toggle mode output to TMx (Timer Event Counter Pin). | ||
| 1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). | ||
| [19] | CAPSRC | Capture Pin Source Select Bit |
| 0 = Capture Function source is from TMx_EXT (x= 0~1) | ||
| pin. | ||
| 1 = Capture Function source is from internal ACMP output signal. | ||
| User can set CAPSRCMP (TIMERx_EXTCTL[9]) to decide which ACMP output signal as timer capture source. | ||
| [23] | WKEN | Wake-up Function Enable Bit |
| If this bit is set to 1, while the timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. | ||
| 0 = Wake-up function Disabled if timer interrupt signal generated. | ||
| 1 = Wake-up function Enabled if timer interrupt signal generated. | ||
| [24] | EXTCNTEN | Event Counter Mode Enable Bit |
| This bit is for external counting pin function enabled. | ||
| 0 = Event counter mode Disabled. | ||
| 1 = Event counter mode Enabled. | ||
| Note: When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source | ||
| [25] | ACTSTS | Timer Active Status (Read Only) |
| This bit indicates the 24-bit up counter status. | ||
| 0 = 24-bit up counter is not active. | ||
| 1 = 24-bit up counter is active. | ||
| [26] | RSTCNT | Timer Counter Reset |
| Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1. | ||
| 0 = No effect. | ||
| 1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit. | ||
| [28:27] | OPMODE | Timer Counting Mode Selection |
| 00 = The Timer controller is operated in one-shot mode. | ||
| 01 = The Timer controller is operated in periodic mode. | ||
| 10 = The Timer controller is operated in toggle-output mode. | ||
| 11 = The Timer controller is operated in continuous counting mode. | ||
| [29] | INTEN | Timer Interrupt Enable Bit |
| 0 = Timer Interrupt Disabled. | ||
| 1 = Timer Interrupt Enabled. | ||
| Note: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal will be generated and inform CPU. | ||
| [30] | CNTEN | Timer Counting Enable Bit |
| 0 = Stops/Suspends counting. | ||
| 1 = Starts counting. | ||
| Note1: In stop status, and then setting CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. | ||
| Note2: This bit is auto-cleared by hardware in one-shot mode (TIMERx_CTL[28:27] = 2'b00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated. | ||
| [31] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Bit (Write Protect) |
| 0 = ICE debug mode acknowledgement effects TIMER counting. | ||
| TIMER counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| TIMER counter will keep going no matter CPU is held by ICE or not. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
Definition at line 10386 of file Mini58Series.h.
| __IO uint32_t WDT_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RSTCNT | Reset WDT Up Counter (Write Protect) |
| 0 = No effect. | ||
| 1 = Reset the internal 18-bit WDT up counter value. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: This bit will be automatically cleared by hardware. | ||
| [1] | RSTEN | WDT Time-out Reset Enable Bit (Write Protect) |
| Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. | ||
| 0 = WDT time-out reset function Disabled. | ||
| 1 = WDT time-out reset function Enabled. | ||
| Note: This bit is write-protected. Refer to the SYS_REGLCTL register. | ||
| [2] | RSTF | WDT Time-out Reset Flag |
| This bit indicates the system has been reset by WDT time-out reset or not. | ||
| 0 = WDT time-out reset did not occur. | ||
| 1 = WDT time-out reset occurred. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [3] | IF | WDT Time-out Interrupt Flag |
| This bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval | ||
| 0 = WDT time-out interrupt did not occur. | ||
| 1 = WDT time-out interrupt occurred. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [4] | WKEN | WDT Time-out Wake-up Function Control (Write Protect) |
| If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. | ||
| 0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. | ||
| 1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to LIRC or LXT. | ||
| [5] | WKF | WDT Time-out Wake-up Flag (Write Protect) |
| This bit indicates the interrupt wake-up flag status of WDT | ||
| 0 = WDT does not cause chip wake-up. | ||
| 1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: This bit is cleared by writing 1 to it. | ||
| [6] | INTEN | WDT Time-out Interrupt Enable Bit (Write Protect) |
| If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. | ||
| 0 = WDT time-out interrupt Disabled. | ||
| 1 = WDT time-out interrupt Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [7] | WDTEN | WDT Enable Bit (Write Protect) |
| 0 = WDT Disabled (This action will reset the internal up counter value). | ||
| 1 = WDT Enabled. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0. | ||
| [10:8] | TOUTSEL | WDT Time-out Interval Selection (Write Protect) |
| These three bits select the time-out interval period for the WDT. | ||
| 000 = 2^4 * WDT_CLK. | ||
| 001 = 2^6 * WDT_CLK. | ||
| 010 = 2^8 * WDT_CLK. | ||
| 011 = 2^10 * WDT_CLK. | ||
| 100 = 2^12 * WDT_CLK. | ||
| 101 = 2^14 * WDT_CLK. | ||
| 110 = 2^16 * WDT_CLK. | ||
| 111 = 2^18 * WDT_CLK. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [31] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Bit (Write Protect) |
| 0 = ICE debug mode acknowledgement affects WDT counting. | ||
| WDT up counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| WDT up counter will keep going no matter CPU is held by ICE or not. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
Definition at line 11454 of file Mini58Series.h.
| __IO uint32_t WWDT_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WWDTEN | WWDT Enable Bit |
| Set this bit to enable WWDT counter counting. | ||
| 0 = WWDT counter is stopped. | ||
| 1 = WWDT counter is starting counting. | ||
| [1] | INTEN | WWDT Interrupt Enable Bit |
| If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. | ||
| 0 = WWDT counter compare match interrupt Disabled. | ||
| 1 = WWDT counter compare match interrupt Enabled. | ||
| [11:8] | PSCSEL | WWDT Counter Prescale Period Select Bits |
| 0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. | ||
| 0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. | ||
| 0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. | ||
| 0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. | ||
| 0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. | ||
| 0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. | ||
| 0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. | ||
| 0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. | ||
| 1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. | ||
| 1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. | ||
| 1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. | ||
| 1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. | ||
| 1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. | ||
| 1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. | ||
| 1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. | ||
| 1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. | ||
| [21:16] | CMPDAT | WWDT Window Compare Bits |
| Set this register to adjust the valid reload window. | ||
| Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. | ||
| If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. | ||
| [31] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Bit |
| 0 = ICE debug mode acknowledgement effects WWDT counting. | ||
| WWDT down counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| WWDT down counter will keep going no matter CPU is held by ICE or not. |
Definition at line 11585 of file Mini58Series.h.
| __IO uint32_t I2C_T::CTL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WKEN | Wake-up Enable Bit |
| 0 = I2C wake-up function Disabled. | ||
| 1 = I2C wake-up function Enabled. | ||
| The system can be woken up by I2C bus when the system is set into Power mode and the received data matched one of the addresses in Address Register. | ||
| Note: Only I2C0 channel supports wake-up function. This bit is not valid on I2C1 channel. | ||
| [1] | TWOLVFIFO | Two-level Buffer Enable Bit |
| 0 = Two-level buffer Disabled. | ||
| 1 = Two-level buffer Enabled. | ||
| Set to enable the two-level buffer for I2C transmitted or received buffer. | ||
| It is used to improve the performance of the I2C bus. | ||
| If this bit is set = 1, the control bit of STA for repeat start or STO bit should be set after the current SI is clear. | ||
| For example: if there are 4 data shall be transmitted and then stop it. | ||
| The STO bit shall be set after the 3rd data's SI event being clear. | ||
| In this time, the 4th data can be transmitted and the I2C stop after the 4th data transmission don. | ||
| [2] | NSTRETCH | No Stretch On The I2C Bus |
| 0 = The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode. | ||
| 1 = The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode. | ||
| [3] | OVIEN | I2C Overrun Interrupt Control |
| Setting OVIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is overrun event in received buffer. | ||
| 0 = Overrun Interrupt Disabled. | ||
| 1 = Overrun Interrupt Enabled. | ||
| [4] | URIEN | I2C Under Run Interrupt Control |
| Setting URIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is under run event happened in transmitted buffer. | ||
| 0 = Under run Interrupt Disabled. | ||
| 1 = Under run Interrupt Enabled. |
Definition at line 4812 of file Mini58Series.h.
| __I uint32_t ADC_T::DAT |
| Bits | Field | Descriptions |
|---|---|---|
| [9:0] | RESULT | A/D Conversion Result |
| This field contains conversion result of ADC. | ||
| [16] | OV | Over Run Flag |
| If converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. | ||
| It is cleared by hardware after the ADC_DAT register is rea. | ||
| 0 = Data in RESULT[9:0] is recent conversion result. | ||
| 1 = Data in RESULT[9:0] overwrote. | ||
| [17] | VALID | Valid Flag |
| This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read. | ||
| 0 = Data in RESULT[9:0] bits not valid. | ||
| 1 = Data in RESULT[9:0] bits valid. |
Definition at line 344 of file Mini58Series.h.
| __IO uint32_t I2C_T::DAT |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DAT | I2C Data Register |
| Bit [7:0] is located with the 8-bit transferred data of the I2C serial port. |
Definition at line 4615 of file Mini58Series.h.
| __IO uint32_t UART_T::DAT |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DAT | Receiving/Transmit Buffer |
| Write Operation: | ||
| By writing one byte to this register, the data byte will be stored in transmitter FIFO. | ||
| The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TX. | ||
| Read Operation: | ||
| By reading this register, the UART will return an 8-bit data received from receiving FIFO. |
Definition at line 10719 of file Mini58Series.h.
| __IO uint32_t GPIO_T::DATMSK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DATMSK0 | Port 0-5 Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. | ||
| If the write signal is masked, writing data to the protect bit is ignore. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [1] | DATMSK1 | Port 0-5 Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. | ||
| If the write signal is masked, writing data to the protect bit is ignore. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [2] | DATMSK2 | Port 0-5 Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. | ||
| If the write signal is masked, writing data to the protect bit is ignore. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [3] | DATMSK3 | Port 0-5 Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. | ||
| If the write signal is masked, writing data to the protect bit is ignore. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [4] | DATMSK4 | Port 0-5 Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. | ||
| If the write signal is masked, writing data to the protect bit is ignore. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [5] | DATMSK5 | Port 0-5 Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. | ||
| If the write signal is masked, writing data to the protect bit is ignore. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [6] | DATMSK6 | Port 0-5 Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. | ||
| If the write signal is masked, writing data to the protect bit is ignore. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [7] | DATMSK7 | Port 0-5 Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. | ||
| If the write signal is masked, writing data to the protect bit is ignore. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. |
Definition at line 2077 of file Mini58Series.h.
| __IO uint32_t GPIO_DB_T::DBCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | DBCLKSEL | De-bounce Sampling Cycle Selection |
| 0000 = Sample interrupt input once per 1 clock. | ||
| 0001 = Sample interrupt input once per 2 clocks. | ||
| 0010 = Sample interrupt input once per 4 clocks. | ||
| 0011 = Sample interrupt input once per 8 clocks. | ||
| 0100 = Sample interrupt input once per 16 clocks. | ||
| 0101 = Sample interrupt input once per 32 clocks. | ||
| 0110 = Sample interrupt input once per 64 clocks. | ||
| 0111 = Sample interrupt input once per 128 clocks. | ||
| 1000 = Sample interrupt input once per 256 clocks. | ||
| 1001 = Sample interrupt input once per 2*256 clocks. | ||
| 1010 = Sample interrupt input once per 4*256 clocks. | ||
| 1011 = Sample interrupt input once per 8*256 clocks. | ||
| 1100 = Sample interrupt input once per 16*256 clocks. | ||
| 1101 = Sample interrupt input once per 32*256 clocks. | ||
| 1110 = Sample interrupt input once per 64*256 clocks. | ||
| 1111 = Sample interrupt input once per 128*256 clocks. | ||
| [4] | DBCLKSRC | De-bounce Counter Clock Source Selection |
| 0 = De-bounce counter clock source is HCLK. | ||
| 1 = De-bounce counter clock source is 10 kHz internal low speed RC oscillator (LIRC). | ||
| [5] | ICLKON | Interrupt Clock On Mode |
| 0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. | ||
| 1 = All I/O pins edge detection circuit is always active after reset. | ||
| Note: It is recommended to disable this bit to save system power if no special application concern. |
Definition at line 2974 of file Mini58Series.h.
| __IO uint32_t GPIO_T::DBEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DBEN0 | Port 0-5 Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [1] | DBEN1 | Port 0-5 Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [2] | DBEN2 | Port 0-5 Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [3] | DBEN3 | Port 0-5 Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [4] | DBEN4 | Port 0-5 Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [5] | DBEN5 | Port 0-5 Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [6] | DBEN6 | Port 0-5 Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [7] | DBEN7 | Port 0-5 Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note1: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. |
Definition at line 2305 of file Mini58Series.h.
| __I uint32_t FMC_T::DFBA |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | DFBA | Data Flash Base Address |
| This register indicates Data Flash start address. It is a read only register. | ||
| The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 | ||
| This register is valid when DFEN (CONFIG0[0]) =0 . |
Definition at line 1475 of file Mini58Series.h.
| __IO uint32_t GPIO_T::DINOFF |
| Bits | Field | Descriptions |
|---|---|---|
| [16] | DINOFF0 | Port 0-5 Pin[N] Digital Input Path Disable Control |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [17] | DINOFF1 | Port 0-5 Pin[N] Digital Input Path Disable Control |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [18] | DINOFF2 | Port 0-5 Pin[N] Digital Input Path Disable Control |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [19] | DINOFF3 | Port 0-5 Pin[N] Digital Input Path Disable Control |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [20] | DINOFF4 | Port 0-5 Pin[N] Digital Input Path Disable Control |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [21] | DINOFF5 | Port 0-5 Pin[N] Digital Input Path Disable Control |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [22] | DINOFF6 | Port 0-5 Pin[N] Digital Input Path Disable Control |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [23] | DINOFF7 | Port 0-5 Pin[N] Digital Input Path Disable Control |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. |
Definition at line 1857 of file Mini58Series.h.
| __IO uint32_t GPIO_T::DOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DOUT0 | Port 0-5 Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [1] | DOUT1 | Port 0-5 Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [2] | DOUT2 | Port 0-5 Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [3] | DOUT3 | Port 0-5 Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [4] | DOUT4 | Port 0-5 Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [5] | DOUT5 | Port 0-5 Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [6] | DOUT6 | Port 0-5 Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [7] | DOUT7 | Port 0-5 Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. |
Definition at line 1955 of file Mini58Series.h.
| __IO uint32_t PWM_T::DTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DTI01 | Dead-time Interval Register For Pair Of Channel0 And Channel1 (PWM0_CH0 And PWM0_CH1 Pair) |
| These 8 bits determine dead-time length. | ||
| The unit time of dead-time length is received from corresponding PWM_CLKDIV bits. | ||
| [15:8] | DTI23 | Dead-time Interval Register For Pair Of Channel2 And Channel3 (PWM0_CH2 And PWM0_CH3 Pair) |
| These 8 bits determine dead-time length. | ||
| The unit time of dead-time length is received from corresponding PWM_CLKDIV bits. | ||
| [23:16] | DTI45 | Dead-time Interval Register For Pair Of Channel4 And Channel5 (PWM0_CH4 And PWM0_CH5 Pair) |
| These 8 bits determine dead-time length. | ||
| The unit time of dead-time length is received from corresponding PWM_CLKDIV bits. |
Definition at line 7275 of file Mini58Series.h.
| __IO uint32_t TIMER_T::EINTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CAPIF | Timer External Capture Interrupt Flag |
| This bit indicates the timer external capture interrupt flag status. | ||
| 0 = TMx_EXT (x= 0~1) pin interrupt did not occur. | ||
| 1 = TMx_EXT (x= 0~1) pin interrupt occurred. | ||
| Note1: This bit is cleared by writing 1 to it. | ||
| Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~1) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. | ||
| Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. | ||
| If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. |
Definition at line 10520 of file Mini58Series.h.
| __IO uint32_t TIMER_T::EXTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CNTPHASE | Timer External Count Phase |
| This bit indicates the detection phase of external counting pin TMx (x= 0~1). | ||
| 0 = A falling edge of external counting pin will be counted. | ||
| 1 = A rising edge of external counting pin will be counted. | ||
| [2:1] | CAPEDGE | Timer External Capture Pin Edge Detection |
| 00 = A falling edge on TMx_EXT (x= 0~1) pin will be detected. | ||
| 01 = A rising edge on TMx_EXT (x= 0~1) pin will be detected. | ||
| 10 = Either rising or falling edge on TMx_EXT (x= 0~1) pin will be detected. | ||
| 11 = Reserved. | ||
| [3] | CAPEN | Timer External Capture Pin Enable Bit |
| This bit enables the TMx_EXT pin. | ||
| 0 = TMx_EXT (x= 0~1) pin Disabled. | ||
| 1 = TMx_EXT (x= 0~1) pin Enabled. | ||
| [4] | CAPFUNCS | Capture Function Select Bit |
| 0 = External Capture Mode Enabled. | ||
| 1 = External Reset Mode Enabled. | ||
| Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~1) pin is using to save the 24-bit timer counter value to CAPDAT register. | ||
| Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~1) pin is using to reset the 24-bit timer counter value. | ||
| [5] | CAPIEN | Timer External Capture Interrupt Enable Bit |
| 0 = TMx_EXT (x= 0~1) pin detection Interrupt Disabled. | ||
| 1 = TMx_EXT (x= 0~1) pin detection Interrupt Enabled. | ||
| Note: CAPIEN is used to enable timer external interrupt. | ||
| If CAPIEN enabled, timer will generate an interrupt when CAPIF (TIMERx_EINTSTS[0]) is . | ||
| For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, an 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. | ||
| [6] | CAPDBEN | Timer External Capture Pin De-bounce Enable Bit |
| 0 = TMx_EXT (x= 0~1) pin de-bounce Disabled. | ||
| 1 = TMx_EXT (x= 0~1) pin de-bounce Enabled. | ||
| Note1: If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit. | ||
| Note2: The de-bounce circuit doesn't support ACMP output. | ||
| [7] | CNTDBEN | Timer Counter Pin De-bounce Enable Bit |
| 0 = TMx (x= 0~1) pin de-bounce Disabled. | ||
| 1 = TMx (x= 0~1) pin de-bounce Enabled. | ||
| Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. | ||
| [8] | CAPSEL | Capture Mode Select Bit |
| 0 = Timer counter reset function or free-counting mode of timer capture function. | ||
| 1 = Trigger-counting mode of timer capture function. | ||
| [9] | ACMPSSEL | ACMP Source Selection to Trigger Capture Function |
| For Timer 0: | ||
| 0 = Capture Function source is from ACMP0 output signal for TIMER0. | ||
| 1 = Capture Function source is from ACMP1 output signal for TIMER0. | ||
| For Timer 1: | ||
| 0 = Capture Function source is from ACMP1 output signal for TIMER1. | ||
| 1 = Capture Function source is from ACMP0 output signal for TIMER1. |
Definition at line 10502 of file Mini58Series.h.
| __IO uint32_t ADC_T::EXTSMPT |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | EXTSMPT | Additional ADC Sample Clock |
| If the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal. | ||
| The default sampling time is 1 ADC clocks. | ||
| The additional clock number will be inserted to lengthen the sampling clock. | ||
| 0 = Number of additional clock cycles is 0. | ||
| 1 = Number of additional clock cycles is 1. | ||
| 2 = Number of additional clock cycles is 2. | ||
| 3 = Number of additional clock cycles is 4. | ||
| 4 = Number of additional clock cycles is 8. | ||
| 5 = Number of additional clock cycles is 16. | ||
| 6 = Number of additional clock cycles is 32. | ||
| 7 = Number of additional clock cycles is 64. | ||
| 8 = Number of additional clock cycles is 128. | ||
| 9 = Number of additional clock cycles is 256. | ||
| 10 = Number of additional clock cycles is 512. | ||
| 11 = Number of additional clock cycles is 1024. | ||
| 12 = Number of additional clock cycles is 1024. | ||
| 13 = Number of additional clock cycles is 1024. | ||
| 14 = Number of additional clock cycles is 1024. | ||
| 15 = Number of additional clock cycles is 1024. |
Definition at line 567 of file Mini58Series.h.
| __IO uint32_t FMC_T::FATCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [6:4] | FOM | Frequency Optimization Mode (Write Protect) |
| The Mini58 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency. | ||
| 0x1 = Frequency <= 24MHz. | ||
| Others = Frequency <= 50MHz. |
Definition at line 1489 of file Mini58Series.h.
| __IO uint32_t UART_T::FIFO |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | RXRST | RX Field Software Reset |
| When RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared. | ||
| 0 = No effect. | ||
| 1 = Reset RX internal state machine and pointers reset. | ||
| Note: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles. | ||
| [2] | TXRST | TX Field Software Reset |
| When TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared. | ||
| 0 = No effect. | ||
| 1 = Reset TX internal state machine and pointers reset. | ||
| Note: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles. | ||
| [7:4] | RFITL | RX FIFO Interrupt (RDAINT) Trigger Level (Only Available In UART0) |
| When the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set (if RDAIEN in UART_INTEN register is enable, an interrupt will generated). | ||
| 0000 = RX FIFO Interrupt Trigger Level is 1 byte. | ||
| 0001 = RX FIFO Interrupt Trigger Level is 4 bytes. | ||
| 0010 = RX FIFO Interrupt Trigger Level is 8 bytes. | ||
| 0011 = RX FIFO Interrupt Trigger Level is 14 bytes. | ||
| Other = Reserved. | ||
| [8] | RXOFF | Receiver Disable Register (Only Available In UART0) |
| The receiver is disabled or not (setting 1 to disable the receiver). | ||
| 0 = Receiver Enabled. | ||
| 1 = Receiver Disabled. | ||
| Note: This field is used for RS-485 Normal Multi-drop mode. | ||
| It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programme. | ||
| [19:16] | RTSTRGLV | RTS Trigger Level (For Auto-flow Control Use) (Only Available In UART0) |
| 0000 = RTS Trigger Level is 1 byte. | ||
| 0001 = RTS Trigger Level is 4 bytes. | ||
| 0010 = RTS Trigger Level is 8 bytes. | ||
| 0011 = RTS Trigger Level is 14 bytes. | ||
| Other = Reserved. | ||
| Note: This field is used for RTS auto-flow control. |
Definition at line 10802 of file Mini58Series.h.
| __IO uint32_t SPI_T::FIFOCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXRST | Clear Receive FIFO Buffer |
| 0 = No effect. | ||
| 1 = Clear receive FIFO buffer. | ||
| Note: This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared. | ||
| [1] | TXRST | Clear Transmit FIFO Buffer |
| 0 = No effect. | ||
| 1 = Clear transmit FIFO buffer. | ||
| Note: This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared. | ||
| [2] | RXTHIEN | Receive Threshold Interrupt Enable Bit |
| 0 = Receive threshold interrupt Disabled. | ||
| 1 = Receive threshold interrupt Enabled. | ||
| [3] | TXTHIEN | Transmit Threshold Interrupt Enable Bit |
| 0 = Transmit threshold interrupt Disabled. | ||
| 1 = Transmit threshold interrupt Enabled. | ||
| [6] | RXOVIEN | Receive FIFO Overrun Interrupt Enable Bit |
| 0 = Receive | ||
| FIFO overrun interrupt Disabled. | ||
| 1 = Receive | ||
| FIFO overrun interrupt Enabled. | ||
| [21] | RXTOIEN | Receive FIFO Time-out Interrupt Enable Bit |
| 0 = Time-out interrupt Disabled. | ||
| 1 = Time-out interrupt Enabled. | ||
| [25:24] | RXTH | Receive FIFO Threshold |
| If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. | ||
| [29:28] | TXTH | Transmit FIFO Threshold |
| If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. |
Definition at line 9235 of file Mini58Series.h.
| __IO uint32_t UART_T::FIFOSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXOVIF | RX Overflow Error Interrupt Flag |
| This bit is set when RX FIFO overflow. | ||
| If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set. | ||
| 0 = RX FIFO did not overflow. | ||
| 1 = RX FIFO overflowed. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [3] | ADDRDETF | RS-485 Address Byte Detection Flag (Only Available In UART0) |
| This bit is set to 1 while ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode and receive detect a data with an address bit (bit 9 = 1). | ||
| Note1: This field is used for RS-485 function mode. | ||
| Note2: This bit is cleared by writing 1 to it. | ||
| [4] | PEF | Parity Error Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid "parity bit". | ||
| 0 = No parity error is generated. | ||
| 1 = Parity error is generate. | ||
| Note: This bit is read only, but can be cleared by writing '1' to it. | ||
| [5] | FEF | Framing Error Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit follows the last data bit or parity bit is detected as logic 0). | ||
| 0 = No framing error is generated. | ||
| 1 = Framing error is generated. | ||
| Note: This bit is read only, but can be cleared by writing '1' to it . | ||
| [6] | BIF | Break Interrupt Flag (Read Only) |
| This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits). | ||
| 0 = No Break interrupt is generated. | ||
| 1 = Break interrupt is generated. | ||
| Note: This bit is read only, but software can write 1 to clear it. | ||
| [13:8] | RXPTR | RX FIFO Pointer (Read Only) |
| This field indicates the RX FIFO Buffer Pointer. | ||
| When UART receives one byte from external device, RXPTR increases one. | ||
| When one byte of RX FIFO is read by CPU, RXPTR decreases on. | ||
| The Maximum value shown in RXPTR is 15. | ||
| When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. | ||
| As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 1. | ||
| [14] | RXEMPTY | Receiver FIFO Empty (Read Only) |
| This bit initiate RX FIFO empty or not. | ||
| 0 = RX FIFO is not empty. | ||
| 1 = RX FIFO is empty. | ||
| Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. | ||
| It will be cleared when UART receives any new data. | ||
| [15] | RXFULL | Receiver FIFO Full (Read Only) |
| This bit initiates RX FIFO full or not. | ||
| 0 = RX FIFO is not full. | ||
| 1 = RX FIFO is full. | ||
| Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. | ||
| [21:16] | TXPTR | TX FIFO Pointer (Read Only) |
| This field indicates the TX FIFO Buffer Pointer. | ||
| When CPU writes one byte into UART_DAT, TXPTR increases one. | ||
| When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases on. | ||
| The Maximum value shown in TXPTR is 15. | ||
| When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. | ||
| As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 1. | ||
| [22] | TXEMPTY | Transmitter FIFO Empty (Read Only) |
| This bit indicates TX FIFO empty or not. | ||
| 0 = TX FIFO is not empty. | ||
| 1 = TX FIFO is empty. | ||
| Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. | ||
| It will be cleared when writing data into THR (TX FIFO not empty). | ||
| [23] | TXFULL | Transmitter FIFO Full (Read Only) |
| This bit indicates TX FIFO full or not. | ||
| 0 = TX FIFO is not full. | ||
| 1 = TX FIFO is full. | ||
| Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. | ||
| [24] | TXOVIF | TX Overflow Error Interrupt Flag |
| If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to | ||
| logic 1. | ||
| 0 = TX FIFO did not overflow. | ||
| 1 = TX FIFO overflowed. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [28] | TXEMPTYF | Transmitter Empty Flag (Read Only) |
| This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. | ||
| 0 = TX FIFO is not empty. | ||
| 1 = TX FIFO is empty. | ||
| Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. |
Definition at line 10969 of file Mini58Series.h.
| __IO uint32_t UART_T::FUNSEL |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | FUN_SEL | Function Selection |
| 00 = UART function mode. | ||
| 01 = Reserved. | ||
| 10 = IrDA function mode. (Only Available in UART0) | ||
| 11 = RS-485 function mode. (Only Available in UART0) |
Definition at line 11156 of file Mini58Series.h.
| __IO uint32_t PWM_T::IFA |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | IFAEN | Interrupt Accumulation Function Enable Bit |
| 0 = Interrupt accumulation function Disabled. | ||
| 1 = Interrupt accumulation function Enabled. | ||
| [7:4] | IFCNT | Interrupt Accumulation Counter |
| When IFAEN is set, IFCNT will decrease when every ZIFn flag is set and when IFCNT reach to zero, the PWMn interrupt will occurred and IFCNT will reload itself. |
Definition at line 7822 of file Mini58Series.h.
| __IO uint32_t GPIO_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FLIEN0 | Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [1] | FLIEN1 | Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [2] | FLIEN2 | Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [3] | FLIEN3 | Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [4] | FLIEN4 | Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [5] | FLIEN5 | Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [6] | FLIEN6 | Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [7] | FLIEN7 | Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1function | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [16] | RHIEN0 | Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [17] | RHIEN1 | Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [18] | RHIEN2 | Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [19] | RHIEN3 | Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [20] | RHIEN4 | Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [21] | RHIEN5 | Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [22] | RHIEN6 | Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [23] | RHIEN7 | Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1: | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. |
Definition at line 2701 of file Mini58Series.h.
| __IO uint32_t PWM_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | ZIEN0 | PWM Zero Point Interrupt Enable Bit |
| 0 = PWM0_CHn zero point interrupt Disabled. | ||
| 1 = PWM0_CHn zero point interrupt Enabled. | ||
| [5:0] | ZIEN1 | PWM Zero Point Interrupt Enable Bit |
| 0 = PWM0_CHn zero point interrupt Disabled. | ||
| 1 = PWM0_CHn zero point interrupt Enabled. | ||
| [5:0] | ZIEN2 | PWM Zero Point Interrupt Enable Bit |
| 0 = PWM0_CHn zero point interrupt Disabled. | ||
| 1 = PWM0_CHn zero point interrupt Enabled. | ||
| [5:0] | ZIEN3 | PWM Zero Point Interrupt Enable Bit |
| 0 = PWM0_CHn zero point interrupt Disabled. | ||
| 1 = PWM0_CHn zero point interrupt Enabled. | ||
| [5:0] | ZIEN4 | PWM Zero Point Interrupt Enable Bit |
| 0 = PWM0_CHn zero point interrupt Disabled. | ||
| 1 = PWM0_CHn zero point interrupt Enabled. | ||
| [5:0] | ZIEN5 | PWM Zero Point Interrupt Enable Bit |
| 0 = PWM0_CHn zero point interrupt Disabled. | ||
| 1 = PWM0_CHn zero point interrupt Enabled. | ||
| [13:8] | CMPDIEN0 | PWM Compare Down Interrupt Enable Bit |
| 0 = PWM0_CHn compare down interrupt Disabled. | ||
| 1 = PWM0_CHn compare down interrupt Enabled. | ||
| [13:8] | CMPDIEN1 | PWM Compare Down Interrupt Enable Bit |
| 0 = PWM0_CHn compare down interrupt Disabled. | ||
| 1 = PWM0_CHn compare down interrupt Enabled. | ||
| [13:8] | CMPDIEN2 | PWM Compare Down Interrupt Enable Bit |
| 0 = PWM0_CHn compare down interrupt Disabled. | ||
| 1 = PWM0_CHn compare down interrupt Enabled. | ||
| [13:8] | CMPDIEN3 | PWM Compare Down Interrupt Enable Bit |
| 0 = PWM0_CHn compare down interrupt Disabled. | ||
| 1 = PWM0_CHn compare down interrupt Enabled. | ||
| [13:8] | CMPDIEN4 | PWM Compare Down Interrupt Enable Bit |
| 0 = PWM0_CHn compare down interrupt Disabled. | ||
| 1 = PWM0_CHn compare down interrupt Enabled. | ||
| [13:8] | CMPDIEN5 | PWM Compare Down Interrupt Enable Bit |
| 0 = PWM0_CHn compare down interrupt Disabled. | ||
| 1 = PWM0_CHn compare down interrupt Enabled. | ||
| [16] | BRKIEN | Fault Brake0 And Fault Brake1 Interrupt Enable Bit |
| 0 = BRKIF0 and BRKIF1 trigger PWM interrupt Disabled. | ||
| 1 = BRKIF0 and BRKIF1 trigger PWM interrupt Enabled. | ||
| [17] | PINTTYPE | PWM Interrupt Type Selection |
| 0 = ZIFn will be set if PWM counter underflows. | ||
| 1 = ZIFn will be set if PWM counter matches PERIODn register. | ||
| Note: This bit is effective when PWM is in center-aligned type only. | ||
| [23:18] | PIEN0 | PWM Period Interrupt Enable Bit |
| 0 = PWM0_CHn period interrupt Disabled. | ||
| 1 = PWM0_CHn period interrupt Enabled. | ||
| [23:18] | PIEN1 | PWM Period Interrupt Enable Bit |
| 0 = PWM0_CHn period interrupt Disabled. | ||
| 1 = PWM0_CHn period interrupt Enabled. | ||
| [23:18] | PIEN2 | PWM Period Interrupt Enable Bit |
| 0 = PWM0_CHn period interrupt Disabled. | ||
| 1 = PWM0_CHn period interrupt Enabled. | ||
| [23:18] | PIEN3 | PWM Period Interrupt Enable Bit |
| 0 = PWM0_CHn period interrupt Disabled. | ||
| 1 = PWM0_CHn period interrupt Enabled. | ||
| [23:18] | PIEN4 | PWM Period Interrupt Enable Bit |
| 0 = PWM0_CHn period interrupt Disabled. | ||
| 1 = PWM0_CHn period interrupt Enabled. | ||
| [23:18] | PIEN5 | PWM Period Interrupt Enable Bit |
| 0 = PWM0_CHn period interrupt Disabled. | ||
| 1 = PWM0_CHn period interrupt Enabled. | ||
| [29:24] | CMPUIEN0 | PWM Compare Up Interrupt Enable Bit |
| 0 = PWM0_CHn compare up interrupt Disabled. | ||
| 1 = PWM0_CHn compare up interrupt Enabled. | ||
| [29:24] | CMPUIEN1 | PWM Compare Up Interrupt Enable Bit |
| 0 = PWM0_CHn compare up interrupt Disabled. | ||
| 1 = PWM0_CHn compare up interrupt Enabled. | ||
| [29:24] | CMPUIEN2 | PWM Compare Up Interrupt Enable Bit |
| 0 = PWM0_CHn compare up interrupt Disabled. | ||
| 1 = PWM0_CHn compare up interrupt Enabled. | ||
| [29:24] | CMPUIEN3 | PWM Compare Up Interrupt Enable Bit |
| 0 = PWM0_CHn compare up interrupt Disabled. | ||
| 1 = PWM0_CHn compare up interrupt Enabled. | ||
| [29:24] | CMPUIEN4 | PWM Compare Up Interrupt Enable Bit |
| 0 = PWM0_CHn compare up interrupt Disabled. | ||
| 1 = PWM0_CHn compare up interrupt Enabled. | ||
| [29:24] | CMPUIEN5 | PWM Compare Up Interrupt Enable Bit |
| 0 = PWM0_CHn compare up interrupt Disabled. | ||
| 1 = PWM0_CHn compare up interrupt Enabled. |
Definition at line 7076 of file Mini58Series.h.
| __IO uint32_t UART_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDAIEN | Receive Data Available Interrupt Enable Bit |
| 0 = RDAINT Masked off. | ||
| 1 = RDAINT Enabled. | ||
| [1] | THREIEN | Transmit Holding Register Empty Interrupt Enable Bit |
| 0 = THREINT Masked off. | ||
| 1 = THREINT Enabled. | ||
| [2] | RLSIEN | Receive Line Status Interrupt Enable Bit |
| 0 = RLSINT Masked off. | ||
| 1 = RLSINT Enabled. | ||
| [3] | MODEMIEN | Modem Status Interrupt Enable Bit |
| 0 = MODEMINT Masked off. | ||
| 1 = MODEMINT Enabled. | ||
| [4] | RXTOIEN | RX Time-out Interrupt Enable Bit |
| 0 = RXTOINT Masked off. | ||
| 1 = RXTOINT Enabled. | ||
| [5] | BUFERRIEN | Buffer Error Interrupt Enable Bit |
| 0 = Buffer Error Interrupt Masked Disabled. | ||
| 1 = Buffer Error Interrupt Masked Enabled. | ||
| [9] | WKCTSIEN | Wake-up CPU Function Interrupt Enable Bit (Only Available In UART0) |
| 0 = UART wake-up function Disabled. | ||
| 1 = UART Wake-up function Enabled. | ||
| Note: When the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode. | ||
| [11] | TOCNTEN | Time-out Counter Enable Bit |
| 0 = Time-out counter Disabled. | ||
| 1 = Time-out counter Enabled. | ||
| [12] | ATORTSEN | RTS Auto Flow Control Enable Bit (Only Available In UART0) |
| 0 = RTS auto flow control Disabled. | ||
| 1 = RTS auto flow control Enabled. | ||
| Note: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO [19:16]), the UART will de-assert RTS signal. | ||
| [13] | ATOCTSEN | CTS Auto Flow Control Enable Bit (Only Available In UART0) |
| 0 = CTS auto flow control Disabled. | ||
| 1 = CTS auto flow control Enabled. | ||
| Note: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). |
Definition at line 10762 of file Mini58Series.h.
| __IO uint32_t GPIO_T::INTSRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | INTSRC0 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [1] | INTSRC1 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [2] | INTSRC2 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [3] | INTSRC3 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [4] | INTSRC4 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [5] | INTSRC5 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [6] | INTSRC6 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [7] | INTSRC7 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [8] | INTSRC8 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [9] | INTSRC9 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [10] | INTSRC10 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [11] | INTSRC11 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [12] | INTSRC12 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [13] | INTSRC13 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [14] | INTSRC14 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [15] | INTSRC15 | Port 0-5 Pin[N] Interrupt Source Flag |
| Write Operation: | ||
| 0 = No action. | ||
| 1 = Clear the corresponding pending interrupt. | ||
| Read Operation: | ||
| 0 = No interrupt at Px.n. | ||
| 1 = Px.n generates an interrupt. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. |
Definition at line 2935 of file Mini58Series.h.
| __IO uint32_t PWM_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | ZIF0 | PWM Zero Point Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches zero point. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [5:0] | ZIF1 | PWM Zero Point Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches zero point. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [5:0] | ZIF2 | PWM Zero Point Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches zero point. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [5:0] | ZIF3 | PWM Zero Point Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches zero point. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [5:0] | ZIF4 | PWM Zero Point Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches zero point. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [5:0] | ZIF5 | PWM Zero Point Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches zero point. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [13:8] | CMPDIF0 | PWM Compare Down Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [13:8] | CMPDIF1 | PWM Compare Down Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [13:8] | CMPDIF2 | PWM Compare Down Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [13:8] | CMPDIF3 | PWM Compare Down Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [13:8] | CMPDIF4 | PWM Compare Down Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [13:8] | CMPDIF5 | PWM Compare Down Interrupt Flag |
| Flag is set by hardware when PWMn counter down count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [16] | BRKIF0 | PWM Brake0 Flag |
| 0 = PWM Brake does not recognize a falling signal at BKP0. | ||
| 1 = When PWM Brake detects a falling signal at pin BKP0; this flag will be set to high. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [17] | BRKIF1 | PWM Brake1 Flag |
| 0 = PWM Brake does not recognize a falling signal at BKP1. | ||
| 1 = When PWM Brake detects a falling signal at pin BKP1; this flag will be set to high. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [23:18] | PIF0 | PWM Period Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter reaches PERIODn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [23:18] | PIF1 | PWM Period Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter reaches PERIODn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [23:18] | PIF2 | PWM Period Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter reaches PERIODn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [23:18] | PIF3 | PWM Period Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter reaches PERIODn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [23:18] | PIF4 | PWM Period Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter reaches PERIODn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [23:18] | PIF5 | PWM Period Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter reaches PERIODn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [29:24] | CMPUIF0 | PWM Compare Up Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter up count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [29:24] | CMPUIF1 | PWM Compare Up Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter up count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [29:24] | CMPUIF2 | PWM Compare Up Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter up count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [29:24] | CMPUIF3 | PWM Compare Up Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter up count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [29:24] | CMPUIF4 | PWM Compare Up Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter up count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [29:24] | CMPUIF5 | PWM Compare Up Interrupt Flag |
| Flag is set by hardware when PWM0_CHn counter up count reaches CMPn. | ||
| Note: This bit can be cleared by software writing 1. |
Definition at line 7166 of file Mini58Series.h.
| __IO uint32_t TIMER_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TIF | Timer Interrupt Flag |
| This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. | ||
| 0 = No effect. | ||
| 1 = CNT value matches the CMPDAT value. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [1] | TWKF | Timer Wake-up Flag |
| This bit indicates the interrupt wake-up flag status of timer. | ||
| 0 = Timer does not cause CPU wake-up. | ||
| 1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. | ||
| Note: This bit is cleared by writing 1 to it. |
Definition at line 10423 of file Mini58Series.h.
| __IO uint32_t UART_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDAIF | Receive Data Available Interrupt Flag (Read Only) |
| When the number of bytes in the RX FIFO equals the RFITL(UART_FIFO[7:4]) then the RDAIF(UART_INTSTS[0]) will be set. | ||
| If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generate. | ||
| 0 = No RDA interrupt flag is generated. | ||
| 1 = RDA interrupt flag is generated. | ||
| Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UART_FIFO[7:4])). | ||
| [1] | THREIF | Transmit Holding Register Empty Interrupt Flag (Read Only) |
| This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. | ||
| If THREIEN (UART_INTEN [1]) is enabled, the THRE interrupt will be generate. | ||
| 0 = No THRE interrupt flag is generated. | ||
| 1 = THRE interrupt flag is generated. | ||
| Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). | ||
| [2] | RLSIF | Receive Line Interrupt Flag (Read Only) |
| This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). | ||
| If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generate. | ||
| 0 = No RLS interrupt flag is generated. | ||
| 1 = RLS interrupt flag is generated. | ||
| Note1: In RS-485 function mode, this field is set including "receiver detects and receives address byte character (bit 9 = 1) bit". | ||
| At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. | ||
| (Only Available in UART0). | ||
| Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. | ||
| (Only Available in UART0). | ||
| [3] | MODEMIF | MODEM Interrupt Flag (Read Only) (Only Available In UART0) |
| This bit is set when the CTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). | ||
| If MODEMIEN (UART_INTEN[3]) is enabled, the Modem interrupt will be generate. | ||
| 0 = No Modem interrupt flag is generated. | ||
| 1 = Modem interrupt flag is generated. | ||
| Note: This bit is read only and reset to 0 when bit CTSDETF (UART_MODEMSTS[0]) is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0]). | ||
| [4] | RXTOIF | Time-out Interrupt Flag (Read Only) |
| This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UARTTOUT[7:0]). | ||
| If RXTOIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generate. | ||
| 0 = No Time-out interrupt flag is generated. | ||
| 1 = Time-out interrupt flag is generated. | ||
| Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. | ||
| [5] | BUFERRIF | Buffer Error Interrupt Flag (Read Only) |
| This bit is set when the TX/RX FIFO overflow flag (TXOVIF (UART_FIFOSTS[24]) or RXOVIF(UART_FIFOSTS[0])) is set. | ||
| When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. | ||
| If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generate. | ||
| 0 = No buffer error interrupt flag is generated. | ||
| 1 = Buffer error interrupt flag is generated. | ||
| Note: This bit is read only and reset to 0 when all bits of TXOVIF (UART_FIFOSTS[24]) and RXOVIF (UART_FIFOSTS[0]) are cleared. | ||
| [8] | RDAINT | Receive Data Available Interrupt Indicator (Read Only) |
| This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. | ||
| 0 = No RDA interrupt is generated. | ||
| 1 = RDA interrupt is generated. | ||
| [9] | THREINT | Transmit Holding Register Empty Interrupt Indicator (Read Only) |
| This bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1. | ||
| 0 = No THRE interrupt is generated. | ||
| 1 = THRE interrupt is generated. | ||
| [10] | RLSINT | Receive Line Status Interrupt (Read Only) |
| This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1. | ||
| 0 = No RLS interrupt is generated. | ||
| 1 = RLS interrupt is generated. | ||
| [11] | MODEMINT | MODEM Status Interrupt Indicator (Read Only) |
| This bit is set if MODEMIEN (UART_INTEN[3]) and MODENIF (UART_INTSTS[3]) are both set to 1. | ||
| 0 = No Modem interrupt is generated. | ||
| 1 = Modem interrupt is generated. | ||
| [12] | RXTOINT | Time-out Interrupt Indicator (Read Only) |
| This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1. | ||
| 0 = No Time-out interrupt is generated. | ||
| 1 = Time-out interrupt is generated. | ||
| [13] | BUFERRINT | Buffer Error Interrupt Indicator (Read Only) |
| This bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_INTSTS[5]) are both set to 1. | ||
| 0 = No buffer error interrupt is generated. | ||
| 1 = buffer error interrupt is generated. | ||
| [16] | CTSWKIF | NCTS Wake-up Interrupt Flag (Read Only) (Only Available In UART0) |
| 0 = Chip stays in power-down state. | ||
| 1 = Chip wake-up from power-down state by nCTS wake-up. | ||
| Note1: If WKCTSIEN (UART_IER[9])is enabled, the wake-up interrupt is generated. | ||
| Note2: This bit is read only, but can be cleared by writing '1' to it. |
Definition at line 11049 of file Mini58Series.h.
| __IO uint32_t GPIO_T::INTTYPE |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TYPE0 | Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [1] | TYPE1 | Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [2] | TYPE2 | Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [3] | TYPE3 | Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [4] | TYPE4 | Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [5] | TYPE5 | Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [6] | TYPE6 | Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [7] | TYPE7 | Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control |
| TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. | ||
| If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. | ||
| If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). | ||
| If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid only for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignore. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. |
Definition at line 2451 of file Mini58Series.h.
| __IO uint32_t SYS_T::IPRST0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CHIPRST | CHIP One-shot Reset (Write Protect) |
| Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. | ||
| The CHIPRST is the same as the POR reset, all the chip controllers is reset and the chip settings from flash are also reload. | ||
| 0 = Chip normal operation. | ||
| 1 = CHIP one-shot reset. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [1] | CPURST | Processor Core One-shot Reset (Write Protect) |
| Setting this bit will only reset the processor core and Flash Memory Controller (FMC), and this bit will automatically return to 0 after the 2 clock cycles. | ||
| 0 = Processor core normal operation. | ||
| 1 = Processor core one-shot reset. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
Definition at line 9545 of file Mini58Series.h.
| __IO uint32_t SYS_T::IPRST1 |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | GPIORST | GPIO (P0~P5) Controller Reset |
| 0 = GPIO controller normal operation. | ||
| 1 = GPIO controller reset. | ||
| [2] | TMR0RST | Timer0 Controller Reset |
| 0 = Timer0 controller normal operation. | ||
| 1 = Timer0 controller reset. | ||
| [3] | TMR1RST | Timer1 Controller Reset |
| 0 = Timer1 controller normal operation. | ||
| 1 = Timer1 controller reset. | ||
| [8] | I2C0RST | I2C0 Controller Reset |
| 0 = I2C0 controller normal operation. | ||
| 1 = I2C0 controller reset. | ||
| [9] | I2C1RST | I2C1 Controller Reset |
| 0 = I2C1 controller normal operation. | ||
| 1 = I2C1 controller reset. | ||
| [12] | SPI0RST | SPI0 Controller Reset |
| 0 = SPI controller normal operation. | ||
| 1 = SPI controller reset. | ||
| [16] | UART0RST | UART0 Controller Reset |
| 0 = UART0 controller normal operation. | ||
| 1 = UART0 controller reset. | ||
| [17] | UART1RST | UART1 Controller Reset |
| 0 = UART1 controller normal operation. | ||
| 1 = UART1 controller reset. | ||
| [20] | PWM0RST | PWM0 Controller Reset |
| 0 = PWM0 controller normal operation. | ||
| 1 = PWM0 controller reset. | ||
| [22] | ACMPRST | ACMP Controller Reset |
| 0 = ACMP controller normal operation. | ||
| 1 = ACMP controller reset. | ||
| [28] | ADCRST | ADC Controller Reset |
| 0 = ADC controller normal operation. | ||
| 1 = ADC controller reset. |
Definition at line 9588 of file Mini58Series.h.
| __IO uint32_t SYS_T::IRCTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FREQSEL | Trim Frequency Select Bit |
| This bit is to enable the HIRC auto trim. | ||
| When setting this bit to 1, the HIRC auto trim function will trim HIRC to 22.1184 MHz automatically based on the LXT reference clock. | ||
| During auto trim operation, if LXT clock error is detected or trim retry limitation count reached, this field will be cleared to 0 automatically. | ||
| 0 = HIRC auto trim function Disabled. | ||
| 1 = HIRC auto trim function Enabled and HIRC trimmed to 22.1184 MHz. | ||
| [5:4] | LOOPSEL | Trim Calculation Loop |
| This field defines trim value calculation based on the number of LXT clock. | ||
| For example, if LOOPSEL is set as "00", auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT clocks. | ||
| This field also defines how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC is locked. | ||
| Once the HIRC is locked, the internal trim value update counter will be reset. | ||
| If the trim value update counter reaches this limitation value and frequency of HIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 0. | ||
| 00 = Trim value calculation is based on average difference in 4 LXT clock and trim retry count limitation is 64. | ||
| 01 = Trim value calculation is based on average difference in 8 LXT clock and trim retry count limitation is 128. | ||
| 10 = Trim value calculation is based on average difference in 16 LXT clock and trim retry count limitation is 256. | ||
| 11 = Trim value calculation is based on average difference in 32 LXT clock and trim retry count limitation is 512. |
Definition at line 9974 of file Mini58Series.h.
| __IO uint32_t SYS_T::IRCTIEN |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | TFAILIEN | Trim Failure Interrupt Enable Bit |
| This bit controls if an interrupt will be triggered while HIRC trim value update limitation count is reached and HIRC frequency is still not locked on target frequency set by FREQSEL (SYS_IRCTCTL[1:0]). | ||
| If this bit is high and TFAILIF (SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count is reached. | ||
| 0 = TFAILIF (SYS_IRCTISTS[1]) status Disabled to trigger an interrupt to CPU. | ||
| 1 = TFAILIF (SYS_IRCTISTS[1]) status Enabled to trigger an interrupt to CPU. | ||
| [2] | CLKEIEN | LXT Clock Error Interrupt Enable Bit |
| This bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation. | ||
| If this bit is high, and CLKERRIF (SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the LXT clock frequency is inaccurate. | ||
| 0 = CLKERRIF (SYS_IRCTISTS[2]) status Disabled to trigger an interrupt to CPU. | ||
| 1 = CLKERRIF (SYS_IRCTISTS[2]) status Enabled to trigger an interrupt to CPU. |
Definition at line 9994 of file Mini58Series.h.
| __IO uint32_t SYS_T::IRCTISTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FREQLOCK | HIRC Frequency Lock Status |
| This bit indicates the HIRC frequency locked in 22.1184 MHz. | ||
| This is a read only status bit and doesn't trigger any interrupt. | ||
| [1] | TFAILIF | Trim Failure Interrupt Status |
| This bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. | ||
| Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRCTCTL[1:0]) will be cleared to 0 by hardware automatically. | ||
| If this bit is set and TFAILIEN (SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. | ||
| Software can write 1 to clear this bit to . | ||
| 0 = Trim value update limitation count is not reached. | ||
| 1 = Trim value update limitation count is reached and HIRC frequency is still not locked. | ||
| [2] | CLKERRIF | LXT Clock Error Interrupt Status |
| This bit indicates that LXT clock frequency is inaccuracy. | ||
| Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRCTCTL[0]) will be cleared to 0 by hardware automatically. | ||
| If this bit is set and CLKEIEN (SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy. | ||
| Software can write 1 to clear this bit to . | ||
| 0 = LXT clock frequency is accuracy. | ||
| 1 = LXT clock frequency is inaccuracy. |
Definition at line 10021 of file Mini58Series.h.
| __IO uint32_t UART_T::IRDA |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | TXEN | IrDA Receiver/Transmitter Selection Enable Bit |
| 0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) | ||
| 1 = IrDA Transmitter Enabled and Receiver Disabled. | ||
| [5] | TXINV | IrDA Inverse Transmitting Output Signal |
| 0 = None inverse transmitting signal. (Default) | ||
| 1 = Inverse transmitting output signal. | ||
| [6] | RXINV | IrDA Inverse Receive Input Signal |
| 0 = None inverse receiving input signal. | ||
| 1 = Inverse receiving input signal. (Default) |
Definition at line 11111 of file Mini58Series.h.
| __IO uint32_t INTR_T::IRQ |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | MCU_IRQ | MCU IRQ Source Bits |
| The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. | ||
| There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mod. | ||
| The MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0. | ||
| When the MCU_IRQ[n] is 0, setting MCU_IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n]. | ||
| When the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting MCU_IRQ[n] 0 has no effect. |
Definition at line 5278 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ0_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BOD_INT | IRQ0 Source Identity |
| 0 = IRQ0 source is not from BOD interrupt (BOD_INT). | ||
| 1 = IRQ0 source is from BOD interrupt (BOD_INT). |
Definition at line 4970 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ12_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | UART0_INT | IRQ12 Source Identity |
| 0 = IRQ12 source is not from UART0 interrupt (UART0_INT). | ||
| 1 = IRQ12 source is from UART0 interrupt (UART0_INT). |
Definition at line 5116 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ13_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | UART1_INT | IRQ13 Source Identity |