cleanup on connection methods + documentation. custom DBAPI arguments specified in query string, ‘connect_args’ argument to ‘create_engine’, or custom creation function via ‘creator’ function to ‘create_engine’.(link)
added “recycle” argument to Pool, is “pool_recycle” on create_engine, defaults to 3600 seconds; connections after this age will be closed and replaced with a new one, to handle db’s that automatically close stale connections(link)
changed “invalidate” semantics with pooled connection; will instruct the underlying connection record to reconnect the next time its called. “invalidate” will also automatically be called if any error is thrown in the underlying call to connection.cursor(). this will hopefully allow the connection pool to reconnect to a database that had been stopped and started without restarting the connecting application(link)
eesh ! the tutorial doctest was broken for quite some time.(link)
add_property() method on mapper does a “compile all mappers” step in case the given property references a non-compiled mapper (as it did in the case of the tutorial !)(link)
check for pg sequence already existing before create(link)
if a contextual session is established via MapperExtension.get_session (as it is using the sessioncontext plugin, etc), a lazy load operation will use that session by default if the parent object is not persistent with a session already.(link)
lazy loads will not fire off for an object that does not have a database identity (why? see http://www.sqlalchemy.org/trac/wiki/WhyDontForeignKeysLoadData)(link)
unit-of-work does a better check for “orphaned” objects that are part of a “delete-orphan” cascade, for certain conditions where the parent isnt available to cascade from.(link)
mappers can tell if one of their objects is an “orphan” based on interactions with the attribute package. this check is based on a status flag maintained for each relationship when objects are attached and detached from each other.(link)
it is now invalid to declare a self-referential relationship with “delete-orphan” (as the abovementioned check would make them impossible to save)(link)
improved the check for objects being part of a session when the unit of work seeks to flush() them as part of a relationship..(link)
statement execution supports using the same BindParam object more than once in an expression; simplified handling of positional parameters. nice job by Bill Noon figuring out the basic idea.(link)
postgres reflection moved to use pg_schema tables, can be overridden with use_information_schema=True argument to create_engine.(link)
added case_sensitive argument to MetaData, Table, Column, determines itself automatically based on if a parent schemaitem has a non-None setting for the flag, or if not, then whether the identifier name is all lower case or not. when set to True, quoting is applied to identifiers with mixed or uppercase identifiers. quoting is also applied automatically in all cases to identifiers that are known to be reserved words or contain other non-standard characters. various database dialects can override all of this behavior, but currently they are all using the default behavior. tested with postgres, mysql, sqlite, oracle. needs more testing with firebird, ms-sql. part of the ongoing work with(link)
unit tests updated to run without any pysqlite installed; pool test uses a mock DBAPI(link)
urls support escaped characters in passwords(link)
added limit/offset to UNION queries (though not yet in oracle)(link)
added “timezone=True” flag to DateTime and Time types. postgres so far will convert this to “TIME[STAMP] (WITH|WITHOUT) TIME ZONE”, so that control over timezone presence is more controllable (psycopg2 returns datetimes with tzinfo’s if available, which can create confusion against datetimes that dont).(link)
fix to using query.count() with distinct, **kwargs with SelectResults count()(link)
deregister Table from MetaData when autoload fails;(link)
import of py2.5s sqlite3(link)
unicode fix for startswith()/endswith()(link)
quoting facilities set up so that database-specific quoting can be turned on for individual table, schema, and column identifiers when used in all queries/creates/drops. Enabled via “quote=True” in Table or Column, as well as “quote_schema=True” in Table. Thanks to Aaron Spike for his excellent efforts.(link)
assignmapper was setting is_primary=True, causing all sorts of mayhem by not raising an error when redundant mappers were set up, fixed(link)
added allow_null_pks option to Mapper, allows rows where some primary key columns are null (i.e. when mapping to outer joins etc)(link)
modifcation to unitofwork to not maintain ordering within the “new” list or within the UOWTask “objects” list; instead, new objects are tagged with an ordering identifier as they are registered as new with the session, and the INSERT statements are then sorted within the mapper save_obj. the INSERT ordering has basically been pushed all the way to the end of the flush cycle. that way the various sorts and organizations occuring within UOWTask (particularly the circular task sort) dont have to worry about maintaining order (which they werent anyway)(link)
fixed reflection of foreign keys to autoload the referenced table if it was not loaded already(link)
custom primary/secondary join conditions in a relation will be propagated to backrefs by default. specifying a backref() will override this behavior.(link)
better check for ambiguous join conditions in sql.Join; propagates to a better error message in PropertyLoader (i.e. relation()/backref()) for when the join condition can’t be reasonably determined.(link)
sqlite creates ForeignKeyConstraint objects properly upon table reflection.(link)
adjustments to pool stemming from changes made for. overflow counter should only be decremented if the connection actually succeeded. added a test script to attempt testing this.(link)
fixed mysql reflection of default values to be PassiveDefault(link)
added reflected ‘tinyint’, ‘mediumint’ type to MS-SQL.(link)
SingletonThreadPool has a size and does a cleanup pass, so that only a given number of thread-local connections stay around (needed for sqlite applications that dispose of threads en masse)(link)
fixed small pickle bug(s) with lazy loaders(link)
fixed possible error in mysql reflection where certain versions return an array instead of string for SHOW CREATE TABLE call(link)
fix to lazy loads when mapping to joins(link)
all create()/drop() calls have a keyword argument of “connectable”. “engine” is deprecated.(link)
fixed ms-sql connect() to work with adodbapi(link)
added “nowait” flag to Select()(link)
inheritance check uses issubclass() instead of direct __mro__ check to make sure class A inherits from B, allowing mapper inheritance to more flexibly correspond to class inheritance(link)
SelectResults will use a subselect, when calling an aggregate (i.e. max, min, etc.) on a SelectResults that has an ORDER BY clause(link)
fixes to types so that database-specific types more easily used; fixes to mysql text types to work with this methodology(link)
some fixes to sqlite date type organization(link)
added MSTinyInteger to MS-SQL(link)
big overhaul to schema to allow truly composite primary and foreign key constraints, via new ForeignKeyConstraint and PrimaryKeyConstraint objects. Existing methods of primary/foreign key creation have not been changed but use these new objects behind the scenes. table creation and reflection is now more table oriented rather than column oriented.(link)
overhaul to MapperExtension calling scheme, wasnt working very well previously(link)
tweaks to ActiveMapper, supports self-referential relationships(link)
slight rearrangement to objectstore (in activemapper/threadlocal) so that the SessionContext is referenced by ‘.context’ instead of subclassed directly.(link)
activemapper will use threadlocal’s objectstore if the mod is activated when activemapper is imported(link)
small fix to URL regexp to allow filenames with ‘@’ in them(link)
fixes to Session expunge/update/etc...needs more cleanup.(link)
select_table mappers still werent always compiling(link)
fixed up Boolean datatype(link)
added count()/count_by() to list of methods proxied by assignmapper; this also adds them to activemapper(link)
connection exceptions wrapped in DBAPIError(link)
ActiveMapper now supports autoloading column definitions from the database if you supply a __autoload__ = True attribute in your mapping inner-class. Currently this does not support reflecting any relationships.(link)
deferred column load could screw up the connection status in a flush() under some circumstances, this was fixed(link)
expunge() was not working with cascade, fixed.(link)
potential endless loop in cascading operations fixed.(link)
added “synonym()” function, applied to properties to have a propname the same as another, for the purposes of overriding props and allowing the original propname to be accessible in select_by().(link)
fix to typing in clause construction which specifically helps type issues with polymorphic_union (CAST/ColumnClause propagates its type to proxy columns)(link)
mapper compilation work ongoing, someday it’ll work....moved around the initialization of MapperProperty objects to be after all mappers are created to better handle circular compilations. do_init() method is called on all properties now which are more aware of their “inherited” status if so.(link)
eager loads explicitly disallowed on self-referential relationships, or relationships to an inheriting mapper (which is also self-referential)(link)
reduced bind param size in query._get to appease the picky oracle(link)
added ‘checkfirst’ argument to table.create()/table.drop(), as well as table.exists()(link)
some other ongoing fixes to inheritance(link)
attribute/backref/orphan/history-tracking tweaks as usual...(link)
fixed endless loop bug in select_by(), if the traversal hit two mappers that referenced each other(link)
upgraded all unittests to insert ‘./lib/’ into sys.path, working around new setuptools PYTHONPATH-killing behavior(link)
further fixes with attributes/dependencies/etc....(link)
improved error handling for when DynamicMetaData is not connected(link)
MS-SQL support largely working (tested with pymssql)(link)
ordering of UPDATE and DELETE statements within groups is now in order of primary key values, for more deterministic ordering(link)
after_insert/delete/update mapper extensions now called per object, not per-object-per-table(link)
further fixes/refactorings to mapper compilation(link)
try/except when the mapper sets init.__name__ on a mapped class, supports python 2.3(link)
fixed bug where threadlocal engine would still autocommit despite a transaction in progress(link)
lazy load and deferred load operations require the parent object to be in a Session to do the operation; whereas before the operation would just return a blank list or None, it now raises an exception.(link)
Session.update() is slightly more lenient if the session to which the given object was formerly attached to was garbage collected; otherwise still requires you explicitly remove the instance from the previous Session.(link)
fixes to mapper compilation, checking for more error conditions(link)
small fix to eager loading combined with ordering/limit/offset(link)
utterly remarkable: added a single space between ‘CREATE TABLE’ and ‘(<the rest of it>’ since thats how MySQL indicates a non- reserved word tablename.....(link)
more fixes to inheritance, related to many-to-many relations properly saving(link)
fixed bug when specifying explicit module to mysql dialect(link)
when QueuePool times out it raises a TimeoutError instead of erroneously making another connection(link)
Queue.Queue usage in pool has been replaced with a locally modified version (works in py2.3/2.4!) that uses a threading.RLock for a mutex. this is to fix a reported case where a ConnectionFairy’s __del__() method got called within the Queue’s get() method, which then returns its connection to the Queue via the put() method, causing a reentrant hang unless threading.RLock is used.(link)
postgres will not place SERIAL keyword on a primary key column if it has a foreign key constraint(link)
cursor() method on ConnectionFairy allows db-specific extension arguments to be propagated(link)
lazy load bind params properly propagate column type(link)
new MySQL types: MSEnum, MSTinyText, MSMediumText, MSLongText, etc. more support for MS-specific length/precision params in numeric types patch courtesy Mike Bernson(link)
some fixes to connection pool invalidate()(link)
overhaul to mapper compilation to be deferred. this allows mappers to be constructed in any order, and their relationships to each other are compiled when the mappers are first used.(link)
fixed a pretty big speed bottleneck in cascading behavior particularly when backrefs were in use(link)
the attribute instrumentation module has been completely rewritten; its now a large degree simpler and clearer, slightly faster. the “history” of an attribute is no longer micromanaged with each change and is instead part of a “CommittedState” object created when the instance is first loaded. HistoryArraySet is gone, the behavior of list attributes is now more open ended (i.e. theyre not sets anymore).(link)
py2.4 “set” construct used internally, falls back to sets.Set when “set” not available/ordering is needed.(link)
fix to transaction control, so that repeated rollback() calls dont fail (was failing pretty badly when flush() would raise an exception in a larger try/except transaction block)(link)
“foreignkey” argument to relation() can also be a list. fixed auto-foreignkey detection(link)
fixed bug where tables with schema names werent getting indexed in the MetaData object properly(link)
fixed bug where Column with redefined “key” property wasnt getting type conversion happening in the ResultProxy(link)
fixed ‘port’ attribute of URL to be an integer if present(link)
fixed old bug where if a many-to-many table mapped as “secondary” had extra columns, delete operations didnt work(link)
bugfixes for mapping against UNION queries(link)
fixed incorrect exception class thrown when no DB driver present(link)
added NonExistentTable exception thrown when reflecting a table that doesnt exist(link)
small fix to ActiveMapper regarding one-to-one backrefs, other refactorings(link)
overridden constructor in mapped classes gets __name__ and __doc__ from the original class(link)
fixed small bug in selectresult.py regarding mapper extension(link)
small tweak to cascade_mappers, not very strongly supported function at the moment(link)
some fixes to between(), column.between() to propagate typing information better(link)
if an object fails to be constructed, is not added to the session(link)
CAST function has been made into its own clause object with its own compilation function in ansicompiler; allows MySQL to silently ignore most CAST calls since MySQL seems to only support the standard CAST syntax with Date types. MySQL-compatible CAST support for strings, ints, etc. a TODO(link)
big improvements to polymorphic inheritance behavior, enabling it to work with adjacency list table structures(link)
major fixes and refactorings to inheritance relationships overall, more unit tests(link)
fixed “echo_pool” flag on create_engine()(link)
fix to docs, removed incorrect info that close() is unsafe to use with threadlocal strategy (its totally safe !)(link)
create_engine() can take URLs as string or unicode(link)
firebird support partially completed; thanks to James Ralston and Brad Clements for their efforts.(link)
Oracle url translation was broken, fixed, will feed host/port/sid into cx_oracle makedsn() if ‘database’ field is present, else uses straight TNS name from the ‘host’ field(link)
fix to using unicode criterion for query.get()/query.load()(link)
count() function on selectables now uses table primary key or first column instead of “1” for criterion, also uses label “rowcount” instead of “count”.(link)
got rudimental “mapping to multiple tables” functionality cleaned up, more correctly documented(link)
restored global_connect() function, attaches to a DynamicMetaData instance called “default_metadata”. leaving MetaData arg to Table out will use the default metadata.(link)
fixes to session cascade behavior, entity_name propigation(link)
reorganized unittests into subdirectories(link)
more fixes to threadlocal connection nesting patterns(link)
“pool” argument to create_engine() properly propagates(link)
fixes to URL, raises exception if not parsed, does not pass blank fields along to the DB connect string (a string such as user:host@/db was breaking on postgres)(link)
small fixes to Mapper when it inserts and tries to get new primary key values back(link)
rewrote half of TLEngine, the ComposedSQLEngine used with ‘strategy=”threadlocal”’. it now properly implements engine.begin()/ engine.commit(), which nest fully with connection.begin()/trans.commit(). added about six unittests.(link)
major “duh” in pool.Pool, forgot to put back the WeakValueDictionary. unittest which was supposed to check for this was also silently missing it. fixed unittest to ensure that ConnectionFairy properly falls out of scope.(link)
placeholder dispose() method added to SingletonThreadPool, doesnt do anything yet(link)
rollback() is automatically called when an exception is raised, but only if theres no transaction in process (i.e. works more like autocommit).(link)
fixed exception raise in sqlite if no sqlite module present(link)
added extra example detail for association object doc(link)
Connection adds checks for already being closed(link)
overhaul to Engine system so that what was formerly the SQLEngine is now a ComposedSQLEngine which consists of a variety of components, including a Dialect, ConnectionProvider, etc. This impacted all the db modules as well as Session and Mapper.(link)
create_engine now takes only RFC-1738-style strings: driver://user:password@host:port/database(link)
total rewrite of connection-scoping methodology, Connection objects can now execute clause elements directly, added explicit “close” as well as support throughout Engine/ORM to handle closing properly, no longer relying upon __del__ internally to return connections to the pool.(link)
overhaul to Session interface and scoping. uses hibernate-style methods, including query(class), save(), save_or_update(), etc. no threadlocal scope is installed by default. Provides a binding interface to specific Engines and/or Connections so that underlying Schema objects do not need to be bound to an Engine. Added a basic SessionTransaction object that can simplistically aggregate transactions across multiple engines.(link)
overhaul to mapper’s dependency and “cascade” behavior; dependency logic factored out of properties.py into a separate module “dependency.py”. “cascade” behavior is now explicitly controllable, proper implementation of “delete”, “delete-orphan”, etc. dependency system can now determine at flush time if a child object has a parent or not so that it makes better decisions on how that child should be updated in the DB with regards to deletes.(link)
overhaul to Schema to build upon MetaData object instead of an Engine. Entire SQL/Schema system can be used with no Engines whatsoever, executed solely by an explicit Connection object. the “bound” methodlogy exists via the BoundMetaData for schema objects. ProxyEngine is generally not needed anymore and is replaced by DynamicMetaData.(link)
true polymorphic behavior implemented, fixes(link)
“oid” system has been totally moved into compile-time behavior; if they are used in an order_by where they are not available, the order_by doesnt get compiled, fixes(link)
overhaul to packaging; “mapping” is now “orm”, “objectstore” is now “session”, the old “objectstore” namespace gets loaded in via the “threadlocal” mod if used(link)
mods now called in via “import <modname>”. extensions favored over mods as mods are globally-monkeypatching(link)
fix to add_property so that it propagates properties to inheriting mappers(link)
backrefs create themselves against primary mapper of its originating property, priamry/secondary join arguments can be specified to override. helps their usage with polymorphic mappers(link)
“table exists” function has been implemented(link)
“create_all/drop_all” added to MetaData object(link)
improvements and fixes to topological sort algorithm, as well as more unit tests(link)
tutorial page added to docs which also can be run with a custom doctest runner to ensure its properly working. docs generally overhauled to deal with new code patterns(link)
many more fixes, refactorings.(link)
migration guide is available on the Wiki at http://www.sqlalchemy.org/trac/wiki/02Migration(link)


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EXtra Memory
Mike Kane and Bryan W. Lewis, September 2018
Kyle from Progressive at our R meetup earlier in 2018:
Some folks still like SAS because many methods can work on arbitrarily large data—maybe slowly, but they work.
R is fundamentally an in-memory computing environment.
Out of core computing in R...
- ff -Adler and Oehlschlägel
- bigmemory/bigalgebra (only matrices) -Kane and Emerson
- biglm/bigglm -Lumley
- iotools -Urbanek
- manual chunking Map/Reduce, foreach, etc.
- dplyr/sparklyr/... (external processing)
...and probably many others.
These specialized approaches require you to adapt to them.
The benefit is great performance is sometimes possible.
The problem is that things don't "just work." Many analyses can be tricky and very hard to implement! (Especially with packages using compiled code.)
Out of core getting interesting thanks to very fast, low-latency SSD and Optane storage media today.
Well, what about kernel swap to storage media?
- page-based, with attempts to map sequential pages together
- global in operation and can adversely affect entire OS
- works remarkably well in general
exm - a custom memory allocator that maps large allocations to files
- allocation- and page-fault based, always maintains sequential page order
- paging behavior tunable using madvise
- local operation specific to individual programs
(doesn't muck up rest of OS)
- dynamic allocations (swap is too, kinda)
- transparent to applications (like swap)
Started way back in 2005, sat for a long time. Dusting it off again.
Best together:
swap for handling lots of small allocations
exm for handling large allocations
swap + exm "just works"
exm simple command-line, C and R-package API:
- where to allocate exm_path()
- allocation threshold exm_threshold()
- control fork behavior (share/copy-on-write*/duplicate)
- tracemem()-like stuff...
*Copy in-core on write only for now.
Linux-only for now.
exm R --quiet
> library(exm)
> exm_threshold(1e8)
> system.time({x = matrix(runif(2000000 * 1000),
ncol=1000)})
user system elapsed
59.968 31.284 107.004
> object.size(x)
16000000200 bytes
> system.time({q = qr(x)})
user system elapsed
5403.564 3669.676 14393.603
Tested on my old home PC with a single AMD A10-7850K with 4 cores,
16 GB DDR4 RAM, NVME-attached 250GB Samsung SSD 850 EVO drive.
(*) figures from an HP ProLiant DL580 G7 w/1TB RAM and OMP_NUM_CORES=4.
Both using Ubuntu + OpenBLAS.
One more thing...this works for anything (not just R).
One more thing...this works for
anything (not just R).
One more even crazier thing...
distributed virtual shared memory with shim:
https://github.com/bwlewis/shim
(This project started as a way to define and allocate into virtual DSM over
Linux clusters using PVFS2.)


You are already familiar with the 80/20 rule. In the late 1800s an Italian economist discovered that 80% of the wealth in his country was owned by 20% of the people. More recently we find that the 80/20 rule applies in other areas of our lives. Professional service firms find that eighty percent of the revenue comes from twenty percent of the clients. Merchants find that eighty percent of sales comes from twenty percent of the products. Winners at the very top of any field tend to win by a large margin.
Another View of the 80/20 Rule
The Long Tail by Chris Anderson offers another way to look at the 80/20 rule. Our business example: A book store. The graph below shows book sales ranked by sales volume. Best-sellers are on the left side of the chart (in green) while slower sellers fill in the curve toward the right. Since shelf space is limited and expensive, the store only carries the most popular books along the left side of the chart. Smart application of the 80/20 rule, right? Maybe.
The Long Tail: Everything Else
High-volume books sell much more than other books. High-volume books (the short head) are the 20 percent that generate 80 percent of the revenue. The Long Tail is made up of everything else.
When a book store chooses to carry 20% of the available titles, how do they decide which 20% to carry? How do they predict the hits in advance?
Answer: They can’t. Sometimes a sure hit fizzles into a dud, while a “sleeper” rockets to the best-seller list. A similar problem is faced by movie distributors, retail stores, and other businesses. How do you profit from hits that you cannot predict?
The Long Tail in 1897
Sears, Roebuck & Co. is one of the oldest Long Tail companies in the USA. If you wanted to buy a product in late 1800’s America, you would visit the general store. Most Americans lived on farms at that time, so visiting the store meant riding into town. Product selection was limited to the items on the store shelf. Shopping for a better price meant traveling to the next town — a tough journey in the days before automobiles.
Sears entered the scene in 1897. Launching in the middle of the railroad boom gave Sears access to a cheap delivery system for both suppliers and customers. Efficient warehouses located at the country’s busiest railroad hub, Chicago, maximized their distribution leverage. The result: The cozy general store system was disrupted by the Sears catalog, 786-pages filled with more products and better prices.
Note that the Sears catalog did not put the general store completely out of business. Impulse buyers still shopped at the general store. But Sears certainly shook things up by making Long Tail products available for everybody.
The Long Tail in 1994
In 1994 a math geek named Jeff Bezos was reviewing Internet investment opportunities. Bezos observed that book sellers were expanding their physical stores, but none were expanding on the web. He smelled an opportunity. Bezos believed that a new distribution system (the web) could make a wider selection (the Long Tail) available to the world. Amazon.com was born.
Sears launched in the middle of the railroad boom, and Bezos launched Amazon.com in the middle of the first Internet boom. Sears benefited from inexpensive distribution via railroads, while Amazon distributes its catalog virtually free via the web. Great business ideas often repeat themselves.
The Long Tail Today
Do you remember record stores? Record stores had a problem — limited shelf space. Store managers had to figure out which records to stock by predicting (in advance) which records would sell best — the 80/20 rule again.
Some people argue that record stores were destroyed by free music downloads. However, “free” was only part of the problem. The bigger challenge came from the wider selection (Long Tail) offered through music downloads. In January 2009, Apple announced that over six billion songs had been downloaded through iTunes at 99 cents each. Apple’s distribution costs are virtually zero thanks to iTunes.
Apple found abundant opportunities in the Long Tail of music distribution. Video entertainment is next.
What About the Crud?
Some argue that there is a reason why some products are in the Long Tail instead of the short head: If you consider the entire spectrum of any product type, a large percentage of it is crud. The music industry is one example. True, the “better” music gets recorded by a large music studio or played on radio stations. But the Long Tail is full of music that never made it that far — from the amateur taking his first lesson to the garage band with great musical skills and bad marketing.
Of course, one person’s crud is another person’s masterpiece. Musical tastes vary widely. The Long Tail works in the digital music business because it makes tiny niches of music available to people who want them.
The Long Tail Future
Given the success of Long Tail companies (like Sears, Amazon, and Apple) one might wonder if there are any Long Tail opportunities left in our economy. The answer is yes! Anderson argues that a Long Tail company needs to do two things to succeed:
- Make a wide selection available, from the short head and the Long Tail.
- Help customers find what they want.
Everything, Easy to Find
If you make everything available, customers could become annoyed if they have to sift through it. So we have to make it easy for them to find exactly what they want.
Sears made everything available through railroads, and they solved the sifting problem with the Sears catalog. The catalog served as a convenient way for customers to find the products they wanted.
Amazon’s recommendation software is wonderful — unless you’re a customer trying to save money! The engine examines a customer’s past purchases and uses that information to suggest future purchases. Human clerks have done the same thing for centuries. But Amazon’s software does it faster with zero vacation days.
Apple makes everything available and easily searchable through iTunes.
Conclusion
History shows that Long Tail opportunities tend to coincide with the introduction of disruptive technologies. Railroads and the Internet are two examples. Sears could not have existed in catalog form before railroads. Amazon could not have offered the long tail of book selection without the Internet. In both cases, the advent of a faster & cheaper distribution system was a catalyst for a powerful new business model.
Are there any Long Tail opportunities left in today’s marketplace? Yes. And the next Long Tail enterprise might be launched by you.
Suggested Reading
The Long Tail, by Chris Anderson. The drastic reduction in the cost of distribution for digital information has far-reaching effects upon our economy. As a result, some businesses will thrive while others will die.
Note: A version of this post originally appeared on the WisdomGroup Blog.


31 May 2007
The Ministry of Health of Indonesia has announced a new case of human infection of H5N1 avian influenza. A 45-year-old male from Grobogan district, Central Java Province developed symptoms on 17 May, was hospitalized on 26 May and died in hospital on 28 May. Initial investigations into the source of his infection indicate exposure to dead poultry.
Of the 98 cases confirmed to date in Indonesia, 78 have been fatal.


Hours of development and testing go into maintaining this extension. If you feel it's worth a couple bucks, you can buy my cats a snack. I really appreciate it. <3


class: center, middle, inverse, title-slide .title[ # Estimation ] .author[ ### Mahendra Mariadassou, INRAE
.small[from original slides by Tristan Mary-Huard] ] .date[ ### Shandong University, Weihai (CN)
Summer School 2022 ] --- --- class: middle, inverse, center # Recap --- ## So far... Last session we focused on the estimation of the .alert[population mean]. -- We established the following points: - Any estimation strategy requires - a way to sample the individuals from the population (eg SRS and iid sampling) - a strategy to compute the estimate from the sample (eg empirical average). - Different estimation strategies can be evaluated/compared through their bias, variance and MSE. - SRS / iid seems a relevant strategy for which theoretical guarantees can be derived. -- .center[ Assuming now that observations are sampled independently from a parametric distribution `\(\L(\theta)\)`, can we propose a *systematic* way to obtain a good estimator for parameter `\(\theta\)` ? ] --- class: middle, inverse, center # Technical detour: Properties of gaussian variables --- ## Gaussian variable .def[Definition:] A real-valued continuous random variable `\(X\)` is normally distributed `\(\mathcal{N}(\mu, \sigma^2)\)`, noted `\(X \sim \mathcal{N}(\mu, \sigma^2)\)`: $$ f_{\mu, \sigma}(x) = \frac{1}{\sigma\sqrt{2\pi}}e^{-\frac{(x - \mu)^2}{2\sigma^2}} $$ where `\(\mu\)` is the .blue[mean] and `\(\sigma\)` the .blue[standard deviation]. -- In other words, the probability that `\(X\)` takes values in an infinitesimal interval of size `\(dx\)` around `\(x\)` is $$ \mathbb{P}\left( X \in \left[x - \frac{dx}{2}, x + \frac{dx}{2} \right] \right) = f_{\mu, \sigma}(x)dx $$ When moving to non infinitesimal intervals of the form `\([a, b]\)`, we can simply integrate the previous equality over `\(x\)` to obtain `$$\begin{equation} \mathbb{P}(X \in [a, b]) = \int_{x = a}^{x = b} f_{\mu, \sigma}(x)dx \end{equation}$$` --- class: inverse ## Algebraic properties: `\(\mu\)` Gaussian densities for different values of `\(\mu\)`  --- ## Translation We can check that: `$$f_{\mu, \sigma}(x) = f_{\mu + h, \sigma}(x + h)$$` for all `\(x\)`, `\(h\)`, `\(\mu\)` and `\(\sigma\)` -- Formally, if we note `\(y = x+h\)`, `$$\begin{align} f_{\mu+h, \sigma}(y) dy & = f_{\mu+h, \sigma}(x+h) d(x+h) \\ & = \frac{1}{\sigma\sqrt{2\pi}}\exp\left\{-\frac{(x+h - (\mu+h))^2}{2\sigma^2}\right\} dx \\ & = \frac{1}{\sigma\sqrt{2\pi}}\exp\left\{-\frac{(x - \mu)^2}{2\sigma^2}\right\} dx = f_{\mu, \sigma}(x)dx \end{align}$$` --- ## Link with random variables To make the connection explcit in terms of random variables, $$ X \sim \mathcal{N}(\mu, \sigma^2) \Rightarrow Y = X + h \sim \mathcal{N}(\mu + h, \sigma^2) $$ In particular, $$ \forall a \leq b \in \mathbb{R}, \quad \mathbb{P}(Y \in [a+h, b+h]) = \mathbb{P}(X \in [a, b]) $$ --- class: inverse ## Algebraic properties: `\(\sigma\)` Gaussian densities for different values of `\(\sigma\)`  --- ## Scaling We can can check that `\(f_{\mu, \sigma}(x) = a f_{a\mu, a\sigma}(ax)\)` for all `\(x\)`, `\(a\)` and `\(\sigma\)` -- Note `\(y = ax\)`, `$$\begin{equation} f_{\mu, a\sigma}(y)dy = f_{\mu, a\sigma}(ax)d(ax) = \frac{1}{a\sigma\sqrt{2\pi}}e^{-\frac{(ax - a \mu)^2}{2(a\sigma)^2}} adx= \frac{1}{\sigma\sqrt{2\pi}}e^{-\frac{(x - \mu)^2}{2\sigma^2}} dx = f_{\mu, \sigma}(x)dx \end{equation}$$` -- To make the connection explcit in terms of random variables, $$ X \sim \mathcal{N}(\mu, \sigma^2) \Rightarrow Y = aX \sim \mathcal{N}(a\mu, a^2\sigma^2) $$ -- In particular, $$ \forall x_1 \leq x_2 \in \mathbb{R}, \quad \mathbb{P}(Y \in [ax_1, ax_2]) = \mathbb{P}\left(X \in \left[x_1, x_2 \right]\right) $$ .question[Quizz1] --- ## Standard normal gaussian Combining the two previous observations: $$ X \sim \mathcal{N}(\mu, \sigma^2) \Rightarrow Y = aX + h \sim \mathcal{N}(a\mu + h, a^2\sigma^2) $$ -- If we consider a standard gaussian `\(Z \sim \mathcal{N}(0, 1)\)` and and two parameters `\(\mu\)` and `\(\sigma^2\)`, we have $$ X = \mu + \sigma Z \sim \mathcal{N}(\mu, \sigma^2) $$ -- Conversely, if `\(X \sim \mathcal{N}(\mu, \sigma^2)\)`, then $$ Z = \frac{X - \mu}{\sigma} \sim \mathcal{N}(0, 1) $$ -- .blue[Every] gaussian can be scaled and translated back to the standard gaussian `\(\mathcal{N}(0, 1)\)`. --- ## Mean and variance We admit that `\(\int_\mathbb{R} e^{-x^2/2} dx = \sqrt{2\pi}\)`. -- We can prove that (using the standard gaussian) that `$$X \sim \mathcal{N}(\mu, \sigma) \Rightarrow E[X] = \mu \quad \text{and} \quad V[X] = \sigma^2$$` -- .blue[Proof:] Using the standard gaussian and scaling / translation --- ## Sum of independent gaussians Consider two independent random variables `\(X_1 \sim \mathcal{N}(\mu_1, \sigma_1^2)\)` and `\(X_2 \sim \mathcal{N}(\mu_2, \sigma_2^2)\)`. What can we say about `\(Z = X_1 + X_2\)`? -- .blue[It turns out we can say a lot !!] -- The sums of two independent gaussians is also gaussian !! -- $$ Z \sim \mathcal{N}\left(\mu_1 + \mu_2, \sigma_1^2 + \sigma_2^2 \right) $$ -- What about the average ? .question[quizz2] -- $$ Z = \frac{X_1 + X_2}{2} \sim \mathcal{N}\left( \frac{\mu_1 + \mu_2}{2}, \frac{\sigma_1^2 + \sigma_2^2}{4} \right) $$ --- class: middle, inverse, center # Chi-square distribution --- ## Introducing the `\(\chi^2\)` distribution Let `\(X_1,...,X_n\)` be `\(n\)` real random variables such that `$$X_i \sim \N(0,1), \ i.i.d.$$` Define a new positive random variable `$$U = \sum_{i=1}^{n} X_i^2$$` Then `\(U\)` is said to have a `\(\chi^2(n)\)` distribution. `\(n\)` is called the **degree of freedom** of `\(U\)`. .blue[Question] What are the mean and variance of `\(U\)` ? .question[quizz3] -- `$$E[U] = n, \quad V[U] = 2n$$` --- ## Proof: --- class: middle, center, inverse # A first example ## Discrete observations --- ## First example: infering allelic frequency Consider a biallelic genetic marker. Note `\(A\)` the reference allele and `\(a\)` the mutant allele. A geneticist sampled 7 individuals in the population and obtained the following genotypes: (a A), (A A), (A A), (A A), (A A), (A a), (A A) -- .blue[Objective] Infer the mutant allele frequency `\(f_a\)`. --- ## Modeling .blue[Assumptions] - Individuals are unrelated, - Hardy-Weinberg Equilibrium is achieved for the considered marker - the two alleles from an individual are independent `\(\Rightarrow\)` 7 `\(\times2=\)` 14 independent observations. -- .blue[Statistical model] Sampled alleles can be modeled as independent Bernoulli experiments. Let `$$X_i = \begin{cases} 1 & \text{if allele a is observed in sample } i \\ 0 & \text{otherwise} \end{cases}$$` One has `$$X_i \sim \B(f_a),\ \text{i.i.d}$$` --- class: middle, center, inverse # Likelihood --- ## Likelihood Assume `\(f_a\)` is known. What would be the probability of observing the collected sample ? Recall the observed allele sequence: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 `$$\begin{align} & P(X_1= 1, X_2=0, ..., X_{13}=0, X_{14}=0) & \\ & = P(X_1=1) \times P(X_2=0)\times ...\times P( X_{13}=0)\times P( X_{14}=0) \\ & = (1-f_a)^{n_A}\times f_a^{n_a} \\ & = Lik_{f_a}(x_1,...,x_n) \\ \end{align}$$` where `\(n_a=\sum_i x_i=\)` 2, `\(n_A=n-n_a=\)` 12. -- Function `\(Lik_{f_a}\)` is the **likelihood** function that depends on the unknown .alert[parameter] `\(f_a\)`. --- ## Likelihood What likelihood value do we get .pull-left[ - for `\(f_a=\)` 0 ? - for `\(f_a=\)` 1 ? - for `\(f_a=\)` 0.4 ? - for `\(f_a=\)` 0.2 ? - for `\(f_a=\)` 0.5 ? .question[quizz4] ] -- .pull-right[ ![](Figures/Likelihood_final.png) ] -- Can we find the value of `\(f_a\)` that .alert[maximizes] the likelihood ? `$$\widehat{f}_a = \arg\max_{f_a} Lik_{f_a}(x_1,...,x_n)$$` --- ## Maximizing the likelihood One can find `\(\widehat{f}_a\)` analytically. One has `$$\begin{eqnarray} \widehat{f}_a &=& \arg\max_{f_a} Lik_{f_a}(x_1,\dots,x_n) \\ & = & \arg\max_{f_a} \ \log Lik_{f_a}(x_1,...,x_n) \ \text{ using the monotonicity of log}\\ & = & \arg\max_{f_a} \ \log (1-f_a)^{n_A} \times f_a^{n_a} \\ & = & \arg\max_{f_a} \ n_A\log(1-f_a) + n_a\log(f_a) \\ & = & \arg\max_{f_a} \ LLik_{f_a}(x_1,...,x_n) \end{eqnarray}$$` -- Deriving `\(LLik_{f_a}\)` w.r.t. `\(f_a\)` yields `$$\widehat{f}_a = \frac{n_a}{n}= 0.14$$` --- ## The log "monotonicity" property  Different functions, different maximum values, but same maximum location ! --- ## Maximizing the likelihood One can find `\(\widehat{f}_a\)` analytically. One has `$$\begin{eqnarray} \widehat{f}_a &=& \arg\max_{f_a} Lik_{f_a}(x_1,...,x_n) \\ &=& \arg\max_{f_a} \ \log Lik_{f_a}(x_1,...,x_n) \ \text{ using the monotonicity of log}\\ &=& \arg\max_{f_a} \ \log (1-f_a)^{n_A}\times f_a^{n_a} \\ &=& \arg\max_{f_a}\ n_A\log(1-f_a) + n_a\log(f_a) \\ &=& \arg\max_{f_a}\ LLik_{f_a}(x_1,...,x_n) \\ \end{eqnarray}$$` -- Deriving `\(LLik_{f_a}\)` w.r.t. `\(f_a\)` yields `$$\widehat{f}_a = \frac{n_a}{n}= 0.14$$` --- ## Maximizing the likelihood  --- ## Maximum likelihood estimator We showed that on our specific example `$$\widehat{f}_a = \frac{n_a}{n} = \frac{1}{n}\sum_{i=1}^n x_i$$` which leads to the **ML estimator** `$$F_a = \frac{1}{n}\sum_{i=1}^n X_i.$$` .remark[Remark:] Remember that `\(F_a\)` is a .alert[random variable] while `\(\hat{f}_a\)` is a .alert[numeric value]. .blue[Question:] What are the bias, variance and MSE of this ML estimator ? -- `$$B(F_a)=0,\quad V(F_a) = \frac{1}{n}f_a(1-f_a)=MSE(F_a)$$` --- class: middle, center, inverse # A second example ## Continuous observations --- ## Second example: maize yield analysis Grain yield was evaluated for 261 maize "dent" lines. Here are the first 30 recorded values: .center[ ``` 16.8409 16.0331 16.1603 14.6450 12.5485 17.9981 17.0086 15.9537 14.8380 17.6652 16.6532 15.8661 18.0482 16.7795 11.9385 14.5463 13.6835 14.0806 17.4285 16.8205 18.9517 12.5905 14.6746 15.6237 14.4720 14.8696 13.4080 16.2017 13.2779 18.8557 ``` ] -- .blue[Objective:] Infer the mean yield and the yield variability in the dent population. --- ## Modeling .blue[Assumptions] - Lines were selected at random in the overall population, - No spatial field effect. `\(\Rightarrow\)` 261 independent observations. -- .blue[Statistical model] Let `\(X_i\)` be the yield recorded for the `\(i^{th}\)` line. One has `$$X_i \sim \N\left(\mu,\sigma^2\right),\ \text{i.i.d}$$` --- ## Likelihood Assume both `\(\mu\)` and `\(\sigma^2\)` are known. How likely was it to observe the collected sample ? For continuous variables likelihood is quantified through **density**. Recall the gaussian density function: `$$f_{\mu,\sigma}(x) = \frac{1}{\sqrt{2\pi}\sigma}\exp\left\{ -\frac{(x-\mu)^2}{2\sigma^2}\right\}$$` -- `$$\begin{align} Lik_{\mu,\sigma^2}(x_1,...,x_n) & = f_{\mu,\sigma}(x_1, x_2, ..., x_{n-1}, x_{n}) \\ & = f_{\mu,\sigma}(x_1)\times f_{\mu,\sigma}(x_2)\times ..., f_{\mu,\sigma}(x_{n-1})\times f_{\mu,\sigma}(x_{n}) \quad \text{(i.i.d)} \\ & = \prod_{i=1}^{n} \frac{1}{\sqrt{2\pi}\sigma}\exp\left\{ -\frac{(x_i-\mu)^2}{2\sigma^2} \right\}\\ \end{align}$$` --- ## Maximizing the likelihood .blue[Step 1:] use the log trick `$$\begin{eqnarray} \arg\max_{\mu,\sigma^2}Lik_{\mu,\sigma^2}(x_1,...,x_n) &=& \arg\max_{\mu,\sigma^2}\log Lik_{\mu,\sigma^2}(x_1,...,x_n)\\ &=& \arg\max_{\mu,\sigma^2}LLik_{\mu,\sigma^2}(x_1,...,x_n)\\ \end{eqnarray}$$` -- .blue[Step 2] Set the **partial** derivatives to 0: `$$\begin{equation} \left. \frac{\partial LLik(\mu,\sigma^2)}{\partial \mu} \right|_{\mu = \hat{\mu}, \sigma^2 = \hat{\sigma}^2} = 0,\quad \left. \frac{\partial LLik(\mu,\sigma^2)}{\partial \sigma^2} \right|_{\mu = \hat{\mu}, \sigma^2 = \hat{\sigma}^2}= 0 \end{equation}$$` -- One obtains: `$$\widehat{\mu}=\frac{1}{n}\sum_{i=1}^{n}x_i,\quad \widehat{\sigma}^2=\frac{1}{n}\sum_{i=1}^{n}(x_i-\widehat{\mu})^2$$` -- .blue[Numerical application] `\(\widehat{\mu}=\)` 15.86 `\(,\quad \widehat{\sigma}^2=\)` 3.72 --- ## Proof: --- ## Properties of the ML estimators The ML estimators are `$$\overline{X}=\frac{1}{n}\sum_{i=1}^{n}X_i,\quad S^2_n=\frac{1}{n}\sum_{i=1}^{n}\left(X_i-\overline{X}\right)^2$$` -- Compute .pull-left[ - the bias, variance and MSE of `\(\overline{X}\)` - the bias of `\(S^2\)` ] -- .pull-right[ - `\(B\left[\overline{X}\right]= 0, V\left[\overline{X}\right]= \frac{\sigma^2}{n} = MSE\left[\overline{X}\right]\)` - `\(B[S_n^2]= -\frac{\sigma^2}{n}\)` ] -- Can we modify `\(S_n^2\)` to obtain an unbiased estimator ? --- ## Debiasing `\(S_n^2\)` .blue[Intuition] Where does the bias come from ? Let's compute $$\sum_{i=1}^n \left(X_i - \overline{X}\right) = 0 $$ -- The `\(n\)` terms are dependant as they sum up to `\(0\)` !!! -- .blue[Unbiased predictor] Define `$$S^2_{n-1}=\frac{1}{n-1}\sum_{i=1}^{n}(X_i-\overline{X})^2$$` and show that this variance estimator is unbiased. --- ## Proof --- ## Summary .blue[General strategy] Assume `\(X_1,...,X_n\sim \L(\theta)\)` i.i.d. - Write the likelihood of the data `$$Lik_{\theta}(x_1,...,x_n) = \begin{cases} \prod_{i=1}^{n}P_\theta(x_i) & \text{discrete case} \\ \prod_{i=1}^{n}f_\theta(x_i) & \text{continuous case} \end{cases}$$` - Find `$$\widehat{\theta} = \arg\max_{\theta}Lik_\theta(x_1,...,x_n)$$` using log-transformation + derivation. --- class: middle, inverse, center # Exercises --- ## Exercise 1: Hotline A hotline operator spent the following times answering the last 12 customer queries: ``` 0.6 11.5 14.1 3.4 9.3 14.7 7.1 50 2.3 2.3 6.6 9.3 ``` Assume the amount `\(X\)` of time spent with a customer is `\(X\sim \mathcal{E}(\lambda)\)` with density `\(f(x) = \lambda e^{-\lambda x}\)` for `\(x \geq 0\)` .pull-left[ - Find the ML estimator of `\(\lambda\)`. - Provide an estimation of the average time spent by the operator with a customer. - Compute `\(P(X>t+\delta|X>t)\)` for `\(t, \delta > 0\)` - Assume the operator spent four minutes with a given customer. Provide an estimation of the probability that he will spend at least three more minutes more with him. ] -- .pull-right[ - `\(\hat{\lambda}_{ML} = \left( \frac{1}{n} \sum_{i=1}^n X_i \right)^{-1}\)` - `\(\widehat{\lambda}^{-1} = \frac{1}{n} \sum_{i=1}^n x_i = 10.933\)` - Exponential variables are memoryless $$ P(X>t+\delta|X>t) = P(X> \delta) $$ - `\(P(X> 7 | X> 4) = P(X > 3) = 1 - e^{-3 \hat{\lambda}} = 0.76\)` ]


object RelaxedCSVParser
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Creates Relaxed csv parser to read from file
Creates Relaxed csv parser to read from file
- file
to read from
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does it have a header
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to quote fields
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to separate records
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Creates relaxed csv parser to read from channel
Creates relaxed csv parser to read from channel
- channel
to read from
- header
does it have a header
- quotingString
to quote fields
- recordSeparator
to separate records
- fieldSeparator
to separate fields
- escapeString
optional escape string, supplying Some() here enables escaping
- codec
to convert bytes to characters and back
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def
fromStream(stream: InputStream, header: Boolean = false, quotingString: String = "\"", recordSeparator: String = "\n", fieldSeparator: String = ",", escapeString: Option[String] = None)(implicit codec: Codec): RelaxedCSVParser
Creates relaxed csv parser to read from stream
Creates relaxed csv parser to read from stream
- stream
to read from
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does it have a header
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to quote fields
- recordSeparator
to separate records
- fieldSeparator
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(Since version ) see corresponding Javadoc for more information.


Organising your fridge into categories, for example, Meat and fish on the bottom shelf, Vegetables in the veggie draw, as well as having set areas for other food categories. Organising your food is not only aesthetic but it is an easy way to beagle to see all of the food you have. By organising your fridge you are more likely to know what food you have and when it needs to be used by. Knowing this means you can plan meals around the food that will go off first. This can greatly reduce your household's food waste.
Washing fruits and vegetables and prepping them into containers very easily tidies up your fridge and makes foods more easily accessible, whether you're getting a snack or about to prepare dinner, Using air tight containers to keep the freshness in makes it last longer as well!


Maps
Kakurenbocchi
Lose It
Gate One
Nobody To Love
Kakumei no Bullet
Pokemon Capture
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--- title: Projects desc: Projects layout: page --- Most of the software I write can be found on github.
Throughout the years I have created quite a few games. This is a collection of some of them.


My name is Harald Sack and you can give me a ring via 1-800-555-0527. My favorite beverage is Green Tea.


In mobile interfaces, you sometimes need a user-friendly back-button within the interface itself (without relying on the mobile browser chrome).
The advantage to using the back-button component is that when clicked, it will keep the behavior of the browser's back- and forward-buttons functioning as expected, whereas a normal link to the previous page would add the current page to the browser's back-button and disable the forward-button.


© {{ site.time | date: '%Y' }} Kristen Blanks. Powered by Jekyll. Twitter / Instagram / Github / Linkedin / Google-plus /


@* * Copyright 2021 HM Revenue & Customs * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. *@ @( field: Field, label: Option[String] = None, labelClass: Option[String] = None, labelHtml: Option[Html] = None, inputClass: Option[String] = None, hint: Option[String] = None, max: Int = 1000, inputPurpose: Option[String] = None, headingIsLabel: Boolean = false, contentHtml : Option[Html] = None, captionMsg: Option[String] = None )(implicit messages: Messages)


Interfaces
AdminCatalogAsyncClient
AdminCatalogClient
AdminNetworkAsyncClient
AdminNetworkClient
AdminOrgAsyncClient
AdminOrgClient
AdminQueryAsyncClient
AdminQueryClient
AdminVdcAsyncClient
AdminVdcClient
GroupAsyncClient
GroupClient
UserAsyncClient
UserClient |


List one IP per line. IP Ranges should end in period or colon (for IPv6) (ex. 127.0. will ban everything starting with those two octets) Comments should be prepended with hash (#comment).


Initially syphilis begins as an ugly-looking sore with a hard rim around it, which heals on its own. During the next stage of the disease, you may notice a rash on your body (see Tip 151). This too will disappear on its own. The third and final phase of syphilis is when the infecting germ damages one of the valves (doors) in your heart and/or destroys brain cells, causing mental deterioration. Syphilis is curable if you receive antibiotics when you first notice the sore with the hard rim around it. Therefore if you have a non-painful, raw-looking sore near the genitals and/or mouth, see your doctor as soon as possible. (Also see Appendix C, about syphilis screening.)
Note: Even if the signs of this disease disappear on their own, it is still very important to get treatment.


File Directory - No Confirmation
If you set this radio button, Moderate will delete files from a file directory without confirmation; it will also delete associated entries from the file list for those files that have such entries.


Cedar Fair says attendance, pass sales up at amusement parks
by The Associated PressSANDUSKY, Ohio (AP) — Cedar Fair Entertainment says its amusement and water parks have seen another jump in attendance this year.
The Sandusky, Ohio-based company says helping drive the increase are its popular Halloween and winter events along with new nighttime festivals at some of its parks.
Attendance is up 4% overall this year at Cedar Fair’s 11 amusement parks and five water parks across the U.S.
The company said Wednesday that season pass sales for next year are up 50% compared with a year ago.
Much of that is linked to a new discounted pass at the company’s flagship park, Cedar Point, in Sandusky.
Company officials say they plan to roll out more special events in 2020 to get more people in the parks during what are considered slower times of the year.


Overview
Value types are created on the stack, and reference types are created on the heap.
Both are stored in computer RAM.
Each thread gets a stack, while there’s typically only one heap for the application.
Stack
When a function is called, a block is reserved on the top of the stack for local variables and some bookkeeping data in a LIFO order. Freeing a block from the stack is nothing more than adjusting one pointer.
Heap
Unlike the stack, there’s no enforced pattern to the allocation and deallocation of blocks from the heap; you can allocate a block at any time and free it at any time. This makes it much more complex to keep track of which parts of the heap are allocated or free at any given time; there are many custom heap allocators available to tune heap performance for different usage patterns.
Q & A
What is their scope?
The stack is attached to a thread, so when the thread exits the stack is reclaimed.
The heap is typically allocated at application startup by the runtime, and is reclaimed when the application (technically process) exits.
Thread and process - what’s the difference? Read [Design] Process VS. Thread.
What determines the size of each of them?
The size of the stack is set when a thread is created.
The size of the heap is set on application startup, but can grow as space is needed (the allocator requests more memory from the operating system).
What makes one faster?
The stack is faster because the access pattern makes it trivial to allocate and deallocate memory from it, while the heap has much more complex bookkeeping involved in an allocation or free.
Each byte in the stack tends to be reused very frequently which means it tends to be mapped to the processor’s cache, making it very fast.
Another performance hit for the heap is that the heap, being mostly a global resource, typically has to be multi-threading safe, i.e. each allocation and deallocation needs to be (typically) synchronized.


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@* * Copyright 2021 HM Revenue & Customs * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. *@ @import iht.controllers.application.routes @import iht.viewmodels.application.overview._ @this() @(model: DeclarationSectionViewModel)(implicit request:Request[_], messages: Messages)
@Messages("page.iht.application.estateOverview.declaration.allSectionsNotComplete.guidance.text1")
@Messages("page.iht.application.estateOverview.declaration.allSectionsNotComplete.guidance.text2")
@Messages("page.iht.application.estateOverview.declaration.continue.guidance.text")
@Messages("page.iht.application.estateOverview.declaration.allSectionsComplete.guidance.text")


Using the Roland 560i, I printed two multicolor stickers. My first sticker was a sticker of my dog. I imported his image into adobe photoshop and copied it into corel draw. Around his head, I had to put a specific pink outline so that the printer knew where to cut. My second sticker was a picture of my uncles face. I inserted it into a circle then put the pink outline around it so it would be cut out. Next, I loaded them onto a flashdrive and printed them.
Using the Roland GS-24 CAMM 1, I printed two one color stickers. My first sticker was a yellow dog and the second was a pink elephant. I used Corel draw and uploaded clipart of the dog and elephant. I then printed them.
I made the sticker of my dog face because I love him. I made the sticker of my uncle for my father. I made the elephant and yellow dog sticker because I like dogs and elephants.
What was the thought process while I was creating my notebook?I put the stickers on my laptop instead of a notebook. My thought process was that I wanted to have quality stickers on my laptop.
What was the most challenging part of this process?The most challenging part was getting the pink boarder around the images.
What did you learn in the process?I learned how to insert images into shapes and make stickers.
To make my wax mold, got an image that said "Believe and turned it into a 3D image on Selva 3D. The wax was then milled out in the MDX40A. Now, my wax mold can be used as a chocolate mold.
For this assignment, I made an Indians pendant. First, using Corel Draw, I made my wooden molds. Using the Laser cutter, I engraved the top wooden block with a simple circle. On the middle wood block, I cut a hole so I could pore the pewter in. The bottom block had the Cleveland Indians logo on it. After I made the wooden molds, I clamped them together and was able to pored in baby powder, so the pewter would not stick and then the pewter. When the pewter cooled, I took it out of the mold and cut off the top excess pewter, buffed it out, and drilled a hole in the top.


Habermas says that
[quote]At one time, the process of making things public [Publizität] was intended to subject persons or affairs to public reason, and to make political decisions subject to appeal before the court of public opinion.
But often enough today the process of making public simply serves the arcane policies of special intersts; in the form of "publicity" it wins public prestige for people or affairs, thus making them worthy of acclamation in a climate of non-public opnion.
If you believe this narrative -- in which the public sphere has suffered a marked decline since the early 19th Century — the open question is, can the Web reverse that trend?
Everything depends on what you think the main virtues of the public sphere are, and how the Web can prop them up.
Think about the structure of HTML (links, hypertext) and also about the interactivity that the Web now gives you. Make an argument IN HTML about whether the Web saves the Public Sphere (Mark Poster thinks it does) or continues to pose problems for it. As you do this, use as many tags as you can, and mess with the CSS on this page if you have a chance.
When Tim Berners-Lee(http://en.wikipedia.org/wiki/Tim_Berners-Lee) first tried to build a web browser, he thought it would be a kind of specialized word processor. he imagined that every user would be *creating* as much as *consuming*. He wanted to call it the "read/write web".
But browsers never became the creation tools he wanted them to be.
Instead we now have [websites](http://facebook.com) that invite creation.
These present their own encodings of [public](http://en.wikipedia.org/wiki/Walled_garden_%28technology%29) and [private](https://www.facebook.com/help/privacy).
The truth is, over these last 4 years, the web has given us a gift: the first pathological narcissist to hold the presidency in some time. How much responsiblility do Twitter and Breitbart hold? What if, instead of a Public Sphere, we've just ended up with an infinite array of vacuous echo chambers? What happens to legitimacy, authenticity, democracy, then?
Think about the structure of HTML (links, hypertext) and also about the interactivity that the Web now gives you. Make an argument IN HTML about whether the Web saves the Public Sphere ([Mark Poster thinks it does](http://www.humanities.uci.edu/mposter/writings/democ.html)) or continues to pose problems for it. As you do this, **use as many tags as you can, and mess with the CSS on this page if you have a chance**.
You can learn more about HTML tags at [mozilla](https://developer.mozilla.org/en-US/docs/HTML) or [W3schools](http://w3schools.com/html/default.asp) or using [Google](https://www.google.com/search?q=html+tutorials).


MEDIXA
This script is a hospital and doctor listing management tool. It is great if you are looking for an easy-to-use
script
to register an updated listing of doctors and hospital from which users can search and book appointments. In
addition;
the script allows users to book and track appointments with physicians, who will be duly notified by email and in
app
notifications. Dashboards are created for hospitals accounts where they can manage their physicians, define
facilities
they offer, upload photos and more.
- Full Admin Dashboard
- Dashboard for hospitals
- Notify doctors of new appointments
- Filter by type, facilities or specialities
- Robust search with ranking algorithm
- User Management and Authentication
DEMO AUTHENTICATION
-
Admin Dashboard
- email<EMAIL_ADDRESS>- passsword: password
-
Hospital Dashboard
- email<EMAIL_ADDRESS>- passsword: password
-
Doctor Account
- email<EMAIL_ADDRESS>- passsword: password
Book appointments with notifications
Dashboard for hospitals to manage doctors
Filter & search algorithm - relevance ranking


|
Apollo Register Documentation v2.4.2
|
| 0x00000000: | PCFG - PDM Configuration Register |
| 0x00000004: | VCFG - Voice Configuration Register |
| 0x00000008: | VOICESTAT - Voice Status Register |
| 0x0000000C: | FIFOREAD - FIFO Read |
| 0x00000010: | FIFOFLUSH - FIFO Flush |
| 0x00000014: | FIFOTHR - FIFO Threshold |
| 0x00000200: | INTEN - IO Master Interrupts: Enable |
| 0x00000204: | INTSTAT - IO Master Interrupts: Status |
| 0x00000208: | INTCLR - IO Master Interrupts: Clear |
| 0x0000020C: | INTSET - IO Master Interrupts: Set |
| 0x00000240: | DMATRIGEN - DMA Trigger Enable Register |
| 0x00000244: | DMATRIGSTAT - DMA Trigger Status Register |
| 0x00000280: | DMACFG - DMA Configuration Register |
| 0x00000288: | DMATOTCOUNT - DMA Total Transfer Count |
| 0x0000028C: | DMATARGADDR - DMA Target Address Register |
| 0x00000290: | DMASTAT - DMA Status Register |
| Instance 0 Address: | 0x50011000 |
PDM Configuration Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LRSWAP
0x0 |
PGARIGHT
0x0 |
PGALEFT
0x0 |
RSVD
0x0 |
MCLKDIV
0x0 |
SINCRATE
0x30 |
ADCHPD
0x1 |
HPCUTOFF
0xb |
CYCLES
0x1 |
SOFTMUTE
0x0 |
PDMCOREEN
0x1 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | LRSWAP | RW | Left/right channel swap. EN = 0x1 - Swap left and right channels (FIFO Read RIGHT_LEFT). NOSWAP = 0x0 - No channel swapping (IFO Read LEFT_RIGHT). |
| 30:26 | PGARIGHT | RW | Right channel PGA gain. P405DB = 0x1F - 40.5 db gain. P390DB = 0x1E - 39.0 db gain. P375DB = 0x1D - 37.5 db gain. P360DB = 0x1C - 36.0 db gain. P345DB = 0x1B - 34.5 db gain. P330DB = 0x1A - 33.0 db gain. P315DB = 0x19 - 31.5 db gain. P300DB = 0x18 - 30.0 db gain. P285DB = 0x17 - 28.5 db gain. P270DB = 0x16 - 27.0 db gain. P255DB = 0x15 - 25.5 db gain. P240DB = 0x14 - 24.0 db gain. P225DB = 0x13 - 22.5 db gain. P210DB = 0x12 - 21.0 db gain. P195DB = 0x11 - 19.5 db gain. P180DB = 0x10 - 18.0 db gain. P165DB = 0xF - 16.5 db gain. P150DB = 0xE - 15.0 db gain. P135DB = 0xD - 13.5 db gain. P120DB = 0xC - 12.0 db gain. P105DB = 0xB - 10.5 db gain. P90DB = 0xA - 9.0 db gain. P75DB = 0x9 - 7.5 db gain. P60DB = 0x8 - 6.0 db gain. P45DB = 0x7 - 4.5 db gain. P30DB = 0x6 - 3.0 db gain. P15DB = 0x5 - 1.5 db gain. 0DB = 0x4 - 0.0 db gain. M15DB = 0x3 - -1.5 db gain. M300DB = 0x2 - -3.0 db gain. M45DB = 0x1 - -4.5 db gain. M60DB = 0x0 - -6.0 db gain. |
| 25:21 | PGALEFT | RW | Left channel PGA gain. P405DB = 0x1F - 40.5 db gain. P390DB = 0x1E - 39.0 db gain. P375DB = 0x1D - 37.5 db gain. P360DB = 0x1C - 36.0 db gain. P345DB = 0x1B - 34.5 db gain. P330DB = 0x1A - 33.0 db gain. P315DB = 0x19 - 31.5 db gain. P300DB = 0x18 - 30.0 db gain. P285DB = 0x17 - 28.5 db gain. P270DB = 0x16 - 27.0 db gain. P255DB = 0x15 - 25.5 db gain. P240DB = 0x14 - 24.0 db gain. P225DB = 0x13 - 22.5 db gain. P210DB = 0x12 - 21.0 db gain. P195DB = 0x11 - 19.5 db gain. P180DB = 0x10 - 18.0 db gain. P165DB = 0xF - 16.5 db gain. P150DB = 0xE - 15.0 db gain. P135DB = 0xD - 13.5 db gain. P120DB = 0xC - 12.0 db gain. P105DB = 0xB - 10.5 db gain. P90DB = 0xA - 9.0 db gain. P75DB = 0x9 - 7.5 db gain. P60DB = 0x8 - 6.0 db gain. P45DB = 0x7 - 4.5 db gain. P30DB = 0x6 - 3.0 db gain. P15DB = 0x5 - 1.5 db gain. 0DB = 0x4 - 0.0 db gain. M15DB = 0x3 - -1.5 db gain. M300DB = 0x2 - -3.0 db gain. M45DB = 0x1 - -4.5 db gain. M60DB = 0x0 - -6.0 db gain. |
| 20:19 | RSVD | RO | This bitfield is reserved for future use. |
| 18:17 | MCLKDIV | RW | PDM_CLK frequency divisor. MCKDIV4 = 0x3 - Divide input clock by 4 MCKDIV3 = 0x2 - Divide input clock by 3 MCKDIV2 = 0x1 - Divide input clock by 2 MCKDIV1 = 0x0 - Divide input clock by 1 |
| 16:10 | SINCRATE | RW | SINC decimation rate. |
| 9 | ADCHPD | RW | High pass filter control. EN = 0x1 - Enable high pass filter. DIS = 0x0 - Disable high pass filter. |
| 8:5 | HPCUTOFF | RW | High pass filter coefficients. |
| 4:2 | CYCLES | RW | Number of clocks during gain-setting changes. |
| 1 | SOFTMUTE | RW | Soft mute control. EN = 0x1 - Enable Soft Mute. DIS = 0x0 - Disable Soft Mute. |
| 0 | PDMCOREEN | RW | Data Streaming Control. EN = 0x1 - Enable Data Streaming. DIS = 0x0 - Disable Data Streaming. |
| Instance 0 Address: | 0x50011004 |
Voice Configuration Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| IOCLKEN
0x0 |
RSTB
0x0 |
PDMCLKSEL
0x0 |
PDMCLKEN
0x0 |
RSVD
0x0 |
I2SEN
0x0 |
BCLKINV
0x0 |
RSVD
0x0 |
DMICKDEL
0x0 |
SELAP
0x0 |
RSVD
0x0 |
PCMPACK
0x0 |
RSVD
0x0 |
CHSET
0x1 |
RSVD
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31 | IOCLKEN | RW | Enable the IO clock. DIS = 0x0 - Disable FIFO read. EN = 0x1 - Enable FIFO read. |
| 30 | RSTB | RW | Reset the IP core. RESET = 0x0 - Reset the core. NORM = 0x1 - Enable the core. |
| 29:27 | PDMCLKSEL | RW | Select the PDM input clock. DISABLE = 0x0 - Static value. 12MHz = 0x1 - PDM clock is 12 MHz. 6MHz = 0x2 - PDM clock is 6 MHz. 3MHz = 0x3 - PDM clock is 3 MHz. 1_5MHz = 0x4 - PDM clock is 1.5 MHz. 750KHz = 0x5 - PDM clock is 750 KHz. 375KHz = 0x6 - PDM clock is 375 KHz. 187KHz = 0x7 - PDM clock is 187.5 KHz. |
| 26 | PDMCLKEN | RW | Enable the serial clock. DIS = 0x0 - Disable serial clock. EN = 0x1 - Enable serial clock. |
| 25:21 | RSVD | RO | This bitfield is reserved for future use. |
| 20 | I2SEN | RW | I2S interface enable. DIS = 0x0 - Disable I2S interface. EN = 0x1 - Enable I2S interface. |
| 19 | BCLKINV | RW | I2S BCLK input inversion. INV = 0x0 - BCLK inverted. NORM = 0x1 - BCLK not inverted. |
| 18 | RSVD | RO | This bitfield is reserved for future use. |
| 17 | DMICKDEL | RW | PDM clock sampling delay. 0CYC = 0x0 - No delay. 1CYC = 0x1 - 1 cycle delay. |
| 16 | SELAP | RW | Select PDM input clock source. I2S = 0x1 - Clock source from I2S BCLK. INTERNAL = 0x0 - Clock source from internal clock generator. |
| 15:9 | RSVD | RO | This bitfield is reserved for future use. |
| 8 | PCMPACK | RW | PCM data packing enable. DIS = 0x0 - Disable PCM packing. EN = 0x1 - Enable PCM packing. |
| 7:5 | RSVD | RO | This bitfield is reserved for future use. |
| 4:3 | CHSET | RW | Set PCM channels. DIS = 0x0 - Channel disabled. LEFT = 0x1 - Mono left channel. RIGHT = 0x2 - Mono right channel. STEREO = 0x3 - Stereo channels. |
| 2:0 | RSVD | RO | This bitfield is reserved for future use. |
| Instance 0 Address: | 0x50011008 |
Voice Status Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
FIFOCNT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:6 | RSVD | RO | This bitfield is reserved for future use. |
| 5:0 | FIFOCNT | RO | Valid 32-bit entries currently in the FIFO. |
| Instance 0 Address: | 0x5001100C |
FIFO Read
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FIFOREAD
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | FIFOREAD | RO | FIFO read data. |
| Instance 0 Address: | 0x50011010 |
FIFO Flush
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
FIFOFLUSH
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:1 | RSVD | RO | This bitfield is reserved for future use. |
| 0 | FIFOFLUSH | WO | FIFO FLUSH. |
| Instance 0 Address: | 0x50011014 |
FIFO Threshold
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
FIFOTHR
0x10 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:5 | RSVD | RO | This bitfield is reserved for future use. |
| 4:0 | FIFOTHR | RW | FIFO Threshold value. When the FIFO count is equal to, or larger than this value (in words), a THR interrupt is generated (if enabled) |
| Instance 0 Address: | 0x50011200 |
Set bits in this register to allow this module to generate the corresponding interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DERR
0x0 |
DCMP
0x0 |
UNDFL
0x0 |
OVF
0x0 |
THR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:5 | RSVD | RO | RESERVED |
| 4 | DERR | RW | DMA Error receieved |
| 3 | DCMP | RW | DMA completed a transfer |
| 2 | UNDFL | RW | This is the FIFO underflow interrupt. |
| 1 | OVF | RW | This is the FIFO overflow interrupt. |
| 0 | THR | RW | This is the FIFO threshold interrupt. |
| Instance 0 Address: | 0x50011204 |
Read bits from this register to discover the cause of a recent interrupt.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DERR
0x0 |
DCMP
0x0 |
UNDFL
0x0 |
OVF
0x0 |
THR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:5 | RSVD | RO | RESERVED |
| 4 | DERR | RW | DMA Error receieved |
| 3 | DCMP | RW | DMA completed a transfer |
| 2 | UNDFL | RW | This is the FIFO underflow interrupt. |
| 1 | OVF | RW | This is the FIFO overflow interrupt. |
| 0 | THR | RW | This is the FIFO threshold interrupt. |
| Instance 0 Address: | 0x50011208 |
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DERR
0x0 |
DCMP
0x0 |
UNDFL
0x0 |
OVF
0x0 |
THR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:5 | RSVD | RO | RESERVED |
| 4 | DERR | RW | DMA Error receieved |
| 3 | DCMP | RW | DMA completed a transfer |
| 2 | UNDFL | RW | This is the FIFO underflow interrupt. |
| 1 | OVF | RW | This is the FIFO overflow interrupt. |
| 0 | THR | RW | This is the FIFO threshold interrupt. |
| Instance 0 Address: | 0x5001120C |
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DERR
0x0 |
DCMP
0x0 |
UNDFL
0x0 |
OVF
0x0 |
THR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:5 | RSVD | RO | RESERVED |
| 4 | DERR | RW | DMA Error receieved |
| 3 | DCMP | RW | DMA completed a transfer |
| 2 | UNDFL | RW | This is the FIFO underflow interrupt. |
| 1 | OVF | RW | This is the FIFO overflow interrupt. |
| 0 | THR | RW | This is the FIFO threshold interrupt. |
| Instance 0 Address: | 0x50011240 |
DMA Trigger Enable Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DTHR90
0x0 |
DTHR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:2 | RSVD | RO | RESERVED. |
| 1 | DTHR90 | RW | Trigger DMA at FIFO 90 percent full. This signal is also used internally for AUTOHIP function |
| 0 | DTHR | RW | Trigger DMA upon when FIFO iss filled to level indicated by the FIFO THRESHOLD,at granularity of 16 bytes only |
| Instance 0 Address: | 0x50011244 |
DMA Trigger Status Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DTHR90STAT
0x0 |
DTHRSTAT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:2 | RSVD | RO | RESERVED. |
| 1 | DTHR90STAT | RO | Triggered DMA from FIFO reaching 90 percent full |
| 0 | DTHRSTAT | RO | Triggered DMA from FIFO reaching threshold |
| Instance 0 Address: | 0x50011280 |
DMA Configuration Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DPWROFF
0x0 |
DAUTOHIP
0x0 |
DMAPRI
0x0 |
RSVD
0x0 |
DMADIR
0x0 |
RSVD
0x0 |
DMAEN
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:11 | RSVD | RO | RESERVED. |
| 10 | DPWROFF | RW | Power Off the ADC System upon DMACPL. |
| 9 | DAUTOHIP | RW | Raise priority to high on fifo full, and DMAPRI set to low |
| 8 | DMAPRI | RW | Sets the Priority of the DMA request LOW = 0x0 - Low Priority (service as best effort) HIGH = 0x1 - High Priority (service immediately) |
| 7:3 | RSVD | RO | RESERVED. |
| 2 | DMADIR | RO | Direction P2M = 0x0 - Peripheral to Memory (SRAM) transaction. THe PDM module will only DMA to memory. M2P = 0x1 - Memory to Peripheral transaction. Not available for PDM module |
| 1 | RSVD | RO | RESERVED. |
| 0 | DMAEN | RW | DMA Enable DIS = 0x0 - Disable DMA Function EN = 0x1 - Enable DMA Function |
| Instance 0 Address: | 0x50011288 |
DMA Total Transfer Count
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
TOTCOUNT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:20 | RSVD | RO | RESERVED. |
| 19:0 | TOTCOUNT | RW | Total Transfer Count. The transfer count must be a multiple of the THR setting to avoid DMA overruns. |
| Instance 0 Address: | 0x5001128C |
DMA Target Address Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| UTARGADDR
0x100 |
LTARGADDR
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:20 | UTARGADDR | RO | SRAM Target |
| 19:0 | LTARGADDR | RW | DMA Target Address. This register is not updated with the current address of the DMA, but will remain static with the original address during the DMA transfer. |
| Instance 0 Address: | 0x50011290 |
DMA Status Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
DMAERR
0x0 |
DMACPL
0x0 |
DMATIP
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:3 | RSVD | RO | RESERVED. |
| 2 | DMAERR | RW | DMA Error |
| 1 | DMACPL | RW | DMA Transfer Complete |
| 0 | DMATIP | RW | DMA Transfer In Progress |


Posted on January 13th, 2018
Today we have some exciting news to announce for the Zildith Network. To support our past Avicus players, we have decided to open up rank trials to players who previously had donor ranks on the Avicus Network. We will have five donation ranks on the Zildith Network: Alpha, Delta, Gamma, Omega, and Zeta. In order to find out what trial ranks you are eligible for, find your Avicus rank in the list below.
If you currently have the “Iron” rank on Avicus, you will be receiving a three week Trial of the “Alpha” rank. The Alpha rank includes the following perks:
If you currently have the “Gold” rank on Avicus, you will get the choice of receiving either a three week trial of the “Alpha” rank, or a two week trial of the “Delta” rank. The Delta rank includes the following perks:
If you currently have the “Emerald” rank on Avicus, you will get the choice of receiving either a three week trial of the “Delta” rank, or a two week trial of the “Gamma” rank. The Gamma rank includes the following perks:
If you currently have either the “Diamond” or “Bedrock” rank on Avicus, you will get the choice of receiving either a three week trial of the “Gamma” rank, or a two week trial of the “Omega” rank. The Omega rank includes the following perks:
The “Zeta” rank is not available to trial. Here is what the Zeta package includes:
*Please note that if you purchase a rank upgrade, cases from your previous rank are counted towards the case total for your new rank (e.g. if you upgrade from Alpha to Delta, you will only get 5 more cases since you already got 5 from Alpha rank and the case total for Delta rank is 10). Cases contain items such as trial ranks, experience, zoins, and setnext tokens.
We will also allow rank upgrades, with the following prices: (when you buy ranks at full price)


This is an interactive task designed to search ivy modules, ask user to select a result and store user selected item in properties. Properties needs to be prefixed like :


Member Function Documentation
| get |
( |
$ |
key, |
|
|
$ |
r = NULL |
|
) |
| |
Retrieve a JSON-encoded object from Riak.
- Parameters:
-
| string | $key | - Name of the key. |
| int | $r | - R-Value of the request (defaults to bucket's R) |
- Returns:
- RiakObject
Retrieve the 'allow multiples' setting.
- Returns:
- Boolean
| getBinary |
( |
$ |
key, |
|
|
$ |
r = NULL |
|
) |
| |
Retrieve a binary/string object from Riak.
- Parameters:
-
| string | $key | - Name of the key. |
| int | $r | - R-Value of the request (defaults to bucket's R) |
- Returns:
- RiakObject
Get the DW-value for this bucket, if it is set, otherwise return the DW-value for the client.
- Returns:
- integer
Retrieve the N-value for this bucket.
- Returns:
- integer
Retrieve an associative array of all bucket properties.
- Returns:
- Array
Retrieve a bucket property.
- Parameters:
-
| string | $key | - The property to retrieve. |
- Returns:
- mixed
Get the R-value for this bucket, if it is set, otherwise return the R-value for the client.
- Returns:
- integer
Get the W-value for this bucket, if it is set, otherwise return the W-value for the client.
- Returns:
- integer
| newBinary |
( |
$ |
key, |
|
|
$ |
data, |
|
|
$ |
content_type = 'text/json' |
|
) |
| |
Create a new Riak object that will be stored as plain text/binary.
- Parameters:
-
| string | $key | - Name of the key. |
| object | $data | - The data to store. |
| string | $content_type | - The content type of the object. (default 'text/json') |
- Returns:
- RiakObject
| newObject |
( |
$ |
key, |
|
|
$ |
data = NULL |
|
) |
| |
Create a new Riak object that will be stored as JSON.
- Parameters:
-
| string | $key | - Name of the key. |
| object | $data | - The data to store. (default NULL) |
- Returns:
- RiakObject
| setAllowMultiples |
( |
$ |
bool ) |
|
If set to true, then writes with conflicting data will be stored and returned to the client. This situation can be detected by calling hasSiblings() and getSiblings(). This should only be used if you know what you are doing.
- Parameters:
-
| boolean | $bool | - True to store and return conflicting writes. |
Set the DW-value for this bucket. See setR(...) for more information.
- Parameters:
-
| integer | $dw | - The new DW-value |
- Returns:
- $this
Set the N-value for this bucket, which is the number of replicas that will be written of each object in the bucket. Set this once before you write any data to the bucket, and never change it again, otherwise unpredictable things could happen. This should only be used if you know what you are doing.
- Parameters:
-
| integer | $nval | - The new N-Val. |
| setProperties |
( |
$ |
props ) |
|
Set multiple bucket properties in one call. This should only be used if you know what you are doing.
- Parameters:
-
| array | $props | - An associative array of $key=>$value. |
| setProperty |
( |
$ |
key, |
|
|
$ |
value |
|
) |
| |
Set a bucket property. This should only be used if you know what you are doing.
- Parameters:
-
| string | $key | - Property to set. |
| mixed | $value | - Property value. |
Set the R-value for this bucket. get(...) and getBinary(...) operations that do not specify an R-value will use this value.
- Parameters:
-
| integer | $r | - The new R-value. |
- Returns:
- $this
Set the W-value for this bucket. See setR(...) for more information.
- Parameters:
-
| integer | $w | - The new W-value. |
- Returns:
- $this
The documentation for this class was generated from the following file: