Electronic structure calculations
Eigenvalue problems hold an important role in the study of
the electronic structure of many-body systems. Exploiting the Density
Functional Theory (DFT) framework, the solution
of the all-electron Schr $\ddot{o}$dinger equation is replaced by a
one-electron Schr $\ddot{o}$dinger equation with an effective potential
which leads to a nonlinear eigenvalue problem, known as the Kohn-Sham
equation:
\begin{equation} \label{eq:kseq}
- \left[\frac{\nabla^2}{2} + V_{ion}(r) + V_H(\rho(r), r) + V_{XC}(\rho(r), r)\right] \Psi_i(r) = E_i \Psi_i(r)
\end{equation}
where $\Psi_i(r)$ is a wave function and $E_i$ is a Kohn-Sham
eigenvalue. The ionic potential $V_{ion}$
reflects contributions from the core and depends on
the position $r$ only. Both the Hartree and the Exchange-Correlation potentials
depend on the charge density:
\begin{equation}\label{eq:rho}
\rho(r) = 2 \sum_{i=1}^{n_{occ}} |\Psi_i(r)|^2,
\end{equation}
where $n_{occ}$ is the number of occupied states (for most systems of
interest this is half the number of valence electrons).
Since the total potential $V_{total} = V_{ion}+V_H + V_{XC}$
depends on $\rho(r)$ which itself depends on eigenfunctions of the
Hamiltonian, Equation (\ref{eq:kseq}) can be viewed
as a nonlinear eigenvalue problem or a nonlinear eigenvector problem.
The Hatree potential $V_H$ is obtained from
$\rho$ by solving the Poisson equation $ \nabla^2 V_H(r) = -4 \pi \rho(r)$
with appropriate boundary conditions. The Exchange-Correlation term $V_{XC}$
is the key to the DFT approach and it captures the effects of reducing
the problem from many particles to a one-electron problem, i.e.,
from replacing wavefunctions with many coordinates into ones that
depend solely on space location $r$.
Self-consistent iterations for solving the Kohn-Sham equation start with
an initial guess of the charge density $\rho(r)$, from which a guess for
$V_{total}$ is computed. Then (\ref{eq:kseq}) is solved for $\Psi_i(r)$'s and a new $\rho(r)$ is obtained
from (\ref{eq:rho}) and the potentials are updated.
Then (\ref{eq:kseq}) is solved again for a new $\rho$ obtained from
the new $\Psi_i(r)$'s,
and the process is repeated until the total potential has
converged.
A typical electronic structure calculation with many atoms requires
the calculation of a large number of eigenvalues, specifically the
$n_{occ}$ leftmost ones. In addition, calculations based on
Time-Dependent Density Functional Theory,
require a substantial
number of unoccupied states, states beyond the Fermi level, in addition
to the occupied ones.
Thus, it is not uncommon to see eigenvalue problems
in the size of millions where (tens) of thousands of eigenvalues may be
needed.
A 3-unit carbon nanotube (3-CNT) molecule.
This image appears in the paper "PFEAST: A High Performance Sparse Eigenvalue Solver Using Distributed-Memory Linear Solvers".
One can also "attack" the problem without using pseudopotentials, i.e., using an all-electron (full potential)
approach where the effect of core electrons is explicitly included in the model.
Finite element modal and frequency response analysis
Engineering structures have a set of natural frequencies (the frequency at which a
structure tends to oscillate in the absence of any external force). If a structure is excited by an
external force whose frequency is close to a natural frequency, the structure starts oscillating
and the amplitude of the vibration increases manyfold (i.e., resonance takes place). Frequency response
analysis describes how a structure responds to a prescribe load over a range of frequencies, and allows
to determine its resonance behavior. Ideally, forced and natural frequencies should not be close
(see here for an example
of resonance).
Assuming a closed domain without damping, the frequency response function is
often modeled as the solution of the following linear system:
\begin{equation}
K-\omega^2 M = f, \label{modan}
\end{equation}
where $K$ and $M$ are symmetric matrices known as the stiffness and mass matrix, respectively.
The right-hand side $f$ represents the force applied to the structure. Variable
$\omega$ represents the frequency of interest, and, typically, takes values within a
frequency band $\Omega=[\omega_l,\omega_u]$. The standard approach of solving
equation (\ref{modan}) for all different frequency instances becomes
computationally intractable for modern Finite Element models since the size of the stiffness and
mass matrices can easily be in the order of millions.
An alternative is to project equation (\ref{modan}) on a low-dimensional subspace, drastically
reducing the dimension of the problem,
and compute the frequency response of the projected structure for as many frequency instances as
necessary, instead. The most commonly used choice is to form the aforementioned
low-dimensional subspace by the eigenvectors of the matrix pancil $(K,M)$ which correspond to
eigenvalues which magnitude is located within a certain region on the real axis. The latter
leads to the necessity to partially solve an eigenvalue problem of the form $Kx=\lambda M x$.
Matrix $M$ is positive-definite, while the accuracy sought for the eigenpairs is of the order
of the discretization error of the FE model.


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Pacific Crest Marathon
Sunriver OR/USA
Website: aasportsltd.com/event/pacificcrest
Race Winners
(21 runnings)
23 Jun
2007
24 Jun
2006
25 Jun
2005
26 Jun
2004
28 Jun
2003
29 Jun
2002
2001
2000
1999
1998
1997
Notes: 1997 is believed to have been the inaugural year. The times for
2016 are net times.
25 Jun
2017
2:47:45
Chris McIsaac (USA)
3:23:38
Lindsay Brunsma (USA)
25 Jun
2016
2:54:52
David Harkin (OR/USA)
3:38:36
Kate Willette (OR/USA)
27
Jun
2015
3:19:53
Albert Hesse (ID/USA)
3:44:18
Amber Hertz (WI/USA)
28
Jun
2014
3:01:55
Larry Sanderson (CA/USA)
3:16:00
Karla Hoggard (OR/USA)
29
Jun
2013
2:45:13
Brendan Lunty-2
3:25:50
Ashley Hall (ID/USA)
23 Jun
2012
2:45:13
Brendan Lunty (AB/CAN)
3:34:28
Tamara Starr (OR/USA)
25 Jun
2011
2:49:39
Chuck Engle-2
3:34:32
Catherine Fisse (CA/USA)
26 Jun
2010
2:58:33
Holden Rennaker (OR/USA)
3:10:02
Sabine Pullins (GER)
27 Jun
2009
2:59:06
Brian Baker (ID/USA)
3:18:20
Lori Buratto (WA/USA)
28 Jun
2008
3:08:29
J J Howard (OR/USA)
3:19:37
Erica Johnson (OR/USA)
2:56:32
Ruslan Tkebuchava (WA/USA)
3:22:49
Becky Hacker (OR/USA)
2:49:08
Chuck Engle (OR/USA)
3:11:14
Dru Carpenter (OR/USA)
3:09:28
Greg Walchli (WA/USA)
3:09:54
Ann-Marie Thiesen (WA/USA)
3:01:01
Murray Thorson (WA/USA)
3:20:58
Eva Lust (WA/USA)
2:59:40
Lee Goodwin (ID/USA)
3:18:13
Jennifer Sventek (OR/USA)
2:37:45
Andy Martin (OR/USA)
3:33:54
Lynn Jacobs (OR/USA)
---
n/a
---
n/a
---
n/a
---
n/a
---
n/a
---
n/a
---
n/a
---
n/a
---
n/a
---
n/a
Most Wins
(1997/date)
Men
2
Chuck Engle (OR/USA)
2006,2011
Brendan Lunty (AB/CAN)
2012-13
Women
No woman has won more than once, according to
available information.
Prize Money (ADR qualified runners) Year Men Women Total 2016 $1,700 $1,000 $2,700
Race Time Bias
(sec/km)
Insufficient data to calculate the race time bias.
Competitive Level
(1990-date)
Insufficient data to calculate the competitive level.
Quality Performances
Men no men under 2:20 Women no women under 2:50
Finishers
Year Men Women M+F 2017 34 15 49 2016 51 34 85 2015 35 38 73 2014 57 60 117 2013 67 79 146 2012 60 71 131 2011 87 84 171 2010 109<PHONE_NUMBER> 104 78 182 2008 93 58 151 2007 74 64 138 2006 66 61 127 2005 70 59 129 2004 72 61 133 2003 70 59 129 2002 48 29 77 Sums 1097 955 2052 M/F 1.15
Last Updated on 26 Jun 2017


--- layout: page permalink: /publication/ ---
Rishabh Misra, Mengting Wan, Julian McAuley, "Decomposing Fit Semantics for Product Size Recommendation in Metric Spaces", in Proc. of 2018 ACM Conference on Recommender Systems (RecSys'18), Vancouver, Canada, Oct. 2018.


Experiment Page
Full Page
Map division Page
GPS Data(/gpsdatas)
This is an example paragraph. Anything in the body tag will appear on the page, just like this p tag and its contents.
{{message}}
{% for image in message %}
- ID: "{{image.id}}", ("{{image.longitude}}","{{image.latitude}}"), Name: "{{image.name}}", Description: "{{image.description}}", URL: "{{image.photo.url}}"
{% endfor %}


Just a student and junior programmer, who's live in Jakarta (Indonesia)
HTML :
CSS :
JavaScript :
C++ :
Restaurant Menu


- add_limit!
- add_limit_offset!
- begin_db_transaction
- commit_db_transaction
- default_sequence_name
- delete
- execute
- insert
- reset_sequence!
- rollback_db_transaction
- select_all
- select_one
- select_value
- select_values
- transaction
- update
Alias for add_limit_offset!.
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 75 75: def add_limit!(sql, options) 76: add_limit_offset!(sql, options) if options 77: end
Appends LIMIT and OFFSET options to a SQL statement. This method modifies the sql parameter.
Examples
add_limit_offset!('SELECT * FROM suppliers', {:limit => 10, :offset => 50})
generates
SELECT * FROM suppliers LIMIT 10 OFFSET 50
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 85 85: def add_limit_offset!(sql, options) 86: if limit = options[:limit] 87: sql << " LIMIT #{limit}" 88: if offset = options[:offset] 89: sql << " OFFSET #{offset}" 90: end 91: end 92: end
Begins the transaction (and turns off auto-committing).
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 65 65: def begin_db_transaction() end
Commits the transaction (and turns on auto-committing).
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 68 68: def commit_db_transaction() end
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 94 94: def default_sequence_name(table, column) 95: nil 96: end
Executes the delete statement and returns the number of rows affected.
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 40 40: def delete(sql, name = nil) end
Executes the SQL statement in the context of this connection. This abstract method raises a NotImplementedError.
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 29 29: def execute(sql, name = nil) 30: raise NotImplementedError, "execute is an abstract method" 31: end
Returns the last auto-generated ID from the affected table.
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 34 34: def insert(sql, name = nil, pk = nil, id_value = nil, sequence_name = nil) end
Set the sequence to the max value of the table’s column.
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 99 99: def reset_sequence!(table, column, sequence = nil) 100: # Do nothing by default. Implement for PostgreSQL, Oracle, ... 101: end
Rolls back the transaction (and turns on auto-committing). Must be done if the transaction block raises an exception or returns false.
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 72 72: def rollback_db_transaction() end
Returns an array of record hashes with the column names as keys and column values as values.
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 6 6: def select_all(sql, name = nil) 7: end
Returns a record hash with the column names as keys and column values as values.
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 11 11: def select_one(sql, name = nil) 12: end
Returns a single value from a record
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 15 15: def select_value(sql, name = nil) 16: result = select_one(sql, name) 17: result.nil? ? nil : result.values.first 18: end
Returns an array of the values of the first column in a select:
select_values("SELECT id FROM companies LIMIT 3") => [1,2,3]
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 22 22: def select_values(sql, name = nil) 23: result = select_all(sql, name) 24: result.map{ |v| v.values.first } 25: end
Wrap a block in a transaction. Returns result of block.
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 43 43: def transaction(start_db_transaction = true) 44: transaction_open = false 45: begin 46: if block_given? 47: if start_db_transaction 48: begin_db_transaction 49: transaction_open = true 50: end 51: yield 52: end 53: rescue Exception => database_transaction_rollback 54: if transaction_open 55: transaction_open = false 56: rollback_db_transaction 57: end 58: raise 59: end 60: ensure 61: commit_db_transaction if transaction_open 62: end
Executes the update statement and returns the number of rows affected.
[ show source ]
# File vendor/rails/activerecord/lib/active_record/connection_adapters/abstract/database_statements.rb, line 37 37: def update(sql, name = nil) end


Yars' Revenge tells the story of a race of radioactive mutant flies
(ah, what a surprise) as they struggle to defeat the Qotile, some sort
of evil-ish thing that blew up a planet belonging to the Yars.
 The thing is surrounded by a red energy shield that you blow
apart in bits and chunks. Once enough of it is gone, you can trigger
the "Zorlon Cannon" (science fiction terms at their best!) to destroy
it. Basically, it sits on the other side of the screen and follows your
vertical movement. You then hit the fire button to launch the missile.
The trick is, the Qotile and its shield are constantly moving, so you
have to time your shot. Because the missile follows your every move,
you have to get out of the way before it nails you.
A direct hit destroys the Qotile, and induces a colorful, full-screen, seizure-inducing explosion. Pretty cool.
So, right now, this seems like an easy game. But really, what makes it
hard is something I haven't yet disclosed, which is the destroyer
missile.
 At first it's not that bad, as you can take plenty of solid shots
at the shield before you have to reposition. However, a lot of the
game's difficulty centers around the missile; in later levels, the
thing moves so dang fast you only get one or two shots in a most before
you have to reposition your Yar to prevent getting hit. Thankfully, the
game allows you to wrap around the screen.  Though while you're in there you can't
shoot, so it's a fair trade-off.
The Qotile also has another, minor attack, called a swirl. Every
thirty-something seconds the thing turns into a swirl that launches
itself at you. It's pretty easy to dodge, since the Neutral Zone
doesn't keep you safe from it.
So, once you get deep into the game, it's insanely hard (and takes
considerably longer to beat with each level), what with the funny
rectangles chasing you and whatnot. Heck, some levels are Neutral
Zone-less even, which means there's no where to hide... dun dun dun.
Graphically, the game is simple but good. The game takes place in
space, where everything is black. The explosions and Neutral Zone
however, show off some pretty sweet color effects (try looking at a
screenshot). Your Yar is a pretty simple looking dragonfly-kinda thing.
It doesn't look like what they show in the comics (a four-armed
humanoid fly), but it still looks great. As it moves, it flaps its
wings in a two frame animation. Nice touch.
The Qotile is basically this pretzel-shaped thing. There's a comic
based on this (eleven whole pages) that makes it looks like a city on a
planet. So it's a moving fortress? Who knows.. it's evil anyway.
The game's background music is this constant humming that gives the
game a good sense of atmosphere. There's also sounds to accompany
shooting the Qotile shield and blowing the thing up.
Being an Atari 2600 game, as well as an incredibly common one, it's
very easy to find this game for less than a buck, especially in game
lots on sites like eBay (I once had five copies of the game). So if
you're out looking for 2600s or games for it and don't have this, find
it. It's great.


{% load filters %}
{% include './shared/modal.html' %}
{% include './shared/navigation.html' %}
{% include './shared/footer.html' %}


--- layout: post date: 2011-02-23 time: "09:00:00" authors: ["Greg Wilson"] title: Ask, And Ye Shall Receive tags: ["Content"] ---
Thanks to Elango Cheran, we now have an episode on the secure shell—yay!


Want to trade in your old sneakers for a custom pair fo Forcefields? Make a case for why your shoes have got to go and you may be one of ten lucky winners.


{% extends "search.html" %} {% block user_pref %}{{ user_pref|safe }}{% endblock %} {% block body_onload %}TypeSummary.init(){% endblock %} {% block title %}{{ title }}{% endblock %} {% block right_pane_content %}
Overview for {{ title }} |
|
Total Gigawatt Hours Generated and CO2 Emitted (Tonnes) |
|
Cumulative Capacity vs Years (Country Aggregate) |
|
New Capacity Added vs Years (Country Aggregate) |
|
Data as Table |
|


*Please use computer or labtop for best experience
CRAZE
I’ll take a one way ticket back to the 90s by presenting 4 style of fashion and cool things which make it’s the decade that never ended.
Overview of this decade. As the 20th century came to a close, fashion reached its most casual. Both men and women adopted grunge fashion in the early part of the decade and loose, oversized clothing and jeans became staples.
CASUAL. DRESS. GRUNGE. PLAID. CASUAL. DRESS. GRUNGE. PLAID.
PLAID. CASUAL. DRESS. GRUNGE. PLAID. CASUAL. DRESS. GRUNGE.
B
A
C
K
I N
I N
T
O
1990S
OVERSIZED SWEATER
BAGGY JEANS
SNEAKER
BAGGY JEANS
SNEAKER
“ It was born of a desire to not engage with fashion at all.”
CASUAL
In the 1990s fashion became more and more casual. Jeans and oversize sweater became typical casualwear as trends in music like grunge, hip-hop and Britpop influenced styles throughout the decade.
Discman
When the Sony Discman made CDs portable in the '90s, it was like the future had finally arrived. Sure, the music skipped whenever the Discman was even slightly jostled, but it was still a huge revelation.
SLIP DRESS
“ In the mid-nineties, styles became more feminine again.”
DRESS
Slip dresses epitomized the minimalist look during this period. Silky versions were worn as formalwear while a popular daytime look was a slip dress over a white t-shirt.
Tamagotchi
Raise an adorable pet alive in your pocket. Tamagotchis were so addictive among kids in the '90s that some schools actually banned them because students would skip class to "feed" their handheld digital pets.
Baggy Jeans
flannel shirts
Dr. Martens boots
flannel shirts
Dr. Martens boots
“ The desire for vintage clothing encouraged the spread of second-hand clothing stores”
GRUNGE
Second-hand clothing stores which were also used for the grunge fashion. it was a widespread look that was based on everyday clothing.
Bart Simpsons
Bart Simpson "Eat My Shorts" T-shirt was an act of rebellious defiance.  It's the one look that everybody in the '90s, regardless of their personal aesthetics, could agree on.
Clueless
The movie that create the lifestyle bible of the 90s teenager which illustrate that they were full with determination and they want to be loved by their friends.These thing carry on to each generation of teenagers.
CRAZE
CRAZE is a personal passion project during
internship with 5lab. Made for celebrating the iconic 90s fashion through an visual design piece.
Design & Developement
Arocha Tippayakrisorn
Photographs, References
Model photographs are souse from vogue.com and a special thanks to all photographers whose work is used
(Online)Karina Reddy. Fashion History Timeline.
Published on Sep 24 2020, souse from fashionhistory.fitnyc.edu


/fast-checkbox>
Work center
Object status
Document class
ID for documents and relations
File size (in bytes)
Flag for binary files/fast-checkbox>
Line number in internal table
Line number in internal table
Relative storage location of physical document
HTML content type
Component attribute for the application
Document Type
Document number
Document version
Document part
Short Description
ID for documents and relations
Name of person responsible
Time of change (UTC)
Name of person responsible
Time of change (UTC)
Structure name o API table extension
Data part of BAPI extension parameter
Data part of BAPI extension parameter
Data part of BAPI extension parameter
Data part of BAPI extension parameter
UTC Time Stamp in Short Form (YYYYMMDDhhmmss)
Time Zone
User Name in User Master Record
Text Line
Text for Note
Notification No
Consecutive Number of Activity
Item Number in Item Record
Catalog Type - Activities
Code Group - Activities
Activity Code
Activity Text
Name of Person who Created the Object
Date on Which Record Was Created
Name of person who changed object
Date of Last Change
Start Date
End Date
Object Long Text Available
Primary language indicator for text segment
Start Time of Activity
End Time of Activity
Time, at Which Record Was Added
Time of Change
Delete Data Record
Sort Number for Activity
Short Description of the Code Group
Activity Code Short Text
Notification No
Item Number in Item Record
Sequential Number for Cause
Name of Person who Created the Object
Date on Which Record Was Created
Name of person who changed object
Date of Last Change
Cause Text
Catalog Type - Causes
Code Group - Causes
Cause Code
Object Long Text Available
Primary language indicator for text segment
Time, at Which Record Was Added
Time of Change
Delete Data Record
Sort Number for Cause
Short Description of the Code Group
Cause Code Short Text
Object number
Partner Function
Counter for differentiation 6-digit
Object Category
Partner
Data origin indicator
Date on Which Record Was Created
Time, at Which Record Was Added
Name of Person who Created the Object
Date of Last Change
Time of Change
Name of person who changed object
Delete Data Record
Address number
Time Zone for Partner
Notification No
Sequential Task Number
Catalog Type - Tasks
Code Group - Tasks
Task Code
Short Text for Task
Name of Person who Created the Object
Date on Which Record Was Created
Name of person who changed object
Date of Last Change
Planned Start Date
Planned finish date
Object Number for Status Management
Object Long Text Available
Primary language indicator for text segment
Planned Start Time for Task
Planned Finish Time for Task
Person Who Completed the Task
Date on Which the Task Was Completed
Time at Which Task Was Completed
Date on Which Task Was Resubmitted
Item Number in Item Record
Time, at Which Record Was Added
Time of Change
Function of Person Responsible for Task
Person Responsible for Task (Partner Number)
Delete Data Record
Sort Number for Task
Short Description of the Code Group
Task Code Short Text
System Status for Notification
User Status Active/fast-checkbox>
Field displaying user status
Notification No
Item Number in Item Record
Name of Person who Created the Object
Date on Which Record Was Created
Name of person who changed object
Date of Last Change
Notification Item Short Text
Catalog Type - Problems/Defects
Code Group - Problem
Problem or Damage Code
Catalog Type - Object Parts
Code Group - Object Parts
Part of Object
Assembly
Object Long Text Available
Primary language indicator for text segment
Time, at Which Record Was Added
Time of Change
Delete Data Record
Sort Number for Item
Short Description of the Code Group
Problem Code Short Text
Short Description of the Code Group
Object Part Code Short Text
Classification
Class Description
Internal Class Number
Character field of length 40
Class Type
Long Material Number for Field ASSEMBLY
External GUID for ASSEMBLY Field
Version Number for ASSEMBLY Field
Start Point
End Point
Length
Unit of Measurement for Linear Data
Unit of Measurement for Linear Data in ISO Code
Type of First Offset
Value of Offset 1
Unit of Measurement for Offset 1
Unit of Measurement for Offset 1 in ISO Code
Type of Second Offset
Value of Offset 2
Unit of Measurement for Offset 2
Unit of Measurement for Offset 2 in ISO Code
First Offset Type Description
Second Offset Type Description
Equipment Number
Description of Technical Object
Functional Location
Description of functional location
Marker for Start Point
Distance between Marker and Start Point
Marker for End Point
Length Spec for Distance between Marker and End Point
Unit for the Distance from Marker
Unit for the Distance from Marker in ISO Code
Assembly
Message type: S Success, E Error, W Warning, I Info, A Abort
Message Class
Message Number
Message Text
Application log: log number
Application log: Internal message serial number
Message Variable
Message Variable
Message Variable
Message Variable
Parameter Name
Lines in parameter
Field in parameter
Logical system from which message originates
System status
Individual status of an object (short form)
Object status


{% block head %}{% endblock %}
who's on
first
jump to a
random place
Search for a place
Search
remember — this is a simple full-text search tool and
not
a
proper geocoder
{% block content %}{% endblock %}


WHAT IS THISSTREAMING VIA EMBEDDED LINKS. YOUTUBE BACKLINKS FROM ORGANIC SITES WILL HELP INCREASE OUR VIEW COUNTS. |
WHAT TO DO1. Play all the embedded videos on this page2. BASIC YOUTUBE STREAMING RULE: Watch in 480p or above, with full volume, and in normal speed(you may mute your device instead) 3. Let the videos finish playing. 4. PLAY 2048 IF YOU'RE BORED 5. Once done, switch to the normal youtube streaming mode and watch other SVT videos. 6. Come back here and refresh the page. |
REMEMBERDON'T RELY ON THIS ALONE.  YOUTUBE BACKLINKS FROM ORGANIC SITES WILL HELP INCREASE OUR VIEW COUNTS. |
WHAT TO DO1. Play all the embedded videos on this page2. BASIC YOUTUBE STREAMING RULE: Watch in 480p or above, with full volume, and in normal speed(you may mute your device instead) 3. Let the videos finish playing. 4. PLAY 2048 IF YOU'RE BORED 5. Once done, switch to the normal youtube streaming mode and watch other SVT videos. 6. Come back here and refresh the page. |
REMEMBERDON'T RELY ON THIS ALONE. SWITCH BETWEEN STREAMING VIA EMBEDDED LINKS AND YOUTUBE STREAMING FROM TIME TO TIME.SCROLL DOWN FOR THE VIDEOS! |
How to play: Use your arrow keys to move the tiles. When two similar albums meet, they merge into a brand new album!
SEVENTEEN ALBUMS: 17 CARAT | BOYS BE | LOVE & LETTER | LOVE & LETTER REPACKAGED | GOING SEVENTEEN | AL1 | TEEN,AGE | DIRECTOR'S CUT | WE MAKE YOU | YOU MAKE MY DAY | YOU MADE MY DAWN | HAPPY ENDING | HIT DIGITAL SINGLE | AN ODE | FALLIN FLOWER | HENG:GARAE (HANA, DUL, SET, NET)
Created by : @lemonadecoups (twitter). A variant of gabrielecirulli's 2048.


The sparse-MVS leader-board is based on two datasets, DTU dataset and Tanks-and-Temples (T&T) dataset. The sparse MVS setting in our leader-board selects a small proportion of the camera views by consecutively sampling a view from every sparsity = n camera index, i.e., {1, n + 1, 2n + 1, · · · }. In reality, it is also practical to sample small-batches of images at sparse viewpoints, i.e., grouping batches of views with certain Batchsize at the previously defined sparse viewpoints with a certain Sparsity. When Sparsity = 3 and Batchsize = 1, the chosen camera indexes are 1 / 4 / 7 / 10 / · · · . When Sparsity = 3 and Batchsize = 2, the chosen camera indexes are 1,2 / 4,5 / 7,8 / 10,11 / · · · .
The figure below depicts the relationship between sparsity n and the average baseline angle θ averaging over all the ground-truth points in the 22 models of the DTU dataset and 8 models of the Tanks and Temples intermediate dataset respectively. Note that, for simplicity, only the nearest view pairs are considered to calculate the baseline angle statistics.
As the sparsity increases n = 1, ..., 11, the average baseline angle θ, defined by the intersected projection rays, gradually grows in a large range, e.g. reaching more than 70° in both DTU and T&T datasets. So this sparse-MVS setting is reasonable by not only covering various degrees of sparsity but also containing irregular sampling locations.
The relationship between sparsity and the average baseline angle on 22 models. See the paper SurfaceNet+ for more details.
The relationship between sparsity and the average baseline angle on 8 models of intermediate dataset.
The precision and recall have two metrics: the distance metric and the percentage metric. The distance metric is the original DTU dataset matlab code (download). The percentage metric is changed by the evaluation code provided by Tanks and Temples (download). The overall score for the percentage metric is measured as the f-score, and a similar measurement for the distance metric overall is given by the average of the mean precision and mean recall.


The click package is added to a queue to be processed. A bot will pick up the click and install it on a device of your choosing. The application is run and screenshots are taken. The screenshots and log files are emailed to you soon after.
How long does it take to run the app
Under best-case scenario a few minutes for the app to install, run and the email to arrive. If there's a long queue then you may have to wait a while.
What devices can apps be tested on?
Currently the LG Nexus 4 and Asus Nexus 7 (2013) devices are supported. More devices will be made available shortly.
What limits are there?
Currently applications uploaded will have the following restrictions:-
Apps must pass the same click review tools as used in the Ubuntu App Store
Devices have no gps, wifi or cellular access. We're evaluating how to provide this and may do in the future.
Webapps are rejected as they will require network access, which isn't available
Scopes are allowed, but their functionality may be limited given the lack of network access


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UFC 244 video: Dana White rants about Corey Anderson’s ‘crybaby bulls—t’
by Anton TabuenaCorey Anderson and the UFC seems to still have a bit of a strained relationship. This past week, the light heavyweight contender revealed that the promotion told him he didn’t move the needle enough to get big fights. Saturday night at UFC 244, Anderson completely derailed the hype-train behind Johnny Walker, knocking him out swiftly in the first round.
After the big win over the man many deemed as the next challenger to Jon Jones, Anderson demanded a title shot. He also said that if the UFC doesn’t want to offer him what he feels he has rightfully earned, they should just release him from his contract.
Dana White didn’t seem too happy to hear that.
“So he came in here very angry this week. All these conspiracy theories, we hate him, we this, that and everything else, all this crybaby bulls—t,” White said. “We’re trying to get him beat. We can’t get you beat. You can either win or you can’t. We like Walker better or whatever the stuff he was saying.
“No, some guys move faster than others, you’re telling us what you deserve. Show us what you deserve. Tonight you showed us. Got it. Message received. Now we know.”
While White acknowledged the big win over Walker, he didn’t guarantee a title shot for him next.
“Not one person clapped for him at the weigh-ins,” White said. “Walker got a pretty big pop when he came out. I’ll bet people will notice him next time, won’t they?  You did something. Now we’ll move on.
“I’m not saying you’re getting a title shot next or whatever. (Dominick) Reyes won too, impressively,” he said. “We’ll figure out what’s next for you.
“And when your contract is up, if you still don’t want to be here, you can do whatever you want to do. In the mean time, take the fights that we offer you. Pretty simple.”
With the KO over Walker, Anderson has now won four fights in a row. He’s had 14 fights with the UFC already dating back to 2014, where he has compiled a 10-4 record with the promotion and 13-4 overall.


Here are some of my favorite people!
These are my favorite icecreams, in order:
I really love teaching programming, and I want to help people who are unemployed or underemployed. That's why I founded Epicodus, a vocational school for aspiring programmers.
Thanks for reading about me!


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Summary
Amsterdam-West was built between roughly the end of the 19th century and 1960. It is the most densely populated borough of Amsterdam and hosts a variety of neighbourhoods and cultures.
Things to do
Look at user-submitted tasks for what you can do in Amsterdam-West!
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Nieuw-West
Nieuw-West is a sprawling, high-density suburban residential area in the west of Amsterdam. It is the most populous borough at over 150,000 inhabitants.
Zuid
Zuid is one of the most densely populated boroughs with 8,500 homes per square kilometer. It is home to the Museum Quarter and the Zuidas business district.
West
Amsterdam-West was built between roughly the end of the 19th century and 1960. It is the most densely populated borough of Amsterdam and hosts a variety of neighbourhoods and cultures.
Oost
Marked by bordering the Singelgracht, Amstel river and IJ lake, Oost is a diverse and colorful borough that is also home to the HvA.
Noord
Noord is seperated from the other boroughs of Amsterdam by the IJ lake, and is perfect for those who want to see a part of Amsterdam less crowded.
Zuidoost
Home to the Johan Cruyff Arena and surrounding entertainment and shopping district, Zuidoost is a multicultural borough that is an exclave of Amsterdam.
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Centrum is the historical city centre of Amsterdam and home to its most recognizable landmarks. For a classic Amsterdam experience, Centrum offers limitless possibilities.
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| DOSE: T+ 0:00 |
3 hits |
oral |
LSD |
(blotter / tab) |
| T+ 1:39 |
1 hit |
smoked |
Crack |
(powder / crystals) |
| T+ 1:55 |
1 hit |
smoked |
5-MeO-DMT |
(powder / crystals) |
Day 1: Two of my friends and I drove to CA, and got a hotel near Six Flags Magic Mountain. We brought 9 hits of acid, which was in the form of smarties, about 3/4 gram of crack, and some 5-MeO-DMT, which my friends didn't tell me about until it was too late.  Before this experience, I had only done acid once, with 2 hits, I tried crack once, about 1/4 g, and other than that I've only smoked weed. I hadn't even been on a roller coaster before this day.
We were all in a pretty good mood, but I was nervous because I was the least experienced one (with drugs and amusement parks).
Day 2:
7:00 am: We wake up, each take 3 hits of acid, and eat a small meal from the hotel. We load the crackpipe, and leave for the park.
7:28: We get to 6 flags, and start waiting in line. I start feeling nervous and jittery, but my friends don't feel anything yet.
7:46: We finally get to the front of the line, and the acid has begun to kick in for all of us. Visuals start about the same time we get through into the park.
8:02: We arrive at Superman:Ride of Steel, and start waiting. People offer us to cut, but we were just going to wait for the acid to kick in a little more, so we stay in the back of the line.
8:39: Arrive about 2 people towards the front, my friend gives me a cue to take a hit from the crack pipe. I hide the pipe under the big blanket and take a huge toke. I tried to hold it in, but my head started feeling way bigger and uncomfortable, so I blow out the smoke. I turn to look at my friends, and almost go blind. I see extremely bright lights, and noises seem to blend in this frightening groan. I started wondering if this really was the crack reacting with the acid, but I coudn't keep a train of thought going.
8:42: They say we can get on the ride. My friends have to pretty much drag me onto the ride as I'm gripping the wheelchair as if my life depended on it. I keep slipping in and out of reality, wondering if I'm really on the ride. The ride starts.
8:43: I just lose it. I feel like I'm going 10,000 mph through a void. I start screaming and crying. All my muscles tighten up, and I sweat like crazy. We get to the top and I start crying. We roll back down and wait to get off the ride.
8:46: My friends quickly get me onto the wheelchair and push me away from the crowds. I look down and notice I've wet my pants and puked all over myself (which I don't even remember doing). My face is still pouring with sweat and tears. My friends try to calm me down, giving me a soda and telling me everything will be OK.
8:55: My friends tell me that they mixed in some 5-MeO-DMT with the crack. I asked what it was, they said toad venom and explained it. They had to repeat a lot of stuff because their voices were distorted and I had to hear things 2 or 3 times to understand it.
9:00: I feel better, because I feel the 5-MeO-DMT wearing off. The acid is still running strong, and I still feel dirty from the body fluids. I see a crowd of people and I think they are laughing and pointing at me. They start to come closer, and I tell my friends to avoid the crowd. They look over, and told me that they were actually walking away.
9:12: My friends are still talking to me, and I ask what to do about my clothes. They said 'this might happen, we are prepared.'
They told me that there was one spare change of clothes that would fit any of us under the wheelchair. I thank them and now am a lot happier.
9:20: We go to where nobody can see us, I stand up, and bring the clothes into a bathroom, hoping nobody would be in there. There was only one person, and they looked at me, but didn't say anything
about the puke or pee. I quickly go into a stall and start undressing. After what seemed to be 4 hours, I finally get all my clothes on and join my friends.
9:35: I ask how long I took, he said 15 minutes. I put the dirty clothes and blanket under the wheelchair. I looked up at on of my friend's faces and stare.  He said 'be careful dude, your pupils are soooooo dialated.'
9:40: I ask my friend to ride the wheel chair. He said 'ok it's not too dirty.' Walking felt great. I apologized to my friends for wasting time getting dressed and what not, but they said it was cool, they were sorry for giving me 5-MeO without permission. We were all now in a mood where we feel like we need to apologize.
The rest of the day, we went on a few more rides, and my friends found places to take hits from the pipe before going on them. We each took 1 hit from the pipe and each went on a different ride while on the 5-MeO. I didn't go on any more roller coasters, but some other rides. When I waited for my friends I walked around trying to avoid people. I was very paranoid.
Day 3: I was very sore, especially my neck. This was probably because I tightened my muscles on the roller coasters. I will never go on a rollercoaster or take 5-MeO-DMT again (purposely!), but still might do acid to confront my problems.
Final note: I woudn't recommend doing any drugs on roller coasters, unless you like VERY intense stuff. I wouldn't recommend bringing a crack pipe to such a public place, much less smoking out of it. I was very lucky (some people may say unlucky) that I didn't get caught.
Experience Reports are the writings and opinions of the individual authors who submit them.
Some of the activities described are dangerous and/or illegal and none are recommended by Erowid.


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{% extends "osmaxx/base.html" %} {% load i18n %} {% load static %} {% block breadcrumb %} {{ block.super }}
OSMaxx (short for "OpenStreetMap Arbitrary Excerpt Export") cuts out OpenStreetMap (OSM) data, processes it to geospatial data structures, converts it to typical GIS file formats and offers those for download.
A product fact sheet (in German) is available.
All our code is open-source and contributions are welcome.
You can find the online documentation of the schema on GitHub: Export Schema Documentation.
These can be found in our separate downloads page.
All data used by OSMaxx comes directly or indirectly from OpenStreetMap:
The bulk of our input data (everything not listed separately below) is verbatim OpenStreetMap data, taken from our own regularly (about every two hours, depending on the current load) synchronized database import of the OpenStreetMap planet.
Please see whether it's already been reported on GitHub. If not, please file a new issue there.
OSMaxx has been developed by the Geometa Lab at the HSR University of Applied Sciences Rapperswil. The Geometa Lab team can be reached via email<EMAIL_ADDRESS>Be sure to visit our blog.
Geometa Lab ℅ Prof. Stefan Keller


Visit our site at http://www.entertainmentcruises.com
TREAT YOUR SWEET TO ROMANCE ON THE WATER.
The hip and contemporary Mystic Blue offers the most fun and romantic
Valentine’s experience in the entire city!
Join us all weekend long for:
A complimentary rose and champagne toast
Amazing views of the world-famous skyline
Tasty eats
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DJ beats for dancing with your special someone
Reserve by 1/31 and SAVE 15%.Just use promo code EARLYBIRD when
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We’re sure you’ll love being out on the water aboard fun Mystic Blue,
but don’t just take our word for it. Check out our most recent
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--- title: Garden Adventures layout: default ---
Garden Adventures are classes for children ages 4-12. Each class focuses on a different topic and seeks to help kids connect with plants while encouraging them to explore the wonders of the natural world. Classes are designed for parents or caregivers to attend and participate with their child. Limit one adult/caregiver per child.
REGISTRATION REQUIRED
NO INFANTS PLEASE
Session A: SATURDAY, APRIL 8 @ 10AM - 11:30AM
Session B: SATURDAY, APRIL 8 @ 1PM - 2:30PM
Did you know the Garden has over 230,000 daffodils? Join us as we investigate this unique flower and learn why it’s one of Red Butte’s favorite blooming bulbs. After we’ll head outside to explore a few of the different daffodil varieties growing in the Garden before returning to the Sprout House to create dazzling daffodil sun catchers.
Session A: SATURDAY, APRIL 8 @ 10AM - 11:30AM
SOLD OUT!
Session B: SATURDAY, APRIL 8 @ 1PM - 2:30PM
SOLD OUT!
Celebrate spring by planting a fairy garden in this special Garden Adventure! After learning what a fairy garden is and how to care for it, participants will work together to design, plant, and decorate the perfect tiny oasis for a fairy, gnome, or elf using small-scale plants and handcrafted accessories. Containers, plants, decorations, and more will be provided. Don’t miss out on this magical class!
Session A: SATURDAY, APRIL 29 @ 10AM - 11:30AM
Session B: SATURDAY, APRIL 29 @ 1PM - 2:30PM
What do rubber, chocolate, and charcoal all have in common? They all come from trees! Join us as we celebrate Arbor Day (April 28) and investigate the largest residents of the Garden. Together we’ll explore the world of trees and discover a few of the unique varieties found in the Garden, including gingkos, giant sequoias, paperbark maples, and more. At the end of class, we’ll plant live tree seedlings to take home.
Session A: SATURDAY, MAY 6 @ 10AM - 11:30AM
Session B: SATURDAY, MAY 6 @ 1PM - 2:30PM
Did you know butterflies play an important role in helping the Garden grow? Discover how these beautiful bugs help plants grow as we study the butterfly life cycle, go on a butterfly hunt in the Garden, and create butterfly feeders to hang in our home gardens.


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|
M480 BSP V3.05.005
The Board Support Package for M480 Series
|
#include <timer_reg.h>
Data Fields | |
| __IO uint32_t | CTL |
| __IO uint32_t | CMP |
| __IO uint32_t | INTSTS |
| __IO uint32_t | CNT |
| __I uint32_t | CAP |
| __IO uint32_t | EXTCTL |
| __IO uint32_t | EINTSTS |
| __IO uint32_t | TRGCTL |
| __IO uint32_t | ALTCTL |
| __IO uint32_t | PWMCTL |
| __IO uint32_t | PWMCLKSRC |
| __IO uint32_t | PWMCLKPSC |
| __IO uint32_t | PWMCNTCLR |
| __IO uint32_t | PWMPERIOD |
| __IO uint32_t | PWMCMPDAT |
| __IO uint32_t | PWMDTCTL |
| __I uint32_t | PWMCNT |
| __IO uint32_t | PWMMSKEN |
| __IO uint32_t | PWMMSK |
| __IO uint32_t | PWMBNF |
| __IO uint32_t | PWMFAILBRK |
| __IO uint32_t | PWMBRKCTL |
| __IO uint32_t | PWMPOLCTL |
| __IO uint32_t | PWMPOEN |
| __O uint32_t | PWMSWBRK |
| __IO uint32_t | PWMINTEN0 |
| __IO uint32_t | PWMINTEN1 |
| __IO uint32_t | PWMINTSTS0 |
| __IO uint32_t | PWMINTSTS1 |
| __IO uint32_t | PWMEADCTS |
| __IO uint32_t | PWMSCTL |
| __O uint32_t | PWMSTRG |
| __IO uint32_t | PWMSTATUS |
| __I uint32_t | PWMPBUF |
| __I uint32_t | PWMCMPBUF |
@addtogroup TIMER Timer Controller(TIMER) Memory Mapped Structure for TIMER Controller
Definition at line 26 of file timer_reg.h.
| TIMER_T::ALTCTL |
[0x0020] Timer Alternative Control Register
| Bits | Field | Descriptions |
| [0] | FUNCSEL | Function Selection
0 = Timer controller is used as timer function. 1 = Timer controller is used as PWM function. Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. |
Definition at line 1614 of file timer_reg.h.
| TIMER_T::CAP |
[0x0010] Timer Capture Data Register
| Bits | Field | Descriptions |
| [23:0] | CAPDAT | Timer Capture Data Register
When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. |
Definition at line 1610 of file timer_reg.h.
| TIMER_T::CMP |
[0x0004] Timer Comparator Register
| Bits | Field | Descriptions |
| [23:0] | CMPDAT | Timer Comparator Value
CMPDAT is a 24-bit compared value register When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. |
Definition at line 1607 of file timer_reg.h.
| TIMER_T::CNT |
[0x000c] Timer Data Register
| Bits | Field | Descriptions |
| [23:0] | CNT | Timer Data Register
Read operation. Read this register to get CNT value. For example: If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value. If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value. Write operation. Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. |
| [31] | RSTACT | Timer Data Register Reset Active (Read Only)
This bit indicates if the counter reset operation active. When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress Once the counter reset operation done, timer clear this bit to 0 automatically. 0 = Reset operation is done. 1 = Reset operation triggered by writing TIMERx_CNT is in progress. Note: This bit is read only. |
Definition at line 1609 of file timer_reg.h.
| TIMER_T::CTL |
[0x0000] Timer Control Register
| Bits | Field | Descriptions |
| [7:0] | PSC | Prescale Counter
Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter If this field is 0 (PSC = 0), then there is no scaling. Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. |
| [19] | INTRGEN | Inter-timer Trigger Mode Enable Control
Setting this bit will enable the inter-timer trigger capture function. The Timer0/2 will be in event counter mode and counting with external clock source or event Also, Timer1/3 will be in trigger-counting mode of capture function. 0 = Inter-Timer Trigger Capture mode Disabled. 1 = Inter-Timer Trigger Capture mode Enabled. Note: For Timer1/3, this bit is ignored and the read back value is always 0. |
| [20] | PERIOSEL | Periodic Mode Behavior Selection Enable Bit
0 = The behavior selection in periodic mode is Disabled. When user updates CMPDAT while timer is running in periodic mode, CNT will be reset to default value. 1 = The behavior selection in periodic mode is Enabled. When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list, If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. If updated CMPDAT value < CNT, CNT will be reset to default value. |
| [21] | TGLPINSEL | Toggle-output Pin Select
0 = Toggle mode output to TMx (Timer Event Counter Pin). 1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). |
| [22] | CAPSRC | Capture Pin Source Selection
0 = Capture Function source is from TMx_EXT (x= 0~3) pin. 1 = Capture Function source is from internal ACMP output signal User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source. |
| [23] | WKEN | Wake-up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 0 = Wake-up function Disabled if timer interrupt signal generated. 1 = Wake-up function Enabled if timer interrupt signal generated. |
| [24] | EXTCNTEN | Event Counter Mode Enable Bit
This bit is for external counting pin function enabled. 0 = Event counter mode Disabled. 1 = Event counter mode Enabled. Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. |
| [25] | ACTSTS | Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status. 0 = 24-bit up counter is not active. 1 = 24-bit up counter is active. Note: This bit may active when CNT 0 transition to CNT 1. |
| [28:27] | OPMODE | Timer Counting Mode Select
00 = The Timer controller is operated in One-shot mode. 01 = The Timer controller is operated in Periodic mode. 10 = The Timer controller is operated in Toggle-output mode. 11 = The Timer controller is operated in Continuous Counting mode. |
| [29] | INTEN | Timer Interrupt Enable Bit
0 = Timer time-out interrupt Disabled. 1 = Timer time-out interrupt Enabled. Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. |
| [30] | CNTEN | Timer Counting Enable Bit
0 = Stops/Suspends counting. 1 = Starts counting. Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. |
| [31] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Control (Write Protect)
0 = ICE debug mode acknowledgement effects TIMER counting. TIMER counter will be held while CPU is held by ICE. 1 = ICE debug mode acknowledgement Disabled. TIMER counter will keep going no matter CPU is held by ICE or not. Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
Definition at line 1606 of file timer_reg.h.
| __IO uint32_t TIMER_T::EINTSTS |
[0x0018] Timer External Interrupt Status Register
Definition at line 1612 of file timer_reg.h.
| TIMER_T::EXTCTL |
[0x0014] Timer External Control Register
| Bits | Field | Descriptions |
| [0] | CNTPHASE | Timer External Count Phase
This bit indicates the detection phase of external counting pin TMx (x= 0~3). 0 = A falling edge of external counting pin will be counted. 1 = A rising edge of external counting pin will be counted. |
| [3] | CAPEN | Timer External Capture Pin Enable Bit
This bit enables the TMx_EXT capture pin input function. 0 =TMx_EXT (x= 0~3) pin Disabled. 1 =TMx_EXT (x= 0~3) pin Enabled. |
| [4] | CAPFUNCS | Capture Function Selection
0 = External Capture Mode Enabled. 1 = External Reset Mode Enabled. Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field. Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately. |
| [5] | CAPIEN | Timer External Capture Interrupt Enable Bit
0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled. 1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled. Note: CAPIEN is used to enable timer external interrupt If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. |
| [6] | CAPDBEN | Timer External Capture Pin De-bounce Enable Bit
0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled. 1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled. Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. |
| [7] | CNTDBEN | Timer Counter Pin De-bounce Enable Bit
0 = TMx (x= 0~3) pin de-bounce Disabled. 1 = TMx (x= 0~3) pin de-bounce Enabled. Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. |
| [8:10] | ICAPSEL | Internal Capture Source Select
000 = Capture Function source is from internal ACMP0 output signal. 001 = Capture Function source is from internal ACMP1 output signal. 010 = Capture Function source is from HXT. 011 = Capture Function source is from LXT. 100 = Capture Function source is from HIRC. 101 = Capture Function source is from LIRC. 110 = Reserved. 111 = Reserved. Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. |
| [14:12] | CAPEDGE | Timer External Capture Pin Edge Detect
When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. 000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin. 001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin. 010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer. 011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer.. 110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin. 111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin. 100, 101 = Reserved. |
| [16] | ECNTSSEL | Event Counter Source Selection to Trigger Event Counter Function
0 = Event Counter input source is from TMx (x= 0~3) pin. 1 = Event Counter input source is from USB internal SOF output signal. |
| [31:28] | CAPDIVSCL | Timer Capture Source Divider
This bits indicate the divide scale for capture source divider 0000 = Capture source/1. 0001 = Capture source/2. 0010 = Capture source/4. 0011 = Capture source/8. 0100 = Capture source/16. 0101 = Capture source/32. 0110 = Capture source/64. 0111 = Capture source/128. 1000 = Capture source/256. 1001~1111 = Reserved. Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. * @var TIMER_T::EINTSTS xternal Interrupt Status Register ------------------------------------------------------------------------------ Descriptions :---- | |
| [0] | CAPIF | Timer External Capture Interrupt Flag
This bit indicates the timer external capture interrupt flag status. 0 = TMx_EXT (x= 0~3) pin interrupt did not occur. 1 = TMx_EXT (x= 0~3) pin interrupt occurred. Note1: This bit is cleared by writing 1 to it. Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. |
Definition at line 1611 of file timer_reg.h.
| TIMER_T::INTSTS |
[0x0008] Timer Interrupt Status Register
| Bits | Field | Descriptions |
| [0] | TIF | Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. 0 = No effect. 1 = CNT value matches the CMPDAT value. Note: This bit is cleared by writing 1 to it. |
| [1] | TWKF | Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer. 0 = Timer does not cause CPU wake-up. 1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. Note: This bit is cleared by writing 1 to it. |
Definition at line 1608 of file timer_reg.h.
| TIMER_T::PWMBNF |
[0x0068] Timer PWM Brake Pin Noise Filter Register
| Bits | Field | Descriptions |
| [0] | BRKNFEN | Brake Pin Noise Filter Enable Bit
0 = Pin noise filter detect of PWMx_BRAKEy Disabled. 1 = Pin noise filter detect of PWMx_BRAKEy Enabled. |
| [3:1] | BRKNFSEL | Brake Pin Noise Filter Clock Selection
000 = Noise filter clock is PCLKx. 001 = Noise filter clock is PCLKx/2. 010 = Noise filter clock is PCLKx/4. 011 = Noise filter clock is PCLKx/8. 100 = Noise filter clock is PCLKx/16. 101 = Noise filter clock is PCLKx/32. 110 = Noise filter clock is PCLKx/64. 111 = Noise filter clock is PCLKx/128. |
| [6:4] | BRKFCNT | Brake Pin Noise Filter Count
The fields is used to control the active noise filter sample time. Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT. |
| [7] | BRKPINV | Brake Pin Detection Control Bit
0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect. 1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect . |
| [17:16] | BKPINSRC | Brake Pin Source Select
00 = Brake pin source comes from PWM0_BRAKE0 pin. 01 = Brake pin source comes from PWM0_BRAKE1 pin. 10 = Brake pin source comes from PWM1_BRAKE0 pin. 11 = Brake pin source comes from PWM1_BRAKE1 pin. |
Definition at line 1628 of file timer_reg.h.
| TIMER_T::PWMBRKCTL |
[0x0070] Timer PWM Brake Control Register
| Bits | Field | Descriptions |
| [0] | CPO0EBEN | Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
0 = Internal ACMP0_O signal as edge-detect brake source Disabled. 1 = Internal ACMP0_O signal as edge-detect brake source Enabled. Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. Note2: This register is write protected. Refer toSYS_REGLCTL register. |
| [1] | CPO1EBEN | Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
0 = Internal ACMP1_O signal as edge-detect brake source Disabled. 1 = Internal ACMP1_O signal as edge-detect brake source Enabled. Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. Note2: This register is write protected. Refer toSYS_REGLCTL register. |
| [4] | BRKPEEN | Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)
0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled. 1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [7] | SYSEBEN | Enable System Fail As Edge-detect Brake Source (Write Protect)
0 = System fail condition as edge-detect brake source Disabled. 1 = System fail condition as edge-detect brake source Enabled. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [8] | CPO0LBEN | Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
0 = Internal ACMP0_O signal as level-detect brake source Disabled. 1 = Internal ACMP0_O signal as level-detect brake source Enabled. Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. Note2: This register is write protected. Refer toSYS_REGLCTL register. |
| [9] | CPO1LBEN | Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
0 = Internal ACMP1_O signal as level-detect brake source Disabled. 1 = Internal ACMP1_O signal as level-detect brake source Enabled. Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [12] | BRKPLEN | Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)
0 = PWMx_BRAKEy pin event as level-detect brake source Disabled. 1 = PWMx_BRAKEy pin event as level-detect brake source Enabled. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [15] | SYSLBEN | Enable System Fail As Level-detect Brake Source (Write Protect)
0 = System fail condition as level-detect brake source Disabled. 1 = System fail condition as level-detect brake source Enabled. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [17:16] | BRKAEVEN | PWM Brake Action Select for PWMx_CH0 (Write Protect)
00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output. 01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened. 10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened. 11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [19:18] | BRKAODD | PWM Brake Action Select for PWMx_CH1 (Write Protect)
00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output. 01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened. 10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened. 11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened. Note: This register is write protected. Refer toSYS_REGLCTL register. |
Definition at line 1630 of file timer_reg.h.
| TIMER_T::PWMCLKPSC |
[0x0048] Timer PWM Counter Clock Pre-scale Register
| Bits | Field | Descriptions |
| [11:0] | CLKPSC | PWM Counter Clock Pre-scale
The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1) If CLKPSC is 0, then there is no scaling in PWM counter clock source. |
Definition at line 1620 of file timer_reg.h.
| TIMER_T::PWMCLKSRC |
[0x0044] Timer PWM Counter Clock Source Register
| Bits | Field | Descriptions |
| [2:0] | CLKSRC | PWM Counter Clock Source Select
The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event. 000 = TMRx_CLK. 001 = Internal TIMER0 time-out or capture event. 010 = Internal TIMER1 time-out or capture event. 011 = Internal TIMER2 time-out or capture event. 100 = Internal TIMER3 time-out or capture event. Others = Reserved. Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. |
Definition at line 1619 of file timer_reg.h.
| TIMER_T::PWMCMPBUF |
[0x00a4] Timer PWM Comparator Buffer Register
| Bits | Field | Descriptions |
| [15:0] | CMPBUF | PWM Comparator Buffer Register (Read Only)
Used as CMP active register. |
Definition at line 1643 of file timer_reg.h.
| TIMER_T::PWMCMPDAT |
[0x0054] Timer PWM Comparator Register
| Bits | Field | Descriptions |
| [15:0] | CMP | PWM Comparator Register
PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert. |
Definition at line 1623 of file timer_reg.h.
| TIMER_T::PWMCNT |
[0x005c] Timer PWM Counter Register
| Bits | Field | Descriptions |
| [15:0] | CNT | PWM Counter Value Register (Read Only)
User can monitor CNT to know the current counter value in 16-bit period counter. |
| [16] | DIRF | PWM Counter Direction Indicator Flag (Read Only)
0 = Counter is active in down count. 1 = Counter is active up count. |
Definition at line 1625 of file timer_reg.h.
| TIMER_T::PWMCNTCLR |
[0x004c] Timer PWM Clear Counter Register
| Bits | Field | Descriptions |
| [0] | CNTCLR | Clear PWM Counter Control Bit
It is automatically cleared by hardware. 0 = No effect. 1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type. |
Definition at line 1621 of file timer_reg.h.
| TIMER_T::PWMCTL |
[0x0040] Timer PWM Control Register
| Bits | Field | Descriptions |
| [0] | CNTEN | PWM Counter Enable Bit
0 = PWM counter and clock prescale Stop Running. 1 = PWM counter and clock prescale Start Running. |
| [2:1] | CNTTYPE | PWM Counter Behavior Type
00 = Up count type. 01 = Down count type. 10 = Up-down count type. 11 = Reserved. |
| [3] | CNTMODE | PWM Counter Mode
0 = Auto-reload mode. 1 = One-shot mode. |
| [8] | CTRLD | Center Re-load
In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. |
| [9] | IMMLDEN | Immediately Load Enable Bit
0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. 1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP. Note: If IMMLDEN is enabled, CTRLD will be invalid. |
| [16] | OUTMODE | PWM Output Mode
This bit controls the output mode of corresponding PWM channel. 0 = PWM independent mode. 1 = PWM complementary mode. |
| [30] | DBGHALT | ICE Debug Mode Counter Halt (Write Protect)
If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. 0 = ICE debug mode counter halt disable. 1 = ICE debug mode counter halt enable. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [31] | DBGTRIOFF | ICE Debug Mode Acknowledge Disable Bit (Write Protect)
0 = ICE debug mode acknowledgement effects PWM output. PWM output pin will be forced as tri-state while ICE debug mode acknowledged. 1 = ICE debug mode acknowledgement disabled. PWM output pin will keep output no matter ICE debug mode acknowledged or not. Note: This register is write protected. Refer toSYS_REGLCTL register. |
Definition at line 1618 of file timer_reg.h.
| TIMER_T::PWMDTCTL |
[0x0058] Timer PWM Dead-Time Control Register
| Bits | Field | Descriptions |
| [11:0] | DTCNT | Dead-time Counter (Write Protect)
The dead-time can be calculated from the following two formulas: Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0. Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [16] | DTEN | Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)
Dead-time insertion function is only active when PWM complementary mode is enabled If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. 0 = Dead-time insertion Disabled on the pin pair. 1 = Dead-time insertion Enabled on the pin pair. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [24] | DTCKSEL | Dead-time Clock Select (Write Protect)
0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale. 1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale. Note: This register is write protected. Refer toSYS_REGLCTL register. |
Definition at line 1624 of file timer_reg.h.
| TIMER_T::PWMEADCTS |
[0x0090] Timer PWM EADC Trigger Source Select Register
| Bits | Field | Descriptions |
| [2:0] | TRGSEL | PWM Counter Event Source Select to Trigger EADC Conversion
000 = Trigger EADC conversion at zero point (ZIF). 001 = Trigger EADC conversion at period point (PIF). 010 = Trigger EADC conversion at zero or period point (ZIF or PIF). 011 = Trigger EADC conversion at compare up count point (CMPUIF). 100 = Trigger EADC conversion at compare down count point (CMPDIF). Others = Reserved. |
| [7] | TRGEN | PWM Counter Event Trigger EADC Conversion Enable Bit
0 = PWM counter event trigger EADC conversion Disabled. 1 = PWM counter event trigger EADC conversion Enabled. |
Definition at line 1638 of file timer_reg.h.
| TIMER_T::PWMFAILBRK |
[0x006c] Timer PWM System Fail Brake Control Register
| Bits | Field | Descriptions |
| [0] | CSSBRKEN | Clock Security System Detection Trigger PWM Brake Function Enable Bit
0 = Brake Function triggered by clock fail detection Disabled. 1 = Brake Function triggered by clock fail detection Enabled. |
| [1] | BODBRKEN | Brown-out Detection Trigger PWM Brake Function Enable Bit
0 = Brake Function triggered by BOD event Disabled. 1 = Brake Function triggered by BOD event Enabled. |
| [2] | RAMBRKEN | SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit
0 = Brake Function triggered by SRAM parity error detection Disabled. 1 = Brake Function triggered by SRAM parity error detection Enabled. |
| [3] | CORBRKEN | Core Lockup Detection Trigger PWM Brake Function Enable Bit
0 = Brake Function triggered by core lockup event Disabled. 1 = Brake Function triggered by core lockup event Enabled. |
Definition at line 1629 of file timer_reg.h.
| TIMER_T::PWMINTEN0 |
[0x0080] Timer PWM Interrupt Enable Register 0
| Bits | Field | Descriptions |
| [0] | ZIEN | PWM Zero Point Interrupt Enable Bit
0 = Zero point interrupt Disabled. 1 = Zero point interrupt Enabled. |
| [1] | PIEN | PWM Period Point Interrupt Enable Bit
0 = Period point interrupt Disabled. 1 = Period point interrupt Enabled. Note: When in up-down count type, period point means the center point of current PWM period. |
| [2] | CMPUIEN | PWM Compare Up Count Interrupt Enable Bit
0 = Compare up count interrupt Disabled. 1 = Compare up count interrupt Enabled. |
| [3] | CMPDIEN | PWM Compare Down Count Interrupt Enable Bit
0 = Compare down count interrupt Disabled. 1 = Compare down count interrupt Enabled. |
Definition at line 1634 of file timer_reg.h.
| TIMER_T::PWMINTEN1 |
[0x0084] Timer PWM Interrupt Enable Register 1
| Bits | Field | Descriptions |
| [0] | BRKEIEN | PWM Edge-detect Brake Interrupt Enable (Write Protect)
0 = PWM edge-detect brake interrupt Disabled. 1 = PWM edge-detect brake interrupt Enabled. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [8] | BRKLIEN | PWM Level-detect Brake Interrupt Enable (Write Protect)
0 = PWM level-detect brake interrupt Disabled. 1 = PWM level-detect brake interrupt Enabled. Note: This register is write protected. Refer toSYS_REGLCTL register. |
Definition at line 1635 of file timer_reg.h.
| TIMER_T::PWMINTSTS0 |
[0x0088] Timer PWM Interrupt Status Register 0
| Bits | Field | Descriptions |
| [0] | ZIF | PWM Zero Point Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter reaches zero. Note: This bit is cleared by writing 1 to it. |
| [1] | PIF | PWM Period Point Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. Note1: When in up-down count type, PIF flag means the center point flag of current PWM period. Note2: This bit is cleared by writing 1 to it. |
| [2] | CMPUIF | PWM Compare Up Count Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type. Note2: This bit is cleared by writing 1 to it. |
| [3] | CMPDIF | PWM Compare Down Count Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP. Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type. Note2: This bit is cleared by writing 1 to it. |
Definition at line 1636 of file timer_reg.h.
| TIMER_T::PWMINTSTS1 |
[0x008c] Timer PWM Interrupt Status Register 1
| Bits | Field | Descriptions |
| [0] | BRKEIF0 | Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
0 = PWMx_CH0 edge-detect brake event do not happened. 1 = PWMx_CH0 edge-detect brake event happened. Note1: This bit is cleared by writing 1 to it. Note2: This register is write protected. Refer toSYS_REGLCTL register. |
| [1] | BRKEIF1 | Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)
0 = PWMx_CH1 edge-detect brake event do not happened. 1 = PWMx_CH1 edge-detect brake event happened. Note1: This bit is cleared by writing 1 to it. Note2: This register is write protected. Refer toSYS_REGLCTL register. |
| [8] | BRKLIF0 | Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
0 = PWMx_CH0 level-detect brake event do not happened. 1 = PWMx_CH0 level-detect brake event happened. Note1: This bit is cleared by writing 1 to it. Note2: This register is write protected. Refer toSYS_REGLCTL register. |
| [9] | BRKLIF1 | Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)
0 = PWMx_CH1 level-detect brake event do not happened. 1 = PWMx_CH1 level-detect brake event happened. Note1: This bit is cleared by writing 1 to it. Note2: This register is write protected. Refer toSYS_REGLCTL register. |
| [16] | BRKESTS0 | Edge -detect Brake Status of PWMx_CH0 (Read Only)
0 = PWMx_CH0 edge-detect brake state is released. 1 = PWMx_CH0 at edge-detect brake state. Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. |
| [17] | BRKESTS1 | Edge-detect Brake Status of PWMx_CH1 (Read Only)
0 = PWMx_CH1 edge-detect brake state is released. 1 = PWMx_CH1 at edge-detect brake state. Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. |
| [24] | BRKLSTS0 | Level-detect Brake Status of PWMx_CH0 (Read Only)
0 = PWMx_CH0 level-detect brake state is released. 1 = PWMx_CH0 at level-detect brake state. Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. |
| [25] | BRKLSTS1 | Level-detect Brake Status of PWMx_CH1 (Read Only)
0 = PWMx_CH1 level-detect brake state is released. 1 = PWMx_CH1 at level-detect brake state. Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. |
Definition at line 1637 of file timer_reg.h.
| TIMER_T::PWMMSK |
[0x0064] Timer PWM Output Mask Data Control Register
| Bits | Field | Descriptions |
| [0] | MSKDAT0 | PWMx_CH0 Output Mask Data Control Bit
This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1). 0 = Output logic Low to PWMx_CH0. 1 = Output logic High to PWMx_CH0. |
| [1] | MSKDAT1 | PWMx_CH1 Output Mask Data Control Bit
This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1). 0 = Output logic Low to PWMx_CH1. 1 = Output logic High to PWMx_CH1. |
Definition at line 1627 of file timer_reg.h.
| TIMER_T::PWMMSKEN |
[0x0060] Timer PWM Output Mask Enable Register
| Bits | Field | Descriptions |
| [0] | MSKEN0 | PWMx_CH0 Output Mask Enable Bit
The PWMx_CH0 output signal will be masked when this bit is enabled The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. 0 = PWMx_CH0 output signal is non-masked. 1 = PWMx_CH0 output signal is masked and output MSKDAT0 data. |
| [1] | MSKEN1 | PWMx_CH1 Output Mask Enable Bit
The PWMx_CH1 output signal will be masked when this bit is enabled The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. 0 = PWMx_CH1 output signal is non-masked. 1 = PWMx_CH1 output signal is masked and output MSKDAT1 data. |
Definition at line 1626 of file timer_reg.h.
| TIMER_T::PWMPBUF |
[0x00a0] Timer PWM Period Buffer Register
| Bits | Field | Descriptions |
| [15:0] | PBUF | PWM Period Buffer Register (Read Only)
Used as PERIOD active register. |
Definition at line 1642 of file timer_reg.h.
| TIMER_T::PWMPERIOD |
[0x0050] Timer PWM Period Register
| Bits | Field | Descriptions |
| [15:0] | PERIOD | PWM Period Register
In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. In up and down count type: PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. In up-down count type: PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK. Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. |
Definition at line 1622 of file timer_reg.h.
| TIMER_T::PWMPOEN |
[0x0078] Timer PWM Pin Output Enable Register
| Bits | Field | Descriptions |
| [0] | POEN0 | PWMx_CH0 Output Pin Enable Bit
0 = PWMx_CH0 pin at tri-state mode. 1 = PWMx_CH0 pin in output mode. |
| [1] | POEN1 | PWMx_CH1 Output Pin Enable Bit
0 = PWMx_CH1 pin at tri-state mode. 1 = PWMx_CH1 pin in output mode. |
Definition at line 1632 of file timer_reg.h.
| TIMER_T::PWMPOLCTL |
[0x0074] Timer PWM Pin Output Polar Control Register
| Bits | Field | Descriptions |
| [0] | PINV0 | PWMx_CH0 Output Pin Polar Control Bit
The bit is used to control polarity state of PWMx_CH0 output pin. 0 = PWMx_CH0 output pin polar inverse Disabled. 1 = PWMx_CH0 output pin polar inverse Enabled. |
| [1] | PINV1 | PWMx_CH1 Output Pin Polar Control Bit
The bit is used to control polarity state of PWMx_CH1 output pin. 0 = PWMx_CH1 output pin polar inverse Disabled. 1 = PWMx_CH1 output pin polar inverse Enabled. |
Definition at line 1631 of file timer_reg.h.
| TIMER_T::PWMSCTL |
[0x0094] Timer PWM Synchronous Control Register
| Bits | Field | Descriptions |
| [1:0] | SYNCMODE | PWM Synchronous Mode Enable Select
00 = PWM synchronous function Disabled. 01 = PWM synchronous counter start function Enabled. 10 = Reserved. 11 = PWM synchronous counter clear function Enabled. |
| [8] | SYNCSRC | PWM Synchronous Counter Start/Clear Source Select
0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN. 1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN. Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0. Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. |
Definition at line 1639 of file timer_reg.h.
| TIMER_T::PWMSTATUS |
[0x009c] Timer PWM Status Register
| Bits | Field | Descriptions |
| [0] | CNTMAXF | PWM Counter Equal to 0xFFFF Flag
0 = Indicates the PWM counter value never reached its maximum value 0xFFFF. 1 = Indicates the PWM counter value has reached its maximum value. Note: This bit is cleared by writing 1 to it. |
| [16] | EADCTRGF | Trigger EADC Start Conversion Flag
0 = PWM counter event trigger EADC start conversion is not occurred. 1 = PWM counter event trigger EADC start conversion has occurred. Note: This bit is cleared by writing 1 to it. |
Definition at line 1641 of file timer_reg.h.
| TIMER_T::PWMSTRG |
[0x0098] Timer PWM Synchronous Trigger Register
| Bits | Field | Descriptions |
| [0] | STRGEN | PWM Counter Synchronous Trigger Enable Bit (Write Only)
PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting. Note: This bit is only available in TIMER0 and TIMER2. |
Definition at line 1640 of file timer_reg.h.
| TIMER_T::PWMSWBRK |
[0x007c] Timer PWM Software Trigger Brake Control Register
| Bits | Field | Descriptions |
| [0] | BRKETRG | Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)
Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. Note: This register is write protected. Refer toSYS_REGLCTL register. |
| [8] | BRKLTRG | Software Trigger Level-detect Brake Source (Write Only) (Write Protect)
Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. Note: This register is write protected. Refer toSYS_REGLCTL register. |
Definition at line 1633 of file timer_reg.h.
| TIMER_T::TRGCTL |
[0x001c] Timer Trigger Control Register
| Bits | Field | Descriptions |
| [0] | TRGSSEL | Trigger Source Select Bit
This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. 0 = Time-out interrupt signal is used to internal trigger EPWM, BPWM, PDMA, DAC, and EADC. 1 = Capture interrupt signal is used to internal trigger EPWM, BPWM, PDMA, DAC, and EADC. |
| [1] | TRGEPWM | Trigger EPWM and BPWM Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be as EPWM and BPWM counter clock source. 0 = Timer interrupt trigger EPWM and BPWM Disabled. 1 = Timer interrupt trigger EPWM and BPWM Enabled. Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM and BPWM counter clock source. If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM counter clock source. |
| [2] | TRGEADC | Trigger EADC Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. 0 = Timer interrupt trigger EADC Disabled. 1 = Timer interrupt trigger EADC Enabled. Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion. |
| [3] | TRGDAC | Trigger DAC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. 0 = Timer interrupt trigger DAC Disabled. 1 = Timer interrupt trigger DAC Enabled. Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC. If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC. |
| [4] | TRGPDMA | Trigger PDMA Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. 0 = Timer interrupt trigger PDMA Disabled. 1 = Timer interrupt trigger PDMA Enabled. Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. |
Definition at line 1613 of file timer_reg.h.


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Famous charactor, Gunma-chan


I’m a computer science student from the University of Texas at El Paso working as a research assistant in additive manufacturing. My aim is to develop solutions against some of the most complex problems in a constantly changing world.
Designed and managed database application using PHP and MySQL. Built computer-controlled systems for interpreting and altering the machine specific code of 3D printers using Python. Modified and improved existing computer code to ensure up to date technology and techniques are implemented. Composed materials for reports, presentations, and submissions to peer-reviewed project reports.
Tutored students individually and in small groups to reinforce learning concepts. Created new lab assignments based on course objectives. Drafted effective learning plans to address students' coding weaknesses and strengths. Coached and gave instructional support to students unable to attend regular classes.
Supervised, installed, operated, and performed maintenance on manual and automated telecommunications equipment that linked computers to networks. Automated message switching equipment, performed network troubleshooting, problem diagnosis, and tests. Provided desktop computer support which included diagnosing and resolving any workstation operating system software, application software, or hardware problems.
Currently I am in the developement of a system for path path-finding agents needed to navigate through a Computer Aided Design (CAD) model within Fusion 360. This priority routing system uses artificial intelligence to route circuits of components in 3D space. The goal of this project is to ultimaly reduce costs by implementing optimal paths and automating significant manual tasks.
Apart from being a research assistant, I enjoy most of my time listening, collecting, and creating music. When given the opportunity, I perfrom at local shows and do opening acts for world class artists.
Apart from music, I follow a number of fantasy genre manga and anime, I am a physics enthusiast, and I spend a large amount of my free time exploring the latest technology advancements in the artificial intelligence world.


Project background
With my background as a mental health therapist, it was my goal to build an application that I thought of prior to beginning as a developer.
The feeling reframer's idea is based on concepts borrowed from a psychological therapy approach known as Narrative Therapy. Narrative therapy is based on the post modern principle that our reality is created by the words we use to describe it.
As a therapist, I find work with people who come in with a limited emotional vocabulary, which making it difficlu to express theirselves accurately. Thus, it is important to be able to have synonyms to express accurately what is truly being felt.
Bio
Hello, my name is Matt St.Clair. I am an Air Force veteran and a mental health therapist, transitioning into the web development field. I am finishing a B.S. in computer applications development from Renton Technical College while also taking full stack web development courses at Codefellows code camp in Seattle. I enjoy front end as well as back end work but am especially fascinated with UX design and how it blends with my social sciences background. I also enjoy front-end work because it allows me to collaborate and create with clients.
Technical Experience
At codefellows, I have created web apps in HTML, CSS, and JavaScript in Atom using Chrome developer tools, and often working in groups, utilizing issues in GitHub and agile project workflow. At Renton Technical College, I work in Android and Visual Studios using object oriented programming as well as in multiple data base platforms to include MS Access, Excel, and Tableau. I am also the web content manager at Renton Area Youth and Family Services on their Wordpress site.


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I am passionate Web Designer with good command in HTML, CSS and Java Script. Also, I am creative graphic designer and enthusiastic techie. I have experienced in Python web frameworks like Django and Flask to provide a high level backend.
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The purpose of the project is to develop a prototype of Black Box for vehicle attributes checking from a user’s android phone which can be installed into any bike.
The objective of the project is to provide maximum details about the computer in network to the administrator on their mobile phone, so that admin can view and monitor all the machines in the network.


|
e-puck
1.0
|
Files | |
| file | e_calc_po3030k.c |
| Calculate the timing for the camera (two timers) | |
| file | e_po3030k.h |
| PO3030k library header (two timers) | |
| file | e_po6030k.h |
| PO6030k library header. | |
| file | e_po8030d.h |
| P08030d library header. | |
| file | e_timers.c |
| Manage camera's interrupts (two timers) | |
This driver expose most of the Po3030k camera interfaces. Some functions are usefull, some other not. But since this is not up to the driver to decide if a function is needed, I've exported almost all.
The architecture is quite simple. The driver keep a array where every known camera register is keept in memory. The configuration function only alter this array. When you call, for example e_po3030k_config_cam(), nothing is written on the camera, but only in the internal register representation.
To effectively write the register, you must call e_po3030k_write_cam_registers(). This is typically done after every configuration call and before acquire the first picture.
The camera is, by default, configured with the followin settings:
There is no default setting for the image size and color.
The maximum framerate ( without doing anything else than acquiring the picture ) vary with the subsampling and the color mode. Here are some framerates:
This driver is extremly sensible to interrupt latency, thus it use interrupt priority to be sure that the latencies are kepts low. The Timer4 and Timer5 interrupt priority are set at level 6 and interrupt nesting is enabled. The Timer4 interrupt use the "push.s" and "pop.s" instructions. You should not have any code using thoses two instructions when you use the camera. This include the _ISRFAST C macro. If you use them, some random and really hard to debug behavior will happen. You have been warned !
This example tell de driver to aquire 160x160 pixel picture from the camera 4x subsampling, thus resulting with a 40x40 pixel. The buffer as a size of 40*40*2 because RGB565 is a two bytes per pixel data format.
This example configure the camera to aquire a 320x8 pixel picture, but subsampled 2x in width and 4x in heigth, thus resulting in a 160*2 linear greyscale picture. It "emulate" a linear camera. This example tell the camera to to enable the vertical and horizontal mirror, and to set the average exposure to 100.
This driver expose the subset features bewteen the po6030k and po3030k camera interfaces.


Provides statistical tools for Bayesian structure learning in undirected graphical models for continuous, discrete, and mixed data. The package is implemented the recent improvements in the Bayesian graphical models literature, including Mohammadi and Wit (2015) <doi:10.1214/14-BA889>, Mohammadi et al. (2017) <doi:10.1111/rssc.12171>, and Dobra and Mohammadi (2018) <doi:10.1214/18-AOAS1164>. To speed up the computations, the BDMCMC sampling algorithms are implemented in parallel using OpenMP in C++.
| Version: | 2.53 |
| Imports: | Matrix, igraph |
| Published: | 2018-11-14 |
| Author: | Reza Mohammadi [aut, cre] , Ernst Wit [aut], Adrian Dobra [ctb] |
| Maintainer: | Reza Mohammadi <a.mohammadi at uva.nl> |
| License: | GPL-2 | GPL-3 [expanded from: GPL (≥ 2)] |
| URL: | https://www.uva.nl/profile/a.mohammadi |
| NeedsCompilation: | yes |
| Citation: | BDgraph citation info |
| Materials: | NEWS |
| In views: | Bayesian, HighPerformanceComputing, gR |
| CRAN checks: | BDgraph results |
| Reference manual: | BDgraph.pdf |
| Vignettes: |
BDgraph: An R Package for Bayesian Structure Learning in Graphical Models |
| Package source: | BDgraph_2.53.tar.gz |
| Windows binaries: | r-devel: BDgraph_2.53.zip, r-release: BDgraph_2.53.zip, r-oldrel: BDgraph_2.53.zip |
| OS X binaries: | r-release: BDgraph_2.53.tgz, r-oldrel: BDgraph_2.53.tgz |
| Old sources: | BDgraph archive |
| Reverse depends: | ssgraph |
| Reverse imports: | bmixture, bootnet, qgraph |
Please use the canonical form https://CRAN.R-project.org/package=BDgraph to link to this page.