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M480 BSP V3.05.005
The Board Support Package for M480 Series
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#include <uart_reg.h>
Data Fields | |
| __IO uint32_t | DAT |
| __IO uint32_t | INTEN |
| __IO uint32_t | FIFO |
| __IO uint32_t | LINE |
| __IO uint32_t | MODEM |
| __IO uint32_t | MODEMSTS |
| __IO uint32_t | FIFOSTS |
| __IO uint32_t | INTSTS |
| __IO uint32_t | TOUT |
| __IO uint32_t | BAUD |
| __IO uint32_t | IRDA |
| __IO uint32_t | ALTCTL |
| __IO uint32_t | FUNCSEL |
| __IO uint32_t | LINCTL |
| __IO uint32_t | LINSTS |
| __IO uint32_t | BRCOMP |
| __IO uint32_t | WKCTL |
| __IO uint32_t | WKSTS |
| __IO uint32_t | DWKCOMP |
@addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART) Memory Mapped Structure for UART Controller
Definition at line 26 of file uart_reg.h.
| UART_T::ALTCTL |
[0x002c] UART Alternate Control/Status Register
| Bits | Field | Descriptions |
| [3:0] | BRKFL | UART LIN Break Field Length
This field indicates a 4-bit LIN TX break field count. Note1: This break field length is BRKFL + 1. Note2: According to LIN spec, the reset value is 0xC (break field length = 13). |
| [6] | LINRXEN | LIN RX Enable Bit
0 = LIN RX mode Disabled. 1 = LIN RX mode Enabled. |
| [7] | LINTXEN | LIN TX Break Mode Enable Bit
0 = LIN TX Break mode Disabled. 1 = LIN TX Break mode Enabled. Note: When TX break field transfer operation finished, this bit will be cleared automatically. |
| [8] | RS485NMM | RS-485 Normal Multi-drop Operation Mode (NMM)
0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. 1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. Note: It cannot be active with RS-485_AAD operation mode. |
| [9] | RS485AAD | RS-485 Auto Address Detection Operation Mode (AAD)
0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. 1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. Note: It cannot be active with RS-485_NMM operation mode. |
| [10] | RS485AUD | RS-485 Auto Direction Function (AUD)
0 = RS-485 Auto Direction Operation function (AUD) Disabled. 1 = RS-485 Auto Direction Operation function (AUD) Enabled. Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. |
| [15] | ADDRDEN | RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode. 0 = Address detection mode Disabled. 1 = Address detection mode Enabled. Note: This bit is used for RS-485 any operation mode. |
| [17] | ABRIF | Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. 0 = No auto-baud rate interrupt flag is generated. 1 = Auto-baud rate interrupt flag is generated. Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]) |
| [18] | ABRDEN | Auto-baud Rate Detect Enable Bit
0 = Auto-baud rate detect function Disabled. 1 = Auto-baud rate detect function Enabled. Note : This bit is cleared automatically after auto-baud detection is finished. |
| [20:19] | ABRDBITS | Auto-baud Rate Detect Bit Length
00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. 01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. 10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. 11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. Note : The calculation of bit number includes the START bit. |
| [31:24] | ADDRMV | Address Match Value
This field contains the RS-485 address match values. Note: This field is used for RS-485 auto address detection mode. |
Definition at line 1833 of file uart_reg.h.
| UART_T::BAUD |
[0x0024] UART Baud Rate Divider Register
| Bits | Field | Descriptions |
| [15:0] | BRD | Baud Rate Divider
The field indicates the baud rate divider This filed is used in baud rate calculation The detail description is shown in Table 7.15-4. |
| [27:24] | EDIVM1 | Extra Divider for BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2 The detail description is shown in Table 7.15-4 |
| [28] | BAUDM0 | BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0 UART provides three baud rate calculation modes This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode The detail description is shown in Table 7.15-4. |
| [29] | BAUDM1 | BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1 UART provides three baud rate calculation modes This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode The detail description is shown in Table 7.15-4. Note: In IrDA mode must be operated in mode 0. |
Definition at line 1831 of file uart_reg.h.
| UART_T::BRCOMP |
[0x003c] UART Baud Rate Compensation Register
| Bits | Field | Descriptions |
| [8:0] | BRCOMP | Baud Rate Compensation Patten
These 9-bits are used to define the relative bit is compensated or not. BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. |
| [31] | BRCOMPDEC | Baud Rate Compensation Decrease
0 = Positive (increase one module clock) compensation for each compensated bit. 1 = Negative (decrease one module clock) compensation for each compensated bit. |
Definition at line 1837 of file uart_reg.h.
| UART_T::DAT |
[0x0000] UART Receive/Transmit Buffer Register
| Bits | Field | Descriptions |
| [7:0] | DAT | Data Receive/Transmit Buffer
Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation: By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. |
| [8] | PARITY | Parity Bit Receive/Transmit Buffer
Write Operation: By writing to this bit, the parity bit will be stored in transmitter FIFO If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. Read Operation: If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. |
Definition at line 1822 of file uart_reg.h.
| UART_T::DWKCOMP |
[0x0048] UART Incoming Data Wake-up Compensation Register
| Bits | Field | Descriptions |
| [15:0] | STCOMP | Start Bit Compensation Value
These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode. Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. |
Definition at line 1840 of file uart_reg.h.
| UART_T::FIFO |
[0x0008] UART FIFO Control Register
| Bits | Field | Descriptions |
| [1] | RXRST | RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. 0 = No effect. 1 = Reset the RX internal state machine and pointers. Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. |
| [2] | TXRST | TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. 0 = No effect. 1 = Reset the TX internal state machine and pointers. Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. |
| [7:4] | RFITL | RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 0000 = RX FIFO Interrupt Trigger Level is 1 byte. 0001 = RX FIFO Interrupt Trigger Level is 4 bytes. 0010 = RX FIFO Interrupt Trigger Level is 8 bytes. 0011 = RX FIFO Interrupt Trigger Level is 14 bytes. Others = Reserved. |
| [8] | RXOFF | Receiver Disable Bit
The receiver is disabled or not (set 1 to disable receiver). 0 = Receiver Enabled. 1 = Receiver Disabled. Note: This bit is used for RS-485 Normal Multi-drop mode It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. |
| [19:16] | RTSTRGLV | nRTS Trigger Level for Auto-flow Control Use
0000 = nRTS Trigger Level is 1 byte. 0001 = nRTS Trigger Level is 4 bytes. 0010 = nRTS Trigger Level is 8 bytes. 0011 = nRTS Trigger Level is 14 bytes. Others = Reserved. Note: This field is used for auto nRTS flow control. |
Definition at line 1824 of file uart_reg.h.
| UART_T::FIFOSTS |
[0x0018] UART FIFO Status Register
| Bits | Field | Descriptions |
| [0] | RXOVIF | RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. 0 = RX FIFO is not overflow. 1 = RX FIFO is overflow. Note: This bit can be cleared by writing '1' to it. |
| [1] | ABRDIF | Auto-baud Rate Detect Interrupt Flag
This bit is set to logic '1' when auto-baud rate detect function is finished. 0 = Auto-baud rate detect function is not finished. 1 = Auto-baud rate detect function is finished. Note: This bit can be cleared by writing '1' to it. |
| [2] | ABRDTOIF | Auto-baud Rate Detect Time-out Interrupt Flag
This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. 0 = Auto-baud rate counter is underflow. 1 = Auto-baud rate counter is overflow. Note: This bit can be cleared by writing '1' to it. |
| [3] | ADDRDETF | RS-485 Address Byte Detect Flag
0 = Receiver detects a data that is not an address bit (bit 9 ='0'). 1 = Receiver detects a data that is an address bit (bit 9 ='1'). Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. Note2: This bit can be cleared by writing '1' to it. |
| [4] | PEF | Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. 0 = No parity error is generated. 1 = Parity error is generated. Note: This bit can be cleared by writing '1' to it. |
| [5] | FEF | Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). 0 = No framing error is generated. 1 = Framing error is generated. Note: This bit can be cleared by writing '1' to it. |
| [6] | BIF | Break Interrupt Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). 0 = No Break interrupt is generated. 1 = Break interrupt is generated. Note: This bit can be cleared by writing '1' to it. |
| [13:8] | RXPTR | RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer When UART receives one byte from external device, RXPTR increases one When one byte of RX FIFO is read by CPU, RXPTR decreases one. The Maximum value shown in RXPTR is 15 When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0 As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15 |
| [14] | RXEMPTY | Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not. 0 = RX FIFO is not empty. 1 = RX FIFO is empty. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high It will be cleared when UART receives any new data. |
| [15] | RXFULL | Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not. 0 = RX FIFO is not full. 1 = RX FIFO is full. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. |
| [21:16] | TXPTR | TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer When CPU writes one byte into UART_DAT, TXPTR increases one When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. The Maximum value shown in TXPTR is 15 When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0 As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15 |
| [22] | TXEMPTY | Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not. 0 = TX FIFO is not empty. 1 = TX FIFO is empty. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high It will be cleared when writing data into UART_DAT (TX FIFO not empty). |
| [23] | TXFULL | Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not. 0 = TX FIFO is not full. 1 = TX FIFO is full. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. |
| [24] | TXOVIF | TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. 0 = TX FIFO is not overflow. 1 = TX FIFO is overflow. Note: This bit can be cleared by writing '1' to it. |
| [28] | TXEMPTYF | Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. 0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. 1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. |
| [29] | RXIDLE | RX Idle Status (Read Only)
This bit is set by hardware when RX is idle. 0 = RX is busy. 1 = RX is idle. (Default) |
| [31] | TXRXACT | TX and RX Active Status (Read Only)
This bit indicates TX and RX are active or inactive. 0 = TX and RX are inactive. 1 = TX and RX are active. (Default) Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared The UART controller can not transmit or receive data at this moment Otherwise this bit is set. |
Definition at line 1828 of file uart_reg.h.
| UART_T::FUNCSEL |
[0x0030] UART Function Select Register
| Bits | Field | Descriptions |
| [1:0] | FUNCSEL | Function Select
00 = UART function. 01 = LIN function. 10 = IrDA function. 11 = RS-485 function. |
| [3] | TXRXDIS | TX and RX Disable Bit
Setting this bit can disable TX and RX. 0 = TX and RX Enabled. 1 = TX and RX Disabled. Note: The TX and RX will not disable immediately when this bit is set The TX and RX complete current task before disable TX and RX When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. |
Definition at line 1834 of file uart_reg.h.
| UART_T::INTEN |
[0x0004] UART Interrupt Enable Register
| Bits | Field | Descriptions |
| [0] | RDAIEN | Receive Data Available Interrupt Enable Bit
0 = Receive data available interrupt Disabled. 1 = Receive data available interrupt Enabled. |
| [1] | THREIEN | Transmit Holding Register Empty Interrupt Enable Bit
0 = Transmit holding register empty interrupt Disabled. 1 = Transmit holding register empty interrupt Enabled. |
| [2] | RLSIEN | Receive Line Status Interrupt Enable Bit
0 = Receive Line Status interrupt Disabled. 1 = Receive Line Status interrupt Enabled. |
| [3] | MODEMIEN | Modem Status Interrupt Enable Bit
0 = Modem status interrupt Disabled. 1 = Modem status interrupt Enabled. |
| [4] | RXTOIEN | RX Time-out Interrupt Enable Bit
0 = RX time-out interrupt Disabled. 1 = RX time-out interrupt Enabled. |
| [5] | BUFERRIEN | Buffer Error Interrupt Enable Bit
0 = Buffer error interrupt Disabled. 1 = Buffer error interrupt Enabled. |
| [6] | WKIEN | Wake-up Interrupt Enable Bit
0 = Wake-up Interrupt Disabled. 1 = Wake-up Interrupt Enabled. |
| [8] | LINIEN | LIN Bus Interrupt Enable Bit
0 = LIN bus interrupt Disabled. 1 = LIN bus interrupt Enabled. Note: This bit is used for LIN function mode. |
| [11] | TOCNTEN | Receive Buffer Time-out Counter Enable Bit
0 = Receive Buffer Time-out counter Disabled. 1 = Receive Buffer Time-out counter Enabled. |
| [12] | ATORTSEN | nRTS Auto-flow Control Enable Bit
0 = nRTS auto-flow control Disabled. 1 = nRTS auto-flow control Enabled. Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. |
| [13] | ATOCTSEN | nCTS Auto-flow Control Enable Bit
0 = nCTS auto-flow control Disabled. 1 = nCTS auto-flow control Enabled. Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). |
| [14] | TXPDMAEN | TX PDMA Enable Bit
This bit can enable or disable TX PDMA service. 0 = TX PDMA Disabled. 1 = TX PDMA Enabled. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA transmit request operation is stop Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. |
| [15] | RXPDMAEN | RX PDMA Enable Bit
This bit can enable or disable RX PDMA service. 0 = RX PDMA Disabled. 1 = RX PDMA Enabled. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. |
| [18] | ABRIEN | Auto-baud Rate Interrupt Enable Bit
0 = Auto-baud rate interrupt Disabled. 1 = Auto-baud rate interrupt Enabled. |
| [22] | TXENDIEN | Transmitter Empty Interrupt Enable Bit
If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 0 = Transmitter empty interrupt Disabled. 1 = Transmitter empty interrupt Enabled. |
Definition at line 1823 of file uart_reg.h.
| UART_T::INTSTS |
[0x001c] UART Interrupt Status Register
| Bits | Field | Descriptions |
| [0] | RDAIF | Receive Data Available Interrupt Flag
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. 0 = No RDA interrupt flag is generated. 1 = RDA interrupt flag is generated. Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). |
| [1] | THREIF | Transmit Holding Register Empty Interrupt Flag
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. 0 = No THRE interrupt flag is generated. 1 = THRE interrupt flag is generated. Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). |
| [2] | RLSIF | Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set) If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. 0 = No RLS interrupt flag is generated. 1 = RLS interrupt flag is generated. Note1: In RS-485 function mode, this field is set include "receiver detect and received address byte character (bit9 = '1') bit" At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. |
| [3] | MODEMIF | MODEM Interrupt Flag (Read Only)
This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1) If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. 0 = No Modem interrupt flag is generated. 1 = Modem interrupt flag is generated. Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). |
| [4] | RXTOIF | RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]) If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. 0 = No RX time-out interrupt flag is generated. 1 = RX time-out interrupt flag is generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. |
| [5] | BUFERRIF | Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set) When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. 0 = No buffer error interrupt flag is generated. 1 = Buffer error interrupt flag is generated. Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). |
| [6] | WKIF | UART Wake-up Interrupt Flag (Read Only)
This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1. 0 = No UART wake-up interrupt flag is generated. 1 = UART wake-up interrupt flag is generated. Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. |
| [7] | LINIF | LIN Bus Interrupt Flag
This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] = 1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])) If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated. 0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. 1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). |
| [8] | RDAINT | Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 0 = No RDA interrupt is generated. 1 = RDA interrupt is generated. |
| [9] | THREINT | Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. 0 = No THRE interrupt is generated. 1 = THRE interrupt is generated. |
| [10] | RLSINT | Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 0 = No RLS interrupt is generated. 1 = RLS interrupt is generated. |
| [11] | MODEMINT | MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 0 = No Modem interrupt is generated. 1 = Modem interrupt is generated. |
| [12] | RXTOINT | RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 0 = No RX time-out interrupt is generated. 1 = RX time-out interrupt is generated. |
| [13] | BUFERRINT | Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. 0 = No buffer error interrupt is generated. 1 = Buffer error interrupt is generated. |
| [14] | WKINT | UART Wake-up Interrupt Indicator (Read Only)
This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 0 = No UART wake-up interrupt is generated. 1 = UART wake-up interrupt is generated. |
| [15] | LININT | LIN Bus Interrupt Indicator (Read Only)
This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. 0 = No LIN Bus interrupt is generated. 1 = The LIN Bus interrupt is generated. |
| [18] | HWRLSIF | PDMA Mode Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set) If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. 0 = No RLS interrupt flag is generated in PDMA mode. 1 = RLS interrupt flag is generated in PDMA mode. Note1: In RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = '1') bit". Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared |
| [19] | HWMODIF | PDMA Mode MODEM Interrupt Flag (Read Only)
This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1)) If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. 0 = No Modem interrupt flag is generated in PDMA mode. 1 = Modem interrupt flag is generated in PDMA mode. Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). |
| [20] | HWTOIF | PDMA Mode RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]) If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . 0 = No RX time-out interrupt flag is generated in PDMA mode. 1 = RX time-out interrupt flag is generated in PDMA mode. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. |
| [21] | HWBUFEIF | PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set) When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. 0 = No buffer error interrupt flag is generated in PDMA mode. 1 = Buffer error interrupt flag is generated in PDMA mode. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. |
| [22] | TXENDIF | Transmitter Empty Interrupt Flag
This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set) If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. 0 = No transmitter empty interrupt flag is generated. 1 = Transmitter empty interrupt flag is generated. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. |
| [26] | HWRLSINT | PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. 0 = No RLS interrupt is generated in PDMA mode. 1 = RLS interrupt is generated in PDMA mode. |
| [27] | HWMODINT | PDMA Mode MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. 0 = No Modem interrupt is generated in PDMA mode. 1 = Modem interrupt is generated in PDMA mode. |
| [28] | HWTOINT | PDMA Mode RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. 0 = No RX time-out interrupt is generated in PDMA mode. 1 = RX time-out interrupt is generated in PDMA mode. |
| [29] | HWBUFEINT | PDMA Mode Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 0 = No buffer error interrupt is generated in PDMA mode. 1 = Buffer error interrupt is generated in PDMA mode. |
| [30] | TXENDINT | Transmitter Empty Interrupt Indicator (Read Only)
This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. 0 = No Transmitter Empty interrupt is generated. 1 = Transmitter Empty interrupt is generated. |
| [31] | ABRINT | Auto-baud Rate Interrupt Indicator (Read Only)
This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 0 = No Auto-baud Rate interrupt is generated. 1 = The Auto-baud Rate interrupt is generated. |
Definition at line 1829 of file uart_reg.h.
| UART_T::IRDA |
[0x0028] UART IrDA Control Register
| Bits | Field | Descriptions |
| [1] | TXEN | IrDA Receiver/Transmitter Selection Enable Bit
0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) 1 = IrDA Transmitter Enabled and Receiver Disabled. |
| [5] | TXINV | IrDA Inverse Transmitting Output Signal
0 = None inverse transmitting signal. (Default). 1 = Inverse transmitting output signal. Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. |
| [6] | RXINV | IrDA Inverse Receive Input Signal
0 = None inverse receiving input signal. 1 = Inverse receiving input signal. (Default) Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. |
Definition at line 1832 of file uart_reg.h.
| UART_T::LINCTL |
[0x0034] UART LIN Control Register
| Bits | Field | Descriptions |
| [0] | SLVEN | LIN Slave Mode Enable Bit
0 = LIN slave mode Disabled. 1 = LIN slave mode Enabled. |
| [1] | SLVHDEN | LIN Slave Header Detection Enable Bit
0 = LIN slave header detection Disabled. 1 = LIN slave header detection Enabled. Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. |
| [2] | SLVAREN | LIN Slave Automatic Resynchronization Mode Enable Bit
0 = LIN automatic resynchronization Disabled. 1 = LIN automatic resynchronization Enabled. Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1). Note3: The control and interactions of this field are explained in <IP_ADDRESS> (Slave mode with automatic resynchronization). |
| [3] | SLVDUEN | LIN Slave Divider Update Method Enable Bit
0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time). 1 = UART_BAUD is updated at the next received character User must set the bit before checksum reception. Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). Note2: This bit used for LIN Slave Automatic Resynchronization mode (for Non-Automatic Resynchronization mode, this bit should be kept cleared) Note3: The control and interactions of this field are explained in <IP_ADDRESS> (Slave mode with automatic resynchronization). |
| [4] | MUTE | LIN Mute Mode Enable Bit
0 = LIN mute mode Disabled. 1 = LIN mute mode Enabled. Note: The exit from mute mode condition and each control and interactions of this field are explained in <IP_ADDRESS> (LIN slave mode). |
| [8] | SENDH | LIN TX Send Header Enable Bit
The LIN TX header can be break field or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). 0 = Send LIN TX header Disabled. 1 = Send LIN TX header Enabled. Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. |
| [9] | IDPEN | LIN ID Parity Enable Bit
0 = LIN frame ID parity Disabled. 1 = LIN frame ID parity Enabled. Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked. Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10 |
| [10] | BRKDETEN | LIN Break Detection Enable Bit
When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated. 0 = LIN break detection Disabled . 1 = LIN break detection Enabled. |
| [11] | LINRXOFF | LIN Receiver Disable Bit
If the receiver is enabled (LINRXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (LINRXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore. 0 = LIN receiver Enabled. 1 = LIN receiver Disabled. Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01). |
| [12] | BITERREN | Bit Error Detect Enable Bit
0 = Bit error detection function Disabled. 1 = Bit error detection function Enabled. Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. |
| [19:16] | BRKFL | LIN Break Field Length
This field indicates a 4-bit LIN TX break field count. Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). Note2: This break field length is BRKFL + 1. Note3: According to LIN spec, the reset value is 12 (break field length = 13). |
| [21:20] | BSL | LIN Break/Sync Delimiter Length
00 = The LIN break/sync delimiter length is 1-bit time. 01 = The LIN break/sync delimiter length is 2-bit time. 10 = The LIN break/sync delimiter length is 3-bit time. 11 = The LIN break/sync delimiter length is 4-bit time. Note: This bit used for LIN master to sending header field. |
| [23:22] | HSEL | LIN Header Select
00 = The LIN header includes 'break field'. 01 = The LIN header includes 'break field' and 'sync field'. 10 = The LIN header includes 'break field', 'sync field' and 'frame ID field'. 11 = Reserved. Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1). |
| [31:24] | PID | LIN PID Bits
This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1. If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). Note2: This field can be used for LIN master mode or slave mode. |
Definition at line 1835 of file uart_reg.h.
| UART_T::LINE |
[0x000c] UART Line Control Register
| Bits | Field | Descriptions |
| [1:0] | WLS | Word Length Selection
This field sets UART word length. 00 = 5 bits. 01 = 6 bits. 10 = 7 bits. 11 = 8 bits. |
| [2] | NSB | Number of 'STOP Bit'
0 = One 'STOP bit' is generated in the transmitted data. 1 = When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data. |
| [3] | PBE | Parity Bit Enable Bit
0 = Parity bit generated Disabled. 1 = Parity bit generated Enabled. Note: Parity bit is generated on each outgoing character and is checked on each incoming data. |
| [4] | EPE | Even Parity Enable Bit
0 = Odd number of logic '1's is transmitted and checked in each word. 1 = Even number of logic '1's is transmitted and checked in each word. Note: This bit has effect only when PBE (UART_LINE[3]) is set. |
| [5] | SPE | Stick Parity Enable Bit
0 = Stick parity Disabled. 1 = Stick parity Enabled. Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0 If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. |
| [6] | BCB | Break Control Bit
0 = Break Control Disabled. 1 = Break Control Enabled. Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0) This bit acts only on TX line and has no effect on the transmitter logic. |
| [7] | PSS | Parity Bit Source Selection
The parity bit can be selected to be generated and checked automatically or by software. 0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically. 1 = Parity bit generated and checked by software. Note1: This bit has effect only when PBE (UART_LINE[3]) is set. Note2: If PSS is 0, the parity bit is transmitted and checked automatically If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). |
| [8] | TXDINV | TX Data Inverted
0 = Transmitted data signal inverted Disabled. 1 = Transmitted data signal inverted Enabled. Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. |
| [9] | RXDINV | RX Data Inverted
0 = Received data signal inverted Disabled. 1 = Received data signal inverted Enabled. Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. |
Definition at line 1825 of file uart_reg.h.
| UART_T::LINSTS |
[0x0038] UART LIN Status Register
| Bits | Field | Descriptions |
| [0] | SLVHDETF | LIN Slave Header Detection Flag
This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. 0 = LIN header not detected. 1 = LIN header detected (break + sync + frame ID). Note1: This bit can be cleared by writing 1 to it. Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. |
| [1] | SLVHEF | LIN Slave Header Error Flag
This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. 0 = LIN header error not detected. 1 = LIN header error detected. Note1: This bit can be cleared by writing 1 to it. Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). |
| [2] | SLVIDPEF | LIN Slave ID Parity Error Flag
This bit is set by hardware when receipted frame ID parity is not correct. 0 = No active. 1 = Receipted frame ID parity is not correct. Note1: This bit can be cleared by writing 1 to it. Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]). |
| [3] | SLVSYNCF | LIN Slave Sync Field
This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. 0 = The current character is not at LIN sync state. 1 = The current character is at LIN sync state. Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1). Note2: This bit can be cleared by writing 1 to it. Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. |
| [8] | BRKDETF | LIN Break Detection Flag
This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. 0 = LIN break not detected. 1 = LIN break detected. Note1: This bit can be cleared by writing 1 to it. Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1). |
| [9] | BITEF | Bit Error Detect Status Flag
At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. 0 = Bit error not detected. 1 = Bit error detected. Note1: This bit can be cleared by writing 1 to it. Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1). |
Definition at line 1836 of file uart_reg.h.
| UART_T::MODEM |
[0x0010] UART Modem Control Register
| Bits | Field | Descriptions |
| [1] | RTS | nRTS (Request-to-send) Signal Control
This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. 0 = nRTS signal is active. 1 = nRTS signal is inactive. Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. |
| [9] | RTSACTLV | nRTS Pin Active Level
This bit defines the active level state of nRTS pin output. 0 = nRTS pin output is high level active. 1 = nRTS pin output is low level active. (Default) Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. |
| [13] | RTSSTS | nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status. 0 = nRTS pin output is low level voltage logic state. 1 = nRTS pin output is high level voltage logic state. |
Definition at line 1826 of file uart_reg.h.
| UART_T::MODEMSTS |
[0x0014] UART Modem Status Register
| Bits | Field | Descriptions |
| [0] | CTSDETF | Detect nCTS State Change Flag
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. 0 = nCTS input has not change state. 1 = nCTS input has change state. Note: This bit can be cleared by writing '1' to it. |
| [4] | CTSSTS | nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status. 0 = nCTS pin input is low level voltage logic state. 1 = nCTS pin input is high level voltage logic state. Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. |
| [8] | CTSACTLV | nCTS Pin Active Level
This bit defines the active level state of nCTS pin input. 0 = nCTS pin input is high level active. 1 = nCTS pin input is low level active. (Default) Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. |
Definition at line 1827 of file uart_reg.h.
| UART_T::TOUT |
[0x0020] UART Time-out Register
| Bits | Field | Descriptions |
| [7:0] | TOIC | Time-out Interrupt Comparator
The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]) Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]) In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255 So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. |
| [15:8] | DLY | TX Delay Time Value
This field is used to programming the transfer delay time between the last stop bit and next start bit The unit is bit time. |
Definition at line 1830 of file uart_reg.h.
| UART_T::WKCTL |
[0x0040] UART Wake-up Control Register
| Bits | Field | Descriptions |
| [0] | WKCTSEN | nCTS Wake-up Enable Bit
0 = nCTS Wake-up system function Disabled. 1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external. nCTS change will wake-up system from Power-down mode. |
| [1] | WKDATEN | Incoming Data Wake-up Enable Bit
0 = Incoming data wake-up system function Disabled. 1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,. incoming data will wake-up system from Power-down mode. |
| [2] | WKRFRTEN | Received Data FIFO Reached Threshold Wake-up Enable Bit
0 = Received Data FIFO reached threshold wake-up system function Disabled. 1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is. in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. |
| [3] | WKRS485EN | RS-485 Address Match (AAD Mode) Wake-up Enable Bit
0 = RS-485 Address Match (AAD mode) wake-up system function Disabled. 1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in. Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. |
| [4] | WKTOUTEN | Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
0 = Received Data FIFO reached threshold time-out wake-up system function Disabled. 1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the. system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up system from Power-down mode. Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. |
Definition at line 1838 of file uart_reg.h.
| UART_T::WKSTS |
[0x0044] UART Wake-up Status Register
| Bits | Field | Descriptions |
| [0] | CTSWKF | nCTS Wake-up Flag
This bit is set if chip wake-up from power-down state by nCTS wake-up. 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by nCTS wake-up. Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. |
| [1] | DATWKF | Incoming Data Wake-up Flag
This bit is set if chip wake-up from power-down state by data wake-up. 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by Incoming Data wake-up. Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. |
| [2] | RFRTWKF | Received Data FIFO Reached Threshold Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up . 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up. Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. |
| [3] | RS485WKF | RS-485 Address Match (AAD Mode) Wake-up Flag
This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up. Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. |
| [4] | TOUTWKF | Received Data FIFO Threshold Time-out Wake-up Flag
This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out. wake-up. Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. Note2: This bit can be cleared by writing '1' to it. |
Definition at line 1839 of file uart_reg.h.


Hey, thanks for stopping by. I am an Interaction Designer interested in utilizing digital technologies to solve problems big and small. I am currently disrupting traditional business practices and building kick-ass applications as a Product Designer at Nasdaq OMX. I earned my MFA in Design and Technology at Parsons The New School for Design, where I focused on developing social interfaces to foster interdisciplinary collaboration and product development. I am an international award winning mobile and product designer, and recently have presented at a handful of international conferences (see the full list below).
I am currently seeking an opportunity leading Product and Interaction Design.
Check me out on Twitter, github and LinkedIn, and feel free to reach out at tami [dot] evnin [at] gmail.
Nasdaq
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Lead a team to plan strategy for multi-product integration. Evaluate current product offerings for better interface and interaction opportunities. Design, prototype, and implement front-end user experience proposals. Establish and maintain front-end pattern library.
Skills: Leadership, HTML5, CSS3 (LESS), JavaScript (jQuery, custom), Adobe CS6
The New School
New York, NY
August 2011
Developed Introduction to the Processing Programming Language course curriculum with a team of seven teachers for the Parsons MFA D+T Bootcamp. Implemented curriculum through daily lessons which spanned 15 2.5 hour classes over three weeks.
Simple (formerly BankSimple)
New York, NY
May 2011 to July 2011
Worked with Research Director to design and develop internal analytics tool and internal press archive. Designed landing pages and developed strategy for multivariate user testing.
Skills: HTML5, CSS3, JavaScript (jQuery, MooTools, custom), Ruby on Rails
New York Economic Development Corporation (NYCEDC)
New York, NY
January 2011 to May 2011
Updated content on internal and external company websites and managed microsites. Compiled marketing assets to develop an interactive display and experience of company projects.
Skills: HTML, CSS, JavaScript (jQuery, MooTools, custom)
Parsons The New School for Design
2012
University of California, Berkeley
2009
UX Speakeasy: Redux
San Diego, CA
November 2014
Asbury Agile
Asbury Park, NJ
October 2014
Forge Conference
Philadelphia, PA
October 2014
Information Architecture (IA) Summit
San Diego, CA
March 2014
Agile
Nashville, TN
August 2013
WebVisions NYC
New York, NY
April 2014
(sponsored by EPFL+ECAL Lab in partnership with ENSCI-Les Ateliers, Royal College of Art, and Parsons The New School for Design)
Project selected for exhibition and commercialization, 2012
(sponsored by Samsung Mob!le and Twitter)
Austin, TX
Featured Artist, 2012
(sponsored by 7scenes)
Amsterdam, NL
Winner, 2011


Deep learning has permeated just about every industry, and its impact on our lives will only continue to grow. It is the driving force behind technologies such as machine translation, autonomous driving, and speech recognition. While deep learning is not a brand new technology, recent developments in computing hardware, especially GPUs, have made training deep neural networks (DNNs) on large datasets feasible. The tech behemoths (Google, Amazon, Facebook, Microsoft) have all invested huge amounts of money into developing their artificial intelligence arms (and they are not the only ones). Consequently, there is a great demand for talent in the field. If you believe deep learning is of interest to you, please check out some of Clemson students' showcases made possible by deep learning.
Check It OutCan you guess the real image? Try out this interactive showcase that uses Caffe and Cuda to colorize grayscale images.
Made by: Jake Roose and Kylon Tyner
Generate psychedelic images algorithmically! This showcase warps Death Valley into a trippy stadium using the Google DeepDream algorithm and the Tensorflow framework.
Made by: Angelo Carrabba


PickerField
can display an entity instance and perform actions represented by buttons on the right.
You can link the component with an entity attribute by specifying dataContainer
and property
XML attributes. The entity attribute should be a reference to another entity.


Unit 3, Week 8 Cultural Blogpost
Questions
Wednesday February 18, 2015
Finding the perfect question is a difficult quest to embark on. Part of a great question is looking for a specific answer. Another part is doing research before asking the question. An informed question is easier to understand and will therefore solicit better answers.


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Portable
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Predictions
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Multiple description mode
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Recommendations:
Priority Histogram
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Wont Fix Pie Chart
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Ludwig Favre, Born in France in 1976, in north of Paris.
Ludwig Favre is a Photographer specializing in major cities and landscapes of america, raised in Paris, currently living in Paris. He has created visuals on a variety of media platforms from advertising campaigns to magazine editorials, books, galleries over the world.


TXmlRpcProtocol class
TXmlRpcProtocol is a class that implements XML-Rpc protocol in TRpcService. It's basically a wrapper to the xmlrpc_server_* family of php methods.
Located in /Web/Services/TRpcService.php (line 615)
TRpcProtocol | --TXmlRpcProtocol
Constructor
Destructor
Registers a new RPC method and handler details
Handles the RPC request
Turns the given exception into an XML RPC fault
Sets the correct response headers
Decodes XML encoded data into PHP data
Encodes PHP data into XML data
Inherited From TRpcProtocol
TRpcProtocol::addMethod()
TRpcProtocol::callApiMethod()
TRpcProtocol::callMethod()
TRpcProtocol::createErrorResponse()
TRpcProtocol::createResponseHeaders()
TRpcProtocol::decode()
TRpcProtocol::encode()
Documentation generated on Sat, 19 Jan 2013 13:03:47 +0100 by phpDocumentor 1.4.3


The latest stable version of Ruby is 3.0.1. You can try Ruby in your browser at https://try.ruby-lang.org, or select from any number of installation options described below:
$ sudo apt-get install ruby-full
$ sudo yum install ruby
The Snap package manager is developed by Canonical and provides the ability to switch between various channels.
$ sudo snap install ruby --classic
-- switching between channels --
$ sudo snap switch ruby --channel=2.3/stable
$ sudo snap refresh
$ sudo pacman -S ruby
$ brew install ruby
$ pkg install ruby
(Refer to the Ruby installation guide for additional help.)
Return to topIf the version of Ruby for your particular system is out of date, you may choose to use an installer; many support switching between versions. If you choose to use RVM as a version manager, no additional installer is required.
ruby-buildThis is a plugin for rbenv which allows for compiling and installing multiple versions of Ruby. It is available for macOS, Linux, and other UNIX-like OSs.
ruby-installInstaller which allows compiling and installing multiplier versions of Ruby into arbitrary target directories. The complementary tool chruby allows users to switch between Ruby versions. Available for macOS, Linux, and other UNIX-like OSs.
RubyInstallerWindows installer providing a full Ruby development environment.
RubyStackIf you intend to install Ruby to use Ruby on Rails, this installer provides a complete development environment and supports macOS, Linux, Windows, virtual machines, and cloud images.
Return to topManagers allow for ease or automatic switching between Ruby versions depending on project and other advantages, but are not officially supported.
asdf-vmExtendable version manager supporting multiple languages.
chrubyProvides support for switching being Ruby versions installed by ruby-install or build from source.
rbenvManages multiple installations but lacks the ability to install Ruby itself.
RVM (“Ruby Version Manager”) uruLightweight, multi-platform command line tool which supports most OSs.
Return to topFinally, you can install Ruby from the source once downloaded and unpacked.
$ ./configure
$ make
$ sudo make install
The default install location for Ruby is /usr/local.
Return to topRuby Interpreters: What You Need to Know is an article discussing a number of interpreters available for Ruby; YARV, Ruby MRI, JRuby, and Rubinius
Return to top


This project aims to work as a start point for your Angular projects. It is a collection of configuration and scaffolded source files.
Browser: AngularJS, Angular UI Bootstrap, Angular UI Router, Restangular, LoDash, Alertify.js
Server: Express.js, Grunt.js, Browserify


To be continued in Stroopy's next adventures…
Can't wait? Browse a summary of SCP. Get summary Or get involved with Stellar


← Home
The sum of the numbers 1 to n
Go
The sum of the numbers 1 to
is
.
Provide a number to see the sum.


Before Change
def load_best_model(self):
return model with best accuracy
model_id = max(self.history, key=lambda x: x["accuracy"])["model_id"]
return load_model(os.path.join(self.path, str(model_id) + ".h5"))
def add_model(self, model, x_train, y_train, x_test, y_test):
add one model while will be trained to history list
After Change
def load_best_model(self):
return model with best accuracy
return self.load_model_by_id(max(self.history, key=lambda x: x["accuracy"])["model_id"])
def add_model(self, model, x_train, y_train, x_test, y_test):
add one model while will be trained to history list


| Data |
Open |
Load a CmdsFile and open an animation. A IconDir must set before. |
|
Close |
Close an animation. |
|
IconDir |
Set an icon directory. |
|
Exit |
Close the viewer application. |
| Simulation |
Start |
Start the animation. |
|
Pause |
Pause the animation. |
|
Stop |
Stop the animation. |
|
SetSpeed |
Set speedfactor. |
|
TimeFlowMode |
Set TimeFlowMode. |
| View |
Zoom |
Set zoomfactor of actual view. |
| Help |
Help |
This menue. |
|
About Simulation Project |
Some information about the actual simulation model. |
|
About Simulation Framework |
Some information about the DESMO-J simulation framework. |


Simulacrum Installation / Pedro Henrique
- Curated by Matheus Pereira
- about 14 hours
Installations & Structures · Santa Maria da Feira, Portugal
- version="1.0" encoding="UTF-8"? Architects: Pedro Henrique
- version="1.0" encoding="UTF-8"?YearCompletion year of this architecture project Year: 2019
- version="1.0" encoding="UTF-8"?PhotographsPhotographs: Ivo Tavares Studio
- version="1.0" encoding="UTF-8"?ManufacturersBrands with products used in this architecture project Manufacturers: Tintas Neuce
- Author Pedro Henrique
- Co-authors André Rocha, João Silva, Margarida Pais, Rafaela Silva, Teresa Leite
- Metal Structure Entreferros Serralharia Construções Metálicas, Lda. (Jorge Silva)
- Cargo Net Structure Carlos Sousa, Lda.
- Painting Tintas Neuce
More Specs Less Specs
Text description provided by the architects. Simulacro aims to awaken the senses and the imagination of the passerby to the heart of the city of Santa Maria da Feira, where the Caster River runs every day. Like him, we walk past the city without observing it. This is an unconscious act common to all of us that manage ourselves by a schedule, activity, commitment, or purpose.
During the design process we rediscover the course of this river that unravels the core of one of the oldest blocks of the city. This core reveals what we dare to call non-place, because it is not the result of a plan of its own but rather the result of everything that happens around it.
This non-place has both remnant and potentiality and therefore we intend to temporarily transform it into a (ephemeral) space, giving it conditions to create permanence. Therefore, the first goal of this intervention is to transform non-place into an ephemeral space of being.
This ephemeral space causes permanence that triggers observation and contemplation. When we allow ourselves to truly observe, we allow ourselves to understand what surrounds us, to imagine about this reality, to form criticism, to reflect.
To do so, we put an accessible safety net over the river. Once in the net, the public is hovering over the river - a natural reflector that generates innumerable points of view. Each of them can be a different trigger of thoughts and therefore of criticism and reflection.
Simulacro (it could be reality) starts from the vision of a group of architects who, through the discipline of architecture intend to transform non-place into an ephemeral space and foster reflection and criticism about the public's claim of public space.


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Guidance
Mathematics test materials administered to eligible pupils at the end of key stage 2 in May 2016.
Key stage 2 mathematics tests administered in schools in May 2016. Test administration instructions and mark schemes are also provided.
Please refer to the copyright ownership report for details of how schools, educational establishments and third parties can use these materials.


...I couldn't think of a catchy title.
Me in natural habitat.
I like to know it's a rollercoaster before I get in line.
A shortcoming, imperfection, or lack.
When we say, 'Defect Free Software'. We're using a shorthand for saying that we want our software without shortcomings or imperfections.
Complexity produces software defects
'Controlling complexity is the essence of computer programming.' -Brian Kernighan
Types of Complexity:
If you changed your entire architecture, essential complexity would remain unaltered, but accidental complexity may vary significantly.
Software with no defects that is still 'fit to purpose', is high quality software.
Since reducing complexity lowers the defect rate, doing so while remaining 'fit to purpose' must raise quality.
Basically, if you can remove complexity without removing capability, quality increases.
Cease dependence on inspection to achieve quality. Eliminate the need for massive inspection by building quality into the product in the first place. -William E. Deming
That's not really true though, for instance. Database servers are extremely complex, and bring with them many things that we'll never have need for.
We've added massive complexity in return for ease.
This applies to almost all tools. Often tooling we use is combating the symptoms of complexity without treating the root cause, complexity itself.
Linters are great tools for enforcing a consistent style of coding, but it's very use is often a sign that the tool in question (in this case a programming language) is allowing people to use it in undesirable ways?
To be clear, I'm not arguing against linters, just pointing out that they're mitigating a problem caused by other things.
There are many ways to attempt this, but it falls mostly outside of the scope of this talk
I encourage anyone here not intimately familiar with Domain Driven Design to look into it. Notice the word complexity in the tagline of the book? Not a coincidence...
Great paper on this subject to look into it 'Out of the Tar Pit' by Ben Moseley and Peter Marks. They trace software complexity through great minds like Brooks and Dijkstra.
Often able to describe a solution in less lines of code, with less ceremony.
What about C#?
In some ways, C# is much less complex than certain languages
C# is easily less complex than two extremely common languages:
But there are still 'features' of C# that makes it less easy to quickly reason about. They add incidental complexity, let's look at some examples...
Is the following true or false?
var cust1 = new Customer(99, "J Smith");
var cust2 = new Customer(99, "J Smith");
cust1.Equals(cust2);
|
Who Knows?
What does this print?
var cust = new Customer();
Console.WriteLine(cust.Address.Country);
|
Depends if the Address property is null or not. Hopefully the constructor initialized Address and the Country property.
The point is that objects can exist in an invalid state.
What does this output?
var repo = new CustomerRepository();
var customer = repo.GetById(42);
Console.WriteLine(customer.Id);
|
Well, the value of customer could be:
Wouldn't it be nice if we didn't have to worry about null?
Will this return an int?
try {
Int32.Parse("ABCxxx");
}
catch (Exception ex) {
//exception code
}
|
No, obviously it will throw an exception.
What is an improvement? How about:
int result = 0;
bool parsed = false;
parse = Int32.TryParse("ABCxxx", out result);
|
Now my code always returns true/false (no exceptions), and I can check the bool before using the output integer.
I've made the possible cases explicit, and the code easier to understand because it isn't full of exception handling code.
Imagine if SQL didn't exist and every 'query' resulted in statements like:
foreach (Customer c in Customers)
{
decimal sum = 0.00;
foreach (Order o in Orders)
{
if (o.CustomerId == c.CustomerId)
{
sum += o.Total
}
}
}
|
Almost all operations in C# use statements. Some things like LINQ are expressions, what's the difference?
Statements usually assign their result to a variable, which can change over time.
Lets look at some C# with statements, then replace some of the statements with expressions.
int i;
int length;
var numArray = new int[] { 1, 2, 3 };
int sum;
length = numArray.Length;
for (i = 0; i < length; i++)
{
sum += numArray[i];
}
|
var numArray = new int[] { 1, 2, 3 };
int sum = 0;
foreach (var i in numArray)
{
sum += i;
}
|
var numArray = new int[] { 1, 2, 3 };
var sum = array.Sum();
|
C# encourages the use of mutability almost everywhere.
That means it's really easy to create changes, but difficult to track down the source of a change. As soon as you start contending with concurrency or parallelism, it can become a nightmare.
Wouldn't it be nice if your language pushed you down the right path from day one?
Treating functions as a value is useful.
Allows use to pass functions to other functions. Or return a function from another function.
C# actually does allow this, but it isn't very idiomatic.
Also, most libraries don't do it, so you fight against the tide.
Allows you to partially specify parameters to a function. It produces a new function with those parameters statically set.
imagine a function like the following
1:
|
let add x y = x + y |
This function is called 'add' and takes 2 parameters, x and y. It then sums them and returns the new value. We could also add this definition.
1:
|
let addFive = add 5 |
We partially filled in a call to 'add' with the first parameter set to 5.
Now we can call addFive without creating a new duplicate definition.
In C#, types are either built into the langauge as keywords, or defined as classes.
Unfortunately, they have pretty high ceremony, and combining them results in a lot more code.
Algebraic types allows one to add or multiple 'types' (not values) together to produce new types.
consider these types:
1: 2: 3: |
type EmailAddress = string type CustomerName = string type ContactInfo = EmailAddress * CustomerName |
contactInfo is the equivalent of a C# tuple that has two properties, one of type emailAddress and one of type customerName.
But we could also 'sum' types together to make types that can be either one or the other.
1: 2: 3: |
type ContactInfo = |Complete of emailAddress * customerName |Incomplete of emailAddress |
Now we have a type that could be either Complete or Incomplete, and we can make code respond accordingly.
So we have a ContactInfo type, how does using that look in practice?
Match Expression:
1: 2: 3: |
match contact with | Complete email,name -> sendEmail email name | Incomplete email -> sendEmail email "Sir or Madame" |
We tested for the type of the contact and then reacted accordingly.
An introduction to F# for Object-Oriented, enterprise developers.
Rich Hickey (creator of Clojure) conference talks
You will never read a more fun intro to a programming language.
A clojure variant of Learn You A Haskell For Great Good


Mobile Web Monitor
*nix web interface monitoring for mobile
Copyright(c) 2014 Stefano Cudini
MIT License
Tested on:
- Server: Debian Squeeze
- Client: iPhone 4s iOS 7
Source code:
Github
Screenshots
Features
- Mobile browsing
- Secure access
- Un/Ban ips address
- IP location finder
- Fail2ban logs
- Ports monitoring
- Processes monitoring
- PHP errors monitoring
- SSH users attempts cloud
- SSH recent logins
Requirements
- apache2, mod_auth_basic, mod_ssl, mod_status, mod_info
- php > 5.3
- phpmyadmin
- fail2ban
- API KEY from ipinfodb.com
Permissions
- keep writable from www-data file: ./scripts/unbanip-list.list
- keep writable from www-data dir: ./geoip/cache/
- keep writable only root files: ./scripts/*.sh
Setup
- create new file ./etc/conf.json from ./etc/conf.default.json
- create apache ssl virtual host using ./etc/apache.conf
- copy ./etc/crond.conf in /etc/cron.d/mwm
- browser https://adminsite.com/admin.php


Check your inbox for the link to your download, "5 Tips on Pricing as a Freelancer" in a few minutes.
But first, press play!
Help a girl out!


MacDevMike's Blog
- Tech Blog Feb 4, 2015
- Cultural Blog Feb 5, 2015
- Tech Blog Feb 15, 2015
- Tech Blog Feb 21, 2015
- Cultural Blog Feb 21, 2015
- Cultural Blog Feb 27, 2015
- Technical Blog Mar 1, 2015
- Cultural Blog Mar 8, 2015
- Technical Blog Mar 8, 2015
- Cultural Blog Mar 15, 2015
- Technical Blog Mar 15, 2015
- Cultural Blog Apr 8, 2015


{% extends "extends/base.html" %} {% block title %} {{ post.title }} {% endblock %} {% block header %}{% endblock %} {% block content %} {% include "includes/user_card.html" with paginator=post_count users=post.author %} {% include "includes/single_post_card.html" %} {% include "includes/comments.html" with items=comments %} {% endblock %}


Winning the tournament, however, is a different story.
When the MAC released its preseason coaches’ poll on Nov. 3, 2021, the Bobcats were picked to finish second in the regular season and didn’t receive a single vote to win the MAC Tournament.
There is good cause to believe, however, that Ohio will break from those expectations and repeat its tournament run from last year. If the Bobcats pull it off, they will have won consecutive MAC titles for the first time in program history and be guaranteed their 15th all-time appearance in the NCAA Tournament.
The Bobcats have a championship-caliber lineup. The three-man arsenal of Mark Sears, Ben Vander Plas and Jason Carter provide the backbone on offense, while fellow starters Miles Brown and Ben Roderick can pack a punch once in a blue moon. Not to mention a bench crammed with competent role players and a lack of severe injuries that have kept the lineup intact.
As the season winds down, Ohio is tied for first place with Toledo and has just three games left until it packs its bags for Cleveland. While its spot in the tournament is finalized, its seeding is not. If Ohio drops its final three games, it could shoot all the way down to the No. 4 seed.
Is that likely? No, but it is possible.
Regardless if it ends the regular season in first or fourth place, the chances of advancing to the MAC Tournament semifinals at minimum skew in Ohio’s favor. It has a perfect record against the teams fighting over the final three spots in the bracket. It also defeated current No. 5 seed Akron in early January.
But no matter the seeding, Ohio will hit a bump sooner or later. It has before. Both Toledo and Kent State knocked Ohio on its face during the regular season. How well that translates to success in the tournament is anyone’s guess.
The Rockets have a history of disappointment. They haven’t won the MAC title since 1980, and three regular season championships since then don’t substitute for a lack of titles.
Still, there’s no time like the present. Toledo coach Tod Kowalczyk routinely produces first-rate teams that tyrannize conference opponents. This year is no exception. Toledo’s starting rotation is one of the most balanced in the MAC, even after star guard Marreon Jackson transferred to Arizona State following last season.
Toledo is the team to beat in the MAC, and Ohio failed twice in the regular season. Unless the tournament curse haunts Toledo for another year, Ohio might be stumped a third time if the two teams clash in Cleveland.
The other hurdle standing between Ohio and a MAC title is Kent State. The two programs split their regular season series, but it wasn’t pretty for Ohio. A slim win followed by a blowout loss doesn’t lend well to its postseason hopes.
Kent State last won a MAC title in 2017. However, they haven’t made it further than the semifinals since then. Ohio sent them packing after the quarterfinals in 2021.
Therein lies Ohio’s hope.
The Bobcats were the first team to secure a spot in the MAC Tournament — and for good reason. They’ve proven time and time again why they belong in the postseason.
Will they shatter preseason notions of how far their success can carry them?
For good or bad, yes. And Ohio won’t know for certain until tournament time approaches.


--- title: 'Array Languages: R vs APL' author: Jonathan Carroll date: '2023-07-07' slug: array-languages-r-vs-apl categories: - rstats - APL tags: - rstats - APL type: '' subtitle: '' image: '' editor_options: chunk_output_type: console ---
I’ve been learning at least one new programming language a month through Exercism which has been really fun and interesting. I frequently say that “every language you learn teaches you something about all the others you know” and with nearly a dozen under my belt so far I’m starting to worry about the combinatorics of that statement.
APL isn’t on the list of languages but I’ve seen it in codegolf solutions often enough that it seemed worth a look.
I’ve been learning at least one new programming language a month through Exercism which has been really fun and interesting. I frequently say that “every language you learn teaches you something about all the others you know” and with nearly a dozen under my belt so far I’m starting to worry about the combinatorics of that statement.
APL isn’t on the list of languages but I’ve seen it in codegolf solutions often enough that it seemed worth a look.
Now, when I say “learning” I mean “good enough to do 5 toy exercises” which is what you need to do to in order to earn the badge for that month in the “#12in23 challenge” (gamification FTW). That’s often sufficient for me to get a taste for the language and see if it’s something I’d like to dive deeper into.
It means I’ve been watching a lot of “<language> beginner tutorial” videos recently, which may have been what prompted YouTube to suggest to me a video from code_report; I think this one comparing a leetcode solution to the problem
find the GCD (greatest common divisor) of the smallest and largest numbers in an array
written in 16 (sixteen!!!) languages. Some of those I know a little or a moderate amount about, but one stood out. The APL solution comprises 5 glyphs (symbols) representing operations
⌈/∨⌊/
I’ve seen APL solutions pop up in codegolf and they’ve just looked like madness,
which is probably fair. The linked video prompted me to look into some of their
other videos and they do a great job explaining the glyphs in APL and how they
compare to other languages. It turns out this madness is not nearly as hard to
read as it looks. The above glyphs represent “maximum” (⌈), “reduce” (/), “GCD”
(∨), and “minimum” (⌊) and those all correspond well to the problem statement.
The function itself is
“point-free” whereby the
argument(s) aren’t specified at all; like saying mean
rather than mean(x)
.
For the truly adventurous: ‘The Hideous Beauty of Point-Free Programming; An
exercise in combinators using
Haskell’
I ended up diving deeper and deeper, and it all started to make more and more sense.
In a recent stream, ThePrimeagen responded to the comment about some language that “<x> is more readable” with “readability is just familiarity” and that stuck with me - I’m not entirely sure I 100% agree with it because I can find several ways to write some code that someone familiar with that language will either find easy or hard to read, despite familiarity. I think {dplyr} in R does a fantastic job of abstracting operations with verbs and making data pipelines easy to comprehend, certainly much more than the base-equivalent code.
So, would APL be “readable” if I was more familiar with it? Let’s find out!
There aren’t that many glyphs in APL - there are far more unique functions in most big libraries from any mainstream language. Looking at the top of the ‘ride’ editor for Dyalog APL there are 80 glyphs. To make a slightly unfair example, there are a lot of exported functions (288 of them) in {dplyr}…
packageVersion("dplyr")
## [1] '1.0.10'
ns <- sort(getNamespaceExports("dplyr"))
head(ns, 20)
## [1] ".data" "%>%" "across" "add_count" "add_count_"
## [6] "add_row" "add_rownames" "add_tally" "add_tally_" "all_equal"
## [11] "all_of" "all_vars" "anti_join" "any_of" "any_vars"
## [16] "arrange" "arrange_" "arrange_all" "arrange_at" "arrange_if"
tail(ns, 20)
## [1] "tbl_vars" "tibble" "top_frac"
## [4] "top_n" "transmute" "transmute_"
## [7] "transmute_all" "transmute_at" "transmute_if"
## [10] "tribble" "type_sum" "ungroup"
## [13] "union" "union_all" "validate_grouped_df"
## [16] "validate_rowwise_df" "vars" "with_groups"
## [19] "with_order" "wrap_dbplyr_obj"
Taking the functions listed as S3method
or export
in the
NAMESPACE
file is 470+. Sure, these aren’t all user-facing, but still. Lots.
So, 80 isn’t a “huge” number, if that’s the entire language.
I watched some more videos about what the glyphs mean and how they work. I started to become slightly familiar with what they mean. Learning is done with the hands, not the eyes, though - as this (not new) blog post goes into great detail on, so I felt that I needed to actually write something. I installed Dyalog APL and the ride editor (given that it uses glyphs, a non-standard editor seems to make sense; I’ve otherwise been completing the Exercism solutions in emacs). I also found tryapl.org as an online editor.
The first step was to just follow along what I’d seen in the videos. I had most recently watched this one that does include a comparison to R (and Julia) so I tried to recreate what I’d seen built up. I was shocked that I actually could!
From reshaping into a matrix, to building up the sequence, to inserting the combinator - it all came together easily enough.
On “combinators” - if you aren’t familiar with Lambda Calculus and have a spare hour, this is a wonderful talk explaining the basics and demonstrating them using JavaScript.
More videos, more learning. I found this one which is another leetcode problem which was roughly
find the maximum value of the sum of rows of a matrix
That sounded like something R would easily handle, but this particular
video didn’t feature R. It did feature C++, the solution for which
requires two for
loops and looked (to me) horrific - I’m used to just
passing a matrix to an R function and not having to worry about loops.
I’ve had many discussions on this topic because for whatever reason, for
loops have a particular reputation in R despite them not (necessarily) being
any worse than any other solution. The short response is that if you’re using one
when you could be using vectorisation, you’re probably stating your problem poorly
and can do better (in terms of readability, performance, or both). This video
covers the points really nicely.
Jenny Bryan made the point that
Of course someone has to write loops… It doesn’t have to be you
alluding to the fact that vectorisation (either with the *apply
family or purrr
)
still has a C loop buried within (I covered some of this myself in another post).
Miles McBain makes a point of never using them (directly).
Okay, so, returning to the leetcode problem. The APL solution in the video is
reshaping (⍴
) a vector to a matrix then reducing (/
) addition (+
) across rows (last-axis; c.f. first axis would be +⌿
) and reducing (/
) that with maximum (⌈
)
making the entire solution
x ← 3 3⍴1 2 3 5 5 5 3 1 4
⌈/+/x
15
which is an elegant, compact solution. APL agrees to ignore the [1]
at the
start of R’s default output if R agrees to ignore the odd indenting of APL commands.
As a sidenote: I love that I finally get to use the OG assignment arrow ←
that inspired the usage in R (as <-
). This isn’t some ligature font, it’s the
actual arrow glyph with Unicode code point U+2190. The APL keyboard has this on
a key and that was common around the time that it made it into R (or S).
The video explains that this solution is
particularly nice because it’s explicit that two “reduce” operations
are occurring. The +
operator in APL can be either unary (takes 1 argument) or
binary (takes 2 arguments) but it can’t loop over an entire vector. To achieve that,
it’s combined with /
which performs “reduce”, essentially applying +
across
the input.
It’s a fairly straightforward answer with R, too:
a <- matrix(c(1, 2, 3,
5, 5, 5,
3, 1, 4),
3, 3, byrow = TRUE)
a
## [,1] [,2] [,3]
## [1,] 1 2 3
## [2,] 5 5 5
## [3,] 3 1 4
max(rowSums(a))
## [1] 15
and done. Nice. No for
loops. Or are there? Of course there are, somewhere, but
can we write this “like” the APL solution and be more explicit with the “reduce”
steps over binary operators? R has a Reduce()
function for exactly this case.
A simplified rowSums()
function could just be applying the sum
operation to
the rows of the matrix
s <- function(x) apply(x, 1, sum)
but sum(x)
is itself vectorised - it’s an application of the binary +
operation
across a vector, so really we could have
s <- function(x) apply(x, 1, \(y) Reduce(`+`, y))
s(a)
## [1] 6 15 8
This isn’t so bad compared to APL which “naturally” performs the reduction
over that dimension. Compare (⍝
signifies a comment):
x
1 2 3
5 5 5
3 1 4
⍝ "rowSums"
+/x
6 15 8
⍝ "colSums"
+⌿x
9 8 12
There’s nothing here that says x
needs to have more than 1 dimension, though -
it’s the same operator(s) on a vector, just that they do the same thing
+/(1 2 3)
6
+⌿(1 2 3)
6
max
is also vectorised, so a simple, ostensibly binary version of that could be
m <- function(x, y) ifelse(x > y, x, y)
m(1, 2)
## [1] 2
m(4, 2)
## [1] 4
Together, an R solution using these could be
Reduce(m, s(a))
## [1] 15
which, if we shortened Reduce
to a single character
R <- Reduce
would be
R(m, s(a))
## [1] 15
That’s not a lot more characters than APL. I’ve abstracted at least one of the functions, though - APL uses the operators directly, in which case we’d have
maxWealth <- \(x) R(m, apply(x, 1, \(y) R(`+`, y)))
maxWealth(a)
## [1] 15
That’s only using Reduce
, binary +
, a simplified max
(which we could
imagine was a built-in we could shorten to m
), and the apply
over rows.
Comparing these directly (with some artistic license):
m R + R
⌈ / + /
The point of this whole exercise wasn’t to rebuild the APL solution in R - it was to think more deeply about what abstractions R offers and how they compare to a language that uses (only) the atomic constructs directly.
I love that in R I can pass either individual values or a vector to sum
and it “just deals with it”
sum(4, 5, 6) # sum some "scalars"
## [1] 15
vals <- c(4, 5, 6)
sum(vals) # sum a vector
## [1] 15
This ability to hide/abstract the looping over dimensions and to work directly with
objects with more than one dimension is what qualifies R as an “array language”.
This is also (mimicking, perhaps) “rank polymorphism” which APL does have. Julia
gets around this with “broadcasting”. But, at least in R, this hides/abstracts some of what is happening, and sometimes/often, that’s a for
loop.
Does every programmer need to know the gory details? Absolutely not. Might it be useful for gaining a better understanding of the language and how to work with it? I really think it is. It’s why I’m digging further and further into functional programming in general.
I do believe that the APL solution is more explicit in what it’s doing; that it doesn’t hide (much, if any) of the implementation details. I’m comfortable with the abstractions in R and will continue to write R for this reason, but if I had a need to do some array math in any other language, I now feel like APL really does have a lot to offer.
Bonus Round
I was thinking about the leetcode problem and thought that a slightly more complex version would be to return “which row has the maximum?” rather than the maximum itself.
In R, there is another useful function to achieve this
which.max(rowSums(a))
## [1] 2
so, have I learned enough APL to do this myself?
There’s a “Grade Down” operator (⍒
) which seems equivalent to R’s
order(decreasing = TRUE)
and a “First” operator (⊃
) like head(n = 1)
so a solution seems to be to get the indices of the sorted (decreasing)
elements then take the first one
⊃⍒+/x
2
Apparently an alternative would be to find the (first) element of the input (⍵
) that
matches the maximum which would be
{⍵⍳⌈/⍵}(+/x)
2
which, at least to me, isn’t as elegant.
Lastly, Kieran Healy relayed to me a small algorithm for finding ‘primes smaller than some number’ in APL which cleaned up as
((⊢~∘.×⍨)1↓⍳)(50)
2 3 5 7 11 13 17 19 23 29 31 37 41 43 47
This makes use of some combinators (e.g. the C-combinator ⍨
- possibly the
coolest glyph in the entire system),
but roughly involves filtering values not (~
)
members (∈
) of values produced by the outer (º
) product (.
) using
multiplication (×
) (i.e. numbers that can be made by multiplying other
numbers) from the sequence (⍳
) from 2 to some value (dropping (↓
) 1;
3↓⍳8 == 4:8
). With the small amount I’ve learned - mostly from watching
someone else use the language - I was able to decipher at least what the
operators were in all of that, even if I probably couldn’t come up with the
solution myself.
I’m happy to call that “readable”.
I looked around for code to generate the primes below some number in R. I couldn’t (easily) find one that worked without an explicit loop. I found a version in {sfsmisc} which compacts to
primes. <- function(n) {
## By Bill Venables <= 2001
x <- 1:n
x[1] <- 0
p <- 1
while((p <- p + 1) <= floor(sqrt(n)))
if(x[p] != 0)
x[seq(p^2, n, p)] <- 0
x[x > 0]
}
primes.(50)
## [1] 2 3 5 7 11 13 17 19 23 29 31 37 41 43 47
Taking inspiration from the APL solution, though - what if we just generate all
products from the set of numbers 2:n
and exclude those as “not prime” from all
the numbers up to n
?
primes <- function(n) {
s <- 2:n
setdiff(s, c(outer(s, s, `*`)))
}
primes(50)
## [1] 2 3 5 7 11 13 17 19 23 29 31 37 41 43 47
That… works! It’s slower and uses more memory, for sure, but that wasn’t our criteria, and isn’t relevant for a once-off evaluation. Even better - I can “read” exactly what it’s doing.
I’ve learned a lot and I’ll continue to learn more about APL because I really do think that understanding how these operators come together to build a function will be enlightening in terms of a functional approach.
I still haven’t made it to trying out BQN (almost constructed by incrementing
each letter of APL, IBM -> HAL
style, but perhaps officially
“Big Questions Notation”, and sometimes
pronounced “bacon”) but it sounds like it has some newer improvements over APL
and will be worth a try.
As always, comments and discussions are welcome here or on Mastodon.
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A dedicated third year student pursuing a double major in computer science and Russian at Portland State University looking for industry experience in software engineering.
Study abroad in Korea and Kazakhstan adapt me to excel in foreign situations and cooperate with diverse backgrounds.
I am detail oriented, self-motivated, and an empathetic leader with strong soft skills and a passion for being an active member in my community.


---
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permalink: /resources/communities/religious/
layout: single
---
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Torrent
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DoubleLessTest.testComparableLessFailMessage: Double 'valueA'(0.123) is less than Double 'valueB'(0.124). Extra info goes here. DoubleLessTest.testComparableLessFailNoMessage: Double 'valueA'(0.123) is less than Double 'valueB'(0.124).


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Toronto police unable to locate man seen swinging axe, yelling at people downtown
by The Canadian Press, StaffToronto police say they weren't able to find a man who had reportedly been walking around the downtown area and swinging an axe.
They say the man was yelling at people on Saturday evening and striking garages with the large axe.
They say he then started swinging it at transit poles.
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