AMED_AARCH32_ENCODING_VUZP_VTRN_A1_D, //!< 64-bit SIMD vector
AMED_AARCH32_ENCODING_VUZP_VTRN_T1_D, //!< 64-bit SIMD vector
AMED_AARCH32_ENCODING_VZIP_VTRN_A1_D, //!< 64-bit SIMD vector
AMED_AARCH32_ENCODING_VZIP_VTRN_T1_D, //!< 64-bit SIMD vector
} amed_aarch32_encoding;
#define AMED_AARCH32_SYNC_OP_MAX_TEXT_LENGTH (5 + 1)
typedef enum _amed_aarch32_sync_op
{
AMED_AARCH32_SYNC_OP_NONE,
AMED_AARCH32_SYNC_OP_CSYNC,
} amed_aarch32_sync_op;
#define AMED_AARCH32_CCLASS_MAX_TEXT_LENGTH (18 + 1)
typedef enum _amed_aarch32_cclass
{
AMED_AARCH32_CCLASS_NONE,
AMED_AARCH32_CCLASS_invalid, //!< INVALID
AMED_AARCH32_CCLASS_ADC_i_a1, //!< A1
AMED_AARCH32_CCLASS_ADC_i_t1, //!< T1
AMED_AARCH32_CCLASS_ADC_r_a1, //!< A1
AMED_AARCH32_CCLASS_ADC_r_t1, //!< T1
AMED_AARCH32_CCLASS_ADC_r_t2, //!< T2
AMED_AARCH32_CCLASS_ADC_rr_a1, //!< A1
AMED_AARCH32_CCLASS_ADD_i_a1, //!< A1
AMED_AARCH32_CCLASS_ADD_i_t1, //!< T1
AMED_AARCH32_CCLASS_ADD_i_t2, //!< T2
AMED_AARCH32_CCLASS_ADD_i_t3, //!< T3
AMED_AARCH32_CCLASS_ADD_i_t4, //!< T4
AMED_AARCH32_CCLASS_ADD_r_a1, //!< A1
AMED_AARCH32_CCLASS_ADD_r_t1, //!< T1
AMED_AARCH32_CCLASS_ADD_r_t2, //!< T2
AMED_AARCH32_CCLASS_ADD_r_t3, //!< T3
AMED_AARCH32_CCLASS_ADD_rr_a1, //!< A1
AMED_AARCH32_CCLASS_ADD_SP_i_a1, //!< A1
AMED_AARCH32_CCLASS_ADD_SP_i_t1, //!< T1
AMED_AARCH32_CCLASS_ADD_SP_i_t2, //!< T2
AMED_AARCH32_CCLASS_ADD_SP_i_t3, //!< T3
AMED_AARCH32_CCLASS_ADD_SP_i_t4, //!< T4
AMED_AARCH32_CCLASS_ADD_SP_r_a1, //!< A1
AMED_AARCH32_CCLASS_ADD_SP_r_t1, //!< T1
AMED_AARCH32_CCLASS_ADD_SP_r_t2, //!< T2
AMED_AARCH32_CCLASS_ADD_SP_r_t3, //!< T3
AMED_AARCH32_CCLASS_ADR_a1, //!< A1
AMED_AARCH32_CCLASS_ADR_a2, //!< A2
AMED_AARCH32_CCLASS_ADR_t1, //!< T1
AMED_AARCH32_CCLASS_ADR_t2, //!< T2
AMED_AARCH32_CCLASS_ADR_t3, //!< T3
AMED_AARCH32_CCLASS_AND_i_a1, //!< A1
AMED_AARCH32_CCLASS_AND_i_t1, //!< T1
AMED_AARCH32_CCLASS_AND_r_a1, //!< A1
AMED_AARCH32_CCLASS_AND_r_t1, //!< T1
AMED_AARCH32_CCLASS_AND_r_t2, //!< T2
AMED_AARCH32_CCLASS_AND_rr_a1, //!< A1
AMED_AARCH32_CCLASS_B_a1, //!< A1
AMED_AARCH32_CCLASS_B_t1, //!< T1
AMED_AARCH32_CCLASS_B_t2, //!< T2
AMED_AARCH32_CCLASS_B_t3, //!< T3
AMED_AARCH32_CCLASS_B_t4, //!< T4
AMED_AARCH32_CCLASS_BFC_a1, //!< A1
AMED_AARCH32_CCLASS_BFC_t1, //!< T1
AMED_AARCH32_CCLASS_BFI_a1, //!< A1
AMED_AARCH32_CCLASS_BFI_t1, //!< T1
AMED_AARCH32_CCLASS_BIC_i_a1, //!< A1
AMED_AARCH32_CCLASS_BIC_i_t1, //!< T1
AMED_AARCH32_CCLASS_BIC_r_a1, //!< A1
AMED_AARCH32_CCLASS_BIC_r_t1, //!< T1
AMED_AARCH32_CCLASS_BIC_r_t2, //!< T2
AMED_AARCH32_CCLASS_BIC_rr_a1, //!< A1
AMED_AARCH32_CCLASS_BKPT_a1, //!< A1
AMED_AARCH32_CCLASS_BKPT_t1, //!< T1
AMED_AARCH32_CCLASS_BL_i_a1, //!< A1
AMED_AARCH32_CCLASS_BL_i_a2, //!< A2
AMED_AARCH32_CCLASS_BL_i_t1, //!< T1
AMED_AARCH32_CCLASS_BL_i_t2, //!< T2
AMED_AARCH32_CCLASS_BLX_r_a1, //!< A1
AMED_AARCH32_CCLASS_BLX_r_t1, //!< T1
AMED_AARCH32_CCLASS_BX_a1, //!< A1
AMED_AARCH32_CCLASS_BX_t1, //!< T1
AMED_AARCH32_CCLASS_BXJ_a1, //!< A1
AMED_AARCH32_CCLASS_BXJ_t1, //!< T1
AMED_AARCH32_CCLASS_CBNZ_t1, //!< T1
AMED_AARCH32_CCLASS_CLREX_a1, //!< A1
AMED_AARCH32_CCLASS_CLREX_t1, //!< T1
AMED_AARCH32_CCLASS_CLZ_a1, //!< A1
AMED_AARCH32_CCLASS_CLZ_t1, //!< T1
AMED_AARCH32_CCLASS_CMN_i_a1, //!< A1
AMED_AARCH32_CCLASS_CMN_i_t1, //!< T1
AMED_AARCH32_CCLASS_CMN_r_a1, //!< A1
AMED_AARCH32_CCLASS_CMN_r_t1, //!< T1
AMED_AARCH32_CCLASS_CMN_r_t2, //!< T2
AMED_AARCH32_CCLASS_CMN_rr_a1, //!< A1
AMED_AARCH32_CCLASS_CMP_i_a1, //!< A1
AMED_AARCH32_CCLASS_CMP_i_t1, //!< T1
AMED_AARCH32_CCLASS_CMP_i_t2, //!< T2
AMED_AARCH32_CCLASS_CMP_r_a1, //!< A1
AMED_AARCH32_CCLASS_CMP_r_t1, //!< T1
AMED_AARCH32_CCLASS_CMP_r_t2, //!< T2
AMED_AARCH32_CCLASS_CMP_r_t3, //!< T3
AMED_AARCH32_CCLASS_CMP_rr_a1, //!< A1
AMED_AARCH32_CCLASS_CPS_a1, //!< A1
AMED_AARCH32_CCLASS_CPS_t1, //!< T1
AMED_AARCH32_CCLASS_CPS_t2, //!< T2
AMED_AARCH32_CCLASS_CRC32_a1, //!< A1
AMED_AARCH32_CCLASS_CRC32_t1, //!< T1
AMED_AARCH32_CCLASS_CRC32C_a1, //!< A1
AMED_AARCH32_CCLASS_CRC32C_t1, //!< T1
AMED_AARCH32_CCLASS_CSDB_a1, //!< A1
AMED_AARCH32_CCLASS_CSDB_t1, //!< T1
AMED_AARCH32_CCLASS_DBG_a1, //!< A1
AMED_AARCH32_CCLASS_DBG_t1, //!< T1
AMED_AARCH32_CCLASS_DCPS1_t1, //!< T1
AMED_AARCH32_CCLASS_DCPS2_t1, //!< T1
AMED_AARCH32_CCLASS_DCPS3_t1, //!< T1
AMED_AARCH32_CCLASS_DMB_a1, //!< A1
AMED_AARCH32_CCLASS_DMB_t1, //!< T1
AMED_AARCH32_CCLASS_DSB_a1, //!< A1
AMED_AARCH32_CCLASS_DSB_t1, //!< T1
AMED_AARCH32_CCLASS_EOR_i_a1, //!< A1
AMED_AARCH32_CCLASS_EOR_i_t1, //!< T1
AMED_AARCH32_CCLASS_EOR_r_a1, //!< A1
AMED_AARCH32_CCLASS_EOR_r_t1, //!< T1
AMED_AARCH32_CCLASS_EOR_r_t2, //!< T2
AMED_AARCH32_CCLASS_EOR_rr_a1, //!< A1
AMED_AARCH32_CCLASS_ERET_a1, //!< A1
AMED_AARCH32_CCLASS_ERET_t1, //!< T1
AMED_AARCH32_CCLASS_ESB_a1, //!< A1
AMED_AARCH32_CCLASS_ESB_t1, //!< T1
AMED_AARCH32_CCLASS_HLT_a1, //!< A1
AMED_AARCH32_CCLASS_HLT_t1, //!< T1
AMED_AARCH32_CCLASS_HVC_a1, //!< A1
AMED_AARCH32_CCLASS_HVC_t1, //!< T1
AMED_AARCH32_CCLASS_ISB_a1, //!< A1
AMED_AARCH32_CCLASS_ISB_t1, //!< T1
AMED_AARCH32_CCLASS_IT_t1, //!< T1
AMED_AARCH32_CCLASS_LDA_a1, //!< A1
AMED_AARCH32_CCLASS_LDA_t1, //!< T1
AMED_AARCH32_CCLASS_LDAB_a1, //!< A1
AMED_AARCH32_CCLASS_LDAB_t1, //!< T1
AMED_AARCH32_CCLASS_LDAEX_a1, //!< A1
AMED_AARCH32_CCLASS_LDAEX_t1, //!< T1
AMED_AARCH32_CCLASS_LDAEXB_a1, //!< A1
AMED_AARCH32_CCLASS_LDAEXB_t1, //!< T1
AMED_AARCH32_CCLASS_LDAEXD_a1, //!< A1
AMED_AARCH32_CCLASS_LDAEXD_t1, //!< T1
AMED_AARCH32_CCLASS_LDAEXH_a1, //!< A1
AMED_AARCH32_CCLASS_LDAEXH_t1, //!< T1
AMED_AARCH32_CCLASS_LDAH_a1, //!< A1
AMED_AARCH32_CCLASS_LDAH_t1, //!< T1
AMED_AARCH32_CCLASS_LDC_i_a1, //!< A1
AMED_AARCH32_CCLASS_LDC_i_t1, //!< T1
AMED_AARCH32_CCLASS_LDC_l_a1, //!< A1
AMED_AARCH32_CCLASS_LDC_l_t1, //!< T1
AMED_AARCH32_CCLASS_LDM_a1, //!< A1
AMED_AARCH32_CCLASS_LDM_t1, //!< T1
AMED_AARCH32_CCLASS_LDM_t2, //!< T2
AMED_AARCH32_CCLASS_LDM_e_a1, //!< A1
AMED_AARCH32_CCLASS_LDM_u_a1, //!< A1
AMED_AARCH32_CCLASS_LDMDA_a1, //!< A1
AMED_AARCH32_CCLASS_LDMDB_a1, //!< A1
AMED_AARCH32_CCLASS_LDMDB_t1, //!< T1
AMED_AARCH32_CCLASS_LDMIB_a1, //!< A1
AMED_AARCH32_CCLASS_LDR_i_a1, //!< A1
AMED_AARCH32_CCLASS_LDR_i_t1, //!< T1
AMED_AARCH32_CCLASS_LDR_i_t2, //!< T2
AMED_AARCH32_CCLASS_LDR_i_t3, //!< T3
AMED_AARCH32_CCLASS_LDR_i_t4, //!< T4
AMED_AARCH32_CCLASS_LDR_l_a1, //!< A1
AMED_AARCH32_CCLASS_LDR_l_t1, //!< T1
AMED_AARCH32_CCLASS_LDR_l_t2, //!< T2
AMED_AARCH32_CCLASS_LDR_r_a1, //!< A1
AMED_AARCH32_CCLASS_LDR_r_t1, //!< T1
AMED_AARCH32_CCLASS_LDR_r_t2, //!< T2
AMED_AARCH32_CCLASS_LDRB_i_a1, //!< A1
AMED_AARCH32_CCLASS_LDRB_i_t1, //!< T1
AMED_AARCH32_CCLASS_LDRB_i_t2, //!< T2
AMED_AARCH32_CCLASS_LDRB_i_t3, //!< T3
AMED_AARCH32_CCLASS_LDRB_l_a1, //!< A1
AMED_AARCH32_CCLASS_LDRB_l_t1, //!< T1
AMED_AARCH32_CCLASS_LDRB_r_a1, //!< A1
AMED_AARCH32_CCLASS_LDRB_r_t1, //!< T1
AMED_AARCH32_CCLASS_LDRB_r_t2, //!< T2
AMED_AARCH32_CCLASS_LDRBT_a1, //!< A1
AMED_AARCH32_CCLASS_LDRBT_a2, //!< A2
AMED_AARCH32_CCLASS_LDRBT_t1, //!< T1
AMED_AARCH32_CCLASS_LDRD_i_a1, //!< A1
AMED_AARCH32_CCLASS_LDRD_i_t1, //!< T1
AMED_AARCH32_CCLASS_LDRD_l_a1, //!< A1
AMED_AARCH32_CCLASS_LDRD_l_t1, //!< T1
AMED_AARCH32_CCLASS_LDRD_r_a1, //!< A1
AMED_AARCH32_CCLASS_LDREX_a1, //!< A1
AMED_AARCH32_CCLASS_LDREX_t1, //!< T1
AMED_AARCH32_CCLASS_LDREXB_a1, //!< A1
AMED_AARCH32_CCLASS_LDREXB_t1, //!< T1
AMED_AARCH32_CCLASS_LDREXD_a1, //!< A1
AMED_AARCH32_CCLASS_LDREXD_t1, //!< T1
AMED_AARCH32_CCLASS_LDREXH_a1, //!< A1
AMED_AARCH32_CCLASS_LDREXH_t1, //!< T1
AMED_AARCH32_CCLASS_LDRH_i_a1, //!< A1
AMED_AARCH32_CCLASS_LDRH_i_t1, //!< T1
AMED_AARCH32_CCLASS_LDRH_i_t2, //!< T2
AMED_AARCH32_CCLASS_LDRH_i_t3, //!< T3
AMED_AARCH32_CCLASS_LDRH_l_a1, //!< A1
AMED_AARCH32_CCLASS_LDRH_l_t1, //!< T1
AMED_AARCH32_CCLASS_LDRH_r_a1, //!< A1
AMED_AARCH32_CCLASS_LDRH_r_t1, //!< T1
AMED_AARCH32_CCLASS_LDRH_r_t2, //!< T2
AMED_AARCH32_CCLASS_LDRHT_a1, //!< A1
AMED_AARCH32_CCLASS_LDRHT_a2, //!< A2
AMED_AARCH32_CCLASS_LDRHT_t1, //!< T1
AMED_AARCH32_CCLASS_LDRSB_i_a1, //!< A1
AMED_AARCH32_CCLASS_LDRSB_i_t1, //!< T1
AMED_AARCH32_CCLASS_LDRSB_i_t2, //!< T2
AMED_AARCH32_CCLASS_LDRSB_l_a1, //!< A1
AMED_AARCH32_CCLASS_LDRSB_l_t1, //!< T1
AMED_AARCH32_CCLASS_LDRSB_r_a1, //!< A1
AMED_AARCH32_CCLASS_LDRSB_r_t1, //!< T1
AMED_AARCH32_CCLASS_LDRSB_r_t2, //!< T2
AMED_AARCH32_CCLASS_LDRSBT_a1, //!< A1
AMED_AARCH32_CCLASS_LDRSBT_a2, //!< A2
AMED_AARCH32_CCLASS_LDRSBT_t1, //!< T1
AMED_AARCH32_CCLASS_LDRSH_i_a1, //!< A1
AMED_AARCH32_CCLASS_LDRSH_i_t1, //!< T1
AMED_AARCH32_CCLASS_LDRSH_i_t2, //!< T2
AMED_AARCH32_CCLASS_LDRSH_l_a1, //!< A1
AMED_AARCH32_CCLASS_LDRSH_l_t1, //!< T1
AMED_AARCH32_CCLASS_LDRSH_r_a1, //!< A1
AMED_AARCH32_CCLASS_LDRSH_r_t1, //!< T1
AMED_AARCH32_CCLASS_LDRSH_r_t2, //!< T2
AMED_AARCH32_CCLASS_LDRSHT_a1, //!< A1
AMED_AARCH32_CCLASS_LDRSHT_a2, //!< A2
AMED_AARCH32_CCLASS_LDRSHT_t1, //!< T1
AMED_AARCH32_CCLASS_LDRT_a1, //!< A1
AMED_AARCH32_CCLASS_LDRT_a2, //!< A2
AMED_AARCH32_CCLASS_LDRT_t1, //!< T1
AMED_AARCH32_CCLASS_MCR_a1, //!< A1
AMED_AARCH32_CCLASS_MCR_t1, //!< T1
AMED_AARCH32_CCLASS_MCRR_a1, //!< A1
AMED_AARCH32_CCLASS_MCRR_t1, //!< T1
AMED_AARCH32_CCLASS_MLA_a1, //!< A1
AMED_AARCH32_CCLASS_MLA_t1, //!< T1
AMED_AARCH32_CCLASS_MLS_a1, //!< A1
AMED_AARCH32_CCLASS_MLS_t1, //!< T1
AMED_AARCH32_CCLASS_MOV_i_a1, //!< A1
AMED_AARCH32_CCLASS_MOV_i_a2, //!< A2
AMED_AARCH32_CCLASS_MOV_i_t1, //!< T1
AMED_AARCH32_CCLASS_MOV_i_t2, //!< T2
AMED_AARCH32_CCLASS_MOV_i_t3, //!< T3
AMED_AARCH32_CCLASS_MOV_r_a1, //!< A1
AMED_AARCH32_CCLASS_MOV_r_t1, //!< T1
AMED_AARCH32_CCLASS_MOV_r_t2, //!< T2
AMED_AARCH32_CCLASS_MOV_r_t3, //!< T3
AMED_AARCH32_CCLASS_MOV_rr_a1, //!< A1
AMED_AARCH32_CCLASS_MOV_rr_t1, //!< T1
AMED_AARCH32_CCLASS_MOV_rr_t2, //!< T2
AMED_AARCH32_CCLASS_MOVT_a1, //!< A1
AMED_AARCH32_CCLASS_MOVT_t1, //!< T1
AMED_AARCH32_CCLASS_MRC_a1, //!< A1
AMED_AARCH32_CCLASS_MRC_t1, //!< T1
AMED_AARCH32_CCLASS_MRRC_a1, //!< A1
AMED_AARCH32_CCLASS_MRRC_t1, //!< T1
AMED_AARCH32_CCLASS_MRS_a1, //!< A1
AMED_AARCH32_CCLASS_MRS_t1, //!< T1
AMED_AARCH32_CCLASS_MRS_br_a1, //!< A1
AMED_AARCH32_CCLASS_MRS_br_t1, //!< T1
AMED_AARCH32_CCLASS_MSR_br_a1, //!< A1
AMED_AARCH32_CCLASS_MSR_br_t1, //!< T1
AMED_AARCH32_CCLASS_MSR_i_a1, //!< A1
AMED_AARCH32_CCLASS_MSR_r_a1, //!< A1
AMED_AARCH32_CCLASS_MSR_r_t1, //!< T1
AMED_AARCH32_CCLASS_MUL_a1, //!< A1
AMED_AARCH32_CCLASS_MUL_t1, //!< T1
AMED_AARCH32_CCLASS_MUL_t2, //!< T2
AMED_AARCH32_CCLASS_MVN_i_a1, //!< A1
AMED_AARCH32_CCLASS_MVN_i_t1, //!< T1
AMED_AARCH32_CCLASS_MVN_r_a1, //!< A1
AMED_AARCH32_CCLASS_MVN_r_t1, //!< T1
AMED_AARCH32_CCLASS_MVN_r_t2, //!< T2
AMED_AARCH32_CCLASS_MVN_rr_a1, //!< A1
AMED_AARCH32_CCLASS_NOP_a1, //!< A1
AMED_AARCH32_CCLASS_NOP_t1, //!< T1
AMED_AARCH32_CCLASS_NOP_t2, //!< T2
AMED_AARCH32_CCLASS_ORN_i_t1, //!< T1
AMED_AARCH32_CCLASS_ORN_r_t1, //!< T1
AMED_AARCH32_CCLASS_ORR_i_a1, //!< A1
AMED_AARCH32_CCLASS_ORR_i_t1, //!< T1
AMED_AARCH32_CCLASS_ORR_r_a1, //!< A1
AMED_AARCH32_CCLASS_ORR_r_t1, //!< T1
AMED_AARCH32_CCLASS_ORR_r_t2, //!< T2
AMED_AARCH32_CCLASS_ORR_rr_a1, //!< A1
AMED_AARCH32_CCLASS_PKH_a1, //!< A1
AMED_AARCH32_CCLASS_PKH_t1, //!< T1
AMED_AARCH32_CCLASS_PLD_i_a1, //!< A1
AMED_AARCH32_CCLASS_PLD_i_t1, //!< T1
AMED_AARCH32_CCLASS_PLD_i_t2, //!< T2
AMED_AARCH32_CCLASS_PLD_l_a1, //!< A1
AMED_AARCH32_CCLASS_PLD_l_t1, //!< T1
AMED_AARCH32_CCLASS_PLD_r_a1, //!< A1
AMED_AARCH32_CCLASS_PLD_r_t1, //!< T1
AMED_AARCH32_CCLASS_PLI_i_a1, //!< A1
AMED_AARCH32_CCLASS_PLI_i_t1, //!< T1
AMED_AARCH32_CCLASS_PLI_i_t2, //!< T2
AMED_AARCH32_CCLASS_PLI_i_t3, //!< T3
AMED_AARCH32_CCLASS_PLI_r_a1, //!< A1
AMED_AARCH32_CCLASS_PLI_r_t1, //!< T1
AMED_AARCH32_CCLASS_POP_t1, //!< T1
AMED_AARCH32_CCLASS_PSSBB_a1, //!< A1
AMED_AARCH32_CCLASS_PSSBB_t1, //!< T1
AMED_AARCH32_CCLASS_PUSH_t1, //!< T1
AMED_AARCH32_CCLASS_QADD_a1, //!< A1
AMED_AARCH32_CCLASS_QADD_t1, //!< T1
AMED_AARCH32_CCLASS_QADD16_a1, //!< A1
AMED_AARCH32_CCLASS_QADD16_t1, //!< T1
AMED_AARCH32_CCLASS_QADD8_a1, //!< A1
AMED_AARCH32_CCLASS_QADD8_t1, //!< T1
AMED_AARCH32_CCLASS_QASX_a1, //!< A1
AMED_AARCH32_CCLASS_QASX_t1, //!< T1
AMED_AARCH32_CCLASS_QDADD_a1, //!< A1
AMED_AARCH32_CCLASS_QDADD_t1, //!< T1
AMED_AARCH32_CCLASS_QDSUB_a1, //!< A1
AMED_AARCH32_CCLASS_QDSUB_t1, //!< T1
AMED_AARCH32_CCLASS_QSAX_a1, //!< A1
AMED_AARCH32_CCLASS_QSAX_t1, //!< T1
AMED_AARCH32_CCLASS_QSUB_a1, //!< A1
AMED_AARCH32_CCLASS_QSUB_t1, //!< T1
AMED_AARCH32_CCLASS_QSUB16_a1, //!< A1
AMED_AARCH32_CCLASS_QSUB16_t1, //!< T1
AMED_AARCH32_CCLASS_QSUB8_a1, //!< A1
AMED_AARCH32_CCLASS_QSUB8_t1, //!< T1
AMED_AARCH32_CCLASS_RBIT_a1, //!< A1
AMED_AARCH32_CCLASS_RBIT_t1, //!< T1
AMED_AARCH32_CCLASS_REV_a1, //!< A1
AMED_AARCH32_CCLASS_REV_t1, //!< T1
AMED_AARCH32_CCLASS_REV_t2, //!< T2
AMED_AARCH32_CCLASS_REV16_a1, //!< A1
AMED_AARCH32_CCLASS_REV16_t1, //!< T1
AMED_AARCH32_CCLASS_REV16_t2, //!< T2
AMED_AARCH32_CCLASS_REVSH_a1, //!< A1
AMED_AARCH32_CCLASS_REVSH_t1, //!< T1
AMED_AARCH32_CCLASS_REVSH_t2, //!< T2
AMED_AARCH32_CCLASS_RFE_a1, //!< A1
AMED_AARCH32_CCLASS_RFE_t1, //!< T1
AMED_AARCH32_CCLASS_RFE_t2, //!< T2
AMED_AARCH32_CCLASS_RSB_i_a1, //!< A1
AMED_AARCH32_CCLASS_RSB_i_t1, //!< T1
AMED_AARCH32_CCLASS_RSB_i_t2, //!< T2
AMED_AARCH32_CCLASS_RSB_r_a1, //!< A1
AMED_AARCH32_CCLASS_RSB_r_t1, //!< T1
AMED_AARCH32_CCLASS_RSB_rr_a1, //!< A1
AMED_AARCH32_CCLASS_RSC_i_a1, //!< A1
AMED_AARCH32_CCLASS_RSC_r_a1, //!< A1
AMED_AARCH32_CCLASS_RSC_rr_a1, //!< A1
AMED_AARCH32_CCLASS_SADD16_a1, //!< A1
AMED_AARCH32_CCLASS_SADD16_t1, //!< T1
AMED_AARCH32_CCLASS_SADD8_a1, //!< A1
AMED_AARCH32_CCLASS_SADD8_t1, //!< T1
AMED_AARCH32_CCLASS_SASX_a1, //!< A1
AMED_AARCH32_CCLASS_SASX_t1, //!< T1
AMED_AARCH32_CCLASS_SB_a1, //!< A1
AMED_AARCH32_CCLASS_SB_t1, //!< T1
AMED_AARCH32_CCLASS_SBC_i_a1, //!< A1
AMED_AARCH32_CCLASS_SBC_i_t1, //!< T1
AMED_AARCH32_CCLASS_SBC_r_a1, //!< A1
AMED_AARCH32_CCLASS_SBC_r_t1, //!< T1
AMED_AARCH32_CCLASS_SBC_r_t2, //!< T2
AMED_AARCH32_CCLASS_SBC_rr_a1, //!< A1
AMED_AARCH32_CCLASS_SBFX_a1, //!< A1
AMED_AARCH32_CCLASS_SBFX_t1, //!< T1
AMED_AARCH32_CCLASS_SDIV_a1, //!< A1
AMED_AARCH32_CCLASS_SDIV_t1, //!< T1
AMED_AARCH32_CCLASS_SEL_a1, //!< A1
AMED_AARCH32_CCLASS_SEL_t1, //!< T1
AMED_AARCH32_CCLASS_SETEND_a1, //!< A1
AMED_AARCH32_CCLASS_SETEND_t1, //!< T1
AMED_AARCH32_CCLASS_SETPAN_a1, //!< A1
AMED_AARCH32_CCLASS_SETPAN_t1, //!< T1
AMED_AARCH32_CCLASS_SEV_a1, //!< A1
AMED_AARCH32_CCLASS_SEV_t1, //!< T1
AMED_AARCH32_CCLASS_SEV_t2, //!< T2
AMED_AARCH32_CCLASS_SEVL_a1, //!< A1
AMED_AARCH32_CCLASS_SEVL_t1, //!< T1
AMED_AARCH32_CCLASS_SEVL_t2, //!< T2
AMED_AARCH32_CCLASS_SHADD16_a1, //!< A1
AMED_AARCH32_CCLASS_SHADD16_t1, //!< T1
AMED_AARCH32_CCLASS_SHADD8_a1, //!< A1
AMED_AARCH32_CCLASS_SHADD8_t1, //!< T1
AMED_AARCH32_CCLASS_SHASX_a1, //!< A1
AMED_AARCH32_CCLASS_SHASX_t1, //!< T1
AMED_AARCH32_CCLASS_SHSAX_a1, //!< A1
AMED_AARCH32_CCLASS_SHSAX_t1, //!< T1
AMED_AARCH32_CCLASS_SHSUB16_a1, //!< A1
AMED_AARCH32_CCLASS_SHSUB16_t1, //!< T1
AMED_AARCH32_CCLASS_SHSUB8_a1, //!< A1
AMED_AARCH32_CCLASS_SHSUB8_t1, //!< T1
AMED_AARCH32_CCLASS_SMC_a1, //!< A1
AMED_AARCH32_CCLASS_SMC_t1, //!< T1
AMED_AARCH32_CCLASS_SMLABB_a1, //!< A1
AMED_AARCH32_CCLASS_SMLABB_t1, //!< T1
AMED_AARCH32_CCLASS_SMLAD_a1, //!< A1
AMED_AARCH32_CCLASS_SMLAD_t1, //!< T1
AMED_AARCH32_CCLASS_SMLAL_a1, //!< A1
AMED_AARCH32_CCLASS_SMLAL_t1, //!< T1
AMED_AARCH32_CCLASS_SMLALBB_a1, //!< A1
AMED_AARCH32_CCLASS_SMLALBB_t1, //!< T1
AMED_AARCH32_CCLASS_SMLALD_a1, //!< A1
AMED_AARCH32_CCLASS_SMLALD_t1, //!< T1
AMED_AARCH32_CCLASS_SMLAWB_a1, //!< A1
AMED_AARCH32_CCLASS_SMLAWB_t1, //!< T1
AMED_AARCH32_CCLASS_SMLSD_a1, //!< A1
AMED_AARCH32_CCLASS_SMLSD_t1, //!< T1
AMED_AARCH32_CCLASS_SMLSLD_a1, //!< A1
AMED_AARCH32_CCLASS_SMLSLD_t1, //!< T1
AMED_AARCH32_CCLASS_SMMLA_a1, //!< A1
AMED_AARCH32_CCLASS_SMMLA_t1, //!< T1
AMED_AARCH32_CCLASS_SMMLS_a1, //!< A1
AMED_AARCH32_CCLASS_SMMLS_t1, //!< T1
AMED_AARCH32_CCLASS_SMMUL_a1, //!< A1
AMED_AARCH32_CCLASS_SMMUL_t1, //!< T1
AMED_AARCH32_CCLASS_SMUAD_a1, //!< A1
AMED_AARCH32_CCLASS_SMUAD_t1, //!< T1
AMED_AARCH32_CCLASS_SMULBB_a1, //!< A1
AMED_AARCH32_CCLASS_SMULBB_t1, //!< T1
AMED_AARCH32_CCLASS_SMULL_a1, //!< A1
AMED_AARCH32_CCLASS_SMULL_t1, //!< T1
AMED_AARCH32_CCLASS_SMULWB_a1, //!< A1
AMED_AARCH32_CCLASS_SMULWB_t1, //!< T1
AMED_AARCH32_CCLASS_SMUSD_a1, //!< A1
AMED_AARCH32_CCLASS_SMUSD_t1, //!< T1
AMED_AARCH32_CCLASS_SRS_a1, //!< A1
AMED_AARCH32_CCLASS_SRS_t1, //!< T1
AMED_AARCH32_CCLASS_SRS_t2, //!< T2
AMED_AARCH32_CCLASS_SSAT_a1, //!< A1
AMED_AARCH32_CCLASS_SSAT_t1, //!< T1
AMED_AARCH32_CCLASS_SSAT16_a1, //!< A1
AMED_AARCH32_CCLASS_SSAT16_t1, //!< T1
AMED_AARCH32_CCLASS_SSAX_a1, //!< A1
AMED_AARCH32_CCLASS_SSAX_t1, //!< T1
AMED_AARCH32_CCLASS_SSBB_a1, //!< A1
AMED_AARCH32_CCLASS_SSBB_t1, //!< T1
AMED_AARCH32_CCLASS_SSUB16_a1, //!< A1
AMED_AARCH32_CCLASS_SSUB16_t1, //!< T1
AMED_AARCH32_CCLASS_SSUB8_a1, //!< A1
AMED_AARCH32_CCLASS_SSUB8_t1, //!< T1
AMED_AARCH32_CCLASS_STC_a1, //!< A1
AMED_AARCH32_CCLASS_STC_t1, //!< T1
AMED_AARCH32_CCLASS_STL_a1, //!< A1
AMED_AARCH32_CCLASS_STL_t1, //!< T1
AMED_AARCH32_CCLASS_STLB_a1, //!< A1
AMED_AARCH32_CCLASS_STLB_t1, //!< T1
AMED_AARCH32_CCLASS_STLEX_a1, //!< A1
AMED_AARCH32_CCLASS_STLEX_t1, //!< T1
AMED_AARCH32_CCLASS_STLEXB_a1, //!< A1
AMED_AARCH32_CCLASS_STLEXB_t1, //!< T1
AMED_AARCH32_CCLASS_STLEXD_a1, //!< A1
AMED_AARCH32_CCLASS_STLEXD_t1, //!< T1
AMED_AARCH32_CCLASS_STLEXH_a1, //!< A1
AMED_AARCH32_CCLASS_STLEXH_t1, //!< T1
AMED_AARCH32_CCLASS_STLH_a1, //!< A1
AMED_AARCH32_CCLASS_STLH_t1, //!< T1
AMED_AARCH32_CCLASS_STM_a1, //!< A1
AMED_AARCH32_CCLASS_STM_t1, //!< T1
AMED_AARCH32_CCLASS_STM_t2, //!< T2
AMED_AARCH32_CCLASS_STM_u_a1, //!< A1
AMED_AARCH32_CCLASS_STMDA_a1, //!< A1
AMED_AARCH32_CCLASS_STMDB_a1, //!< A1
AMED_AARCH32_CCLASS_STMDB_t1, //!< T1
AMED_AARCH32_CCLASS_STMIB_a1, //!< A1
AMED_AARCH32_CCLASS_STR_i_a1, //!< A1
AMED_AARCH32_CCLASS_STR_i_t1, //!< T1
AMED_AARCH32_CCLASS_STR_i_t2, //!< T2
AMED_AARCH32_CCLASS_STR_i_t3, //!< T3
AMED_AARCH32_CCLASS_STR_i_t4, //!< T4
AMED_AARCH32_CCLASS_STR_r_a1, //!< A1
AMED_AARCH32_CCLASS_STR_r_t1, //!< T1
AMED_AARCH32_CCLASS_STR_r_t2, //!< T2
AMED_AARCH32_CCLASS_STRB_i_a1, //!< A1
AMED_AARCH32_CCLASS_STRB_i_t1, //!< T1
AMED_AARCH32_CCLASS_STRB_i_t2, //!< T2
AMED_AARCH32_CCLASS_STRB_i_t3, //!< T3
AMED_AARCH32_CCLASS_STRB_r_a1, //!< A1
AMED_AARCH32_CCLASS_STRB_r_t1, //!< T1
AMED_AARCH32_CCLASS_STRB_r_t2, //!< T2
AMED_AARCH32_CCLASS_STRBT_a1, //!< A1
AMED_AARCH32_CCLASS_STRBT_a2, //!< A2
AMED_AARCH32_CCLASS_STRBT_t1, //!< T1
AMED_AARCH32_CCLASS_STRD_i_a1, //!< A1
AMED_AARCH32_CCLASS_STRD_i_t1, //!< T1
AMED_AARCH32_CCLASS_STRD_r_a1, //!< A1
AMED_AARCH32_CCLASS_STREX_a1, //!< A1
AMED_AARCH32_CCLASS_STREX_t1, //!< T1
AMED_AARCH32_CCLASS_STREXB_a1, //!< A1
AMED_AARCH32_CCLASS_STREXB_t1, //!< T1
AMED_AARCH32_CCLASS_STREXD_a1, //!< A1
AMED_AARCH32_CCLASS_STREXD_t1, //!< T1
AMED_AARCH32_CCLASS_STREXH_a1, //!< A1
AMED_AARCH32_CCLASS_STREXH_t1, //!< T1
AMED_AARCH32_CCLASS_STRH_i_a1, //!< A1
AMED_AARCH32_CCLASS_STRH_i_t1, //!< T1
AMED_AARCH32_CCLASS_STRH_i_t2, //!< T2
AMED_AARCH32_CCLASS_STRH_i_t3, //!< T3
AMED_AARCH32_CCLASS_STRH_r_a1, //!< A1
AMED_AARCH32_CCLASS_STRH_r_t1, //!< T1
AMED_AARCH32_CCLASS_STRH_r_t2, //!< T2
AMED_AARCH32_CCLASS_STRHT_a1, //!< A1
AMED_AARCH32_CCLASS_STRHT_a2, //!< A2
AMED_AARCH32_CCLASS_STRHT_t1, //!< T1
AMED_AARCH32_CCLASS_STRT_a1, //!< A1
AMED_AARCH32_CCLASS_STRT_a2, //!< A2
AMED_AARCH32_CCLASS_STRT_t1, //!< T1
AMED_AARCH32_CCLASS_SUB_i_a1, //!< A1
AMED_AARCH32_CCLASS_SUB_i_t1, //!< T1
AMED_AARCH32_CCLASS_SUB_i_t2, //!< T2
AMED_AARCH32_CCLASS_SUB_i_t3, //!< T3
AMED_AARCH32_CCLASS_SUB_i_t4, //!< T4
AMED_AARCH32_CCLASS_SUB_i_t5, //!< T5
AMED_AARCH32_CCLASS_SUB_r_a1, //!< A1
AMED_AARCH32_CCLASS_SUB_r_t1, //!< T1
AMED_AARCH32_CCLASS_SUB_r_t2, //!< T2
AMED_AARCH32_CCLASS_SUB_rr_a1, //!< A1
AMED_AARCH32_CCLASS_SUB_SP_i_a1, //!< A1
AMED_AARCH32_CCLASS_SUB_SP_i_t1, //!< T1
AMED_AARCH32_CCLASS_SUB_SP_i_t2, //!< T2
AMED_AARCH32_CCLASS_SUB_SP_i_t3, //!< T3
AMED_AARCH32_CCLASS_SUB_SP_r_a1, //!< A1
AMED_AARCH32_CCLASS_SUB_SP_r_t1, //!< T1
AMED_AARCH32_CCLASS_SVC_a1, //!< A1
AMED_AARCH32_CCLASS_SVC_t1, //!< T1
AMED_AARCH32_CCLASS_SXTAB_a1, //!< A1
AMED_AARCH32_CCLASS_SXTAB_t1, //!< T1
AMED_AARCH32_CCLASS_SXTAB16_a1, //!< A1
AMED_AARCH32_CCLASS_SXTAB16_t1, //!< T1
AMED_AARCH32_CCLASS_SXTAH_a1, //!< A1
AMED_AARCH32_CCLASS_SXTAH_t1, //!< T1
AMED_AARCH32_CCLASS_SXTB_a1, //!< A1
AMED_AARCH32_CCLASS_SXTB_t1, //!< T1
AMED_AARCH32_CCLASS_SXTB_t2, //!< T2
AMED_AARCH32_CCLASS_SXTB16_a1, //!< A1
AMED_AARCH32_CCLASS_SXTB16_t1, //!< T1
AMED_AARCH32_CCLASS_SXTH_a1, //!< A1
AMED_AARCH32_CCLASS_SXTH_t1, //!< T1
AMED_AARCH32_CCLASS_SXTH_t2, //!< T2
AMED_AARCH32_CCLASS_TBB_t1, //!< T1
AMED_AARCH32_CCLASS_TEQ_i_a1, //!< A1
AMED_AARCH32_CCLASS_TEQ_i_t1, //!< T1
AMED_AARCH32_CCLASS_TEQ_r_a1, //!< A1
AMED_AARCH32_CCLASS_TEQ_r_t1, //!< T1
AMED_AARCH32_CCLASS_TEQ_rr_a1, //!< A1
AMED_AARCH32_CCLASS_TSB_a1, //!< A1
AMED_AARCH32_CCLASS_TSB_t1, //!< T1
AMED_AARCH32_CCLASS_TST_i_a1, //!< A1
AMED_AARCH32_CCLASS_TST_i_t1, //!< T1
AMED_AARCH32_CCLASS_TST_r_a1, //!< A1
AMED_AARCH32_CCLASS_TST_r_t1, //!< T1
AMED_AARCH32_CCLASS_TST_r_t2, //!< T2
AMED_AARCH32_CCLASS_TST_rr_a1, //!< A1
AMED_AARCH32_CCLASS_UADD16_a1, //!< A1
AMED_AARCH32_CCLASS_UADD16_t1, //!< T1
AMED_AARCH32_CCLASS_UADD8_a1, //!< A1
AMED_AARCH32_CCLASS_UADD8_t1, //!< T1
AMED_AARCH32_CCLASS_UASX_a1, //!< A1
AMED_AARCH32_CCLASS_UASX_t1, //!< T1
AMED_AARCH32_CCLASS_UBFX_a1, //!< A1
AMED_AARCH32_CCLASS_UBFX_t1, //!< T1
AMED_AARCH32_CCLASS_UDF_a1, //!< A1
AMED_AARCH32_CCLASS_UDF_t1, //!< T1
AMED_AARCH32_CCLASS_UDF_t2, //!< T2
AMED_AARCH32_CCLASS_UDIV_a1, //!< A1
AMED_AARCH32_CCLASS_UDIV_t1, //!< T1
AMED_AARCH32_CCLASS_UHADD16_a1, //!< A1
AMED_AARCH32_CCLASS_UHADD16_t1, //!< T1
AMED_AARCH32_CCLASS_UHADD8_a1, //!< A1
AMED_AARCH32_CCLASS_UHADD8_t1, //!< T1
AMED_AARCH32_CCLASS_UHASX_a1, //!< A1
AMED_AARCH32_CCLASS_UHASX_t1, //!< T1
AMED_AARCH32_CCLASS_UHSAX_a1, //!< A1
AMED_AARCH32_CCLASS_UHSAX_t1, //!< T1
AMED_AARCH32_CCLASS_UHSUB16_a1, //!< A1
AMED_AARCH32_CCLASS_UHSUB16_t1, //!< T1
AMED_AARCH32_CCLASS_UHSUB8_a1, //!< A1
AMED_AARCH32_CCLASS_UHSUB8_t1, //!< T1
AMED_AARCH32_CCLASS_UMAAL_a1, //!< A1
AMED_AARCH32_CCLASS_UMAAL_t1, //!< T1
AMED_AARCH32_CCLASS_UMLAL_a1, //!< A1
AMED_AARCH32_CCLASS_UMLAL_t1, //!< T1
AMED_AARCH32_CCLASS_UMULL_a1, //!< A1
AMED_AARCH32_CCLASS_UMULL_t1, //!< T1
AMED_AARCH32_CCLASS_UQADD16_a1, //!< A1
AMED_AARCH32_CCLASS_UQADD16_t1, //!< T1
AMED_AARCH32_CCLASS_UQADD8_a1, //!< A1
AMED_AARCH32_CCLASS_UQADD8_t1, //!< T1
AMED_AARCH32_CCLASS_UQASX_a1, //!< A1
AMED_AARCH32_CCLASS_UQASX_t1, //!< T1
AMED_AARCH32_CCLASS_UQSAX_a1, //!< A1
AMED_AARCH32_CCLASS_UQSAX_t1, //!< T1
AMED_AARCH32_CCLASS_UQSUB16_a1, //!< A1
AMED_AARCH32_CCLASS_UQSUB16_t1, //!< T1
AMED_AARCH32_CCLASS_UQSUB8_a1, //!< A1
AMED_AARCH32_CCLASS_UQSUB8_t1, //!< T1
AMED_AARCH32_CCLASS_USAD8_a1, //!< A1
AMED_AARCH32_CCLASS_USAD8_t1, //!< T1
AMED_AARCH32_CCLASS_USADA8_a1, //!< A1
AMED_AARCH32_CCLASS_USADA8_t1, //!< T1
AMED_AARCH32_CCLASS_USAT_a1, //!< A1
AMED_AARCH32_CCLASS_USAT_t1, //!< T1
AMED_AARCH32_CCLASS_USAT16_a1, //!< A1
AMED_AARCH32_CCLASS_USAT16_t1, //!< T1
AMED_AARCH32_CCLASS_USAX_a1, //!< A1
AMED_AARCH32_CCLASS_USAX_t1, //!< T1
AMED_AARCH32_CCLASS_USUB16_a1, //!< A1
AMED_AARCH32_CCLASS_USUB16_t1, //!< T1
AMED_AARCH32_CCLASS_USUB8_a1, //!< A1
AMED_AARCH32_CCLASS_USUB8_t1, //!< T1
AMED_AARCH32_CCLASS_UXTAB_a1, //!< A1
AMED_AARCH32_CCLASS_UXTAB_t1, //!< T1
AMED_AARCH32_CCLASS_UXTAB16_a1, //!< A1
AMED_AARCH32_CCLASS_UXTAB16_t1, //!< T1
AMED_AARCH32_CCLASS_UXTAH_a1, //!< A1
AMED_AARCH32_CCLASS_UXTAH_t1, //!< T1
AMED_AARCH32_CCLASS_UXTB_a1, //!< A1
AMED_AARCH32_CCLASS_UXTB_t1, //!< T1
AMED_AARCH32_CCLASS_UXTB_t2, //!< T2
AMED_AARCH32_CCLASS_UXTB16_a1, //!< A1
AMED_AARCH32_CCLASS_UXTB16_t1, //!< T1
AMED_AARCH32_CCLASS_UXTH_a1, //!< A1
AMED_AARCH32_CCLASS_UXTH_t1, //!< T1
AMED_AARCH32_CCLASS_UXTH_t2, //!< T2
AMED_AARCH32_CCLASS_WFE_a1, //!< A1
AMED_AARCH32_CCLASS_WFE_t1, //!< T1
AMED_AARCH32_CCLASS_WFE_t2, //!< T2
AMED_AARCH32_CCLASS_WFI_a1, //!< A1
AMED_AARCH32_CCLASS_WFI_t1, //!< T1
AMED_AARCH32_CCLASS_WFI_t2, //!< T2
AMED_AARCH32_CCLASS_YIELD_a1, //!< A1
AMED_AARCH32_CCLASS_YIELD_t1, //!< T1
AMED_AARCH32_CCLASS_YIELD_t2, //!< T2
AMED_AARCH32_CCLASS_ADD_ADR_a1, //!< A1
AMED_AARCH32_CCLASS_ADD_ADR_t1, //!< T1
AMED_AARCH32_CCLASS_ADD_ADR_t3, //!< T3
AMED_AARCH32_CCLASS_ASR_MOV_r_a1, //!< A1
AMED_AARCH32_CCLASS_ASR_MOV_r_t2, //!< T2
AMED_AARCH32_CCLASS_ASR_MOV_r_t3, //!< T3
AMED_AARCH32_CCLASS_ASR_MOV_rr_a1, //!< A1
AMED_AARCH32_CCLASS_ASR_MOV_rr_t1, //!< T1
AMED_AARCH32_CCLASS_ASR_MOV_rr_t2, //!< T2
AMED_AARCH32_CCLASS_ASRS_MOV_r_a1, //!< A1
AMED_AARCH32_CCLASS_ASRS_MOV_r_t2, //!< T2
AMED_AARCH32_CCLASS_ASRS_MOV_r_t3, //!< T3
AMED_AARCH32_CCLASS_ASRS_MOV_rr_a1, //!< A1
AMED_AARCH32_CCLASS_ASRS_MOV_rr_t1, //!< T1
AMED_AARCH32_CCLASS_ASRS_MOV_rr_t2, //!< T2
AMED_AARCH32_CCLASS_LSL_MOV_r_a1, //!< A1
AMED_AARCH32_CCLASS_LSL_MOV_r_t2, //!< T2
AMED_AARCH32_CCLASS_LSL_MOV_r_t3, //!< T3
AMED_AARCH32_CCLASS_LSL_MOV_rr_a1, //!< A1
AMED_AARCH32_CCLASS_LSL_MOV_rr_t1, //!< T1
AMED_AARCH32_CCLASS_LSL_MOV_rr_t2, //!< T2
AMED_AARCH32_CCLASS_LSLS_MOV_r_a1, //!< A1
AMED_AARCH32_CCLASS_LSLS_MOV_r_t2, //!< T2
AMED_AARCH32_CCLASS_LSLS_MOV_r_t3, //!< T3
AMED_AARCH32_CCLASS_LSLS_MOV_rr_a1, //!< A1
AMED_AARCH32_CCLASS_LSLS_MOV_rr_t1, //!< T1
AMED_AARCH32_CCLASS_LSLS_MOV_rr_t2, //!< T2
AMED_AARCH32_CCLASS_LSR_MOV_r_a1, //!< A1
AMED_AARCH32_CCLASS_LSR_MOV_r_t2, //!< T2
AMED_AARCH32_CCLASS_LSR_MOV_r_t3, //!< T3
AMED_AARCH32_CCLASS_LSR_MOV_rr_a1, //!< A1
AMED_AARCH32_CCLASS_LSR_MOV_rr_t1, //!< T1
AMED_AARCH32_CCLASS_LSR_MOV_rr_t2, //!< T2
AMED_AARCH32_CCLASS_LSRS_MOV_r_a1, //!< A1
AMED_AARCH32_CCLASS_LSRS_MOV_r_t2, //!< T2
AMED_AARCH32_CCLASS_LSRS_MOV_r_t3, //!< T3
AMED_AARCH32_CCLASS_LSRS_MOV_rr_a1, //!< A1
AMED_AARCH32_CCLASS_LSRS_MOV_rr_t1, //!< T1
AMED_AARCH32_CCLASS_LSRS_MOV_rr_t2, //!< T2
AMED_AARCH32_CCLASS_POP_LDM_a1, //!< A1
AMED_AARCH32_CCLASS_POP_LDM_t2, //!< T2
AMED_AARCH32_CCLASS_POP_LDR_i_a1, //!< A1
AMED_AARCH32_CCLASS_POP_LDR_i_t4, //!< T4
AMED_AARCH32_CCLASS_PUSH_STMDB_a1, //!< A1
AMED_AARCH32_CCLASS_PUSH_STMDB_t1, //!< T1
AMED_AARCH32_CCLASS_PUSH_STR_i_a1, //!< A1
AMED_AARCH32_CCLASS_PUSH_STR_i_t4, //!< T4
AMED_AARCH32_CCLASS_ROR_MOV_r_a1, //!< A1
AMED_AARCH32_CCLASS_ROR_MOV_r_t3, //!< T3
AMED_AARCH32_CCLASS_ROR_MOV_rr_a1, //!< A1
AMED_AARCH32_CCLASS_ROR_MOV_rr_t1, //!< T1
AMED_AARCH32_CCLASS_ROR_MOV_rr_t2, //!< T2
AMED_AARCH32_CCLASS_RORS_MOV_r_a1, //!< A1
AMED_AARCH32_CCLASS_RORS_MOV_r_t3, //!< T3
AMED_AARCH32_CCLASS_RORS_MOV_rr_a1, //!< A1
AMED_AARCH32_CCLASS_RORS_MOV_rr_t1, //!< T1
AMED_AARCH32_CCLASS_RORS_MOV_rr_t2, //!< T2
AMED_AARCH32_CCLASS_RRX_MOV_r_a1, //!< A1
AMED_AARCH32_CCLASS_RRX_MOV_r_t3, //!< T3
AMED_AARCH32_CCLASS_RRXS_MOV_r_a1, //!< A1
AMED_AARCH32_CCLASS_RRXS_MOV_r_t3, //!< T3
AMED_AARCH32_CCLASS_SUB_ADR_a2, //!< A2
AMED_AARCH32_CCLASS_SUB_ADR_t2, //!< T2
AMED_AARCH32_CCLASS_AESD_a1, //!< A1
AMED_AARCH32_CCLASS_AESD_t1, //!< T1
AMED_AARCH32_CCLASS_AESE_a1, //!< A1
AMED_AARCH32_CCLASS_AESE_t1, //!< T1
AMED_AARCH32_CCLASS_AESIMC_a1, //!< A1
AMED_AARCH32_CCLASS_AESIMC_t1, //!< T1
AMED_AARCH32_CCLASS_AESMC_a1, //!< A1
AMED_AARCH32_CCLASS_AESMC_t1, //!< T1
AMED_AARCH32_CCLASS_FLDMX_a1, //!< A1
AMED_AARCH32_CCLASS_FLDMX_t1, //!< T1
AMED_AARCH32_CCLASS_FSTMX_a1, //!< A1
AMED_AARCH32_CCLASS_FSTMX_t1, //!< T1
AMED_AARCH32_CCLASS_SHA1C_a1, //!< A1
AMED_AARCH32_CCLASS_SHA1C_t1, //!< T1
AMED_AARCH32_CCLASS_SHA1H_a1, //!< A1
AMED_AARCH32_CCLASS_SHA1H_t1, //!< T1
AMED_AARCH32_CCLASS_SHA1M_a1, //!< A1
AMED_AARCH32_CCLASS_SHA1M_t1, //!< T1
AMED_AARCH32_CCLASS_SHA1P_a1, //!< A1
AMED_AARCH32_CCLASS_SHA1P_t1, //!< T1
AMED_AARCH32_CCLASS_SHA1SU0_a1, //!< A1
AMED_AARCH32_CCLASS_SHA1SU0_t1, //!< T1
AMED_AARCH32_CCLASS_SHA1SU1_a1, //!< A1
AMED_AARCH32_CCLASS_SHA1SU1_t1, //!< T1
AMED_AARCH32_CCLASS_SHA256H_a1, //!< A1
AMED_AARCH32_CCLASS_SHA256H_t1, //!< T1
AMED_AARCH32_CCLASS_SHA256H2_a1, //!< A1
AMED_AARCH32_CCLASS_SHA256H2_t1, //!< T1
AMED_AARCH32_CCLASS_SHA256SU0_a1, //!< A1
AMED_AARCH32_CCLASS_SHA256SU0_t1, //!< T1
AMED_AARCH32_CCLASS_SHA256SU1_a1, //!< A1
AMED_AARCH32_CCLASS_SHA256SU1_t1, //!< T1
AMED_AARCH32_CCLASS_ST4_1_a3, //!< A3
AMED_AARCH32_CCLASS_VABA_a1, //!< A1
AMED_AARCH32_CCLASS_VABA_t1, //!< T1
AMED_AARCH32_CCLASS_VABAL_a1, //!< A1
AMED_AARCH32_CCLASS_VABAL_t1, //!< T1
AMED_AARCH32_CCLASS_VABD_f_a1, //!< A1
AMED_AARCH32_CCLASS_VABD_f_t1, //!< T1
AMED_AARCH32_CCLASS_VABD_i_a1, //!< A1
AMED_AARCH32_CCLASS_VABD_i_t1, //!< T1
AMED_AARCH32_CCLASS_VABDL_i_a1, //!< A1
AMED_AARCH32_CCLASS_VABDL_i_t1, //!< T1
AMED_AARCH32_CCLASS_VABS_a1, //!< A1
AMED_AARCH32_CCLASS_VABS_a2, //!< A2
AMED_AARCH32_CCLASS_VABS_t1, //!< T1
AMED_AARCH32_CCLASS_VABS_t2, //!< T2
AMED_AARCH32_CCLASS_VACGE_a1, //!< A1
AMED_AARCH32_CCLASS_VACGE_t1, //!< T1
AMED_AARCH32_CCLASS_VACGT_a1, //!< A1
AMED_AARCH32_CCLASS_VACGT_t1, //!< T1
AMED_AARCH32_CCLASS_VADD_f_a1, //!< A1
AMED_AARCH32_CCLASS_VADD_f_a2, //!< A2
AMED_AARCH32_CCLASS_VADD_f_t1, //!< T1
AMED_AARCH32_CCLASS_VADD_f_t2, //!< T2
AMED_AARCH32_CCLASS_VADD_i_a1, //!< A1
AMED_AARCH32_CCLASS_VADD_i_t1, //!< T1
AMED_AARCH32_CCLASS_VADDHN_a1, //!< A1
AMED_AARCH32_CCLASS_VADDHN_t1, //!< T1
AMED_AARCH32_CCLASS_VADDL_a1, //!< A1
AMED_AARCH32_CCLASS_VADDL_t1, //!< T1
AMED_AARCH32_CCLASS_VADDW_a1, //!< A1
AMED_AARCH32_CCLASS_VADDW_t1, //!< T1
AMED_AARCH32_CCLASS_VAND_r_a1, //!< A1
AMED_AARCH32_CCLASS_VAND_r_t1, //!< T1
AMED_AARCH32_CCLASS_VBIC_i_a1, //!< A1
AMED_AARCH32_CCLASS_VBIC_i_a2, //!< A2
AMED_AARCH32_CCLASS_VBIC_i_t1, //!< T1
AMED_AARCH32_CCLASS_VBIC_i_t2, //!< T2
AMED_AARCH32_CCLASS_VBIC_r_a1, //!< A1
AMED_AARCH32_CCLASS_VBIC_r_t1, //!< T1
AMED_AARCH32_CCLASS_VBIF_a1, //!< A1
AMED_AARCH32_CCLASS_VBIF_t1, //!< T1
AMED_AARCH32_CCLASS_VBIT_a1, //!< A1
AMED_AARCH32_CCLASS_VBIT_t1, //!< T1
AMED_AARCH32_CCLASS_VBSL_a1, //!< A1
AMED_AARCH32_CCLASS_VBSL_t1, //!< T1
AMED_AARCH32_CCLASS_VCADD_a1, //!< A1
AMED_AARCH32_CCLASS_VCADD_t1, //!< T1
AMED_AARCH32_CCLASS_VCEQ_i_a1, //!< A1
AMED_AARCH32_CCLASS_VCEQ_i_t1, //!< T1
AMED_AARCH32_CCLASS_VCEQ_r_a1, //!< A1
AMED_AARCH32_CCLASS_VCEQ_r_a2, //!< A2
AMED_AARCH32_CCLASS_VCEQ_r_t1, //!< T1
AMED_AARCH32_CCLASS_VCEQ_r_t2, //!< T2
AMED_AARCH32_CCLASS_VCGE_i_a1, //!< A1
AMED_AARCH32_CCLASS_VCGE_i_t1, //!< T1
AMED_AARCH32_CCLASS_VCGE_r_a1, //!< A1
AMED_AARCH32_CCLASS_VCGE_r_a2, //!< A2
AMED_AARCH32_CCLASS_VCGE_r_t1, //!< T1
AMED_AARCH32_CCLASS_VCGE_r_t2, //!< T2
AMED_AARCH32_CCLASS_VCGT_i_a1, //!< A1
AMED_AARCH32_CCLASS_VCGT_i_t1, //!< T1
AMED_AARCH32_CCLASS_VCGT_r_a1, //!< A1
AMED_AARCH32_CCLASS_VCGT_r_a2, //!< A2
AMED_AARCH32_CCLASS_VCGT_r_t1, //!< T1
AMED_AARCH32_CCLASS_VCGT_r_t2, //!< T2
AMED_AARCH32_CCLASS_VCLE_i_a1, //!< A1
AMED_AARCH32_CCLASS_VCLE_i_t1, //!< T1
AMED_AARCH32_CCLASS_VCLS_a1, //!< A1
AMED_AARCH32_CCLASS_VCLS_t1, //!< T1
AMED_AARCH32_CCLASS_VCLT_i_a1, //!< A1
AMED_AARCH32_CCLASS_VCLT_i_t1, //!< T1
AMED_AARCH32_CCLASS_VCLZ_a1, //!< A1
AMED_AARCH32_CCLASS_VCLZ_t1, //!< T1
AMED_AARCH32_CCLASS_VCMLA_a1, //!< A1
AMED_AARCH32_CCLASS_VCMLA_t1, //!< T1
AMED_AARCH32_CCLASS_VCMLA_s_a1, //!< A1
AMED_AARCH32_CCLASS_VCMLA_s_t1, //!< T1
AMED_AARCH32_CCLASS_VCMP_a1, //!< A1
AMED_AARCH32_CCLASS_VCMP_a2, //!< A2
AMED_AARCH32_CCLASS_VCMP_t1, //!< T1
AMED_AARCH32_CCLASS_VCMP_t2, //!< T2
AMED_AARCH32_CCLASS_VCMPE_a1, //!< A1
AMED_AARCH32_CCLASS_VCMPE_a2, //!< A2
AMED_AARCH32_CCLASS_VCMPE_t1, //!< T1
AMED_AARCH32_CCLASS_VCMPE_t2, //!< T2
AMED_AARCH32_CCLASS_VCNT_a1, //!< A1
AMED_AARCH32_CCLASS_VCNT_t1, //!< T1
AMED_AARCH32_CCLASS_VCVT_bfs_a1, //!< A1
AMED_AARCH32_CCLASS_VCVT_bfs_t1, //!< T1
AMED_AARCH32_CCLASS_VCVT_ds_a1, //!< A1
AMED_AARCH32_CCLASS_VCVT_ds_t1, //!< T1
AMED_AARCH32_CCLASS_VCVT_hs_a1, //!< A1
AMED_AARCH32_CCLASS_VCVT_hs_t1, //!< T1
AMED_AARCH32_CCLASS_VCVT_is_a1, //!< A1
AMED_AARCH32_CCLASS_VCVT_is_t1, //!< T1
AMED_AARCH32_CCLASS_VCVT_iv_a1, //!< A1
AMED_AARCH32_CCLASS_VCVT_iv_t1, //!< T1
AMED_AARCH32_CCLASS_VCVT_vi_a1, //!< A1
AMED_AARCH32_CCLASS_VCVT_vi_t1, //!< T1
AMED_AARCH32_CCLASS_VCVT_xs_a1, //!< A1
AMED_AARCH32_CCLASS_VCVT_xs_t1, //!< T1
AMED_AARCH32_CCLASS_VCVT_xv_a1, //!< A1
AMED_AARCH32_CCLASS_VCVT_xv_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTA_asimd_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTA_asimd_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTA_vfp_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTA_vfp_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTB_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTB_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTB_bfs_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTB_bfs_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTM_asimd_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTM_asimd_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTM_vfp_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTM_vfp_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTN_asimd_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTN_asimd_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTN_vfp_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTN_vfp_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTP_asimd_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTP_asimd_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTP_vfp_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTP_vfp_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTR_iv_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTR_iv_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTT_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTT_t1, //!< T1
AMED_AARCH32_CCLASS_VCVTT_bfs_a1, //!< A1
AMED_AARCH32_CCLASS_VCVTT_bfs_t1, //!< T1
AMED_AARCH32_CCLASS_VDIV_a1, //!< A1
AMED_AARCH32_CCLASS_VDIV_t1, //!< T1
AMED_AARCH32_CCLASS_VDOT_a1, //!< A1
AMED_AARCH32_CCLASS_VDOT_t1, //!< T1
AMED_AARCH32_CCLASS_VDOT_s_a1, //!< A1
AMED_AARCH32_CCLASS_VDOT_s_t1, //!< T1
AMED_AARCH32_CCLASS_VDUP_r_a1, //!< A1
AMED_AARCH32_CCLASS_VDUP_r_t1, //!< T1
AMED_AARCH32_CCLASS_VDUP_s_a1, //!< A1
AMED_AARCH32_CCLASS_VDUP_s_t1, //!< T1
AMED_AARCH32_CCLASS_VEOR_a1, //!< A1
AMED_AARCH32_CCLASS_VEOR_t1, //!< T1
AMED_AARCH32_CCLASS_VEXT_a1, //!< A1
AMED_AARCH32_CCLASS_VEXT_t1, //!< T1
AMED_AARCH32_CCLASS_VFMA_a1, //!< A1
AMED_AARCH32_CCLASS_VFMA_a2, //!< A2
AMED_AARCH32_CCLASS_VFMA_t1, //!< T1
AMED_AARCH32_CCLASS_VFMA_t2, //!< T2
AMED_AARCH32_CCLASS_VFMA_bf_a1, //!< A1
AMED_AARCH32_CCLASS_VFMA_bf_t1, //!< T1
AMED_AARCH32_CCLASS_VFMA_bfs_a1, //!< A1
AMED_AARCH32_CCLASS_VFMA_bfs_t1, //!< T1
AMED_AARCH32_CCLASS_VFMAL_a1, //!< A1
AMED_AARCH32_CCLASS_VFMAL_t1, //!< T1
AMED_AARCH32_CCLASS_VFMAL_s_a1, //!< A1
AMED_AARCH32_CCLASS_VFMAL_s_t1, //!< T1
AMED_AARCH32_CCLASS_VFMS_a1, //!< A1
AMED_AARCH32_CCLASS_VFMS_a2, //!< A2
AMED_AARCH32_CCLASS_VFMS_t1, //!< T1
AMED_AARCH32_CCLASS_VFMS_t2, //!< T2
AMED_AARCH32_CCLASS_VFMSL_a1, //!< A1
AMED_AARCH32_CCLASS_VFMSL_t1, //!< T1
AMED_AARCH32_CCLASS_VFMSL_s_a1, //!< A1
AMED_AARCH32_CCLASS_VFMSL_s_t1, //!< T1
AMED_AARCH32_CCLASS_VFNMA_a1, //!< A1
AMED_AARCH32_CCLASS_VFNMA_t1, //!< T1
AMED_AARCH32_CCLASS_VFNMS_a1, //!< A1
AMED_AARCH32_CCLASS_VFNMS_t1, //!< T1
AMED_AARCH32_CCLASS_VHADD_a1, //!< A1
AMED_AARCH32_CCLASS_VHADD_t1, //!< T1
AMED_AARCH32_CCLASS_VHSUB_a1, //!< A1
AMED_AARCH32_CCLASS_VHSUB_t1, //!< T1
AMED_AARCH32_CCLASS_VINS_a1, //!< A1
AMED_AARCH32_CCLASS_VINS_t1, //!< T1
AMED_AARCH32_CCLASS_VJCVT_a1, //!< A1
AMED_AARCH32_CCLASS_VJCVT_t1, //!< T1
AMED_AARCH32_CCLASS_VLD1_1_a1, //!< A1
AMED_AARCH32_CCLASS_VLD1_1_a2, //!< A2
AMED_AARCH32_CCLASS_VLD1_1_a3, //!< A3
AMED_AARCH32_CCLASS_VLD1_1_t1, //!< T1
AMED_AARCH32_CCLASS_VLD1_1_t2, //!< T2
AMED_AARCH32_CCLASS_VLD1_1_t3, //!< T3
AMED_AARCH32_CCLASS_VLD1_a_a1, //!< A1
AMED_AARCH32_CCLASS_VLD1_a_t1, //!< T1
AMED_AARCH32_CCLASS_VLD1_m_a1, //!< A1
AMED_AARCH32_CCLASS_VLD1_m_a2, //!< A2
AMED_AARCH32_CCLASS_VLD1_m_a3, //!< A3
AMED_AARCH32_CCLASS_VLD1_m_a4, //!< A4
AMED_AARCH32_CCLASS_VLD1_m_t1, //!< T1
AMED_AARCH32_CCLASS_VLD1_m_t2, //!< T2
AMED_AARCH32_CCLASS_VLD1_m_t3, //!< T3
AMED_AARCH32_CCLASS_VLD1_m_t4, //!< T4
AMED_AARCH32_CCLASS_VLD2_1_a1, //!< A1
AMED_AARCH32_CCLASS_VLD2_1_a2, //!< A2
AMED_AARCH32_CCLASS_VLD2_1_a3, //!< A3
AMED_AARCH32_CCLASS_VLD2_1_t1, //!< T1
AMED_AARCH32_CCLASS_VLD2_1_t2, //!< T2
AMED_AARCH32_CCLASS_VLD2_1_t3, //!< T3
AMED_AARCH32_CCLASS_VLD2_a_a1, //!< A1
AMED_AARCH32_CCLASS_VLD2_a_t1, //!< T1
AMED_AARCH32_CCLASS_VLD2_m_a1, //!< A1
AMED_AARCH32_CCLASS_VLD2_m_a2, //!< A2
AMED_AARCH32_CCLASS_VLD2_m_t1, //!< T1
AMED_AARCH32_CCLASS_VLD2_m_t2, //!< T2
AMED_AARCH32_CCLASS_VLD3_1_a1, //!< A1
AMED_AARCH32_CCLASS_VLD3_1_a2, //!< A2
AMED_AARCH32_CCLASS_VLD3_1_a3, //!< A3
AMED_AARCH32_CCLASS_VLD3_1_t1, //!< T1
AMED_AARCH32_CCLASS_VLD3_1_t2, //!< T2
AMED_AARCH32_CCLASS_VLD3_1_t3, //!< T3
AMED_AARCH32_CCLASS_VLD3_a_a1, //!< A1
AMED_AARCH32_CCLASS_VLD3_a_t1, //!< T1
AMED_AARCH32_CCLASS_VLD3_m_a1, //!< A1
AMED_AARCH32_CCLASS_VLD3_m_t1, //!< T1
AMED_AARCH32_CCLASS_VLD4_1_a1, //!< A1
AMED_AARCH32_CCLASS_VLD4_1_a2, //!< A2
AMED_AARCH32_CCLASS_VLD4_1_a3, //!< A3
AMED_AARCH32_CCLASS_VLD4_1_t1, //!< T1
AMED_AARCH32_CCLASS_VLD4_1_t2, //!< T2
AMED_AARCH32_CCLASS_VLD4_1_t3, //!< T3
AMED_AARCH32_CCLASS_VLD4_a_a1, //!< A1
AMED_AARCH32_CCLASS_VLD4_a_t1, //!< T1
AMED_AARCH32_CCLASS_VLD4_m_a1, //!< A1
AMED_AARCH32_CCLASS_VLD4_m_t1, //!< T1
AMED_AARCH32_CCLASS_VLDM_a1, //!< A1
AMED_AARCH32_CCLASS_VLDM_a2, //!< A2
AMED_AARCH32_CCLASS_VLDM_t1, //!< T1
AMED_AARCH32_CCLASS_VLDM_t2, //!< T2
AMED_AARCH32_CCLASS_VLDR_i_a1, //!< A1
AMED_AARCH32_CCLASS_VLDR_i_t1, //!< T1
AMED_AARCH32_CCLASS_VLDR_l_a1, //!< A1
AMED_AARCH32_CCLASS_VLDR_l_t1, //!< T1
AMED_AARCH32_CCLASS_VMAX_f_a1, //!< A1
AMED_AARCH32_CCLASS_VMAX_f_t1, //!< T1
AMED_AARCH32_CCLASS_VMAX_i_a1, //!< A1
AMED_AARCH32_CCLASS_VMAX_i_t1, //!< T1
AMED_AARCH32_CCLASS_VMAXNM_a1, //!< A1
AMED_AARCH32_CCLASS_VMAXNM_a2, //!< A2
AMED_AARCH32_CCLASS_VMAXNM_t1, //!< T1
AMED_AARCH32_CCLASS_VMAXNM_t2, //!< T2
AMED_AARCH32_CCLASS_VMIN_f_a1, //!< A1
AMED_AARCH32_CCLASS_VMIN_f_t1, //!< T1
AMED_AARCH32_CCLASS_VMIN_i_a1, //!< A1
AMED_AARCH32_CCLASS_VMIN_i_t1, //!< T1
AMED_AARCH32_CCLASS_VMINNM_a1, //!< A1
AMED_AARCH32_CCLASS_VMINNM_a2, //!< A2
AMED_AARCH32_CCLASS_VMINNM_t1, //!< T1
AMED_AARCH32_CCLASS_VMINNM_t2, //!< T2
AMED_AARCH32_CCLASS_VMLA_f_a1, //!< A1
AMED_AARCH32_CCLASS_VMLA_f_a2, //!< A2
AMED_AARCH32_CCLASS_VMLA_f_t1, //!< T1
AMED_AARCH32_CCLASS_VMLA_f_t2, //!< T2
AMED_AARCH32_CCLASS_VMLA_i_a1, //!< A1
AMED_AARCH32_CCLASS_VMLA_i_t1, //!< T1
AMED_AARCH32_CCLASS_VMLA_s_a1, //!< A1
AMED_AARCH32_CCLASS_VMLA_s_t1, //!< T1
AMED_AARCH32_CCLASS_VMLAL_i_a1, //!< A1
AMED_AARCH32_CCLASS_VMLAL_i_t1, //!< T1
AMED_AARCH32_CCLASS_VMLAL_s_a1, //!< A1
AMED_AARCH32_CCLASS_VMLAL_s_t1, //!< T1
AMED_AARCH32_CCLASS_VMLS_f_a1, //!< A1
AMED_AARCH32_CCLASS_VMLS_f_a2, //!< A2
AMED_AARCH32_CCLASS_VMLS_f_t1, //!< T1
AMED_AARCH32_CCLASS_VMLS_f_t2, //!< T2
AMED_AARCH32_CCLASS_VMLS_i_a1, //!< A1
AMED_AARCH32_CCLASS_VMLS_i_t1, //!< T1
AMED_AARCH32_CCLASS_VMLS_s_a1, //!< A1
AMED_AARCH32_CCLASS_VMLS_s_t1, //!< T1
AMED_AARCH32_CCLASS_VMLSL_i_a1, //!< A1
AMED_AARCH32_CCLASS_VMLSL_i_t1, //!< T1
AMED_AARCH32_CCLASS_VMLSL_s_a1, //!< A1
AMED_AARCH32_CCLASS_VMLSL_s_t1, //!< T1
AMED_AARCH32_CCLASS_VMMLA_a1, //!< A1
AMED_AARCH32_CCLASS_VMMLA_t1, //!< T1
AMED_AARCH32_CCLASS_VMOV_d_a1, //!< A1
AMED_AARCH32_CCLASS_VMOV_d_t1, //!< T1
AMED_AARCH32_CCLASS_VMOV_h_a1, //!< A1
AMED_AARCH32_CCLASS_VMOV_h_t1, //!< T1
AMED_AARCH32_CCLASS_VMOV_i_a1, //!< A1
AMED_AARCH32_CCLASS_VMOV_i_a2, //!< A2
AMED_AARCH32_CCLASS_VMOV_i_a3, //!< A3
AMED_AARCH32_CCLASS_VMOV_i_a4, //!< A4
AMED_AARCH32_CCLASS_a5, //!< A5
AMED_AARCH32_CCLASS_VMOV_i_t1, //!< T1
AMED_AARCH32_CCLASS_VMOV_i_t2, //!< T2
AMED_AARCH32_CCLASS_VMOV_i_t3, //!< T3
AMED_AARCH32_CCLASS_VMOV_i_t4, //!< T4
AMED_AARCH32_CCLASS_VMOV_i_t5, //!< T5
AMED_AARCH32_CCLASS_VMOV_r_a2, //!< A2
AMED_AARCH32_CCLASS_VMOV_r_t2, //!< T2
AMED_AARCH32_CCLASS_VMOV_rs_a1, //!< A1
AMED_AARCH32_CCLASS_VMOV_rs_t1, //!< T1
AMED_AARCH32_CCLASS_VMOV_s_a1, //!< A1
AMED_AARCH32_CCLASS_VMOV_s_t1, //!< T1
AMED_AARCH32_CCLASS_VMOV_sr_a1, //!< A1
AMED_AARCH32_CCLASS_VMOV_sr_t1, //!< T1
AMED_AARCH32_CCLASS_VMOV_ss_a1, //!< A1
AMED_AARCH32_CCLASS_VMOV_ss_t1, //!< T1
AMED_AARCH32_CCLASS_VMOVL_a1, //!< A1
AMED_AARCH32_CCLASS_VMOVL_t1, //!< T1
AMED_AARCH32_CCLASS_VMOVN_a1, //!< A1
AMED_AARCH32_CCLASS_VMOVN_t1, //!< T1
AMED_AARCH32_CCLASS_VMOVX_a1, //!< A1
AMED_AARCH32_CCLASS_VMOVX_t1, //!< T1
AMED_AARCH32_CCLASS_VMRS_a1, //!< A1
AMED_AARCH32_CCLASS_VMRS_t1, //!< T1
AMED_AARCH32_CCLASS_VMSR_a1, //!< A1
AMED_AARCH32_CCLASS_VMSR_t1, //!< T1
AMED_AARCH32_CCLASS_VMUL_f_a1, //!< A1
AMED_AARCH32_CCLASS_VMUL_f_a2, //!< A2
AMED_AARCH32_CCLASS_VMUL_f_t1, //!< T1
AMED_AARCH32_CCLASS_VMUL_f_t2, //!< T2
AMED_AARCH32_CCLASS_VMUL_i_a1, //!< A1
AMED_AARCH32_CCLASS_VMUL_i_t1, //!< T1
AMED_AARCH32_CCLASS_VMUL_s_a1, //!< A1
AMED_AARCH32_CCLASS_VMUL_s_t1, //!< T1
AMED_AARCH32_CCLASS_VMULL_i_a1, //!< A1
AMED_AARCH32_CCLASS_VMULL_i_t1, //!< T1
AMED_AARCH32_CCLASS_VMULL_s_a1, //!< A1
AMED_AARCH32_CCLASS_VMULL_s_t1, //!< T1
AMED_AARCH32_CCLASS_VMVN_i_a1, //!< A1
AMED_AARCH32_CCLASS_VMVN_i_a2, //!< A2
AMED_AARCH32_CCLASS_VMVN_i_a3, //!< A3
AMED_AARCH32_CCLASS_VMVN_i_t1, //!< T1
AMED_AARCH32_CCLASS_VMVN_i_t2, //!< T2
AMED_AARCH32_CCLASS_VMVN_i_t3, //!< T3
AMED_AARCH32_CCLASS_VMVN_r_a1, //!< A1
AMED_AARCH32_CCLASS_VMVN_r_t1, //!< T1
AMED_AARCH32_CCLASS_VNEG_a1, //!< A1
AMED_AARCH32_CCLASS_VNEG_a2, //!< A2
AMED_AARCH32_CCLASS_VNEG_t1, //!< T1
AMED_AARCH32_CCLASS_VNEG_t2, //!< T2
AMED_AARCH32_CCLASS_VNMLA_a1, //!< A1
AMED_AARCH32_CCLASS_VNMLA_t1, //!< T1
AMED_AARCH32_CCLASS_VNMLS_a1, //!< A1
AMED_AARCH32_CCLASS_VNMLS_t1, //!< T1
AMED_AARCH32_CCLASS_VNMUL_a1, //!< A1
AMED_AARCH32_CCLASS_VNMUL_t1, //!< T1
AMED_AARCH32_CCLASS_VORN_r_a1, //!< A1
AMED_AARCH32_CCLASS_VORN_r_t1, //!< T1
AMED_AARCH32_CCLASS_VORR_i_a1, //!< A1
AMED_AARCH32_CCLASS_VORR_i_a2, //!< A2
AMED_AARCH32_CCLASS_VORR_i_t1, //!< T1
AMED_AARCH32_CCLASS_VORR_i_t2, //!< T2
AMED_AARCH32_CCLASS_VORR_r_a1, //!< A1
AMED_AARCH32_CCLASS_VORR_r_t1, //!< T1
AMED_AARCH32_CCLASS_VPADAL_a1, //!< A1
AMED_AARCH32_CCLASS_VPADAL_t1, //!< T1
AMED_AARCH32_CCLASS_VPADD_f_a1, //!< A1
AMED_AARCH32_CCLASS_VPADD_f_t1, //!< T1
AMED_AARCH32_CCLASS_VPADD_i_a1, //!< A1
AMED_AARCH32_CCLASS_VPADD_i_t1, //!< T1
AMED_AARCH32_CCLASS_VPADDL_a1, //!< A1
AMED_AARCH32_CCLASS_VPADDL_t1, //!< T1
AMED_AARCH32_CCLASS_VPMAX_f_a1, //!< A1
AMED_AARCH32_CCLASS_VPMAX_f_t1, //!< T1
AMED_AARCH32_CCLASS_VPMAX_i_a1, //!< A1
AMED_AARCH32_CCLASS_VPMAX_i_t1, //!< T1
AMED_AARCH32_CCLASS_VPMIN_f_a1, //!< A1
AMED_AARCH32_CCLASS_VPMIN_f_t1, //!< T1
AMED_AARCH32_CCLASS_VPMIN_i_a1, //!< A1
AMED_AARCH32_CCLASS_VPMIN_i_t1, //!< T1
AMED_AARCH32_CCLASS_VQABS_a1, //!< A1
AMED_AARCH32_CCLASS_VQABS_t1, //!< T1
AMED_AARCH32_CCLASS_VQADD_a1, //!< A1
AMED_AARCH32_CCLASS_VQADD_t1, //!< T1
AMED_AARCH32_CCLASS_VQDMLAL_a1, //!< A1
AMED_AARCH32_CCLASS_VQDMLAL_a2, //!< A2
AMED_AARCH32_CCLASS_VQDMLAL_t1, //!< T1
AMED_AARCH32_CCLASS_VQDMLAL_t2, //!< T2
AMED_AARCH32_CCLASS_VQDMLSL_a1, //!< A1
AMED_AARCH32_CCLASS_VQDMLSL_a2, //!< A2
AMED_AARCH32_CCLASS_VQDMLSL_t1, //!< T1
AMED_AARCH32_CCLASS_VQDMLSL_t2, //!< T2
AMED_AARCH32_CCLASS_VQDMULH_a1, //!< A1
AMED_AARCH32_CCLASS_VQDMULH_a2, //!< A2
AMED_AARCH32_CCLASS_VQDMULH_t1, //!< T1
AMED_AARCH32_CCLASS_VQDMULH_t2, //!< T2
AMED_AARCH32_CCLASS_VQDMULL_a1, //!< A1
AMED_AARCH32_CCLASS_VQDMULL_a2, //!< A2
AMED_AARCH32_CCLASS_VQDMULL_t1, //!< T1
AMED_AARCH32_CCLASS_VQDMULL_t2, //!< T2
AMED_AARCH32_CCLASS_VQMOVN_a1, //!< A1
AMED_AARCH32_CCLASS_VQMOVN_t1, //!< T1
AMED_AARCH32_CCLASS_VQNEG_a1, //!< A1
AMED_AARCH32_CCLASS_VQNEG_t1, //!< T1
AMED_AARCH32_CCLASS_VQRDMLAH_a1, //!< A1
AMED_AARCH32_CCLASS_VQRDMLAH_a2, //!< A2
AMED_AARCH32_CCLASS_VQRDMLAH_t1, //!< T1
AMED_AARCH32_CCLASS_VQRDMLAH_t2, //!< T2
AMED_AARCH32_CCLASS_VQRDMLSH_a1, //!< A1
AMED_AARCH32_CCLASS_VQRDMLSH_a2, //!< A2
AMED_AARCH32_CCLASS_VQRDMLSH_t1, //!< T1
AMED_AARCH32_CCLASS_VQRDMLSH_t2, //!< T2
AMED_AARCH32_CCLASS_VQRDMULH_a1, //!< A1
AMED_AARCH32_CCLASS_VQRDMULH_a2, //!< A2
AMED_AARCH32_CCLASS_VQRDMULH_t1, //!< T1
AMED_AARCH32_CCLASS_VQRDMULH_t2, //!< T2
AMED_AARCH32_CCLASS_VQRSHL_a1, //!< A1
AMED_AARCH32_CCLASS_VQRSHL_t1, //!< T1
AMED_AARCH32_CCLASS_VQRSHRN_a1, //!< A1
AMED_AARCH32_CCLASS_VQRSHRN_t1, //!< T1
AMED_AARCH32_CCLASS_VQSHL_i_a1, //!< A1
AMED_AARCH32_CCLASS_VQSHL_i_t1, //!< T1
AMED_AARCH32_CCLASS_VQSHL_r_a1, //!< A1
AMED_AARCH32_CCLASS_VQSHL_r_t1, //!< T1
AMED_AARCH32_CCLASS_VQSHRN_a1, //!< A1
AMED_AARCH32_CCLASS_VQSHRN_t1, //!< T1
AMED_AARCH32_CCLASS_VQSUB_a1, //!< A1
AMED_AARCH32_CCLASS_VQSUB_t1, //!< T1
AMED_AARCH32_CCLASS_VRADDHN_a1, //!< A1
AMED_AARCH32_CCLASS_VRADDHN_t1, //!< T1
AMED_AARCH32_CCLASS_VRECPE_a1, //!< A1
AMED_AARCH32_CCLASS_VRECPE_t1, //!< T1
AMED_AARCH32_CCLASS_VRECPS_a1, //!< A1
AMED_AARCH32_CCLASS_VRECPS_t1, //!< T1
AMED_AARCH32_CCLASS_VREV16_a1, //!< A1
AMED_AARCH32_CCLASS_VREV16_t1, //!< T1
AMED_AARCH32_CCLASS_VREV32_a1, //!< A1
AMED_AARCH32_CCLASS_VREV32_t1, //!< T1
AMED_AARCH32_CCLASS_VREV64_a1, //!< A1
AMED_AARCH32_CCLASS_VREV64_t1, //!< T1
AMED_AARCH32_CCLASS_VRHADD_a1, //!< A1
AMED_AARCH32_CCLASS_VRHADD_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTA_asimd_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTA_asimd_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTA_vfp_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTA_vfp_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTM_asimd_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTM_asimd_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTM_vfp_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTM_vfp_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTN_asimd_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTN_asimd_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTN_vfp_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTN_vfp_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTP_asimd_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTP_asimd_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTP_vfp_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTP_vfp_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTR_vfp_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTR_vfp_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTX_asimd_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTX_asimd_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTX_vfp_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTX_vfp_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTZ_asimd_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTZ_asimd_t1, //!< T1
AMED_AARCH32_CCLASS_VRINTZ_vfp_a1, //!< A1
AMED_AARCH32_CCLASS_VRINTZ_vfp_t1, //!< T1
AMED_AARCH32_CCLASS_VRSHL_a1, //!< A1
AMED_AARCH32_CCLASS_VRSHL_t1, //!< T1
AMED_AARCH32_CCLASS_VRSHR_a1, //!< A1
AMED_AARCH32_CCLASS_VRSHR_t1, //!< T1
AMED_AARCH32_CCLASS_VRSHRN_a1, //!< A1
AMED_AARCH32_CCLASS_VRSHRN_t1, //!< T1
AMED_AARCH32_CCLASS_VRSQRTE_a1, //!< A1
AMED_AARCH32_CCLASS_VRSQRTE_t1, //!< T1
AMED_AARCH32_CCLASS_VRSQRTS_a1, //!< A1
AMED_AARCH32_CCLASS_VRSQRTS_t1, //!< T1
AMED_AARCH32_CCLASS_VRSRA_a1, //!< A1
AMED_AARCH32_CCLASS_VRSRA_t1, //!< T1
AMED_AARCH32_CCLASS_VRSUBHN_a1, //!< A1
AMED_AARCH32_CCLASS_VRSUBHN_t1, //!< T1
AMED_AARCH32_CCLASS_VSDOT_a1, //!< A1
AMED_AARCH32_CCLASS_VSDOT_t1, //!< T1
AMED_AARCH32_CCLASS_VSDOT_s_a1, //!< A1
AMED_AARCH32_CCLASS_VSDOT_s_t1, //!< T1
AMED_AARCH32_CCLASS_VSEL_a1, //!< A1
AMED_AARCH32_CCLASS_VSEL_t1, //!< T1
AMED_AARCH32_CCLASS_VSHL_i_a1, //!< A1
AMED_AARCH32_CCLASS_VSHL_i_t1, //!< T1
AMED_AARCH32_CCLASS_VSHL_r_a1, //!< A1
AMED_AARCH32_CCLASS_VSHL_r_t1, //!< T1
AMED_AARCH32_CCLASS_VSHLL_a1, //!< A1
AMED_AARCH32_CCLASS_VSHLL_a2, //!< A2
AMED_AARCH32_CCLASS_VSHLL_t1, //!< T1
AMED_AARCH32_CCLASS_VSHLL_t2, //!< T2
AMED_AARCH32_CCLASS_VSHR_a1, //!< A1
AMED_AARCH32_CCLASS_VSHR_t1, //!< T1
AMED_AARCH32_CCLASS_VSHRN_a1, //!< A1
AMED_AARCH32_CCLASS_VSHRN_t1, //!< T1
AMED_AARCH32_CCLASS_VSLI_a1, //!< A1
AMED_AARCH32_CCLASS_VSLI_t1, //!< T1
AMED_AARCH32_CCLASS_VSMMLA_a1, //!< A1
AMED_AARCH32_CCLASS_VSMMLA_t1, //!< T1
AMED_AARCH32_CCLASS_VSQRT_a1, //!< A1
AMED_AARCH32_CCLASS_VSQRT_t1, //!< T1
AMED_AARCH32_CCLASS_VSRA_a1, //!< A1
AMED_AARCH32_CCLASS_VSRA_t1, //!< T1
AMED_AARCH32_CCLASS_VSRI_a1, //!< A1
AMED_AARCH32_CCLASS_VSRI_t1, //!< T1
AMED_AARCH32_CCLASS_VST1_1_a1, //!< A1
AMED_AARCH32_CCLASS_VST1_1_a2, //!< A2
AMED_AARCH32_CCLASS_VST1_1_a3, //!< A3
AMED_AARCH32_CCLASS_VST1_1_t1, //!< T1
AMED_AARCH32_CCLASS_VST1_1_t2, //!< T2
AMED_AARCH32_CCLASS_VST1_1_t3, //!< T3
AMED_AARCH32_CCLASS_VST1_m_a1, //!< A1
AMED_AARCH32_CCLASS_VST1_m_a2, //!< A2
AMED_AARCH32_CCLASS_VST1_m_a3, //!< A3
AMED_AARCH32_CCLASS_VST1_m_a4, //!< A4
AMED_AARCH32_CCLASS_VST1_m_t1, //!< T1
AMED_AARCH32_CCLASS_VST1_m_t2, //!< T2
AMED_AARCH32_CCLASS_VST1_m_t3, //!< T3
AMED_AARCH32_CCLASS_VST1_m_t4, //!< T4
AMED_AARCH32_CCLASS_VST2_1_a1, //!< A1
AMED_AARCH32_CCLASS_VST2_1_a2, //!< A2
AMED_AARCH32_CCLASS_VST2_1_a3, //!< A3
AMED_AARCH32_CCLASS_VST2_1_t1, //!< T1
AMED_AARCH32_CCLASS_VST2_1_t2, //!< T2
AMED_AARCH32_CCLASS_VST2_1_t3, //!< T3
AMED_AARCH32_CCLASS_VST2_m_a1, //!< A1
AMED_AARCH32_CCLASS_VST2_m_a2, //!< A2
AMED_AARCH32_CCLASS_VST2_m_t1, //!< T1
AMED_AARCH32_CCLASS_VST2_m_t2, //!< T2
AMED_AARCH32_CCLASS_VST3_1_a1, //!< A1
AMED_AARCH32_CCLASS_VST3_1_a2, //!< A2
AMED_AARCH32_CCLASS_VST3_1_a3, //!< A3
AMED_AARCH32_CCLASS_VST3_1_t1, //!< T1
AMED_AARCH32_CCLASS_VST3_1_t2, //!< T2
AMED_AARCH32_CCLASS_VST3_1_t3, //!< T3
AMED_AARCH32_CCLASS_VST3_m_a1, //!< A1
AMED_AARCH32_CCLASS_VST3_m_t1, //!< T1
AMED_AARCH32_CCLASS_VST4_1_a1, //!< A1
AMED_AARCH32_CCLASS_VST4_1_a2, //!< A2
AMED_AARCH32_CCLASS_VST4_1_a3, //!< A3
AMED_AARCH32_CCLASS_VST4_1_t1, //!< T1
AMED_AARCH32_CCLASS_VST4_1_t2, //!< T2
AMED_AARCH32_CCLASS_VST4_1_t3, //!< T3
AMED_AARCH32_CCLASS_VST4_m_a1, //!< A1
AMED_AARCH32_CCLASS_VST4_m_t1, //!< T1
AMED_AARCH32_CCLASS_VSTM_a1, //!< A1
AMED_AARCH32_CCLASS_VSTM_a2, //!< A2
AMED_AARCH32_CCLASS_VSTM_t1, //!< T1
AMED_AARCH32_CCLASS_VSTM_t2, //!< T2
AMED_AARCH32_CCLASS_VSTR_a1, //!< A1
AMED_AARCH32_CCLASS_VSTR_t1, //!< T1
AMED_AARCH32_CCLASS_VSUB_f_a1, //!< A1
AMED_AARCH32_CCLASS_VSUB_f_a2, //!< A2
AMED_AARCH32_CCLASS_VSUB_f_t1, //!< T1
AMED_AARCH32_CCLASS_VSUB_f_t2, //!< T2
AMED_AARCH32_CCLASS_VSUB_i_a1, //!< A1
AMED_AARCH32_CCLASS_VSUB_i_t1, //!< T1
AMED_AARCH32_CCLASS_VSUBHN_a1, //!< A1
AMED_AARCH32_CCLASS_VSUBHN_t1, //!< T1
AMED_AARCH32_CCLASS_VSUBL_a1, //!< A1
AMED_AARCH32_CCLASS_VSUBL_t1, //!< T1
AMED_AARCH32_CCLASS_VSUBW_a1, //!< A1
AMED_AARCH32_CCLASS_VSUBW_t1, //!< T1
AMED_AARCH32_CCLASS_VSUDOT_s_a1, //!< A1
AMED_AARCH32_CCLASS_VSUDOT_s_t1, //!< T1
AMED_AARCH32_CCLASS_VSWP_a1, //!< A1
AMED_AARCH32_CCLASS_VSWP_t1, //!< T1
AMED_AARCH32_CCLASS_VTBL_a1, //!< A1
AMED_AARCH32_CCLASS_VTBL_t1, //!< T1
AMED_AARCH32_CCLASS_VTRN_a1, //!< A1
AMED_AARCH32_CCLASS_VTRN_t1, //!< T1
AMED_AARCH32_CCLASS_VTST_a1, //!< A1
AMED_AARCH32_CCLASS_VTST_t1, //!< T1
AMED_AARCH32_CCLASS_VUDOT_a1, //!< A1
AMED_AARCH32_CCLASS_VUDOT_t1, //!< T1
AMED_AARCH32_CCLASS_VUDOT_s_a1, //!< A1
AMED_AARCH32_CCLASS_VUDOT_s_t1, //!< T1
AMED_AARCH32_CCLASS_VUMMLA_a1, //!< A1
AMED_AARCH32_CCLASS_VUMMLA_t1, //!< T1
AMED_AARCH32_CCLASS_VUSDOT_a1, //!< A1
AMED_AARCH32_CCLASS_VUSDOT_t1, //!< T1
AMED_AARCH32_CCLASS_VUSDOT_s_a1, //!< A1
AMED_AARCH32_CCLASS_VUSDOT_s_t1, //!< T1
AMED_AARCH32_CCLASS_VUSMMLA_a1, //!< A1
AMED_AARCH32_CCLASS_VUSMMLA_t1, //!< T1
AMED_AARCH32_CCLASS_VUZP_a1, //!< A1
AMED_AARCH32_CCLASS_VUZP_t1, //!< T1
AMED_AARCH32_CCLASS_VZIP_a1, //!< A1
AMED_AARCH32_CCLASS_VZIP_t1, //!< T1
AMED_AARCH32_CCLASS_VACLE_VACGE_a1, //!< A1
AMED_AARCH32_CCLASS_VACLE_VACGE_t1, //!< T1
AMED_AARCH32_CCLASS_VACLT_VACGT_a1, //!< A1
AMED_AARCH32_CCLASS_VACLT_VACGT_t1, //!< T1
AMED_AARCH32_CCLASS_VAND_VBIC_i_a1, //!< A1
AMED_AARCH32_CCLASS_VAND_VBIC_i_a2, //!< A2
AMED_AARCH32_CCLASS_VAND_VBIC_i_t1, //!< T1
AMED_AARCH32_CCLASS_VAND_VBIC_i_t2, //!< T2
AMED_AARCH32_CCLASS_VCLE_VCGE_r_a1, //!< A1
AMED_AARCH32_CCLASS_VCLE_VCGE_r_a2, //!< A2
AMED_AARCH32_CCLASS_VCLE_VCGE_r_t1, //!< T1
AMED_AARCH32_CCLASS_VCLE_VCGE_r_t2, //!< T2
AMED_AARCH32_CCLASS_VCLT_VCGT_r_a1, //!< A1
AMED_AARCH32_CCLASS_VCLT_VCGT_r_a2, //!< A2
AMED_AARCH32_CCLASS_VCLT_VCGT_r_t1, //!< T1
AMED_AARCH32_CCLASS_VCLT_VCGT_r_t2, //!< T2
AMED_AARCH32_CCLASS_VEXT_VEXT_a1, //!< A1
AMED_AARCH32_CCLASS_VEXT_VEXT_t1, //!< T1
AMED_AARCH32_CCLASS_VMOV_VORR_r_a1, //!< A1
AMED_AARCH32_CCLASS_VMOV_VORR_r_t1, //!< T1
AMED_AARCH32_CCLASS_VORN_VORR_i_a1, //!< A1
AMED_AARCH32_CCLASS_VORN_VORR_i_a2, //!< A2
AMED_AARCH32_CCLASS_VORN_VORR_i_t1, //!< T1
AMED_AARCH32_CCLASS_VORN_VORR_i_t2, //!< T2
AMED_AARCH32_CCLASS_VPOP_VLDM_a1, //!< A1
AMED_AARCH32_CCLASS_VPOP_VLDM_a2, //!< A2
AMED_AARCH32_CCLASS_VPOP_VLDM_t1, //!< T1
AMED_AARCH32_CCLASS_VPOP_VLDM_t2, //!< T2
AMED_AARCH32_CCLASS_VPUSH_VSTM_a1, //!< A1
AMED_AARCH32_CCLASS_VPUSH_VSTM_a2, //!< A2
AMED_AARCH32_CCLASS_VPUSH_VSTM_t1, //!< T1
AMED_AARCH32_CCLASS_VPUSH_VSTM_t2, //!< T2
AMED_AARCH32_CCLASS_VQRSHRN_VQMOVN_a1, //!< A1
AMED_AARCH32_CCLASS_VQRSHRN_VQMOVN_t1, //!< T1
AMED_AARCH32_CCLASS_VQRSHRUN_VQMOVN_a1, //!< A1
AMED_AARCH32_CCLASS_VQRSHRUN_VQMOVN_t1, //!< T1
AMED_AARCH32_CCLASS_VQSHRN_VQMOVN_a1, //!< A1
AMED_AARCH32_CCLASS_VQSHRN_VQMOVN_t1, //!< T1
AMED_AARCH32_CCLASS_VQSHRUN_VQMOVN_a1, //!< A1
AMED_AARCH32_CCLASS_VQSHRUN_VQMOVN_t1, //!< T1
AMED_AARCH32_CCLASS_VRSHR_VORR_r_a1, //!< A1
AMED_AARCH32_CCLASS_VRSHR_VORR_r_t1, //!< T1
AMED_AARCH32_CCLASS_VRSHRN_VMOVN_a1, //!< A1
AMED_AARCH32_CCLASS_VRSHRN_VMOVN_t1, //!< T1
AMED_AARCH32_CCLASS_VSHR_VORR_r_a1, //!< A1
AMED_AARCH32_CCLASS_VSHR_VORR_r_t1, //!< T1
AMED_AARCH32_CCLASS_VSHRN_VMOVN_a1, //!< A1
AMED_AARCH32_CCLASS_VSHRN_VMOVN_t1, //!< T1
AMED_AARCH32_CCLASS_VUZP_VTRN_a1, //!< A1
AMED_AARCH32_CCLASS_VUZP_VTRN_t1, //!< T1
AMED_AARCH32_CCLASS_VZIP_VTRN_a1, //!< A1
AMED_AARCH32_CCLASS_VZIP_VTRN_t1, //!< T1
} amed_aarch32_cclass;
#define AMED_AARCH32_EXTENSION_MAX_TEXT_LENGTH (23 + 1)
typedef enum _amed_aarch32_extension
{
AMED_AARCH32_EXTENSION_NONE,
AMED_AARCH32_EXTENSION_AES,
AMED_AARCH32_EXTENSION_BF16,
AMED_AARCH32_EXTENSION_BIT128PMULL,
AMED_AARCH32_EXTENSION_CRC,
AMED_AARCH32_EXTENSION_DOTP,
AMED_AARCH32_EXTENSION_FCADD,
AMED_AARCH32_EXTENSION_FJCVTZS,
AMED_AARCH32_EXTENSION_FP16,
AMED_AARCH32_EXTENSION_FP16MULNOROUNDINGTOFP32,
AMED_AARCH32_EXTENSION_INT8MATMUL,
AMED_AARCH32_EXTENSION_PAN,
AMED_AARCH32_EXTENSION_QRDMLAH,
AMED_AARCH32_EXTENSION_RAS,
AMED_AARCH32_EXTENSION_SHA1,
AMED_AARCH32_EXTENSION_SHA256,
} amed_aarch32_extension;
#define AMED_AARCH32_PAGE_MAX_TEXT_LENGTH (15 + 1)
typedef enum _amed_aarch32_page
{
AMED_AARCH32_PAGE_NONE,
AMED_AARCH32_PAGE_invalid, //!< invalid:invalid
AMED_AARCH32_PAGE_ADC_i, //!< ADC, ADCS (immediate):Add with Carry (immediate)
AMED_AARCH32_PAGE_ADC_r, //!< ADC, ADCS (register):Add with Carry (register)
AMED_AARCH32_PAGE_ADC_rr, //!< ADC, ADCS (register-shifted register):Add with Carry (register-shifted register)
AMED_AARCH32_PAGE_ADD_i, //!< ADD, ADDS (immediate):Add (immediate)
AMED_AARCH32_PAGE_ADD_r, //!< ADD, ADDS (register):Add (register)
AMED_AARCH32_PAGE_ADD_rr, //!< ADD, ADDS (register-shifted register):Add (register-shifted register)
AMED_AARCH32_PAGE_ADD_SP_i, //!< ADD, ADDS (SP plus immediate):Add to SP (immediate)
AMED_AARCH32_PAGE_ADD_SP_r, //!< ADD, ADDS (SP plus register):Add to SP (register)
AMED_AARCH32_PAGE_ADR, //!< ADR:Form PC-relative address
AMED_AARCH32_PAGE_AND_i, //!< AND, ANDS (immediate):Bitwise AND (immediate)
AMED_AARCH32_PAGE_AND_r, //!< AND, ANDS (register):Bitwise AND (register)
AMED_AARCH32_PAGE_AND_rr, //!< AND, ANDS (register-shifted register):Bitwise AND (register-shifted register)
AMED_AARCH32_PAGE_B, //!< B:Branch
AMED_AARCH32_PAGE_BFC, //!< BFC:Bit Field Clear
AMED_AARCH32_PAGE_BFI, //!< BFI:Bit Field Insert
AMED_AARCH32_PAGE_BIC_i, //!< BIC, BICS (immediate):Bitwise Bit Clear (immediate)
AMED_AARCH32_PAGE_BIC_r, //!< BIC, BICS (register):Bitwise Bit Clear (register)
AMED_AARCH32_PAGE_BIC_rr, //!< BIC, BICS (register-shifted register):Bitwise Bit Clear (register-shifted register)
AMED_AARCH32_PAGE_BKPT, //!< BKPT:Breakpoint
AMED_AARCH32_PAGE_BL_i, //!< BL, BLX (immediate):Branch with Link and optional Exchange (immediate)
AMED_AARCH32_PAGE_BLX_r, //!< BLX (register):Branch with Link and Exchange (register)
AMED_AARCH32_PAGE_BX, //!< BX:Branch and Exchange
AMED_AARCH32_PAGE_BXJ, //!< BXJ:Branch and Exchange, previously Branch and Exchange Jazelle
AMED_AARCH32_PAGE_CBNZ, //!< CBNZ, CBZ:Compare and Branch on Nonzero or Zero
AMED_AARCH32_PAGE_CLREX, //!< CLREX:Clear-Exclusive
AMED_AARCH32_PAGE_CLZ, //!< CLZ:Count Leading Zeros
AMED_AARCH32_PAGE_CMN_i, //!< CMN (immediate):Compare Negative (immediate)
AMED_AARCH32_PAGE_CMN_r, //!< CMN (register):Compare Negative (register)
AMED_AARCH32_PAGE_CMN_rr, //!< CMN (register-shifted register):Compare Negative (register-shifted register)
AMED_AARCH32_PAGE_CMP_i, //!< CMP (immediate):Compare (immediate)
AMED_AARCH32_PAGE_CMP_r, //!< CMP (register):Compare (register)
AMED_AARCH32_PAGE_CMP_rr, //!< CMP (register-shifted register):Compare (register-shifted register)
AMED_AARCH32_PAGE_CPS, //!< CPS, CPSID, CPSIE:Change PE State
AMED_AARCH32_PAGE_CRC32, //!< CRC32:CRC32
AMED_AARCH32_PAGE_CRC32C, //!< CRC32C:CRC32C
AMED_AARCH32_PAGE_CSDB, //!< CSDB:Consumption of Speculative Data Barrier
AMED_AARCH32_PAGE_DBG, //!< DBG:Debug hint
AMED_AARCH32_PAGE_DCPS1, //!< DCPS1:Debug Change PE State to EL1
AMED_AARCH32_PAGE_DCPS2, //!< DCPS2:Debug Change PE State to EL2
AMED_AARCH32_PAGE_DCPS3, //!< DCPS3:Debug Change PE State to EL3
AMED_AARCH32_PAGE_DMB, //!< DMB:Data Memory Barrier
AMED_AARCH32_PAGE_DSB, //!< DSB:Data Synchronization Barrier
AMED_AARCH32_PAGE_EOR_i, //!< EOR, EORS (immediate):Bitwise Exclusive OR (immediate)
AMED_AARCH32_PAGE_EOR_r, //!< EOR, EORS (register):Bitwise Exclusive OR (register)
AMED_AARCH32_PAGE_EOR_rr, //!< EOR, EORS (register-shifted register):Bitwise Exclusive OR (register-shifted register)
AMED_AARCH32_PAGE_ERET, //!< ERET:Exception Return
AMED_AARCH32_PAGE_ESB, //!< ESB:Error Synchronization Barrier
AMED_AARCH32_PAGE_HLT, //!< HLT:Halting Breakpoint
AMED_AARCH32_PAGE_HVC, //!< HVC:Hypervisor Call
AMED_AARCH32_PAGE_ISB, //!< ISB:Instruction Synchronization Barrier
AMED_AARCH32_PAGE_IT, //!< IT:If-Then
AMED_AARCH32_PAGE_LDA, //!< LDA:Load-Acquire Word
AMED_AARCH32_PAGE_LDAB, //!< LDAB:Load-Acquire Byte
AMED_AARCH32_PAGE_LDAEX, //!< LDAEX:Load-Acquire Exclusive Word
AMED_AARCH32_PAGE_LDAEXB, //!< LDAEXB:Load-Acquire Exclusive Byte
AMED_AARCH32_PAGE_LDAEXD, //!< LDAEXD:Load-Acquire Exclusive Doubleword
AMED_AARCH32_PAGE_LDAEXH, //!< LDAEXH:Load-Acquire Exclusive Halfword
AMED_AARCH32_PAGE_LDAH, //!< LDAH:Load-Acquire Halfword
AMED_AARCH32_PAGE_LDC_i, //!< LDC (immediate):Load data to System register (immediate)
AMED_AARCH32_PAGE_LDC_l, //!< LDC (literal):Load data to System register (literal)
AMED_AARCH32_PAGE_LDM, //!< LDM, LDMIA, LDMFD:Load Multiple (Increment After, Full Descending)
AMED_AARCH32_PAGE_LDM_e, //!< LDM (exception return):Load Multiple (exception return)
AMED_AARCH32_PAGE_LDM_u, //!< LDM (User registers):Load Multiple (User registers)
AMED_AARCH32_PAGE_LDMDA, //!< LDMDA, LDMFA:Load Multiple Decrement After (Full Ascending)
AMED_AARCH32_PAGE_LDMDB, //!< LDMDB, LDMEA:Load Multiple Decrement Before (Empty Ascending)
AMED_AARCH32_PAGE_LDMIB, //!< LDMIB, LDMED:Load Multiple Increment Before (Empty Descending)
AMED_AARCH32_PAGE_LDR_i, //!< LDR (immediate):Load Register (immediate)
AMED_AARCH32_PAGE_LDR_l, //!< LDR (literal):Load Register (literal)
AMED_AARCH32_PAGE_LDR_r, //!< LDR (register):Load Register (register)
AMED_AARCH32_PAGE_LDRB_i, //!< LDRB (immediate):Load Register Byte (immediate)
AMED_AARCH32_PAGE_LDRB_l, //!< LDRB (literal):Load Register Byte (literal)
AMED_AARCH32_PAGE_LDRB_r, //!< LDRB (register):Load Register Byte (register)
AMED_AARCH32_PAGE_LDRBT, //!< LDRBT:Load Register Byte Unprivileged
AMED_AARCH32_PAGE_LDRD_i, //!< LDRD (immediate):Load Register Dual (immediate)
AMED_AARCH32_PAGE_LDRD_l, //!< LDRD (literal):Load Register Dual (literal)
AMED_AARCH32_PAGE_LDRD_r, //!< LDRD (register):Load Register Dual (register)
AMED_AARCH32_PAGE_LDREX, //!< LDREX:Load Register Exclusive
AMED_AARCH32_PAGE_LDREXB, //!< LDREXB:Load Register Exclusive Byte
AMED_AARCH32_PAGE_LDREXD, //!< LDREXD:Load Register Exclusive Doubleword
AMED_AARCH32_PAGE_LDREXH, //!< LDREXH:Load Register Exclusive Halfword
AMED_AARCH32_PAGE_LDRH_i, //!< LDRH (immediate):Load Register Halfword (immediate)
AMED_AARCH32_PAGE_LDRH_l, //!< LDRH (literal):Load Register Halfword (literal)
AMED_AARCH32_PAGE_LDRH_r, //!< LDRH (register):Load Register Halfword (register)
AMED_AARCH32_PAGE_LDRHT, //!< LDRHT:Load Register Halfword Unprivileged
AMED_AARCH32_PAGE_LDRSB_i, //!< LDRSB (immediate):Load Register Signed Byte (immediate)
AMED_AARCH32_PAGE_LDRSB_l, //!< LDRSB (literal):Load Register Signed Byte (literal)
AMED_AARCH32_PAGE_LDRSB_r, //!< LDRSB (register):Load Register Signed Byte (register)
AMED_AARCH32_PAGE_LDRSBT, //!< LDRSBT:Load Register Signed Byte Unprivileged
AMED_AARCH32_PAGE_LDRSH_i, //!< LDRSH (immediate):Load Register Signed Halfword (immediate)
AMED_AARCH32_PAGE_LDRSH_l, //!< LDRSH (literal):Load Register Signed Halfword (literal)
AMED_AARCH32_PAGE_LDRSH_r, //!< LDRSH (register):Load Register Signed Halfword (register)
AMED_AARCH32_PAGE_LDRSHT, //!< LDRSHT:Load Register Signed Halfword Unprivileged
AMED_AARCH32_PAGE_LDRT, //!< LDRT:Load Register Unprivileged
AMED_AARCH32_PAGE_MCR, //!< MCR:Move to System register from general-purpose register or execute a System instruction
AMED_AARCH32_PAGE_MCRR, //!< MCRR:Move to System register from two general-purpose registers
AMED_AARCH32_PAGE_MLA, //!< MLA, MLAS:Multiply Accumulate
AMED_AARCH32_PAGE_MLS, //!< MLS:Multiply and Subtract
AMED_AARCH32_PAGE_MOV_i, //!< MOV, MOVS (immediate):Move (immediate)
AMED_AARCH32_PAGE_MOV_r, //!< MOV, MOVS (register):Move (register)
AMED_AARCH32_PAGE_MOV_rr, //!< MOV, MOVS (register-shifted register):Move (register-shifted register)
AMED_AARCH32_PAGE_MOVT, //!< MOVT:Move Top
AMED_AARCH32_PAGE_MRC, //!< MRC:Move to general-purpose register from System register
AMED_AARCH32_PAGE_MRRC, //!< MRRC:Move to two general-purpose registers from System register
AMED_AARCH32_PAGE_MRS, //!< MRS:Move Special register to general-purpose register
AMED_AARCH32_PAGE_MRS_br, //!< MRS (Banked register):Move Banked or Special register to general-purpose register
AMED_AARCH32_PAGE_MSR_br, //!< MSR (Banked register):Move general-purpose register to Banked or Special register
AMED_AARCH32_PAGE_MSR_i, //!< MSR (immediate):Move immediate value to Special register
AMED_AARCH32_PAGE_MSR_r, //!< MSR (register):Move general-purpose register to Special register
AMED_AARCH32_PAGE_MUL, //!< MUL, MULS:Multiply
AMED_AARCH32_PAGE_MVN_i, //!< MVN, MVNS (immediate):Bitwise NOT (immediate)
AMED_AARCH32_PAGE_MVN_r, //!< MVN, MVNS (register):Bitwise NOT (register)
AMED_AARCH32_PAGE_MVN_rr, //!< MVN, MVNS (register-shifted register):Bitwise NOT (register-shifted register)
AMED_AARCH32_PAGE_NOP, //!< NOP:No Operation
AMED_AARCH32_PAGE_ORN_i, //!< ORN, ORNS (immediate):Bitwise OR NOT (immediate)
AMED_AARCH32_PAGE_ORN_r, //!< ORN, ORNS (register):Bitwise OR NOT (register)
AMED_AARCH32_PAGE_ORR_i, //!< ORR, ORRS (immediate):Bitwise OR (immediate)
AMED_AARCH32_PAGE_ORR_r, //!< ORR, ORRS (register):Bitwise OR (register)
AMED_AARCH32_PAGE_ORR_rr, //!< ORR, ORRS (register-shifted register):Bitwise OR (register-shifted register)
AMED_AARCH32_PAGE_PKH, //!< PKHBT, PKHTB:Pack Halfword
AMED_AARCH32_PAGE_PLD_i, //!< PLD, PLDW (immediate):Preload Data (immediate)
AMED_AARCH32_PAGE_PLD_l, //!< PLD (literal):Preload Data (literal)
AMED_AARCH32_PAGE_PLD_r, //!< PLD, PLDW (register):Preload Data (register)
AMED_AARCH32_PAGE_PLI_i, //!< PLI (immediate, literal):Preload Instruction (immediate, literal)
AMED_AARCH32_PAGE_PLI_r, //!< PLI (register):Preload Instruction (register)
AMED_AARCH32_PAGE_POP, //!< POP:Pop Multiple Registers from Stack
AMED_AARCH32_PAGE_PSSBB, //!< PSSBB:Physical Speculative Store Bypass Barrier
AMED_AARCH32_PAGE_PUSH, //!< PUSH:Push Multiple Registers to Stack
AMED_AARCH32_PAGE_QADD, //!< QADD:Saturating Add
AMED_AARCH32_PAGE_QADD16, //!< QADD16:Saturating Add 16
AMED_AARCH32_PAGE_QADD8, //!< QADD8:Saturating Add 8
AMED_AARCH32_PAGE_QASX, //!< QASX:Saturating Add and Subtract with Exchange
AMED_AARCH32_PAGE_QDADD, //!< QDADD:Saturating Double and Add
AMED_AARCH32_PAGE_QDSUB, //!< QDSUB:Saturating Double and Subtract
AMED_AARCH32_PAGE_QSAX, //!< QSAX:Saturating Subtract and Add with Exchange
AMED_AARCH32_PAGE_QSUB, //!< QSUB:Saturating Subtract
AMED_AARCH32_PAGE_QSUB16, //!< QSUB16:Saturating Subtract 16
AMED_AARCH32_PAGE_QSUB8, //!< QSUB8:Saturating Subtract 8
AMED_AARCH32_PAGE_RBIT, //!< RBIT:Reverse Bits
AMED_AARCH32_PAGE_REV, //!< REV:Byte-Reverse Word
AMED_AARCH32_PAGE_REV16, //!< REV16:Byte-Reverse Packed Halfword
AMED_AARCH32_PAGE_REVSH, //!< REVSH:Byte-Reverse Signed Halfword
AMED_AARCH32_PAGE_RFE, //!< RFE, RFEDA, RFEDB, RFEIA, RFEIB:Return From Exception
AMED_AARCH32_PAGE_RSB_i, //!< RSB, RSBS (immediate):Reverse Subtract (immediate)
AMED_AARCH32_PAGE_RSB_r, //!< RSB, RSBS (register):Reverse Subtract (register)
AMED_AARCH32_PAGE_RSB_rr, //!< RSB, RSBS (register-shifted register):Reverse Subtract (register-shifted register)
AMED_AARCH32_PAGE_RSC_i, //!< RSC, RSCS (immediate):Reverse Subtract with Carry (immediate)
AMED_AARCH32_PAGE_RSC_r, //!< RSC, RSCS (register):Reverse Subtract with Carry (register)
AMED_AARCH32_PAGE_RSC_rr, //!< RSC, RSCS (register-shifted register):Reverse Subtract (register-shifted register)
AMED_AARCH32_PAGE_SADD16, //!< SADD16:Signed Add 16
AMED_AARCH32_PAGE_SADD8, //!< SADD8:Signed Add 8
AMED_AARCH32_PAGE_SASX, //!< SASX:Signed Add and Subtract with Exchange
AMED_AARCH32_PAGE_SB, //!< SB:Speculation Barrier
AMED_AARCH32_PAGE_SBC_i, //!< SBC, SBCS (immediate):Subtract with Carry (immediate)
AMED_AARCH32_PAGE_SBC_r, //!< SBC, SBCS (register):Subtract with Carry (register)
AMED_AARCH32_PAGE_SBC_rr, //!< SBC, SBCS (register-shifted register):Subtract with Carry (register-shifted register)
AMED_AARCH32_PAGE_SBFX, //!< SBFX:Signed Bit Field Extract
AMED_AARCH32_PAGE_SDIV, //!< SDIV:Signed Divide
AMED_AARCH32_PAGE_SEL, //!< SEL:Select Bytes
AMED_AARCH32_PAGE_SETEND, //!< SETEND:Set Endianness
AMED_AARCH32_PAGE_SETPAN, //!< SETPAN:Set Privileged Access Never
AMED_AARCH32_PAGE_SEV, //!< SEV:Send Event
AMED_AARCH32_PAGE_SEVL, //!< SEVL:Send Event Local
AMED_AARCH32_PAGE_SHADD16, //!< SHADD16:Signed Halving Add 16
AMED_AARCH32_PAGE_SHADD8, //!< SHADD8:Signed Halving Add 8
AMED_AARCH32_PAGE_SHASX, //!< SHASX:Signed Halving Add and Subtract with Exchange
AMED_AARCH32_PAGE_SHSAX, //!< SHSAX:Signed Halving Subtract and Add with Exchange
AMED_AARCH32_PAGE_SHSUB16, //!< SHSUB16:Signed Halving Subtract 16
AMED_AARCH32_PAGE_SHSUB8, //!< SHSUB8:Signed Halving Subtract 8
AMED_AARCH32_PAGE_SMC, //!< SMC:Secure Monitor Call
AMED_AARCH32_PAGE_SMLABB, //!< SMLABB, SMLABT, SMLATB, SMLATT:Signed Multiply Accumulate (halfwords)
AMED_AARCH32_PAGE_SMLAD, //!< SMLAD, SMLADX:Signed Multiply Accumulate Dual
AMED_AARCH32_PAGE_SMLAL, //!< SMLAL, SMLALS:Signed Multiply Accumulate Long
AMED_AARCH32_PAGE_SMLALBB, //!< SMLALBB, SMLALBT, SMLALTB, SMLALTT:Signed Multiply Accumulate Long (halfwords)
AMED_AARCH32_PAGE_SMLALD, //!< SMLALD, SMLALDX:Signed Multiply Accumulate Long Dual
AMED_AARCH32_PAGE_SMLAWB, //!< SMLAWB, SMLAWT:Signed Multiply Accumulate (word by halfword)
AMED_AARCH32_PAGE_SMLSD, //!< SMLSD, SMLSDX:Signed Multiply Subtract Dual
AMED_AARCH32_PAGE_SMLSLD, //!< SMLSLD, SMLSLDX:Signed Multiply Subtract Long Dual
AMED_AARCH32_PAGE_SMMLA, //!< SMMLA, SMMLAR:Signed Most Significant Word Multiply Accumulate
AMED_AARCH32_PAGE_SMMLS, //!< SMMLS, SMMLSR:Signed Most Significant Word Multiply Subtract
AMED_AARCH32_PAGE_SMMUL, //!< SMMUL, SMMULR:Signed Most Significant Word Multiply
AMED_AARCH32_PAGE_SMUAD, //!< SMUAD, SMUADX:Signed Dual Multiply Add
AMED_AARCH32_PAGE_SMULBB, //!< SMULBB, SMULBT, SMULTB, SMULTT:Signed Multiply (halfwords)
AMED_AARCH32_PAGE_SMULL, //!< SMULL, SMULLS:Signed Multiply Long
AMED_AARCH32_PAGE_SMULWB, //!< SMULWB, SMULWT:Signed Multiply (word by halfword)
AMED_AARCH32_PAGE_SMUSD, //!< SMUSD, SMUSDX:Signed Multiply Subtract Dual
AMED_AARCH32_PAGE_SRS, //!< SRS, SRSDA, SRSDB, SRSIA, SRSIB:Store Return State
AMED_AARCH32_PAGE_SSAT, //!< SSAT:Signed Saturate
AMED_AARCH32_PAGE_SSAT16, //!< SSAT16:Signed Saturate 16
AMED_AARCH32_PAGE_SSAX, //!< SSAX:Signed Subtract and Add with Exchange
AMED_AARCH32_PAGE_SSBB, //!< SSBB:Speculative Store Bypass Barrier
AMED_AARCH32_PAGE_SSUB16, //!< SSUB16:Signed Subtract 16
AMED_AARCH32_PAGE_SSUB8, //!< SSUB8:Signed Subtract 8
AMED_AARCH32_PAGE_STC, //!< STC:Store data to System register
AMED_AARCH32_PAGE_STL, //!< STL:Store-Release Word
AMED_AARCH32_PAGE_STLB, //!< STLB:Store-Release Byte
AMED_AARCH32_PAGE_STLEX, //!< STLEX:Store-Release Exclusive Word
AMED_AARCH32_PAGE_STLEXB, //!< STLEXB:Store-Release Exclusive Byte
AMED_AARCH32_PAGE_STLEXD, //!< STLEXD:Store-Release Exclusive Doubleword
AMED_AARCH32_PAGE_STLEXH, //!< STLEXH:Store-Release Exclusive Halfword
AMED_AARCH32_PAGE_STLH, //!< STLH:Store-Release Halfword
AMED_AARCH32_PAGE_STM, //!< STM, STMIA, STMEA:Store Multiple (Increment After, Empty Ascending)
AMED_AARCH32_PAGE_STM_u, //!< STM (User registers):Store Multiple (User registers)
AMED_AARCH32_PAGE_STMDA, //!< STMDA, STMED:Store Multiple Decrement After (Empty Descending)
AMED_AARCH32_PAGE_STMDB, //!< STMDB, STMFD:Store Multiple Decrement Before (Full Descending)
AMED_AARCH32_PAGE_STMIB, //!< STMIB, STMFA:Store Multiple Increment Before (Full Ascending)
AMED_AARCH32_PAGE_STR_i, //!< STR (immediate):Store Register (immediate)
AMED_AARCH32_PAGE_STR_r, //!< STR (register):Store Register (register)
AMED_AARCH32_PAGE_STRB_i, //!< STRB (immediate):Store Register Byte (immediate)
AMED_AARCH32_PAGE_STRB_r, //!< STRB (register):Store Register Byte (register)
AMED_AARCH32_PAGE_STRBT, //!< STRBT:Store Register Byte Unprivileged
AMED_AARCH32_PAGE_STRD_i, //!< STRD (immediate):Store Register Dual (immediate)
AMED_AARCH32_PAGE_STRD_r, //!< STRD (register):Store Register Dual (register)
AMED_AARCH32_PAGE_STREX, //!< STREX:Store Register Exclusive
AMED_AARCH32_PAGE_STREXB, //!< STREXB:Store Register Exclusive Byte
AMED_AARCH32_PAGE_STREXD, //!< STREXD:Store Register Exclusive Doubleword
AMED_AARCH32_PAGE_STREXH, //!< STREXH:Store Register Exclusive Halfword
AMED_AARCH32_PAGE_STRH_i, //!< STRH (immediate):Store Register Halfword (immediate)
AMED_AARCH32_PAGE_STRH_r, //!< STRH (register):Store Register Halfword (register)
AMED_AARCH32_PAGE_STRHT, //!< STRHT:Store Register Halfword Unprivileged
AMED_AARCH32_PAGE_STRT, //!< STRT:Store Register Unprivileged
AMED_AARCH32_PAGE_SUB_i, //!< SUB, SUBS (immediate):Subtract (immediate)
AMED_AARCH32_PAGE_SUB_r, //!< SUB, SUBS (register):Subtract (register)
AMED_AARCH32_PAGE_SUB_rr, //!< SUB, SUBS (register-shifted register):Subtract (register-shifted register)
AMED_AARCH32_PAGE_SUB_SP_i, //!< SUB, SUBS (SP minus immediate):Subtract from SP (immediate)
AMED_AARCH32_PAGE_SUB_SP_r, //!< SUB, SUBS (SP minus register):Subtract from SP (register)
AMED_AARCH32_PAGE_SVC, //!< SVC:Supervisor Call
AMED_AARCH32_PAGE_SXTAB, //!< SXTAB:Signed Extend and Add Byte
AMED_AARCH32_PAGE_SXTAB16, //!< SXTAB16:Signed Extend and Add Byte 16
AMED_AARCH32_PAGE_SXTAH, //!< SXTAH:Signed Extend and Add Halfword
AMED_AARCH32_PAGE_SXTB, //!< SXTB:Signed Extend Byte
AMED_AARCH32_PAGE_SXTB16, //!< SXTB16:Signed Extend Byte 16
AMED_AARCH32_PAGE_SXTH, //!< SXTH:Signed Extend Halfword
AMED_AARCH32_PAGE_TBB, //!< TBB, TBH:Table Branch Byte or Halfword
AMED_AARCH32_PAGE_TEQ_i, //!< TEQ (immediate):Test Equivalence (immediate)
AMED_AARCH32_PAGE_TEQ_r, //!< TEQ (register):Test Equivalence (register)
AMED_AARCH32_PAGE_TEQ_rr, //!< TEQ (register-shifted register):Test Equivalence (register-shifted register)
AMED_AARCH32_PAGE_TSB, //!< TSB CSYNC:Trace Synchronization Barrier
AMED_AARCH32_PAGE_TST_i, //!< TST (immediate):Test (immediate)
AMED_AARCH32_PAGE_TST_r, //!< TST (register):Test (register)
AMED_AARCH32_PAGE_TST_rr, //!< TST (register-shifted register):Test (register-shifted register)
AMED_AARCH32_PAGE_UADD16, //!< UADD16:Unsigned Add 16
AMED_AARCH32_PAGE_UADD8, //!< UADD8:Unsigned Add 8
AMED_AARCH32_PAGE_UASX, //!< UASX:Unsigned Add and Subtract with Exchange
AMED_AARCH32_PAGE_UBFX, //!< UBFX:Unsigned Bit Field Extract
AMED_AARCH32_PAGE_UDF, //!< UDF:Permanently Undefined
AMED_AARCH32_PAGE_UDIV, //!< UDIV:Unsigned Divide
AMED_AARCH32_PAGE_UHADD16, //!< UHADD16:Unsigned Halving Add 16
AMED_AARCH32_PAGE_UHADD8, //!< UHADD8:Unsigned Halving Add 8
AMED_AARCH32_PAGE_UHASX, //!< UHASX:Unsigned Halving Add and Subtract with Exchange
AMED_AARCH32_PAGE_UHSAX, //!< UHSAX:Unsigned Halving Subtract and Add with Exchange
AMED_AARCH32_PAGE_UHSUB16, //!< UHSUB16:Unsigned Halving Subtract 16
AMED_AARCH32_PAGE_UHSUB8, //!< UHSUB8:Unsigned Halving Subtract 8
AMED_AARCH32_PAGE_UMAAL, //!< UMAAL:Unsigned Multiply Accumulate Accumulate Long
AMED_AARCH32_PAGE_UMLAL, //!< UMLAL, UMLALS:Unsigned Multiply Accumulate Long
AMED_AARCH32_PAGE_UMULL, //!< UMULL, UMULLS:Unsigned Multiply Long
AMED_AARCH32_PAGE_UQADD16, //!< UQADD16:Unsigned Saturating Add 16
AMED_AARCH32_PAGE_UQADD8, //!< UQADD8:Unsigned Saturating Add 8
AMED_AARCH32_PAGE_UQASX, //!< UQASX:Unsigned Saturating Add and Subtract with Exchange
AMED_AARCH32_PAGE_UQSAX, //!< UQSAX:Unsigned Saturating Subtract and Add with Exchange
AMED_AARCH32_PAGE_UQSUB16, //!< UQSUB16:Unsigned Saturating Subtract 16
AMED_AARCH32_PAGE_UQSUB8, //!< UQSUB8:Unsigned Saturating Subtract 8
AMED_AARCH32_PAGE_USAD8, //!< USAD8:Unsigned Sum of Absolute Differences
AMED_AARCH32_PAGE_USADA8, //!< USADA8:Unsigned Sum of Absolute Differences and Accumulate
AMED_AARCH32_PAGE_USAT, //!< USAT:Unsigned Saturate
AMED_AARCH32_PAGE_USAT16, //!< USAT16:Unsigned Saturate 16
AMED_AARCH32_PAGE_USAX, //!< USAX:Unsigned Subtract and Add with Exchange
AMED_AARCH32_PAGE_USUB16, //!< USUB16:Unsigned Subtract 16
AMED_AARCH32_PAGE_USUB8, //!< USUB8:Unsigned Subtract 8
AMED_AARCH32_PAGE_UXTAB, //!< UXTAB:Unsigned Extend and Add Byte
AMED_AARCH32_PAGE_UXTAB16, //!< UXTAB16:Unsigned Extend and Add Byte 16
AMED_AARCH32_PAGE_UXTAH, //!< UXTAH:Unsigned Extend and Add Halfword
AMED_AARCH32_PAGE_UXTB, //!< UXTB:Unsigned Extend Byte
AMED_AARCH32_PAGE_UXTB16, //!< UXTB16:Unsigned Extend Byte 16
AMED_AARCH32_PAGE_UXTH, //!< UXTH:Unsigned Extend Halfword
AMED_AARCH32_PAGE_WFE, //!< WFE:Wait For Event
AMED_AARCH32_PAGE_WFI, //!< WFI:Wait For Interrupt
AMED_AARCH32_PAGE_YIELD, //!< YIELD:Yield hint
AMED_AARCH32_PAGE_ADD_ADR, //!< ADD (immediate, to PC):Add to PC
AMED_AARCH32_PAGE_ASR_MOV_r, //!< ASR (immediate):Arithmetic Shift Right (immediate)
AMED_AARCH32_PAGE_ASR_MOV_rr, //!< ASR (register):Arithmetic Shift Right (register)
AMED_AARCH32_PAGE_ASRS_MOV_r, //!< ASRS (immediate):Arithmetic Shift Right, setting flags (immediate)
AMED_AARCH32_PAGE_ASRS_MOV_rr, //!< ASRS (register):Arithmetic Shift Right, setting flags (register)
AMED_AARCH32_PAGE_LSL_MOV_r, //!< LSL (immediate):Logical Shift Left (immediate)
AMED_AARCH32_PAGE_LSL_MOV_rr, //!< LSL (register):Logical Shift Left (register)
AMED_AARCH32_PAGE_LSLS_MOV_r, //!< LSLS (immediate):Logical Shift Left, setting flags (immediate)
AMED_AARCH32_PAGE_LSLS_MOV_rr, //!< LSLS (register):Logical Shift Left, setting flags (register)
AMED_AARCH32_PAGE_LSR_MOV_r, //!< LSR (immediate):Logical Shift Right (immediate)
AMED_AARCH32_PAGE_LSR_MOV_rr, //!< LSR (register):Logical Shift Right (register)
AMED_AARCH32_PAGE_LSRS_MOV_r, //!< LSRS (immediate):Logical Shift Right, setting flags (immediate)
AMED_AARCH32_PAGE_LSRS_MOV_rr, //!< LSRS (register):Logical Shift Right, setting flags (register)
AMED_AARCH32_PAGE_POP_LDM, //!< POP (multiple registers):Pop Multiple Registers from Stack
AMED_AARCH32_PAGE_POP_LDR_i, //!< POP (single register):Pop Single Register from Stack
AMED_AARCH32_PAGE_PUSH_STMDB, //!< PUSH (multiple registers):Push multiple registers to Stack
AMED_AARCH32_PAGE_PUSH_STR_i, //!< PUSH (single register):Push Single Register to Stack
AMED_AARCH32_PAGE_ROR_MOV_r, //!< ROR (immediate):Rotate Right (immediate)
AMED_AARCH32_PAGE_ROR_MOV_rr, //!< ROR (register):Rotate Right (register)
AMED_AARCH32_PAGE_RORS_MOV_r, //!< RORS (immediate):Rotate Right, setting flags (immediate)
AMED_AARCH32_PAGE_RORS_MOV_rr, //!< RORS (register):Rotate Right, setting flags (register)
AMED_AARCH32_PAGE_RRX_MOV_r, //!< RRX:Rotate Right with Extend
AMED_AARCH32_PAGE_RRXS_MOV_r, //!< RRXS:Rotate Right with Extend, setting flags
AMED_AARCH32_PAGE_SUB_ADR, //!< SUB (immediate, from PC):Subtract from PC
AMED_AARCH32_PAGE_AESD, //!< AESD:AES single round decryption
AMED_AARCH32_PAGE_AESE, //!< AESE:AES single round encryption
AMED_AARCH32_PAGE_AESIMC, //!< AESIMC:AES inverse mix columns
AMED_AARCH32_PAGE_AESMC, //!< AESMC:AES mix columns
AMED_AARCH32_PAGE_FLDMX, //!< FLDM*X (FLDMDBX, FLDMIAX):FLDM*X
AMED_AARCH32_PAGE_FSTMX, //!< FSTMDBX, FSTMIAX:FSTMX
AMED_AARCH32_PAGE_SHA1C, //!< SHA1C:SHA1 hash update (choose)
AMED_AARCH32_PAGE_SHA1H, //!< SHA1H:SHA1 fixed rotate
AMED_AARCH32_PAGE_SHA1M, //!< SHA1M:SHA1 hash update (majority)
AMED_AARCH32_PAGE_SHA1P, //!< SHA1P:SHA1 hash update (parity)
AMED_AARCH32_PAGE_SHA1SU0, //!< SHA1SU0:SHA1 schedule update 0
AMED_AARCH32_PAGE_SHA1SU1, //!< SHA1SU1:SHA1 schedule update 1
AMED_AARCH32_PAGE_SHA256H, //!< SHA256H:SHA256 hash update part 1
AMED_AARCH32_PAGE_SHA256H2, //!< SHA256H2:SHA256 hash update part 2
AMED_AARCH32_PAGE_SHA256SU0, //!< SHA256SU0:SHA256 schedule update 0
AMED_AARCH32_PAGE_SHA256SU1, //!< SHA256SU1:SHA256 schedule update 1
AMED_AARCH32_PAGE_ST4_1, //!< VST4 (single 4-element structure from one lane):Store single 4-element structure from one lane of four registers
AMED_AARCH32_PAGE_VABA, //!< VABA:Vector Absolute Difference and Accumulate
AMED_AARCH32_PAGE_VABAL, //!< VABAL:Vector Absolute Difference and Accumulate Long
AMED_AARCH32_PAGE_VABD_f, //!< VABD (floating-point):Vector Absolute Difference (floating-point)
AMED_AARCH32_PAGE_VABD_i, //!< VABD (integer):Vector Absolute Difference (integer)
AMED_AARCH32_PAGE_VABDL_i, //!< VABDL (integer):Vector Absolute Difference Long (integer)
AMED_AARCH32_PAGE_VABS, //!< VABS:Vector Absolute
AMED_AARCH32_PAGE_VACGE, //!< VACGE:Vector Absolute Compare Greater Than or Equal
AMED_AARCH32_PAGE_VACGT, //!< VACGT:Vector Absolute Compare Greater Than
AMED_AARCH32_PAGE_VADD_f, //!< VADD (floating-point):Vector Add (floating-point)
AMED_AARCH32_PAGE_VADD_i, //!< VADD (integer):Vector Add (integer)
AMED_AARCH32_PAGE_VADDHN, //!< VADDHN:Vector Add and Narrow, returning High Half
AMED_AARCH32_PAGE_VADDL, //!< VADDL:Vector Add Long
AMED_AARCH32_PAGE_VADDW, //!< VADDW:Vector Add Wide
AMED_AARCH32_PAGE_VAND_r, //!< VAND (register):Vector Bitwise AND (register)
AMED_AARCH32_PAGE_VBIC_i, //!< VBIC (immediate):Vector Bitwise Bit Clear (immediate)
AMED_AARCH32_PAGE_VBIC_r, //!< VBIC (register):Vector Bitwise Bit Clear (register)
AMED_AARCH32_PAGE_VBIF, //!< VBIF:Vector Bitwise Insert if False
AMED_AARCH32_PAGE_VBIT, //!< VBIT:Vector Bitwise Insert if True
AMED_AARCH32_PAGE_VBSL, //!< VBSL:Vector Bitwise Select
AMED_AARCH32_PAGE_VCADD, //!< VCADD:Vector Complex Add
AMED_AARCH32_PAGE_VCEQ_i, //!< VCEQ (immediate #0):Vector Compare Equal to Zero
AMED_AARCH32_PAGE_VCEQ_r, //!< VCEQ (register):Vector Compare Equal
AMED_AARCH32_PAGE_VCGE_i, //!< VCGE (immediate #0):Vector Compare Greater Than or Equal to Zero
AMED_AARCH32_PAGE_VCGE_r, //!< VCGE (register):Vector Compare Greater Than or Equal
AMED_AARCH32_PAGE_VCGT_i, //!< VCGT (immediate #0):Vector Compare Greater Than Zero
AMED_AARCH32_PAGE_VCGT_r, //!< VCGT (register):Vector Compare Greater Than
AMED_AARCH32_PAGE_VCLE_i, //!< VCLE (immediate #0):Vector Compare Less Than or Equal to Zero
AMED_AARCH32_PAGE_VCLS, //!< VCLS:Vector Count Leading Sign Bits
AMED_AARCH32_PAGE_VCLT_i, //!< VCLT (immediate #0):Vector Compare Less Than Zero
AMED_AARCH32_PAGE_VCLZ, //!< VCLZ:Vector Count Leading Zeros
AMED_AARCH32_PAGE_VCMLA, //!< VCMLA:Vector Complex Multiply Accumulate
AMED_AARCH32_PAGE_VCMLA_s, //!< VCMLA (by element):Vector Complex Multiply Accumulate (by element)
AMED_AARCH32_PAGE_VCMP, //!< VCMP:Vector Compare
AMED_AARCH32_PAGE_VCMPE, //!< VCMPE:Vector Compare, raising Invalid Operation on NaN
AMED_AARCH32_PAGE_VCNT, //!< VCNT:Vector Count Set Bits
AMED_AARCH32_PAGE_VCVT_bfs, //!< VCVT (from single-precision to BFloat16, Advanced SIMD):Vector Convert from single-precision to BFloat16
AMED_AARCH32_PAGE_VCVT_ds, //!< VCVT (between double-precision and single-precision):Convert between double-precision and single-precision
AMED_AARCH32_PAGE_VCVT_hs, //!< VCVT (between half-precision and single-precision, Advanced SIMD):Vector Convert between half-precision and single-precision
AMED_AARCH32_PAGE_VCVT_is, //!< VCVT (between floating-point and integer, Advanced SIMD):Vector Convert between floating-point and integer
AMED_AARCH32_PAGE_VCVT_iv, //!< VCVT (floating-point to integer, floating-point):Convert floating-point to integer with Round towards Zero
AMED_AARCH32_PAGE_VCVT_vi, //!< VCVT (integer to floating-point, floating-point):Convert integer to floating-point
AMED_AARCH32_PAGE_VCVT_xs, //!< VCVT (between floating-point and fixed-point, Advanced SIMD):Vector Convert between floating-point and fixed-point
AMED_AARCH32_PAGE_VCVT_xv, //!< VCVT (between floating-point and fixed-point, floating-point):Convert between floating-point and fixed-point
AMED_AARCH32_PAGE_VCVTA_asimd, //!< VCVTA (Advanced SIMD):Vector Convert floating-point to integer with Round to Nearest with Ties to Away
AMED_AARCH32_PAGE_VCVTA_vfp, //!< VCVTA (floating-point):Convert floating-point to integer with Round to Nearest with Ties to Away
AMED_AARCH32_PAGE_VCVTB, //!< VCVTB:Convert to or from a half-precision value in the bottom half of a single-precision register
AMED_AARCH32_PAGE_VCVTB_bfs, //!< VCVTB (BFloat16):Converts from a single-precision value to a BFloat16 value in the bottom half of a single-precision register
AMED_AARCH32_PAGE_VCVTM_asimd, //!< VCVTM (Advanced SIMD):Vector Convert floating-point to integer with Round towards -Infinity
AMED_AARCH32_PAGE_VCVTM_vfp, //!< VCVTM (floating-point):Convert floating-point to integer with Round towards -Infinity
AMED_AARCH32_PAGE_VCVTN_asimd, //!< VCVTN (Advanced SIMD):Vector Convert floating-point to integer with Round to Nearest
AMED_AARCH32_PAGE_VCVTN_vfp, //!< VCVTN (floating-point):Convert floating-point to integer with Round to Nearest
AMED_AARCH32_PAGE_VCVTP_asimd, //!< VCVTP (Advanced SIMD):Vector Convert floating-point to integer with Round towards +Infinity
AMED_AARCH32_PAGE_VCVTP_vfp, //!< VCVTP (floating-point):Convert floating-point to integer with Round towards +Infinity
AMED_AARCH32_PAGE_VCVTR_iv, //!< VCVTR:Convert floating-point to integer
AMED_AARCH32_PAGE_VCVTT, //!< VCVTT:Convert to or from a half-precision value in the top half of a single-precision register
AMED_AARCH32_PAGE_VCVTT_bfs, //!< VCVTT (BFloat16):Converts from a single-precision value to a BFloat16 value in the top half of a single-precision register.
AMED_AARCH32_PAGE_VDIV, //!< VDIV:Divide
AMED_AARCH32_PAGE_VDOT, //!< VDOT (vector):BFloat16 floating-point (BF16) dot product (vector)
AMED_AARCH32_PAGE_VDOT_s, //!< VDOT (by element):BFloat16 floating-point indexed dot product (vector, by element)
AMED_AARCH32_PAGE_VDUP_r, //!< VDUP (general-purpose register):Duplicate general-purpose register to vector
AMED_AARCH32_PAGE_VDUP_s, //!< VDUP (scalar):Duplicate vector element to vector
AMED_AARCH32_PAGE_VEOR, //!< VEOR:Vector Bitwise Exclusive OR
AMED_AARCH32_PAGE_VEXT, //!< VEXT (byte elements):Vector Extract
AMED_AARCH32_PAGE_VFMA, //!< VFMA:Vector Fused Multiply Accumulate
AMED_AARCH32_PAGE_VFMA_bf, //!< VFMAB, VFMAT (BFloat16, vector):BFloat16 floating-point widening multiply-add long (vector)
AMED_AARCH32_PAGE_VFMA_bfs, //!< VFMAB, VFMAT (BFloat16, by scalar):BFloat16 floating-point widening multiply-add long (by scalar)
AMED_AARCH32_PAGE_VFMAL, //!< VFMAL (vector):Vector Floating-point Multiply-Add Long to accumulator (vector)
AMED_AARCH32_PAGE_VFMAL_s, //!< VFMAL (by scalar):Vector Floating-point Multiply-Add Long to accumulator (by scalar)
AMED_AARCH32_PAGE_VFMS, //!< VFMS:Vector Fused Multiply Subtract
AMED_AARCH32_PAGE_VFMSL, //!< VFMSL (vector):Vector Floating-point Multiply-Subtract Long from accumulator (vector)
AMED_AARCH32_PAGE_VFMSL_s, //!< VFMSL (by scalar):Vector Floating-point Multiply-Subtract Long from accumulator (by scalar)
AMED_AARCH32_PAGE_VFNMA, //!< VFNMA:Vector Fused Negate Multiply Accumulate
AMED_AARCH32_PAGE_VFNMS, //!< VFNMS:Vector Fused Negate Multiply Subtract
AMED_AARCH32_PAGE_VHADD, //!< VHADD:Vector Halving Add
AMED_AARCH32_PAGE_VHSUB, //!< VHSUB:Vector Halving Subtract
AMED_AARCH32_PAGE_VINS, //!< VINS:Vector move Insertion
AMED_AARCH32_PAGE_VJCVT, //!< VJCVT:Javascript Convert to signed fixed-point, rounding toward Zero
AMED_AARCH32_PAGE_VLD1_1, //!< VLD1 (single element to one lane):Load single 1-element structure to one lane of one register
AMED_AARCH32_PAGE_VLD1_a, //!< VLD1 (single element to all lanes):Load single 1-element structure and replicate to all lanes of one register
AMED_AARCH32_PAGE_VLD1_m, //!< VLD1 (multiple single elements):Load multiple single 1-element structures to one, two, three, or four registers
AMED_AARCH32_PAGE_VLD2_1, //!< VLD2 (single 2-element structure to one lane):Load single 2-element structure to one lane of two registers
AMED_AARCH32_PAGE_VLD2_a, //!< VLD2 (single 2-element structure to all lanes):Load single 2-element structure and replicate to all lanes of two registers
AMED_AARCH32_PAGE_VLD2_m, //!< VLD2 (multiple 2-element structures):Load multiple 2-element structures to two or four registers
AMED_AARCH32_PAGE_VLD3_1, //!< VLD3 (single 3-element structure to one lane):Load single 3-element structure to one lane of three registers
AMED_AARCH32_PAGE_VLD3_a, //!< VLD3 (single 3-element structure to all lanes):Load single 3-element structure and replicate to all lanes of three registers
AMED_AARCH32_PAGE_VLD3_m, //!< VLD3 (multiple 3-element structures):Load multiple 3-element structures to three registers
AMED_AARCH32_PAGE_VLD4_1, //!< VLD4 (single 4-element structure to one lane):Load single 4-element structure to one lane of four registers
AMED_AARCH32_PAGE_VLD4_a, //!< VLD4 (single 4-element structure to all lanes):Load single 4-element structure and replicate to all lanes of four registers
AMED_AARCH32_PAGE_VLD4_m, //!< VLD4 (multiple 4-element structures):Load multiple 4-element structures to four registers
AMED_AARCH32_PAGE_VLDM, //!< VLDM, VLDMDB, VLDMIA:Load Multiple SIMD&FP registers
AMED_AARCH32_PAGE_VLDR_i, //!< VLDR (immediate):Load SIMD&FP register (immediate)
AMED_AARCH32_PAGE_VLDR_l, //!< VLDR (literal):Load SIMD&FP register (literal)
AMED_AARCH32_PAGE_VMAX_f, //!< VMAX (floating-point):Vector Maximum (floating-point)
AMED_AARCH32_PAGE_VMAX_i, //!< VMAX (integer):Vector Maximum (integer)
AMED_AARCH32_PAGE_VMAXNM, //!< VMAXNM:Floating-point Maximum Number
AMED_AARCH32_PAGE_VMIN_f, //!< VMIN (floating-point):Vector Minimum (floating-point)
AMED_AARCH32_PAGE_VMIN_i, //!< VMIN (integer):Vector Minimum (integer)
AMED_AARCH32_PAGE_VMINNM, //!< VMINNM:Floating-point Minimum Number
AMED_AARCH32_PAGE_VMLA_f, //!< VMLA (floating-point):Vector Multiply Accumulate (floating-point)
AMED_AARCH32_PAGE_VMLA_i, //!< VMLA (integer):Vector Multiply Accumulate (integer)
AMED_AARCH32_PAGE_VMLA_s, //!< VMLA (by scalar):Vector Multiply Accumulate (by scalar)
AMED_AARCH32_PAGE_VMLAL_i, //!< VMLAL (integer):Vector Multiply Accumulate Long (integer)
AMED_AARCH32_PAGE_VMLAL_s, //!< VMLAL (by scalar):Vector Multiply Accumulate Long (by scalar)
AMED_AARCH32_PAGE_VMLS_f, //!< VMLS (floating-point):Vector Multiply Subtract (floating-point)
AMED_AARCH32_PAGE_VMLS_i, //!< VMLS (integer):Vector Multiply Subtract (integer)
AMED_AARCH32_PAGE_VMLS_s, //!< VMLS (by scalar):Vector Multiply Subtract (by scalar)
AMED_AARCH32_PAGE_VMLSL_i, //!< VMLSL (integer):Vector Multiply Subtract Long (integer)
AMED_AARCH32_PAGE_VMLSL_s, //!< VMLSL (by scalar):Vector Multiply Subtract Long (by scalar)
AMED_AARCH32_PAGE_VMMLA, //!< VMMLA:BFloat16 floating-point matrix multiply-accumulate
AMED_AARCH32_PAGE_VMOV_d, //!< VMOV (between two general-purpose registers and a doubleword floating-point register):Copy two general-purpose registers to or from a SIMD&FP register
AMED_AARCH32_PAGE_VMOV_h, //!< VMOV (between general-purpose register and half-precision):Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register
AMED_AARCH32_PAGE_VMOV_i, //!< VMOV (immediate):Copy immediate value to a SIMD&FP register
AMED_AARCH32_PAGE_VMOV_r, //!< VMOV (register):Copy between FP registers
AMED_AARCH32_PAGE_VMOV_rs, //!< VMOV (general-purpose register to scalar):Copy a general-purpose register to a vector element
AMED_AARCH32_PAGE_VMOV_s, //!< VMOV (between general-purpose register and single-precision):Copy a general-purpose register to or from a 32-bit SIMD&FP register
AMED_AARCH32_PAGE_VMOV_sr, //!< VMOV (scalar to general-purpose register):Copy a vector element to a general-purpose register with sign or zero extension
AMED_AARCH32_PAGE_VMOV_ss, //!< VMOV (between two general-purpose registers and two single-precision registers):Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers
AMED_AARCH32_PAGE_VMOVL, //!< VMOVL:Vector Move Long
AMED_AARCH32_PAGE_VMOVN, //!< VMOVN:Vector Move and Narrow
AMED_AARCH32_PAGE_VMOVX, //!< VMOVX:Vector Move extraction
AMED_AARCH32_PAGE_VMRS, //!< VMRS:Move SIMD&FP Special register to general-purpose register
AMED_AARCH32_PAGE_VMSR, //!< VMSR:Move general-purpose register to SIMD&FP Special register
AMED_AARCH32_PAGE_VMUL_f, //!< VMUL (floating-point):Vector Multiply (floating-point)
AMED_AARCH32_PAGE_VMUL_i, //!< VMUL (integer and polynomial):Vector Multiply (integer and polynomial)
AMED_AARCH32_PAGE_VMUL_s, //!< VMUL (by scalar):Vector Multiply (by scalar)
AMED_AARCH32_PAGE_VMULL_i, //!< VMULL (integer and polynomial):Vector Multiply Long (integer and polynomial)
AMED_AARCH32_PAGE_VMULL_s, //!< VMULL (by scalar):Vector Multiply Long (by scalar)
AMED_AARCH32_PAGE_VMVN_i, //!< VMVN (immediate):Vector Bitwise NOT (immediate)
AMED_AARCH32_PAGE_VMVN_r, //!< VMVN (register):Vector Bitwise NOT (register)
AMED_AARCH32_PAGE_VNEG, //!< VNEG:Vector Negate
AMED_AARCH32_PAGE_VNMLA, //!< VNMLA:Vector Negate Multiply Accumulate
AMED_AARCH32_PAGE_VNMLS, //!< VNMLS:Vector Negate Multiply Subtract
AMED_AARCH32_PAGE_VNMUL, //!< VNMUL:Vector Negate Multiply
AMED_AARCH32_PAGE_VORN_r, //!< VORN (register):Vector bitwise OR NOT (register)
AMED_AARCH32_PAGE_VORR_i, //!< VORR (immediate):Vector Bitwise OR (immediate)
AMED_AARCH32_PAGE_VORR_r, //!< VORR (register):Vector bitwise OR (register)
AMED_AARCH32_PAGE_VPADAL, //!< VPADAL:Vector Pairwise Add and Accumulate Long
AMED_AARCH32_PAGE_VPADD_f, //!< VPADD (floating-point):Vector Pairwise Add (floating-point)
AMED_AARCH32_PAGE_VPADD_i, //!< VPADD (integer):Vector Pairwise Add (integer)
AMED_AARCH32_PAGE_VPADDL, //!< VPADDL:Vector Pairwise Add Long
AMED_AARCH32_PAGE_VPMAX_f, //!< VPMAX (floating-point):Vector Pairwise Maximum (floating-point)
AMED_AARCH32_PAGE_VPMAX_i, //!< VPMAX (integer):Vector Pairwise Maximum (integer)
AMED_AARCH32_PAGE_VPMIN_f, //!< VPMIN (floating-point):Vector Pairwise Minimum (floating-point)
AMED_AARCH32_PAGE_VPMIN_i, //!< VPMIN (integer):Vector Pairwise Minimum (integer)
AMED_AARCH32_PAGE_VQABS, //!< VQABS:Vector Saturating Absolute
AMED_AARCH32_PAGE_VQADD, //!< VQADD:Vector Saturating Add
AMED_AARCH32_PAGE_VQDMLAL, //!< VQDMLAL:Vector Saturating Doubling Multiply Accumulate Long
AMED_AARCH32_PAGE_VQDMLSL, //!< VQDMLSL:Vector Saturating Doubling Multiply Subtract Long
AMED_AARCH32_PAGE_VQDMULH, //!< VQDMULH:Vector Saturating Doubling Multiply Returning High Half
AMED_AARCH32_PAGE_VQDMULL, //!< VQDMULL:Vector Saturating Doubling Multiply Long
AMED_AARCH32_PAGE_VQMOVN, //!< VQMOVN, VQMOVUN:Vector Saturating Move and Narrow
AMED_AARCH32_PAGE_VQNEG, //!< VQNEG:Vector Saturating Negate
AMED_AARCH32_PAGE_VQRDMLAH, //!< VQRDMLAH:Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half
AMED_AARCH32_PAGE_VQRDMLSH, //!< VQRDMLSH:Vector Saturating Rounding Doubling Multiply Subtract Returning High Half
AMED_AARCH32_PAGE_VQRDMULH, //!< VQRDMULH:Vector Saturating Rounding Doubling Multiply Returning High Half
AMED_AARCH32_PAGE_VQRSHL, //!< VQRSHL:Vector Saturating Rounding Shift Left
AMED_AARCH32_PAGE_VQRSHRN, //!< VQRSHRN, VQRSHRUN:Vector Saturating Rounding Shift Right, Narrow
AMED_AARCH32_PAGE_VQSHL_i, //!< VQSHL, VQSHLU (immediate):Vector Saturating Shift Left (immediate)
AMED_AARCH32_PAGE_VQSHL_r, //!< VQSHL (register):Vector Saturating Shift Left (register)
AMED_AARCH32_PAGE_VQSHRN, //!< VQSHRN, VQSHRUN:Vector Saturating Shift Right, Narrow
AMED_AARCH32_PAGE_VQSUB, //!< VQSUB:Vector Saturating Subtract
AMED_AARCH32_PAGE_VRADDHN, //!< VRADDHN:Vector Rounding Add and Narrow, returning High Half
AMED_AARCH32_PAGE_VRECPE, //!< VRECPE:Vector Reciprocal Estimate
AMED_AARCH32_PAGE_VRECPS, //!< VRECPS:Vector Reciprocal Step
AMED_AARCH32_PAGE_VREV16, //!< VREV16:Vector Reverse in halfwords
AMED_AARCH32_PAGE_VREV32, //!< VREV32:Vector Reverse in words
AMED_AARCH32_PAGE_VREV64, //!< VREV64:Vector Reverse in doublewords
AMED_AARCH32_PAGE_VRHADD, //!< VRHADD:Vector Rounding Halving Add
AMED_AARCH32_PAGE_VRINTA_asimd, //!< VRINTA (Advanced SIMD):Vector Round floating-point to integer towards Nearest with Ties to Away
AMED_AARCH32_PAGE_VRINTA_vfp, //!< VRINTA (floating-point):Round floating-point to integer to Nearest with Ties to Away
AMED_AARCH32_PAGE_VRINTM_asimd, //!< VRINTM (Advanced SIMD):Vector Round floating-point to integer towards -Infinity
AMED_AARCH32_PAGE_VRINTM_vfp, //!< VRINTM (floating-point):Round floating-point to integer towards -Infinity
AMED_AARCH32_PAGE_VRINTN_asimd, //!< VRINTN (Advanced SIMD):Vector Round floating-point to integer to Nearest
AMED_AARCH32_PAGE_VRINTN_vfp, //!< VRINTN (floating-point):Round floating-point to integer to Nearest
AMED_AARCH32_PAGE_VRINTP_asimd, //!< VRINTP (Advanced SIMD):Vector Round floating-point to integer towards +Infinity
AMED_AARCH32_PAGE_VRINTP_vfp, //!< VRINTP (floating-point):Round floating-point to integer towards +Infinity
AMED_AARCH32_PAGE_VRINTR_vfp, //!< VRINTR:Round floating-point to integer
AMED_AARCH32_PAGE_VRINTX_asimd, //!< VRINTX (Advanced SIMD):Vector round floating-point to integer inexact
AMED_AARCH32_PAGE_VRINTX_vfp, //!< VRINTX (floating-point):Round floating-point to integer inexact
AMED_AARCH32_PAGE_VRINTZ_asimd, //!< VRINTZ (Advanced SIMD):Vector round floating-point to integer towards Zero
AMED_AARCH32_PAGE_VRINTZ_vfp, //!< VRINTZ (floating-point):Round floating-point to integer towards Zero
AMED_AARCH32_PAGE_VRSHL, //!< VRSHL:Vector Rounding Shift Left
AMED_AARCH32_PAGE_VRSHR, //!< VRSHR:Vector Rounding Shift Right
AMED_AARCH32_PAGE_VRSHRN, //!< VRSHRN:Vector Rounding Shift Right and Narrow
AMED_AARCH32_PAGE_VRSQRTE, //!< VRSQRTE:Vector Reciprocal Square Root Estimate
AMED_AARCH32_PAGE_VRSQRTS, //!< VRSQRTS:Vector Reciprocal Square Root Step
AMED_AARCH32_PAGE_VRSRA, //!< VRSRA:Vector Rounding Shift Right and Accumulate
AMED_AARCH32_PAGE_VRSUBHN, //!< VRSUBHN:Vector Rounding Subtract and Narrow, returning High Half
AMED_AARCH32_PAGE_VSDOT, //!< VSDOT (vector):Dot Product vector form with signed integers.
AMED_AARCH32_PAGE_VSDOT_s, //!< VSDOT (by element):Dot Product index form with signed integers.
AMED_AARCH32_PAGE_VSEL, //!< VSELEQ, VSELGE, VSELGT, VSELVS:Floating-point conditional select
AMED_AARCH32_PAGE_VSHL_i, //!< VSHL (immediate):Vector Shift Left (immediate)
AMED_AARCH32_PAGE_VSHL_r, //!< VSHL (register):Vector Shift Left (register)
AMED_AARCH32_PAGE_VSHLL, //!< VSHLL:Vector Shift Left Long
AMED_AARCH32_PAGE_VSHR, //!< VSHR:Vector Shift Right
AMED_AARCH32_PAGE_VSHRN, //!< VSHRN:Vector Shift Right Narrow
AMED_AARCH32_PAGE_VSLI, //!< VSLI:Vector Shift Left and Insert
AMED_AARCH32_PAGE_VSMMLA, //!< VSMMLA:Widening 8-bit signed integer matrix multiply-accumulate into 2x2 matrix
AMED_AARCH32_PAGE_VSQRT, //!< VSQRT:Square Root
AMED_AARCH32_PAGE_VSRA, //!< VSRA:Vector Shift Right and Accumulate
AMED_AARCH32_PAGE_VSRI, //!< VSRI:Vector Shift Right and Insert
AMED_AARCH32_PAGE_VST1_1, //!< VST1 (single element from one lane):Store single element from one lane of one register
AMED_AARCH32_PAGE_VST1_m, //!< VST1 (multiple single elements):Store multiple single elements from one, two, three, or four registers
AMED_AARCH32_PAGE_VST2_1, //!< VST2 (single 2-element structure from one lane):Store single 2-element structure from one lane of two registers
AMED_AARCH32_PAGE_VST2_m, //!< VST2 (multiple 2-element structures):Store multiple 2-element structures from two or four registers
AMED_AARCH32_PAGE_VST3_1, //!< VST3 (single 3-element structure from one lane):Store single 3-element structure from one lane of three registers
AMED_AARCH32_PAGE_VST3_m, //!< VST3 (multiple 3-element structures):Store multiple 3-element structures from three registers
AMED_AARCH32_PAGE_VST4_1, //!< VST4 (single 4-element structure from one lane):Store single 4-element structure from one lane of four registers
AMED_AARCH32_PAGE_VST4_m, //!< VST4 (multiple 4-element structures):Store multiple 4-element structures from four registers
AMED_AARCH32_PAGE_VSTM, //!< VSTM, VSTMDB, VSTMIA:Store multiple SIMD&FP registers
AMED_AARCH32_PAGE_VSTR, //!< VSTR:Store SIMD&FP register
AMED_AARCH32_PAGE_VSUB_f, //!< VSUB (floating-point):Vector Subtract (floating-point)
AMED_AARCH32_PAGE_VSUB_i, //!< VSUB (integer):Vector Subtract (integer)
AMED_AARCH32_PAGE_VSUBHN, //!< VSUBHN:Vector Subtract and Narrow, returning High Half
AMED_AARCH32_PAGE_VSUBL, //!< VSUBL:Vector Subtract Long
AMED_AARCH32_PAGE_VSUBW, //!< VSUBW:Vector Subtract Wide
AMED_AARCH32_PAGE_VSUDOT_s, //!< VSUDOT (by element):Dot Product index form with signed and unsigned integers (by element)
AMED_AARCH32_PAGE_VSWP, //!< VSWP:Vector Swap
AMED_AARCH32_PAGE_VTBL, //!< VTBL, VTBX:Vector Table Lookup and Extension
AMED_AARCH32_PAGE_VTRN, //!< VTRN:Vector Transpose
AMED_AARCH32_PAGE_VTST, //!< VTST:Vector Test Bits
AMED_AARCH32_PAGE_VUDOT, //!< VUDOT (vector):Dot Product vector form with unsigned integers.
AMED_AARCH32_PAGE_VUDOT_s, //!< VUDOT (by element):Dot Product index form with unsigned integers.