make
make
make
make
to Update Archive Filesmake
make
make
override
Directiveforeach
Functionfile
Functioncall
Functionvalue
Functioneval
Functionorigin
Functionflavor
Functionshell
Functionguile
Functionmake
make
to Update Archive Files
make
make
make
This file documents the GNU make
utility, which determines
automatically which pieces of a large program need to be recompiled,
and issues the commands to recompile them.
This is Edition 0.73, last updated 30 September 2014,
of The GNU Make Manual, for GNU make
version 4.1.
Copyright © 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with the Front-Cover Texts being “A GNU Manual,” and with the Back-Cover Texts as in (a) below. A copy of the license is included in the section entitled “GNU Free Documentation License.”
(a) The FSF’s Back-Cover Text is: “You have the freedom to copy and modify this GNU manual. Buying copies from the FSF supports it in developing GNU and promoting software freedom.”
| • Overview: | Overview of make .
| |
| • Introduction: | An introduction to make .
| |
| • Makefiles: | Makefiles tell make what to do.
| |
| • Rules: | Rules describe when a file must be remade. | |
| • Recipes: | Recipes say how to remake a file. | |
| • Using Variables: | You can use variables to avoid repetition. | |
| • Conditionals: | Use or ignore parts of the makefile based on the values of variables. | |
| • Functions: | Many powerful ways to manipulate text. | |
| • Invoking make: | How to invoke make on the command line.
| |
| • Implicit Rules: | Use implicit rules to treat many files alike, based on their file names. | |
| • Archives: | How make can update library archives.
| |
| • Extending make: | Using extensions to make .
| |
| • Features: | Features GNU make has over other make s.
| |
| • Missing: | What GNU make lacks from other make s.
| |
| • Makefile Conventions: | Conventions for writing makefiles for GNU programs. | |
| • Quick Reference: | A quick reference for experienced users. | |
| • Error Messages: | A list of common errors generated by make .
| |
| • Complex Makefile: | A real example of a straightforward, but nontrivial, makefile. | |
| • GNU Free Documentation License: | License for copying this manual. | |
| • Concept Index: | Index of Concepts. | |
| • Name Index: | Index of Functions, Variables, & Directives. | |
— The Detailed Node Listing —
Overview of | ||
| • Preparing: | Preparing and running make .
| |
| • Reading: | On reading this text. | |
| • Bugs: | Problems and bugs. | |
An Introduction to Makefiles | ||
| • Rule Introduction: | What a rule looks like. | |
| • Simple Makefile: | A simple makefile. | |
| • How Make Works: | How make processes this makefile.
| |
| • Variables Simplify: | Variables make makefiles simpler. | |
| • make Deduces: | Letting make deduce the recipes.
| |
| • Combine By Prerequisite: | Another style of makefile. | |
| • Cleanup: | Rules for cleaning the directory. | |
Writing Makefiles | ||
| • Makefile Contents: | What makefiles contain. | |
| • Makefile Names: | How to name your makefile. | |
| • Include: | How one makefile can use another makefile. | |
| • MAKEFILES Variable: | The environment can specify extra makefiles. | |
| • Remaking Makefiles: | How makefiles get remade. | |
| • Overriding Makefiles: | How to override part of one makefile with another makefile. | |
| • Reading Makefiles: | How makefiles are parsed. | |
| • Secondary Expansion: | How and when secondary expansion is performed. | |
What Makefiles Contain | ||
| • Splitting Lines: | Splitting long lines in makefiles | |
Writing Rules | ||
| • Rule Example: | An example explained. | |
| • Rule Syntax: | General syntax explained. | |
| • Prerequisite Types: | There are two types of prerequisites. | |
| • Wildcards: | Using wildcard characters such as ‘*’. | |
| • Directory Search: | Searching other directories for source files. | |
| • Phony Targets: | Using a target that is not a real file’s name. | |
| • Force Targets: | You can use a target without a recipe or prerequisites to mark other targets as phony. | |
| • Empty Targets: | When only the date matters and the files are empty. | |
| • Special Targets: | Targets with special built-in meanings. | |
| • Multiple Targets: | When to make use of several targets in a rule. | |
| • Multiple Rules: | How to use several rules with the same target. | |
| • Static Pattern: | Static pattern rules apply to multiple targets and can vary the prerequisites according to the target name. | |
| • Double-Colon: | How to use a special kind of rule to allow several independent rules for one target. | |
| • Automatic Prerequisites: | How to automatically generate rules giving prerequisites from source files themselves. | |
Using Wildcard Characters in File Names | ||
| • Wildcard Examples: | Several examples. | |
| • Wildcard Pitfall: | Problems to avoid. | |
| • Wildcard Function: | How to cause wildcard expansion where it does not normally take place. | |
Searching Directories for Prerequisites | ||
| • General Search: | Specifying a search path that applies to every prerequisite. | |
| • Selective Search: | Specifying a search path for a specified class of names. | |
| • Search Algorithm: | When and how search paths are applied. | |
| • Recipes/Search: | How to write recipes that work together with search paths. | |
| • Implicit/Search: | How search paths affect implicit rules. | |
| • Libraries/Search: | Directory search for link libraries. | |
Static Pattern Rules | ||
| • Static Usage: | The syntax of static pattern rules. | |
| • Static versus Implicit: | When are they better than implicit rules? | |
Writing Recipes in Rules | ||
| • Recipe Syntax: | Recipe syntax features and pitfalls. | |
| • Echoing: | How to control when recipes are echoed. | |
| • Execution: | How recipes are executed. | |
| • Parallel: | How recipes can be executed in parallel. | |
| • Errors: | What happens after a recipe execution error. | |
| • Interrupts: | What happens when a recipe is interrupted. | |
| • Recursion: | Invoking make from makefiles.
| |
| • Canned Recipes: | Defining canned recipes. | |
| • Empty Recipes: | Defining useful, do-nothing recipes. | |
Recipe Syntax | ||
| • Splitting Recipe Lines: | Breaking long recipe lines for readability. | |
| • Variables in Recipes: | Using make variables in recipes.
| |
Recipe Execution | ||
| • One Shell: | One shell for all lines in a recipe. | |
| • Choosing the Shell: | How make chooses the shell used
to run recipes.
| |
Parallel Execution | ||
| • Parallel Output: | Handling output during parallel execution | |
| • Parallel Input: | Handling input during parallel execution | |
Recursive Use of | ||
| • MAKE Variable: | The special effects of using ‘$(MAKE)’. | |
| • Variables/Recursion: | How to communicate variables to a sub-make .
| |
| • Options/Recursion: | How to communicate options to a sub-make .
| |
| • -w Option: | How the ‘-w’ or ‘--print-directory’ option
helps debug use of recursive make commands.
| |
How to Use Variables | ||
| • Reference: | How to use the value of a variable. | |
| • Flavors: | Variables come in two flavors. | |
| • Advanced: | Advanced features for referencing a variable. | |
| • Values: | All the ways variables get their values. | |
| • Setting: | How to set a variable in the makefile. | |
| • Appending: | How to append more text to the old value of a variable. | |
| • Override Directive: | How to set a variable in the makefile even if the user has set it with a command argument. | |
| • Multi-Line: | An alternate way to set a variable to a multi-line string. | |
| • Undefine Directive: | How to undefine a variable so that it appears as if it was never set. | |
| • Environment: | Variable values can come from the environment. | |
| • Target-specific: | Variable values can be defined on a per-target basis. | |
| • Pattern-specific: | Target-specific variable values can be applied to a group of targets that match a pattern. | |
| • Suppressing Inheritance: | Suppress inheritance of variables. | |
| • Special Variables: | Variables with special meaning or behavior. | |
Advanced Features for Reference to Variables | ||
| • Substitution Refs: | Referencing a variable with substitutions on the value. | |
| • Computed Names: | Computing the name of the variable to refer to. | |
Conditional Parts of Makefiles | ||
| • Conditional Example: | Example of a conditional | |
| • Conditional Syntax: | The syntax of conditionals. | |
| • Testing Flags: | Conditionals that test flags. | |
Functions for Transforming Text | ||
| • Syntax of Functions: | How to write a function call. | |
| • Text Functions: | General-purpose text manipulation functions. | |
| • File Name Functions: | Functions for manipulating file names. | |
| • Conditional Functions: | Functions that implement conditions. | |
| • Foreach Function: | Repeat some text with controlled variation. | |
| • File Function: | Write text to a file. | |
| • Call Function: | Expand a user-defined function. | |
| • Value Function: | Return the un-expanded value of a variable. | |
| • Eval Function: | Evaluate the arguments as makefile syntax. | |
| • Origin Function: | Find where a variable got its value. | |
| • Flavor Function: | Find out the flavor of a variable. | |
| • Make Control Functions: | Functions that control how make runs. | |
| • Shell Function: | Substitute the output of a shell command. | |
| • Guile Function: | Use GNU Guile embedded scripting language. | |
How to Run | ||
| • Makefile Arguments: | How to specify which makefile to use. | |
| • Goals: | How to use goal arguments to specify which parts of the makefile to use. | |
| • Instead of Execution: | How to use mode flags to specify what kind of thing to do with the recipes in the makefile other than simply execute them. | |
| • Avoiding Compilation: | How to avoid recompiling certain files. | |
| • Overriding: | How to override a variable to specify an alternate compiler and other things. | |
| • Testing: | How to proceed past some errors, to test compilation. | |
| • Options Summary: | Summary of Options | |
Using Implicit Rules | ||
| • Using Implicit: | How to use an existing implicit rule to get the recipes for updating a file. | |
| • Catalogue of Rules: | A list of built-in rules. | |
| • Implicit Variables: | How to change what predefined rules do. | |
| • Chained Rules: | How to use a chain of implicit rules. | |
| • Pattern Rules: | How to define new implicit rules. | |
| • Last Resort: | How to define a recipe for rules which cannot find any. | |
| • Suffix Rules: | The old-fashioned style of implicit rule. | |
| • Implicit Rule Search: | The precise algorithm for applying implicit rules. | |
Defining and Redefining Pattern Rules | ||
| • Pattern Intro: | An introduction to pattern rules. | |
| • Pattern Examples: | Examples of pattern rules. | |
| • Automatic Variables: | How to use automatic variables in the recipe of implicit rules. | |
| • Pattern Match: | How patterns match. | |
| • Match-Anything Rules: | Precautions you should take prior to defining rules that can match any target file whatever. | |
| • Canceling Rules: | How to override or cancel built-in rules. | |
Using | ||
| • Archive Members: | Archive members as targets. | |
| • Archive Update: | The implicit rule for archive member targets. | |
| • Archive Pitfalls: | Dangers to watch out for when using archives. | |
| • Archive Suffix Rules: | You can write a special kind of suffix rule for updating archives. | |
Implicit Rule for Archive Member Targets | ||
| • Archive Symbols: | How to update archive symbol directories. | |
Extending GNU | ||
| • Guile Integration: | Using Guile as an embedded scripting language. | |
| • Loading Objects: | Loading dynamic objects as extensions. | |
GNU Guile Integration | ||
| • Guile Types: | Converting Guile types to make strings.
| |
| • Guile Interface: | Invoking make functions from Guile.
| |
| • Guile Example: | Example using Guile in make .
| |
Loading Dynamic Objects | ||
| • load Directive: | Loading dynamic objects as extensions. | |
| • Remaking Loaded Objects: | How loaded objects get remade. | |
| • Loaded Object API: | Programmatic interface for loaded objects. | |
| • Loaded Object Example: | Example of a loaded object | |
Next: Introduction, Previous: Top, Up: Top [Contents][Index]
make
The make
utility automatically determines which pieces of a large
program need to be recompiled, and issues commands to recompile them.
This manual describes GNU make
, which was implemented by Richard
Stallman and Roland McGrath. Development since Version 3.76 has been
handled by Paul D. Smith.
GNU make
conforms to section 6.2 of IEEE Standard
1003.2-1992 (POSIX.2).
Our examples show C programs, since they are most common, but you can use
make
with any programming language whose compiler can be run with a
shell command. Indeed, make
is not limited to programs. You can
use it to describe any task where some files must be updated automatically
from others whenever the others change.
| • Preparing: | Preparing and running make .
| |
| • Reading: | On reading this text. | |
| • Bugs: | Problems and bugs. |
To prepare to use make
, you must write a file called
the makefile that describes the relationships among files
in your program and provides commands for updating each file.
In a program, typically, the executable file is updated from object
files, which are in turn made by compiling source files.
Once a suitable makefile exists, each time you change some source files, this simple shell command:
make
suffices to perform all necessary recompilations. The make
program
uses the makefile data base and the last-modification times of the files to
decide which of the files need to be updated. For each of those files, it
issues the recipes recorded in the data base.
You can provide command line arguments to make
to control which
files should be recompiled, or how. See How to Run
make
.
If you are new to make
, or are looking for a general
introduction, read the first few sections of each chapter, skipping the
later sections. In each chapter, the first few sections contain
introductory or general information and the later sections contain
specialized or technical information.
The exception is the second chapter, An
Introduction to Makefiles, all of which is introductory.
If you are familiar with other make
programs, see Features of GNU make
, which lists the enhancements GNU
make
has, and Incompatibilities and Missing
Features, which explains the few things GNU make
lacks that
others have.
For a quick summary, see Options Summary, Quick Reference, and Special Targets.
If you have problems with GNU make
or think you’ve found a bug,
please report it to the developers; we cannot promise to do anything but
we might well want to fix it.
Before reporting a bug, make sure you’ve actually found a real bug. Carefully reread the documentation and see if it really says you can do what you’re trying to do. If it’s not clear whether you should be able to do something or not, report that too; it’s a bug in the documentation!
Before reporting a bug or trying to fix it yourself, try to isolate it
to the smallest possible makefile that reproduces the problem. Then
send us the makefile and the exact results make
gave you,
including any error or warning messages. Please don’t paraphrase
these messages: it’s best to cut and paste them into your report.
When generating this small makefile, be sure to not use any non-free
or unusual tools in your recipes: you can almost always emulate what
such a tool would do with simple shell commands. Finally, be sure to
explain what you expected to occur; this will help us decide whether
the problem was really in the documentation.
Once you have a precise problem you can report it in one of two ways. Either send electronic mail to:
<EMAIL_ADDRESS>or use our Web-based project management tool, at:
http://savannah.gnu.org/projects/make/
In addition to the information above, please be careful to include the
version number of make
you are using. You can get this
information with the command ‘make --version’. Be sure also to
include the type of machine and operating system you are using. One
way to obtain this information is by looking at the final lines of
output from the command ‘make --help’.
You need a file called a makefile to tell make
what to do.
Most often, the makefile tells make
how to compile and link a
program.
In this chapter, we will discuss a simple makefile that describes how to
compile and link a text editor which consists of eight C source files
and three header files. The makefile can also tell make
how to
run miscellaneous commands when explicitly asked (for example, to remove
certain files as a clean-up operation). To see a more complex example
of a makefile, see Complex Makefile.
When make
recompiles the editor, each changed C source file
must be recompiled. If a header file has changed, each C source file
that includes the header file must be recompiled to be safe. Each
compilation produces an object file corresponding to the source file.
Finally, if any source file has been recompiled, all the object files,
whether newly made or saved from previous compilations, must be linked
together to produce the new executable editor.
| • Rule Introduction: | What a rule looks like. | |
| • Simple Makefile: | A simple makefile. | |
| • How Make Works: | How make processes this makefile.
| |
| • Variables Simplify: | Variables make makefiles simpler. | |
| • make Deduces: | Letting make deduce the recipes.
| |
| • Combine By Prerequisite: | Another style of makefile. | |
| • Cleanup: | Rules for cleaning the directory. |
Next: Simple Makefile, Previous: Introduction, Up: Introduction [Contents][Index]
A simple makefile consists of “rules” with the following shape:
target … : prerequisites … recipe … …
A target is usually the name of a file that is generated by a program; examples of targets are executable or object files. A target can also be the name of an action to carry out, such as ‘clean’ (see Phony Targets).
A prerequisite is a file that is used as input to create the target. A target often depends on several files.
A recipe is an action that make
carries out. A recipe
may have more than one command, either on the same line or each on its
own line. Please note: you need to put a tab character at
the beginning of every recipe line! This is an obscurity that catches
the unwary. If you prefer to prefix your recipes with a character
other than tab, you can set the .RECIPEPREFIX
variable to an
alternate character (see Special Variables).
Usually a recipe is in a rule with prerequisites and serves to create a target file if any of the prerequisites change. However, the rule that specifies a recipe for the target need not have prerequisites. For example, the rule containing the delete command associated with the target ‘clean’ does not have prerequisites.
A rule, then, explains how and when to remake certain files
which are the targets of the particular rule. make
carries out
the recipe on the prerequisites to create or update the target. A
rule can also explain how and when to carry out an action.
See Writing Rules.
A makefile may contain other text besides rules, but a simple makefile need only contain rules. Rules may look somewhat more complicated than shown in this template, but all fit the pattern more or less.
Next: How Make Works, Previous: Rule Introduction, Up: Introduction [Contents][Index]
Here is a straightforward makefile that describes the way an
executable file called edit
depends on eight object files
which, in turn, depend on eight C source and three header files.
In this example, all the C files include defs.h, but only those defining editing commands include command.h, and only low level files that change the editor buffer include buffer.h.
edit : main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o cc -o edit main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o main.o : main.c defs.h cc -c main.c kbd.o : kbd.c defs.h command.h cc -c kbd.c command.o : command.c defs.h command.h cc -c command.c display.o : display.c defs.h buffer.h cc -c display.c insert.o : insert.c defs.h buffer.h cc -c insert.c search.o : search.c defs.h buffer.h cc -c search.c files.o : files.c defs.h buffer.h command.h cc -c files.c utils.o : utils.c defs.h cc -c utils.c clean : rm edit main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o
We split each long line into two lines using backslash/newline; this is like using one long line, but is easier to read. See Splitting Long Lines.
To use this makefile to create the executable file called edit, type:
make
To use this makefile to delete the executable file and all the object files from the directory, type:
make clean
In the example makefile, the targets include the executable file ‘edit’, and the object files ‘main.o’ and ‘kbd.o’. The prerequisites are files such as ‘main.c’ and ‘defs.h’. In fact, each ‘.o’ file is both a target and a prerequisite. Recipes include ‘cc -c main.c’ and ‘cc -c kbd.c’.
When a target is a file, it needs to be recompiled or relinked if any of its prerequisites change. In addition, any prerequisites that are themselves automatically generated should be updated first. In this example, edit depends on each of the eight object files; the object file main.o depends on the source file main.c and on the header file defs.h.
A recipe may follow each line that contains a target and
prerequisites. These recipes say how to update the target file. A
tab character (or whatever character is specified by the
.RECIPEPREFIX
variable; see Special Variables) must come at
the beginning of every line in the recipe to distinguish recipes from
other lines in the makefile. (Bear in mind that make
does not
know anything about how the recipes work. It is up to you to supply
recipes that will update the target file properly. All make
does is execute the recipe you have specified when the target file
needs to be updated.)
The target ‘clean’ is not a file, but merely the name of an
action. Since you normally do not want to carry out the actions in
this rule, ‘clean’ is not a prerequisite of any other rule.
Consequently, make
never does anything with it unless you tell
it specifically. Note that this rule not only is not a prerequisite,
it also does not have any prerequisites, so the only purpose of the
rule is to run the specified recipe. Targets that do not refer to
files but are just actions are called phony targets.
See Phony Targets, for information about this kind of target.
See Errors in Recipes, to see how to cause make
to ignore errors from rm
or any other command.
Next: Variables Simplify, Previous: Simple Makefile, Up: Introduction [Contents][Index]
make
Processes a MakefileBy default, make
starts with the first target (not targets whose
names start with ‘.’). This is called the default goal.
(Goals are the targets that make
strives ultimately to
update. You can override this behavior using the command line
(see Arguments to Specify the Goals) or with the
.DEFAULT_GOAL
special variable (see Other Special Variables).
In the simple example of the previous section, the default goal is to update the executable program edit; therefore, we put that rule first.
Thus, when you give the command:
make
make
reads the makefile in the current directory and begins by
processing the first rule. In the example, this rule is for relinking
edit; but before make
can fully process this rule, it
must process the rules for the files that edit depends on,
which in this case are the object files. Each of these files is
processed according to its own rule. These rules say to update each
‘.o’ file by compiling its source file. The recompilation must
be done if the source file, or any of the header files named as
prerequisites, is more recent than the object file, or if the object
file does not exist.
The other rules are processed because their targets appear as
prerequisites of the goal. If some other rule is not depended on by the
goal (or anything it depends on, etc.), that rule is not processed,
unless you tell make
to do so (with a command such as
make clean
).
Before recompiling an object file, make
considers updating its
prerequisites, the source file and header files. This makefile does not
specify anything to be done for them—the ‘.c’ and ‘.h’ files
are not the targets of any rules—so make
does nothing for these
files. But make
would update automatically generated C programs,
such as those made by Bison or Yacc, by their own rules at this time.
After recompiling whichever object files need it, make
decides
whether to relink edit. This must be done if the file
edit does not exist, or if any of the object files are newer than
it. If an object file was just recompiled, it is now newer than
edit, so edit is relinked.
Thus, if we change the file insert.c and run make
,
make
will compile that file to update insert.o, and then
link edit. If we change the file command.h and run
make
, make
will recompile the object files kbd.o,
command.o and files.o and then link the file edit.
Next: make Deduces, Previous: How Make Works, Up: Introduction [Contents][Index]
In our example, we had to list all the object files twice in the rule for edit (repeated here):
edit : main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o cc -o edit main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o
Such duplication is error-prone; if a new object file is added to the system, we might add it to one list and forget the other. We can eliminate the risk and simplify the makefile by using a variable. Variables allow a text string to be defined once and substituted in multiple places later (see How to Use Variables).
It is standard practice for every makefile to have a variable named
objects
, OBJECTS
, objs
, OBJS
, obj
,
or OBJ
which is a list of all object file names. We would
define such a variable objects
with a line like this in the
makefile:
objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o
Then, each place we want to put a list of the object file names, we can substitute the variable’s value by writing ‘$(objects)’ (see How to Use Variables).
Here is how the complete simple makefile looks when you use a variable for the object files:
objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o edit : $(objects) cc -o edit $(objects) main.o : main.c defs.h cc -c main.c kbd.o : kbd.c defs.h command.h cc -c kbd.c command.o : command.c defs.h command.h cc -c command.c display.o : display.c defs.h buffer.h cc -c display.c insert.o : insert.c defs.h buffer.h cc -c insert.c search.o : search.c defs.h buffer.h cc -c search.c files.o : files.c defs.h buffer.h command.h cc -c files.c utils.o : utils.c defs.h cc -c utils.c clean : rm edit $(objects)
Next: Combine By Prerequisite, Previous: Variables Simplify, Up: Introduction [Contents][Index]
make
Deduce the RecipesIt is not necessary to spell out the recipes for compiling the individual
C source files, because make
can figure them out: it has an
implicit rule for updating a ‘.o’ file from a correspondingly
named ‘.c’ file using a ‘cc -c’ command. For example, it will
use the recipe ‘cc -c main.c -o main.o’ to compile main.c into
main.o. We can therefore omit the recipes from the rules for the
object files. See Using Implicit Rules.
When a ‘.c’ file is used automatically in this way, it is also automatically added to the list of prerequisites. We can therefore omit the ‘.c’ files from the prerequisites, provided we omit the recipe.
Here is the entire example, with both of these changes, and a variable
objects
as suggested above:
objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o edit : $(objects) cc -o edit $(objects) main.o : defs.h kbd.o : defs.h command.h command.o : defs.h command.h display.o : defs.h buffer.h insert.o : defs.h buffer.h search.o : defs.h buffer.h files.o : defs.h buffer.h command.h utils.o : defs.h .PHONY : clean clean : rm edit $(objects)
This is how we would write the makefile in actual practice. (The complications associated with ‘clean’ are described elsewhere. See Phony Targets, and Errors in Recipes.)
Because implicit rules are so convenient, they are important. You will see them used frequently.
Next: Cleanup, Previous: make Deduces, Up: Introduction [Contents][Index]
When the objects of a makefile are created only by implicit rules, an alternative style of makefile is possible. In this style of makefile, you group entries by their prerequisites instead of by their targets. Here is what one looks like:
objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o edit : $(objects) cc -o edit $(objects) $(objects) : defs.h kbd.o command.o files.o : command.h display.o insert.o search.o files.o : buffer.h
Here defs.h is given as a prerequisite of all the object files; command.h and buffer.h are prerequisites of the specific object files listed for them.
Whether this is better is a matter of taste: it is more compact, but some people dislike it because they find it clearer to put all the information about each target in one place.
Previous: Combine By Prerequisite, Up: Introduction [Contents][Index]
Compiling a program is not the only thing you might want to write rules for. Makefiles commonly tell how to do a few other things besides compiling a program: for example, how to delete all the object files and executables so that the directory is ‘clean’.
Here is how we
could write a make
rule for cleaning our example editor:
clean: rm edit $(objects)
In practice, we might want to write the rule in a somewhat more complicated manner to handle unanticipated situations. We would do this:
.PHONY : clean clean : -rm edit $(objects)
This prevents make
from getting confused by an actual file
called clean and causes it to continue in spite of errors from
rm
. (See Phony Targets, and Errors in
Recipes.)
A rule such as this should not be placed at the beginning of the
makefile, because we do not want it to run by default! Thus, in the
example makefile, we want the rule for edit
, which recompiles
the editor, to remain the default goal.
Since clean
is not a prerequisite of edit
, this rule will not
run at all if we give the command ‘make’ with no arguments. In
order to make the rule run, we have to type ‘make clean’.
See How to Run make
.
Next: Rules, Previous: Introduction, Up: Top [Contents][Index]
The information that tells make
how to recompile a system comes from
reading a data base called the makefile.
| • Makefile Contents: | What makefiles contain. | |
| • Makefile Names: | How to name your makefile. | |
| • Include: | How one makefile can use another makefile. | |
| • MAKEFILES Variable: | The environment can specify extra makefiles. | |
| • Remaking Makefiles: | How makefiles get remade. | |
| • Overriding Makefiles: | How to override part of one makefile with another makefile. | |
| • Reading Makefiles: | How makefiles are parsed. | |
| • Secondary Expansion: | How and when secondary expansion is performed. |
Next: Makefile Names, Previous: Makefiles, Up: Makefiles [Contents][Index]
Makefiles contain five kinds of things: explicit rules, implicit rules, variable definitions, directives, and comments. Rules, variables, and directives are described at length in later chapters.
objects
as a list of all object files (see Variables
Make Makefiles Simpler).
make
to do something
special while reading the makefile. These include:
#
, escape it with a backslash (e.g., \#
). Comments may
appear on any line in the makefile, although they are treated
specially in certain situations.
You cannot use comments within variable references or function calls:
any instance of #
will be treated literally (rather than as the
start of a comment) inside a variable reference or function call.
Comments within a recipe are passed to the shell, just as with any other recipe text. The shell decides how to interpret it: whether or not this is a comment is up to the shell.
Within a define
directive, comments are not ignored during the
definition of the variable, but rather kept intact in the value of the
variable. When the variable is expanded they will either be treated
as make
comments or as recipe text, depending on the context in
which the variable is evaluated.
| • Splitting Lines: | Splitting long lines in makefiles |
Previous: Makefile Contents, Up: Makefile Contents [Contents][Index]
Makefiles use a “line-based” syntax in which the newline character
is special and marks the end of a statement. GNU make
has no
limit on the length of a statement line, up to the amount of memory in
your computer.
However, it is difficult to read lines which are too long to display
without wrapping or scrolling. So, you can format your makefiles for
readability by adding newlines into the middle of a statement: you do
this by escaping the internal newlines with a backslash (\
)
character. Where we need to make a distinction we will refer to
“physical lines” as a single line ending with a newline (regardless
of whether it is escaped) and a “logical line” being a complete
statement including all escaped newlines up to the first non-escaped
newline.
The way in which backslash/newline combinations are handled depends on whether the statement is a recipe line or a non-recipe line. Handling of backslash/newline in a recipe line is discussed later (see Splitting Recipe Lines).
Outside of recipe lines, backslash/newlines are converted into a single space character. Once that is done, all whitespace around the backslash/newline is condensed into a single space: this includes all whitespace preceding the backslash, all whitespace at the beginning of the line after the backslash/newline, and any consecutive backslash/newline combinations.
If the .POSIX
special target is defined then backslash/newline
handling is modified slightly to conform to POSIX.2: first, whitespace
preceding a backslash is not removed and second, consecutive
backslash/newlines are not condensed.
Next: Include, Previous: Makefile Contents, Up: Makefiles [Contents][Index]
By default, when make
looks for the makefile, it tries the
following names, in order: GNUmakefile, makefile
and Makefile.
Normally you should call your makefile either makefile or
Makefile. (We recommend Makefile because it appears
prominently near the beginning of a directory listing, right near other
important files such as README.) The first name checked,
GNUmakefile, is not recommended for most makefiles. You should
use this name if you have a makefile that is specific to GNU
make
, and will not be understood by other versions of
make
. Other make
programs look for makefile and
Makefile, but not GNUmakefile.
If make
finds none of these names, it does not use any makefile.
Then you must specify a goal with a command argument, and make
will attempt to figure out how to remake it using only its built-in
implicit rules. See Using Implicit Rules.
If you want to use a nonstandard name for your makefile, you can specify
the makefile name with the ‘-f’ or ‘--file’ option. The
arguments ‘-f name’ or ‘--file=name’ tell
make
to read the file name as the makefile. If you use
more than one ‘-f’ or ‘--file’ option, you can specify several
makefiles. All the makefiles are effectively concatenated in the order
specified. The default makefile names GNUmakefile,
makefile and Makefile are not checked automatically if you
specify ‘-f’ or ‘--file’.
Next: MAKEFILES Variable, Previous: Makefile Names, Up: Makefiles [Contents][Index]
The include
directive tells make
to suspend reading the
current makefile and read one or more other makefiles before continuing.
The directive is a line in the makefile that looks like this:
include filenames…
filenames can contain shell file name patterns. If filenames is empty, nothing is included and no error is printed.
Extra spaces are allowed and ignored at the beginning of the line, but
the first character must not be a tab (or the value of
.RECIPEPREFIX
)—if the line begins with a tab, it will be
considered a recipe line. Whitespace is required between
include
and the file names, and between file names; extra
whitespace is ignored there and at the end of the directive. A
comment starting with ‘#’ is allowed at the end of the line. If
the file names contain any variable or function references, they are
expanded. See How to Use Variables.
For example, if you have three .mk files, a.mk,
b.mk, and c.mk, and $(bar)
expands to
bish bash
, then the following expression
include foo *.mk $(bar)
is equivalent to
include foo a.mk b.mk c.mk bish bash
When make
processes an include
directive, it suspends
reading of the containing makefile and reads from each listed file in
turn. When that is finished, make
resumes reading the
makefile in which the directive appears.
One occasion for using include
directives is when several programs,
handled by individual makefiles in various directories, need to use a
common set of variable definitions
(see Setting Variables) or pattern rules
(see Defining and Redefining Pattern Rules).
Another such occasion is when you want to generate prerequisites from
source files automatically; the prerequisites can be put in a file that
is included by the main makefile. This practice is generally cleaner
than that of somehow appending the prerequisites to the end of the main
makefile as has been traditionally done with other versions of
make
. See Automatic Prerequisites.
If the specified name does not start with a slash, and the file is not found in the current directory, several other directories are searched. First, any directories you have specified with the ‘-I’ or ‘--include-dir’ option are searched (see Summary of Options). Then the following directories (if they exist) are searched, in this order: prefix/include (normally /usr/local/include 1) /usr/gnu/include, /usr/local/include, /usr/include.
If an included makefile cannot be found in any of these directories, a
warning message is generated, but it is not an immediately fatal error;
processing of the makefile containing the include
continues.
Once it has finished reading makefiles, make
will try to remake
any that are out of date or don’t exist.
See How Makefiles Are Remade.
Only after it has tried to find a way to remake a makefile and failed,
will make
diagnose the missing makefile as a fatal error.
If you want make
to simply ignore a makefile which does not exist
or cannot be remade, with no error message, use the -include
directive instead of include
, like this:
-include filenames…
This acts like include
in every way except that there is no
error (not even a warning) if any of the filenames (or any
prerequisites of any of the filenames) do not exist or cannot be
remade.
For compatibility with some other make
implementations,
sinclude
is another name for -include
.
Next: Remaking Makefiles, Previous: Include, Up: Makefiles [Contents][Index]
MAKEFILES
If the environment variable MAKEFILES
is defined, make
considers its value as a list of names (separated by whitespace) of
additional makefiles to be read before the others. This works much
like the include
directive: various directories are searched
for those files (see Including Other Makefiles). In
addition, the default goal is never taken from one of these makefiles
(or any makefile included by them) and it is not an error if the files
listed in MAKEFILES
are not found.
The main use of MAKEFILES
is in communication between recursive
invocations of make
(see Recursive Use of
make
). It usually is not desirable to set the environment
variable before a top-level invocation of make
, because it is
usually better not to mess with a makefile from outside. However, if
you are running make
without a specific makefile, a makefile in
MAKEFILES
can do useful things to help the built-in implicit
rules work better, such as defining search paths (see Directory Search).
Some users are tempted to set MAKEFILES
in the environment
automatically on login, and program makefiles to expect this to be done.
This is a very bad idea, because such makefiles will fail to work if run by
anyone else. It is much better to write explicit include
directives
in the makefiles. See Including Other Makefiles.
Next: Overriding Makefiles, Previous: MAKEFILES Variable, Up: Makefiles [Contents][Index]
Sometimes makefiles can be remade from other files, such as RCS or SCCS
files. If a makefile can be remade from other files, you probably want
make
to get an up-to-date version of the makefile to read in.
To this end, after reading in all makefiles, make
will consider
each as a goal target and attempt to update it. If a makefile has a
rule which says how to update it (found either in that very makefile or
in another one) or if an implicit rule applies to it (see Using Implicit Rules), it will be updated if necessary. After
all makefiles have been checked, if any have actually been changed,
make
starts with a clean slate and reads all the makefiles over
again. (It will also attempt to update each of them over again, but
normally this will not change them again, since they are already up to
date.)
If you know that one or more of your makefiles cannot be remade and
you want to keep make
from performing an implicit rule search
on them, perhaps for efficiency reasons, you can use any normal method
of preventing implicit rule look-up to do so. For example, you can
write an explicit rule with the makefile as the target, and an empty
recipe (see Using Empty Recipes).
If the makefiles specify a double-colon rule to remake a file with
a recipe but no prerequisites, that file will always be remade
(see Double-Colon). In the case of makefiles, a makefile that has a
double-colon rule with a recipe but no prerequisites will be remade every
time make
is run, and then again after make
starts over
and reads the makefiles in again. This would cause an infinite loop:
make
would constantly remake the makefile, and never do anything
else. So, to avoid this, make
will not attempt to
remake makefiles which are specified as targets of a double-colon rule
with a recipe but no prerequisites.
If you do not specify any makefiles to be read with ‘-f’ or
‘--file’ options, make
will try the default makefile names;
see What Name to Give Your Makefile. Unlike
makefiles explicitly requested with ‘-f’ or ‘--file’ options,
make
is not certain that these makefiles should exist. However,
if a default makefile does not exist but can be created by running
make
rules, you probably want the rules to be run so that the
makefile can be used.
Therefore, if none of the default makefiles exists, make
will try
to make each of them in the same order in which they are searched for
(see What Name to Give Your Makefile)
until it succeeds in making one, or it runs out of names to try. Note
that it is not an error if make
cannot find or make any makefile;
a makefile is not always necessary.
When you use the ‘-t’ or ‘--touch’ option (see Instead of Executing Recipes), you would not want to use an out-of-date makefile to decide which targets to touch. So the ‘-t’ option has no effect on updating makefiles; they are really updated even if ‘-t’ is specified. Likewise, ‘-q’ (or ‘--question’) and ‘-n’ (or ‘--just-print’) do not prevent updating of makefiles, because an out-of-date makefile would result in the wrong output for other targets. Thus, ‘make -f mfile -n foo’ will update mfile, read it in, and then print the recipe to update foo and its prerequisites without running it. The recipe printed for foo will be the one specified in the updated contents of mfile.
However, on occasion you might actually wish to prevent updating of even the makefiles. You can do this by specifying the makefiles as goals in the command line as well as specifying them as makefiles. When the makefile name is specified explicitly as a goal, the options ‘-t’ and so on do apply to them.
Thus, ‘make -f mfile -n mfile foo’ would read the makefile mfile, print the recipe needed to update it without actually running it, and then print the recipe needed to update foo without running that. The recipe for foo will be the one specified by the existing contents of mfile.
Next: Reading Makefiles, Previous: Remaking Makefiles, Up: Makefiles [Contents][Index]
Sometimes it is useful to have a makefile that is mostly just like another makefile. You can often use the ‘include’ directive to include one in the other, and add more targets or variable definitions. However, it is invalid for two makefiles to give different recipes for the same target. But there is another way.
In the containing makefile (the one that wants to include the other),
you can use a match-anything pattern rule to say that to remake any
target that cannot be made from the information in the containing
makefile, make
should look in another makefile.
See Pattern Rules, for more information on pattern rules.
For example, if you have a makefile called Makefile that says how to make the target ‘foo’ (and other targets), you can write a makefile called GNUmakefile that contains:
foo: frobnicate > foo %: force @$(MAKE) -f Makefile $@ force: ;
If you say ‘make foo’, make
will find GNUmakefile,
read it, and see that to make foo, it needs to run the recipe
‘frobnicate > foo’. If you say ‘make bar’, make
will
find no way to make bar in GNUmakefile, so it will use the
recipe from the pattern rule: ‘make -f Makefile bar’. If
Makefile provides a rule for updating bar, make
will apply the rule. And likewise for any other target that
GNUmakefile does not say how to make.
The way this works is that the pattern rule has a pattern of just
‘%’, so it matches any target whatever. The rule specifies a
prerequisite force, to guarantee that the recipe will be run even
if the target file already exists. We give the force target an
empty recipe to prevent make
from searching for an implicit rule to
build it—otherwise it would apply the same match-anything rule to
force itself and create a prerequisite loop!
Next: Secondary Expansion, Previous: Overriding Makefiles, Up: Makefiles [Contents][Index]
make
Reads a MakefileGNU make
does its work in two distinct phases. During the first
phase it reads all the makefiles, included makefiles, etc. and
internalizes all the variables and their values, implicit and explicit
rules, and constructs a dependency graph of all the targets and their
prerequisites. During the second phase, make
uses these internal
structures to determine what targets will need to be rebuilt and to
invoke the rules necessary to do so.
It’s important to understand this two-phase approach because it has a
direct impact on how variable and function expansion happens; this is
often a source of some confusion when writing makefiles. Here we will
present a summary of the phases in which expansion happens for different
constructs within the makefile. We say that expansion is
immediate if it happens during the first phase: in this case
make
will expand any variables or functions in that section of a
construct as the makefile is parsed. We say that expansion is
deferred if expansion is not performed immediately. Expansion of
a deferred construct is not performed until either the construct appears
later in an immediate context, or until the second phase.
You may not be familiar with some of these constructs yet. You can reference this section as you become familiar with them, in later chapters.

For the shell assignment operator, ‘!=’, the right-hand side is evaluated immediately and handed to the shell. The result is stored in the variable named on the left, and that variable becomes a simple variable (and will thus be re-evaluated on each reference).
Conditional directives are parsed immediately. This means, for example, that automatic variables cannot be used in conditional directives, as automatic variables are not set until the recipe for that rule is invoked. If you need to use automatic variables in a conditional directive you must move the condition into the recipe and use shell conditional syntax instead.
A rule is always expanded the same way, regardless of the form:
immediate : immediate ; deferred deferred
That is, the target and prerequisite sections are expanded immediately, and the recipe used to construct the target is always deferred.
Previous: Reading Makefiles, Up: Makefiles [Contents][Index]
In the previous section we learned that GNU make
works in two
distinct phases: a read-in phase and a target-update phase
(see How make
Reads a Makefile). GNU
make also has the ability to enable a second expansion of the
prerequisites (only) for some or all targets defined in the makefile.
In order for this second expansion to occur, the special target
.SECONDEXPANSION
must be defined before the first prerequisite
list that makes use of this feature.
If that special target is defined then in between the two phases mentioned above, right at the end of the read-in phase, all the prerequisites of the targets defined after the special target are expanded a second time. In most circumstances this secondary expansion will have no effect, since all variable and function references will have been expanded during the initial parsing of the makefiles. In order to take advantage of the secondary expansion phase of the parser, then, it’s necessary to escape the variable or function reference in the makefile. In this case the first expansion merely un-escapes the reference but doesn’t expand it, and expansion is left to the secondary expansion phase. For example, consider this makefile:
.SECONDEXPANSION: ONEVAR = onefile TWOVAR = twofile myfile: $(ONEVAR) $$(TWOVAR)
After the first expansion phase the prerequisites list of the
myfile target will be onefile
and $(TWOVAR)
; the
first (unescaped) variable reference to ONEVAR is expanded,
while the second (escaped) variable reference is simply unescaped,
without being recognized as a variable reference. Now during the
secondary expansion the first word is expanded again but since it
contains no variable or function references it remains the value
onefile, while the second word is now a normal reference to the
variable TWOVAR, which is expanded to the value twofile.
The final result is that there are two prerequisites, onefile
and twofile.
Obviously, this is not a very interesting case since the same result could more easily have been achieved simply by having both variables appear, unescaped, in the prerequisites list. One difference becomes apparent if the variables are reset; consider this example:
.SECONDEXPANSION: AVAR = top onefile: $(AVAR) twofile: $$(AVAR) AVAR = bottom
Here the prerequisite of onefile will be expanded immediately, and resolve to the value top, while the prerequisite of twofile will not be full expanded until the secondary expansion and yield a value of bottom.
This is marginally more exciting, but the true power of this feature
only becomes apparent when you discover that secondary expansions
always take place within the scope of the automatic variables for that
target. This means that you can use variables such as $@
,
$*
, etc. during the second expansion and they will have their
expected values, just as in the recipe. All you have to do is defer
the expansion by escaping the $
. Also, secondary expansion
occurs for both explicit and implicit (pattern) rules. Knowing this,
the possible uses for this feature increase dramatically. For
example:
.SECONDEXPANSION: main_OBJS := main.o try.o test.o lib_OBJS := lib.o api.o main lib: $$($$@_OBJS)
Here, after the initial expansion the prerequisites of both the
main and lib targets will be $($@_OBJS)
. During
the secondary expansion, the $@
variable is set to the name of
the target and so the expansion for the main target will yield
$(main_OBJS)
, or main.o try.o test.o
, while the
secondary expansion for the lib target will yield
$(lib_OBJS)
, or lib.o api.o
.
You can also mix in functions here, as long as they are properly escaped:
main_SRCS := main.c try.c test.c lib_SRCS := lib.c api.c .SECONDEXPANSION: main lib: $$(patsubst %.c,%.o,$$($$@_SRCS))
This version allows users to specify source files rather than object files, but gives the same resulting prerequisites list as the previous example.
Evaluation of automatic variables during the secondary expansion
phase, especially of the target name variable $$@
, behaves
similarly to evaluation within recipes. However, there are some
subtle differences and “corner cases” which come into play for the
different types of rule definitions that make
understands. The
subtleties of using the different automatic variables are described
below.
During the secondary expansion of explicit rules, $$@
and
$$%
evaluate, respectively, to the file name of the target and,
when the target is an archive member, the target member name. The
$$<
variable evaluates to the first prerequisite in the first
rule for this target. $$^
and $$+
evaluate to the list
of all prerequisites of rules that have already appeared for
the same target ($$+
with repetitions and $$^
without). The following example will help illustrate these behaviors:
.SECONDEXPANSION: foo: foo.1 bar.1 $$< $$^ $$+ # line #1 foo: foo.2 bar.2 $$< $$^ $$+ # line #2 foo: foo.3 bar.3 $$< $$^ $$+ # line #3
In the first prerequisite list, all three variables ($$<
,
$$^
, and $$+
) expand to the empty string. In the
second, they will have values foo.1
, foo.1 bar.1
, and
foo.1 bar.1
respectively. In the third they will have values
foo.1
, foo.1 bar.1 foo.2 bar.2
, and foo.1 bar.1
foo.2 bar.2 foo.1 foo.1 bar.1 foo.1 bar.1
respectively.
Rules undergo secondary expansion in makefile order, except that the rule with the recipe is always evaluated last.
The variables $$?
and $$*
are not available and expand
to the empty string.
Rules for secondary expansion of static pattern rules are identical to
those for explicit rules, above, with one exception: for static
pattern rules the $$*
variable is set to the pattern stem. As
with explicit rules, $$?
is not available and expands to the
empty string.
As make
searches for an implicit rule, it substitutes the stem
and then performs secondary expansion for every rule with a matching
target pattern. The value of the automatic variables is derived in
the same fashion as for static pattern rules. As an example:
.SECONDEXPANSION: foo: bar foo foz: fo%: bo% %oo: $$< $$^ $$+ $$*
When the implicit rule is tried for target foo, $$<
expands to bar, $$^
expands to bar boo,
$$+
also expands to bar boo, and $$*
expands to
f.
Note that the directory prefix (D), as described in Implicit Rule Search Algorithm, is appended (after expansion) to all the patterns in the prerequisites list. As an example:
.SECONDEXPANSION: /tmp/foo.o: %.o: $$(addsuffix /%.c,foo bar) foo.h @echo $^
The prerequisite list printed, after the secondary expansion and
directory prefix reconstruction, will be /tmp/foo/foo.c
/tmp/bar/foo.c foo.h. If you are not interested in this
reconstruction, you can use $$*
instead of %
in the
prerequisites list.
A rule appears in the makefile and says when and how to remake certain files, called the rule’s targets (most often only one per rule). It lists the other files that are the prerequisites of the target, and the recipe to use to create or update the target.
The order of rules is not significant, except for determining the
default goal: the target for make
to consider, if you do
not otherwise specify one. The default goal is the target of the first
rule in the first makefile. If the first rule has multiple targets,
only the first target is taken as the default. There are two
exceptions: a target starting with a period is not a default unless it
contains one or more slashes, ‘/’, as well; and, a target that
defines a pattern rule has no effect on the default goal.
(See Defining and Redefining Pattern Rules.)
Therefore, we usually write the makefile so that the first rule is the one for compiling the entire program or all the programs described by the makefile (often with a target called ‘all’). See Arguments to Specify the Goals.
| • Rule Example: | An example explained. | |
| • Rule Syntax: | General syntax explained. | |
| • Prerequisite Types: | There are two types of prerequisites. | |
| • Wildcards: | Using wildcard characters such as ‘*’. | |
| • Directory Search: | Searching other directories for source files. | |
| • Phony Targets: | Using a target that is not a real file’s name. | |
| • Force Targets: | You can use a target without a recipe or prerequisites to mark other targets as phony. | |
| • Empty Targets: | When only the date matters and the files are empty. | |
| • Special Targets: | Targets with special built-in meanings. | |
| • Multiple Targets: | When to make use of several targets in a rule. | |
| • Multiple Rules: | How to use several rules with the same target. | |
| • Static Pattern: | Static pattern rules apply to multiple targets and can vary the prerequisites according to the target name. | |
| • Double-Colon: | How to use a special kind of rule to allow several independent rules for one target. | |
| • Automatic Prerequisites: | How to automatically generate rules giving prerequisites from source files themselves. |
Next: Rule Syntax, Previous: Rules, Up: Rules [Contents][Index]
Here is an example of a rule:
foo.o : foo.c defs.h # module for twiddling the frobs cc -c -g foo.c
Its target is foo.o and its prerequisites are foo.c and defs.h. It has one command in the recipe: ‘cc -c -g foo.c’. The recipe starts with a tab to identify it as a recipe.
This rule says two things:
cc
as stated.
The recipe does not explicitly mention defs.h, but we presume
that foo.c includes it, and that that is why defs.h was
added to the prerequisites.
Next: Prerequisite Types, Previous: Rule Example, Up: Rules [Contents][Index]
In general, a rule looks like this:
targets : prerequisites recipe …
or like this:
targets : prerequisites ; recipe recipe …
The targets are file names, separated by spaces. Wildcard characters may be used (see Using Wildcard Characters in File Names) and a name of the form a(m) represents member m in archive file a (see Archive Members as Targets). Usually there is only one target per rule, but occasionally there is a reason to have more (see Multiple Targets in a Rule).
The recipe lines start with a tab character (or the first
character in the value of the .RECIPEPREFIX
variable;
see Special Variables). The first recipe line may appear on the line
after the prerequisites, with a tab character, or may appear on the
same line, with a semicolon. Either way, the effect is the same.
There are other differences in the syntax of recipes.
See Writing Recipes in Rules.
Because dollar signs are used to start make
variable
references, if you really want a dollar sign in a target or
prerequisite you must write two of them, ‘$$’ (see How to Use Variables). If you have enabled secondary
expansion (see Secondary Expansion) and you want a literal dollar
sign in the prerequisites list, you must actually write four
dollar signs (‘$$$$’).
You may split a long line by inserting a backslash followed by a
newline, but this is not required, as make
places no limit on
the length of a line in a makefile.
A rule tells make
two things: when the targets are out of date,
and how to update them when necessary.
The criterion for being out of date is specified in terms of the prerequisites, which consist of file names separated by spaces. (Wildcards and archive members (see Archives) are allowed here too.) A target is out of date if it does not exist or if it is older than any of the prerequisites (by comparison of last-modification times). The idea is that the contents of the target file are computed based on information in the prerequisites, so if any of the prerequisites changes, the contents of the existing target file are no longer necessarily valid.
How to update is specified by a recipe. This is one or more lines to be executed by the shell (normally ‘sh’), but with some extra features (see Writing Recipes in Rules).
Next: Wildcards, Previous: Rule Syntax, Up: Rules [Contents][Index]
There are actually two different types of prerequisites understood by
GNU make
: normal prerequisites such as described in the
previous section, and order-only prerequisites. A normal
prerequisite makes two statements: first, it imposes an order in which
recipes will be invoked: the recipes for all prerequisites of a target
will be completed before the recipe for the target is run. Second, it
imposes a dependency relationship: if any prerequisite is newer than
the target, then the target is considered out-of-date and must be
rebuilt.
Normally, this is exactly what you want: if a target’s prerequisite is updated, then the target should also be updated.
Occasionally, however, you have a situation where you want to impose a
specific ordering on the rules to be invoked without forcing
the target to be updated if one of those rules is executed. In that
case, you want to define order-only prerequisites. Order-only
prerequisites can be specified by placing a pipe symbol (|
)
in the prerequisites list: any prerequisites to the left of the pipe
symbol are normal; any prerequisites to the right are order-only:
targets : normal-prerequisites | order-only-prerequisites
The normal prerequisites section may of course be empty. Also, you may still declare multiple lines of prerequisites for the same target: they are appended appropriately (normal prerequisites are appended to the list of normal prerequisites; order-only prerequisites are appended to the list of order-only prerequisites). Note that if you declare the same file to be both a normal and an order-only prerequisite, the normal prerequisite takes precedence (since they have a strict superset of the behavior of an order-only prerequisite).
Consider an example where your targets are to be placed in a separate
directory, and that directory might not exist before make
is
run. In this situation, you want the directory to be created before
any targets are placed into it but, because the timestamps on
directories change whenever a file is added, removed, or renamed, we
certainly don’t want to rebuild all the targets whenever the
directory’s timestamp changes. One way to manage this is with
order-only prerequisites: make the directory an order-only
prerequisite on all the targets:
OBJDIR := objdir OBJS := $(addprefix $(OBJDIR)/,foo.o bar.o baz.o) $(OBJDIR)/%.o : %.c $(COMPILE.c) $(OUTPUT_OPTION) $< all: $(OBJS) $(OBJS): | $(OBJDIR) $(OBJDIR): mkdir $(OBJDIR)
Now the rule to create the objdir directory will be run, if needed, before any ‘.o’ is built, but no ‘.o’ will be built because the objdir directory timestamp changed.
Next: Directory Search, Previous: Prerequisite Types, Up: Rules [Contents][Index]
A single file name can specify many files using wildcard characters.
The wildcard characters in make
are ‘*’, ‘?’ and
‘[…]’, the same as in the Bourne shell. For example, *.c
specifies a list of all the files (in the working directory) whose names
end in ‘.c’.
The character ‘~’ at the beginning of a file name also has special significance. If alone, or followed by a slash, it represents your home directory. For example ~/bin expands to /home/you/bin. If the ‘~’ is followed by a word, the string represents the home directory of the user named by that word. For example ~john/bin expands to /home/john/bin. On systems which don’t have a home directory for each user (such as MS-DOS or MS-Windows), this functionality can be simulated by setting the environment variable HOME.
Wildcard expansion is performed by make
automatically in
targets and in prerequisites. In recipes, the shell is responsible
for wildcard expansion. In other contexts, wildcard expansion happens
only if you request it explicitly with the wildcard
function.
The special significance of a wildcard character can be turned off by preceding it with a backslash. Thus, foo\*bar would refer to a specific file whose name consists of ‘foo’, an asterisk, and ‘bar’.
| • Wildcard Examples: | Several examples. | |
| • Wildcard Pitfall: | Problems to avoid. | |
| • Wildcard Function: | How to cause wildcard expansion where it does not normally take place. |
Next: Wildcard Pitfall, Previous: Wildcards, Up: Wildcards [Contents][Index]
Wildcards can be used in the recipe of a rule, where they are expanded by the shell. For example, here is a rule to delete all the object files:
clean: rm -f *.o
Wildcards are also useful in the prerequisites of a rule. With the following rule in the makefile, ‘make print’ will print all the ‘.c’ files that have changed since the last time you printed them:
print: *.c lpr -p $? touch print
This rule uses print as an empty target file; see Empty Target Files to Record Events. (The automatic variable ‘$?’ is used to print only those files that have changed; see Automatic Variables.)
Wildcard expansion does not happen when you define a variable. Thus, if you write this:
objects = *.o
then the value of the variable objects
is the actual string
‘*.o’. However, if you use the value of objects
in a
target or prerequisite, wildcard expansion will take place there. If
you use the value of objects
in a recipe, the shell may perform
wildcard expansion when the recipe runs. To set objects
to the
expansion, instead use:
objects := $(wildcard *.o)
See Wildcard Function.
Next: Wildcard Function, Previous: Wildcard Examples, Up: Wildcards [Contents][Index]
Now here is an example of a naive way of using wildcard expansion, that does not do what you would intend. Suppose you would like to say that the executable file foo is made from all the object files in the directory, and you write this:
objects = *.o foo : $(objects) cc -o foo $(CFLAGS) $(objects)
The value of objects
is the actual string ‘*.o’. Wildcard
expansion happens in the rule for foo, so that each existing
‘.o’ file becomes a prerequisite of foo and will be recompiled if
necessary.
But what if you delete all the ‘.o’ files? When a wildcard matches
no files, it is left as it is, so then foo will depend on the
oddly-named file *.o. Since no such file is likely to exist,
make
will give you an error saying it cannot figure out how to
make *.o. This is not what you want!
Actually it is possible to obtain the desired result with wildcard
expansion, but you need more sophisticated techniques, including the
wildcard
function and string substitution.
See The Function wildcard
.
Microsoft operating systems (MS-DOS and MS-Windows) use backslashes to separate directories in pathnames, like so:
c:\foo\bar\baz.c
This is equivalent to the Unix-style c:/foo/bar/baz.c (the
c: part is the so-called drive letter). When make
runs on
these systems, it supports backslashes as well as the Unix-style forward
slashes in pathnames. However, this support does not include the
wildcard expansion, where backslash is a quote character. Therefore,
you must use Unix-style slashes in these cases.
Previous: Wildcard Pitfall, Up: Wildcards [Contents][Index]
wildcard
Wildcard expansion happens automatically in rules. But wildcard expansion
does not normally take place when a variable is set, or inside the
arguments of a function. If you want to do wildcard expansion in such
places, you need to use the wildcard
function, like this:
$(wildcard pattern…)
This string, used anywhere in a makefile, is replaced by a
space-separated list of names of existing files that match one of the
given file name patterns. If no existing file name matches a pattern,
then that pattern is omitted from the output of the wildcard
function. Note that this is different from how unmatched wildcards
behave in rules, where they are used verbatim rather than ignored
(see Wildcard Pitfall).
One use of the wildcard
function is to get a list of all the C source
files in a directory, like this:
$(wildcard *.c)
We can change the list of C source files into a list of object files by replacing the ‘.c’ suffix with ‘.o’ in the result, like this:
$(patsubst %.c,%.o,$(wildcard *.c))
(Here we have used another function, patsubst
.
See Functions for String Substitution and Analysis.)
Thus, a makefile to compile all C source files in the directory and then link them together could be written as follows:
objects := $(patsubst %.c,%.o,$(wildcard *.c)) foo : $(objects) cc -o foo $(objects)
(This takes advantage of the implicit rule for compiling C programs, so there is no need to write explicit rules for compiling the files. See The Two Flavors of Variables, for an explanation of ‘:=’, which is a variant of ‘=’.)
Next: Phony Targets, Previous: Wildcards, Up: Rules [Contents][Index]
For large systems, it is often desirable to put sources in a separate
directory from the binaries. The directory search features of
make
facilitate this by searching several directories
automatically to find a prerequisite. When you redistribute the files
among directories, you do not need to change the individual rules,
just the search paths.
| • General Search: | Specifying a search path that applies to every prerequisite. | |
| • Selective Search: | Specifying a search path for a specified class of names. | |
| • Search Algorithm: | When and how search paths are applied. | |
| • Recipes/Search: | How to write recipes that work together with search paths. | |
| • Implicit/Search: | How search paths affect implicit rules. | |
| • Libraries/Search: | Directory search for link libraries. |
Next: Selective Search, Previous: Directory Search, Up: Directory Search [Contents][Index]
VPATH
: Search Path for All PrerequisitesThe value of the make
variable VPATH
specifies a list of
directories that make
should search. Most often, the
directories are expected to contain prerequisite files that are not in the
current directory; however, make
uses VPATH
as a search
list for both prerequisites and targets of rules.
Thus, if a file that is listed as a target or prerequisite does not exist
in the current directory, make
searches the directories listed in
VPATH
for a file with that name. If a file is found in one of
them, that file may become the prerequisite (see below). Rules may then
specify the names of files in the prerequisite list as if they all
existed in the current directory. See Writing Recipes with Directory Search.
In the VPATH
variable, directory names are separated by colons or
blanks. The order in which directories are listed is the order followed
by make
in its search. (On MS-DOS and MS-Windows, semi-colons
are used as separators of directory names in VPATH
, since the
colon can be used in the pathname itself, after the drive letter.)
For example,
VPATH = src:../headers
specifies a path containing two directories, src and
../headers, which make
searches in that order.
With this value of VPATH
, the following rule,
foo.o : foo.c
is interpreted as if it were written like this:
foo.o : src/foo.c
assuming the file foo.c does not exist in the current directory but is found in the directory src.
Next: Search Algorithm, Previous: General Search, Up: Directory Search [Contents][Index]
vpath
DirectiveSimilar to the VPATH
variable, but more selective, is the
vpath
directive (note lower case), which allows you to specify a
search path for a particular class of file names: those that match a
particular pattern. Thus you can supply certain search directories for
one class of file names and other directories (or none) for other file
names.
There are three forms of the vpath
directive:
vpath pattern directories
Specify the search path directories for file names that match pattern.
The search path, directories, is a list of directories to be
searched, separated by colons (semi-colons on MS-DOS and MS-Windows) or
blanks, just like the search path used in the VPATH
variable.
vpath pattern
Clear out the search path associated with pattern.
vpath
Clear all search paths previously specified with vpath
directives.
A vpath
pattern is a string containing a ‘%’ character. The
string must match the file name of a prerequisite that is being searched
for, the ‘%’ character matching any sequence of zero or more
characters (as in pattern rules; see Defining and
Redefining Pattern Rules). For example, %.h
matches files that
end in .h
. (If there is no ‘%’, the pattern must match the
prerequisite exactly, which is not useful very often.)
‘%’ characters in a vpath
directive’s pattern can be quoted
with preceding backslashes (‘\’). Backslashes that would otherwise
quote ‘%’ characters can be quoted with more backslashes.
Backslashes that quote ‘%’ characters or other backslashes are
removed from the pattern before it is compared to file names. Backslashes
that are not in danger of quoting ‘%’ characters go unmolested.
When a prerequisite fails to exist in the current directory, if the
pattern in a vpath
directive matches the name of the
prerequisite file, then the directories in that directive are searched
just like (and before) the directories in the VPATH
variable.
For example,
vpath %.h ../headers
tells make
to look for any prerequisite whose name ends in .h
in the directory ../headers if the file is not found in the current
directory.
If several vpath
patterns match the prerequisite file’s name, then
make
processes each matching vpath
directive one by one,
searching all the directories mentioned in each directive. make
handles multiple vpath
directives in the order in which they
appear in the makefile; multiple directives with the same pattern are
independent of each other.
Thus,
vpath %.c foo vpath % blish vpath %.c bar
will look for a file ending in ‘.c’ in foo, then blish, then bar, while
vpath %.c foo:bar vpath % blish
will look for a file ending in ‘.c’ in foo, then bar, then blish.
Next: Recipes/Search, Previous: Selective Search, Up: Directory Search [Contents][Index]
When a prerequisite is found through directory search, regardless of type
(general or selective), the pathname located may not be the one that
make
actually provides you in the prerequisite list. Sometimes
the path discovered through directory search is thrown away.
The algorithm make
uses to decide whether to keep or abandon a
path found via directory search is as follows:
make
doesn’t need to rebuild
the target then you use the path found via directory search.
make
must rebuild, then the target is rebuilt locally,
not in the directory found via directory search.
This algorithm may seem complex, but in practice it is quite often exactly what you want.
Other versions of make
use a simpler algorithm: if the file does
not exist, and it is found via directory search, then that pathname is
always used whether or not the target needs to be built. Thus, if the
target is rebuilt it is created at the pathname discovered during
directory search.
If, in fact, this is the behavior you want for some or all of your
directories, you can use the GPATH
variable to indicate this to
make
.
GPATH
has the same syntax and format as VPATH
(that is, a
space- or colon-delimited list of pathnames). If an out-of-date target
is found by directory search in a directory that also appears in
GPATH
, then that pathname is not thrown away. The target is
rebuilt using the expanded path.
Next: Implicit/Search, Previous: Search Algorithm, Up: Directory Search [Contents][Index]
When a prerequisite is found in another directory through directory search,
this cannot change the recipe of the rule; they will execute as written.
Therefore, you must write the recipe with care so that it will look for
the prerequisite in the directory where make
finds it.
This is done with the automatic variables such as ‘$^’ (see Automatic Variables). For instance, the value of ‘$^’ is a list of all the prerequisites of the rule, including the names of the directories in which they were found, and the value of ‘$@’ is the target. Thus:
foo.o : foo.c cc -c $(CFLAGS) $^ -o $@
(The variable CFLAGS
exists so you can specify flags for C
compilation by implicit rules; we use it here for consistency so it will
affect all C compilations uniformly;
see Variables Used by Implicit Rules.)
Often the prerequisites include header files as well, which you do not want to mention in the recipe. The automatic variable ‘$<’ is just the first prerequisite:
VPATH = src:../headers foo.o : foo.c defs.h hack.h cc -c $(CFLAGS) $< -o $@
Next: Libraries/Search, Previous: Recipes/Search, Up: Directory Search [Contents][Index]
The search through the directories specified in VPATH
or with
vpath
also happens during consideration of implicit rules
(see Using Implicit Rules).
For example, when a file foo.o has no explicit rule, make
considers implicit rules, such as the built-in rule to compile
foo.c if that file exists. If such a file is lacking in the
current directory, the appropriate directories are searched for it. If
foo.c exists (or is mentioned in the makefile) in any of the
directories, the implicit rule for C compilation is applied.
The recipes of implicit rules normally use automatic variables as a matter of necessity; consequently they will use the file names found by directory search with no extra effort.
Previous: Implicit/Search, Up: Directory Search [Contents][Index]
Directory search applies in a special way to libraries used with the linker. This special feature comes into play when you write a prerequisite whose name is of the form ‘-lname’. (You can tell something strange is going on here because the prerequisite is normally the name of a file, and the file name of a library generally looks like libname.a, not like ‘-lname’.)
When a prerequisite’s name has the form ‘-lname’, make
handles it specially by searching for the file libname.so,
and, if it is not found, for the file libname.a in the current
directory, in directories specified by matching vpath
search paths and the VPATH
search path, and then in the
directories /lib, /usr/lib, and prefix/lib
(normally /usr/local/lib, but MS-DOS/MS-Windows versions of
make
behave as if prefix is defined to be the root of the
DJGPP installation tree).
For example, if there is a /usr/lib/libcurses.a library on your system (and no /usr/lib/libcurses.so file), then
foo : foo.c -lcurses cc $^ -o $@
would cause the command ‘cc foo.c /usr/lib/libcurses.a -o foo’ to be executed when foo is older than foo.c or than /usr/lib/libcurses.a.
Although the default set of files to be searched for is
libname.so and libname.a, this is customizable
via the .LIBPATTERNS
variable. Each word in the value of this
variable is a pattern string. When a prerequisite like
‘-lname’ is seen, make
will replace the percent in
each pattern in the list with name and perform the above directory
searches using each library file name.
The default value for .LIBPATTERNS
is ‘lib%.so lib%.a’,
which provides the default behavior described above.
You can turn off link library expansion completely by setting this variable to an empty value.
Next: Force Targets, Previous: Directory Search, Up: Rules [Contents][Index]
A phony target is one that is not really the name of a file; rather it is just a name for a recipe to be executed when you make an explicit request. There are two reasons to use a phony target: to avoid a conflict with a file of the same name, and to improve performance.
If you write a rule whose recipe will not create the target file, the recipe will be executed every time the target comes up for remaking. Here is an example:
clean: rm *.o temp
Because the rm
command does not create a file named clean,
probably no such file will ever exist. Therefore, the rm
command
will be executed every time you say ‘make clean’.
In this example, the clean target will not work properly if a
file named clean is ever created in this directory. Since it
has no prerequisites, clean would always be considered up to
date and its recipe would not be executed. To avoid this problem you
can explicitly declare the target to be phony by making it a
prerequisite of the special target .PHONY
(see Special Built-in Target Names) as follows:
.PHONY: clean clean: rm *.o temp
Once this is done, ‘make clean’ will run the recipe regardless of whether there is a file named clean.
Phony targets are also useful in conjunction with recursive
invocations of make
(see Recursive Use of make
).
In this situation the makefile will often contain a variable which
lists a number of sub-directories to be built. A simplistic way to
handle this is to define one rule with a recipe that loops over the
sub-directories, like this:
SUBDIRS = foo bar baz subdirs: for dir in $(SUBDIRS); do \ $(MAKE) -C $$dir; \ done
There are problems with this method, however. First, any error
detected in a sub-make is ignored by this rule, so it will continue
to build the rest of the directories even when one fails. This can be
overcome by adding shell commands to note the error and exit, but then
it will do so even if make
is invoked with the -k
option, which is unfortunate. Second, and perhaps more importantly,
you cannot take advantage of make
’s ability to build targets in
parallel (see Parallel Execution), since there is only
one rule.
By declaring the sub-directories as .PHONY
targets (you must do
this as the sub-directory obviously always exists; otherwise it won’t
be built) you can remove these problems:
SUBDIRS = foo bar baz .PHONY: subdirs $(SUBDIRS) subdirs: $(SUBDIRS) $(SUBDIRS): $(MAKE) -C $@ foo: baz
Here we’ve also declared that the foo sub-directory cannot be built until after the baz sub-directory is complete; this kind of relationship declaration is particularly important when attempting parallel builds.
The implicit rule search (see Implicit Rules) is skipped for
.PHONY
targets. This is why declaring a target as
.PHONY
is good for performance, even if you are not worried
about the actual file existing.
A phony target should not be a prerequisite of a real target file; if it
is, its recipe will be run every time make
goes to update that
file. As long as a phony target is never a prerequisite of a real
target, the phony target recipe will be executed only when the phony
target is a specified goal (see Arguments to Specify the
Goals).
Phony targets can have prerequisites. When one directory contains multiple programs, it is most convenient to describe all of the programs in one makefile ./Makefile. Since the target remade by default will be the first one in the makefile, it is common to make this a phony target named ‘all’ and give it, as prerequisites, all the individual programs. For example:
all : prog1 prog2 prog3 .PHONY : all prog1 : prog1.o utils.o cc -o prog1 prog1.o utils.o prog2 : prog2.o cc -o prog2 prog2.o prog3 : prog3.o sort.o utils.o cc -o prog3 prog3.o sort.o utils.o
Now you can say just ‘make’ to remake all three programs, or specify as arguments the ones to remake (as in ‘make prog1 prog3’). Phoniness is not inherited: the prerequisites of a phony target are not themselves phony, unless explicitly declared to be so.
When one phony target is a prerequisite of another, it serves as a subroutine of the other. For example, here ‘make cleanall’ will delete the object files, the difference files, and the file program:
.PHONY: cleanall cleanobj cleandiff cleanall : cleanobj cleandiff rm program cleanobj : rm *.o cleandiff : rm *.diff
Next: Empty Targets, Previous: Phony Targets, Up: Rules [Contents][Index]
If a rule has no prerequisites or recipe, and the target of the rule
is a nonexistent file, then make
imagines this target to have
been updated whenever its rule is run. This implies that all targets
depending on this one will always have their recipe run.
An example will illustrate this:
clean: FORCE rm $(objects) FORCE:
Here the target ‘FORCE’ satisfies the special conditions, so the target clean that depends on it is forced to run its recipe. There is nothing special about the name ‘FORCE’, but that is one name commonly used this way.
As you can see, using ‘FORCE’ this way has the same results as using ‘.PHONY: clean’.
Using ‘.PHONY’ is more explicit and more efficient. However,
other versions of make
do not support ‘.PHONY’; thus
‘FORCE’ appears in many makefiles. See Phony Targets.
Next: Special Targets, Previous: Force Targets, Up: Rules [Contents][Index]
The empty target is a variant of the phony target; it is used to hold recipes for an action that you request explicitly from time to time. Unlike a phony target, this target file can really exist; but the file’s contents do not matter, and usually are empty.
The purpose of the empty target file is to record, with its
last-modification time, when the rule’s recipe was last executed. It
does so because one of the commands in the recipe is a touch
command to update the target file.
The empty target file should have some prerequisites (otherwise it doesn’t make sense). When you ask to remake the empty target, the recipe is executed if any prerequisite is more recent than the target; in other words, if a prerequisite has changed since the last time you remade the target. Here is an example:
print: foo.c bar.c lpr -p $? touch print
With this rule, ‘make print’ will execute the lpr
command if
either source file has changed since the last ‘make print’. The
automatic variable ‘$?’ is used to print only those files that have
changed (see Automatic Variables).
Next: Multiple Targets, Previous: Empty Targets, Up: Rules [Contents][Index]
Certain names have special meanings if they appear as targets.
.PHONY
The prerequisites of the special target .PHONY
are considered to
be phony targets. When it is time to consider such a target,
make
will run its recipe unconditionally, regardless of
whether a file with that name exists or what its last-modification
time is. See Phony Targets.
.SUFFIXES
The prerequisites of the special target .SUFFIXES
are the list
of suffixes to be used in checking for suffix rules.
See Old-Fashioned Suffix Rules.
.DEFAULT
The recipe specified for .DEFAULT
is used for any target for
which no rules are found (either explicit rules or implicit rules).
See Last Resort. If a .DEFAULT
recipe is specified, every
file mentioned as a prerequisite, but not as a target in a rule, will have
that recipe executed on its behalf. See Implicit Rule Search Algorithm.
.PRECIOUS
The targets which .PRECIOUS
depends on are given the following
special treatment: if make
is killed or interrupted during the
execution of their recipes, the target is not deleted.
See Interrupting or Killing make
. Also, if the
target is an intermediate file, it will not be deleted after it is no
longer needed, as is normally done. See Chains of
Implicit Rules. In this latter respect it overlaps with the
.SECONDARY
special target.
You can also list the target pattern of an implicit rule (such as
‘%.o’) as a prerequisite file of the special target .PRECIOUS
to preserve intermediate files created by rules whose target patterns
match that file’s name.
.INTERMEDIATE
The targets which .INTERMEDIATE
depends on are treated as
intermediate files. See Chains of Implicit Rules.
.INTERMEDIATE
with no prerequisites has no effect.
.SECONDARY
The targets which .SECONDARY
depends on are treated as
intermediate files, except that they are never automatically deleted.
See Chains of Implicit Rules.
.SECONDARY
with no prerequisites causes all targets to be treated
as secondary (i.e., no target is removed because it is considered
intermediate).
.SECONDEXPANSION
If .SECONDEXPANSION
is mentioned as a target anywhere in the
makefile, then all prerequisite lists defined after it appears
will be expanded a second time after all makefiles have been read in.
See Secondary Expansion.
.DELETE_ON_ERROR
If .DELETE_ON_ERROR
is mentioned as a target anywhere in the
makefile, then make
will delete the target of a rule if it has
changed and its recipe exits with a nonzero exit status, just as it
does when it receives a signal. See Errors in Recipes.
.IGNORE
If you specify prerequisites for .IGNORE
, then make
will
ignore errors in execution of the recipe for those particular files.
The recipe for .IGNORE
(if any) is ignored.
If mentioned as a target with no prerequisites, .IGNORE
says to
ignore errors in execution of recipes for all files. This usage of
‘.IGNORE’ is supported only for historical compatibility. Since
this affects every recipe in the makefile, it is not very useful; we
recommend you use the more selective ways to ignore errors in specific
recipes. See Errors in Recipes.
.LOW_RESOLUTION_TIME
If you specify prerequisites for .LOW_RESOLUTION_TIME
,
make
assumes that these files are created by commands that
generate low resolution time stamps. The recipe for the
.LOW_RESOLUTION_TIME
target are ignored.
The high resolution file time stamps of many modern file systems
lessen the chance of make
incorrectly concluding that a file
is up to date. Unfortunately, some hosts do not provide a way to set a
high resolution file time stamp, so commands like ‘cp -p’ that
explicitly set a file’s time stamp must discard its sub-second part.
If a file is created by such a command, you should list it as a
prerequisite of .LOW_RESOLUTION_TIME
so that make
does not mistakenly conclude that the file is out of date. For
example:
.LOW_RESOLUTION_TIME: dst dst: src cp -p src dst
Since ‘cp -p’ discards the sub-second part of src’s time
stamp, dst is typically slightly older than src even when
it is up to date. The .LOW_RESOLUTION_TIME
line causes
make
to consider dst to be up to date if its time stamp
is at the start of the same second that src’s time stamp is in.
Due to a limitation of the archive format, archive member time stamps
are always low resolution. You need not list archive members as
prerequisites of .LOW_RESOLUTION_TIME
, as make
does this
automatically.
.SILENT
If you specify prerequisites for .SILENT
, then make
will
not print the recipe used to remake those particular files before
executing them. The recipe for .SILENT
is ignored.
If mentioned as a target with no prerequisites, .SILENT
says not
to print any recipes before executing them. This usage of
‘.SILENT’ is supported only for historical compatibility. We
recommend you use the more selective ways to silence specific recipes.
See Recipe Echoing. If you want to silence all recipes
for a particular run of make
, use the ‘-s’ or
‘--silent’ option (see Options Summary).
.EXPORT_ALL_VARIABLES
Simply by being mentioned as a target, this tells make
to
export all variables to child processes by default.
See Communicating Variables to a
Sub-make
.
.NOTPARALLEL
If .NOTPARALLEL
is mentioned as a target, then this invocation
of make
will be run serially, even if the ‘-j’ option is
given. Any recursively invoked make
command will still run
recipes in parallel (unless its makefile also contains this target).
Any prerequisites on this target are ignored.
.ONESHELL
If .ONESHELL
is mentioned as a target, then when a target is
built all lines of the recipe will be given to a single invocation of
the shell rather than each line being invoked separately
(see Recipe Execution).
.POSIX
If .POSIX
is mentioned as a target, then the makefile will be
parsed and run in POSIX-conforming mode. This does not mean
that only POSIX-conforming makefiles will be accepted: all advanced
GNU make
features are still available. Rather, this target
causes make
to behave as required by POSIX in those areas
where make
’s default behavior differs.
In particular, if this target is mentioned then recipes will be
invoked as if the shell had been passed the -e
flag: the first
failing command in a recipe will cause the recipe to fail immediately.
Any defined implicit rule suffix also counts as a special target if it appears as a target, and so does the concatenation of two suffixes, such as ‘.c.o’. These targets are suffix rules, an obsolete way of defining implicit rules (but a way still widely used). In principle, any target name could be special in this way if you break it in two and add both pieces to the suffix list. In practice, suffixes normally begin with ‘.’, so these special target names also begin with ‘.’. See Old-Fashioned Suffix Rules.
Next: Multiple Rules, Previous: Special Targets, Up: Rules [Contents][Index]
A rule with multiple targets is equivalent to writing many rules, each with one target, and all identical aside from that. The same recipe applies to all the targets, but its effect may vary because you can substitute the actual target name into the recipe using ‘$@’. The rule contributes the same prerequisites to all the targets also.
This is useful in two cases.
kbd.o command.o files.o: command.h
gives an additional prerequisite to each of the three object files mentioned.
bigoutput littleoutput : text.g generate text.g -$(subst output,,$@) > $@
is equivalent to
bigoutput : text.g generate text.g -big > bigoutput littleoutput : text.g generate text.g -little > littleoutput
Here we assume the hypothetical program generate
makes two
types of output, one if given ‘-big’ and one if given
‘-little’.
See Functions for String Substitution and Analysis,
for an explanation of the subst
function.
Suppose you would like to vary the prerequisites according to the target, much as the variable ‘$@’ allows you to vary the recipe. You cannot do this with multiple targets in an ordinary rule, but you can do it with a static pattern rule. See Static Pattern Rules.
Next: Static Pattern, Previous: Multiple Targets, Up: Rules [Contents][Index]
One file can be the target of several rules. All the prerequisites mentioned in all the rules are merged into one list of prerequisites for the target. If the target is older than any prerequisite from any rule, the recipe is executed.
There can only be one recipe to be executed for a file. If more than
one rule gives a recipe for the same file, make
uses the last
one given and prints an error message. (As a special case, if the
file’s name begins with a dot, no error message is printed. This odd
behavior is only for compatibility with other implementations of
make
… you should avoid using it). Occasionally it is
useful to have the same target invoke multiple recipes which are
defined in different parts of your makefile; you can use
double-colon rules (see Double-Colon) for this.
An extra rule with just prerequisites can be used to give a few extra
prerequisites to many files at once. For example, makefiles often
have a variable, such as objects
, containing a list of all the
compiler output files in the system being made. An easy way to say
that all of them must be recompiled if config.h changes is to
write the following:
objects = foo.o bar.o foo.o : defs.h bar.o : defs.h test.h $(objects) : config.h
This could be inserted or taken out without changing the rules that really specify how to make the object files, making it a convenient form to use if you wish to add the additional prerequisite intermittently.
Another wrinkle is that the additional prerequisites could be
specified with a variable that you set with a command line argument to
make
(see Overriding Variables). For example,
extradeps= $(objects) : $(extradeps)
means that the command ‘make extradeps=foo.h’ will consider foo.h as a prerequisite of each object file, but plain ‘make’ will not.
If none of the explicit rules for a target has a recipe, then make
searches for an applicable implicit rule to find one
see Using Implicit Rules).
Next: Double-Colon, Previous: Multiple Rules, Up: Rules [Contents][Index]
Static pattern rules are rules which specify multiple targets and construct the prerequisite names for each target based on the target name. They are more general than ordinary rules with multiple targets because the targets do not have to have identical prerequisites. Their prerequisites must be analogous, but not necessarily identical.
| • Static Usage: | The syntax of static pattern rules. | |
| • Static versus Implicit: | When are they better than implicit rules? |
Next: Static versus Implicit, Previous: Static Pattern, Up: Static Pattern [Contents][Index]
Here is the syntax of a static pattern rule:
targets …: target-pattern: prereq-patterns … recipe …
The targets list specifies the targets that the rule applies to. The targets can contain wildcard characters, just like the targets of ordinary rules (see Using Wildcard Characters in File Names).
The target-pattern and prereq-patterns say how to compute the prerequisites of each target. Each target is matched against the target-pattern to extract a part of the target name, called the stem. This stem is substituted into each of the prereq-patterns to make the prerequisite names (one from each prereq-pattern).
Each pattern normally contains the character ‘%’ just once. When the target-pattern matches a target, the ‘%’ can match any part of the target name; this part is called the stem. The rest of the pattern must match exactly. For example, the target foo.o matches the pattern ‘%.o’, with ‘foo’ as the stem. The targets foo.c and foo.out do not match that pattern.
The prerequisite names for each target are made by substituting the stem for the ‘%’ in each prerequisite pattern. For example, if one prerequisite pattern is %.c, then substitution of the stem ‘foo’ gives the prerequisite name foo.c. It is legitimate to write a prerequisite pattern that does not contain ‘%’; then this prerequisite is the same for all targets.
‘%’ characters in pattern rules can be quoted with preceding backslashes (‘\’). Backslashes that would otherwise quote ‘%’ characters can be quoted with more backslashes. Backslashes that quote ‘%’ characters or other backslashes are removed from the pattern before it is compared to file names or has a stem substituted into it. Backslashes that are not in danger of quoting ‘%’ characters go unmolested. For example, the pattern the\%weird\\%pattern\\ has ‘the%weird\’ preceding the operative ‘%’ character, and ‘pattern\\’ following it. The final two backslashes are left alone because they cannot affect any ‘%’ character.
Here is an example, which compiles each of foo.o and bar.o from the corresponding .c file:
objects = foo.o bar.o all: $(objects) $(objects): %.o: %.c $(CC) -c $(CFLAGS) $< -o $@
Here ‘$<’ is the automatic variable that holds the name of the prerequisite and ‘$@’ is the automatic variable that holds the name of the target; see Automatic Variables.
Each target specified must match the target pattern; a warning is issued
for each target that does not. If you have a list of files, only some of
which will match the pattern, you can use the filter
function to
remove non-matching file names (see Functions for String Substitution and Analysis):
files = foo.elc bar.o lose.o $(filter %.o,$(files)): %.o: %.c $(CC) -c $(CFLAGS) $< -o $@ $(filter %.elc,$(files)): %.elc: %.el emacs -f batch-byte-compile $<
In this example the result of ‘$(filter %.o,$(files))’ is bar.o lose.o, and the first static pattern rule causes each of these object files to be updated by compiling the corresponding C source file. The result of ‘$(filter %.elc,$(files))’ is foo.elc, so that file is made from foo.el.
Another example shows how to use $*
in static pattern rules:
bigoutput littleoutput : %output : text.g generate text.g -$* > $@
When the generate
command is run, $*
will expand to the
stem, either ‘big’ or ‘little’.
Previous: Static Usage, Up: Static Pattern [Contents][Index]
A static pattern rule has much in common with an implicit rule defined as a
pattern rule (see Defining and Redefining Pattern Rules).
Both have a pattern for the target and patterns for constructing the
names of prerequisites. The difference is in how make
decides
when the rule applies.
An implicit rule can apply to any target that matches its pattern, but it does apply only when the target has no recipe otherwise specified, and only when the prerequisites can be found. If more than one implicit rule appears applicable, only one applies; the choice depends on the order of rules.
By contrast, a static pattern rule applies to the precise list of targets that you specify in the rule. It cannot apply to any other target and it invariably does apply to each of the targets specified. If two conflicting rules apply, and both have recipes, that’s an error.
The static pattern rule can be better than an implicit rule for these reasons:
make
to use the wrong implicit rule. The choice
might depend on the order in which the implicit rule search is done.
With static pattern rules, there is no uncertainty: each rule applies
to precisely the targets specified.
Next: Automatic Prerequisites, Previous: Static Pattern, Up: Rules [Contents][Index]
Double-colon rules are explicit rules written with ‘::’ instead of ‘:’ after the target names. They are handled differently from ordinary rules when the same target appears in more than one rule. Pattern rules with double-colons have an entirely different meaning (see Match-Anything Rules).
When a target appears in multiple rules, all the rules must be the same type: all ordinary, or all double-colon. If they are double-colon, each of them is independent of the others. Each double-colon rule’s recipe is executed if the target is older than any prerequisites of that rule. If there are no prerequisites for that rule, its recipe is always executed (even if the target already exists). This can result in executing none, any, or all of the double-colon rules.
Double-colon rules with the same target are in fact completely separate from one another. Each double-colon rule is processed individually, just as rules with different targets are processed.
The double-colon rules for a target are executed in the order they appear in the makefile. However, the cases where double-colon rules really make sense are those where the order of executing the recipes would not matter.
Double-colon rules are somewhat obscure and not often very useful; they provide a mechanism for cases in which the method used to update a target differs depending on which prerequisite files caused the update, and such cases are rare.
Each double-colon rule should specify a recipe; if it does not, an implicit rule will be used if one applies. See Using Implicit Rules.
Previous: Double-Colon, Up: Rules [Contents][Index]
In the makefile for a program, many of the rules you need to write often
say only that some object file depends on some header
file. For example, if main.c uses defs.h via an
#include
, you would write:
main.o: defs.h
You need this rule so that make
knows that it must remake
main.o whenever defs.h changes. You can see that for a
large program you would have to write dozens of such rules in your
makefile. And, you must always be very careful to update the makefile
every time you add or remove an #include
.
To avoid this hassle, most modern C compilers can write these rules for
you, by looking at the #include
lines in the source files.
Usually this is done with the ‘-M’ option to the compiler.
For example, the command:
cc -M main.c
generates the output:
main.o : main.c defs.h
Thus you no longer have to write all those rules yourself. The compiler will do it for you.
Note that such a rule constitutes mentioning main.o in a
makefile, so it can never be considered an intermediate file by
implicit rule search. This means that make
won’t ever remove
the file after using it; see Chains of Implicit
Rules.
With old make
programs, it was traditional practice to use this
compiler feature to generate prerequisites on demand with a command like
‘make depend’. That command would create a file depend
containing all the automatically-generated prerequisites; then the
makefile could use include
to read them in (see Include).
In GNU make
, the feature of remaking makefiles makes this
practice obsolete—you need never tell make
explicitly to
regenerate the prerequisites, because it always regenerates any makefile
that is out of date. See Remaking Makefiles.
The practice we recommend for automatic prerequisite generation is to have one makefile corresponding to each source file. For each source file name.c there is a makefile name.d which lists what files the object file name.o depends on. That way only the source files that have changed need to be rescanned to produce the new prerequisites.
Here is the pattern rule to generate a file of prerequisites (i.e., a makefile) called name.d from a C source file called name.c:
%.d: %.c @set -e; rm -f $@; \ $(CC) -M $(CPPFLAGS) $< ><EMAIL_ADDRESS>\ sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' <<EMAIL_ADDRESS>> $@; \ rm -f<EMAIL_ADDRESS>See Pattern Rules, for information on defining pattern rules. The
‘-e’ flag to the shell causes it to exit immediately if the
$(CC)
command (or any other command) fails (exits with a
nonzero status).
With the GNU C compiler, you may wish to use the ‘-MM’ flag instead of ‘-M’. This omits prerequisites on system header files. See Options Controlling the Preprocessor in Using GNU CC, for details.
The purpose of the sed
command is to translate (for example):
main.o : main.c defs.h
into:
main.o main.d : main.c defs.h
This makes each ‘.d’ file depend on all the source and header files
that the corresponding ‘.o’ file depends on. make
then
knows it must regenerate the prerequisites whenever any of the source or
header files changes.
Once you’ve defined the rule to remake the ‘.d’ files,
you then use the include
directive to read them all in.
See Include. For example:
sources = foo.c bar.c include $(sources:.c=.d)
(This example uses a substitution variable reference to translate the
list of source files ‘foo.c bar.c’ into a list of prerequisite
makefiles, ‘foo.d bar.d’. See Substitution Refs, for full
information on substitution references.) Since the ‘.d’ files are
makefiles like any others, make
will remake them as necessary
with no further work from you. See Remaking Makefiles.
Note that the ‘.d’ files contain target definitions; you should
be sure to place the include
directive after the first,
default goal in your makefiles or run the risk of having a random
object file become the default goal.
See How Make Works.
Next: Using Variables, Previous: Rules, Up: Top [Contents][Index]
The recipe of a rule consists of one or more shell command lines to be executed, one at a time, in the order they appear. Typically, the result of executing these commands is that the target of the rule is brought up to date.
Users use many different shell programs, but recipes in makefiles are always interpreted by /bin/sh unless the makefile specifies otherwise. See Recipe Execution.
| • Recipe Syntax: | Recipe syntax features and pitfalls. | |
| • Echoing: | How to control when recipes are echoed. | |
| • Execution: | How recipes are executed. | |
| • Parallel: | How recipes can be executed in parallel. | |
| • Errors: | What happens after a recipe execution error. | |
| • Interrupts: | What happens when a recipe is interrupted. | |
| • Recursion: | Invoking make from makefiles.
| |
| • Canned Recipes: | Defining canned recipes. | |
| • Empty Recipes: | Defining useful, do-nothing recipes. |
Makefiles have the unusual property that there are really two distinct
syntaxes in one file. Most of the makefile uses make
syntax
(see Writing Makefiles). However, recipes are meant
to be interpreted by the shell and so they are written using shell
syntax. The make
program does not try to understand shell
syntax: it performs only a very few specific translations on the
content of the recipe before handing it to the shell.
Each line in the recipe must start with a tab (or the first character
in the value of the .RECIPEPREFIX
variable; see Special Variables), except that the first recipe line may be attached to the
target-and-prerequisites line with a semicolon in between. Any
line in the makefile that begins with a tab and appears in a “rule
context” (that is, after a rule has been started until another rule
or variable definition) will be considered part of a recipe for that
rule. Blank lines and lines of just comments may appear among the
recipe lines; they are ignored.
Some consequences of these rules include:
make
comment; it will be
passed to the shell as-is. Whether the shell treats it as a comment
or not depends on your shell.
make
variable definition, and passed to the
shell.
ifdef
, ifeq
,
etc. see Syntax of Conditionals) in a “rule
context” which is indented by a tab as the first character on the
line, will be considered part of a recipe and be passed to the shell.
| • Splitting Recipe Lines: | Breaking long recipe lines for readability. | |
| • Variables in Recipes: | Using make variables in recipes.
|
Next: Variables in Recipes, Previous: Recipe Syntax, Up: Recipe Syntax [Contents][Index]
One of the few ways in which make
does interpret recipes is
checking for a backslash just before the newline. As in normal
makefile syntax, a single logical recipe line can be split into
multiple physical lines in the makefile by placing a backslash before
each newline. A sequence of lines like this is considered a single
recipe line, and one instance of the shell will be invoked to run it.
However, in contrast to how they are treated in other places in a makefile (see Splitting Long Lines), backslash/newline pairs are not removed from the recipe. Both the backslash and the newline characters are preserved and passed to the shell. How the backslash/newline is interpreted depends on your shell. If the first character of the next line after the backslash/newline is the recipe prefix character (a tab by default; see Special Variables), then that character (and only that character) is removed. Whitespace is never added to the recipe.
For example, the recipe for the all target in this makefile:
all : @echo no\ space @echo no\ space @echo one \ space @echo one\ space
consists of four separate shell commands where the output is:
nospace nospace one space one space
As a more complex example, this makefile:
all : ; @echo 'hello \ world' ; echo "hello \ world"
will invoke one shell with a command of:
echo 'hello \ world' ; echo "hello \ world"
which, according to shell quoting rules, will yield the following output:
hello \ world hello world
Notice how the backslash/newline pair was removed inside the string
quoted with double quotes ("…"
), but not from the string
quoted with single quotes ('…'
). This is the way the
default shell (/bin/sh) handles backslash/newline pairs. If
you specify a different shell in your makefiles it may treat them
differently.
Sometimes you want to split a long line inside of single quotes, but
you don’t want the backslash/newline to appear in the quoted content.
This is often the case when passing scripts to languages such as Perl,
where extraneous backslashes inside the script can change its meaning
or even be a syntax error. One simple way of handling this is to
place the quoted string, or even the entire command, into a
make
variable then use the variable in the recipe. In this
situation the newline quoting rules for makefiles will be used, and
the backslash/newline will be removed. If we rewrite our example
above using this method:
HELLO = 'hello \ world' all : ; @echo $(HELLO)
we will get output like this:
hello world
If you like, you can also use target-specific variables (see Target-specific Variable Values) to obtain a tighter correspondence between the variable and the recipe that uses it.
Previous: Splitting Recipe Lines, Up: Recipe Syntax [Contents][Index]
The other way in which make
processes recipes is by expanding
any variable references in them (see Basics of Variable
References). This occurs after make has finished reading all the
makefiles and the target is determined to be out of date; so, the
recipes for targets which are not rebuilt are never expanded.
Variable and function references in recipes have identical syntax and
semantics to references elsewhere in the makefile. They also have the
same quoting rules: if you want a dollar sign to appear in your
recipe, you must double it (‘$$’). For shells like the default
shell, that use dollar signs to introduce variables, it’s important to
keep clear in your mind whether the variable you want to reference is
a make
variable (use a single dollar sign) or a shell variable
(use two dollar signs). For example:
LIST = one two three all: for i in $(LIST); do \ echo $$i; \ done
results in the following command being passed to the shell:
for i in one two three; do \ echo $i; \ done
which generates the expected result:
one two three
Next: Execution, Previous: Recipe Syntax, Up: Recipes [Contents][Index]
Normally make
prints each line of the recipe before it is
executed. We call this echoing because it gives the appearance
that you are typing the lines yourself.
When a line starts with ‘@’, the echoing of that line is suppressed.
The ‘@’ is discarded before the line is passed to the shell.
Typically you would use this for a command whose only effect is to print
something, such as an echo
command to indicate progress through
the makefile:
@echo About to make distribution files
When make
is given the flag ‘-n’ or ‘--just-print’ it
only echoes most recipes, without executing them. See Summary of Options. In this case even the recipe lines
starting with ‘@’ are printed. This flag is useful for finding
out which recipes make
thinks are necessary without actually
doing them.
The ‘-s’ or ‘--silent’
flag to make
prevents all echoing, as if all recipes
started with ‘@’. A rule in the makefile for the special target
.SILENT
without prerequisites has the same effect
(see Special Built-in Target Names).
.SILENT
is essentially obsolete since ‘@’ is more flexible.
When it is time to execute recipes to update a target, they are
executed by invoking a new sub-shell for each line of the recipe,
unless the .ONESHELL
special target is in effect
(see Using One Shell) (In practice, make
may
take shortcuts that do not affect the results.)
Please note: this implies that setting shell variables and
invoking shell commands such as cd
that set a context local to
each process will not affect the following lines in the recipe.2 If you want to use cd
to affect the next statement,
put both statements in a single recipe line. Then make
will
invoke one shell to run the entire line, and the shell will execute
the statements in sequence. For example:
foo : bar/lose cd $(@D) && gobble $(@F) > ../$@
Here we use the shell AND operator (&&
) so that if the
cd
command fails, the script will fail without trying to invoke
the gobble
command in the wrong directory, which could cause
problems (in this case it would certainly cause ../foo to be
truncated, at least).
| • One Shell: | One shell for all lines in a recipe. | |
| • Choosing the Shell: | How make chooses the shell used
to run recipes.
|
Next: Choosing the Shell, Previous: Execution, Up: Execution [Contents][Index]
Sometimes you would prefer that all the lines in the recipe be passed
to a single invocation of the shell. There are generally two
situations where this is useful: first, it can improve performance in
makefiles where recipes consist of many command lines, by avoiding
extra processes. Second, you might want newlines to be included in
your recipe command (for example perhaps you are using a very
different interpreter as your SHELL
). If the .ONESHELL
special target appears anywhere in the makefile then all
recipe lines for each target will be provided to a single invocation
of the shell. Newlines between recipe lines will be preserved. For
example:
.ONESHELL: foo : bar/lose cd $(@D) gobble $(@F) > ../$@
would now work as expected even though the commands are on different recipe lines.
If .ONESHELL
is provided, then only the first line of the
recipe will be checked for the special prefix characters (‘@’,
‘-’, and ‘+’). Subsequent lines will include the special
characters in the recipe line when the SHELL
is invoked. If
you want your recipe to start with one of these special characters
you’ll need to arrange for them to not be the first characters on the
first line, perhaps by adding a comment or similar. For example, this
would be a syntax error in Perl because the first ‘@’ is removed
by make:
.ONESHELL: SHELL = /usr/bin/perl .SHELLFLAGS = -e show : @f = qw(a b c); print "@f\n";
However, either of these alternatives would work properly:
.ONESHELL: SHELL = /usr/bin/perl .SHELLFLAGS = -e show : # Make sure "@" is not the first character on the first line @f = qw(a b c); print "@f\n";
or
.ONESHELL: SHELL = /usr/bin/perl .SHELLFLAGS = -e show : my @f = qw(a b c); print "@f\n";
As a special feature, if SHELL
is determined to be a
POSIX-style shell, the special prefix characters in “internal”
recipe lines will removed before the recipe is processed. This
feature is intended to allow existing makefiles to add the
.ONESHELL
special target and still run properly without
extensive modifications. Since the special prefix characters are not
legal at the beginning of a line in a POSIX shell script this is not a
loss in functionality. For example, this works as expected:
.ONESHELL: foo : bar/lose @cd $(@D) @gobble $(@F) > ../$@
Even with this special feature, however, makefiles with
.ONESHELL
will behave differently in ways that could be
noticeable. For example, normally if any line in the recipe fails,
that causes the rule to fail and no more recipe lines are processed.
Under .ONESHELL
a failure of any but the final recipe line will
not be noticed by make
. You can modify .SHELLFLAGS
to
add the -e
option to the shell which will cause any failure
anywhere in the command line to cause the shell to fail, but this
could itself cause your recipe to behave differently. Ultimately you
may need to harden your recipe lines to allow them to work with
.ONESHELL
.
The program used as the shell is taken from the variable SHELL
.
If this variable is not set in your makefile, the program
/bin/sh is used as the shell. The argument(s) passed to the
shell are taken from the variable .SHELLFLAGS
. The default
value of .SHELLFLAGS
is -c
normally, or -ec
in
POSIX-conforming mode.
Unlike most variables, the variable SHELL
is never set from the
environment. This is because the SHELL
environment variable is
used to specify your personal choice of shell program for interactive
use. It would be very bad for personal choices like this to affect the
functioning of makefiles. See Variables from the
Environment.
Furthermore, when you do set SHELL
in your makefile that value
is not exported in the environment to recipe lines that
make
invokes. Instead, the value inherited from the user’s
environment, if any, is exported. You can override this behavior by
explicitly exporting SHELL
(see Communicating Variables to a Sub-make
), forcing it to be
passed in the environment to recipe lines.
However, on MS-DOS and MS-Windows the value of SHELL
in the
environment is used, since on those systems most users do not
set this variable, and therefore it is most likely set specifically to
be used by make
. On MS-DOS, if the setting of SHELL
is
not suitable for make
, you can set the variable
MAKESHELL
to the shell that make
should use; if set it
will be used as the shell instead of the value of SHELL
.
Choosing a shell in MS-DOS and MS-Windows is much more complex than on other systems.
On MS-DOS, if SHELL
is not set, the value of the variable
COMSPEC
(which is always set) is used instead.
The processing of lines that set the variable SHELL
in Makefiles
is different on MS-DOS. The stock shell, command.com, is
ridiculously limited in its functionality and many users of make
tend to install a replacement shell. Therefore, on MS-DOS, make
examines the value of SHELL
, and changes its behavior based on
whether it points to a Unix-style or DOS-style shell. This allows
reasonable functionality even if SHELL
points to
command.com.
If SHELL
points to a Unix-style shell, make
on MS-DOS
additionally checks whether that shell can indeed be found; if not, it
ignores the line that sets SHELL
. In MS-DOS, GNU make
searches for the shell in the following places:
SHELL
. For
example, if the makefile specifies ‘SHELL = /bin/sh’, make
will look in the directory /bin on the current drive.
PATH
variable, in order.
In every directory it examines, make
will first look for the
specific file (sh in the example above). If this is not found,
it will also look in that directory for that file with one of the known
extensions which identify executable files. For example .exe,
.com, .bat, .btm, .sh, and some others.
If any of these attempts is successful, the value of SHELL
will
be set to the full pathname of the shell as found. However, if none of
these is found, the value of SHELL
will not be changed, and thus
the line that sets it will be effectively ignored. This is so
make
will only support features specific to a Unix-style shell if
such a shell is actually installed on the system where make
runs.
Note that this extended search for the shell is limited to the cases
where SHELL
is set from the Makefile; if it is set in the
environment or command line, you are expected to set it to the full
pathname of the shell, exactly as things are on Unix.
The effect of the above DOS-specific processing is that a Makefile that
contains ‘SHELL = /bin/sh’ (as many Unix makefiles do), will work
on MS-DOS unaltered if you have e.g. sh.exe installed in some
directory along your PATH
.
GNU make
knows how to execute several recipes at once.
Normally, make
will execute only one recipe at a time, waiting
for it to finish before executing the next. However, the ‘-j’ or
‘--jobs’ option tells make
to execute many recipes
simultaneously. You can inhibit parallelism in a particular makefile
with the .NOTPARALLEL
pseudo-target (see Special Built-in Target Names).
On MS-DOS, the ‘-j’ option has no effect, since that system doesn’t support multi-processing.
If the ‘-j’ option is followed by an integer, this is the number of recipes to execute at once; this is called the number of job slots. If there is nothing looking like an integer after the ‘-j’ option, there is no limit on the number of job slots. The default number of job slots is one, which means serial execution (one thing at a time).
Handling recursive make
invocations raises issues for parallel
execution. For more information on this, see Communicating Options to a Sub-make
.
If a recipe fails (is killed by a signal or exits with a nonzero
status), and errors are not ignored for that recipe (see Errors in Recipes), the remaining recipe lines to remake the same
target will not be run. If a recipe fails and the ‘-k’ or
‘--keep-going’ option was not given (see Summary of Options), make
aborts execution. If make
terminates for any reason (including a signal) with child processes
running, it waits for them to finish before actually exiting.
When the system is heavily loaded, you will probably want to run fewer jobs
than when it is lightly loaded. You can use the ‘-l’ option to tell
make
to limit the number of jobs to run at once, based on the load
average. The ‘-l’ or ‘--max-load’
option is followed by a floating-point number. For
example,
-l 2.5
will not let make
start more than one job if the load average is
above 2.5. The ‘-l’ option with no following number removes the
load limit, if one was given with a previous ‘-l’ option.
More precisely, when make
goes to start up a job, and it already has
at least one job running, it checks the current load average; if it is not
lower than the limit given with ‘-l’, make
waits until the load
average goes below that limit, or until all the other jobs finish.
By default, there is no load limit.
| • Parallel Output: | Handling output during parallel execution | |
| • Parallel Input: | Handling input during parallel execution |
Next: Parallel Input, Previous: Parallel, Up: Parallel [Contents][Index]
When running several recipes in parallel the output from each recipe appears as soon as it is generated, with the result that messages from different recipes may be interspersed, sometimes even appearing on the same line. This can make reading the output very difficult.
To avoid this you can use the ‘--output-sync’ (‘-O’) option.
This option instructs make
to save the output from the commands
it invokes and print it all once the commands are completed.
Additionally, if there are multiple recursive make
invocations
running in parallel, they will communicate so that only one of them is
generating output at a time.
If working directory printing is enabled (see The
‘--print-directory’ Option), the enter/leave messages are
printed around each output grouping. If you prefer not to see these
messages add the ‘--no-print-directory’ option to MAKEFLAGS
.
There are four levels of granularity when synchronizing output, specified by giving an argument to the option (e.g., ‘-Oline’ or ‘--output-sync=recurse’).
none
This is the default: all output is sent directly as it is generated and no synchronization is performed.
line
Output from each individual line of the recipe is grouped and printed as soon as that line is complete. If a recipe consists of multiple lines, they may be interspersed with lines from other recipes.
target
Output from the entire recipe for each target is grouped and printed
once the target is complete. This is the default if the
--output-sync
or -O
option is given with no argument.
recurse
Output from each recursive invocation of make
is grouped and
printed once the recursive invocation is complete.
Regardless of the mode chosen, the total build time will be the same. The only difference is in how the output appears.
The ‘target’ and ‘recurse’ modes both collect the output of
the entire recipe of a target and display it uninterrupted when the
recipe completes. The difference between them is in how recipes that
contain recursive invocations of make
are treated
(see Recursive Use of make
). For all recipes
which have no recursive lines, the ‘target’ and ‘recurse’
modes behave identically.
If the ‘recurse’ mode is chosen, recipes that contain recursive
make
invocations are treated the same as other targets: the
output from the recipe, including the output from the recursive
make
, is saved and printed after the entire recipe is complete.
This ensures output from all the targets built by a given recursive
make
instance are grouped together, which may make the output
easier to understand. However it also leads to long periods of time
during the build where no output is seen, followed by large bursts of
output. If you are not watching the build as it proceeds, but instead
viewing a log of the build after the fact, this may be the best option
for you.
If you are watching the output, the long gaps of quiet during the
build can be frustrating. The ‘target’ output synchronization
mode detects when make
is going to be invoked recursively,
using the standard methods, and it will not synchronize the output of
those lines. The recursive make
will perform the
synchronization for its targets and the output from each will be
displayed immediately when it completes. Be aware that output from
recursive lines of the recipe are not synchronized (for example if
the recursive line prints a message before running make
, that
message will not be synchronized).
The ‘line’ mode can be useful for front-ends that are watching
the output of make
to track when recipes are started and
completed.
Some programs invoked by make
may behave differently if they
determine they’re writing output to a terminal versus a file (often
described as “interactive” vs. “non-interactive” modes). For
example, many programs that can display colorized output will not do
so if they determine they are not writing to a terminal. If your
makefile invokes a program like this then using the output
synchronization options will cause the program to believe it’s running