The Pierre-Emerick Aubameyang promise to disappoint Barcelona fans over Arsenal transfer rumours
The Arsenal striker has been linked with a move to Barcelona
by Andy HaPierre-Emerick Aubameyang previously revealed that he 'dreams' of playing for Real Madrid and promised his grandfather he would join the Spanish side one day.
The striker has established himself as one of the most feared strikers in Europe since joining Arsenal in January 2018, and his form has reportedly attracted interest from Barcelona.
According to French outlet Le10 Sport, the La Liga side are keen to sign a forward in the January transfer window, and are eyeing a move for the Arsenal forward.
The report does say however, that Barcelona are yet to make an official approach.
Aubameyang has scored nine goals in 13 appearances so far this season, something which, according to former Arsenal transfer chief Mislintat, is even more impressive considering his selfless nature on the pitch.
Speaking to The Athletic , he said: "He is one, possibly the only one, of these extraordinary top, top, top strikers who is an absolute team player.
"A striker like Neymar or (Sergio) Aguero, for example, would never give a penalty to Pepe to score his first goal. It’s vice versa — ‘Come on, I will take this penalty kick, nobody else!’ Auba gave the chance to Pepe.
"His instinct was, ‘Let’s score and let’s go forward together.’ He takes care about his team-mates.
“Since he joined Arsenal, he played where he was asked and needed, and so he helped especially Lacazette to adapt to the Premier League.
"Maybe this attitude costs him to play for clubs like Real Madrid or Barcelona but maybe they made a mistake not to go for him. I like his mindset. It is good for a team’s atmosphere.”
But Aubameyang confirmed his ambitions of playing for Real Madrid, something which could make a move to fierce rivals Barcelona more unlikely in the future.
"Yes. It's a promise I made to my grandfather," he told beIN Sports after a Champions League match whilst at Borussia Dortmund.
"Right now I feel very good at Dortmund but in the future we'll see."


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In this tutorial we will implement a toy VLSI layout verification application. In VLSI CAD an important step of design is the sign off check that verifies that the physical layout as drawn by mask designers and automated tools implements the logical schematic specified by design engineers. Physical layout is modeled as polygons on layers that are used to print the layout to the silicon wafer during manufacture. It is much better to find physical design mistakes before spending millions of dollars to prepare lithography masks and run a test lot of wafers.
Real layout file formats are binary and often compressed and represent a folded hierarchical model of layout where a group of polygons can be grouped into a cell and instantiated as a group into other cells. For this tutorial we assume a simplified ascii layout file format with no design hierarchy, which we would call "flat" in VLSI jargon. Similarly we assume a flat, ascii logical schematic net list file format. A net is a named electrical connection in a circuit design. The goal of the layout verification tutorial is to parse these two file formats, apply geometry operations provided by Boost.Polygon on the layout data to generate a logical schematic that represents what is implemented in the physical layout and then compare the input schematic with the generated schematic to determine whether they are the same.
First let us define some objects that we will need in the design of our toy layout verification application:
Layout Rectangle: An axis-parallel rectangle with a layer associated
Layout Pin: An axis-parallel rectangle with a layer and net (electrical signal)
name associated
Layout Database: An associative container of layer name to polygon set
Connectivity Database: An associative container of net name to layout database
Physical Device: A specific geometric arrangement on several layers with one or
more input net and one output net
Logical Net: A named graph node
Logical Device: An un-named graph node with a device type
Logical Pin: A special net that defines an input or output for the circuit
Schematic Database: A graph consisting of nets and logical
devices
Next let's define the sequence of operations performed by our toy layout versus schematic application:
Parse Layout: Stream layout rectangles and polygons into a layout database
and stream layout pins into a connectivity database
Extract Connectivity: Add polygons from layout database to connectivity database
by physical touch or overlap relationship
Extract Devices: Populate a schematic database with logical devices based on
physical devices identified within the layout geometry and extract their
terminals from the
connectivity database
Extract Net List: Complete graph represented in schematic database derived from
layout
Parse Schematic: Stream logical nets, devices and pins into a schematic
database
Compare Schematics: Evaluate whether extracted schematic database is equivalent
to input schematic database and output result
To test our application we will extract single logic gates. A logic gate is several transistors that work together to perform a specific logic function. Logic functions include the commonly understood Boolean logic operations such as Boolean AND, OR, XOR and INVERT. Also frequently used are NAND and NOR, which are respectively AND and OR operations followed by an INVERT operation. A NAND gate can be implemented in the CMOS circuit family with four transistors. The NAND gate has two inputs and one output. Each input goes to two transistors, one p-type transistor and one n-type transistor. The "p" stands for positive and the "n" stands for negative. When the p-type transistor is on it pulls the output up to the same voltage as the voltage source. When the n-type transistor is on it pulls the output down to the same voltage as the ground. The process of creating a p-type transistor begins by "doping" the silicon substrate to create n-type material. This area of n-type material will be called the NWELL layer in our test data. Within the area of NWELL a p-diffusion area is created by further doping the silicon to create p-type material. This area of p-type material will be called PDIFF in our test data. Through the middle of a PDIFF area bars of poly-silicon are grown that create conductive lines over the diffusion area. The area of poly-silicon material will be called POLY in our test data. Under some of these poly-silicon lines a thin layer of silicon-oxide provides insulation but allows the voltage field of the poly-silicon to interact with the diffusion. Each of these insulated poly-silicon lines is the "gate" of a transistor. The gate area will be called GATE in our test data. When the voltage at the gate is the same as the ground voltage the p-type transistor is "on" and can pass current from the voltage source to the output . The poly-silicon lines that are not insulated create electrical connections to the transistor for output signals and source voltage. The n-type transistor differs from the p-type in that its diffusion is n-type material outside of NWELL area. Current can pass from the output to the ground when the voltage at the gate of the n-type transistor is at the source voltage level. Above the poly-silicon layer is a layer of silicon-oxide insulator with holes cut out of it that get filled in with metal. These metal filled holes are called vias and we will refer to this layer as VIA0 in our test data. On top of VIA0 is a layer of metal polygons with silicon oxide insulator between them. These metal polygons are wires and we will call them METAL1 in our test data. The Layout Pins in our test data will be on METAL1. In a NAND gate the two n-type transistors are configured in series, meaning that the output of one is the input voltage source of the other. Only if both n-type transistors of a NAND gate are "on" will the output be connected to ground, signifying a logical "false". The two p-type transistors in a NAND gate are configured in parallel. If either input to the NAND gate is a logical "false" the p-type transistor it is connected to will be "on" and the output of the gate will be a logical "true" because the transistor will connect it to the voltage supply. The diagram below is an example of how a NAND gate might be laid out and is not drawn to scale for any real process technology. The diffusion material is intended to be cut away under the gate material by a Boolean NOT operation and is represented as solid bars under the gates of transistors only for convenience of drawing.
The following is the input layout file for the above NAND gate layout, rectangle format is XL XH YL YH:
Rectangle 0 60 24 48 NWELL
Rectangle 3 57 32 43 PDIFF
Rectangle 3 57 5 16 NDIFF
Rectangle 5 7 0 17 POLY
Rectangle 5 7 22 45 POLY
Rectangle 17 19 3 45 POLY
Rectangle 29 31 31 48 POLY
Rectangle 41 43 3 45 POLY
Rectangle 53 55 3 45 POLY
Rectangle 17 19 4 17 GATE
Rectangle 17 19 31 44 GATE
Rectangle 41 43 4 17 GATE
Rectangle 41 43 31 44 GATE
Rectangle 5 7 0 2 VIA0
Rectangle 5 7 23 25 VIA0
Rectangle 17 19 28 30 VIA0
Rectangle 29 31 46 48 VIA0
Rectangle 41 43 18 20 VIA0
Rectangle 53 55 23 25 VIA0
Rectangle 0 60 0 2 METAL1
Rectangle 3 57 28 30 METAL1
Rectangle 0 60 46 48 METAL1
Rectangle 3 57 18 20 METAL1
Rectangle 3 57 23 25 METAL1
Pin 29 31 0 2 METAL1 GND
Pin 29 31 23 25 METAL1 OUTPUT
Pin 29 31 28 30 METAL1 INPUT1
Pin 29 31 46 48 METAL1 VDD
Pin 29 31 18 20 METAL1 INPUT2
The following is the logic schematic net list file for the above NAND gate schematic:
Pin OUTPUT
Pin INPUT1
Pin INPUT2
Pin VDD
Pin GND
Device PTRANS VDD INPUT1 OUTPUT
Device PTRANS VDD
INPUT2 OUTPUT
Device NTRANS GND INPUT1 NET1
Device NTRANS NET1 INPUT2
OUTPUT
A human can look at this schematic and compare it to the drawn layout of the NAND gate above to verify that the drawn layout matches what the schematic says in a few seconds. If you do that now you will probably find the p and n-type transistors and trace the connectivity of the inputs and power to the terminals of the transistors and then to the output. Since there are on the order of one billion transistors on a single chip these days we need to go a lot faster than humans can inspect layout and make fewer mistakes. Using polygon set operations and polygon connectivity extraction provided by Boost.Polygon we will automate the identification of transistors and the tracing of connectivity. Based on this analysis of Boost.Polygon performance we can expect this methodology to easily scale up to million gate blocks on standard workstations and arbitrarily large designs given sufficient system memory. let's start by implementing some data structures for our application.
struct layout_rectangle {
int xl, yl, xh, yh;
std::string layer;
};
Our layout rectangle is nice and minimal, just enough to store its data. It is defined in layout_rectangle.hpp. Next let's implement the layout pin in a similar way.
struct layout_pin {
int xl, yl, xh, yh;
std::string layer;
std::string net;
};
Our layout pin is defined in layout_pin.hpp. Now let's define a layout database object and populate it from our parsed layout data in in layout_database.hpp.
typedef std::map<std::string,
boost::polygon::polygon_90_set_data<int> > layout_database;
//map the layout rectangle data type to the boost::polygon::rectangle_concept
namespace boost { namespace polygon{
template <>
struct rectangle_traits<layout_rectangle> {
typedef int coordinate_type;
typedef interval_data<int> interval_type;
static inline interval_type get(const layout_rectangle&
rectangle, orientation_2d orient) {
if(orient == HORIZONTAL)
return interval_type(rectangle.xl,
rectangle.xh);
return interval_type(rectangle.yl, rectangle.yh);
}
};
template <>
struct geometry_concept<layout_rectangle> { typedef rectangle_concept
type; };
}}
//insert layout rectangles into a layout database
inline void populate_layout_database(layout_database& layout, std::vector<layout_rectangle>&
rects) {
for(std::size_t i = 0; i < rects.size(); ++i) {
layout[rects[i].layer].insert(rects[i]);
}
}
We don't need to insert pins into the layout database because it doesn't know anything about connectivity, just geometry. However, we do need to know something about connectivity to compare a schematic to a layout, so we need to define our connectivity database and some logical objects. First we define an object for a logical device in device.hpp. Since we are lazy this object does double duty as a pin and both types of transistor. A traditional object oriented design might declare a base class with virtual destructor and derive every device from that. Since we aren't paid by the line of code let's just keep things simple.
struct device {
std::string type;
std::vector<std::string> terminals;
};
Now let's define a schematic database object in schematic_database.hpp and populate it from our parsed schematic data.
struct schematic_database{
std::vector<device> devices;
std::map<std::string, std::set<std::size_t> > nets;
};
//given a vector of devices populate the map of net name to set of device index
inline void extract_netlist(std::map<std::string, std::set<std::size_t> >& nets,
std::vector<device>& devices) {
for(std::size_t i = 0; i < devices.size(); ++i) {
for(std::size_t j = 0; j < devices[i].terminals.size(); ++j)
{
//create association between net name and device
id
nets[devices[i].terminals[j]].insert(nets[devices[i].terminals[j]].end(), i);
}
}
}
Our schematic database is just a vector of devices, which are associated to nets by name through their terminals and a map of net name to set of device index into the vector, which completes the graph by associating nets with their devices. Given the devices and their terminal nets we easily build the mapping from nets to devices with the extract_netlist operation. Now we are ready to start working on extracting our layout to a derived schematic database. However, first we need to build a physical connectivity database with geometry in it before we can build a logical connectivity database from the layout. We define a simple connectivity database in connectivity_database.hpp as a map of net name to layout database of geometry connected to that net and populate it with the layout database and pin data.
typedef std::map<std::string,
layout_database > connectivity_database;
//map layout pin data type to boost::polygon::rectangle_concept
namespace boost { namespace polygon{
template <>
struct rectangle_traits<layout_pin> {
typedef int coordinate_type;
typedef interval_data<int> interval_type;
static inline interval_type get(const layout_pin& pin,
orientation_2d orient) {
if(orient == HORIZONTAL)
return interval_type(pin.xl, pin.xh);
return interval_type(pin.yl, pin.yh);
}
};
template <>
struct geometry_concept<layout_pin> { typedef rectangle_concept type; };
}}
//given a layout_database we populate a
connectivity database
inline void populate_connectivity_database(connectivity_database& connectivity,
std::vector<layout_pin>& pins, layout_database& layout) {
using namespace boost::polygon;
using namespace boost::polygon::operators;
for(std::size_t i = 0; i < pins.size(); ++i) {
connectivity[pins[i].net][pins[i].layer].insert(pins[i]);
}
int internal_net_suffix = 0;
//connect metal1 layout to pins which were on metal1
connect_layout_to_layer(connectivity, layout["METAL1"], "METAL1",
"METAL1", "__internal_net_", internal_net_suffix);
//connect via0 layout to metal1
connect_layout_to_layer(connectivity, layout["VIA0"], "VIA0",
"METAL1", "__internal_net_", internal_net_suffix);
//poly needs to have gates subtracted from it to prevent shorting through
transistors
polygon_set poly_not_gate = layout["POLY"] - layout["GATE"];
//connect poly minus gate to via0
connect_layout_to_layer(connectivity, poly_not_gate, "POLY",
"VIA0", "__internal_net_", internal_net_suffix);
//we don't want to short signals through transistors so we subtract the
gate regions
//from the diffusions
polygon_set diff_not_gate = (layout["PDIFF"] + layout["NDIFF"]) -
layout["GATE"];
//connect diffusion minus gate to poly
//Note that I made up the DIFF layer name for combined P and NDIFF
connect_layout_to_layer(connectivity, diff_not_gate, "DIFF",
"POLY", "__internal_net_", internal_net_suffix);
//connect gate to poly to make connections through gates on poly
connect_layout_to_layer(connectivity, layout["GATE"], "GATE",
"POLY", "__internal_net_", internal_net_suffix);
//now we have traced connectivity of the layout down to the transistor
level
//any polygons not connected to pins have been assigned internal net
names
}
This populate connectivity database function is our first real use of Boost.Polygon in our application. Here we are doing Boolean (polygon set) operations on layout layers to merge together the PDIFF and NDIFF layers and cut away the GATE layer from the result, for example. We connect up the layout starting from the pins and working our way down the layer stack to the transistor level. It would work equally well to work our way up the layer stack, or connect things up in any order, really, but this way produces fewer internal temporary nets that need to be merged when connections between them are discovered later. The connect layout to layer function used above needs to be implemented before we can populate our connectivity database.
inline void
connect_layout_to_layer(connectivity_database& connectivity, polygon_set&
layout,
std::string layout_layer, std::string layer,
std::string net_prefix, int& net_suffix) {
if(layout_layer.empty())
return;
boost::polygon::connectivity_extraction_90<int> ce;
std::vector<std::string> net_ids;
for(connectivity_database::iterator itr = connectivity.begin(); itr !=
connectivity.end(); ++itr) {
net_ids.push_back((*itr).first);
ce.insert((*itr).second[layer]);
}
std::vector<polygon> polygons;
layout.get_polygons(polygons);
std::size_t polygon_id_offset = net_ids.size();
for(std::size_t i = 0; i < polygons.size(); ++i) {
ce.insert(polygons[i]);
}
std::vector<std::set<int> > graph(polygons.size() + net_ids.size(),
std::set<int>());
ce.extract(graph);
std::vector<int> polygon_color(polygons.size() + net_ids.size(), 0);
//for each net in net_ids populate connected component with net
for(std::size_t node_id = 0; node_id < net_ids.size(); ++node_id) {
populate_connected_component(connectivity, polygons,
polygon_color, graph, node_id,
polygon_id_offset, net_ids[node_id], net_ids,
net_prefix, layout_layer);
}
//for each polygon_color that is zero populate connected component with
net_prefix + net_suffix++
for(std::size_t i = 0; i < polygons.size(); ++i) {
if(polygon_color[i + polygon_id_offset] == 0) {
std::stringstream ss(std::stringstream::in |
std::stringstream::out);
ss << net_prefix << net_suffix++;
std::string internal_net;
ss >> internal_net;
populate_connected_component(connectivity,
polygons, polygon_color, graph,
i + polygon_id_offset,
polygon_id_offset, internal_net, net_ids,
net_prefix, layout_layer);
}
}
}
The connect layout to layer function uses the connectivity extraction feature of Boost.Polyon to build a connectivity graph for polygons on the input polygon set and in the connectivity database on the specified layer. It then finds polygons associated with existing nets in the connectivity database through graph traversal and inserts them into the connectivity database. Finally, polygons that weren't connected to existing nets are inserted into the connectivity database on auto-generated internal net names. The insertion of a connected component into the connectivity database is handled by the recursive traversal of the connectivity graph that we implement next.
inline void populate_connected_component
(connectivity_database& connectivity, std::vector<polygon>& polygons,
std::vector<int> polygon_color, std::vector<std::set<int> >& graph,
std::size_t node_id, std::size_t polygon_id_offset, std::string& net,
std::vector<std::string>& net_ids, std::string net_prefix,
std::string& layout_layer) {
if(polygon_color[node_id] == 1)
return;
polygon_color[node_id] = 1;
if(node_id < polygon_id_offset && net_ids[node_id] != net) {
//merge nets in connectivity database
//if one of the nets is internal net merge it into the other
std::string net1 = net_ids[node_id];
std::string net2 = net;
if(net.compare(0, net_prefix.length(), net_prefix) == 0) {
net = net1;
std::swap(net1, net2);
} else {
net_ids[node_id] = net;
}
connectivity_database::iterator itr =
connectivity.find(net1);
if(itr != connectivity.end()) {
for(layout_database::iterator itr2 = (*itr).second.begin();
itr2 != (*itr).second.end();
++itr2) {
connectivity[net2][(*itr2).first].insert((*itr2).second);
}
connectivity.erase(itr);
}
}
if(node_id >= polygon_id_offset)
connectivity[net][layout_layer].insert(polygons[node_id -
polygon_id_offset]);
for(std::set<int>::iterator itr = graph[node_id].begin();
itr != graph[node_id].end(); ++itr) {
populate_connected_component(connectivity, polygons,
polygon_color, graph,
*itr, polygon_id_offset, net, net_ids, net_prefix,
layout_layer);
}
}
We want to merge internally generated nets into pin nets, which is the
most complicated part of this simple procedure. Now that we have our
connectivity database extracted from pins down to transistors we need to extract
our transistors and establish the relationship between transistor terminals and
nets in our connectivity database. First let's extract transistors with
the functions defined in defined in
extract_devices.hpp.
typedef boost::polygon::connectivity_extraction_90<int>
connectivity_extraction;
inline std::vector<std::set<int> >
extract_layer(connectivity_extraction& ce, std::vector<std::string>& net_ids,
connectivity_database& connectivity, polygon_set& layout,
std::string layer) {
for(connectivity_database::iterator itr = connectivity.begin(); itr !=
connectivity.end(); ++itr) {
net_ids.push_back((*itr).first);
ce.insert((*itr).second[layer]);
}
std::vector<polygon> polygons;
layout.get_polygons(polygons);
for(std::size_t i = 0; i < polygons.size(); ++i) {
ce.insert(polygons[i]);
}
std::vector<std::set<int> > graph(polygons.size() + net_ids.size(),
std::set<int>());
ce.extract(graph);
return graph;
}
This extract layer algorithm constructs a connectivity graph between polygons in the input polygon set and polygons in the given layer of the connectivity database. It is used to form the association between transistors and their terminal nets in the function for extracting a specific transistor type.
inline void extract_device_type(std::vector<device>&
devices, connectivity_database& connectivity,
polygon_set& layout, std::string type) {
//recall that P and NDIFF were merged into one DIFF layer in the
connectivity database
//find the two nets on the DIFF layer that interact with each transistor
//and then find the net on the poly layer that interacts with each
transistor
boost::polygon::connectivity_extraction_90<int> cediff;
std::vector<std::string> net_ids_diff;
std::vector<std::set<int> > graph_diff =
extract_layer(cediff, net_ids_diff, connectivity, layout,
"DIFF");
boost::polygon::connectivity_extraction_90<int> cepoly;
std::vector<std::string> net_ids_poly;
std::vector<std::set<int> > graph_poly =
extract_layer(cepoly, net_ids_poly, connectivity, layout,
"POLY");
std::vector<device> tmp_devices(graph_diff.size() - net_ids_poly.size());
for(std::size_t i = net_ids_poly.size(); i < graph_diff.size(); ++i) {
tmp_devices[i - net_ids_diff.size()].type = type;
tmp_devices[i - net_ids_diff.size()].terminals = std::vector<std::string>(3,
std::string());
std::size_t j = 0;
for(std::set<int>::iterator itr = graph_diff[i].begin();
itr != graph_diff[i].end(); ++itr,
++j) {
if(j == 0) {
tmp_devices[i - net_ids_diff.size()].terminals[0]
= net_ids_diff[*itr];
} else if(j == 1) {
tmp_devices[i - net_ids_diff.size()].terminals[2]
= net_ids_diff[*itr];
} else {
//error, too many diff connections
tmp_devices[i - net_ids_diff.size()].terminals
= std::vector<std::string>(3, std::string());
}
}
j = 0;
for(std::set<int>::iterator itr = graph_poly[i].begin();
itr != graph_poly[i].end(); ++itr,
++j) {
if(j == 0) {
tmp_devices[i - net_ids_diff.size()].terminals[1]
= net_ids_poly[*itr];
} else {
//error, too many poly connections
tmp_devices[i - net_ids_poly.size()].terminals
= std::vector<std::string>(3, std::string());
}
}
}
devices.insert(devices.end(), tmp_devices.begin(), tmp_devices.end());
}
We append transistors onto the vector of devices with their terminals
populated with net names extracted from the connectivity database.
Transistors' terminals are connected through the POLY and DIFF layers where DIFF
contains both PDIFF and NDIFF. The connection to POLY layer is the gate of
the transistor while the connections to DIFF on either side of the channel of
the transistor are the source and drain. We can use this to extract are p
and n-type transistors.
//populates vector of devices based on connectivity and layout data
inline void extract_devices(std::vector<device>& devices, connectivity_database&
connectivity,
layout_database& layout) {
using namespace boost::polygon::operators;
//p-type transistors are gate that interact with p diffusion and nwell
polygon_set ptransistors = layout["GATE"];
ptransistors.interact(layout["PDIFF"]);
ptransistors.interact(layout["NWELL"]);
//n-type transistors are gate that interact with n diffusion and not
nwell
polygon_set ntransistors = layout["GATE"];
ntransistors.interact(layout["NDIFF"]);
polygon_set not_ntransistors = ntransistors;
not_ntransistors.interact(layout["NWELL"]);
ntransistors -= not_ntransistors;
extract_device_type(devices, connectivity, ptransistors, "PTRANS");
extract_device_type(devices, connectivity, ntransistors, "NTRANS");
}
The extract devices procedure makes some more use of Boost.Polygon Boolean operations on the layout data when we exclude GATE material over NDIFF that isn't also over NWELL to extract our n-type transistors. We also are using the "interact" operation on polygon gets, which is implemented in terms of connectivity extraction and retains all polygons of a polygon set that touch or overlap polygons from another polygon set. Now that we have a vector of devices we can build a schematic database by calling the extract_netlist function. We can then compare the extracted schematic from the schematic read in from file with the functions defined in compare_schematics.hpp. Since comparing two schematics has no geometric aspect we won't go into that procedure here in the tutorial and will skip to the integration of all these procedures in defined in extract.cpp to build the layout to schematic comparison algorithm.
bool compare_files(std::string layout_file,
std::string schematic_file) {
std::ifstream sin(schematic_file.c_str());
std::ifstream lin(layout_file.c_str());
std::vector<layout_rectangle> rects;
std::vector<layout_pin> pins;
parse_layout(rects, pins, lin);
schematic_database reference_schematic;
parse_schematic_database(reference_schematic, sin);
layout_database layout;
populate_layout_database(layout, rects);
connectivity_database connectivity;
populate_connectivity_database(connectivity, pins, layout);
schematic_database schematic;
std::vector<device>& devices = schematic.devices;
for(std::size_t i = 0; i < pins.size(); ++i) {
devices.push_back(device());
devices.back().type = "PIN";
devices.back().terminals.push_back(pins[i].net);
}
extract_devices(devices, connectivity, layout);
extract_netlist(schematic.nets, devices);
return compare_schematics(reference_schematic, schematic);
}
int main(int argc, char **argv) {
if(argc < 3) {
std::cout << "usage: " << argv[0] << " <layout_file> <schematic_file>"
<< std::endl;
return -1;
}
bool result = compare_files(argv[1], argv[2]);
if(result == false) {
std::cout << "Layout does not match schematic." << std::endl;
return 1;
}
std::cout << "Layout does match schematic." << std::endl;
return 0;
}
We test the program with two schematics and three layouts. These
include a nand and a nor gate layout and schematic as well as an incorrect nand
gate layout. The nand layout and schematic are the same as shown above.
> lvs
usage: lvs <layout_file> <schematic_file>
> lvs nand.layout nand.schematic
Layout does match schematic.
> lvs nand_short.layout nand.schematic
Layout does not match schematic.
> lvs nand.layout nor.schematic
Layout does not match schematic.
> lvs nor.layout nor.schematic
Layout does match schematic.
> lvs nor.layout nand.schematic
Layout does not match schematic.
This concludes our tutorial on how to build a simple layout to schematic verification application based on Boost.Polygon library capabilities. The implementation of this application made many simplifying assumptions that are not valid in the real world and hard coded a lot of things that need to be configurable in a real layout verification application. However, it does give an idea of how to use Boost.Polygon to solve real problems and points in the direction of how a real application might use Boost.Polygon.
| Copyright: | Copyright © Intel Corporation 2008-2010. |
|---|---|
| License: | Distributed under the Boost Software License, Version 1.0. (See accompanying file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt) |


Papavi tricks government
Interesting details are emerging about how Charles Kormi Kudzordzi, also known as Papavi, has applied an assortment of tricks to push his so-called Western Togoland agenda.
When he was arrested alongside some members of the Home Study Group Foundation (HSGF) and airlifted to Accra, he cut the picture of a frail old man hardly able to walk and relying heavily on a walking stick.
Many people, who saw him, exhibited empathy for a Papavi when he disembarked the chopper and was taken to the security agents for processing.
Eventually, Papavi had the charges levelled against him dropped by the Attorney General on humanitarian grounds.
No Money
DAILY GUIDE learnt that even when he was released, he was unable to return home on his own; the state had to provide a vehicle to drive him back home in the Volta Region where he was picked up.
He was said to have been given some undisclosed largesse to take care of himself only for him to regroup and start his treasonable acts all over again.
Walking Stick
His latest trick was the one he unfurled in Ho when he declared a so-called independence for Western Togoland.
“Here was a Papavi full of life without a walking stick, standing erect reading his statement to accompany the independence declaration,”a security source said.
Funeral Decoy
The source said Papavi and his men pretended to be organizing a funeral activity and his sympathizers donning the characteristic mourning colours of red and black in the course of the treasonable declaration.
“He hoodwinked the security agents into believing that the activity was really a funeral programme. It was after the declaration that they discovered how they had been fooled.
“His different postures continue to be downloaded on social media following his declaration.
Trickery Traits
There is a school of thought that has downgraded the threat of Papavi referring to him as a trickster who thinks he can make some money from the state through ‘negotiations’.
Some of his followers have fallen for his tricks as evidenced from a so-called military training they are undergoing in the hands of a lone soldier, Staff Sgt. Samuel Kpogli, who has already been arrested.
Daily Guide has learnt that when the Papavi ‘recruits’ report for the military training they are passed out after a few days, the soldier himself making some money for himself.
‘Presidential’ Broadcast
In an audio, Papavi told security agents that he was in the country and would not present himself to the security agents because he did not know what they would do with him.
Wife Arrested
He said in the audio that his close to 70-year-old wife was arrested and locked up, something which has been disputed by a security source.
According to the source, the woman was only questioned about the whereabouts of her husband and was never detained.
In the video which has gone viral, he described himself as the man who brought about the idea of freedom for “our land and this we have been doing for some time now.
“Last Saturday, it came to pass that a declaration was staged. Yes, we mean it. And that I am appealing to all of you, everyone to be peaceful. No declaration is staged without quarrel. It is always so. But we want to set the record for peace to prevail so that the whole world knows that we are peace-loving.”
He continued, “I am asking all kings, queens to advise their people, subordinates, subjects here and there to be peaceful. The youth should advise one another to be peaceful.”
Arrest Stories
He advised the government that “what has started happening is not the right thing. Going round arresting people in the streets, taking them and locking them up in cells, and also going to houses of every individual particularly mine and taking my near 70 years old wife and locking her up because the husband talking on the freedom of a country. No, that is not the right thing.”
He said “I have been arrested for a number of times (2017), and the very government of this country said she was no longer interested in the matter and was discharged. It came again when I spoke in 2019. I was taken to court a number of times and the government repeated the same thing. I think government is looking for peace. If now after government is not interested in the matter and I’m discharged together with those arrested with me yet the police insist that we should keep reporting to them, we did for more than several times, and it stopped somewhere (sic).”
Negotiation Bait
“If with this declaration we are being pursued again, I am asking government that if government feels that I should come back for the case to continue they are free to do so through my lawyers and I will present myself; but to look for me, I don’t know the reason, take me somewhere, I don’t know what they are going to do with me. Human as I am, I will not present myself; I am in the country anyway. I have not travelled (hidden) anywhere.”
Showing Maturity
Papavi said, “But I want the government to show maturity. Invite me legally through my lawyers and I will present myself for the case to continue. Please let us do justice.”
“Again, I am appealing to the international world, those in the corridors of peace, Amnesty International and all the groups we know, to come in to put the situation under control to avoid any possible mayhem,” he added.


BLKID
Section: MAINTENANCE COMMANDS (8)Updated: February 2009
Index Return to Main Contents
NAME
blkid - command-line utility to locate/print block device attributesSYNOPSIS
blkid -L label | -U uuidblkid [-ghlv] [-c file] [-w file] [-o format] [-s tag] [-t NAME=value] device [device ...]
blkid -p [-O offset] [-S size] [-o format] [-s tag] [-u list] device [device ...]
blkid -i [-o format] [-s tag] device [device ...]
DESCRIPTION
The blkid program is the command-line interface to working with libblkid(3) library. It can determine the type of content (e.g. filesystem, swap) a block device holds, and also attributes (tokens, NAME=value pairs) from the content metadata (e.g. LABEL or UUID fields).blkid has two main forms of operation: either searching for a device with a specific NAME=value pair, or displaying NAME=value pairs for one or more devices.
OPTIONS
- -c cachefile
- Read from cachefile instead of reading from the default cache file /etc/blkid/blkid.tab. If you want to start with a clean cache (i.e. don't report devices previously scanned but not necessarily available at this time), specify /dev/null.
- -g
- Perform a garbage collection pass on the blkid cache to remove devices which no longer exist.
- -h
- Display a usage message and exit.
- -i
- Display I/O Limits (aka I/O topology) information. The 'export' output format is automatically enabled. This option could be used together with -p option.
- -l
- Look up one device that matches the search parameter specified using the -t option. If there are multiple devices that match the specified search parameter, then the device with the highest priority is returned, and/or the first device found at a given priority. Device types in order of decreasing priority are Device Mapper, EVMS, LVM, MD, and finally regular block devices. If this option is not specified, blkid will print all of the devices that match the search parameter.
- -L label
-
Look up one device that uses the label (same as: -l -o device -t
LABEL=<label>). This look up method is able to reliable use /dev/disk/by-label
udev symlinks (depends on setting in /etc/blkid.conf). Avoid to use the
symlinks directly. It is not reliable to use the symlinks without verification.
The -L option works on systems with and without udev.
Unfortunately, the original blkid(8) from e2fsprogs use the -L option as a synonym to the -o list option. For better portability use "-l -o device -t LABEL=<label>" and "-o list" in your scripts rather than -L option.
- -u list
-
Restrict probing functions to defined (comma separated) list of "usage" types.
Supported usage types are: filesystem, raid, crypto and other. The list can be
prefixed with "no" to specify the usage types which should be ignored. For example:
blkid -p -u filesystem,other /dev/sda1probes for all filesystems and others (e.g. swap) formats, and
blkid -p -u noraid /dev/sda1probes for all supported formats exclude RAIDs. This option is useful with -p only.
- -U uuid
- Look up one device that uses the uuid. For more details see the -L option.
- -o format
-
Display
blkid's
output using the specified format. The
format
parameter may be:
-
- full
- print all tags (the default)
- value
- print the value of the tags
- list
- print the devices in a user-friendly format, this output format is unsupported for low-level probing (-p or -i)
- device
- print the device name only, this output format is always enabled for -L and -U options
- udev
- print key="value" pairs for easy import into the udev environment
- export
- print key=value pairs for easy import into the environment. This output format is automatically enabled when I/O Limits (-i option) are requested.
-
- -O bytes
- Probe at the given offset (only useful with -p). This option could be used together with -i option.
- -p
- Switch to low-level superblock probing mode (bypass cache).
- -s tag
- For each (specified) device, show only the tags that match tag. It is possible to specify multiple -s options. If no tag is specified, then all tokens are shown for all (specified) devices. In order to just refresh the cache without showing any tokens, use -s none with no other options.
- -S bytes
- Overwrite device/file size (only useful with -p).
- -t NAME=value
- Search for block devices with tokens named NAME that have the value value, and display any devices which are found. Common values for NAME include TYPE, LABEL, and UUID. If there are no devices specified on the command line, all block devices will be searched; otherwise only the specified devices are searched.
- -v
- Display version number and exit.
- -w writecachefile
- Write the device cache to writecachefile instead of writing it to the default cache file /etc/blkid/blkid.tab. If you don't want to save the cache to the default file, specify /dev/null. If not specified it will be the same file as that given by the -c option.
- device
- Display tokens from only the specified device. It is possible to give multiple device options on the command line. If none is given, all devices which appear in /proc/partitions are shown, if they are recognized.
RETURN CODE
If the specified token was found, or if any tags were shown from (specified) devices, 0 is returned. If the specified token was not found, or no (specified) devices could be identified, an exit code of 2 is returned. For usage or other errors, an exit code of 4 is returned.AUTHOR
blkid was written by Andreas Dilger for libblkid and improved by Theodore Ts'o and Karel Zak.AVAILABILITY
The blkid command is part of the util-linux-ng package and is available from ftp://ftp.kernel.org/pub/linux/utils/util-linux-ng/.SEE ALSO
libblkid(3) findfs(8) wipefs(8)
Index
This document was created by man2html, using the manual pages.
Time: 05:34:24 GMT, December 24, 2015


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SEA Games 2019: Football full schedule, live stream, when and where to watch, squad, timing in PDF
by HarigovindThe 2019 Southeast Asian Games (SEA Games) – which will be the 30th edition of the biennial multi-sport event involving Southeast Asian nations, will be hosted by the Philippines from 30 November 2019 to 11 December 2019.
Needless to say, Football will be one of the games which will garner the most attention from fans, as most of the Southeast Asian hotshots – including Malaysia, Vietnam, Thailand and so on – will be participating in the tournament.
It has been understood that Football at the 2019 SEA Games is scheduled to be held between 25 November 2019 and 10 December 2019. The men’s tournament will be held from 25 November to 10 December, while the women’s tournament will begin on 26 November and end on 8 December.
Take a look at the schedule for both the Men’s Football Tournament and the Women’s Football Tournament, right here:
Football at the 2019 SEA Games – Men’s Tournament
25 November 2019
Group A
Malaysia v Myanmar, Rizal Memorial Stadium, Manila (4:00 pm local time)
Philippines v Cambodia, Rizal Memorial Stadium, Manila (8:00 pm local time)
Group B
Vietnam v Brunei, Imus Grandstand and Track Oval, Imus (4:00 pm local time)
26 November 2019
Group B
Thailand v Indonesia, Rizal Memorial Stadium, Manila (4:00 pm local time)
Laos v Singapore, Rizal Memorial Stadium, Manila (8:00 pm local time)
27 November 2019
Group A
Myanmar v Philippines, Rizal Memorial Stadium, Manila (4:00 pm local time)
Cambodia v Timor-Leste, Rizal Memorial Stadium, Manila (8:00 pm local time)
28 November 2019
Group B
Vietnam v Laos, Binan Football Stadium, Binan (4:00 pm local time)
Brunei v Thailand, Rizal Memorial Stadium, Manila (4:00 pm local time)
Indonesia v Singapore, Rizal Memorial Stadium, Manila (8:00 pm local time)
29 November 2019
Group A
Timor-Leste v Myanmar, Rizal Memorial Stadium, Manila (4:00 pm local time)
Philippines v Malaysia, Rizal Memorial Stadium, Manila (8:00 pm local time)
1 December 2019
Group B
Thailand v Singapore, Binan Football Stadium, Binan (4:00 pm local time)
Laos v Brunei, Rizal Memorial Stadium, Manila (4:00 pm local time)
Vietnam v Indonesia, Rizal Memorial Stadium, Manila (8:00 pm local time)
2 December 2019
Group A
Malaysia v Timor-Leste, Rizal Memorial Stadium, Manila (8:00 pm local time)
Myanmar v Cambodia, Binan Football Stadium, Binan (8:00 pm local time)
3 December 2019
Group B
Indonesia v Brunei, Binan Football Stadium, Binan (8:00 pm local time)
Laos v Thailand, Rizal Memorial Stadium, Manila (4:00 pm local time)
Singapore v Vietnam, Rizal Memorial Stadium, Manila (8:00 pm local time)
4 December 2019
Group A
Cambodia v Malaysia, Rizal Memorial Stadium, Manila (4:00 pm local time)
Timor-Leste v Philippines, Binan Football Stadium, Binan (4:00 pm local time)
5 December 2019
Group B
Brunei v Singapore, Rizal Memorial Stadium, Manila (4:00 pm local time)
Indonesia v Laos, Imus Grandstand and Track Oval, Imus (4:00 pm local time)
Vietnam v Thailand, Binan Football Stadium, Binan (4:00 pm local time)
7 December 2019
Semi-finals 1, Rizal Memorial Stadium, Manila (4:00 pm local time)
Semi-finals 2, Rizal Memorial Stadium, Manila (8:00 pm local time)
10 December 2019
Bronze-medal match, Rizal Memorial Stadium, Manila (4:00 pm local time)
Gold-medal match, Rizal Memorial Stadium, Manila (8:00 pm local time)
Football at the 2019 SEA Games – Women’s Tournament
26 November 2019
Group A
Philippines v Myanmar, Binan Football Stadium, Binan (4:00 pm local time)
Group B
Vietnam v Thailand, Binan Football Stadium, Binan (8:00 pm local time)
29 November 2019
Group A
Malaysia v Philippines, Binan Football Stadium, Binan (4:00 pm local time)
Group B
Indonesia v Vietnam, Binan Football Stadium, Binan (8:00 pm local time)
2 December 2019
Group A
Myanmar v Malaysia, Binan Football Stadium, Binan (4:00 pm local time)
Group B
Thailand v Indonesia, Rizal Memorial Stadium, Manila (4:00 pm local time)
5 December 2019
Semi-finals 1, Winner Group A v Runner-up Group B, Rizal Memorial Stadium, Manila (8:00 pm local time)
Semi-finals 2, Winner Group B v Runner-up Group A, Binan Football Stadium, Binan (8:00 pm local time)
8 December 2019
Bronze-medal match, Semi-finals 1 Loser v Semi-finals 2 Loser, Rizal Memorial Stadium, Manila (4:00 pm local time)
Gold-medal match, Semi-finals 1 Winner v Semi-finals 2 Winner, Rizal Memorial Stadium, Manila (8:00 pm local time)


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Churchill Dam starts to overflow
by Algoa FMThe Churchill Dam in Nelson Mandela Bay's catchment area is overflowing, following the good rain that fell in the Kareedouw area last week.
Spokesperson for the SA Weather Service in Port Elizabeth, Garth Sampson says some follow-up rain fell overnight on Saturday into Sunday along the coast and the adjacent interior, with between 7 and 16 mm in Port Elizabeth, 2.6 mm in Kareedouw, 8.4 mm at Patensie, but nothing at Joubertina.
He says he visited the Churchill Dam on Sunday, and it was overflowing.
Sampson says the dam's official level was at 100.21 percent, and this overflowing water will gradually run into the Impofu Dam, which is currently at 16 percent of capacity.
He added, however, that this overflow was very slight and there was not much water running to the Impofu.
Sampson says the drought is by no means broken, and water should still be used sparingly.
He says no rain is expected in the Bay's catchment area for the next week.
(Pic: Garth Sampson - SAWS)


A quick-fix is suggested to rename the variable.
Example:
class Pointless {
Point p = new Point();
public void test(Object a) {
if (a instanceof Point p) {
System.out.print("a is a point (" + p.x + ", " + p.y + ')');
} else {
System.out.print("p is a point (" + p.x + ", " + p.y + ')');
}
}
}
New in 2022.2


new SVGController(SVGPanelName) → {PJP.SVGController}
SVG diagram viewer. It will also add callbacks to the svg elements and other controls
such as zooming and translation on mouse interactions.
Parameters:
| Name | Type | Description |
|---|---|---|
SVGPanelName |
String | Id of the target element for this PJP.SVGController to control. |
- Source:
Returns:
- Type
- PJP.SVGController
Methods
loadSVG(svgName)
Display svg diagram with the matching svgName name.
Parameters:
| Name | Type | Description |
|---|---|---|
svgName |
String | name of the svg. |
- Source:
zoomIn()
Increase zooming of the svg diagram by the given ratio.
- Source:
zoomOut()
Decrease zooming of the svg diagram by the given ratio.
- Source:
zoomReset()
Reset the zoom to 100%;
- Source:
(async, inner) svgLoaded()
SVG diagram has been loaded, add svg callbacks and actions.
- Source:


Preparation time
less than 30 mins
Cooking time
10 to 30 mins
Serves
Serves 4
Chilli con carne is a spicy Mexican-style stew. This recipe is cooked completely in the microwave – and that includes cooking the rice.
Peel and finely chop the onion and garlic (press or chop the garlic as small as you can).
Wipe the mushrooms, if using, with kitchen paper to remove any dirt and slice finely.
Open the cans of tomatoes and beans. Drain the kidney beans through a colander and rinse with cold water.
Put the minced beef into the large bowl and add the onion and garlic. Mix together using a fork until the meat is thoroughly broken up.
Cover with a microwaveable lid or cling film, leaving a small area open to allow steam to escape.
Cook in the microwave on full power for five minutes. Remove from the microwave. Peel back the cling film and stir well with the fork, breaking up any clumps of meat.
Add the mushrooms, crumbled stock cube, chilli flakes or powder, tomatoes and beans to the meat and stir well.
Add a small amount of water to the empty tomato can, swirl around and add to the bowl. Season with black pepper to taste, if using.
Re-cover in the same way and cook on full power for five minutes. Remove the bowl and stir well.
Re-cover, return to the microwave and cook on full power for 10 minutes. Remove halfway through and stir well. Leave to stand while you cook the rice.
To cook the rice, boil the kettle. Add the rice to the sieve. Run cold water through the rice until the water runs clear and drain. Pour the rice into the other large microwave-safe bowl. Fill the same mug with boiling water twice and pour over the rice. Stir once and put into the microwave.
Microwave on full power for 10 minutes.
Remove the rice and stir. Return it to the microwave on full power for another minute.
Remove the rice and leave to stand for 1–2 minutes and then taste to check it is cooked. If it needs slightly more cooking add a small amount of water and cook for another two minutes.


Lumenium is a privately held company developing advanced internal combustion ("IC") engine technology. The company’s proprietary, and multi-patented, designs are derived with advanced mathematics and complex geometry but based on elemental shapes, and the simple interaction of concave and convex parts. This combination forms an efficient and compact alternative to piston engines. Lumenium’s core technology escapes the size, weight and cost mandates of traditional IC engines. Lumenium has developed its technology over the course of ten years, creating and testing many generations of running engine models. Lumenium’s numerous patents have issued both domestically and worldwide.
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public interface GpfDsDevice
DsFormattingDevice.getCapParameters(com.gemalto.idp.mobile.core.util.SecureString, com.gemalto.idp.mobile.otp.dsformatting.Template.DomainType, com.gemalto.idp.mobile.otp.dsformatting.DsCapParameters.DsCapMode, com.gemalto.idp.mobile.otp.dsformatting.DsTransactionData)
to perform dynamic signatures via CAP modes.| Modifier and Type | Method and Description |
|---|---|
SecureString |
getCode(AuthInput authInput)
Generates a code.
|
SecureString |
getDynamicSignature(AuthInput authInput,
SecureString challenge,
Template.DomainType domain,
DsTransactionData dsTransactionData)
Generates a dynamic signature.
|
SecureString getCode(AuthInput authInput) throws IdpException
A GpfDs code in practice is identical to a CAP mode2 token (excluding any prefixing of '0's in order to meet the minimum length requirement).
Use
CapTools.prefixSequenceNumberToOtp(com.gemalto.idp.mobile.core.util.SecureString, com.gemalto.idp.mobile.otp.cap.CapToken, int)
to prefix the sequence number.
Use OtpTools.formatOtp(com.gemalto.idp.mobile.otp.util.OtpTools.FormatType, com.gemalto.idp.mobile.core.util.SecureString)
to format
the token.
authInput
- the authentication input.IdpRuntimeException
- when there is a cryptography operation failureIdpException
- this is generic exception, you can directly catch this
exception or catch each specific exception below.IdpStorageException
- when there is a database operation failure.WrappedCounterException
- when the ATC/counter reaches its maximum value.DeviceFingerprintException
- when the token's fingerprint checksum does not match.PasswordManagerException
- when the TOKEN domain is not logged in (using one of the
password managers)IdpAuthException
- when the authentication mode is not supported by the token.SecureString getDynamicSignature(AuthInput authInput, SecureString challenge, Template.DomainType domain, DsTransactionData dsTransactionData) throws IdpException
Use
CapTools.prefixSequenceNumberToOtp(com.gemalto.idp.mobile.core.util.SecureString, com.gemalto.idp.mobile.otp.cap.CapToken, int)
to prefix the sequence number.
Use OtpTools.formatOtp(com.gemalto.idp.mobile.otp.util.OtpTools.FormatType, com.gemalto.idp.mobile.core.util.SecureString)
to format
the token.
authInput
- the authentication input.challenge
- the challenge received from the bank or null
if
the domain operates in connected mode.domain
- the secure domain.dsTransactionData
- the transaction data or null
if there is no
transaction data.IdpRuntimeException
- when there is a cryptography operation failure.IdpException
- this is generic exception, you can directly catch this
exception or catch each specific exception below.IdpStorageException
- when there is a database operation failure.WrappedCounterException
- when the ATC/counter reaches its maximum value.DeviceFingerprintException
- when the token's fingerprint checksum does not match.PasswordManagerException
- when the TOKEN domain is not logged in (using one of the
password managers).IdpAuthException
- when the authentication mode is not supported by the token.


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David Tennant to play serial killer Dennis Nilsen in new ITV drama Des
One of Britain's most notorious murderers
by Georgia LoganDavid Tennant will play a serial killer in new ITV drama Des.
The 48-year-old actor has signed up to portray Dennis Nilsen - who was one of Britain's most notorious killers - in the new three-part series.
Read More: Prince Andrew 'sacked' from royal duties by the Queen
ITV's head of drama, Polly Hill, told The Sun's Bizarre TV column: "This starts with Nilsen's arrest and is looking at him through the eyes of the police officer trying to identify those he killed and deliver justice.
"David Tennant is going to be brilliant as Nilsen and, with Daniel and Jason, this has an incredible cast."
The project will also star Jason Watkins as Brian Masters, who wrote a book on the killer, and Daniel Mays as Detective Chief Inspector Peter Jay.
Read More: I'm A Celebrity's Caitlyn Jenner says all her kids still call her 'dad'
Dennis was a Scottish serial killer who murdered at least twelve young men between 1978 and 1983 in London.
The killings all took place in the two North London addresses in which he resided between 1978 and 1983 and he became known as the Muswell Hill Murderer, as he committed his later murders in the Muswell Hill district of North London.
Read More: Cheryl reveals she's teaching two-year-old son Bear how to meditate
He disposed of his victims by dissecting the bodies and either burning them or flushing them down the toilet.
Nilsen was caught when DCI Jay was called to his home to investigate human remains clogging up the drains.
He was convicted of six counts of murder and two of attempted murder and sentenced to life imprisonment on 4 November 1983.
Read More: EastEnders fans spot 'clue' that Chantelle will murder abuser Gray
He died in prison on 12 May 2018 at the age of 72.
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18 Mar 2015
Another travel site?
Just as I had settled in on Thessaloniki’s lustrous promenade, my peace was disturbed by a scary thought. Staring into the sunset over the bay and puffing on my celebratory cigar I was startled by the question “What if my friends forget about me?”
Before my departure some of my friends had indeed asked for regular status updates on my trip and/or whether my head was still attached to my shoulders (Day 1: yes).
Cleary keeping my friends informed one by one seems like a lot of repetition. It’s likely that I would eventually start neglecting that task and lose touch. I can easily remedy this by putting regular updates online at a central location.
However I don’t really like or trust Facebook anymore, so putting all my stuff on there didn’t exactly appeal to me. The obvious consequence then is a website, something I had discussed with some of my friends as well. Here is the problem though: Since I am now traveling, my site would be a travel site.
I don’t like travel sites.
Whilst preparing for my trip I had skimmed through many travel-related sites.  Most of them seem to consist of listicles (a topic worthy of a rant of its own. Spoiler: I don’t like them.), “me at the beach” type pictures and rather heavy-handed prose. I’m positive that’s not the kind of writing I would want to spend time on. Partially because of my drastic aversion to listicles, partially since I’m way too pale to be photographed at the beach. Lastly, I’m not under the delusion that I’m any kind of Hemingway. So what is this site going to be then? Hopefully not a travel site!
As much as I enjoy traveling, this undertaking was never meant to be about the travel itself. Instead, I wanted to have the freedom and energy to immerse myself in topics I find interesting. I could have gone the formal-education route and lined up for another degree, tuition fees and a set curriculum. Instead I decided to pursue those interests on my own. That way I can spend the money saved at locations which are all a) sunnier, b) cheaper and c) friendlier than my birthplace. And if that’s the idea, why limit myself to one location? There, that’s how it accidentally turned into a trip. So ideally, this site will be mainly be growing on articles on the topics I’m researching (and of course various vitriolic rants).
But despair not, ye of little faith, I will surely write the occasional bit on my whereabouts (and yes, the status of my neck). Prepare for pictures of beaches, wine-glasses and my horribly sun-burned mug. Hell, I might even take a shot at some destination-related articles with a bit of substance.
Since writing here is also a desperate attempt to build some sort of self-discipline, please feel free to give me a friendly nudge between the eyes if I’m getting too lazy.
So let’s start this experiment then, shall we?
Until next time,
Arne