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M4521 BSP V3.01.000
The Board Support Package for M4521
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Macros | |
| #define | SYS ((SYS_T *) GCR_BASE) |
| #define | SYSINT ((SYS_INT_T *) INT_BASE) |
| #define | CLK ((CLK_T *) CLK_BASE) |
| #define | PA ((GPIO_T *) GPIOA_BASE) |
| #define | PB ((GPIO_T *) GPIOB_BASE) |
| #define | PC ((GPIO_T *) GPIOC_BASE) |
| #define | PD ((GPIO_T *) GPIOD_BASE) |
| #define | PE ((GPIO_T *) GPIOE_BASE) |
| #define | PF ((GPIO_T *) GPIOF_BASE) |
| #define | GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE) |
| #define | PDMA ((PDMA_T *) PDMA_BASE) |
| #define | USBH ((USBH_T *) USBH_BASE) |
| #define | FMC ((FMC_T *) FMC_BASE) |
| #define | EBI ((EBI_T *) EBI_BASE) |
| #define | CRC ((CRC_T *) CRC_BASE) |
| #define | WDT ((WDT_T *) WDT_BASE) |
| #define | WWDT ((WWDT_T *) WWDT_BASE) |
| #define | RTC ((RTC_T *) RTC_BASE) |
| #define | EADC ((EADC_T *) EADC0_BASE) |
| #define | USBD ((USBD_T *) USBD_BASE) |
| #define | TIMER0 ((TIMER_T *) TMR01_BASE) |
| #define | TIMER1 ((TIMER_T *) (TMR01_BASE + 0x20)) |
| #define | TIMER2 ((TIMER_T *) TMR23_BASE) |
| #define | TIMER3 ((TIMER_T *) (TMR23_BASE + 0x20)) |
| #define | PWM0 ((PWM_T *) PWM0_BASE) |
| #define | PWM1 ((PWM_T *) PWM1_BASE) |
| #define | SPI0 ((SPI_T *) SPI0_BASE) |
| #define | SPI1 ((SPI_T *) SPI1_BASE) |
| #define | UART0 ((UART_T *) UART0_BASE) |
| #define | UART1 ((UART_T *) UART1_BASE) |
| #define | UART2 ((UART_T *) UART2_BASE) |
| #define | UART3 ((UART_T *) UART3_BASE) |
| #define | I2C0 ((I2C_T *) I2C0_BASE) |
| #define | I2C1 ((I2C_T *) I2C1_BASE) |
| #define | SC0 ((SC_T *) SC0_BASE) |
| #define | BIT0 0x00000001 |
| #define | BIT1 0x00000002 |
| #define | BIT2 0x00000004 |
| #define | BIT3 0x00000008 |
| #define | BIT4 0x00000010 |
| #define | BIT5 0x00000020 |
| #define | BIT6 0x00000040 |
| #define | BIT7 0x00000080 |
| #define | BIT8 0x00000100 |
| #define | BIT9 0x00000200 |
| #define | BIT10 0x00000400 |
| #define | BIT11 0x00000800 |
| #define | BIT12 0x00001000 |
| #define | BIT13 0x00002000 |
| #define | BIT14 0x00004000 |
| #define | BIT15 0x00008000 |
| #define | BIT16 0x00010000 |
| #define | BIT17 0x00020000 |
| #define | BIT18 0x00040000 |
| #define | BIT19 0x00080000 |
| #define | BIT20 0x00100000 |
| #define | BIT21 0x00200000 |
| #define | BIT22 0x00400000 |
| #define | BIT23 0x00800000 |
| #define | BIT24 0x01000000 |
| #define | BIT25 0x02000000 |
| #define | BIT26 0x04000000 |
| #define | BIT27 0x08000000 |
| #define | BIT28 0x10000000 |
| #define | BIT29 0x20000000 |
| #define | BIT30 0x40000000 |
| #define | BIT31 0x80000000 |
| #define | BYTE0_Msk (0x000000FF) |
| #define | BYTE1_Msk (0x0000FF00) |
| #define | BYTE2_Msk (0x00FF0000) |
| #define | BYTE3_Msk (0xFF000000) |
| #define | _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) |
| #define | _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) |
| #define | _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) |
| #define | _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) |
| #define | TRUE 1 |
| #define | FALSE 0 |
| #define | NULL 0 |
| #define | M8(adr) (*((vu8 *) (adr))) |
| #define | M16(adr) (*((vu16 *) (adr))) |
| #define | M32(adr) (*((vu32 *) (adr))) |
| #define | outpw(port, value) (*((volatile unsigned int *)(port))=(value)) |
| #define | inpw(port) (*((volatile unsigned int *)(port))) |
| #define | outpb(port, value) (*((volatile unsigned char *)(port))=(value)) |
| #define | inpb(port) (*((volatile unsigned char *)(port))) |
| #define | outps(port, value) (*((volatile unsigned short *)(port))=(value)) |
| #define | inps(port) (*((volatile unsigned short *)(port))) |
| #define | outp32(port, value) (*((volatile unsigned int *)(port))=(value)) |
| #define | inp32(port) (*((volatile unsigned int *)(port))) |
| #define | outp8(port, value) (*((volatile unsigned char *)(port))=(value)) |
| #define | inp8(port) (*((volatile unsigned char *)(port))) |
| #define | outp16(port, value) (*((volatile unsigned short *)(port))=(value)) |
| #define | inp16(port) (*((volatile unsigned short *)(port))) |
Typedefs | |
| typedef volatile unsigned char | vu8 |
| typedef volatile unsigned long | vu32 |
| typedef volatile unsigned short | vu16 |
Variables | |
| __I uint32_t | EADC_T::DAT [19] |
| __I uint32_t | EADC_T::CURDAT |
| __IO uint32_t | EADC_T::CTL |
| __O uint32_t | EADC_T::SWTRG |
| __IO uint32_t | EADC_T::PENDSTS |
| __IO uint32_t | EADC_T::OVSTS |
| __I uint32_t | EADC_T::RESERVE0 [8] |
| __IO uint32_t | EADC_T::SCTL [19] |
| __I uint32_t | EADC_T::RESERVE1 [1] |
| __IO uint32_t | EADC_T::INTSRC [4] |
| __IO uint32_t | EADC_T::CMP [4] |
| __I uint32_t | EADC_T::STATUS0 |
| __I uint32_t | EADC_T::STATUS1 |
| __IO uint32_t | EADC_T::STATUS2 |
| __I uint32_t | EADC_T::STATUS3 |
| __I uint32_t | EADC_T::DDAT [4] |
| __IO uint32_t | CLK_T::PWRCTL |
| __IO uint32_t | CLK_T::AHBCLK |
| __IO uint32_t | CLK_T::APBCLK0 |
| __IO uint32_t | CLK_T::APBCLK1 |
| __IO uint32_t | CLK_T::CLKSEL0 |
| __IO uint32_t | CLK_T::CLKSEL1 |
| __IO uint32_t | CLK_T::CLKSEL2 |
| __IO uint32_t | CLK_T::CLKSEL3 |
| __IO uint32_t | CLK_T::CLKDIV0 |
| __IO uint32_t | CLK_T::CLKDIV1 |
| __I uint32_t | CLK_T::RESERVE0 [6] |
| __IO uint32_t | CLK_T::PLLCTL |
| __I uint32_t | CLK_T::RESERVE1 [3] |
| __I uint32_t | CLK_T::STATUS |
| __I uint32_t | CLK_T::RESERVE2 [3] |
| __IO uint32_t | CLK_T::CLKOCTL |
| __I uint32_t | CLK_T::RESERVE3 [3] |
| __IO uint32_t | CLK_T::CLKDCTL |
| __IO uint32_t | CLK_T::CLKDSTS |
| __IO uint32_t | CLK_T::CDUPB |
| __IO uint32_t | CLK_T::CDLOWB |
| __IO uint32_t | CRC_T::CTL |
| __IO uint32_t | CRC_T::DAT |
| __IO uint32_t | CRC_T::SEED |
| __I uint32_t | CRC_T::CHECKSUM |
| __IO uint32_t | EBI_T::CTL0 |
| __IO uint32_t | EBI_T::TCTL0 |
| __I uint32_t | EBI_T::RESERVE0 [2] |
| __IO uint32_t | EBI_T::CTL1 |
| __IO uint32_t | EBI_T::TCTL1 |
| __IO uint32_t | FMC_T::ISPCTL |
| __IO uint32_t | FMC_T::ISPADDR |
| __IO uint32_t | FMC_T::ISPDAT |
| __IO uint32_t | FMC_T::ISPCMD |
| __IO uint32_t | FMC_T::ISPTRG |
| __I uint32_t | FMC_T::DFBA |
| __IO uint32_t | FMC_T::FTCTL |
| __I uint32_t | FMC_T::RESERVE0 [9] |
| __IO uint32_t | FMC_T::ISPSTS |
| __I uint32_t | FMC_T::RESERVE1 [15] |
| __IO uint32_t | FMC_T::MPDAT0 |
| __IO uint32_t | FMC_T::MPDAT1 |
| __IO uint32_t | FMC_T::MPDAT2 |
| __IO uint32_t | FMC_T::MPDAT3 |
| __I uint32_t | FMC_T::RESERVE2 [12] |
| __I uint32_t | FMC_T::MPSTS |
| __I uint32_t | FMC_T::MPADDR |
| __IO uint32_t | GPIO_T::MODE |
| __IO uint32_t | GPIO_T::DINOFF |
| __IO uint32_t | GPIO_T::DOUT |
| __IO uint32_t | GPIO_T::DATMSK |
| __I uint32_t | GPIO_T::PIN |
| __IO uint32_t | GPIO_T::DBEN |
| __IO uint32_t | GPIO_T::INTTYPE |
| __IO uint32_t | GPIO_T::INTEN |
| __IO uint32_t | GPIO_T::INTSRC |
| __IO uint32_t | GPIO_T::SMTEN |
| __IO uint32_t | GPIO_T::SLEWCTL |
| __IO uint32_t | GPIO_T::DRVCTL |
| __IO uint32_t | GPIO_DBCTL_T::DBCTL |
| __IO uint32_t | I2C_T::CTL |
| __IO uint32_t | I2C_T::ADDR0 |
| __IO uint32_t | I2C_T::DAT |
| __I uint32_t | I2C_T::STATUS |
| __IO uint32_t | I2C_T::CLKDIV |
| __IO uint32_t | I2C_T::TOCTL |
| __IO uint32_t | I2C_T::ADDR1 |
| __IO uint32_t | I2C_T::ADDR2 |
| __IO uint32_t | I2C_T::ADDR3 |
| __IO uint32_t | I2C_T::ADDRMSK0 |
| __IO uint32_t | I2C_T::ADDRMSK1 |
| __IO uint32_t | I2C_T::ADDRMSK2 |
| __IO uint32_t | I2C_T::ADDRMSK3 |
| __I uint32_t | I2C_T::RESERVE0 [2] |
| __IO uint32_t | I2C_T::WKCTL |
| __IO uint32_t | I2C_T::WKSTS |
| __IO uint32_t | I2C_T::BUSCTL |
| __IO uint32_t | I2C_T::BUSTCTL |
| __IO uint32_t | I2C_T::BUSSTS |
| __IO uint32_t | I2C_T::PKTSIZE |
| __I uint32_t | I2C_T::PKTCRC |
| __IO uint32_t | I2C_T::BUSTOUT |
| __IO uint32_t | I2C_T::CLKTOUT |
| __IO uint32_t | DSCT_T::CTL |
| __IO uint32_t | DSCT_T::SA |
| __IO uint32_t | DSCT_T::DA |
| __IO uint32_t | DSCT_T::NEXT |
| DSCT_T | PDMA_T::DSCT [12] |
| __I uint32_t | PDMA_T::CURSCAT [12] |
| __I uint32_t | PDMA_T::RESERVE0 [196] |
| __IO uint32_t | PDMA_T::CHCTL |
| __O uint32_t | PDMA_T::STOP |
| __O uint32_t | PDMA_T::SWREQ |
| __I uint32_t | PDMA_T::TRGSTS |
| __IO uint32_t | PDMA_T::PRISET |
| __O uint32_t | PDMA_T::PRICLR |
| __IO uint32_t | PDMA_T::INTEN |
| __IO uint32_t | PDMA_T::INTSTS |
| __IO uint32_t | PDMA_T::ABTSTS |
| __IO uint32_t | PDMA_T::TDSTS |
| __IO uint32_t | PDMA_T::SCATSTS |
| __I uint32_t | PDMA_T::TACTSTS |
| __I uint32_t | PDMA_T::RESERVE1 [1] |
| __IO uint32_t | PDMA_T::TOUTEN |
| __IO uint32_t | PDMA_T::TOUTIEN |
| __IO uint32_t | PDMA_T::SCATBA |
| __IO uint32_t | PDMA_T::TOC0_1 |
| __IO uint32_t | PDMA_T::TOC2_3 |
| __IO uint32_t | PDMA_T::TOC4_5 |
| __IO uint32_t | PDMA_T::TOC6_7 |
| __I uint32_t | PDMA_T::RESERVE2 [12] |
| __IO uint32_t | PDMA_T::REQSEL0_3 |
| __IO uint32_t | PDMA_T::REQSEL4_7 |
| __IO uint32_t | PDMA_T::REQSEL8_11 |
| __IO uint32_t | PWM_T::CTL0 |
| __IO uint32_t | PWM_T::CTL1 |
| __IO uint32_t | PWM_T::SYNC |
| __IO uint32_t | PWM_T::SWSYNC |
| __IO uint32_t | PWM_T::CLKSRC |
| __IO uint32_t | PWM_T::CLKPSC0_1 |
| __IO uint32_t | PWM_T::CLKPSC2_3 |
| __IO uint32_t | PWM_T::CLKPSC4_5 |
| __IO uint32_t | PWM_T::CNTEN |
| __IO uint32_t | PWM_T::CNTCLR |
| __IO uint32_t | PWM_T::LOAD |
| __I uint32_t | PWM_T::RESERVE0 [1] |
| __IO uint32_t | PWM_T::PERIOD [6] |
| __I uint32_t | PWM_T::RESERVE1 [2] |
| __IO uint32_t | PWM_T::CMPDAT [6] |
| __I uint32_t | PWM_T::RESERVE2 [2] |
| __IO uint32_t | PWM_T::DTCTL0_1 |
| __IO uint32_t | PWM_T::DTCTL2_3 |
| __IO uint32_t | PWM_T::DTCTL4_5 |
| __I uint32_t | PWM_T::RESERVE3 [1] |
| __IO uint32_t | PWM_T::PHS0_1 |
| __IO uint32_t | PWM_T::PHS2_3 |
| __IO uint32_t | PWM_T::PHS4_5 |
| __I uint32_t | PWM_T::RESERVE4 [1] |
| __I uint32_t | PWM_T::CNT [6] |
| __I uint32_t | PWM_T::RESERVE5 [2] |
| __IO uint32_t | PWM_T::WGCTL0 |
| __IO uint32_t | PWM_T::WGCTL1 |
| __IO uint32_t | PWM_T::MSKEN |
| __IO uint32_t | PWM_T::MSK |
| __IO uint32_t | PWM_T::BNF |
| __IO uint32_t | PWM_T::FAILBRK |
| __IO uint32_t | PWM_T::BRKCTL0_1 |
| __IO uint32_t | PWM_T::BRKCTL2_3 |
| __IO uint32_t | PWM_T::BRKCTL4_5 |
| __IO uint32_t | PWM_T::POLCTL |
| __IO uint32_t | PWM_T::POEN |
| __O uint32_t | PWM_T::SWBRK |
| __IO uint32_t | PWM_T::INTEN0 |
| __IO uint32_t | PWM_T::INTEN1 |
| __IO uint32_t | PWM_T::INTSTS0 |
| __IO uint32_t | PWM_T::INTSTS1 |
| __IO uint32_t | PWM_T::IFA |
| __IO uint32_t | PWM_T::RESERVE6 [1] |
| __IO uint32_t | PWM_T::EADCTS0 |
| __IO uint32_t | PWM_T::EADCTS1 |
| __IO uint32_t | PWM_T::FTCMPDAT0_1 |
| __IO uint32_t | PWM_T::FTCMPDAT2_3 |
| __IO uint32_t | PWM_T::FTCMPDAT4_5 |
| __I uint32_t | PWM_T::RESERVE7 [1] |
| __IO uint32_t | PWM_T::SSCTL |
| __O uint32_t | PWM_T::SSTRG |
| __I uint32_t | PWM_T::RESERVE8 [2] |
| __IO uint32_t | PWM_T::STATUS |
| __I uint32_t | PWM_T::RESERVE9 [55] |
| __IO uint32_t | PWM_T::CAPINEN |
| __IO uint32_t | PWM_T::CAPCTL |
| __I uint32_t | PWM_T::CAPSTS |
| __I uint32_t | PWM_T::RCAPDAT0 |
| __I uint32_t | PWM_T::FCAPDAT0 |
| __I uint32_t | PWM_T::RCAPDAT1 |
| __I uint32_t | PWM_T::FCAPDAT1 |
| __I uint32_t | PWM_T::RCAPDAT2 |
| __I uint32_t | PWM_T::FCAPDAT2 |
| __I uint32_t | PWM_T::RCAPDAT3 |
| __I uint32_t | PWM_T::FCAPDAT3 |
| __I uint32_t | PWM_T::RCAPDAT4 |
| __I uint32_t | PWM_T::FCAPDAT4 |
| __I uint32_t | PWM_T::RCAPDAT5 |
| __I uint32_t | PWM_T::FCAPDAT5 |
| __IO uint32_t | PWM_T::PDMACTL |
| __I uint32_t | PWM_T::PDMACAP0_1 |
| __I uint32_t | PWM_T::PDMACAP2_3 |
| __I uint32_t | PWM_T::PDMACAP4_5 |
| __I uint32_t | PWM_T::RESERVE10 [1] |
| __IO uint32_t | PWM_T::CAPIEN |
| __IO uint32_t | PWM_T::CAPIF |
| __I uint32_t | PWM_T::RESERVE11 [43] |
| __I uint32_t | PWM_T::PBUF [6] |
| __I uint32_t | PWM_T::CMPBUF [6] |
| __I uint32_t | PWM_T::RESERVE12 [3] |
| __I uint32_t | PWM_T::FTCBUF0_1 |
| __I uint32_t | PWM_T::FTCBUF2_3 |
| __I uint32_t | PWM_T::FTCBUF4_5 |
| __IO uint32_t | PWM_T::FTCI |
| __IO uint32_t | RTC_T::INIT |
| __O uint32_t | RTC_T::RWEN |
| __IO uint32_t | RTC_T::FREQADJ |
| __IO uint32_t | RTC_T::TIME |
| __IO uint32_t | RTC_T::CAL |
| __IO uint32_t | RTC_T::CLKFMT |
| __IO uint32_t | RTC_T::WEEKDAY |
| __IO uint32_t | RTC_T::TALM |
| __IO uint32_t | RTC_T::CALM |
| __I uint32_t | RTC_T::LEAPYEAR |
| __IO uint32_t | RTC_T::INTEN |
| __IO uint32_t | RTC_T::INTSTS |
| __IO uint32_t | RTC_T::TICK |
| __IO uint32_t | RTC_T::TAMSK |
| __IO uint32_t | RTC_T::CAMSK |
| __IO uint32_t | RTC_T::SPRCTL |
| __IO uint32_t | RTC_T::SPR [20] |
| __I uint32_t | RTC_T::RESERVE0 [28] |
| __IO uint32_t | RTC_T::LXTCTL |
| __IO uint32_t | RTC_T::LXTOCTL |
| __IO uint32_t | RTC_T::LXTICTL |
| __IO uint32_t | RTC_T::TAMPCTL |
| __IO uint32_t | SC_T::DAT |
| __IO uint32_t | SC_T::CTL |
| __IO uint32_t | SC_T::ALTCTL |
| __IO uint32_t | SC_T::EGT |
| __IO uint32_t | SC_T::RXTOUT |
| __IO uint32_t | SC_T::ETUCTL |
| __IO uint32_t | SC_T::INTEN |
| __IO uint32_t | SC_T::INTSTS |
| __IO uint32_t | SC_T::STATUS |
| __IO uint32_t | SC_T::PINCTL |
| __IO uint32_t | SC_T::TMRCTL0 |
| __IO uint32_t | SC_T::TMRCTL1 |
| __IO uint32_t | SC_T::TMRCTL2 |
| __IO uint32_t | SC_T::UARTCTL |
| __I uint32_t | SC_T::TMRDAT0 |
| __I uint32_t | SC_T::TMRDAT1_2 |
| __IO uint32_t | SPI_T::CTL |
| __IO uint32_t | SPI_T::CLKDIV |
| __IO uint32_t | SPI_T::SSCTL |
| __IO uint32_t | SPI_T::PDMACTL |
| __IO uint32_t | SPI_T::FIFOCTL |
| __IO uint32_t | SPI_T::STATUS |
| __I uint32_t | SPI_T::RESERVE0 [2] |
| __O uint32_t | SPI_T::TX |
| __I uint32_t | SPI_T::RESERVE1 [3] |
| __I uint32_t | SPI_T::RX |
| __I uint32_t | SPI_T::RESERVE2 [11] |
| __IO uint32_t | SPI_T::I2SCTL |
| __IO uint32_t | SPI_T::I2SCLK |
| __IO uint32_t | SPI_T::I2SSTS |
| __I uint32_t | SYS_T::PDID |
| __IO uint32_t | SYS_T::RSTSTS |
| __IO uint32_t | SYS_T::IPRST0 |
| __IO uint32_t | SYS_T::IPRST1 |
| __IO uint32_t | SYS_T::IPRST2 |
| __I uint32_t | SYS_T::RESERVE0 [1] |
| __IO uint32_t | SYS_T::BODCTL |
| __IO uint32_t | SYS_T::IVSCTL |
| __I uint32_t | SYS_T::RESERVE1 [1] |
| __IO uint32_t | SYS_T::PORCTL |
| __IO uint32_t | SYS_T::VREFCTL |
| __IO uint32_t | SYS_T::USBPHY |
| __IO uint32_t | SYS_T::GPA_MFPL |
| __IO uint32_t | SYS_T::GPA_MFPH |
| __IO uint32_t | SYS_T::GPB_MFPL |
| __IO uint32_t | SYS_T::GPB_MFPH |
| __IO uint32_t | SYS_T::GPC_MFPL |
| __IO uint32_t | SYS_T::GPC_MFPH |
| __IO uint32_t | SYS_T::GPD_MFPL |
| __IO uint32_t | SYS_T::GPD_MFPH |
| __IO uint32_t | SYS_T::GPE_MFPL |
| __IO uint32_t | SYS_T::GPE_MFPH |
| __IO uint32_t | SYS_T::GPF_MFPL |
| __I uint32_t | SYS_T::RESERVE2 [29] |
| __IO uint32_t | SYS_T::SRAM_BISTCTL |
| __I uint32_t | SYS_T::SRAM_BISTSTS |
| __I uint32_t | SYS_T::RESERVE3 [6] |
| __IO uint32_t | SYS_T::IRCTCTL |
| __IO uint32_t | SYS_T::IRCTIEN |
| __IO uint32_t | SYS_T::IRCTISTS |
| __I uint32_t | SYS_T::RESERVE4 [1] |
| __IO uint32_t | SYS_T::REGLCTL |
| __I uint32_t | SYS_T::RESERVE5 [11] |
| __IO uint32_t | SYS_T::IRC48MTCTL |
| __IO uint32_t | SYS_T::IRC48MTIEN |
| __IO uint32_t | SYS_T::IRC48MTISTS |
| __IO uint32_t | SYS_INT_T::NMIEN |
| __I uint32_t | SYS_INT_T::NMISTS |
| __IO uint32_t | TIMER_T::CTL |
| __IO uint32_t | TIMER_T::CMP |
| __IO uint32_t | TIMER_T::INTSTS |
| __I uint32_t | TIMER_T::CNT |
| __I uint32_t | TIMER_T::CAP |
| __IO uint32_t | TIMER_T::EXTCTL |
| __IO uint32_t | TIMER_T::EINTSTS |
| __IO uint32_t | UART_T::DAT |
| __IO uint32_t | UART_T::INTEN |
| __IO uint32_t | UART_T::FIFO |
| __IO uint32_t | UART_T::LINE |
| __IO uint32_t | UART_T::MODEM |
| __IO uint32_t | UART_T::MODEMSTS |
| __IO uint32_t | UART_T::FIFOSTS |
| __IO uint32_t | UART_T::INTSTS |
| __IO uint32_t | UART_T::TOUT |
| __IO uint32_t | UART_T::BAUD |
| __IO uint32_t | UART_T::IRDA |
| __IO uint32_t | UART_T::ALTCTL |
| __IO uint32_t | UART_T::FUNCSEL |
| __IO uint32_t | USBD_EP_T::BUFSEG |
| __IO uint32_t | USBD_EP_T::MXPLD |
| __IO uint32_t | USBD_EP_T::CFG |
| __IO uint32_t | USBD_EP_T::CFGP |
| __IO uint32_t | USBD_T::INTEN |
| __IO uint32_t | USBD_T::INTSTS |
| __IO uint32_t | USBD_T::FADDR |
| __I uint32_t | USBD_T::EPSTS |
| __IO uint32_t | USBD_T::ATTR |
| __I uint32_t | USBD_T::VBUSDET |
| __IO uint32_t | USBD_T::STBUFSEG |
| __I uint32_t | USBD_T::RESERVE0 [29] |
| __IO uint32_t | USBD_T::SE0 |
| __I uint32_t | USBD_T::RESERVE1 [283] |
| USBD_EP_T | USBD_T::EP [8] |
| __I uint32_t | USBH_T::HcRevision |
| __IO uint32_t | USBH_T::HcControl |
| __IO uint32_t | USBH_T::HcCommandStatus |
| __IO uint32_t | USBH_T::HcInterruptStatus |
| __IO uint32_t | USBH_T::HcInterruptEnable |
| __IO uint32_t | USBH_T::HcInterruptDisable |
| __IO uint32_t | USBH_T::HcHCCA |
| __IO uint32_t | USBH_T::HcPeriodCurrentED |
| __IO uint32_t | USBH_T::HcControlHeadED |
| __IO uint32_t | USBH_T::HcControlCurrentED |
| __IO uint32_t | USBH_T::HcBulkHeadED |
| __IO uint32_t | USBH_T::HcBulkCurrentED |
| __IO uint32_t | USBH_T::HcDoneHead |
| __IO uint32_t | USBH_T::HcFmInterval |
| __I uint32_t | USBH_T::HcFmRemaining |
| __I uint32_t | USBH_T::HcFmNumber |
| __IO uint32_t | USBH_T::HcPeriodicStart |
| __IO uint32_t | USBH_T::HcLSThreshold |
| __IO uint32_t | USBH_T::HcRhDescriptorA |
| __IO uint32_t | USBH_T::HcRhDescriptorB |
| __IO uint32_t | USBH_T::HcRhStatus |
| __IO uint32_t | USBH_T::HcRhPortStatus [2] |
| __I uint32_t | USBH_T::RESERVE0 [105] |
| __IO uint32_t | USBH_T::HcPhyControl |
| __IO uint32_t | USBH_T::HcMiscControl |
| __IO uint32_t | WDT_T::CTL |
| __IO uint32_t | WDT_T::ALTCTL |
| __O uint32_t | WWDT_T::RLDCNT |
| __IO uint32_t | WWDT_T::CTL |
| __IO uint32_t | WWDT_T::STATUS |
| __I uint32_t | WWDT_T::CNT |
| #define _GET_BYTE0 | ( | u32Param | ) | (((u32Param) & BYTE0_Msk) ) |
| #define _GET_BYTE1 | ( | u32Param | ) | (((u32Param) & BYTE1_Msk) >> 8) |
| #define _GET_BYTE2 | ( | u32Param | ) | (((u32Param) & BYTE2_Msk) >> 16) |
| #define _GET_BYTE3 | ( | u32Param | ) | (((u32Param) & BYTE3_Msk) >> 24) |
| #define EADC ((EADC_T *) EADC0_BASE) |
| #define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE) |
| #define inp16 | ( | port | ) | (*((volatile unsigned short *)(port))) |
| #define inp32 | ( | port | ) | (*((volatile unsigned int *)(port))) |
| #define inp8 | ( | port | ) | (*((volatile unsigned char *)(port))) |
| #define inpb | ( | port | ) | (*((volatile unsigned char *)(port))) |
| #define inps | ( | port | ) | (*((volatile unsigned short *)(port))) |
| #define PA ((GPIO_T *) GPIOA_BASE) |
| #define PB ((GPIO_T *) GPIOB_BASE) |
| #define PC ((GPIO_T *) GPIOC_BASE) |
| #define PD ((GPIO_T *) GPIOD_BASE) |
| #define PE ((GPIO_T *) GPIOE_BASE) |
| #define PF ((GPIO_T *) GPIOF_BASE) |
| #define TIMER0 ((TIMER_T *) TMR01_BASE) |
| #define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x20)) |
| #define TIMER2 ((TIMER_T *) TMR23_BASE) |
| #define TIMER3 ((TIMER_T *) (TMR23_BASE + 0x20)) |
| #define UART0 ((UART_T *) UART0_BASE) |
| #define UART1 ((UART_T *) UART1_BASE) |
| #define UART2 ((UART_T *) UART2_BASE) |
| #define UART3 ((UART_T *) UART3_BASE) |
| PDMA_T::ABTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | ABTIFn | PDMA Read/Write Target Abort Interrupt Status Flag |
| This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. | ||
| 0 = No AHB bus ERROR response received when channel n transfer. | ||
| 1 = AHB bus ERROR response received when channel n transfer. |
| I2C_T::ADDR0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GC | General Call Function |
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| [7:1] | ADDR | I2C Address |
| The content of this register is irrelevant when I2C is in Master mode. | ||
| In the slave mode, the seven most significant bits must be loaded with the chip's own address. | ||
| The I2C hardware will react if either of the address is matched. |
| I2C_T::ADDR1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GC | General Call Function |
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| [7:1] | ADDR | I2C Address |
| The content of this register is irrelevant when I2C is in Master mode. | ||
| In the slave mode, the seven most significant bits must be loaded with the chip's own address. | ||
| The I2C hardware will react if either of the address is matched. |
| I2C_T::ADDR2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GC | General Call Function |
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| [7:1] | ADDR | I2C Address |
| The content of this register is irrelevant when I2C is in Master mode. | ||
| In the slave mode, the seven most significant bits must be loaded with the chip's own address. | ||
| The I2C hardware will react if either of the address is matched. |
| I2C_T::ADDR3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GC | General Call Function |
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| [7:1] | ADDR | I2C Address |
| The content of this register is irrelevant when I2C is in Master mode. | ||
| In the slave mode, the seven most significant bits must be loaded with the chip's own address. | ||
| The I2C hardware will react if either of the address is matched. |
| I2C_T::ADDRMSK0 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | ADDRMSK | I2C Address Mask |
| 0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). | ||
| 1 = Mask Enabled (the received corresponding address bit is don't care.). | ||
| I2C bus controllers support multiple address recognition with four address mask register. | ||
| When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. | ||
| If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. |
| I2C_T::ADDRMSK1 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | ADDRMSK | I2C Address Mask |
| 0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). | ||
| 1 = Mask Enabled (the received corresponding address bit is don't care.). | ||
| I2C bus controllers support multiple address recognition with four address mask register. | ||
| When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. | ||
| If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. |
| I2C_T::ADDRMSK2 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | ADDRMSK | I2C Address Mask |
| 0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). | ||
| 1 = Mask Enabled (the received corresponding address bit is don't care.). | ||
| I2C bus controllers support multiple address recognition with four address mask register. | ||
| When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. | ||
| If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. |
| I2C_T::ADDRMSK3 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | ADDRMSK | I2C Address Mask |
| 0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). | ||
| 1 = Mask Enabled (the received corresponding address bit is don't care.). | ||
| I2C bus controllers support multiple address recognition with four address mask register. | ||
| When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. | ||
| If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. |
| CLK_T::AHBCLK |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | PDMACKEN | PDMA Controller Clock Enable Bit |
| 0 = PDMA peripheral clock Disabled. | ||
| 1 = PDMA peripheral clock Enabled. | ||
| [2] | ISPCKEN | Flash ISP Controller Clock Enable Bit |
| 0 = Flash ISP peripheral clock Disabled. | ||
| 1 = Flash ISP peripheral clock Enabled. | ||
| [3] | EBICKEN | EBI Controller Clock Enable Bit |
| 0 = EBI peripheral clock Disabled. | ||
| 1 = EBI peripheral clock Enabled. | ||
| [4] | USBHCKEN | USB HOST Controller Clock Enable Bit |
| 0 = USB HOST peripheral clock Disabled. | ||
| 1 = USB HOST peripheral clock Enabled. | ||
| [7] | CRCCKEN | CRC Generator Controller Clock Enable Bit |
| 0 = CRC peripheral clock Disabled. | ||
| 1 = CRC peripheral clock Enabled. | ||
| [15] | FMCIDLE | Flash Memory Controller Clock Enable Bit In IDLE Mode |
| 0 = FMC peripheral clock Disabled when chip operating at IDLE mode. | ||
| 1 = FMC peripheral clock Enabled when chip operating at IDLE mode. |
| SC_T::ALTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TXRST | TX Software Reset |
| When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the TX internal state machine and pointers. | ||
| Note: | ||
| This bit will be auto cleared after reset is complete. | ||
| [1] | RXRST | Rx Software Reset |
| When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the Rx internal state machine and pointers. | ||
| Note: | ||
| This bit will be auto cleared after reset is complete. | ||
| [2] | DACTEN | Deactivation Sequence Generator Enable Bit |
| This bit enables SC controller to initiate the card by deactivation sequence | ||
| 0 = No effect. | ||
| 1 = Deactivation sequence generator Enabled. | ||
| Note1: | ||
| When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1. | ||
| Note2: | ||
| This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). | ||
| So don't fill this bit, TXRST, and RXRST at the same time. | ||
| Note3: | ||
| If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [3] | ACTEN | Activation Sequence Generator Enable Bit |
| This bit enables SC controller to initiate the card by activation sequence | ||
| 0 = No effect. | ||
| 1 = Activation sequence generator Enabled. | ||
| Note1: | ||
| When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1. | ||
| Note2: | ||
| This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time. | ||
| Note3: | ||
| If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [4] | WARSTEN | Warm Reset Sequence Generator Enable Bit |
| This bit enables SC controller to initiate the card by warm reset sequence | ||
| 0 = No effect. | ||
| 1 = Warm reset sequence generator Enabled. | ||
| Note1: | ||
| When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1. | ||
| Note2: | ||
| This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time. | ||
| Note3: | ||
| If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [5] | CNTEN0 | Internal Timer0 Start Enable Bit |
| This bit enables Timer 0 to start counting. | ||
| Software can fill 0 to stop it and set 1 to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Start counting. | ||
| Note1: | ||
| This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01. | ||
| Note2: | ||
| If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware. | ||
| Note3: | ||
| This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). | ||
| So don't fill this bit, TXRST and RXRST at the same time. | ||
| Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [6] | CNTEN1 | Internal Timer1 Start Enable Bit |
| This bit enables Timer 1 to start counting. | ||
| Software can fill 0 to stop it and set 1 to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Start counting. | ||
| Note1: | ||
| This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11. | ||
| Don't filled CNTEN1 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01. | ||
| Note2: | ||
| If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware. | ||
| Note3: | ||
| This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time. | ||
| Note4: | ||
| If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [7] | CNTEN2 | Internal Timer2 Start Enable Bit |
| This bit enables Timer 2 to start counting. | ||
| Software can fill 0 to stop it and set 1 to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Start counting. | ||
| Note1: | ||
| This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11. | ||
| Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10. | ||
| Note2: | ||
| If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware. | ||
| Note3: | ||
| This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). | ||
| So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time. | ||
| Note4: | ||
| If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. | ||
| [9:8] | INITSEL | Initial Timing Selection |
| This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation). | ||
| Unit: SC clock | ||
| Activation: refer to SC Activation Sequence in Figure 6.17-4 | ||
| Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5 | ||
| Deactivation: refer to Deactivation Sequence in Figure 6.17-6 | ||
| [12] | RXBGTEN | Receiver Block Guard Time Function Enable Bit |
| 0 = Receiver block guard time function Disabled. | ||
| 1 = Receiver block guard time function Enabled. | ||
| [13] | ACTSTS0 | Internal Timer0 Active State (Read Only) |
| This bit indicates the timer counter status of timer0. | ||
| 0 = Timer0 is not active. | ||
| 1 = Timer0 is active. | ||
| [14] | ACTSTS1 | Internal Timer1 Active State (Read Only) |
| This bit indicates the timer counter status of timer1. | ||
| 0 = Timer1 is not active. | ||
| 1 = Timer1 is active. | ||
| [15] | ACTSTS2 | Internal Timer2 Active State (Read Only) |
| This bit indicates the timer counter status of timer2. | ||
| 0 = Timer2 is not active. | ||
| 1 = Timer2 is active. |
| UART_T::ALTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | BRKFL | UART LIN Break Field Length (Only Available In UART0/UART1 Channel) |
| This field indicates a 4-bit LIN TX break field count. | ||
| Note1: This break field length is BRKFL + 1 | ||
| Note2: According to LIN spec, the reset value is 0xC (break field length = 13). | ||
| [6] | LINRXEN | LIN RX Enable Bit (Only Available In UART0/UART1 Channel) |
| 0 = LIN RX mode Disabled. | ||
| 1 = LIN RX mode Enabled. | ||
| [7] | LINTXEN | LIN TX Break Mode Enable Bit (Only Available In UART0/UART1 Channel) |
| 0 = LIN TX Break mode Disabled. | ||
| 1 = LIN TX Break mode Enabled. | ||
| Note: When TX break field transfer operation finished, this bit will be cleared automatically. | ||
| [8] | RS485NMM | RS-485 Normal Multi-Drop Operation Mode (NMM) |
| 0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. | ||
| 1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. | ||
| Note: It cannot be active with RS-485_AAD operation mode. | ||
| [9] | RS485AAD | RS-485 Auto Address Detection Operation Mode (AAD) |
| 0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. | ||
| 1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. | ||
| Note: It cannot be active with RS-485_NMM operation mode. | ||
| [10] | RS485AUD | RS-485 Auto Direction Function (AUD) |
| 0 = RS-485 Auto Direction Operation function (AUD) Disabled. | ||
| 1 = RS-485 Auto Direction Operation function (AUD) Enabled. | ||
| Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. | ||
| [15] | ADDRDEN | RS-485 Address Detection Enable Bit |
| This bit is used to enable RS-485 Address Detection mode. | ||
| 0 = Address detection mode Disabled. | ||
| 1 = Address detection mode Enabled. | ||
| Note: This bit is used for RS-485 any operation mode. | ||
| [17] | ABRIF | Auto-Baud Rate Interrupt Flag (Read Only) |
| This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]) | ||
| [18] | ABRDEN | Auto-Baud Rate Detect Enable Bit |
| 0 = Auto-baud rate detect function Disabled. | ||
| 1 = Auto-baud rate detect function Enabled. | ||
| This bit is cleared automatically after auto-baud detection is finished. | ||
| [20:19] | ABRDBITS | Auto-Baud Rate Detect Bit Length |
| 00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. | ||
| 01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. | ||
| 10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. | ||
| 11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. | ||
| Note : The calculation of bit number includes the START bit. | ||
| [31:24] | ADDRMV | Address Match Value |
| This field contains the RS-485 address match values. | ||
| Note: This field is used for RS-485 auto address detection mode. |
| WDT_T::ALTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | RSTDSEL | WDT Reset Delay Selection (Write Protect) |
| When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened. | ||
| User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. | ||
| 00 = WDT Reset Delay Period is 1026 * WDT_CLK. | ||
| 01 = WDT Reset Delay Period is 130 * WDT_CLK. | ||
| 10 = WDT Reset Delay Period is 18 * WDT_CLK. | ||
| 11 = WDT Reset Delay Period is 3 * WDT_CLK. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: This register will be reset to 0 if WDT time-out reset happened. |
| CLK_T::APBCLK0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WDTCKEN | Watchdog Timer Clock Enable Bit (Write Protect) |
| 0 = Watchdog Timer Clock Disabled. | ||
| 1 = Watchdog Timer Clock Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [1] | RTCCKEN | Real-Time-Clock APB Interface Clock Enable Bit |
| This bit is used to control the RTC APB clock only. | ||
| The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]). | ||
| It can be selected to external 32.768 kHz low speed crystal or internal 10 kHz low speed oscillator. | ||
| 0 = RTC Clock Disabled. | ||
| 1 = RTC Clock Enabled. | ||
| [2] | TMR0CKEN | Timer0 Clock Enable Bit |
| 0 = Timer0 Clock Disabled. | ||
| 1 = Timer0 Clock Enabled. | ||
| [3] | TMR1CKEN | Timer1 Clock Enable Bit |
| 0 = Timer1 Clock Disabled. | ||
| 1 = Timer1 Clock Enabled. | ||
| [4] | TMR2CKEN | Timer2 Clock Enable Bit |
| 0 = Timer2 Clock Disabled. | ||
| 1 = Timer2 Clock Enabled. | ||
| [5] | TMR3CKEN | Timer3 Clock Enable Bit |
| 0 = Timer3 Clock Disabled. | ||
| 1 = Timer3 Clock Enabled. | ||
| [6] | CLKOCKEN | CLKO Clock Enable Bit |
| 0 = CLKO Clock Disabled. | ||
| 1 = CLKO Clock Enabled. | ||
| [8] | I2C0CKEN | I2C0 Clock Enable Bit |
| 0 = I2C0 Clock Disabled. | ||
| 1 = I2C0 Clock Enabled. | ||
| [9] | I2C1CKEN | I2C1 Clock Enable Bit |
| 0 = I2C1 Clock Disabled. | ||
| 1 = I2C1 Clock Enabled. | ||
| [12] | SPI0CKEN | SPI0 Clock Enable Bit |
| 0 = SPI0 Clock Disabled. | ||
| 1 = SPI0 Clock Enabled. | ||
| [13] | SPI1CKEN | SPI1 Clock Enable Bit |
| 0 = SPI1 Clock Disabled. | ||
| 1 = SPI1 Clock Enabled. | ||
| [16] | UART0CKEN | UART0 Clock Enable Bit |
| 0 = UART0 clock Disabled. | ||
| 1 = UART0 clock Enabled. | ||
| [17] | UART1CKEN | UART1 Clock Enable Bit |
| 0 = UART1 clock Disabled. | ||
| 1 = UART1 clock Enabled. | ||
| [18] | UART2CKEN | UART2 Clock Enable Bit |
| 0 = UART2 clock Disabled. | ||
| 1 = UART2 clock Enabled. | ||
| [19] | UART3CKEN | UART3 Clock Enable Bit |
| 0 = UART3 clock Disabled. | ||
| 1 = UART3 clock Enabled. | ||
| [27] | USBDCKEN | USB Device Clock Enable Bit |
| 0 = USB Device clock Disabled. | ||
| 1 = USB Device clock Enabled. | ||
| [28] | EADCCKEN | Enhanced Analog-Digital-Converter (EADC) Clock Enable Bit |
| 0 = EADC clock Disabled. | ||
| 1 = EADC clock Enabled. |
| CLK_T::APBCLK1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SC0CKEN | SC0 Clock Enable Bit |
| 0 = SC0 Clock Disabled. | ||
| 1 = SC0 Clock Enabled. | ||
| [16] | PWM0CKEN | PWM0 Clock Enable Bit |
| 0 = PWM0 Clock Disabled. | ||
| 1 = PWM0 Clock Enabled. | ||
| [17] | PWM1CKEN | PWM1 Clock Enable Bit |
| 0 = PWM1 Clock Disabled. | ||
| 1 = PWM1 Clock Enabled. | ||
| [25] | TKCKEN | Touch Key Clock Enable Bit |
| 0 = Touch Key Clock Disabled. | ||
| 1 = Touch key Clock Enabled. |
| USBD_T::ATTR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | USBRST | USB Reset Status |
| 0 = Bus no reset. | ||
| 1 = Bus reset when SE0 (single-ended 0) is presented more than 2.5us. | ||
| Note: This bit is read only. | ||
| [1] | SUSPEND | Suspend Status |
| 0 = Bus no suspend. | ||
| 1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping. | ||
| Note: This bit is read only. | ||
| [2] | RESUME | Resume Status |
| 0 = No bus resume. | ||
| 1 = Resume from suspend. | ||
| Note: This bit is read only. | ||
| [3] | TOUT | Time-Out Status |
| 0 = No time-out. | ||
| 1 = No Bus response more than 18 bits time. | ||
| Note: This bit is read only. | ||
| [4] | PHYEN | PHY Transceiver Function Enable |
| 0 = PHY transceiver function Disabled. | ||
| 1 = PHY transceiver function Enabled. | ||
| [5] | RWAKEUP | Remote Wake-Up |
| 0 = Release the USB bus from K state. | ||
| 1 = Force USB bus to K (USB_D+ low, USB_D- high) state, used for remote wake-up. | ||
| [7] | USBEN | USB Controller Enable |
| 0 = USB Controller Disabled. | ||
| 1 = USB Controller Enabled. | ||
| [8] | DPPUEN | Pull-Up Resistor On USB_D+ Enable |
| 0 = Pull-up resistor in USB_D+ pin Disabled. | ||
| 1 = Pull-up resistor in USB_D+ pin Enabled. | ||
| [9] | PWRDN | Power Down PHY Transceiver, Low Active |
| 0 = Power down related circuits of PHY transceiver. | ||
| 1 = Turn on related circuits of PHY transceiver. | ||
| [10] | BYTEM | CPU Access USB SRAM Size Mode Selection |
| 0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. | ||
| 1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. |
| UART_T::BAUD |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | BRD | Baud Rate Divider |
| The field indicates the baud rate divider. | ||
| This filed is used in baud rate calculation. | ||
| The detail description is shown in Table 6.21-2. | ||
| [27:24] | EDIVM1 | Extra Divider For BAUD Rate Mode 1 |
| This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. | ||
| The detail description is shown in Table 6.21-2. | ||
| [28] | BAUDM0 | BAUD Rate Mode Selection Bit 0 |
| This bit is baud rate mode selection bit 0. | ||
| UART provides three baud rate calculation modes. | ||
| This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. | ||
| The detail description is shown in Table 6.21-2. | ||
| [29] | BAUDM1 | BAUD Rate Mode Selection Bit 1 |
| This bit is baud rate mode selection bit 1. | ||
| UART provides three baud rate calculation modes. | ||
| This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. | ||
| The detail description is shown in Table 6.21-2. | ||
| Note: In IrDA mode must be operated in mode 0. |
| PWM_T::BNF |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BRK0NFEN | PWM Brake 0 Noise Filter Enable |
| 0 = Noise filter of PWM Brake 0 Disabled. | ||
| 1 = Noise filter of PWM Brake 0 Enabled. | ||
| [3:1] | BRK0NFSEL | Brake 0 Edge Detector Filter Clock Selection |
| 000 = Filter clock = HCLK. | ||
| 001 = Filter clock = HCLK/2. | ||
| 010 = Filter clock = HCLK/4. | ||
| 011 = Filter clock = HCLK/8. | ||
| 100 = Filter clock = HCLK/16. | ||
| 101 = Filter clock = HCLK/32. | ||
| 110 = Filter clock = HCLK/64. | ||
| 111 = Filter clock = HCLK/128. | ||
| [6:4] | BRK0FCNT | Brake 0 Edge Detector Filter Count |
| The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. | ||
| [7] | BRK0PINV | Brake 0 Pin Inverse |
| 0 = The state of pin PWMx_BRAKE0 is passed to the negative edge detector. | ||
| 1 = The inverted state of pin PWMx_BRAKE10 is passed to the negative edge detector. | ||
| [8] | BRK1NFEN | PWM Brake 1 Noise Filter Enable |
| 0 = Noise filter of PWM Brake 1 Disabled. | ||
| 1 = Noise filter of PWM Brake 1 Enabled. | ||
| [11:9] | BRK1NFSEL | Brake 1 Edge Detector Filter Clock Selection |
| 000 = Filter clock = HCLK. | ||
| 001 = Filter clock = HCLK/2. | ||
| 010 = Filter clock = HCLK/4. | ||
| 011 = Filter clock = HCLK/8. | ||
| 100 = Filter clock = HCLK/16. | ||
| 101 = Filter clock = HCLK/32. | ||
| 110 = Filter clock = HCLK/64. | ||
| 111 = Filter clock = HCLK/128. | ||
| [14:12] | BRK1FCNT | Brake 1 Edge Detector Filter Count |
| The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. | ||
| [15] | BRK1PINV | Brake 1 Pin Inverse |
| 0 = The state of pin PWMx_BRAKE1 is passed to the negative edge detector. | ||
| 1 = The inverted state of pin PWMx_BRAKE1 is passed to the negative edge detector. | ||
| [16] | BK0SRC | Brake 0 Pin Source Select |
| For PWM0 setting: | ||
| 0 = Brake 0 pin source come from PWM0_BRAKE0. | ||
| 1 = Brake 0 pin source come from PWM1_BRAKE0. | ||
| For PWM1 setting: | ||
| 0 = Brake 0 pin source come from PWM1_BRAKE0. | ||
| 1 = Brake 0 pin source come from PWM0_BRAKE0. | ||
| [24] | BK1SRC | Brake 1 Pin Source Select |
| For PWM0 setting: | ||
| 0 = Brake 1 pin source come from PWM0_BRAKE1. | ||
| 1 = Brake 1 pin source come from PWM1_BRAKE1. | ||
| For PWM1 setting: | ||
| 0 = Brake 1 pin source come from PWM1_BRAKE1. | ||
| 1 = Brake 1 pin source come from PWM0_BRAKE1. |
| SYS_T::BODCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BODEN | Brown-Out Detector Enable Bit (Write Protect) |
| The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]). | ||
| 0 = Brown-out Detector function Disabled. | ||
| 1 = Brown-out Detector function Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [2:1] | BODVL | Brown-Out Detector Threshold Voltage Selection (Write Protect) |
| The default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]). | ||
| 00 = Brown-Out Detector Threshold Voltage is 2.2V | ||
| 01 = Brown-Out Detector Threshold Voltage is 2.7V | ||
| 10 = Brown-Out Detector Threshold Voltage is 3.7V | ||
| 11 = Brown-Out Detector Threshold Voltage is 4.5V | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [3] | BODRSTEN | Brown-Out Reset Enable Bit (Write Protect) |
| The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . | ||
| 0 = Brown-out "INTERRUPT" function Enabled. | ||
| 1 = Brown-out "RESET" function Enabled. | ||
| Note1: | ||
| While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). | ||
| While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. | ||
| BOD interrupt will keep till to the BODEN set to 0. | ||
| BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). | ||
| Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [4] | BODIF | Brown-Out Detector Interrupt Flag |
| 0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. | ||
| 1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [5] | BODLPM | Brown-Out Detector Low Power Mode (Write Protect) |
| 0 = BOD operate in normal mode (default). | ||
| 1 = BOD Low Power mode Enabled. | ||
| Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. | ||
| Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [6] | BODOUT | Brown-Out Detector Output Status |
| 0 = Brown-out Detector output status is 0. | ||
| It means the detected voltage is higher than BODVL setting or BODEN is 0. | ||
| 1 = Brown-out Detector output status is 1. | ||
| It means the detected voltage is lower than BODVL setting. | ||
| If the BODEN is 0, BOD function disabled , this bit always responds 0000. | ||
| [7] | LVREN | Low Voltage Reset Enable Bit (Write Protect) |
| The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. | ||
| LVR function is enabled by default. | ||
| 0 = Low Voltage Reset function Disabled. | ||
| 1 = Low Voltage Reset function Enabled | ||
| Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). | ||
| Note2: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [10:8] | BODDGSEL | Brown-Out Detector Output De-Glitch Time Select (Write Protect) |
| 000 = BOD output is sampled by RC10K clock. | ||
| 001 = 4 system clock (HCLK). | ||
| 010 = 8 system clock (HCLK). | ||
| 011 = 16 system clock (HCLK). | ||
| 100 = 32 system clock (HCLK). | ||
| 101 = 64 system clock (HCLK). | ||
| 110 = 128 system clock (HCLK). | ||
| 111 = 256 system clock (HCLK). | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [14:12] | LVRDGSEL | LVR Output De-Glitch Time Select (Write Protect) |
| 000 = Without de-glitch function. | ||
| 001 = 4 system clock (HCLK). | ||
| 010 = 8 system clock (HCLK). | ||
| 011 = 16 system clock (HCLK). | ||
| 100 = 32 system clock (HCLK). | ||
| 101 = 64 system clock (HCLK). | ||
| 110 = 128 system clock (HCLK). | ||
| 111 = 256 system clock (HCLK). | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
| PWM_T::BRKCTL0_1 |
| Bits | Field | Descriptions |
|---|---|---|
| [4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect) |
| 0 = BKP0 pin as edge-detect brake source Disabled. | ||
| 1 = BKP0 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect) |
| 0 = BKP1 pin as edge-detect brake source Disabled. | ||
| 1 = BKP1 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [7] | SYSEBEN | Enable System Fail As Edge-Detect Brake Source (Write Protect) |
| 0 = System Fail condition as edge-detect brake source Disabled. | ||
| 1 = System Fail condition as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [12] | BRKP0LEN | Enable BKP0 Pin As Level-Detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [13] | BRKP1LEN | Enable BKP1 Pin As Level-Detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [15] | SYSLBEN | Enable System Fail As Level-Detect Brake Source (Write Protect) |
| 0 = System Fail condition as level-detect brake source Disabled. | ||
| 1 = System Fail condition as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [17:16] | BRKAEVEN | PWM Brake Action Select For Even Channel (Write Protect) |
| 00 = PWM even channel level-detect brake function not affect channel output. | ||
| 01 = PWM even channel output tri-state when level-detect brake happened. | ||
| 10 = PWM even channel output low level when level-detect brake happened. | ||
| 11 = PWM even channel output high level when level-detect brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [19:18] | BRKAODD | PWM Brake Action Select For Odd Channel (Write Protect) |
| 00 = PWM odd channel level-detect brake function not affect channel output. | ||
| 01 = PWM odd channel output tri-state when level-detect brake happened. | ||
| 10 = PWM odd channel output low level when level-detect brake happened. | ||
| 11 = PWM odd channel output high level when level-detect brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| PWM_T::BRKCTL2_3 |
| Bits | Field | Descriptions |
|---|---|---|
| [4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect) |
| 0 = BKP0 pin as edge-detect brake source Disabled. | ||
| 1 = BKP0 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect) |
| 0 = BKP1 pin as edge-detect brake source Disabled. | ||
| 1 = BKP1 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [7] | SYSEBEN | Enable System Fail As Edge-Detect Brake Source (Write Protect) |
| 0 = System Fail condition as edge-detect brake source Disabled. | ||
| 1 = System Fail condition as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [12] | BRKP0LEN | Enable BKP0 Pin As Level-Detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [13] | BRKP1LEN | Enable BKP1 Pin As Level-Detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [15] | SYSLBEN | Enable System Fail As Level-Detect Brake Source (Write Protect) |
| 0 = System Fail condition as level-detect brake source Disabled. | ||
| 1 = System Fail condition as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [17:16] | BRKAEVEN | PWM Brake Action Select For Even Channel (Write Protect) |
| 00 = PWM even channel level-detect brake function not affect channel output. | ||
| 01 = PWM even channel output tri-state when level-detect brake happened. | ||
| 10 = PWM even channel output low level when level-detect brake happened. | ||
| 11 = PWM even channel output high level when level-detect brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [19:18] | BRKAODD | PWM Brake Action Select For Odd Channel (Write Protect) |
| 00 = PWM odd channel level-detect brake function not affect channel output. | ||
| 01 = PWM odd channel output tri-state when level-detect brake happened. | ||
| 10 = PWM odd channel output low level when level-detect brake happened. | ||
| 11 = PWM odd channel output high level when level-detect brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| PWM_T::BRKCTL4_5 |
| Bits | Field | Descriptions |
|---|---|---|
| [4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect) |
| 0 = BKP0 pin as edge-detect brake source Disabled. | ||
| 1 = BKP0 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect) |
| 0 = BKP1 pin as edge-detect brake source Disabled. | ||
| 1 = BKP1 pin as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [7] | SYSEBEN | Enable System Fail As Edge-Detect Brake Source (Write Protect) |
| 0 = System Fail condition as edge-detect brake source Disabled. | ||
| 1 = System Fail condition as edge-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [12] | BRKP0LEN | Enable BKP0 Pin As Level-Detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [13] | BRKP1LEN | Enable BKP1 Pin As Level-Detect Brake Source (Write Protect) |
| 0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. | ||
| 1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [15] | SYSLBEN | Enable System Fail As Level-Detect Brake Source (Write Protect) |
| 0 = System Fail condition as level-detect brake source Disabled. | ||
| 1 = System Fail condition as level-detect brake source Enabled. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [17:16] | BRKAEVEN | PWM Brake Action Select For Even Channel (Write Protect) |
| 00 = PWM even channel level-detect brake function not affect channel output. | ||
| 01 = PWM even channel output tri-state when level-detect brake happened. | ||
| 10 = PWM even channel output low level when level-detect brake happened. | ||
| 11 = PWM even channel output high level when level-detect brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [19:18] | BRKAODD | PWM Brake Action Select For Odd Channel (Write Protect) |
| 00 = PWM odd channel level-detect brake function not affect channel output. | ||
| 01 = PWM odd channel output tri-state when level-detect brake happened. | ||
| 10 = PWM odd channel output low level when level-detect brake happened. | ||
| 11 = PWM odd channel output high level when level-detect brake happened. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| USBD_EP_T::BUFSEG |
| Bits | Field | Descriptions |
|---|---|---|
| [8:3] | BUFSEG | Endpoint Buffer Segmentation |
| It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is | ||
| USB_SRAM address + { BUFSEG[8:3], 3'b000} | ||
| Where the USB_SRAM address = USBD_BA+0x100h. | ||
| Refer to the section <IP_ADDRESS> for the endpoint SRAM structure and its description. |
| I2C_T::BUSCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ACKMEN | Acknowledge Control By Manual |
| In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. | ||
| 0 = Slave byte control Disabled. | ||
| 1 = Slave byte control Enabled. | ||
| The 9th bit can response the ACK or NACK according the received data by user. | ||
| When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse. | ||
| Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition. | ||
| [1] | PECEN | Packet Error Checking Calculation Enable Bit |
| 0 = Packet Error Checking Calculation Disabled. | ||
| 1 = Packet Error Checking Calculation Enabled. | ||
| [2] | BMDEN | Bus Management Device Default Address Enable Bit |
| 0 = Device default address Disable. | ||
| When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed. | ||
| 1 = Device default address Enabled. | ||
| When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed. | ||
| [3] | BMHEN | Bus Management Host Enable Bit |
| 0 = Host function Disabled. | ||
| 1 = Host function Enabled and the SUSCON will be used as CONTROL function. | ||
| [4] | ALERTEN | Bus Management Alert Enable Bit |
| Device Mode (BMHEN =0). | ||
| 0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. | ||
| 1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. | ||
| Host Mode (BMHEN =1). | ||
| 0 = BM_ALERT pin not supported. | ||
| 1 = BM_ALERT pin supported. | ||
| [5] | SCTLOSTS | Suspend/Control Data Output Status |
| 0 = The output of SUSCON pin is low. | ||
| 1 = The output of SUSCON pin is high. | ||
| [6] | SCTLOEN | Suspend Or Control Pin Output Enable Bit |
| 0 = The SUSCON pin in input. | ||
| 1 = The output enable is active on the SUSCON pin. | ||
| [7] | BUSEN | BUS Enable Bit |
| 0 = The system management function is Disabled. | ||
| 1 = The system management function is Enable. | ||
| Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. | ||
| [8] | PECTXEN | Packet Error Checking Byte Transmission/Reception |
| This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address Matched is received | ||
| 0 = No PEC transfer. | ||
| 1 = PEC transmission/reception is requested. | ||
| Note: 1.This bit has no effect in slave mode when ACKMEN =0. | ||
| [9] | TIDLE | Timer Check In Idle State |
| The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. | ||
| This bit is used to define which condition is enabled. | ||
| 0 = The BUSTOUT is used to calculate the clock low period in bus active. | ||
| 1 = The BUSTOUT is used to calculate the IDLE period in bus Idle. | ||
| Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. | ||
| [10] | PECCLR | PEC Clear At Repeat Start |
| The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected. | ||
| This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. | ||
| 0 = The PEC calculation is cleared by "Repeat Start" function is Disabled. | ||
| 1 = The PEC calculation is cleared by "Repeat Start" function is Enabled. | ||
| [11] | ACKM9SI | Acknowledge Manual Enable Extra SI Interrupt |
| 0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1. | ||
| 1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1. |
| I2C_T::BUSSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUSY | Bus Busy |
| Indicates that a communication is in progress on the bus. | ||
| It is set by hardware when a START condition is detected. | ||
| It is cleared by hardware when a STOP condition is detected. | ||
| 0 = The bus is IDLE (both SCLK and SDA High). | ||
| 1 = The bus is busy. | ||
| [1] | BCDONE | Byte Count Transmission/Receive Done |
| 0 = Indicates the transmission/ receive is not finished when the PECEN is set. | ||
| 1 = Indicates the transmission/ receive is finished when the PECEN is set. | ||
| Note: Software can write 1 to clear this bit. | ||
| [2] | PECERR | PEC Error In Reception |
| 0 = Indicates the PEC value equal the received PEC data packet. | ||
| 1 = Indicates the PEC value doesn't match the receive PEC data packet. | ||
| Note: Software can write 1 to clear this bit. | ||
| [3] | ALERT | SMBus Alert Status |
| Device Mode (BMHEN =0). | ||
| 0 = Indicates SMALERT pin state is low. | ||
| 1 = Indicates SMALERT pin state is high | ||
| Host Mode (BMHEN =1). | ||
| 0 = No SMBALERT event. | ||
| 1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1. | ||
| Note: 1. | ||
| The SMALERT pin is an open-drain pin, the pull-high resistor is must in the system. | ||
| 2. | ||
| Software can write 1 to clear this bit. | ||
| [4] | SCTLDIN | Bus Suspend Or Control Signal Input Status |
| 0 = The input status of SUSCON pin is 0. | ||
| 1 = The input status of SUSCON pin is 1. | ||
| [5] | BUSTO | Bus Time-out Status |
| 0 = Indicates that there is no any time-out or external clock time-out. | ||
| 1 = Indicates that a time-out or external clock time-out occurred. | ||
| In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. | ||
| Note: Software can write 1 to clear this bit. | ||
| [6] | CLKTO | Clock Low Cumulate Time-out Status |
| 0 = Indicates that the cumulative clock low is no any time-out. | ||
| 1 = Indicates that the cumulative clock low time-out occurred. | ||
| Note: Software can write 1 to clear this bit. |
| I2C_T::BUSTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUSTOEN | Bus Time Out Enable Bit |
| 0 = Indicates the bus clock low time-out detection is Disabled. | ||
| 1 = Indicates the bus clock low time-out detection is Enabled | ||
| bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1), | ||
| [1] | CLKTOEN | Cumulative Clock Low Time Out Enable Bit |
| 0 = Indicates the cumulative clock low time-out detection is Disabled. | ||
| 1 = Indicates the cumulative clock low time-out detection is Enabled. | ||
| For Master, it calculates the period from START to ACK | ||
| For Slave, it calculates the period from START to STOP | ||
| [2] | BUSTOIEN | Time-Out Interrupt Enable Bit |
| BUSY =1. | ||
| 0 = Indicates the SCLK low time-out interrupt is Disabled. | ||
| 1 = Indicates the SCLK low time-out interrupt is Enabled. | ||
| BUSY =0. | ||
| 0 = Indicates the bus IDLE time-out interrupt is Disabled. | ||
| 1 = Indicates the bus IDLE time-out interrupt is Enabled. | ||
| [3] | CLKTOIEN | Extended Clock Time Out Interrupt Enable Bit |
| 0 = Indicates the time extended interrupt is Disabled. | ||
| 1 = Indicates the time extended interrupt is Enabled. | ||
| [4] | TORSTEN | Time Out Reset Enable Bit |
| 0 = Indicates the I2C state machine reset is Disable. | ||
| 1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high) | ||
| [5] | PECIEN | Packet Error Checking Byte Count Done Interrupt Enable Bit |
| 0 = Indicates the byte count done interrupt is Disabled. | ||
| 1 = Indicates the byte count done interrupt is Enabled. | ||
| Note: This bit is used in PECEN =1. |
| I2C_T::BUSTOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | BUSTO | Bus Management Time-out Value |
| Indicate the bus time-out value in bus is IDLE or SCLK low. | ||
| Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. |
| RTC_T::CAL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | DAY | 1-Day Calendar Digit (0~9) |
| [5:4] | TENDAY | 10-Day Calendar Digit (0~3) |
| [11:8] | MON | 1-Month Calendar Digit (0~9) |
| [12] | TENMON | 10-Month Calendar Digit (0~1) |
| [19:16] | YEAR | 1-Year Calendar Digit (0~9) |
| [23:20] | TENYEAR | 10-Year Calendar Digit (0~9) |
| RTC_T::CALM |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | DAY | 1-Day Calendar Digit of Alarm Setting (0~9) |
| [5:4] | TENDAY | 10-Day Calendar Digit of Alarm Setting (0~3) |
| [11:8] | MON | 1-Month Calendar Digit of Alarm Setting (0~9) |
| [12] | TENMON | 10-Month Calendar Digit of Alarm Setting (0~1) |
| [19:16] | YEAR | 1-Year Calendar Digit of Alarm Setting (0~9) |
| [23:20] | TENYEAR | 10-Year Calendar Digit of Alarm Setting (0~9) |
| RTC_T::CAMSK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | MDAY | Mask 1-Day Calendar Digit of Alarm Setting (0~9) |
| [1] | MTENDAY | Mask 10-Day Calendar Digit of Alarm Setting (0~3) |
| [2] | MMON | Mask 1-Month Calendar Digit of Alarm Setting (0~9) |
| [3] | MTENMON | Mask 10-Month Calendar Digit of Alarm Setting (0~1) |
| [4] | MYEAR | Mask 1-Year Calendar Digit of Alarm Setting (0~9) |
| [5] | MTENYEAR | Mask 10-Year Calendar Digit of Alarm Setting (0~9) |
| TIMER_T::CAP |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CAPDAT | Timer Capture Data Register |
| When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. |
| PWM_T::CAPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CAPENn | Capture Function Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. | ||
| 1 = Capture function Enabled. | ||
| Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). | ||
| [13:8] | CAPINVn | Capture Inverter Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = Capture source inverter Disabled. | ||
| 1 = Capture source inverter Enabled. Reverse the input signal from GPIO. | ||
| [21:16] | RCRLDENn | Rising Capture Reload Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = Rising capture reload counter Disabled. | ||
| 1 = Rising capture reload counter Enabled. | ||
| [29:24] | FCRLDENn | Falling Capture Reload Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = Falling capture reload counter Disabled. | ||
| 1 = Falling capture reload counter Enabled. |
| PWM_T::CAPIEN |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CAPRIENn | PWM Capture Rising Latch Interrupt Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = Capture rising edge latch interrupt Disabled. | ||
| 1 = Capture rising edge latch interrupt Enabled. | ||
| Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled. | ||
| [13:8] | CAPFIENn | PWM Capture Falling Latch Interrupt Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = Capture falling edge latch interrupt Disabled. | ||
| 1 = Capture falling edge latch interrupt Enabled. | ||
| Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled. |
| PWM_T::CAPIF |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CRLIFn | PWM Capture Rising Latch Interrupt Flag |
| This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n. | ||
| 0 = No capture rising latch condition happened. | ||
| 1 = Capture rising latch condition happened, this flag will be set to high. | ||
| Note: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data. | ||
| [13:8] | CFLIFn | PWM Capture Falling Latch Interrupt Flag |
| This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n. | ||
| 0 = No capture falling latch condition happened. | ||
| 1 = Capture falling latch condition happened, this flag will be set to high. | ||
| Note: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data. |
| PWM_T::CAPINEN |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CAPINENn | Capture Input Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = PWM Channel capture input path Disabled. | ||
| The input of PWM channel capture function is always regarded as 0. | ||
| 1 = PWM Channel capture input path Enabled. | ||
| The input of PWM channel capture function comes from correlative multifunction pin. |
| PWM_T::CAPSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CRLIFOVn | Capture Rising Latch Interrupt Flag Overrun Status (Read Only) |
| This flag indicates if rising latch happened when the corresponding CRLIF is 1. | ||
| Each bit n controls the corresponding PWM channel n. | ||
| Note: This bit will be cleared automatically when user clear corresponding CRLIF. | ||
| [13:8] | CFLIFOVn | Capture Falling Latch Interrupt Flag Overrun Status (Read Only) |
| This flag indicates if falling latch happened when the corresponding CFLIF is 1. | ||
| Each bit n controls the corresponding PWM channel n. | ||
| Note: This bit will be cleared automatically when user clear corresponding CFLIF. |
| CLK_T::CDLOWB |
| Bits | Field | Descriptions |
|---|---|---|
| [9:0] | LOWERBD | HXT Clock Frequency Detector Low Boundary |
| The bits define the low value of frequency monitor window. | ||
| When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. |
| CLK_T::CDUPB |
| Bits | Field | Descriptions |
|---|---|---|
| [9:0] | UPERBD | HXT Clock Frequency Detector Upper Boundary |
| The bits define the high value of frequency monitor window. | ||
| When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. |
| USBD_EP_T::CFG |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | EPNUM | Endpoint Number |
| These bits are used to define the endpoint number of the current endpoint. | ||
| [4] | ISOCH | Isochronous Endpoint |
| This bit is used to set the endpoint as Isochronous endpoint, no handshake. | ||
| 0 = No Isochronous endpoint. | ||
| 1 = Isochronous endpoint. | ||
| [6:5] | STATE | Endpoint STATE |
| 00 = Endpoint is Disabled. | ||
| 01 = Out endpoint. | ||
| 10 = IN endpoint. | ||
| 11 = Undefined. | ||
| [7] | DSQSYNC | Data Sequence Synchronization |
| 0 = DATA0 PID. | ||
| 1 = DATA1 PID. | ||
| Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. | ||
| Hardware will toggle automatically in IN token base on the bit. | ||
| [9] | CSTALL | Clear STALL Response |
| 0 = Disable the device to clear the STALL handshake in setup stage. | ||
| 1 = Clear the device to response STALL handshake in setup stage. |
| USBD_EP_T::CFGP |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CLRRDY | Clear Ready |
| When the USB_MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. | ||
| If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it will be cleared to 0 automatically. | ||
| For IN token, write 1 to clear the IN token had ready to transmit the data to USB. | ||
| For OUT token, write 1 to clear the OUT token had ready to receive the data from USB. | ||
| This bit is write 1 only and is always 0 when it is read back. | ||
| [1] | SSTALL | Set STALL |
| 0 = Disable the device to response STALL. | ||
| 1 = Set the device to respond STALL automatically. |
| PDMA_T::CHCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | CHENn | PDMA Channel Enable Bit |
| Set this bit to 1 to enable PDMAn operation. | ||
| If each channel is not set as enabled, each channel cannot be active. | ||
| 0 = PDMA channel [n] Disabled. | ||
| 1 = PDMA channel [n] Enabled. | ||
| Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer. | ||
| Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit. |
| CRC_T::CHECKSUM |
| CLK_T::CLKDCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [4] | HXTFDEN | HXT Clock Fail Detector Enable Bit |
| 0 = HXT clock Fail detector Disabled. | ||
| 1 = HXT clock Fail detector Enabled. | ||
| [5] | HXTFIEN | HXT Clock Fail Interrupt Enable Bit |
| 0 = HXT clock Fail interrupt Disabled. | ||
| 1 = HXT clock Fail interrupt Enabled. | ||
| [12] | LXTFDEN | LXT Clock Fail Detector Enable Bit |
| 0 = LXT clock Fail detector Disabled. | ||
| 1 = LXT clock Fail detector Enabled. | ||
| [13] | LXTFIEN | LXT Clock Fail Interrupt Enable Bit |
| 0 = LXT clock Fail interrupt Disabled. | ||
| 1 = LXT clock Fail interrupt Enabled. | ||
| [16] | HXTFQDEN | HXT Clock Frequency Monitor Enable Bit |
| 0 = HXT clock frequency monitor Disabled. | ||
| 1 = HXT clock frequency monitor Enabled. | ||
| [17] | HXTFQIEN | HXT Clock Frequency Monitor Interrupt Enable Bit |
| 0 = HXT clock frequency monitor fail interrupt Disabled. | ||
| 1 = HXT clock frequency monitor fail interrupt Enabled. |
| I2C_T::CLKDIV |
| SPI_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DIVIDER | Clock Divider |
| The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. | ||
| The frequency is obtained according to the following equation. | ||
| fspi_eclk = fspi_clock_src / (DIVIDER + 1) | ||
| where fspi_clock_src is the peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. |
| CLK_T::CLKDIV0 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | HCLKDIV | HCLK Clock Divide Number From HCLK Clock Source |
| HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). | ||
| [7:4] | USBDIV | USB Clock Divide Number From PLL Clock |
| USB clock frequency = (PLL frequency) / (USBDIV + 1). | ||
| [11:8] | UARTDIV | UART Clock Divide Number From UART Clock Source |
| UART clock frequency = (UART clock source frequency) / (UARTDIV + 1). | ||
| [23:16] | EADCDIV | EADC Clock Divide Number From EADC Clock Source |
| EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). |
| CLK_T::CLKDIV1 |
| CLK_T::CLKDSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXTFIF | HXT Clock Fail Interrupt Flag |
| 0 = HXT clock normal. | ||
| 1 = HXT clock stop | ||
| Note: Write 1 to clear the bit to 0. | ||
| [1] | LXTFIF | LXT Clock Fail Interrupt Flag |
| 0 = LXT clock normal. | ||
| 1 = LXT stop | ||
| Note: Write 1 to clear the bit to 0. | ||
| [8] | HXTFQIF | HXT Clock Frequency Monitor Interrupt Flag |
| 0 = HXT clock normal. | ||
| 1 = HXT clock frequency abnormal | ||
| Note: Write 1 to clear the bit to 0. |
| RTC_T::CLKFMT |
| CLK_T::CLKOCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | FREQSEL | Clock Output Frequency Selection |
| The formula of output frequency is | ||
| Fout = Fin/2(N+1). | ||
| Fin is the input clock frequency. | ||
| Fout is the frequency of divider output clock. | ||
| N is the 4-bit value of FREQSEL[3:0]. | ||
| [4] | CLKOEN | Clock Output Enable Bit |
| 0 =Clock Output function Disabled. | ||
| 1 = Clock Output function Enabled. | ||
| [5] | DIV1EN | Clock Output Divide One Enable Bit |
| 0 = Clock Output will output clock with source frequency divided by FREQSEL. | ||
| 1 = Clock Output will output clock with source frequency. | ||
| [6] | CLK1HZEN | Clock Output 1Hz Enable Bit |
| 0 = 1 Hz clock output for 32.768kHz frequency compensation Disabled. | ||
| 1 = 1 Hz clock output for 332.768kHz frequency compensation Enabled. |
| PWM_T::CLKPSC0_1 |
| PWM_T::CLKPSC2_3 |
| PWM_T::CLKPSC4_5 |
| CLK_T::CLKSEL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | HCLKSEL | HCLK Clock Source Selection (Write Protect) |
| Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. | ||
| The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. | ||
| Therefore the default value is either 000b or 111b. | ||
| 000 = Clock source from external 4~24 MHz high-speed crystal clock. | ||
| 001 = Clock source from external 32.768 kHz low-speed crystal clock. | ||
| 010 = Clock source from PLL clock. | ||
| 011 = Clock source from internal 10 kHz low-speed oscillator clock. | ||
| 111= Clock source from internal 22.1184 MHz high-speed oscillator clock. | ||
| Other = Reserved. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [5:3] | STCLKSEL | Cortex-M4 SysTick Clock Source Selection (Write Protect) |
| If SYST_CTRL[2]=0, SysTick uses listed clock source below. | ||
| 000 = Clock source from external 4~24 MHz high-speed crystal clock. | ||
| 001 = Clock source from external 32.768 kHz low-speed crystal clock. | ||
| 010 = Clock source from external 4~24 MHz high-speed crystal clock/2. | ||
| 011 = Clock source from HCLK/2. | ||
| 111 = Clock source from internal 22.1184 MHz high-speed oscillator clock/2. | ||
| Note: if SysTick clock source is not from HCLK (i.e. | ||
| SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [6] | PCLK0SEL | PCLK0 Clock Source Selection (Write Protect) |
| 0 = APB0 BUS clock source from HCLK. | ||
| 1 = APB0 BUS clock source from HCLK/2. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [7] | PCLK1SEL | PCLK1 Clock Source Selection (Write Protect) |
| 0 = APB1 BUS clock source from HCLK. | ||
| 1 = APB1 BUS clock source from HCLK/2. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [8] | USBCKSEL | USB Clock Source Selection (Write Protect) |
| 0 = USBH and USBD clock source from PLL. | ||
| 1 = USBH and USBD clock source from HIRC48M. |
| CLK_T::CLKSEL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | WDTSEL | Watchdog Timer Clock Source Selection (Write Protect) |
| 00 = Reserved. | ||
| 01 = Clock source from external 32.768 kHz low-speed crystal clock. | ||
| 10 = Clock source from HCLK/2048 clock. | ||
| 11 = Clock source from internal 10 kHz low-speed oscillator clock. | ||
| [10:8] | TMR0SEL | TIMER0 Clock Source Selection |
| 000 = Clock source from external 4~24 MHz high-speed crystal clock. | ||
| 001 = Clock source from external 32.768 kHz low-speed crystal clock. | ||
| 010 = Clock source from PCLK0. | ||
| 011 = Clock source from external clock T0 pin | ||
| 101 = Clock source from internal 10 kHz low-speed oscillator clock. | ||
| 111 = Clock source from internal 22.1184 MHz high-speed oscillator clock. | ||
| Others = Reserved. | ||
| [14:12] | TMR1SEL | TIMER1 Clock Source Selection |
| 000 = Clock source from external 4~24 MHz high-speed crystal clock. | ||
| 001 = Clock source from external 32.768 kHz low-speed crystal clock. | ||
| 010 = Clock source from PCLK0. | ||
| 011 = Clock source from external clock T1 pin | ||
| 101 = Clock source from internal 10 kHz low-speed oscillator clock. | ||
| 111 = Clock source from internal 22.1184 MHz high-speed oscillator clock. | ||
| Others = Reserved. | ||
| [18:16] | TMR2SEL | TIMER2 Clock Source Selection |
| 000 = Clock source from external 4~24 MHz high-speed crystal clock. | ||
| 001 = Clock source from external 32.768 kHz low-speed crystal clock. | ||
| 010 = Clock source from PCLK1. | ||
| 011 = Clock source from external clock T2 pin | ||
| 101 = Clock source from internal 10 kHz low-speed oscillator clock. | ||
| 111 = Clock source from internal 22.1184 MHz high-speed oscillator clock. | ||
| Others = Reserved. | ||
| [22:20] | TMR3SEL | TIMER3 Clock Source Selection |
| 000 = Clock source from external 4~24 MHz high-speed crystal clock. | ||
| 001 = Clock source from external 32.768 kHz low-speed crystal clock. | ||
| 010 = Clock source from PCLK1. | ||
| 011 = Clock source from external clock T3 pin. | ||
| 101 = Clock source from internal 10 kHz low-speed oscillator clock. | ||
| 111 = Clock source from internal 22.1184 MHz high-speed oscillator clock. | ||
| Others = Reserved. | ||
| [25:24] | UARTSEL | UART Clock Source Selection |
| 00 = Clock source from external 4~24 MHz high-speed crystal clock (HXT). | ||
| 01 = Clock source from PLL clock. | ||
| 10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). | ||
| 11 = Clock source from internal 22.1184 MHz high-speed oscillator clock (HIRC). | ||
| [29:28] | CLKOSEL | Clock Divider Clock Source Selection |
| 00 = Clock source from external 4~24 MHz high-speed crystal clock. | ||
| 01 = Clock source from external 32.768 kHz low-speed crystal clock. | ||
| 10 = Clock source from HCLK. | ||
| 11 = Clock source from internal 22.1184 MHz high-speed oscillator clock. | ||
| [31:30] | WWDTSEL | Window Watchdog Timer Clock Source Selection |
| 10 = Clock source from HCLK/2048 clock. | ||
| 11 = Clock source from internal 10 kHz low-speed oscillator clock. | ||
| Others = Reserved. |
| CLK_T::CLKSEL2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PWM0SEL | PWM0 Clock Source Selection |
| The peripheral clock source of PWM0 is defined by PWM0SEL. | ||
| 0 = Clock source from PLL clock. | ||
| 1 = Clock source from PCLK0. | ||
| [1] | PWM1SEL | PWM1 Clock Source Selection |
| The peripheral clock source of PWM1 is defined by PWM1SEL. | ||
| 0 = Clock source from PLL clock. | ||
| 1 = Clock source from PCLK1. | ||
| [3:2] | SPI0SEL | SPI0 Clock Source Selection |
| 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = Clock source from PCLK0. | ||
| 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. | ||
| [5:4] | SPI1SEL | SPI1 Clock Source Selection |
| 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = Clock source from PCLK1. | ||
| 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. |
| CLK_T::CLKSEL3 |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | SC0SEL | SC0 Clock Source Selection |
| 00 = Clock source from external 4~24 MHz high-speed crystal clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = Clock source from PCLK0. | ||
| 11 = Clock source from internal 22.1184 MHz high-speed oscillator clock. | ||
| [8] | RTCSEL | RTC Clock Source Selection |
| 0 = Clock source from external 32.768 kHz low-speed oscillator. | ||
| 1 = Clock source from internal 10 kHz low speed RC oscillator. |
| PWM_T::CLKSRC |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | ECLKSRC0 | PWM_CH01 External Clock Source Select |
| 000 = PWMx_CLK, x denotes 0 or 1. | ||
| 001 = TIMER0 overflow. | ||
| 010 = TIMER1 overflow. | ||
| 011 = TIMER2 overflow. | ||
| 100 = TIMER3 overflow. | ||
| Others = Reserved. | ||
| [10:8] | ECLKSRC2 | PWM_CH23 External Clock Source Select |
| 000 = PWMx_CLK, x denotes 0 or 1. | ||
| 001 = TIMER0 overflow. | ||
| 010 = TIMER1 overflow. | ||
| 011 = TIMER2 overflow. | ||
| 100 = TIMER3 overflow. | ||
| Others = Reserved. | ||
| [18:16] | ECLKSRC4 | PWM_CH45 External Clock Source Select |
| 000 = PWMx_CLK, x denotes 0 or 1. | ||
| 001 = TIMER0 overflow. | ||
| 010 = TIMER1 overflow. | ||
| 011 = TIMER2 overflow. | ||
| 100 = TIMER3 overflow. | ||
| Others = Reserved. |
| I2C_T::CLKTOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CLKTO | Bus Clock Low Timer |
| The field is used to configure the cumulative clock extension time-out. | ||
| Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and d clear to 0 first in the BUSEN is set. |
| EADC_T::CMP |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCMPEN | A/D Result Compare Enable Bit |
| 0 = Compare Disabled. | ||
| 1 = Compare Enabled. | ||
| Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. | ||
| [1] | ADCMPIE | A/D Result Compare Interrupt Enable Bit |
| 0 = Compare function interrupt Disabled. | ||
| 1 = Compare function interrupt Enabled. | ||
| If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. | ||
| [2] | CMPCOND | Compare Condition |
| 0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPn | ||
| [27:16]), the internal match counter will increase one. | ||
| 1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. | ||
| Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. | ||
| [7:3] | CMPSPL | Compare Sample Module Selection |
| 00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. | ||
| 00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. | ||
| 00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. | ||
| 00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. | ||
| 00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. | ||
| 00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. | ||
| 00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. | ||
| 00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. | ||
| 01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. | ||
| 01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. | ||
| 01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. | ||
| 01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. | ||
| 01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. | ||
| 01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. | ||
| 01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. | ||
| 01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. | ||
| 10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. | ||
| 10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. | ||
| 10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. | ||
| [11:8] | CMPMCNT | Compare Match Count |
| When the specified A/D sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1. | ||
| If the compare result does not meet the compare condition, the internal compare match counter will reset to 0. | ||
| When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. | ||
| [15] | CMPWEN | Compare Window Mode Enable Bit |
| 0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched. | ||
| ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched. | ||
| 1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. | ||
| ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. | ||
| Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. | ||
| [27:16] | CMPDAT | Comparison Data |
| The 12 bits data is used to compare with conversion result of specified sample module. | ||
| User can use it to monitor the external analog input pin voltage transition without imposing a load on software. |
| TIMER_T::CMP |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CMPDAT | Timer Compared Value |
| CMPDAT is a 24-bit compared value register. | ||
| When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. | ||
| Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). | ||
| Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. | ||
| Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. | ||
| But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. |
| PWM_T::CMPBUF |
| PWM_T::CMPDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CMP | PWM Comparator Register |
| CMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC. | ||
| In independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point. | ||
| In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. |
| PWM_T::CNT |
| TIMER_T::CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CNT | Timer Data Register |
| This field can be reflected the internal 24-bit timer counter value or external event input counter value from Tx_CNT (x=0~3) pin. | ||
| If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24- bit counter value . | ||
| If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24- bit event input counter value. |
| WWDT_T::CNT |
| PWM_T::CNTCLR |
| PWM_T::CNTEN |
| EADC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCEN | A/D Converter Enable Bit |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: Before starting A/D conversion function, this bit should be set to 1. | ||
| Clear it to 0 to disable A/D converter analog circuit power consumption. | ||
| [1] | ADCRST | ADC A/D Converter Control Circuits Reset |
| 0 = No effect. | ||
| 1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. | ||
| Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. | ||
| [2] | ADCIEN0 | Specific Sample Module A/D ADINT0 Interrupt Enable Bit |
| The A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion. | ||
| If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. | ||
| 0 = Specific sample module A/D ADINT0 interrupt function Disabled. | ||
| 1 = Specific sample module A/D ADINT0 interrupt function Enabled. | ||
| [3] | ADCIEN1 | Specific Sample Module A/D ADINT1 Interrupt Enable Bit |
| The A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion. | ||
| If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. | ||
| 0 = Specific sample module A/D ADINT1 interrupt function Disabled. | ||
| 1 = Specific sample module A/D ADINT1 interrupt function Enabled. | ||
| [4] | ADCIEN2 | Specific Sample Module A/D ADINT2 Interrupt Enable Bit |
| The A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion. | ||
| If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. | ||
| 0 = Specific sample module A/D ADINT2 interrupt function Disabled. | ||
| 1 = Specific sample module A/D ADINT2 interrupt function Enabled. | ||
| [5] | ADCIEN3 | Specific Sample Module A/D ADINT3 Interrupt Enable Bit |
| The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion. | ||
| If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. | ||
| 0 = Specific sample module A/D ADINT3 interrupt function Disabled. | ||
| 1 = Specific sample module A/D ADINT3 interrupt function Enabled. | ||
| [8] | DIFFEN | Differential Analog Input Mode Enable Bit |
| 0 = Single-end analog input mode. | ||
| 1 = Differential analog input mode. | ||
| [9] | DMOF | ADC Differential Input Mode Output Format |
| 0 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format. | ||
| 1 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format. | ||
| [11] | PDMAEN | PDMA Transfer Enable Bit |
| When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request. | ||
| 0 = PDMA data transfer Disabled. | ||
| 1 = PDMA data transfer Enabled. | ||
| Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. | ||
| [18:16] | SMPTSEL | ADC Internal Sampling Time Selection |
| ADC internal sampling cycle = SMPTSEL + 1. | ||
| 000 = 1 ADC clock sampling time. | ||
| 001 = 2 ADC clock sampling time. | ||
| 010 = 3 ADC clock sampling time. | ||
| 011 = 4 ADC clock sampling time. | ||
| 100 = 5 ADC clock sampling time. | ||
| 101 = 6 ADC clock sampling time. | ||
| 110 = 7 ADC clock sampling time. | ||
| 111 = 8 ADC clock sampling time. |
| CRC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CRCEN | CRC Channel Enable Bit |
| 0 = No effect. | ||
| 1 = CRC operation Enabled. | ||
| [1] | CRCRST | CRC Engine Reset |
| 0 = No effect. | ||
| 1 = Reset the internal CRC state machine and internal buffer. | ||
| The others contents of CRC_CTL register will not be cleared. | ||
| Note1: This bit will be cleared automatically. | ||
| Note2: Setting this bit will reload the initial seed value (CRC_SEED register). | ||
| [24] | DATREV | Write Data Bit Order Reverse |
| This bit is used to enable the bit order reverse function for write data value in CRC_DAT register. | ||
| 0 = Bit order reversed for CRC write data in Disabled. | ||
| 1 = Bit order reversed for CRC write data in Enabled (per byte). | ||
| Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. | ||
| [25] | CHKSREV | Checksum Bit Order Reverse |
| This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register. | ||
| 0 = Bit order reverse for CRC checksum Disabled. | ||
| 1 = Bit order reverse for CRC checksum Enabled. | ||
| Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. | ||
| [26] | DATFMT | Write Data 1's Complement |
| This bit is used to enable the 1's complement function for write data value in CRC_DAT register. | ||
| 0 = 1's complement for CRC writes data in Disabled. | ||
| 1 = 1's complement for CRC writes data in Enabled. | ||
| [27] | CHKSFMT | Checksum 1's Complement |
| This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. | ||
| 0 = 1's complement for CRC checksum Disabled. | ||
| 1 = 1's complement for CRC checksum Enabled. | ||
| [29:28] | DATLEN | CPU Write Data Length |
| This field indicates the write data length. | ||
| 00 = Data length is 8-bit mode. | ||
| 01 = Data length is 16-bit mode. | ||
| 1x = Data length is 32-bit mode. | ||
| Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0] | ||
| [31:30] | CRCMODE | CRC Polynomial Mode |
| This field indicates the CRC operation polynomial mode. | ||
| 00 = CRC-CCITT Polynomial mode. | ||
| 01 = CRC-8 Polynomial mode. | ||
| 10 = CRC-16 Polynomial mode. | ||
| 11 = CRC-32 Polynomial mode. |
| I2C_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [2] | AA | Assert Acknowledge Control |
| When AA =1 prior to address or data is received, | ||
| an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when | ||
| 1. A slave is acknowledging the address sent from master. | ||
| 2. The receiver devices are acknowledging the data sent by transmitter. | ||
| When AA=0 prior to address or data received, | ||
| a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. | ||
| [3] | SI | I2C Interrupt Flag |
| When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware. | ||
| If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. | ||
| SI must be cleared by software. | ||
| Clear SI by writing 1 to this bit. | ||
| For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. | ||
| [4] | STO | I2C STOP Control |
| In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. | ||
| This bit will be cleared by hardware automatically. | ||
| [5] | STA | I2C START Control |
| Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. | ||
| [6] | I2CEN | I2C Controller Enable Bit |
| Set to enable I2C serial function controller. | ||
| When I2CEN=1 the I2C serial function enable. | ||
| The multi-function pin function must set to SDA, and SCL of I2C function first. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [7] | INTEN | Enable Interrupt |
| 0 = I2C interrupt Disabled. | ||
| 1 = I2C interrupt Enabled. |
| DSCT_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | OPMODE | PDMA Operation Mode Selection |
| 0 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. | ||
| 1 = Basic mode: The descriptor table only has one task. | ||
| When this task is finished, the PDMA_INTSTS[x] will be asserted. | ||
| 2 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute. | ||
| 3 = Reserved. | ||
| Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. | ||
| [2] | TXTYPE | Transfer Type |
| 0 = Burst transfer type. | ||
| 1 = Single transfer type. | ||
| [6:4] | BURSIZE | Burst Size |
| This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. | ||
| 000 = 128 Transfers. | ||
| 001 = 64 Transfers. | ||
| 010 = 32 Transfers. | ||
| 011 = 16 Transfers. | ||
| 100 = 8 Transfers. | ||
| 101 = 4 Transfers. | ||
| 110 = 2 Transfers. | ||
| 111 = 1 Transfers. | ||
| Note: This field is only useful in burst transfer type. | ||
| [7] | TBINTDIS | Table Interrupt Disable |
| This field can be used to decide whether to enable table interrupt or not. | ||
| If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates interrupt. | ||
| 0 = Table interrupt Enabled. | ||
| 1 = Table interrupt Disabled. | ||
| Note: If this bit set to '1', the TEMPTYF will not be set. | ||
| [9:8] | SAINC | Source Address Increment |
| This field is used to set the source address increment size. | ||
| 11 = No increment (fixed address). | ||
| Others = Increment and size is depended on TXWIDTH selection. | ||
| [11:10] | DAINC | Destination Address Increment |
| This field is used to set the destination address increment size. | ||
| 11 = No increment (fixed address). | ||
| Others = Increment and size is depended on TXWIDTH selection. | ||
| [13:12] | TXWIDTH | Transfer Width Selection |
| This field is used for transfer width. | ||
| 00 = One byte (8 bit) is transferred for every operation. | ||
| 01= One half-word (16 bit) is transferred for every operation. | ||
| 10 = One word (32-bit) is transferred for every operation. | ||
| 11 = Reserved. | ||
| Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection | ||
| [29:16] | TXCNT | Transfer Count |
| The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. | ||
| Note: When PDMA finish each transfer data, this field will be decrease immediately. |
| SC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SCEN | SC Engine Enable Bit |
| Set this bit to 1 to enable SC operation. | ||
| If this bit is cleared, SC will force all transition to IDLE state. | ||
| [1] | RXOFF | RX Transition Disable Control |
| 0 = The receiver Enabled. | ||
| 1 = The receiver Disabled. | ||
| Note: | ||
| If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored. | ||
| [2] | TXOFF | TX Transition Disable Control |
| 0 = The transceiver Enabled. | ||
| 1 = The transceiver Disabled. | ||
| [3] | AUTOCEN | Auto Convention Enable Bit |
| 0 = Auto-convention Disabled. | ||
| 1 = Auto-convention Enabled. | ||
| When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11. | ||
| If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F. | ||
| After hardware received first data and stored it at buffer, | ||
| hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically. | ||
| If the first data is not 0x3B or 0x3F, hardware will generate an interrupt if ACERRIEN (SC_INTEN[10]) = 1 to CPU. | ||
| [5:4] | CONSEL | Convention Selection |
| 00 = Direct convention. | ||
| 01 = Reserved. | ||
| 10 = Reserved. | ||
| 11 = Inverse convention. | ||
| Note: | ||
| If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored. | ||
| [7:6] | RXTRGLV | Rx Buffer Trigger Level |
| When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated). | ||
| 00 = INTR_RDA Trigger Level with 01 Bytes. | ||
| 01 = INTR_RDA Trigger Level with 02 Bytes. | ||
| 10 = INTR_RDA Trigger Level with 03 Bytes. | ||
| 11 = Reserved. | ||
| [12:8] | BGT | Block Guard Time (BGT) |
| Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions. | ||
| This field indicates the counter for the bit length of block guard time. | ||
| According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it. | ||
| Note: | ||
| The real block guard time is BGT + 1. | ||
| [14:13] | TMRSEL | Timer Selection |
| 00 = All internal timer function Disabled. | ||
| 01 = Internal 24 bit timer Enabled. | ||
| Software can configure it by setting SC_TMRCTL0 [23:0]. | ||
| SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode. | ||
| 10 = internal 24 bit timer and 8 bit internal timer Enabled. | ||
| Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0]. | ||
| SC_TMRCTL2 will be ignored in this mode. | ||
| 11 = Internal 24 bit timer and two 8 bit timers Enabled. | ||
| Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]. | ||
| [15] | NSB | Stop Bit Length |
| This field indicates the length of stop bit. | ||
| 0 = The stop bit length is 2 ETU. | ||
| 1= The stop bit length is 1 ETU. | ||
| Note: | ||
| The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length | ||
| [18:16] | RXRTY | RX Error Retry Count Number |
| This field indicates the maximum number of receiver retries that are allowed when parity error has occurred | ||
| Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. | ||
| Note2: This field cannot be changed when RXRTYEN enabled. | ||
| The change flow is to disable RXRTYEN first and then fill in new retry value. | ||
| [19] | RXRTYEN | RX Error Retry Enable Bit |
| This bit enables receiver retry function when parity error has occurred. | ||
| 0 = RX error retry function Disabled. | ||
| 1 = RX error retry function Enabled. | ||
| Note: | ||
| Software must fill in the RXRTY value before enabling this bit. | ||
| [22:20] | TXRTY | TX Error Retry Count Number |
| This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. | ||
| Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. | ||
| Note2: This field cannot be changed when TXRTYEN enabled. | ||
| The change flow is to disable TXRTYEN first and then fill in new retry value. | ||
| [23] | TXRTYEN | TX Error Retry Enable Bit |
| This bit enables transmitter retry function when parity error has occurred. | ||
| 0 = TX error retry function Disabled. | ||
| 1 = TX error retry function Enabled. | ||
| [25:24] | CDDBSEL | Card Detect De-Bounce Selection |
| This field indicates the card detect de-bounce selection. | ||
| 00 = De-bounce sample card insert once per 384 (128 * 3) peripheral clocks and de-bounce sample card removal once per 128 peripheral clocks. | ||
| 01 = De-bounce sample card insert once per 192 (64 * 3) peripheral clocks and de-bounce sample card removal once per 64 peripheral clocks. | ||
| 10 = De-bounce sample card insert once per 96 (32 * 3) peripheral clocks and de-bounce sample card removal once per 32 peripheral clocks. | ||
| 11 = De-bounce sample card insert once per 48 (16 * 3) peripheral clocks and de-bounce sample card removal once per 16 peripheral clocks. | ||
| [26] | CDLV | Card Detect Level |
| 0 = When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected. | ||
| 1 = When hardware detects the card detect pin from low to high, it indicates a card is detected. | ||
| Note: Software must select card detect level before Smart Card engine enabled. | ||
| [30] | SYNC | SYNC Flag Indicator |
| Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY. | ||
| 0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. | ||
| 1 = Last value is synchronizing. | ||
| Note: This bit is read only. | ||
| [31] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Control |
| 0 = ICE debug mode acknowledgement affects SC counting. | ||
| SC internal counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| SC internal counter will keep going no matter CPU is held by ICE or not. |
| SPI_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SPIEN | SPI Transfer Control Enable Bit |
| In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. | ||
| In Slave mode, this device is ready to receive data when this bit is set to 1. | ||
| 0 = Transfer control Disabled. | ||
| 1 = Transfer control Enabled. | ||
| Note: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0. | ||
| [1] | RXNEG | Receive On Negative Edge |
| 0 = Received data input signal is latched on the rising edge of SPI bus clock. | ||
| 1 = Received data input signal is latched on the falling edge of SPI bus clock. | ||
| [2] | TXNEG | Transmit On Negative Edge |
| 0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. | ||
| 1 = Transmitted data output signal is changed on the falling edge of SP bus clock. | ||
| [3] | CLKPOL | Clock Polarity |
| 0 = SPI bus clock is idle low. | ||
| 1 = SPI bus clock is idle high. | ||
| [7:4] | SUSPITV | Suspend Interval (Master Only) |
| The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. | ||
| The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. | ||
| The default value is 0x3. | ||
| The period of the suspend interval is obtained according to the following equation. | ||
| (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle | ||
| Example: | ||
| SUSPITV = 0x0 ... 0.5 SPICLK clock cycle. | ||
| SUSPITV = 0x1 ... 1.5 SPICLK clock cycle. | ||
| ... | ||
| SUSPITV = 0xE ... 14.5 SPICLK clock cycle. | ||
| SUSPITV = 0xF ... 15.5 SPICLK clock cycle. | ||
| [12:8] | DWIDTH | Data Width |
| This field specifies how many bits can be transmitted / received in one transaction. | ||
| The minimum bit length is 8 bits and can up to 32 bits. | ||
| DWIDTH = 0x08 ... 8 bits. | ||
| DWIDTH = 0x09 ... 9 bits. | ||
| ... | ||
| DWIDTH = 0x1F ... 31 bits. | ||
| DWIDTH = 0x00 ... 32 bits. | ||
| [13] | LSB | Send LSB First |
| 0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. | ||
| 1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). | ||
| [16] | TWOBIT | 2-Bit Transfer Mode Enable Bit (Only Supported in SPI0) |
| 0 = 2-Bit Transfer mode Disabled. | ||
| 1 = 2-Bit Transfer mode Enabled. | ||
| Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd | ||
| serial transmitted bit data is from the second FIFO buffer data. | ||
| As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. | ||
| [17] | UNITIEN | Unit Transfer Interrupt Enable Bit |
| 0 = SPI unit transfer interrupt Disabled. | ||
| 1 = SPI unit transfer interrupt Enabled. | ||
| [18] | SLAVE | Slave Mode Control |
| 0 = Master mode. | ||
| 1 = Slave mode. | ||
| [19] | REORDER | Byte Reorder Function Enable Bit |
| 0 = Byte Reorder function Disabled. | ||
| 1 = Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. | ||
| The period of the byte suspend interval depends on the setting of SUSPITV. | ||
| Note: | ||
| 1. Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. | ||
| 2. Byte Reorder function is not supported when the Quad or Dual I/O mode is enabled. | ||
| [20] | QDIODIR | Quad Or Dual I/O Mode Direction Control (Only Supported in SPI0) |
| 0 = Quad or Dual Input mode. | ||
| 1 = Quad or Dual Output mode. | ||
| [21] | DUALIOEN | Dual I/O Mode Enable Bit (Only Supported in SPI0) |
| 0 = Dual I/O mode Disabled. | ||
| 1 = Dual I/O mode Enabled. | ||
| [22] | QUADIOEN | Quad I/O Mode Enable Bit (Only Supported in SPI0) |
| 0 = Quad I/O mode Disabled. | ||
| 1 = Quad I/O mode Enabled. |
| TIMER_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | PSC | Prescale Counter |
| Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter. | ||
| If this field is 0 (PSC = 0), then there is no scaling. | ||
| [17] | WKTKEN | Wake-Up Touch-Key Scan Enable Bit |
| If this bit is set to 1, timer time-out interrupt in Power-down mode can be triggered Touch-Key start scan. | ||
| 0 = Timer time-out interrupt signal trigger Touch-Key start scan Disabled. | ||
| 1 = Timer time-out interrupt signal trigger Touch-Key start scan Enabled. | ||
| Note: This bit is only available in TIMER0_CTL. | ||
| [18] | TRGSSEL | Trigger Source Select Bit |
| This bit is used to select trigger source is form Timer time-out interrupt signal or capture interrupt signal. | ||
| 0 = Timer time-out interrupt signal is used to trigger PWM, EADC. | ||
| 1 = Capture interrupt signal is used to trigger PWM, EADC. | ||
| [19] | TRGPWM | Trigger PWM Enable Bit |
| If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered PWM. | ||
| 0 = Timer interrupt trigger PWM Disabled. | ||
| 1 = Timer interrupt trigger PWM Enabled. | ||
| Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PWM. | ||
| If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PWM. | ||
| [21] | TRGEADC | Trigger EADC Enable Bit |
| If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered EADC. | ||
| 0 = Timer interrupt trigger EADC Disabled. | ||
| 1 = Timer interrupt trigger EADC Enabled. | ||
| Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger EADC. | ||
| If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger EADC. | ||
| [22] | TGLPINSEL | Toggle-Output Pin Select |
| 0 = Toggle mode output to Tx_OUT (Timer Event Counter Pin). | ||
| 1 = Toggle mode output to Tx_EXT(Timer External Capture Pin). | ||
| [23] | WKEN | Wake-Up Function Enable Bit |
| If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. | ||
| 0 = Wake-up function Disabled if timer interrupt signal generated. | ||
| 1 = Wake-up function Enabled if timer interrupt signal generated. | ||
| [24] | EXTCNTEN | Event Counter Mode Enable Bit |
| This bit is for external counting pin function enabled. | ||
| 0 = Event counter mode Disabled. | ||
| 1 = Event counter mode Enabled. | ||
| Note: When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. | ||
| [25] | ACTSTS | Timer Active Status Bit (Read Only) |
| This bit indicates the 24-bit up counter status. | ||
| 0 = 24-bit up counter is not active. | ||
| 1 = 24-bit up counter is active. | ||
| [26] | RSTCNT | Timer Counter Reset Bit |
| Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1. | ||
| 0 = No effect. | ||
| 1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit. | ||
| [28:27] | OPMODE | Timer Counting Mode Select |
| 00 = The Timer controller is operated in One-shot mode. | ||
| 01 = The Timer controller is operated in Periodic mode. | ||
| 10 = The Timer controller is operated in Toggle-output mode. | ||
| 11 = The Timer controller is operated in Continuous Counting mode. | ||
| [29] | INTEN | Timer Interrupt Enable Bit |
| 0 = Timer Interrupt Disabled. | ||
| 1 = Timer Interrupt Enabled. | ||
| Note: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. | ||
| [30] | CNTEN | Timer Counting Enable Bit |
| 0 = Stops/Suspends counting. | ||
| 1 = Starts counting. | ||
| Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. | ||
| Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated. | ||
| [31] | ICEDEBUG | ICE Debug Mode Acknowledge Disable |
| 0 = ICE debug mode acknowledgement effects TIMER counting. | ||
| TIMER counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| TIMER counter will keep going no matter CPU is held by ICE or not. |
| WDT_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RSTCNT | Reset WDT Up Counter (Write Protect) |
| 0 = No effect. | ||
| 1 = Reset the internal 18-bit WDT up counter value. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: This bit will be automatically cleared by hardware. | ||
| [1] | RSTEN | WDT Time-Out Reset Enable Control (Write Protect) |
| Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. | ||
| 0 = WDT time-out reset function Disabled. | ||
| 1 = WDT time-out reset function Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [2] | RSTF | WDT Time-Out Reset Flag |
| This bit indicates the system has been reset by WDT time-out reset or not. | ||
| 0 = WDT time-out reset did not occur. | ||
| 1 = WDT time-out reset occurred. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [3] | IF | WDT Time-Out Interrupt Flag |
| This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval | ||
| 0 = WDT time-out interrupt did not occur. | ||
| 1 = WDT time-out interrupt occurred. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [4] | WKEN | WDT Time-Out Wake-Up Function Control (Write Protect) |
| If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. | ||
| 0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. | ||
| 1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator. | ||
| [5] | WKF | WDT Time-Out Wake-Up Flag |
| This bit indicates the interrupt wake-up flag status of WDT | ||
| 0 = WDT does not cause chip wake-up. | ||
| 1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: This bit is cleared by writing 1 to it. | ||
| [6] | INTEN | WDT Time-Out Interrupt Enable Control (Write Protect) |
| If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. | ||
| 0 = WDT time-out interrupt Disabled. | ||
| 1 = WDT time-out interrupt Enabled. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [7] | WDTEN | WDT Enable Control (Write Protect) |
| 0 = WDT Disabled (This action will reset the internal up counter value). | ||
| 1 = WDT Enabled. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0. | ||
| [10:8] | TOUTSEL | WDT Time-Out Interval Selection (Write Protect) |
| These three bits select the time-out interval period for the WDT. | ||
| 000 = (2^4)*TWDT. | ||
| 001 = (2^6)*TWDT. | ||
| 010 = (2^8)*TWDT. | ||
| 011 = (2^10)*TWDT. | ||
| 100 = (2^12)*TWDT. | ||
| 101 = (2^14)*TWDT. | ||
| 110 = (2^16)*TWDT. | ||
| 111 = (2^18)*TWDT. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [31] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Control (Write Protect) |
| 0 = ICE debug mode acknowledgement affects WDT counting. | ||
| WDT up counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| WDT up counter will keep going no matter CPU is held by ICE or not. | ||
| Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
| WWDT_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WWDTEN | WWDT Enable Control Bit |
| Set this bit to enable WWDT counter counting. | ||
| 0 = WWDT counter is stopped. | ||
| 1 = WWDT counter is starting counting. | ||
| [1] | INTEN | WWDT Interrupt Enable Control Bit |
| If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. | ||
| 0 = WWDT counter compare match interrupt Disabled. | ||
| 1 = WWDT counter compare match interrupt Enabled. | ||
| [11:8] | PSCSEL | WWDT Counter Prescale Period Selection |
| 0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT. | ||
| 0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT. | ||
| 0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT. | ||
| 0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT. | ||
| 0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT. | ||
| 0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT. | ||
| 0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT. | ||
| 0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT. | ||
| 1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT. | ||
| 1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT. | ||
| 1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT. | ||
| 1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT. | ||
| 1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT. | ||
| 1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT. | ||
| 1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT. | ||
| 1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT. | ||
| [21:16] | CMPDAT | WWDT Window Compare Register |
| Set this register to adjust the valid reload window. | ||
| Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. | ||
| If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. | ||
| [31] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Control |
| 0 = ICE debug mode acknowledgement effects WWDT counting. | ||
| WWDT down counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| WWDT down counter will keep going no matter CPU is held by ICE or not. |
| EBI_T::CTL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | EN | EBI Enable Bit |
| This bit is the functional enable bit for EBI. | ||
| 0 = EBI function Disabled. | ||
| 1 = EBI function Enabled. | ||
| [1] | DW16 | EBI Data Width 16-Bit Select |
| This bit defines if the EBI data width is 8-bit or 16-bit. | ||
| 0 = EBI data width is 8-bit. | ||
| 1 = EBI data width is 16-bit. | ||
| [2] | CSPOLINV | Chip Select Pin Polar Inverse |
| This bit defines the active level of EBI chip select pin (EBI_nCS). | ||
| 0 = Chip select pin (EBI_nCS) is active low. | ||
| 1 = Chip select pin (EBI_nCS) is active high. | ||
| [10:8] | MCLKDIV | External Output Clock Divider |
| The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: | ||
| 000 = HCLK/1. | ||
| 001 = HCLK/2. | ||
| 010 = HCLK/4. | ||
| 011 = HCLK/8. | ||
| 100 = HCLK/16. | ||
| 101 = HCLK/32. | ||
| 110 = Reserved. | ||
| 111 = Reserved. | ||
| [18:16] | TALE | Extend Time Of ALE |
| The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. | ||
| tALE = (TALE+1)*EBI_MCLK. | ||
| Note: This field only available in EBI_CTL0 register | ||
| [24] | WBUFEN | EBI Write Buffer Enable Bit |
| 0 = EBI write buffer Disabled. | ||
| 1 = EBI write buffer Enabled. | ||
| Note: This bit only available in EBI_CTL0 register |
| PWM_T::CTL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CTRLDn | Center Re-Load |
| Each bit n controls the corresponding PWM channel n. | ||
| In up-down counter type, PERIOD will load to PBUF at the end point of each period. | ||
| CMPDAT will load to CMPBUF at the center point of a period. | ||
| [13:8] | WINLDENn | Window Load Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = PERIOD will load to PBUF at the end point of each period. | ||
| CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. | ||
| 1 = PERIOD will load to PBUF at the end point of each period. | ||
| CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. | ||
| The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success. | ||
| [21:16] | IMMLDENn | Immediately Load Enable |
| Each bit n controls the corresponding PWM channel n. | ||
| 0 = PERIOD will load to PBUF at the end point of each period. | ||
| CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. | ||
| 1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. | ||
| Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. | ||
| [24] | GROUPEN | Group Function Enable |
| 0 = The output waveform of each PWM channel are independent. | ||
| 1 = Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1. | ||
| [30] | DBGHALT | ICE Debug Mode Counter Halt (Write Protect) |
| If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. | ||
| 0 = ICE debug mode counter halt disable. | ||
| 1 = ICE debug mode counter halt enable. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [31] | DBGTRIOFF | ICE Debug Mode Acknowledge Disable (Write Protect) |
| 0 = ICE debug mode acknowledgement effects PWM output. | ||
| PWM pin will be forced as tri-state while ICE debug mode acknowledged. | ||
| 1 = ICE debug mode acknowledgement disabled. | ||
| PWM pin will keep output no matter ICE debug mode acknowledged or not. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. |
| EBI_T::CTL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | EN | EBI Enable Bit |
| This bit is the functional enable bit for EBI. | ||
| 0 = EBI function Disabled. | ||
| 1 = EBI function Enabled. | ||
| [1] | DW16 | EBI Data Width 16-Bit Select |
| This bit defines if the EBI data width is 8-bit or 16-bit. | ||
| 0 = EBI data width is 8-bit. | ||
| 1 = EBI data width is 16-bit. | ||
| [2] | CSPOLINV | Chip Select Pin Polar Inverse |
| This bit defines the active level of EBI chip select pin (EBI_nCS). | ||
| 0 = Chip select pin (EBI_nCS) is active low. | ||
| 1 = Chip select pin (EBI_nCS) is active high. | ||
| [10:8] | MCLKDIV | External Output Clock Divider |
| The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: | ||
| 000 = HCLK/1. | ||
| 001 = HCLK/2. | ||
| 010 = HCLK/4. | ||
| 011 = HCLK/8. | ||
| 100 = HCLK/16. | ||
| 101 = HCLK/32. | ||
| 110 = Reserved. | ||
| 111 = Reserved. | ||
| [18:16] | TALE | Extend Time Of ALE |
| The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. | ||
| tALE = (TALE+1)*EBI_MCLK. | ||
| Note: This field only available in EBI_CTL0 register | ||
| [24] | WBUFEN | EBI Write Buffer Enable Bit |