Porting a New Board To Migen
*Taps mic* Is this thing on? So it's really been 11 months since I last wrote something? I really need to change that! I'm going to attempt to write smaller articles in between my larger, more involved ones to keep me motivated to keep writing.
So today, I'm going to write about a simpler topic I meant to discuss last year, but never got around to it: How to get started with LINK(https://github.com/m-labs/migen, Migen) on your Shiny New FPGA Development Board! This post assumes you have previous experience with Python 3 and experience synthesizing digital logic on FPGAs with Verilog. However, no Migen experience is assumed! Yes, you can port your a development board to Migen without having used Migen before!
What Is Migen- And Why Use It?
Migen is a Python library (framework, maybe?) to build digital circuits either for simulation, synthesis on an FPGA, or ASIC fabrication (the latter of which is mostly untested). Migen is LINK(https://github.com/SpinalHDL, one) LINK(http://www.myhdl.org, of) LINK(https://chisel.eecs.berkeley.edu, many) attempts to solve some deficiences with Verilog and VHDL, the languages most commonly used in industry to develop digital integrated circuits (ICs). If necessary, a designer can use and import Verilog/VHDL directly into their designs using one of the above languages too.
All the languages above either emit Verilog or an LINK(https://github.com/freechipsproject/firrtl, Intermediate Representation) that can be transformed into Verilog/VHDL. I can think of a few reasons why:
- FPGA synthesis/ASIC front-ends are typically proprietary, can't be readily modified, and mostly only support Verilog and VHDL as input.
- Many issues with Verilog, such as synthesis-simulation behavior mismatch, don't occur if Verilog can be emitted in a controlled manner, as is done with the above languages.`'FN(1)
- From my own experience looking at yosys, which can be used as the front-end Verilog compiler to an LINK(http://www.clifford.at/icestorm/, open-source synthesis toolchain), there is little gain to targeting a file format meant for FPGA synthesis (or ASIC fabrication) directly from a higher-level language. Targeting the synthesis file format directly must be shown to be bug-free with respect to having generated Verilog and then generating the synthesis file format from the Verilog; this is nontrivial.
The LINK(https://media.readthedocs.org/pdf/mithro-migen/latest/mithro-migen.pdf, Migen manual) discusses its rationale for existing, but the important reasons that apply to me personally are that Migen:
- Avoids simulation-synthesis behavior mismatches in generated output.
- Makes it easy to automate digital logic design idioms that are tedious in Verilog alone, such as Finite-State Machines and Asynchronous FIFOs.
- Prevents classes of bugs in Verilog code, such as ensuring each signal has an initial value and unused cases in CODE(switch) statements are handled.
- Handles assignments satisfying "same sensitivity list, multiple always blocks" by concatenating them all into a single CODE(always) block, whereas Verilog forbids this for synthesis. In my experience, this increases code clarity.
As an added bonus, I can write a Migen design once and, within reason, generate a bitstream of my design without needing a separate User Constraints File (UCF) for each board that Migen supports. This facilitates design reuse by others who may not have the same board as I do, but has a new board with the required I/O peripherals anyway.
For the above reasons, I am far more productive writing HDL than I ever was writing Verilog.`'FN(2)
Choice of Tools Disclaimer
Of the linked languages above, I have only personally used Migen. Migen was the first Verilog alternative I personally discovered when I started using FPGAs for projects again in 2015 (after a 3 year break). When I first saw the typical code structure of a Migen project, I immediately felt at home writing my own basic designs, and could easily predict which Migen code would emit which Verilog constructs without reading the source. In fact, I ported my own Shiny New FPGA Development Board I just bought to Migen before I even tested my first Migen design!
Because of my extremely positive first impressions, and time spent learning Migen's more complicated features, I've had little incentive to learn a new HDL. That said, I maintain it is up to the reader to experiment and decide which HDL works best for their FPGA/ASIC projects. I only speak for my own experiences, and the point of me writing this post is to make porting a new board to Migen easier than when I learned how to do it. The code re-use aspect of Migen is important to me, and when done correctly, a port to a new board is very low-maintenance.
Leveraging Python To Build FPGA Applications
To motivate how to port a new development board, I need to show Migen code right now. If you haven't seen Migen before now, don't panic! I'll briefly explain each section:
from migen import *
from migen.build.platforms import icestick
class Rot(Module):
def __init__(self):
self.clk_freq = 12000000
self.ready = Signal()
self.rot = Signal(4)
self.divider = Signal(max=self.clk_freq)
self.d1 = Signal()
self.d2 = Signal()
self.d3 = Signal()
self.d4 = Signal()
self.d5 = Signal()
###
self.comb += [j.eq(self.rot[i]) for i, j in enumerate([self.d1, self.d2, self.d3, self.d4])]
self.comb += [self.d5.eq(1)]
self.sync += [
If(self.ready,
If(self.divider == int(self.clk_freq) - 1,
self.divider.eq(0),
self.rot.eq(Cat(self.rot[-1], self.rot[:-1]))
).Else(
self.divider.eq(self.divider + 1)
)
).Else(
self.ready.eq(1),
self.rot.eq(1),
self.divider.eq(0)
)
]
If you've never seen Migen code before, and/or are unfamiliar with its layout, I'll explain some of the more interesting points here in comparison to Verilog:
- CODE_BLOCK(`from migen import *
from migen.build.platforms import icestick')
Migen by default exports a number of primitives to get started writing CODE(Module)s. Other Migen constructs, such as a library of useful building blocks (CODE(migen.genlib)) and Verilog code generation (CODE(migen.fhdl.verilog)) must be imported manually. CODE(migen.build.platforms) contains all the FPGA development platforms Migen supports; the goal of this blog post will be to reimplement the LINK(http://www.latticesemi.com/icestick, iCEstick) development board for use from Migen.
- CODE_BLOCK(`class Rot(Module):')
A CODE(Module) is the basic unit describing digital behavior in Migen. Connections between CODE(Module)s are typically made by declaring instance variables that can be shared between CODE(Modules), and using CODE(submodules). Submodule syntax is described in the manual, and is required to share connections between modules.
- CODE_BLOCK(`self.ready = Signal(1)')
A CODE(Signal) is the basic data type in Migen. Unlike Verilog, which requires keywords to distinguish between data storage (CODE(reg)) and connections/nets (CODE(wire)), Migen can infer from a signal's usage whether or not the signal stores data. The CODE(1) indicates the signal is one-bit wide.
- CODE_BLOCK(`self.divider = Signal(max=self.clk_freq)
')
In addition to providing a bit width, I can tell Migen the maximum a CODE(Signal) is expected to take, and Migen will initialize its width to CODE(log2(max) + 1). However, nothing prevents the signal from exceeding max when run in a simulator or FPGA.
- CODE_BLOCK(`###
self.comb += [j.eq(self.rot[i]) for i, j in enumerate([self.d1, self.d2, self.d3, self.d4])]
')
By convention, data-type declarations are separated from code describing how code should behave using CODE(`###'). Migen statements relating connections of CODE(`Signal')s and other data types must be appended to either a CODE(comb) or CODE(sync) attribute. Connections are typically made using the CODE(eq) function of CODE(Signal)s. Python's slice notation accesses individual or subsets of bits of a CODE(Signal).
CODE(comb), or combinationial, statements are analogous to Verilog's CODE(assign) keyword or combinational CODE(`always @(*)') blocks, depending on the Migen data type/construct. In combinational logic, the output immediately changes in response to a changing or just-initialized) input without any concept of time (in theory).
- CODE_BLOCK(`self.sync += [
If(self.ready,
If(self.divider == int(self.clk_freq) - 1,
self.divider.eq(0),
self.rot.eq(Cat(self.rot[-1], self.rot[:-1]))
).Else(
self.divider.eq(self.divider + 1)
)
).Else(
self.ready.eq(1),
self.rot.eq(1),
self.divider.eq(0)
)
]')
By contrast, appending to the Migen CODE(sync), or synchronous, attribute emits Verilog code whose output only changes in response to a positive edge clock transition of a given clock, using the following syntax: CODE(`module.sync.my_clk += [...]'). If the clock is omitted, the clock defaults to CODE(sys). In synchronous/sequential logic, outputs do not change immediately in response to a changing or just-initialized input; the output only registers a new value based on its input signals in response to a low-to-high transition of another, usually periodic, signal. Migen only emits CODE(`always @(posedge clk)') blocks, so a CODE(negedge) clock must be created by inverting an existing clock, such as CODE(self.comb += [neg_clk.eq(~pos_clk)]).
As one might expect, CODE(`If().Elif().Else()') is analogous to Verilog CODE(if), CODE(else if), CODE(else) blocks. Migen will generate the correct style of CODE(`always') block to represent signal transitions regardless of whether the CODE(If()) statement is part of a CODE(comb) or CODE(sync) block.
I omitted discussing any Migen data types, input arguments to their constructors, other features provided by the package, and common code idioms that I didn't use above for the sake of keeping this blog post on point. Most of the user-facing features/constructors are documented in the user manual. I can discuss features (and behavior) not mentioned in the manual in a follow-up post.
Adding a New Board
The LINK(`#rot', above code) was adapted from the LINK(`https://github.com/cseed/arachne-pnr/tree/master/examples/rot', rot.v) example of Arachne PNR. In words, the above code turns on an LED, counts for 12,000,000 clock cycles, then turns off the previous LED and lights another of 4 LEDs; after 4 LEDs the cycle repeats. A fifth LED is always kept on as soon as the FPGA loads its bitstream.
Our goal is to get this simple Migen design to work on a new FPGA development board, walking through the process. Since this example is tailored to the iCE40 FPGA family, I'm choosing to port the iCEstick board to Migen... which already has a port...
Interactive Porting
My original intention was to write this blog post while I was creating the CODE(icestick.py) platform file to be committed into CODE(migen.build). Unfortunately, at the time, Migen did not have any support for targeting the IceStorm synthesis toolchain.`'FN(3) So I ended up LINK(https://ssl.serverraum.org/lists-archive/devel/2016-May/004205.html, implementing) the IceStorm backend and doing my blog post as intended went by the wayside while debugging.
That said, I'm going to attempt to simulate the process of adding a board from the beginning. I will only assume that the IceStorm backend to Migen exists, but the CODE(icestick.py) board file does not.
We Need a Constraints File
Before I can start writing a board file for iCEstick, we need to know which FPGA pins are connected to what. For many boards, the manufacturer will provide a full User Constraints File (UCF) with this information. For demonstrative purposes`'FN(4) however, I will examine the schematic diagram of iCEstick instead to create my Migen board file. This can be found in a file provided by Lattice at a changing URL called "icestickusermanual.pdf".
We need to know the format of FPGA pin identifiers that Arachne PNR, the place-and-route tool for IceStorm, will expect as well. The format differs for each of the FPGA manufacturers and even between FPGA families of the same manufacturer; Xilinx, for example uses CODE([A-Z]?[0-9]*), as does the Lattice ECP3 family. Fortunately, IceStorm uses pin numbers that correspond to the device package, and these are easily visible on the schematic:
IMG(icestick-schem, `One side (port) of connections of the iCE40 FPGA to iCEstick peripherals. In this image, LED, IrDA, and one side of 600 mil breadboard-compatible breakout connections can be seen.')
If we examine the schematic and user manual, we will find the following peripherals:
- 5 LEDs
- 2x6 Digilient PMOD connector
- IrDA transceiver
- SPI Flash
- FT2232H UART (one channel- the other is used for programming)
- 16 Additional I/O pins
We might not have an actual full constraints file to work with due to how CODE(arachne-pnr) works, but we have all the information to create a Migen board file anyway, since we have the schematics. Armed with this information, we can start creating a board file for iCEStick.
Anatomy of a Migen Board File
Relative to the root of the migen package, migen places board definition files under the CODE(build/platforms) directory. All paths in this section, unless otherwise noted are relative to the package root.
Platform Class
CODE_BLOCK(`from migen.build.generic_platform import * from migen.build.lattice import LatticePlatform from migen.build.lattice.programmer import IceStormProgrammer class Platform(LatticePlatform): default_clk_name = "clk12" default_clk_period = 83.333 def __init__(self): LatticePlatform.__init__(self, "ice40-1k-tq144", _io, _connectors, toolchain="icestorm") def create_programmer(self): return IceStormProgrammer()')A board file consists of the definition of Python CODE(class) conventionally named CODE(Platform). CODE(Platform) should inherit from a class defined for each supported FPGA manufacturer. As of this writing, Migen exports CODE(AlteraPlatform), CODE(XilinxPlatform), and CODE(LatticePlatform), and more are possible in the future. Vendor platforms are defined in a subdirectory under CODE(build) for each vendor, in the file CODE(platform.py).
Each FPGA vendor in turn inherits from CODE(GenericPlatform), which is defined in CODE(build/generic_platform.py) and exports a number of useful methods for use in Migen code (I'll introduce them as needed). The CODE(GenericPlatform) LINK(`https://github.com/m-labs/migen/blob/master/migen/build/generic_platform.py#L230', constructor) accepts the following arguments:
- CODE(device)- A string indicating the FPGA device on your board.FN(5) The string format is vendor-toolchain specific; in the case of IceStorm, the format is currently CODE(`"ice40-{1k,8k}-{package}"').
- CODE(io)- A list of tuples of a specific format which I'll describe shortly. The list represents all non-user-expandable I/O resources on your current board. For instance, LEDs, SPI flash, and ADC connections to your FPGA would be placed in the CODE(io) list.
- CODE(connectors)- A list of tuples with a specific layout, which I'll describe shortly. The list represents user-expandable I/O that by default is not connected to any piece of hardware, such as LINK(https://en.wikipedia.org/wiki/Pmod_Interface, Pmod) headers.
- CODE(name)- I don't know what this input argument does exactly. Like other places in Migen with a CODE(name) input argument, it's meant to control how variable names are generated in the Verilog output. I don't believe it's used by any board file, so I'm ignoring it.
- CODE(toolchain)- The same FPGA vendor can have multiple software suites for their FPGA families, or third-party toolchains can exist. For instance, Xilinx has both the End-of-Life ISE Toolchain and Vivado software available. Additionally, Lattice provides the Diamond toolchain for their higher-end FPGAs while Project IceStorm is an unaffialited open-source synthesis flow for the iCE40 family. Thus, the vendor platform constructors LINK(`https://github.com/m-labs/migen/blob/master/migen/build/lattice/platform.py#L8', also supply) a CODE(toolchain) keyword argument to choose which toolchain to eventually invoke. In the case of iCEStick, we use Migen's CODE(icestorm) backend.
A CODE(Platform) class definition should also define the class variables CODE(default_clk_name) and CODE(default_clk_period), which are used by CODE(GenericPlatform). CODE(default_clk_name) should match the name of a resource in the CODE(io) list that represents a clock input to the FPGA. CODE(default_clk_period) is used by vendor-specific logic in Migen to create a clock constraint in nanoseconds for CODE(default_clk_name). The default clock is associated with the CODE(sys) clock domain for CODE(sync) statements.
Lastly, the CODE(create_programmer) function should return a vendor-specific programmer. Adding a programmer is beyond the scope of this article. If a board can support more than one programming tool, the convention is to return a programmer based on a LINK(`https://github.com/m-labs/migen/blob/master/migen/build/platforms/minispartan6.py#L120-L126', CODE(programmer) class variable) for the given board. This function can be omitted if no programmer fits, or one can be created on-the-fly using CODE(GenericPlatform.create_programmer).
Finalization
Some platforms Migen supports, such as the LINK(`https://github.com/m-labs/migen/blob/master/migen/build/platforms/lx9_microboard.py#L119-L131', LX9 Microboard), have a CODE(do_finalize) method. Finalization in Migen allows a user to defer adding logic to their design until overall resource usage is known. In particular, LX9 Microboard has an Ethernet peripheral, and the Ethernet clocks should use separate timing constraints from the rest of the design. The linked code detects whether the Ethernet peripheral was used using CODE(GenericPlatform.lookup_request("eth_clocks")), and adds appropriate platform constraints to the current design to be synthesized if necessary. If the Ethernet peripheral was not used in the design, the extra constraints are not added, and the CODE(ConstraintError) from CODE(lookup_request) is ignored.
Finalization operates on an internal Migen data structure called CODE(Fragment)s. CODE(Fragment)s require knowledge of Migen internals to use properly, so for the time being I suggest following the linked example if you need to add constraints conditionally. Of course, timing constraints and other User Constraints File data can be added at any point in your design manually using CODE(GenericPlatform.add_period_constraint) and CODE(GenericPlatform.add_platform_command) respectively.
iCEStick does not have any peripherals which need special constraints, and only a single clock; Migen will automatically add a constraint for the default clock. More importantly, in the case of IceStorm/iCEStick, only a global clock constraint is supported due to limitations in specifying constraints. Therefore, I omit the CODE(do_finalize) method for the iCEStick board file. However, one use I have found for CODE(do_finalize) in platforms compatible with IceStorm is to automatically instantiate pins with pullup resistors enabled. This gets around the limitations of Arachne PNR's constraints file format without needing to instantiate Verilog primitives directly in the top level of a Migen source file, and I can show code upon request.
I/O and Connectors
After defining a CODE(Platform) class for your board, all you need to do is fill in a list of CODE(_io) and CODE(_connectors) in your board file, pass them into your CODE(Platform)'s vendor-specific base class constructor, and Migen will take care of the rest!
As I stated before, CODE(io) and CODE(connectors) input arguments to the vendor-specific platform constructor are lists of tuples with a specific format. Let's start with an I/O tuple:
CODE_BLOCK(`(io_name, id, Pins("pin_name", "pin_name") or Subsignal(...), IOStandard("std_name"), Misc("misc"))')An CODE(io_name) is the name of the peripheral, and should match the string passed into the CODE(request) function to gain access to the peripheral's signals from Migen. CODE(id) is a number to distinguish multiple copies of identically-functioning peripherals, such as LEDs. For simple peripherals, CODE(Pins) is a helper class which should contain strings corresponding to the vendor-specific pin identifiers where the peripheral connects to the FPGA; in the case of IceStorm, there are just the pin numbers as defined on the package pinout. I will discuss CODE(Subsignal)s in the next paragraph. These tuple entries are used to create inputs and output names in the Migen-generated Verilog, and provide a variable-name to FPGA pin mapping in a Migen-generated User Constraints File (UCF)
Without going into excess detail`'FN(6), CODE(Subsignals) are a helper class for resources that use FPGA pins which can be seperated cleanly by purpose. The inputs to a CODE(Subsignal) constructor are identical to an I/O tuple entry, except with CODE(id) omitted. The net effect for the end user is that a resource is encapsulated as a class whose Migen CODE(Signals) are accessed via the class' members, i.e. CODE(comb += [my_resource.my_sig.eq(5)]). This is known as a CODE(Record) in Migen. CODE(Records) also come with a number of useful LINK(https://github.com/m-labs/migen/blob/master/migen/genlib/record.py, methods) for constructing Migen statements quickly. Think of them as analogous to C CODE(structs). It is up to your judgment whether an I/O peripheral should use CODE(Subsignals), but in general, I notice that Migen board files make heavy use of them.
The remaining inputs to an I/O tuple entry are optional. CODE(IOStandard) is another helper class which contains a toolchain-specific string that identifies which voltages/logic standard should use. And lastly, the CODE(Misc) helper class contains a space-separated string of other information that should be placed into the User Constraints File along with CODE(IOStandard). Such information includes LINK(`https://github.com/m-labs/migen/blob/master/migen/build/platforms/mercury.py#L35', slew rate) and whether pullups should be enabled. These are in fact currently ignored in the IceStorm toolchain, but for my own reference I have filled them in as necessary.
A connector tuple is a bit simpler:
CODE_BLOCK(`(conn_name, "pin_name, pin_name, pin_name,...")')CODE(conn_name) is analogous to CODE(io_name). The second element of a connector tuple is a space-separated string of pin names matching the vendor's format which indicates which pins on the FPGA are associated with that particular connector. Ideally, the pins should be listed in some order that makes sense for the connector.
By default, pins that are associated with connectors are not exposed by the CODE(Platform) via the CODE(request) method. Instead, a user needs to notify the platform that they wish to use the connector as extra I/O using the CODE(GenericPlatform.add_extension) method. Here is an example adding a LINK(https://blog.digilentinc.com/new-i2c-standard-for-pmods/, PMOD I2C peripheral) using CODE(add_extension):
CODE_BLOCK(`my_i2c_device = [ ("i2c_device", 0, Subsignal("sdc", Pins("PMOD:2"), Misc("PULLUP")), Subsignal("sda", Pins("PMOD:3"), Misc("PULLUP")) ) ] plat.add_extension(my_i2c_device) plat.request("i2c_device")')Note that adding a peripheral using CODE(add_extension) is similar to adding a peripheral to the CODE(io) list, except that the CODE(Pins()) element takes on the form CODE("conn_name:index"). CODE(conn_name) should match a tuple in the CODE(connectors) list, and CODE(index) is a zero-based index into the string of FPGA pins associated with the connector. This allows you to create peripherals on-the-fly that are (in theory) board and vendor-agnostic.
With the last concepts out of the way, let's jump right into creating the CODE(_io) and CODE(_connectors) list for our Platform. Each listed peripheral is implied to be a tuple inside CODE(_io = [...] or _connectors = [...]): CODE_BLOCK(`("user_led", 0, Pins("99"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("98"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("97"), IOStandard("LVCMOS33")), ("user_led", 3, Pins("96"), IOStandard("LVCMOS33")), ("user_led", 4, Pins("95"), IOStandard("LVCMOS33")),')
CODE(user_led)s are simple peripherals found on just about every development board; iCEStick has 5 of them, all identical in function (but the 5th one is green!). Resources with identical function that differ only in a pin should each be declared in their own tuple, incrementing the CODE(id) index.
Resource signal names are by convention; if a resource does not yet exist, it's up to you what you want to name the resource. However, I suggest looking at other board files for prior examples. CODE(user_led), CODE(user_btn), CODE(serial.rx), CODE(serial.tx), CODE(spiflash), and CODE(audio) are all commonly-used I/O names used between board files.
CODE_BLOCK(`("serial", 0, Subsignal("rx", Pins("9")), Subsignal("tx", Pins("8"), Misc("PULLUP")), Subsignal("rts", Pins("7"), Misc("PULLUP")), Subsignal("cts", Pins("4"), Misc("PULLUP")), Subsignal("dtr", Pins("3"), Misc("PULLUP")), Subsignal("dsr", Pins("2"), Misc("PULLUP")), Subsignal("dcd", Pins("1"), Misc("PULLUP")), IOStandard("LVTTL"), ),')Next we have another common peripheral- a UART/serial port. A UART peripheral makes sense to divide using CODE(Subsignal)s, since each pin has a distinct purpose. Although in practice most users will only use CODE(rx) and CODE(tx)`'FN(7), I include all possible pins just in case. I don't remember why I included CODE(PULLUP) as constraints information for a majority of pins. Note that it's perfectly okay to associate a constraint with all CODE(Subsignal)s at once, as I do for the (unused) CODE(IOStandard). CODE_BLOCK(`("irda", 0, Subsignal("rx", Pins("106")), Subsignal("tx", Pins("105")), Subsignal("sd", Pins("107")), IOStandard("LVCMOS33") ),')
The infrared port on iCEStick is another serial port, sans most of the control signals. I omit the optional I/O tuple/CODE(Subsignal) entries here, and define the CODE(IOStandard) similarly to the previous CODE(serial) peripheral.
CODE_BLOCK(`("spiflash", 0, Subsignal("cs_n", Pins("71"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("70"), IOStandard("LVCMOS33")), Subsignal("mosi", Pins("67"), IOStandard("LVCMOS33")), Subsignal("miso", Pins("68"), IOStandard("LVCMOS33")) ),')CODE(spiflash) and its CODE(Subsignal) have standardized, self-explanatory names. I suggest using these signal names when appropriate for all peripherals connected via an LINK(https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus, SPI bus). I don't remember why I added the CODE(IOStandard) per-signal instead of all-at-once here, but the net effect would be the same either way if IceStorm made use of CODE(IOStandard).
CODE_BLOCK(`("clk12", 0, Pins("21"), IOStandard("LVCMOS33")),')Clock signals should be included as well, with at least one clock's CODE(io_name) matching the CODE(default_clk_name). Migen may automatically CODE(request) a clock for your design if certain conditions are met; for now, assume you don't have to CODE(request) the clock.
CODE_BLOCK(`("GPIO0", "44 45 47 48 56 60 61 62"), ("GPIO1", "119 118 117 116 115 114 113 112"), ("PMOD", "78 79 80 81 87 88 90 91"), ')And lastly we have the connectors. The connector pins for CODE(GPIO0-1) and CODE(PMOD) are ordered in increasing pin order, which matches the order they are laid out on their respective connectors. This is a happy coincidence. Make sure to check your schematic and declare FPGA pins in connector order, not the other way around!
Building Our Design For Our "New" Board
Now that we have created our board file, we now need to write the remaining logic to attach the board's I/O to our Rot top level. Assuming the CODE(Rot) module is already defined, we can create a script that will synthesize our design like so:
CODE_BLOCK(`if __name__ == "__main__": plat = icestick.Platform() m = Rot() m.comb += [plat.request("user_led").eq(m.d1) for l in [m.d1, m.d2, m.d3, m.d4, m.d5]] plat.build(m, run=True, build_dir="rot", build_name="rot_migen") plat.create_programmer().flash(0, "rot/rot_migen.bin")')Once again, I will explain each line. It should be appended to the CODE(Rot) top level and then run using your Python 3 interpreter:
- CODE_BLOCK(`plat = icestick.Platform()
m = Rot()')
We create our platform and our CODE(Rot) module here. CODE(plat) contains a number of useful helper methods that help customize what is eventually sent to the synthesis flow.
- CODE_BLOCK(`m.comb += [plat.request("user_led").eq(m.d1) for l in [m.d1, m.d2, m.d3, m.d4, m.d5]]
')
This list comprehension is how we actually connect our I/O to the LED rotation module. CODE(`plat.request("user_led")') will create a Migen CODE(Signal) or CODE(Record) which can be used to assign to CODE(Signals) and CODE(Records) in an existing CODE(Module). CODE(GenericPlatform) does bookkeeping to figure out which CODE(Signals) should be considered I/Os to/from the generated Verilog top level (and consequently, mapped to a User Constraints File).
Repeatedly calling CODE(request) for a given resource name will return a new CODE(Signal) or CODE(Record) of the same type, throwing a CODE(ConstraintError) exception if there are no more available resources.
- CODE_BLOCK(`plat.build(m, run=True, build_dir="rot", build_name="rot_migen")
')
The CODE(GenericPlatform.build) function will emit Verilog output, a User Constraints File specific to your design, a batch file or shell script to invoke the synthesis flow, and any other files required as input to the synthesis toolchain. Optionally, Migen will invoke the generated script to create your design if input argument CODE(run) is true. CODE(build_dir) is self-explanatory, and CODE(build_name) controls the filename of generated files.
I pass in my top level CODE(Rot) CODE(Module) to the CODE(build) function. CODE(GenericPlatform) has internal logic to detect which signals were declared as I/O in the board file while generating Verilog input and output arguments.
- CODE_BLOCK(`plat.create_programmer().flash(0, "rot/rot_migen.bin")
')
This line is optional, but if included, Migen will invoke the CODE(iceprog) FTDI MPSSE programmer for iCEStick automatically after creating a bitstream using IceStorm. The first input argument is the start address to start programming, and the second argument is the name of the output bitstream. The name can be inferred from CODE(build_name) and the toolchain's default extension for bitstreams.
If all goes well, and you were following along, you should now have a blinking LED example on your iCEStick! The final iCEStick platform board file is LINK(https://github.com/m-labs/migen/blob/master/migen/build/platforms/icestick.py, here), which you can use as a reference, and I've made the CODE(Rot) top level available as a LINK(https://gist.github.com/cr1901/afc0442405fa4727802182ff9eac0e84, gist). Take a look at the output files Migen generated, including the output Verilog and User Constraints File, to get a feel of how our "shiny new" board file was used!
Happy Hacking!
If you have read up to this point, you now have some grasp on the Migen framework, and can now start using Migen in your own designs on your own development (or even deployed) designs!
Porting Migen to support your design takes relatively little effort, and you will quickly make up the time spent porting. Besides automating HDL idioms that are tedious to write by hand (such as FSMs), and generating Verilog that is free of certain bug classes, Migen saves time as it automates generating input files and build commands for your synthesis toolchain, and then invoking the synthesis flow automatically. Additionally, if you write your top-level CODE(Module) and glue code correctly, you can have a single HDL design that runs on all platforms that Migen supports, even between vendors, with much less effort than is required to do the same in Verilog alone!`'FN(8)
Migen is certainly a step in the right direction for the future of hacking with FPGAs, and I hope you as the reader give it a try with your Shiny New Development Board like I did, and see whether your experiences were as positive as mine.
Acknowledgements
I'd like to thank LINK(https://twitter.com/m_labs_ltd, Sébastien Bourdeauducq), the primary architect and maintainer of Migen, for looking over an initial version of this post and offering feedback.


"Faces" is an online puzzle game. It is written in HTML and JavaScript and was designed to be played in a web-browser
"Faces" is nothing at all like "Guess Who?", a popular game created by Ora and Theo Coster and first produced by MB Games then later by Hasbro.
The "Faces" game engine was written by Gareth Senior, first in Adobe Flash and ActionScript to tie in with a "1k Runaway" competition that ran on Power FM, and later refined as a standalone game.
Ask questions about the mystery face and receive a yes or no answer. With each question aim to eliminate as many faces as possible, click on a face to eliminate it (but you can click again to bring it back).
Once you have only one face left, that should be the mystery face... the game will tell you if it is....
Keep clicking until you find the face or until your time runs out.
With each successive level you'll get less and less time to find the mystery face.


NIGHTWATCH
A Film Review by James Berardinelli
RATING: ** OUT OF ****
United States, 1998 U.S. Release Date: 4/17/98 (wide) Running Length: 1:40 MPAA Classification: R (Body parts, violence, gore, nude corpses, sex) Theatrical Aspect Ratio: 2.35:1
Cast: Ewan McGregor, Patricia Arquette, Josh Brolin, Nick Nolte, Lauren Graham, Brad Dourif, John C. Reilly, Alix Koromzay Director: Ole Bornedal Producer: Michael Obel Screenplay: Ole Bornedal and Steven Soderbergh based on Bornedal's NATTEVAGTEN Cinematography: Dan Laustsen Music: Joachim Holbek U.S. Distributor: Dimension Films
I have no objection to violence and gore in the movies -- even extreme violence and gore -- as long as it serves a purpose (see GOODFELLAS, PULP FICTION, and even SCREAM for examples). In NIGHTWATCH, however, the most explicit and extreme instances of bloodletting are designed exclusively to titillate or horrify, depending on the viewer's tolerance and point-of-view. Apparently, director Ole Bornedal (remaking his own 1994 Danish hit, NATTEVAGTEN) recognized how thin and contrived his script was, and attempted to plug the holes with something warm, wet, and sticky. As either a slasher/horror flick or a murder mystery/thriller, NIGHTWATCH is a failure.
The film's distribution history -- or lack thereof -- is a tip-off that something is wrong. When a studio believes it has a winner, it rushes the product out to theaters as quickly as possible. With NIGHTWATCH, Miramax has taken exactly the opposite approach, holding the movie in stasis for 18 months (it was originally supposed to be released in October 1996). Anyone hoping for some quality entertainment will realize that this is not a good sign.
Most of the action, such as it is, takes place within a morgue, and Bornedal makes it a suitably creepy place, with long, silent corridors, flickering fluorescent lights, and dancing shadows. Atmosphere is NIGHTWATCH's strongest asset. When the new night watchman, Martin (Ewan McGregor), makes his first rounds through the eerily silent building, we sense his anxiety and the oppressive claustrophobia engendered by the place. Sadly, it's all downhill from there as the movie devolves into something that is simultaneously familiar and ridiculous.
Martin has taken this job because he believes the long hours of solitude will allow him time to study. His girlfriend, Catherine (an underused Patricia Arquette), doesn't like his temporary career choice, although his best friend, James (Josh Brolin), is fascinated by it. But James is a strange person with a penchant for playing bizarre and potentially-dangerous practical jokes, and his fascination with bodies and body parts may point to something dark within him. Meanwhile, Martin is on duty the night that the latest victim of a serial killer is brought in. The police detective in charge of the case, Cray (Nick Nolte, suffering a bad hair day), reveals to Martin that all of the victims have one thing in common: their eyes have been gouged out. Soon, as part of one of James' practical jokes, Martin comes into contact with a prostitute named Joyce (Alix Koromzay) who not only was the friend of one of the killer's victims, but may be in danger herself.
Aside from the atmosphere, which gradually dissipates as the plot takes off, NIGHTWATCH doesn't have much to offer. The identity of the killer is revealed too early (although, to be fair, it's easy to guess who it is about 30 minutes before the camera finally pans to his face) and the convoluted means by which he sets Martin up to take the fall are laughably absurd. Bornedal appears to be disregarding every aspect of police procedure and forensic technology by allowing something so blatantly outrageous to seem even vaguely possible. Hitchcock's movies often had plot holes, but never were they this obvious to viewers while the film was in progress (most were unearthed during post-screening discussions). Then there's the dialogue which, in trying to be profound, frequently ends up sounding silly. We get lines like this one: "If it can't be experienced, it's just meaningless chaos."
The acting is less-than-inspired. Ewan McGregor (sporting a hit- and-miss American accent), who has become a sought-after commodity following his outing in TRAINSPOTTING (so much so that George Lucas pegged him to play Obi-Wan Kenobi in the new STAR WARS film), has a few effective scenes, but, for the most part, he's bland. Josh Brolin is over-the-top, but I suppose that's the intention. And Nick Nolte gives what is likely his worst performance since ANOTHER 48 HOURS. The only one who's any good is Brad Dourif as a doctor with the personality of a ghoul.
My patience for dumb thrillers, where the audience is always about ten steps ahead of the characters, is wearing very thin. If not for Bornedal's stylish approach to the material and a couple of effectively chilling sequences, NIGHTWATCH would have been a complete waste of time and effort. As it is, it's still not worth more than an unenthusiastic video recommendation, which is the medium in which most interested viewers will end up seeing it, since its box office life is likely to be deservedly short.
Copyright 1998 James Berardinelli
- James Berardinelli e-mail<EMAIL_ADDRESS>Now with more than 1400 reviews... The ReelViews web site: http://movie-reviews.colossus.net/
"My belief is that no movie, nothing in life, leaves people neutral.
-- David Puttnam
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Easy CSS Grids
Inspired by flow.gs
Select the desired number of columns, the size of gutters and padding, and space between rows to generate lightweight CSS for a custom grid system
Select the desired number of columns, the size of gutters and padding, and space between rows to generate lightweight CSS for a custom grid system
Select number of columns
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Click below to select the code, then copy it into a CSS file
Click below to select the code, and copy it into an HTML file as a skeleton for your page

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A mimic of the Amazon Dash Button using Python on a Raspberry Pi. Pi-Order holds 4 products at a time and is reprogrammable anytime with new products via a NodeJS web application. More Info: Pi-Order Github. (Click images below to enlarge)
Jayson Perkins | Pi-Order | Portfolio | Resume | Github
 A mimic of the Amazon Dash Button using Python on a Raspberry Pi. Pi-Order holds 4 products at a time and is reprogrammable anytime with new products via a NodeJS web application. More Info: Pi-Order Github. (Click images below to enlarge)


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the purpose of this specific chapter is to set the stage, and answer the following questions:
[[outline/outline]]
[[kintsch_von_dijk_strategies_understanding]]
[[kitsch_van_dijk_towards_model_text_comprehension]]
this section focuses on the applied practice of describing things to the computer. who does it, how they do it, and how they relate to it. it would particularly focus on the historical/sociological aspect of it, to start highlighting that there might be one concept of computing, but the reality of interacting with and thinking in terms of computation is not unidimensional. it establishes different categories of people writing source code: researchers, academics (teachers+students), professionals, hackers, amateurs and artists.
Engelbart’s NLS expanded the view of programmers from business analysts and artiﬁcial intelligence researchers to any information worker. Smalltalk originally focused on children as programmers. Hypercard was developed and distributed at Bill Atkinson’s insistence that “end users” need programming capabilities. (from this). And then they mention diy hacker and maker culture, beginner friendly arduino, max for live and youtube studio (I must define which ones I include, which ones I exclude, and why maybe the definition I want is one where there is a clear definition between programmer and end user?)
a short history of programmers:
he legacy of an earlier tradition of celebratory accounts of “great men,” pioneering machines, and important “firsts” is still very much with us, particularly in popular and journalistic histories. (Nathan Esmenger 2007, Power to the People, Toward a Social History of Computing)
also mention that there is a parallel history of soviet computing (james cortada article) but the domination of the US renders this moot (argue more specifically why)
essentially there is academia/government
then business (IBM, Fortran, personal calculators, visicalc, lotus 123)
then hobbyists (basic)
then academics (history of research, to some extent -> could it be said that universities are a bit less prone to fundamental research today now that they need to do marketable stuff? is this even relevant?)
there might also be a history of artists
programming links technology and mathematics in a very specific way
ref: lammers, programmers at work
[[petre_blackwell_programmers_mental_imagery]]
I argue that aesthetics can help grasp software’s multitude.
There’s also this blog post about all the voices in source code. All the programmers that have given insight, all the copy paste from SO, etc.
see black, p. 101 for a reference to software management literature
[[hayes_cultures_od_code]]
[[cox_mclean_coding_praxis]]
[[knuth_art_of_programming_vol_1]]
[[martin_clean_code]]
[[mcbreen_software_craftsmanship]]
the underhanded c code contest
[[graham_hackers_and_painters]]
[[mateas_montfort_box_darkly]]
[[paloque_berges_poetique_des_codes]]
this section extracts the features that are recurring in the discourses around beauty in source code. it does so by looking at how practical examples and theoretical statements either converge or diverge and how such statements are modulated by the aforeidentified communities. the common point identified, via the subjectivity of writing code, is the concept of the craft.
beauty as a lack of ambiguity, as efficient achievement of an aim (aim of frustration/clarity/imagination)
[[chandra_geek_sublime]]
[[cramer_words_made_flesh]]
[[mitchell_art_of_computer_graphics_programming]]
this first approach, by comparing both source and comment at the same time (taking texts which are explicitly described as being beautiful), explicitly highlights the requirements for source code to be beautiful.
[[pugh_beauty_simplicity]]
[[pineiro_aesthetics_of_code]]
[[cox_the_aesthetics_of_generative_code]]
[[mattt_as_we_may_code]] -> this is somewhat almost architecture, brings a hint
[[mclennan_aesthetics_software_engineering]]
[[pressman_software_engineering_practicioners_approach]]
this second approach contrasts with the functional component of the first one, but nonetheless stands in relationship with it. the creative beauty, by defying traditional beauty standards, does help us highlight, through deviance, what the norm is. these texts on “creative beauty” include the classical perl poetry, code poems, IOCC, code poetry contest, etc.
[[black_art_of_code]] [[raley_code_surface_code_depth]]
[[sondheim_codework]] [[ward_authorship_of_generative_code]] [[knuth_literate_programming]]
[[mclennan_elegance_software_design]]
beautiful proofs in geometry?
Elegance: Through a single lens, it communicates the problem it solves and the machinery of its solution.
[[fuller_software_elegance]] [[spinellis_reading_writing_code]] [[iverson_notation_as_tool_for_thought]]
this subsection also allow us to introduce the concept of craftsmanship and integrate it within a larger tradition of sennett/de certeau/rancière, and connect the practice of programmer to a longer history of craft, a history which in itself has beauty standards TODO
https://dannorth.net/2011/01/11/programming-is-not-a-craft/
[[sennett_the_craftsman]]
the zen of python could tie in to that tradition
this includes practical tips and software craftsmanship
“to grok” -> an expression which means “to grasp vaguely, to have an intuitive understanding of”
[[jones_reckoning_with_matter]]
this section focuses on “you will know when you see it”
Implementation as: THIS GOES WITH GOODMAN
explicit
tacit
practice is synthetic method, a method which regroups, which puts together.
[[freeman_science_as_a_craft]]
[[mills_intellectual_craftsmanship]]
craft might also start to connect to the aesthetics of the everyday. particularly, thomas leddy has an article called “Everyday surface aesthetic qualities: neat, messy, clean, dirty” that might be very good


Koala is a fast, flexible and modularized modern language.
Koala supports interactive, compile and run mode.
This is 'Hello World' in interactive mode.
[james@host ~]$ koala koala 0.9.1 [GCC 8.3.0] on Linux/x86_64 5.0.0-32-generic > "Hello, World" Hello World >
download source code
Our home site is at github.com, you can go Home.


This menu command will copy a URL-type reference to the current message to the clipboard ready for posting into a message. You can also create a link by dragging a message from the thread window to an edit window


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{% load static conf_tags %}
Use this document as a way to quickly start any new project. All you get is this text and a mostly barebones HTML document.


Content
Functional Programming
Reactive Programming, RxJS
Workshop
Functional Programming
Imperative vs Declarative
Imperative
Declarative
Control Flow (if, where, for)
Computation
Many side effects
No side effects
Object Oriented
Functional
State and Data
No program state changes
Immutable Data Structures
Like mathematical functions
Ouput of a function only depends on input
Recursions instead of looping
Benefits
Comprehension
Testability
Behavioral Predictability
Simple to Parallelize
Downsides
Synchronous Performance
Working Memory Usage
Cohesion in big code bases
Multi-paradigm Languages
Can benefit from both
Java/JavaScript Streams
Reactive Extensions
Kotlin
RxJS - Reactive Extensions for JavaScript
Reactive Programming
Static or dynamic data-streams
Propagation of change
Pipes
Streaming operators
Key Concepts
Observables are Objects that can be subscribed to
Subscriptions
call-by-need
Completing an observable
Reactive Data Transformation
Common Fallacies
Nested subscribe statements
Subscribe all the things!
Not cleaning up subscriptions
Not completing observables
Returning new observables every time
Performance
Workshop


By default, jMock is not thread safe and so its mock objects should not be called from multiple threads. However, people frequently do use it this way. They may want to use mock objects when stress-testing the synchronisation of an object they've written and tested using the deterministic executor. Or they may want to test a class that they are implementing with a third-party library that calls into their code from multiple threads. To use jMock with multiple threads, you have to plug a different ThreadingPolicy into the Mockery.
A ThreadingPolicy is an object that the Mockery uses to synchronise access to its state. A ThreadingPolicy wraps a decorator around every Mock Object before it is imposterised and so intercepts all mocked calls entering the Mockery and all results and exceptions that it returns. The default ThreadingPolicy complains if the mock objects are used by more than one thread. But if you want to test multithreaded code you can plug a Synchroniser into the Mockery instead.
You use the Synchroniser like this:
Mockery mockery = new JUnit4Mockery() {{ setThreadingPolicy(new Synchroniser()); }};
Now any mock objects created by the Mockery can be safely invoked from multiple threads. It's that easy. The Synchroniser has other features that help test multithreaded code, that are described elsewhere in the cookbook.
Testing multithreaded code is made difficult because failures do not get thrown on the test thread. The test framework cannot easily trap those exceptions and fail the test with a helpful diagnostic message. Often tests fail with a timeout, which has no message explaining why the timeout was exceeded. Or, an assertion on the test thread fails because an error that occurred on a background thread left the object under test in an invalid state, but information about the root cause of the failure is lost. JMock has a few mechanisms to help with this.
JMock captures the first expectation failure that is thrown from a mock object. If the error is swallowed, either by a background thread or by a try/catch block in the foreground thread, the test will continue running and the mockery will throw the error when the test asserts that all expected calls have been made. This is usually done automatically at the end of the test.
The Synchroniser's wait methods also fail fast and rethrow expectation violations that occur on background threads. A test can wait for the system to enter an expected state but if it does not do so because the system violated an expectation, the wait will immediately abort and throw the error that originally reported the violated expectation.
The Mockery records a trace of all the invocations that any mock object has received during the test and includes the trace recorded so far when it throws an expectation error.
The combination of failing fast, reporting the root cause of failure, and reporting the sequence of calls that led to the failure makes diagnosis much easier than a bare "test timed out" message.


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Toolboxx is a public and open archive for APIs and tools that worth to share. Toolboxx allows you to discover new APIs and tools to improve your work. Please feel free to contribute by suggesting new APIs and tools.


import {MatInputModule} from '@angular/material/input';
MatInput
Selector: input[matInput] textarea[matInput] select[matNativeControl] input[matNativeControl] textarea[matNativeControl]
Exported as: matInput| Name | Description |
|---|---|
@Input()
|
An object used to control when error messages are shown. |
@Input()
|
Whether the element is readonly. |
@Input()
|
Input type of the element. |
|
Whether the component is in an error state. |
| focus | |
|---|---|
|
Focuses the input. |
|
| Parameters | |
|
options? FocusOptions
|
|
| updateErrorState | |
|---|---|
|
Updates the error state based on the provided error state matcher. |
MAT_INPUT_VALUE_ACCESSOR
This token is used to inject the object whose value should be set into MatInput
. If none is
provided, the native HTMLInputElement
is used. Directives like MatDatepickerInput
can provide
themselves for this token, in order to make MatInput
delegate the getting and setting of the
value to them.
const MAT_INPUT_VALUE_ACCESSOR: InjectionToken<{ value: any; }>;


www.redips.net
Drag and drop table content with JavaScript
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here
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table
drop
down
menu
with
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Table2
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Enable dropping to already taken table cells
Confirm before delete object


projects 25 + 5 clock countdown web app fish store manager react firebase web app to manage fish store drum machine react web app to play drums calculator calculator implemented using react apple homepage replica of apple.com more at and


Control Flow Verification Tool Design Document¶
Objective¶
This document provides an overview of an external tool to verify the protection
mechanisms implemented by Clang’s Control Flow Integrity (CFI) schemes
(-fsanitize=cfi
). This tool, provided a binary or DSO, should infer whether
indirect control flow operations are protected by CFI, and should output these
results in a human-readable form.
This tool should also be added as part of Clang’s continuous integration testing framework, where modifications to the compiler ensure that CFI protection schemes are still present in the final binary.
Location¶
This tool will be present as a part of the LLVM toolchain, and will reside in the “/llvm/tools/llvm-cfi-verify” directory, relative to the LLVM trunk. It will be tested in two methods:
- Unit tests to validate code sections, present in “/llvm/unittests/llvm-cfi- verify”.
- Integration tests, present in “/llvm/tools/clang/test/LLVMCFIVerify”. These integration tests are part of clang as part of a continuous integration framework, ensuring updates to the compiler that reduce CFI coverage on indirect control flow instructions are identified.
Background¶
This tool will continuously validate that CFI directives are properly implemented around all indirect control flows by analysing the output machine code. The analysis of machine code is important as it ensures that any bugs present in linker or compiler do not subvert CFI protections in the final shipped binary.
Unprotected indirect control flow instructions will be flagged for manual review. These unexpected control flows may simply have not been accounted for in the compiler implementation of CFI (e.g. indirect jumps to facilitate switch statements may not be fully protected).
It may be possible in the future to extend this tool to flag unnecessary CFI directives (e.g. CFI directives around a static call to a non-polymorphic base type). This type of directive has no security implications, but may present performance impacts.
Design Ideas¶
This tool will disassemble binaries and DSO’s from their machine code format and
analyse the disassembled machine code. The tool will inspect virtual calls and
indirect function calls. This tool will also inspect indirect jumps, as inlined
functions and jump tables should also be subject to CFI protections. Non-virtual
calls (-fsanitize=cfi-nvcall
) and cast checks (-fsanitize=cfi-*cast*
)
are not implemented due to a lack of information provided by the bytecode.
The tool would operate by searching for indirect control flow instructions in
the disassembly. A control flow graph would be generated from a small buffer of
the instructions surrounding the ‘target’ control flow instruction. If the
target instruction is branched-to, the fallthrough of the branch should be the
CFI trap (on x86, this is a ud2
instruction). If the target instruction is
the fallthrough (i.e. immediately succeeds) of a conditional jump, the
conditional jump target should be the CFI trap. If an indirect control flow
instruction does not conform to one of these formats, the target will be noted
as being CFI-unprotected.
Note that in the second case outlined above (where the target instruction is the fallthrough of a conditional jump), if the target represents a vcall that takes arguments, these arguments may be pushed to the stack after the branch but before the target instruction. In these cases, a secondary ‘spill graph’ in constructed, to ensure the register argument used by the indirect jump/call is not spilled from the stack at any point in the interim period. If there are no spills that affect the target register, the target is marked as CFI-protected.
Other Design Notes¶
Only machine code sections that are marked as executable will be subject to this analysis. Non-executable sections do not require analysis as any execution present in these sections has already violated the control flow integrity.
Suitable extensions may be made at a later date to include anaylsis for indirect control flow operations across DSO boundaries. Currently, these CFI features are only experimental with an unstable ABI, making them unsuitable for analysis.


Address: , ,
Phone:
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Email:
Founder:
Current employees of this company: ,
Former employees (alumni) of this company: ,


+++ title = "About Orbiting.com" slug = "about" +++
A simple messaging app for your eyeballs.
Orbiting is a simple visual communication app for groups.
A person is able to use it to type and display the message to those around. We want to create a very simple experience that doesn't require a lot of tech knowledge or experience.
Made with love by Harper Reed, Nick Ng, and Christine Sun Kim
Please send us feedback. We want it! feedback@orbiting.com


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Customer Service Ticketing System
User Story: As a Customer Rep, I want to ensure tasks requiring developer work don't get lost, So I can resolve issues in a timely fashion
Solution: Built a JIRA project to use as a ticketing system
Why I chose it: Ticketing systems ensure that any open tasks remain visible. Because JIRA is already part of our developers' workflow, it is easy to move actionable tickets into the right queues to get addressed.
How we're doing: In two months, we've closed 120 tickets and significantly improved our communication. We were also able to diagnose a handful of recurring problems and implement dev fixes for them.
Solution: Built a JIRA project to use as a ticketing system
Why I chose it: Ticketing systems ensure that any open tasks remain visible. Because JIRA is already part of our developers' workflow, it is easy to move actionable tickets into the right queues to get addressed.
How we're doing: In two months, we've closed 120 tickets and significantly improved our communication. We were also able to diagnose a handful of recurring problems and implement dev fixes for them.
Advertise Future Litters
User Story: : As a Breeder, I want to advertise puppy litters I'm expecting in the near future, So that I can build up a waiting list of qualified buyers
Solution: Upgrade the current default "Contact me for Future Litters" message to be configurable (i.e. "I am expecting a French Bulldog litter in April 2017")
Why I chose it: The work is a low LOE that provides enough value to be an MVP. We plan to test this in beta with a select group of Breeders and get feedback to determine what we can do in future iterations.
Solution: Upgrade the current default "Contact me for Future Litters" message to be configurable (i.e. "I am expecting a French Bulldog litter in April 2017")
Why I chose it: The work is a low LOE that provides enough value to be an MVP. We plan to test this in beta with a select group of Breeders and get feedback to determine what we can do in future iterations.
Ongoing Tasks
My typical day includes (and is definitely not limited to):
- Prioritizing the backlog & roadmap
- Unblocking obstacles for dev & design
- Meeting with stakeholders to discuss needs
- Writing technical specs to convey needs
- Analyzing revenue & activity metrics
- Presenting revenue projections to executives


| Photo | Food | Description | Price |
|---|---|---|---|
| Salad | Fresh, delicious Cobb Salad | $7.99 | |
| Burger | 1/4 lb grass-fed burger with choice of cheese | $6.99 | |
| Chicken Salad Sandwich | Our world famous chicken salad on a bagel with homemade pickles | $8.99 | |
| Buffalo Chicken Sandwich | Spicy fried chicken on a brioche bun | $10.99 | |
| Fries | Hand cut potatoes lightly fried and seasoned | $1.99 | |
| Soda | Regular, diet, orange, or root beer | $1.00 |


--- layout: page ---
Title: |
{{ page.moniker }} |
Department: |
{{ page.department }} |
Email: |
{{ page.email }} |
Phone: |
{{ page.phone }} |
Location: |


Project 3-4: Member Registration
Name:
Address:
Age:
Profession:
Residential status:
Resident
Non-Resident


A
- About us
- About us (library)
- About us (Quality Assurance & Accreditation Department)
- Academics
- Academic Advisement
- Academic Calendar
- Access E-Mail
- Activities (Quality Assurance & Accreditation Department)
- Accounting
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- Administration & Committees (College of Business)
- Advancement Office
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Before Change
assert len(limits) >= num - 1
limits = limits[:num-1] + [float("inf")]
factors = np.ones(num, dtype=int)
while True:
// Calculate the last factor.
factors[-1] = idivc(value, np.prod(factors[:-1]))
if np.prod(factors) == value \
and np.all(np.less(factors, limits)):
yield tuple(np.copy(factors))
// Update the first n - 1 factor combination, backwards.
After Change
// Calculate the last factor.
factors[-1] = idivc(value, prod(factors[:-1]))
if prod(factors) == value \
and all(f <= l for f, l in zip(factors, limits)):
yield tuple(factors)
// Update the first n - 1 factor combination, backwards.


General References for Making Documents Accessible
The references on this page are generally broken up into the following categories:
- Section I. Authoritative Agencies
- Section II. Proprietary Systems For Consideration
- Section III. Browser Accessibility Features (Chrome, Firefox, IE)
- Section IV. Testers, Simulators and Visualizers
- Section V. Blogs, Articles, How-To
- Section VI. WebSites
- Section VII. Nitty-Gritty
This page of references is for general background knowledge. For specific "how-to" skills for technologies used here at this institution -- Adobe, Microsoft, and Kiosks, -- remember to check the main pages Adobe, Microsoft, and Kiosks. These three pages are focused on tips, tricks, and techniques that are targeted to our friends here.


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In the interest of fostering an open and welcoming environment, we as contributors and maintainers pledge to making participation in our club, our projects and our community a harassment-free experience for everyone, regardless of age, body size, disability, ethnicity, gender identity and expression, level of experience, nationality, personal appearance, race, religion, or sexual identity and orientation.
Examples of behavior that contributes to creating a positive environment include:
Examples of unacceptable behavior by participants include:
Other conduct which could reasonably be considered inappropriate in a professional setting
Admins and Moderators are responsible for clarifying the standards of acceptable behavior and are expected to take appropriate and fair corrective action in response to any instances of unacceptable behavior. Moderators have the right and responsibility to remove, edit, or reject comments, commits, code, wiki edits, issues, and other contributions that are not aligned to this Code of Conduct, or to ban temporarily or permanently any contributor for other behaviors that they deem inappropriate, threatening, offensive, or harmful.
This Code of Conduct applies both within project spaces and in public spaces when an individual is representing the project or its community. Examples of representing a project or community include using an official project e-mail address, posting via an official social media account, or acting as an appointed representative at an online or offline event. Representation of a project may be further defined and clarified by the Admin and Moderators.
Instances of abusive, harassing, or otherwise unacceptable behavior may be reported by contacting any of the Moderators or the Admin either through any of our communication channels or in person. All complaints will be reviewed and investigated and will result in a response that is deemed necessary and appropriate to the circumstances. The project team is obligated to maintain confidentiality with regard to the reporter of an incident. Further details of specific enforcement policies may be posted separately. Admin or Moderators who do not follow or enforce the Code of Conduct in good faith may face temporary or permanent repercussions as determined by the members of the Community.


--- title: Commission for Rural Communities layout: gb ---
| Resource | Fetch | Format | Columns | Data | Valid | Entries | Oldest | Latest | Total (GBP) | |
|---|---|---|---|---|---|---|---|---|---|---|
| Spend over £25,000 in the Commission for Rural Communities | ||||||||||
| May 2010 return | ✔ | ✔ | ✘ | ✘ | ✘ | 0 | ||||
| July 2010 return | ✔ | ✔ | ✔ | ✔ | ✔ | 1 | 2010-07-21 | 2010-07-21 | 31654.5 | |
| April 2010 return | ✔ | ✔ | ✔ | ✔ | ✔ | 1 | 2010-04-28 | 2010-04-28 | 27202.49 | |
| August 2010 return | ✔ | ✔ | ✔ | ✔ | ✔ | 1 | 2010-08-05 | 2010-08-05 | 27175.93 | |
| September 2010 return | ✔ | ✔ | ✘ | ✘ | ✘ | 0 | ||||
| October 2010 return | ✔ | ✔ | ✘ | ✘ | ✘ | 0 | ||||
| June 2010 return | ✔ | ✔ | ✔ | ✔ | ✔ | 1 | 2010-06-02 | 2010-06-02 | 60000.0 |
| Resource/Stage | Error |


{% extends 'gedata/base.html' %} {% load humanize %} {% block title %}Gene Expression and Functional Connectivity{% endblock %} {% block content %}
The earlier analyses each focused on a complete sample from a particular donor. We now focus on a subset of these many analyses that used split-half resampling. All split halves are based on all donors (sub-all), all hemispheres (hem-A), but only samples that can map into left hemisphere Glasser parcellations (samp-glasser), and the Fornito/Arnatkeviciute selection of probes (prob-fornito). This results in a starting expression similarity matrix with 15,745 probes and 1,280 samples, [15745, 1280], for all split-half experiments. In some, we used the 1,280 Glasser-compatible original AHBA wellids for sample locations (parby-wellid) and in others we averaged groups of wellids into 180 Glasser parcels (parby-glasser), although only 177 are represented. In some, we split the sample in half by randomly dividing wellids (splby-wellid), leaving some parcels empty and some parcels with fewer samples, and in others we split the sample by Glasser parcels (splby-glasser), leaving fewer parcels, each with all possible wellids together. These were also described in email May 13th, 2019. And obviously, the wellid-parcellated matrices are larger and take longer to run.
Some variables were also altered to allow comparisons of results under different paradigms. We compared these expression similarity matrices with connectivity similarity matrices from two datasets: the HCP data, parcellated into Glasser parcels (comp-glasserconnectivitysim) or left as wellids (comp-hcpniftismoothconnsim); and the INDI NKI data, parcellated into Glasser parcels (comp-indiglasserconnsim) or left as wellids (comp-indiconnsim). In the parcellated HCP data, distance-masking was applied at 16mm (mask-16), 32mm (mask-32), and 64mm (mask-64) thresholds for comparison with unmasked (mask-none) data. There is a mix of 'once' and 'smrt' algorithms, all 'max' some 'min'
So, the SRS-adjusted and properly-masked available comparisons at this point in time (each with 16 train/test splits and 256 permutations of each shuffle type) are:
The primary result is in bold, based on an earlier conversations. Each partially bolded collection has only one variable altered from the primary. We can use each of these to see how changing that particular variable would have changed our primary results.
The following results were NOT SRS-adjusted, but are available from backup. Ask Mike if you're interested.


Kristen Hopper
About Me
I recently had a desire for a career change. After much thought and discussion with people who know and love
me, I came to the realization that programming would be a great field for me to be in. I think analytically
and already have experience as an editor putting me in an ideal position to find and correct bugs in code.
Education
- Brigham Young University B.A. English Language Class of 2011
- Epicodus Ruby & React Track Certificate November 2021
Experience
- Sirsi Dynix Technical Writer 11/2011-9/2012
- Wrote and edited software helps and release notes for updated versions of library software
- Worked and collaborated with a team of developers and engineers to provide quality product
- Communicated with clients to make changes to documents based on customer preferences and recommendations
- EditMyEnglish.com Contract Editor 9/2011-1/2019
- Edited academic, professional, and cultural papers for accurate and concise English
- Interacted with clients to deliver a final product that exceeded expectations
Interests
- Marvel Cinematic Universe
- Star Wars
- Miraculous: Tales of Ladybug and Cat Noir
- Going for walks
- Reading science fiction and fantasy novels
Hobbies
- Music: Piano and Voice
- Crocheting
- Podcast: Sistertaku
- My sister and I record a podcast where we talk about different anime shows. I edit the podcast using
Audacity.
Skills
- Type 80 wpm
- Copyediting
- HTML and CSS
Projects
This is the first webpage I created using HTML. It is about a fictional "Michael" and his favorite things.
This webpage uses HTML and CSS and was made to practice the use of cascading styles.
This webpage uses HTML and CSS to was made to practice the use of divs and spans.
This webpage uses HTML and CSS and was made to practice floats and boxes.


skywalker
Here below is a list of tools in skywalker
.
checkpoint
checkpoint(key, argvals=False, tempdir=False, refresh=False, verbose=True)
Decorator to checkpoint the output of a function to hdf5 files. Add @skywalker.checkpoint(filename)
before a function and the output will be stored to file and computed only if necessary. Deeply inspired by the ediblepickle module. Example:
def test_checkpoint():
import time
@skywalker.checkpoint('checkpoint',argvals=True)
def long_calculation(x,arg=10):
time.sleep(5)
return x,arg
print(long_calculation(2,arg=10))
print(long_calculation(2,arg=10))
print(long_calculation(1,arg=20))
Options are:
argvals
. If True all args will be listed in the file name. If False (default), none of them will. If, e.g., [0,3] only the first and the fourth arg/kwarg will be listed.refresh
. If True, disable checkpointingtempdir
. If True, store in./tmp
dontprint
dontprint(self)
A context manager to suppress all printouts, both stdout and stderr. Full credit goes to randlet. Example:
def test_dontprint():
def message():
print("Function is printing")
print("Main is printing")
message()
with skywalker.dontprint():
message()
plot
plot(function)
This is a decorator to handle various matplotlib options, including saving the file to pdf. Just add @skywalker.plot
to a function that returns a matplotlib figure object. If a list of figure objects is returned, save a single pdf with many pages. Example:
@skywalker.plot
def test_plot():
import matplotlib.pyplot as plt
x=range(100)
y=range(100)
fig = plt.figure(figsize=(6,6))
ax=fig.add_axes([0,0,1,1])
ax.plot(x,y)
return fig
processify
processify(func)
Decorator to spawn a new process every time a function is called. Full credit for this incredibly nice piece of code goes to schlamar; for a nice description see here.
def test_processify():
@skywalker.processify
def tricky():
return os.getpid()
print(os.getpid(), tricky(), tricky())
singleton
singleton(*args, **kwargs)
Decorator to implement the singleton pattern in Python. A single instance of the decorated class can exist at any time. If multiple instances are initiated, identical pointers are returned. Here I use the singleton_decorator module.
def test_singleton():
@skywalker.singleton
class simple(object):
def simple(self,x):
return x
s1=simple()
s2=simple()
print(s1,s2, s1==s2)
timer
timer(function)
Decorator to print a function execution time to screen. Example:
@skywalker.timer
def test_timer():
x = range(int(1e7))


 This must have
been a pirate hangout, because I just found
some treasure!
But I can only carry one up to the surface.
They are both beautiful, but which one do I prefer?
Daminen Hirst "For the Love of God" 2007
>
>


Every web application has some menu to navigate between pages/screens. ASP.NET Boilerplate provides a common ifrastructure to create and show menu to users.
An application may be consists of different modules and each module can have it's own menu items. To define menu items, we need to create a class derived from NavigationProvider.
Assume that we have a main menu as shown below:
Here, Administration menu item has two sub menu items. Example navigation provider class to create such a menu can be as below:
public class SimpleTaskSystemNavigationProvider : NavigationProvider
{
public override void SetNavigation(INavigationProviderContext context)
{
context.Manager.MainMenu
.AddItem(
new MenuItemDefinition(
"Tasks",
new LocalizableString("Tasks", "SimpleTaskSystem"),
url: "/Tasks",
icon: "fa fa-tasks"
)
).AddItem(
new MenuItemDefinition(
"Reports",
new LocalizableString("Reports", "SimpleTaskSystem"),
url: "/Reports",
icon: "fa fa-bar-chart"
)
).AddItem(
new MenuItemDefinition(
"Administration",
new LocalizableString("Administration", "SimpleTaskSystem"),
icon: "fa fa-cogs"
).AddItem(
new MenuItemDefinition(
"UserManagement",
new LocalizableString("UserManagement", "SimpleTaskSystem"),
url: "/Administration/Users",
icon: "fa fa-users",
requiredPermissionName: "SimpleTaskSystem.Permissions.UserManagement"
)
).AddItem(
new MenuItemDefinition(
"RoleManagement",
new LocalizableString("RoleManagement", "SimpleTaskSystem"),
url: "/Administration/Roles",
icon: "fa fa-star",
requiredPermissionName: "SimpleTaskSystem.Permissions.RoleManagement"
)
)
);
}
}
A MenuItemDefinition can basically have a unique name, a localizable display name, a url and an icon. Also,
INavigationProviderContext has methods to get existing menu items, add menus and menu items. Thus, different modules can add it's own items to the menu.
There may be one or more menus in an application. context.Manager.MainMenu references the default, main menu. We can create and add more menus using context.Manager.Menus property.
After creating the navigation provider, we should register it to ASP.NET Boilerplate configuration on PreInitialize event of our module:
Configuration.Navigation.Providers.Add<SimpleTaskSystemNavigationProvider>();
IUserNavigationManager can be injected and used to get menu items and show to the user. Thus, we can create menu in server side.
ASP.NET Boilerplate automatically generates a javascript API to get menu and items in client side. Methods and objects under abp.nav namespace can be used for this purpose. For instance, abp.nav.menus.MainMenu can be used to get main menu of the application. Thus, we can create menu in client side.
ASP.NET Boilerplate templates uses this system to create and show menu to the user. Try to create a template and see source codes for more.


| DOSE: T+ 0:00 |
1.5 g |
oral |
Smarts - Phenibut |
| T+ 1:30 |
500 mg |
oral |
Smarts - Phenibut |
| T+ 2:00 |
1 g |
oral |
Smarts - Phenibut |
In the nootropics circles Phenibut is discussed as being an anti-anxiety chemical, that has some nootropic benefit. While I can't attest to Phenibut's nootropic benefit my experience certainly supports its 'anti-anxiety' effect...
I took 3g which was a mistake, and well outside the range of therapeutic benefit. This drug had a very slow onset. Don't make the same mistake I did by misreading the slow onset of this chemical and increasing the dose.
8:30PM-I took 1.5g thinking I'd finish up some work on my laptop and hit the hay. The powder went down easy enough.
10:00PM-I noticed the time, and paused to consider whether or not I was feeling anything. I 'felt' something, but honestly I thought it had to be a placebo effect. So I took another .5g. I get back on my computer.
10:30PM-I now decide that I am feeling something (...a little relaxed?). But the feeling is very slight. So, I decided to take another 1g. I get back on my computer.
11:00PM-The effect is stronger, noticeable, and pleasant, but no way near as strong as my experience with benzo's. It also had a different feel to it than benzodiazepine. At this point I finish up my work and watch some television.
12:00PM-The effect of Phenibut has been more or less stable for the last hour. I could go to sleep, but it don't feel 'tranquilized'.
12:30AM-At this point I decided 'this must be...it.' The 'relaxed' feeling is mild, definitely not 'tranquillized' in any way. From 11:00-12:30 I noticed no change in intensity, very mild plateau. If this is all Phenibut is at 3g.....not horrible bang for the buck, but no way as strong as billed. I go to bed and fall asleep normally.
7:00AM--my alarm wakes me up, which is usual for me. Typically no matter how late I stayed up the night before I wake up right before it goes off . All I can say about how I felt is 'wow....I REALLY feel funky ', while pleasant, its not how you want to feel on a workday morning. The feeling was VERY pronounced, and like nothing I've felt before. I was a little dizzy, not falling over dizzy, and not unpleasantly dizzy (...if that makes any sense). My mind felt good, but not motivated to focus on anything. After trying to clear the 'fog'(?) with some coffee, I decided I'd work from home instead of driving into the office under the influence of this happy fog.
12:00PM--The morning was interesting, not completely unproductive, but definitely not 'peak' mental performance. The dizzy 'happy fog' effect declined steadily over the morning. By the afternoon I could turn off the fog-lights, I was feeling like my old self. Not a completely wasted day.
I'll use Phenibut again. But next I'll try perhaps 1.0g and take it earlier in the evening. My 'peak' must have occurred sometime after I went to sleep. The effects were much stronger in the morning than the night before, and they declined steadily throughout the morning. From this experience I don't think I could say what the 'peak' felt like, but if the morning is any indication it must have been very intense.
My advice, resist the urge to increase the dose during the long ramp-up phase unless you can afford the 12-18 hours of 'happy fog' time. If you go recreational with this chemical be prepared to deal with the foggy aftermath.
Experience Reports are the writings and opinions of the individual authors who submit them.
Some of the activities described are dangerous and/or illegal and none are recommended by Erowid.


Qt NFC QML Types
To use the classes of the module in your application, you need the following import statement in your .qml
file:
import QtNfc 5.2
Represents a filtering constraint for NDEF message records | |
Represents an NFC MIME record | |
Represents an NFC RTD-Text NDEF record | |
Represents an NFC RTD-URI NDEF record | |
Provides access to NDEF messages stored on NFC Forum tags | |
Type represents a record in an NDEF message |


Irrigation Project
This year we are collaborating with students from the Engineering department at Warwick University to solve one of the largest practical challenges the site faces every year… Irrigation!
Project specifications are as below.
Fenced Area - Width: 20.4M. Length: 13.6M.
Polytunnel - Width: 4.4M. Length: 10.2M.
Water Requirements: At an average of 17L per raised bed with around 22.5 raised beds in total, the volume of water required to cover the entire area would be around 380L. This is for the biggest use case scenario, on a very hot day that would dry up the plants. Regular usage will be lower and as such may not constitute the need for a water tank which holds maximum capacity.
The polytunnel will only require a maximum of two loads of 50L of water with the same extreme environments on a hot day. Majority of the time the load case will be around half of the amount stated.
Our Requirements: Must be an off-grid system with the aim of being sustainable to stick true to the society’s culture. It’s important to try and emulate the values of sustainability and self-sufficiency, something which is so important in a world where national infrastructure sometimes falls short and where we want to remind people of their personal power as a collective to problem-solve and get things done!
This project is just as much political and educational as it is practical.


Hello Spring Boot in Scala!
Viewable as simple html and via appserver
Street:
Teststreet
123 b
Trim → Test Street
or go back to index
Index


import Vex from 'vexflow';
const { Flow } = Vex;
/**
* This class implements a visitor used to convert MusicXML keys to VexFlow keys
*/
class KeyVisitor {
/**
*
* From the docs:
* Traditional key signatures are represented by the number
* of flats and sharps, plus an optional mode for major/
* minor/mode distinctions. Negative numbers are used for
* flats and positive numbers for sharps, reflecting the
* key's placement within the circle of fifths (hence the
* element name).
* @param {xmlKey} Key MusicXml object to be translated
* @returns {VexKey} Vex object
*/
constructor() {
this.keySpec = [];
// Create a lookup table of key names ("C", "B", etc.) that map to key objects
for (const k in Flow.keySignature.keySpecs) {
if ({}.hasOwnProperty.call(Flow.keySignature.keySpecs, k)) {
const newEntry = Flow.keySignature.keySpecs[k];
newEntry.name = k;
this.keySpec.push(newEntry);
}
}
}
visit(key) {
this.xmlKey = key;
let filteredKeys = this.keySpec.filter(k => k.num === Math.abs(this.xmlKey.Fifths));
const mode = this.xmlKey.Mode === 'major' ? 0 : 1;
if (this.xmlKey.Fifth < 0) {
filteredKeys = filteredKeys.filter(k => k.acc === 'b');
} else if (this.xmlKey.Fifths > 0) {
filteredKeys = filteredKeys.filter(k => k.acc === '#');
}
const entry = filteredKeys[mode].name;
return entry;
}
}
export const keyVisitor = new KeyVisitor();


Hello! This is a small project put together by Ahmed and Ken here at Haverford to make checking your shuttle bus times easier.
The source site is here in case you want to take a look.
Bus times appear here!
Looking for a specific time instead?


General Election 2019: Lib Dems pledge £500million for youth services to tackle knife crime epidemic
Jo Swinson has also pledged to give youth services protection in law to stop them being subject cuts
by Oliver Milne, https://www.mirror.co.uk/authors/oliver-milne/A Lib Dem government would invest £500 million to curb the rise of knife violence epidemic on our streets, Jo Swinson has said.
Ms Swinson said her party would invest the cash in youth services as part of a public health approach to cracking down on the knife crime.
The cash would be used to "provide young people with positive, safe and healthy opportunities to prevent them being drawn into youth violence and gang-related crime".
Praising the Scotland's Violence Reduction Unit, the Lib Dems said they would put protection for local youth services in law to protect them from future cuts.
The VRU works with teachers, social workers, and the NHS to help police reduce violence.
Ms Swinson said: "We are in a knife crime epidemic, but successive governments have taken the wrong approach to dealing with it.
"For 25 years, Conservative and Labour governments have been competing to seem tough on crime, without doing enough to actually prevent crime.
" Liberal Democrats will build a brighter future for young people by investing £500 million a year in youth services and taking a public health approach to youth violence.
"With a Liberal Democrat government, young people will have the support and opportunities they deserve, our communities will be stronger and people will feel safer."
Spending on youth services has been cut by 70% since the Conservatives came to power in 2010, but the Liberal Democrats were in coalition until 2015.


{% extends 'layout.html' %} {% block content %} Home Gallery Single gallery Contact Find us on Personal Gallery 2019 @ All rights reserved {% endblock %}


The Design Museum’s Deyan Sudjic was granted access to the legendary Italian house’s archives and headquarters in Milan for upcoming exhibition Prada. Front and Back
London’s Design Museum has announced that its September 2020 exhibition will focus on Prada, the institution having been granted access to the Italian fashion house’s Milanese archives and headquarters – marking the first time a major museum has dedicated an exhibition to Prada. Titled Prada. Front and Back, the exhibition promises a look at both the collections, clothing and accessories produced by the house, as well as the company’s ever-growing infrastructure, in an unprecedented behind-the-scenes exploration of Prada.
Deyan Sudjic has curated the exhibition (it marks Sudjic’s final show as co-director of the Design Museum, a role he is stepping down from in January 2020). “For me, it’s a particularly personal challenge to work on the Prada exhibition – there is so much to explore about a company that never wants to do the obvious thing, and that is such a genuine cultural force,” he says.
At the exhibition’s core, of course, will be Miuccia Prada, who joined her family’s business in the 1970s and first introduced ready-to-wear in 1988. Prada. Front and Back will trace the extraordinary trajectory that Mrs Prada has engineered for the house: taking it from luggage and leather goods to one of the world’s most recognised and revolutionary luxury fashion houses, alongside her husband and co-CEO Patrizio Bertelli. “She has made Prada the essence of modernity,” says the Design Museum.


Toggle between hiding and showing the paragraphs
This is a paragraph with little content.
This is another small paragraph.


I am dedicated to research in the field of Software Engineering, focusing on approaches and techniques to support software developers in their daily tasks related to the creation, understanding, and maintenance of software systems.
My main research topics are:
Applications of Information Retrieval and Natural Language Processing in Software Engineering


A Quality Life Community (AQLC) offers a wellness program for cancer patients, caregivers and loved ones. AQLC provides free series of yoga , meditation classes, recovery retreats, as well as the newest insights on proper medical care, alternative care, nutrition and other innovative therapies.
AQLC is unique in that it is designed to support not just the individual, but is inclusive for the entire family's self-healing. AQLC is also dedicated to teaching yoga and meditation teachers how to teach this powerful work.


---
layout: page
title: vocalisations
subtitle: dutch22
---
Example vocalisations (nonverbal and speech prosody) of 22 positive emotions produced by Dutch speakers:
Nonverbal vocalisation of admiration:
Speech prosody of admiration:
Nonverbal vocalisation of amae:
Speech prosody of amae:
Nonverbal vocalisation of amusement:
Speech prosody of amusement:
Nonverbal vocalisation of awe:
Speech prosody of awe:
Nonverbal vocalisation of determination:
Speech prosody of determination:
Nonverbal vocalisation of elation:
Speech prosody of elation:
Nonverbal vocalisation of elevation:
Speech prosody of elevation:
Nonverbal vocalisation of excitement:
Speech prosody of excitement:
Nonverbal vocalisation of gratitude:
Speech prosody of gratitude:
Nonverbal vocalisation of hope:
Speech prosody of hope:
Nonverbal vocalisation of inspiration:
Speech prosody of inspiration:
Nonverbal vocalisation of interest:
Speech prosody of interest:
Nonverbal vocalisation of lust:
Speech prosody of lust:
Nonverbal vocalisation of moved:
Speech prosody of moved:
Nonverbal vocalisation of pride:
Speech prosody of pride:
Nonverbal vocalisation of positive surprise:
Speech prosody of positive suprise:
Nonverbal vocalisation of relief:
Speech prosody of relief:
Nonverbal vocalisation of being respected:
Speech prosody of being respected:
Nonverbal vocalisation of schadenfreude:
Speech prosody of schadenfreude:
Nonverbal vocalisation of sensory pleasure:
Speech prosody of sensory pleasure:
Nonverbal vocalisation of tenderness:
Speech prosody of tenderness:
Nonverbal vocalisation of triumph:
Speech prosody of triumph:
Chinese vocalisations of 22 positive emotions can be listened from here


| year | title | authors | tags | paper | code | slides |
|---|---|---|---|---|---|---|
| 2019 | disentangled attribution curves for interpreting random forests and boosted trees | devlin, singh, murdoch & yu | ml | arxiv | -- | |
| 2019 | interpretable machine learning: definitions, methods, and applications | Murdoch*, Singh*, Kumbier, Abbasi-Asl, & Yu | ml | arxiv | -- | |
| 2019 | hierarchical interpretations for neural network predictions | Singh*, Murdoch*, & Yu | ml | ICLR | ||
| 2018 | large scale image segmentation with structured loss based deep learning for connectome reconstruction | Funke*, Tschopp*, Grisaitis, Sheridan, Singh, Saalfeld, & Turaga | ml, neuro | TPAMI | -- | |
| 2018 | linearization of excitatory synaptic integration at no extra cost | Morel, Singh, & Levy | neuro | J Comp Neuro | ||
| 2017 | a consensus layer V pyramidal neuron can sustain interpulse-interval coding | Singh & Levy | neuro | Plos One | ||
| 2017 | a constrained, weighted-l1 minimization approach for joint discovery of heterogeneous neural connectivity graphs | Singh, Wang, & Qi | ml, neuro | NIPS Workshop |
{{ timeline_blurb.content }}


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CovidClinical is an international consortium for electronic health record (EHR) data-driven studies of the COVID19 pandemic. The goal of this effort—led by the i2b2 international academics users group—is to inform doctors, epidemiologists and the public about COVID19 patients with data acquired through the health care process.


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Created on {{userInfo.created_at|date|uppercase}}
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Branding, Web Design, UI
UI
Branding, Web Design
Tross is a data-driven crowdfunding powerhouse.
Year: 2017 Client: Tross Services: Web Design Designed at: Tross
Livia is a drug-free solution for menstrual pain.
Year: 2015 Client: Livia Services: Branding, Web Design, UI Designed at: Tross
Atomation's IoT platform makes any object intelligent and connected
Year: 2016 Client: Atomation Services: Web Design Designed at: Tross
Vavoo is the best straightener brush ever.
Year: 2017 Client: Vavoo Services: Web Design Designed at: Tross
The EverThere platform enables advertisers and sponsors to connect with event audiences.
Year: 2016 Client: Everthere Services: Branding, Web Design, UI Designed at: Tross
Upright is a smart wearable posture trainer.
Year: 2015-6 Client: Upright Services: Branding, Web Design Designed at: Tross
Percepto offers autonomous drone solution.
Year: 2015 Client: Percepto Services: Branding Designed at: Tross
Brixo is Bluetooth-enabled electric building blocks.
Year: 2016 Client: Brixo Services: Branding Designed at: Tross
BiggerCake is a crowdfunding software for maximising ROI
Year: 2017 Client: BiggerCake by Tross Services: Branding, Web Design, UI Designed at: Tross
TowNow is a friendly road assistance app
Year: 2015 Client: TowNow Services: Branding, UI Designed at: Tross
MissBeez delivers beauty services to your door
Year: 2015 Client: MissBeez Services: Web Design Designed at: Tross
Recipe app for breakfast. Personal project.


Author Group: Java Programing
Discription: This is a group for Java Programing.
Creator: Joey
Created Date: 2015-2016/1/1
Number of Group: 100
Similarity Teaching Category:
1. Timothy K. Shih: 98.71%
2. Yu-Ren Chen: 93.21%
Similarity Teaching Subject Area:
1. Timothy K. Shih: 98.71%
2. Yu-Ren Chen: 93.21%


Grid based design is the breaking down of a website into rows and columns for the purpose of clearly representing the information on the page. It helps present information in an easy to follow manner.
Because people are accessing the internet from varied sources like telephones, tablets, and computers, web pages need to be able to adapt to the different screen sizes. Responsive webpages are designed to be view-able from multiple mediums and respond to different screen sizes.
Semantic structure is the use of intuitive tags that help organize an html. Some examples are h1 for headers or img for images.
>I like how Udacity pointed us in the right direction with regard to using other websites to help us code. Udacity embraces uses sources like Stackoverflow to resolve coding problems.


Pregnancy/lactation
women should know if immune to rubella nad varicella
MMR
-
2 doses of MMR recommended and funded for women who are susceptible to MMR
-
advised to ensure not pregnant at time of immunisation and for at least 4wks after
- although no evidence MMR teratogenic
-
if mother non immune
- 2 doses MMR separated by 4 wks should be given after delivery
Varicella
-
recommended but Not funded
-
2 doses given 4-8wks apart
Influenza
-
recommended and funded
-
offered to women at any stage during pregnancy as soon as annual influenza vaccine becomes avaiable
Pertusis
-
offered in every pregnancy
-
funded 28-38 wks
-
protect mother
-
antibodies -> baby
-
-
post partum doens’t have benefir of antibodies -> baby
Preterm and low birthweight infants
- vaccination as per schedule - at usual chronological age
Rotavirus
-
exception
-
vaccinate as they leave hospital
-
vaccine virus shed int he stool
influenza
-
preterm who develop chronic lung disease
- influenza vaccien once aged 6mo
infants exposed to HepB (mum has chronic HBV)
- birth dose of hepB and HBIG
Asplenia
-
causes:
-
surgical removal
-
functional
-
disease
-
sickle cell
-
thalassaemia
-
-
congenital asplenia or polysplenia
-
-
-
at risk of fulminat bactramia
-
strep pneumoniae = most common
-
vaccines:
-
pneumococcal conjugae and polysaccharide
-
PCV13
-
polysaccahride funded for adults
-
-
meningococcal conjugate
-
Hib
-
influenza
-
varicella
-
-
elective:
- ASAP and at least 2wks pre-operatively
-
emergency
- 2wks post-operatively
-
antibiotic prophylaxis
-
sickle cell = proven
-
recommended \<5yo
-
monthly benzathine penicillin injections
-
\<5yo
-
older asplenic for at least 2 yrs post splenectomy
-
-