TL;DR
Never use a lousy schematic editor again! SKiDL is a simple module that lets you describe electronic circuits using Python. The resulting Python program outputs a netlist that a PCB layout tool uses to create a finished circuit board.
Contents
- Introduction
- Installation
- Basic Usage
- Going Deeper
- Going Really Deep
- Converting Existing Designs to SKiDL
- SPICE Simulations
Introduction
SKiDL is a module that allows you to compactly describe the interconnection of electronic circuits and components using Python. The resulting Python program performs electrical rules checking for common mistakes and outputs a netlist that serves as input to a PCB layout tool.
Features
- Has a powerful, flexible syntax (because it is Python).
- Permits compact descriptions of electronic circuits (think about not tracing signals through a multi-page schematic).
- Allows textual descriptions of electronic circuits (think about using
diff
and git for circuits). - Performs electrical rules checking (ERC) for common mistakes (e.g., unconnected device I/O pins).
- Supports linear / hierarchical / mixed descriptions of electronic designs.
- Fosters design reuse (think about using PyPi and Github to distribute electronic designs).
- Makes possible the creation of smart circuit modules whose behavior / structure are changed parametrically (think about filters whose component values are automatically adjusted based on your desired cutoff frequency).
- Can work with any ECAD tool (only two methods are needed: one for reading the part libraries and another for outputing the correct netlist format).
- Takes advantage of all the benefits of the Python ecosystem (because it is Python).
- Free software: MIT license.
- Open source: https://github.com/xesscorp/skidl
As a very simple example, the SKiDL program below describes a circuit that takes an input voltage, divides it by three, and outputs it:
from skidl import *
gnd = Net('GND') # Ground reference.
vin = Net('VI') # Input voltage to the divider.
vout = Net('VO') # Output voltage from the divider.
r1, r2 = 2 * Part('device', 'R', TEMPLATE) # Create two resistors.
r1.value, r1.footprint = '1K', 'Resistors_SMD:R_0805' # Set resistor values
r2.value, r2.footprint = '500', 'Resistors_SMD:R_0805' # and footprints.
r1[1] += vin # Connect the input to the first resistor.
r2[2] += gnd # Connect the second resistor to ground.
vout += r1[2], r2[1] # Output comes from the connection of the two resistors.
generate_netlist()
And this is the netlist output that can be fed to a program like KiCad’s PCBNEW
to
create the physical PCB:
(export (version D)
(design
(source "C:\TEMP\skidl tests\intro_example.py")
(date "04/19/2017 04:09 PM")
(tool "SKiDL (0.0.12)"))
(components
(comp (ref R1)
(value 1K)
(footprint Resistors_SMD:R_0805)
(fields
(field (name keywords) "r res resistor")
(field (name description) Resistor))
(libsource (lib device) (part R)))
(comp (ref R2)
(value 500)
(footprint Resistors_SMD:R_0805)
(fields
(field (name keywords) "r res resistor")
(field (name description) Resistor))
(libsource (lib device) (part R))))
(nets
(net (code 0) (name GND)
(node (ref R2) (pin 2)))
(net (code 1) (name VI)
(node (ref R1) (pin 1)))
(net (code 2) (name VO)
(node (ref R1) (pin 2))
(node (ref R2) (pin 1))))
))
Installation
SKiDL is pure Python so it’s easy to install:
$ pip install skidl
or:
$ easy_install skidl
In order for SKiDL to access part libraries, you’ll also need to install KiCad.
Basic Usage
This is the minimum that you need to know to design electronic circuitry using SKiDL:
- How to get access to SKiDL.
- How to find and instantiate a component (or part).
- How to connect pins of the parts to each other using nets.
- How to run an ERC on the circuit.
- How to generate a netlist for the circuit that serves as input to a PCB layout tool.
I’ll demonstrate these steps using SKiDL in an interactive Python session, but normally the statements that are shown would be entered into a file and executed as a Python script.
Accessing SKiDL
To use skidl in a project, just place the following at the top of your file:
import skidl
But for this tutorial, I’ll just import everything:
from skidl import *
Finding Parts
SKiDL provides a convenience function for searching for parts called
(naturally) search
.
For example, if you needed an operational amplifier, then the following command would
pull up some likely candidates:
>>> search('opamp')
linear.lib: LT1492
linear.lib: MCP601SN (2.7V to 6.0V Single Supply CMOS Operational Amplifier, SO-8)
linear.lib: LM321 (Low Power Single Operational Amplifier)
linear.lib: MCP601R (2.7V to 6.0V Single Supply CMOS Operational Amplifier, SOT-23-5)
linear.lib: LM555N (Dual Op amp, rail-to-rail, 8MHz, MSOP8, SOIC8)
...
linear.lib: MCP603ST (2.7V to 6.0V Single Supply CMOS Operational Amplifier, with Chip Select, TSSOP-8)
linear.lib: NE5534 (Low-Noise High-Speed Audio Operational Amplifier)
linear.lib: LT1493
linear.lib: MCP601P (2.7V to 6.0V Single Supply CMOS Operational Amplifier, DIP-8)
linear.lib: MCP601ST (2.7V to 6.0V Single Supply CMOS Operational Amplifier, TSSOP-8)
search
accepts a regular expression and scans for it anywhere within the
name, description and keywords of all the parts in the library path.
(You can read more about how SKiDL handles libraries here.)
So the following search pulls up several candidates:
>>> search('lm35')
dc-dc.lib: LM3578 (Switching Regulator (adjustable))
linear.lib: LM358 (Dual Rail-to-rail CMOS Operational Amplifier)
regul.lib: LM350T (3A 33V Adjustable Linear Regulator, TO-220)
sensors.lib: LM35-LP (Precision centigrade temperature sensor, TO-92 package)
sensors.lib: LM35-D (Precision centigrade temperature sensor, SOIC-8 package)
sensors.lib: LM35-NEB (Precision centigrade temperature sensor, TO-220 package)
If you want to restrict the search to a specific part, then use a regular expression like the following:
>>> search('^lm358$')
linear.lib: LM358 (Dual Rail-to-rail CMOS Operational Amplifier)
Once you have the part name and library, you can see the part’s pin numbers, names
and their functions using the show
function:
>>> show('linear', 'lm358')
LM358: Dual Rail-to-rail CMOS Operational Amplifier
Pin None/4/V-/POWER-IN
Pin None/8/V+/POWER-IN
Pin None/1/~/OUTPUT
Pin None/2/-/INPUT
Pin None/3/+/INPUT
Pin None/5/+/INPUT
Pin None/6/-/INPUT
Pin None/7/~/OUTPUT
show
looks for exact matches of the part name in a library, so the following
command raises an error:
>>> show('linear', 'lm35')
ERROR: Unable to find part lm35 in library linear.
Instantiating Parts
The part library and name are used to instantiate a part as follows:
>>> resistor = Part('device','R')
You can customize the resistor by setting its attributes:
>>> resistor.value = '1K'
>>> resistor.value
'1K'
You can also combine the setting of attributes with the creation of the part:
>>> resistor = Part('device', 'R', value='1K')
>>> resistor.value
'1K'
You can use any valid Python name for a part attribute, but ref
, value
,
and footprint
are necessary in order to generate the final netlist
for your circuit. And the attribute can hold any type of Python object,
but simple strings are probably the most useful.
The ref
attribute holds the reference for the part. It’s set automatically
when you create the part:
>>> resistor.ref
'R1'
Since this was the first resistor we created, it has the honor of being named R1
.
But you can easily change it:
>>> resistor.ref = 'R5'
>>> resistor.ref
'R5'
Now what happens if we create another resistor?:
>>> another_res = Part('device','R')
>>> another_res.ref
'R1'
Since the R1
reference was now available, the new resistor got it.
What if we tried renaming the first resistor back to R1
:
>>> resistor.ref = 'R1'
>>> resistor.ref
'R1_1'
Since the R1
reference was already taken, SKiDL tried to give us
something close to what we wanted.
SKiDL won’t let different parts have the same reference because
that would confuse the hell out of everybody.
Connecting Pins
Parts are great and all, but not very useful if they aren’t connected to anything. The connections between parts are called nets (think of them as wires) and every net has one or more part pins on it. SKiDL makes it easy to create nets and connect pins to them. To demonstrate, let’s build the voltage divider circuit shown in the introduction.
First, start by creating two resistors (note that I’ve also added the
footprint
attribute that describes the physical package for the resistors):
>>> rup = Part('device', 'R', value='1K', footprint='Resistors_SMD:R_0805')
>>> rlow = Part('device', 'R', value='500', footprint='Resistors_SMD:R_0805')
>>> rup.ref, rlow.ref
('R1', 'R2')
>>> rup.value, rlow.value
('1K', '500')
To bring the voltage that will be divided into the circuit, let’s create a net:
>>> v_in = Net('VIN')
>>> v_in.name
'VIN'
Now attach the net to one of the pins of the rup
resistor
(resistors are bidirectional which means it doesn’t matter which pin, so pick pin 1):
>>> rup[1] += v_in
You can verify that the net is attached to pin 1 of the resistor like this:
>>> rup[1].net
VIN: Pin R1/1/~/PASSIVE
Next, create a ground reference net and attach it to rlow
:
>>> gnd = Net('GND')
>>> rlow[1] += gnd
>>> rlow[1].net
GND: Pin R2/1/~/PASSIVE
Finally, the divided voltage has to come out of the circuit on a net. This can be done in several ways. The first way is to define the output net and then attach the unconnected pins of both resistors to it:
>>> v_out = Net('VO')
>>> v_out += rup[2], rlow[2]
>>> rup[2].net, rlow[2].net
(VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE, VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE)
An alternate method is to connect the resistors and then attach their junction to the output net:
>>> rup[2] += rlow[2]
>>> v_out = Net('VO')
>>> v_out += rlow[2]
>>> rup[2].net, rlow[2].net
(VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE, VO: Pin R1/2/~/PASSIVE, Pin R2/2/~/PASSIVE)
Either way works! Sometimes pin-to-pin connections are easier when you’re just wiring two devices together, while the pin-to-net connection method excels when three or more pins have a common connection.
Checking for Errors
Once the parts are wired together, you can do simple electrical rules checking like this:
>>> ERC()
2 warnings found during ERC.
0 errors found during ERC.
Since this is an interactive session, the ERC warnings and errors are stored
in the file skidl.erc
. (Normally, your SKiDL circuit description is stored
as a Python script such as my_circuit.py
and the ERC()
function will
dump its messages to my_circuit.erc
.)
The ERC messages are:
WARNING: Only one pin (PASSIVE pin 1/~ of R/R1) attached to net VIN.
WARNING: Only one pin (PASSIVE pin 1/~ of R/R2) attached to net GND.
These messages are generated because the VIN
and GND
nets each have only
a single pin on them and this usually indicates a problem.
But it’s OK for this simple example, so the ERC can be turned off for
these two nets to prevent the spurious messages:
>>> v_in.do_erc = False
>>> gnd.do_erc = False
>>> ERC()
No ERC errors or warnings found.
Generating a Netlist
The end goal of using SKiDL is to generate a netlist that can be used with a layout tool to generate a PCB. The netlist is output as follows:
>>> generate_netlist()
Like the ERC output, the netlist shown below is stored in the file skidl.net
.
But if your SKiDL circuit description is in the my_circuit.py
file,
then the netlist will be stored in my_circuit.net
.
(export (version D)
(design
(source "C:\xesscorp\KiCad\tools\skidl\skidl\skidl.py")
(date "08/12/2016 10:05 PM")
(tool "SKiDL (0.0.1)"))
(components
(comp (ref R1)
(value 1K)
(footprint Resistors_SMD:R_0805))
(comp (ref R2)
(value 500)
(footprint Resistors_SMD:R_0805)))
(nets
(net (code 0) (name "VIN")
(node (ref R1) (pin 1)))
(net (code 1) (name "GND")
(node (ref R2) (pin 1)))
(net (code 2) (name "VO")
(node (ref R1) (pin 2))
(node (ref R2) (pin 2))))
)
(export (version D)
(design
(source "C:\TEMP\skidl tests\intro_example.py")
(date "04/19/2017 04:09 PM")
(tool "SKiDL (0.0.12)"))
(components
(comp (ref R1)
(value 1K)
(footprint Resistors_SMD:R_0805)
(fields
(field (name keywords) "r res resistor")
(field (name description) Resistor))
(libsource (lib device) (part R)))
(comp (ref R2)
(value 500)
(footprint Resistors_SMD:R_0805)
(fields
(field (name keywords) "r res resistor")
(field (name description) Resistor))
(libsource (lib device) (part R))))
(nets
(net (code 0) (name GND)
(node (ref R2) (pin 2)))
(net (code 1) (name VI)
(node (ref R1) (pin 1)))
(net (code 2) (name VO)
(node (ref R1) (pin 2))
(node (ref R2) (pin 1))))
)
You can also generate the netlist in XML format:
>>> generate_xml()
This is useful in a KiCad environment where the XML file is used as the input to BOM-generation tools.
 This section will talk about some more advanced features.
Basic SKiDL Objects: Parts, Pins, Nets, Buses
SKiDL uses four types of objects to represent a circuit: Part
, Pin
,
Net
, and Bus
.
The Part
object represents an electronic component, which SKiDL thinks of as simple
bags of Pin
objects with a few other attributes attached
(like the part number, name, reference, value, footprint, etc.).
The Pin
object represents a terminal that brings an electronic signal into
and out of the part. Each Pin
object has two important attributes:
part
which stores the reference to thePart
object to which the pin belongs.net
which stores the the reference to theNet
object that the pin is connected to, orNone
if the pin is unconnected.
A Net
object is kind of like a Part
: it’s a simple bag of pins.
The difference is, unlike a part, pins can be added to a net.
This happens when a pin on some part is connected to the net or when the
net is merged with another net.
Finally, a Bus
is just a list of Net
objects.
A bus of a certain width can be created from a number of existing nets,
newly-created nets, or both.
Creating SKiDL Objects
Here’s the most common way to create a part in your circuit:
my_part = Part('some_library', 'some_part_name')
When this is processed, the current directory will be checked for a file
called some_library.lib
which will be opened and scanned for a part with the
name some_part_name
. If the file is not found or it doesn’t contain
the requested part, then the process will be repeated using KiCad’s default
library directory.
(You can change SKiDL’s library search by changing the list of directories
stored in the skidl.lib_search_paths_kicad
list.)
You’re not restricted to using only the current directory or the KiCad default directory to search for parts. You can also search any file for a part by using a full file name:
my_part = Part('C:/my_libs/my_great_parts.lib', 'my_super_regulator')
You’re also not restricted to getting an exact match on the part name: you can use a regular expression instead. For example, this will find a part with “358” anywhere in a part name or alias:
my_part = Part('some_library', '.*358.*')
If the regular expression matches more than one part, then you’ll only get the first match and a warning that multiple parts were found.
Once you have a part, you can set its attributes like you could for any Python
object. As was shown previously, the ref
attribute will already be set
but you can override it:
my_part.ref = 'U5'
The value
and footprint
attributes are also required for generating
a netlist. But you can also add any other attribute:
my_part.manf = 'Atmel'
my_part.setattr('manf#', 'ATTINY4-TSHR'
It’s also possible to set the attributes during the part creation:
my_part = Part('some_lib', 'some_part', ref='U5', footprint='SMD:SOT23_6', manf='Atmel')
Creating nets is also simple:
my_net = Net() # An unnamed net.
my_other_net = Net('Fred') # A named net.
As with parts, SKiDL will alter the name you assign to a net if it collides with another net having the same name.
You can create a bus of a certain width like this:
my_bus = Bus('bus_name', 8) # Create a byte-wide bus.
(All buses must be named, but SKiDL will look for and correct colliding bus names.)
You can also create a bus from existing nets, or buses, or the pins of parts:
my_part = Part('linear', 'LM358')
a_net = Net()
b_net = Net()
bus_nets = Bus('net_bus', a_net, b_net) # A 2-bit bus.
bus_pins = Bus('pin_bus', my_part[1], my_part[3]) # A 2-bit bus.
bus_buses = Bus('bus_bus', my_bus) # An 8-bit bus.
Finally, you can mix-and-match any combination of widths, nets, buses or part pins:
bus_mixed = Bus('mongrel', 8, a_net, my_bus, my_part[2]) # 8+1+8+1 = 18-bit bus.
Finally, you can modify an existing bus by inserting or extending it with any combination of widths, nets, buses or pins:
bus = Bus('A', 8) # Eight-bit bus.
bus.insert(4, Bus('I', 3)) # Insert 3-bit bus before bus line bus[4].
bus.extend(5, Pin(), Net()) # Extend bus with another 5-bit bus, a pin, and a net.
The final object you can create is a Pin
. You’ll probably never do this
(except in interactive sessions), and it’s probably a mistake if
you ever do do it, but here’s how to do it:
>>> p = Pin(num=1, name='my_pin', func=Pin.TRISTATE)
>>> p
Pin ???/1/my_pin/TRISTATE
Finding SKiDL Objects
Sometimes you may want to access a bus or net that’s already been created.
In such an instance, you can use the get()
class method:
n = Net.get('Fred') # Find the existing Net object named 'Fred'.
b = Bus.get('A') # Find the existing Bus object named 'A'.
If a net or bus is found with the exact name that was given, then that SKiDL
object is returned (no wild-card searches using regular expressions are allowed).
If the search is unsuccessful, None
is returned.
There may be other times when you want to access a particular bus or net and,
if it doesn’t exist, then create it.
The fetch()
class method is used for this:
n = Net.fetch('Fred') # Find the existing Net object named 'Fred' or create it if not found.
b = Bus.fetch('A',8) # Find the existing Bus object named 'A' or create it if not found.
Note that with the Bus.fetch()
method, you also have to provide the arguments to
build the bus (such as its width) in case it doesn’t exist.
Copying SKiDL Objects
Instead of creating a SKiDL object from scratch, sometimes it’s easier to just copy an existing object. Here are some examples of creating a resistor and then making some copies of it:
>>> r1 = Part('device', 'R', value=500)
>>> r2 = r1.copy() # Make a single copy of the resistor.
>>> r3 = r1.copy(value='1K') # Make a single copy, but give it a different value.
>>> r4 = r1(value='1K') # You can also call the object directly to make copies.
>>> r5, r6, r7 = r1(3) # Make 3 copies of the resistor.
>>> r8, r9, r10 = r1(value=[110,220,330]) # Make 3 copies, each with a different value.
>>> r11, r12 = 2 * r1 # Make copies using the '*' operator.
In some cases it’s clearer to create parts by copying a template part that doesn’t actually get included in the netlist for the circuitry. This is done like so:
>>> r_template = Part('device', 'R', dest=TEMPLATE) # Create a resistor just for copying.
>>> r1 = r_template(value='1K') # Make copy that becomes part of the actual circuitry.
Accessing Part Pins and Bus Lines
You can access the pins on a part or the individual nets of a bus using numbers, slices, strings, and regular expressions, either singly or in any combination.
Suppose you have a PIC10 processor in a six-pin package:
>>> pic10 = Part('microchip_pic10mcu', 'pic10f220-i/ot')
>>> pic10
PIC10F220-I/OT: PIC10F222, 512W Flash, 24B SRAM, SOT-23-6
Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL
Pin U1/2/VSS/POWER-IN
Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL
Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL
Pin U1/5/VDD/POWER-IN
Pin U1/6/Vpp/~MCLR~/GP3/INPUT
The most natural way to access one of its pins is to give the pin number in brackets:
>>> pic10[3]
Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL
(If you have a part in a BGA package with pins numbers like C11
, then
you’ll have to enter the pin number as a quoted string like ‘C11
’.)
You can also get several pins at once in a list:
>>> pic10[3,1,6]
[Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL, Pin U1/6/Vpp/~MCLR~/GP3/INPUT]
You can even use Python slice notation:
>>> pic10[2:4] # Get pins 2 through 4.
[Pin U1/2/VSS/POWER-IN, Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL]
>>> pic10[4:2] # Get pins 4 through 2.
[Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL, Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/2/VSS/POWER-IN]
>>> pic10[:] # Get all the pins.
[Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL, Pin U1/2/VSS/POWER-IN, Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL, Pin U1/5/VDD/POWER-IN, Pin U1/6/Vpp/~MCLR~/GP3/INPUT]
(It’s important to note that the slice notation used by SKiDL for parts is slightly
different than standard Python. In Python, a slice n:m
would fetch indices
n
, n+1
, ...
, m-1
. With SKiDL, it actually fetches all the
way up to the last number: n
, n+1
, ...
, m-1
, m
.
The reason for doing this is that most electronics designers are used to
the bounds on a slice including both endpoints. Perhaps it is a mistake to
do it this way. We’ll see…)
In addition to the bracket notation, you can also get a single pin using an attribute name
that begins with a ‘p
’ followed by the pin number:
>>> pic10.p2
Pin U1/2/VSS/POWER-IN
Instead of pin numbers, sometimes it makes the design intent more clear to access pins by their names. For example, it’s more obvious that a voltage supply net is being attached to the power pin of the processor when it’s expressed like this:
pic10['VDD'] += supply_5V
Like pin numbers, pin names can also be used as attributes to access the pin:
>>> pic10.VDD
Pin U1/5/VDD/POWER-IN
You can use multiple names or regular expressions to get more than one pin:
>>> pic10['VDD','VSS']
[Pin U1/5/VDD/POWER-IN, Pin U1/2/VSS/POWER-IN]
>>> pic10['.*gp[1-3]']
[Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL, Pin U1/6/Vpp/~MCLR~/GP3/INPUT]
It can be tedious and error prone entering all the quote marks if you’re accessing many pin names. SKiDL lets you enter a single, comma-delimited string of pin names:
>>> pic10['.*GP0, .*GP1, .*GP2']
[Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL, Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL]
Some parts have sequentially-numbered sets of pins like the address and data buses of a RAM. SKiDL lets you access these pins using a slice-like notation in a string like so:
>>> ram = Part('memory', 'sram_512ko')
>>> ram['D[0:7]']
[Pin U1/13/D0/TRISTATE, Pin U1/14/D1/TRISTATE, Pin U1/15/D2/TRISTATE, Pin U1/17/D3/TRISTATE, Pin U1/18/D4/TRISTATE, Pin U1/19/D5/TRISTATE, Pin U1/20/D6/TRISTATE, Pin U1/21/D7/TRISTATE]
Or you can access the pins in the reverse order:
>>> ram = Part('memory', 'sram_512ko')
>>> ram['D[7:0]']
[Pin U2/21/D7/TRISTATE, Pin U2/20/D6/TRISTATE, Pin U2/19/D5/TRISTATE, Pin U2/18/D4/TRISTATE, Pin U2/17/D3/TRISTATE, Pin U2/15/D2/TRISTATE, Pin U2/14/D1/TRISTATE, Pin U2/13/D0/TRISTATE]
Part
objects also provide the get_pins()
function which can select pins in even more ways.
For example, this would get every bidirectional pin of the processor:
>>> pic10.get_pins(func=Pin.BIDIR)
[Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL, Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL]
Accessing the individual nets of a bus works similarly to accessing part pins:
>>> a = Net('NET_A') # Create a named net.
>>> b = Bus('BUS_B', 8, a) # Create a nine-bit bus.
>>> b
BUS_B:
BUS_B0: # Note how the individual nets of the bus are named.
BUS_B1:
BUS_B2:
BUS_B3:
BUS_B4:
BUS_B5:
BUS_B6:
BUS_B7:
NET_A: # The last net retains its original name.
>>> b[0] # Get the first net of the bus.
BUS_B0:
>>> b[4,8] # Get the fifth and ninth bus lines.
[BUS_B4: , NET_A: ]
>>> b[3:0] # Get the first four bus lines in reverse order.
[BUS_B3: , BUS_B2: , BUS_B1: , BUS_B0: ]
>>> b['BUS_B.*'] # Get all the bus lines except the last one.
[BUS_B0: , BUS_B1: , BUS_B2: , BUS_B3: , BUS_B4: , BUS_B5: , BUS_B6: , BUS_B7: ]
>>> b['NET_A'] # Get the last bus line.
NET_A:
Making Connections
Pins, nets, parts and buses can all be connected together in various ways, but the primary rule of SKiDL connections is:
The
+=
operator is the only way to make connections!
At times you’ll mistakenly try to make connections using the
assignment operator (=
). In many cases, SKiDL warns you if you do that,
but there are situations where it can’t (because
Python is a general-purpose programming language where
assignment is a necessary operation).
So remember the primary rule!
After the primary rule, the next thing to remember is that SKiDL’s main purpose is creating netlists. To that end, it handles four basic, connection operations:
Pin-to-Net: A pin is connected to a net, adding it to the list of pins connected to that net. If the pin is already attached to other nets, then those nets are connected to this net as well.
Net-to-Pin: This is the same as doing a pin-to-net connection.
Pin-to-Pin: A net is created and both pins are attached to it. If one or both pins are already connected to other nets, then those nets are connected to the newly-created net as well.
Net-to-Net: Connecting one net to another merges the pins on both nets onto a single, larger net.
For each type of connection operation, there are three variants based on the number of things being connected:
One-to-One: This is the most frequent type of connection, for example, connecting one pin to another or connecting a pin to a net.
One-to-Many: This mainly occurs when multiple pins are connected to the same net, like when multiple ground pins of a chip are connected to the circuit ground net.
Many-to-Many: This usually involves bus connections to a part, such as connecting a bus to the data or address pins of a processor. For this variant, there must be the same number of things to connect in each set, e.g. you can’t connect three pins to four nets.
As a first example, let’s connect a net to a pin on a part:
>>> pic10 = Part('microchip_pic10mcu','pic10f220-i/ot') # Get a part.
>>> io = Net('IO_NET') # Create a net.
>>> pic10['.*GP0'] += io # Connect the net to a part pin.
>>> io # Show the pins connected to the net.
IO_NET: Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL
You can do the same operation in reverse by connecting the part pin to the net with the same result:
>>> pic10 = Part('microchip_pic10mcu','pic10f220-i/ot')
>>> io = Net('IO_NET')
>>> io += pic10['.*GP0'] # Connect a part pin to the net.
>>> io
IO_NET: Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL
You can also connect a pin directly to another pin.
In this case, an implicit net will be created between the pins that you can
access using the net
attribute of either part pin:
>>> pic10['.*GP1'] += pic10['.*GP2'] # Connect two pins together.
>>> pic10['.*GP1'].net # Show the net connected to the pin.
N$1: Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL
>>> pic10['.*GP2'].net # Show the net connected to the other pin. Same thing!
N$1: Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL
You can connect multiple pins together, all at once:
>>> pic10[1] += pic10[2,3,6]
>>> pic10[1].net
N$1: Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL, Pin U1/2/VSS/POWER-IN, Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/6/Vpp/~MCLR~/GP3/INPUT
Or you can do it incrementally:
>>> pic10[1] += pic10[2]
>>> pic10[1] += pic10[3]
>>> pic10[1] += pic10[6]
>>> pic10[1].net
N$1: Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL, Pin U1/2/VSS/POWER-IN, Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/6/Vpp/~MCLR~/GP3/INPUT
If you connect pins on separate nets together, then all the pins are merged onto the same net:
>>> pic10[1] += pic10[2] # Put pins 1 & 2 on one net.
>>> pic10[1].net
N$1: Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL, Pin U1/2/VSS/POWER-IN
>>> pic10[3] += pic10[4] # Put pins 3 & 4 on another net.
>>> pic10[3].net
N$2: Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL
>>> pic10[1] += pic10[4] # Connect two pins from different nets.
>>> pic10[3].net # Now all the pins are on the same net!
N$2: Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL, Pin U1/2/VSS/POWER-IN, Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL, Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL
Here’s an example of connecting a three-bit bus to three pins on a part:
>>> pic10 = Part('microchip_pic10mcu','pic10f220-i/ot')
>>> pic10
PIC10F220-I/OT: PIC10F222, 512W Flash, 24B SRAM, SOT-23-6
Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL
Pin U1/2/VSS/POWER-IN
Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL
Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL
Pin U1/5/VDD/POWER-IN
Pin U1/6/Vpp/~MCLR~/GP3/INPUT
>>> b = Bus('GP', 3) # Create a 3-bit bus.
>>> pic10[4,3,1] += b[2:0] # Connect bus to part pins, one-to-one.
>>> b
GP:
GP0: Pin U1/1/ICSPDAT/AN0/GP0/BIDIRECTIONAL
GP1: Pin U1/3/ICSPCLK/AN1/GP1/BIDIRECTIONAL
GP2: Pin U1/4/T0CKI/FOSC4/GP2/BIDIRECTIONAL
But SKiDL will warn you if there aren’t the same number of things to connect on each side:
>>> pic10[4,3,1] += b[1:0] # Too few bus lines for the pins!
ERROR: Connection mismatch 3 != 2!
Traceback (most recent call last):
File "<stdin>", line 1, in <module>
File "c:\xesscorp\kicad\tools\skidl\skidl\skidl.py", line 3330, in __iadd__
raise Exception
Exception
Units Within Parts
Some components may contain smaller units that operate independently of the component as a whole. For example, an operational amplifier chip might contain two individual opamp units, each capable of operating on their own set of inputs and outputs.
Some library parts may already have predefined units, but you can add them to any part. For example, a four-pin resistor network might contain two resistors: one attached between pins 1 and 4, and the other bewtween pins 2 and 3. Each resistor could be assigned to a unit as follows:
>>> rn = Part('device', 'R_Pack02')
>>> rn.make_unit('A', 1, 4) # Make a unit called 'A' for the first resistor.
R_Pack02 (): 2 Resistor network, parallel topology, DIP package
Pin RN1/4/R1.2/PASSIVE
Pin RN1/1/R1.1/PASSIVE
>>> rn.make_unit('B', 2, 3) # Now make a unit called 'B' for the second resistor.
R_Pack02 (): 2 Resistor network, parallel topology, DIP package
Pin RN1/2/R2.1/PASSIVE
Pin RN1/3/R2.2/PASSIVE
>>> rn.unit['A'][1, 4] += Net(), Net()
Once the units are defined, you can use them just like any part:
>>> rn.unit['A'][1,4] += Net(), Net() # Connect resistor A to two nets.
>>> rn.unit['B'][2,3] += rn.unit['A'][1,4] # Connect resistor B in parallel with resistor A.
Now this isn’t all that useful because you still have to remember which pins are assigned to each unit, and if you wanted to swap the resistors you would have to change the unit names and the pins numbers!. In order to get around this inconvenience, you could assign aliases to each pin like this:
>>> rn = Part('device', 'R_Pack02')
>>> rn.make_unit('A', 1, 4)
R_Pack02 (): 2 Resistor network, parallel topology, DIP package
Pin RN1/4/R1.2/PASSIVE
Pin RN1/1/R1.1/PASSIVE
>>> rn.make_unit('B', 2, 3)
R_Pack02 (): 2 Resistor network, parallel topology, DIP package
Pin RN1/3/R2.2/PASSIVE
Pin RN1/2/R2.1/PASSIVE
>>> rn.unit['A'].set_pin_alias('L',1) # Alias 'L' of pin 1 on left-side of package.
>>> rn.unit['A'].set_pin_alias('R',4) # Alias 'R' of pin 4 on right-side of package.
>>> rn.unit['B'].set_pin_alias('L',2) # Alias 'L' of pin 2 on left-side.
>>> rn.unit['B'].set_pin_alias('R',3) # Alias 'R' of pin 3 on right-side.
Now the same connections can be made using the pin aliases:
>>> rn.unit['A']['L,R'] += Net(), Net() # Connect resistor A to two nets.
>>> rn.unit['B']['L,R'] += rn.unit['A']['L,R'] # Connect resistor B in parallel with resistor A.
In this case, if you wanted to swap the A and B resistors, you only need to change their unit labels. The pin aliases don’t need to be altered.
If you find the unit[...]
notation cumbersome, units can also be accessed by
using their names as attributes:
>>> rn.A['L,R'] += Net(), Net() # Connect resistor A to two nets.
>>> rn.B['L,R'] += rn.A['L,R'] # Connect resistor B in parallel with resistor A.
Hierarchy
SKiDL supports the encapsulation of parts, nets and buses into modules that can be replicated to reduce the design effort, and can be used in other modules to create a functional hierarchy. It does this using Python’s built-in machinery for defining and calling functions so there’s almost nothing new to learn.
As an example, here’s the voltage divider as a module:
from skidl import *
import sys
# Define the voltage divider module. The @subcircuit decorator
# handles some skidl housekeeping that needs to be done.
@subcircuit
def vdiv(inp, outp):
"""Divide inp voltage by 3 and place it on outp net."""
rup = Part('device', 'R', value='1K', footprint='Resistors_SMD:R_0805')
rlo = Part('device','R', value='500', footprint='Resistors_SMD:R_0805')
rup[1,2] += inp, outp
rlo[1,2] += outp, gnd
gnd = Net('GND') # GLobal ground net.
input_net = Net('IN') # Net with the voltage to be divided.
output_net = Net('OUT') # Net with the divided voltage.
# Instantiate the voltage divider and connect it to the input & output nets.
vdiv(input_net, output_net)
generate_netlist(sys.stdout)
For the most part, vdiv
is just a standard Python function:
it accepts inputs, it performs operations on them, and it could return
outputs (but in this case, it doesn’t need to).
Other than the @subcircuit
decorator that appears before the function definition,
vdiv
is just a Python function and it can do anything that a Python function can do.
Here’s the netlist that’s generated:
(export (version D)
(design
(source "C:\TEMP\skidl tests\hier_example.py")
(date "04/20/2017 09:39 AM")
(tool "SKiDL (0.0.12)"))
(components
(comp (ref R1)
(value 1K)
(footprint Resistors_SMD:R_0805)
(fields
(field (name keywords) "r res resistor")
(field (name description) Resistor))
(libsource (lib device) (part R)))
(comp (ref R2)
(value 500)
(footprint Resistors_SMD:R_0805)
(fields
(field (name keywords) "r res resistor")
(field (name description) Resistor))
(libsource (lib device) (part R))))
(nets
(net (code 0) (name GND)
(node (ref R2) (pin 2)))
(net (code 1) (name IN)
(node (ref R1) (pin 1)))
(net (code 2) (name OUT)
(node (ref R1) (pin 2))
(node (ref R2) (pin 1))))
)
For an example of a multi-level hierarchy, the multi_vdiv
module shown below
can use the vdiv
module to divide a voltage multiple times:
from skidl import *
import sys
# Define the voltage divider module.
@subcircuit
def vdiv(inp, outp):
"""Divide inp voltage by 3 and place it on outp net."""
rup = Part('device', 'R', value='1K', footprint='Resistors_SMD:R_0805')
rlo = Part('device','R', value='500', footprint='Resistors_SMD:R_0805')
rup[1,2] += inp, outp
rlo[1,2] += outp, gnd
@subcircuit
def multi_vdiv(repeat, inp, outp):
"""Divide inp voltage by 3 ** repeat and place it on outp net."""
for _ in range(repeat):
out_net = Net() # Create an output net for the current stage.
vdiv(inp, out_net) # Instantiate a divider stage.
inp = out_net # The output net becomes the input net for the next stage.
outp += out_net # Connect the output from the last stage to the module output net.
gnd = Net('GND') # GLobal ground net.
input_net = Net('IN') # Net with the voltage to be divided.
output_net = Net('OUT') # Net with the divided voltage.
multi_vdiv(3, input_net, output_net) # Run the input through 3 voltage dividers.
generate_netlist(sys.stdout)
(For the EE’s out there: yes, I know cascading three simple voltage dividers will not multiplicatively scale the input voltage because of the input and output impedances of each stage! It’s just the simplest example I could think of that shows the feature.)

By default, SKiDL finds the libraries provided by KiCad (using the KISYSMOD
environment variable), so if that’s all you need then you’re all set.
Currently, SKiDL supports the library formats for the following ECAD tools:
KICAD
: KiCad schematic part libraries.SKIDL
: Schematic parts stored as SKiDL/Python modules.
You can set the default library format you want to use in your SKiDL script like so:
set_default_tool(KICAD) # KiCad is the default library format.
set_default_tool(SKIDL) # Now SKiDL is the default library format.
You can select the directories where SKiDL looks for parts using the
lib_search_paths
dictionary:
lib_search_paths[SKIDL] = ['.', '..', 'C:\\temp']
lib_search_paths[KICAD].append('C:\\my\\kicad\\libs')
You can convert a KiCad library into the SKiDL format by exporting it:
kicad_lib = SchLib('device', tool=KICAD) # Open a KiCad library.
kicad_lib.export('my_skidl_lib') # Export it into a file in SKiDL format.
skidl_lib = SchLib('my_skidl_lib', tool=SKIDL) # Create a SKiDL library object from the new file.
if len(skidl_lib) == len(kicad_lib):
print('As expected, both libraries have the same number of parts!')
else:
print('Something went wrong!')
diode = Part(skidl_lib, 'D') # Instantiate a diode from the SKiDL library.
You can make ad-hoc libraries just by creating a SchLib object and adding Part objects to it:
my_lib = SchLib(name='my_lib') # Create an empty library object.
my_part = Part(name='R', tool=SKIDL, dest=TEMPLATE) # Create an empty part object template.
my_part.ref_prefix = 'R' # Set the part reference prefix.
my_part.description = 'resistor' # Set the part's description field.
my_part.keywords = 'res resistor' # Set the part's keywords.
my_part += Pin(num=1, func=Pin.PASSIVE) # Add a pin to the part.
my_part += Pin(num=2, func=Pin.PASSIVE) # Add another pin to the part.
my_lib += my_part # Add the part to the library.
new_resistor = Part(my_lib, 'R') # Instantiate the part from the library.
my_lib.export('my_lib') # Save the library in a file my_lib.py.
Always create a part intended for a library as a template so you don’t inadvertently add it to the circuit netlist. Then set the part attributes and create and add pins to the part. Here are the most common attributes you’ll want to set:
| Attribute | Meaning |
|---|---|
| name | A string containing the name of the part, e.g. ‘LM35’ for a temperature sensor. |
| ref_prefix | A string containing the prefix for this part’s references, e.g. ‘U’ for ICs. |
| description | A string describing the part, e.g. ‘temperature sensor’. |
| keywords | A string containing keywords about the part, e.g. ‘sensor temperature IC’. |
When creating a pin, these are the attributes you’ll want to set:
| Attribute | Meaning |
|---|---|
| num | A string or integer containing the pin number, e.g. 5 or ‘A13’. |
| name | A string containing the name of the pin, e.g. ‘CS’. |
| func | An identifier for the function of the pin. |
The pin function identifiers are as follows:
| Identifier | Pin Function |
|---|---|
| Pin.INPUT | Input pin. |
| Pin.OUTPUT | Output pin. |
| Pin.BIDIR | Bidirectional in/out pin. |
| Pin.TRISTATE | Output pin that goes into a high-impedance state when disabled. |
| Pin.PASSIVE | Pin on a passive component (like a resistor). |
| Pin.UNSPEC | Pin with an unspecified function. |
| Pin.PWRIN | Power input pin (either voltage supply or ground). |
| Pin.PWROUT | Power output pin (like the output of a voltage regulator). |
| Pin.OPENCOLL | Open-collector pin (pulls to ground but not to positive rail). |
| Pin.OPENEMIT | Open-emitter pin (pulls to positive rail but not to ground). |
| Pin.NOCONNECT | A pin that should be left unconnected. |
SKiDL will also create a library of all the parts used in your design whenever
you use the generate_netlist()
function.
For example, if your SKiDL script is named my_design.py
, then the parts instantiated
in that script will be stored as a SKiDL library in the file my_design_lib.py
.
This can be useful if you’re sending the design to someone who may not have all
the libraries you do.
Just send them my_design.py
and my_design_lib.py
and any parts not found
when they run the script will be fetched from the backup parts in the library.
Doodads
SKiDL has a few features that don’t fit into any other category. Here they are.
No Connects
Sometimes you will use a part, but you won’t use every pin. The ERC will complain about those unconnected pins:
>>> pic10 = Part('microchip_pic10mcu','pic10f220-i/ot')
>>> ERC()
ERC WARNING: Unconnected pin: BIDIRECTIONAL pin 1/ICSPDAT/AN0/GP0 of PIC10F220-I/OT/U1.
ERC WARNING: Unconnected pin: POWER-IN pin 2/VSS of PIC10F220-I/OT/U1.
ERC WARNING: Unconnected pin: BIDIRECTIONAL pin 3/ICSPCLK/AN1/GP1 of PIC10F220-I/OT/U1.
ERC WARNING: Unconnected pin: BIDIRECTIONAL pin 4/T0CKI/FOSC4/GP2 of PIC10F220-I/OT/U1.
ERC WARNING: Unconnected pin: POWER-IN pin 5/VDD of PIC10F220-I/OT/U1.
ERC WARNING: Unconnected pin: INPUT pin 6/Vpp/~MCLR~/GP3 of PIC10F220-I/OT/U1.
6 warnings found during ERC.
0 errors found during ERC.
If you have pins that you intentionally want to leave unconnected, then
attach them to the special-purpose NC
(no-connect) net and the warnings will
be supressed:
>>> pic10[1,3,4] += NC
>>> ERC()
ERC WARNING: Unconnected pin: POWER-IN pin 2/VSS of PIC10F220-I/OT/U1.
ERC WARNING: Unconnected pin: POWER-IN pin 5/VDD of PIC10F220-I/OT/U1.
ERC WARNING: Unconnected pin: INPUT pin 6/Vpp/~MCLR~/GP3 of PIC10F220-I/OT/U1.
3 warnings found during ERC.
0 errors found during ERC.
In fact, if you have a part with many pins that are not going to be used,
you can start off by attaching all the pins to the NC
net.
After that, you can attach the pins you’re using to normal nets and they
will be removed from the NC
net:
my_part[:] += NC # Connect every pin to NC net.
...
my_part[5] += Net() # Pin 5 is no longer unconnected.
The NC
net is the only net for which this happens.
For all other nets, connecting two or more nets to the same pin
merges those nets and all the pins on them together.
Net and Pin Drive Levels
Certain parts have power pins that are required to be driven by a power supply net or else ERC warnings ensue. This condition is usually satisfied if the power pins are driven by the output of another part like a voltage regulator. But if the regulator output passes through something like a ferrite bead (to remove noise), then the filtered signal is no longer a supply net and an ERC warning is issued.
In order to satisfy the ERC, the drive strength of a net can be set manually
using its drive
attribute. As a simple example, consider connecting
a net to the power supply input of a processor and then running
the ERC:
>>> pic10 = Part('microchip_pic10mcu','pic10f220-i/ot')
>>> a = Net()
>>> pic10['VDD'] += a
>>> ERC()
...
ERC WARNING: Insufficient drive current on net N$1 for pin POWER-IN pin 5/VDD of PIC10F220-I/OT/U1
...
This issue is fixed by changing the drive
attribute of the net:
>>> pic10 = Part('microchip_pic10mcu','pic10f220-i/ot')
>>> a = Net()
>>> pic10['VDD'] += a
>>> a.drive = POWER
>>> ERC()
...
(Insufficient drive warning is no longer present.)
...
You can set the drive
attribute at any time to any defined level, but POWER
is probably the only setting you’ll use.
For any net you create that supplies power to devices in your circuit,
you should probably set its drive
attribute to POWER
.
This is equivalent to attaching power flags to nets in some ECAD packages like KiCad.
You can also set the drive
attribute of part pins to override their default drive level.
This is sometimes useful when you are using an output pin of a part to power
another part.
>>> pic10_a = Part('microchip_pic10mcu','pic10f220-I/OT')
>>> pic10_b = Part('microchip_pic10mcu','pic10f220-I/OT')
>>> pic10_b['VDD'] += pic10_a[1] # Power pic10_b from output pin of pic10_a.
>>> ERC()
ERC WARNING: Insufficient drive current on net N$1 for pin POWER-IN pin 5/VDD of PIC10F220-I/OT/U2
... <additional unconnected pin warnings> ...
>>> pic10_a[1].drive = POWER # Change drive level of pic10_a output pin.
>>> ERC()
... <unconnected pin warnings, but insufficient drive warning is gone> ...
Pin, Net, Bus Equivalencies
Pins, nets, and buses can all be connected to one another in a number of ways. In order to make them as interchangeable as possible, some additional functions are defined for each object:
__bool__
and __nonzero__
:
Each object will return True
when used in a boolean operation.
This can be useful when trying to select an active connection from a set of
candidates using the or
operator:
>>> a = Net('A')
>>> b = Bus('B', 8)
>>> c = Pin()
>>> d = a or b or c
>>> d
A:
>>> type(d)
<class 'skidl.Net.Net'>
Indexing:
Normally, indices can only be used with a Bus object to select one or more bus lines.
But Pin
and Net
objects can also be indexed as long as the index evaluates to zero:
>>> a = Net('A')
>>> c = Pin()
>>> a[0] += c[0]
WARNING: Attaching non-part Pin to a Net A.
>>> a[0] += c[1]
ERROR: Can't use a non-zero index for a pin.
Traceback (most recent call last):
File "<stdin>", line 1, in <module>
File "C:\xesscorp\KiCad\tools\skidl\skidl\Pin.py", line 251, in __getitem__
raise Exception
Exception
Width:
Bus
, Net
, and Pin
objects all support the width
property.
For a Bus
object, width
returns the number of bus lines it contains.
For a Net
or Pin
object, width
always returns 1.
>>> a = Net('A')
>>> b = Bus('B', 8)
>>> c = Pin()
>>> a.width
1
>>> b.width
8
>>> c.width
1
Selectively Supressing ERC Messages
Sometimes a portion of your circuit throws a lot of ERC warnings or errors even though you know it’s correct.
Going Really Deep
If all you need to do is design the circuitry for a PCB, then you probably know all the SKiDL you need to know. This section will describe the features of SKiDL that might be useful (or not) to some of the avant-garde circuit designers out there.
Circuit Objects
Normally, SKiDL puts parts and nets into a global instance of a Circuit
object
called default_circuit
(which, of course, you never noticed).
But you can create other Circuit
objects:
>>> my_circuit = Circuit()
and then you can create parts, nets and buses and add them to your new circuit:
>>> my_circuit += Part('device','R') # Add a resistor to the circuit.
>>> my_circuit += Net('GND') # Add a net.
>>> my_circuit += Bus('byte_bus', 8) # Add a bus.
In addition to the +=
operator, you can also use the methods add_parts
, add_nets
, and add_buses
.
(There’s also the much less-used -=
operator for removing parts, nets or buses
from a circuit along with the rmv_parts
, rmv_nets
, and rmv_buses
methods.)
You can also place parts, nets, and buses directly into a Circuit object
by using the circuit
parameter of the object constructors:
>>> my_circuit = Circuit()
>>> p = Part('device', 'R', circuit = my_circuit)
>>> n = Net('GND', circuit = my_circuit)
>>> b = Bus('byte_bus', 8, circuit = my_circuit)
Hierarchical circuits also work with Circuit objects. In the previous multi-level hierarchy example, the subcircuit could be instantiated into a Circuit object like this:
my_circuit = Circuit() # New Circuit object.
gnd = Net('GND') # GLobal ground net.
input_net = Net('IN') # Net with the voltage to be divided.
output_net = Net('OUT') # Net with the divided voltage.
my_circuit += gnd, input_net, output_net # Move the nets to the new circuit.
# Instantiate the multi-level hierarchical subcircuit into the new Circuit object.
multi_vdiv(3, input_net, output_net, circuit = my_circuit)
The actual circuit
parameter is not passed on to the subcircuit.
It’s extracted and any elements created in the subcircuit are sent there instead of
to the default circuit.
(If the circuit
argument is omitted, the subcircuit function uses the
default circuit as the target of its operations.)
You can do all the same operations on a Circuit object that are supported on the default circuit, such as:
# Check the circuit for errors.
my_circuit.ERC()
# Generate the netlist from the new Circuit object.
my_circuit.generate_netlist(sys.stdout)
Naturally, the presence of multiple, independent circuits creates the possibility of new types of errors. Here are a few things you can’t do (and will get warned about):
-
You can’t make connections between parts, nets or buses that reside in different Circuit objects.
-
Once a part, net, or bus is connected to something else in a Circuit object, it can’t be moved to a different Circuit object.
Converting Existing Designs to SKiDL
If you have an existing schematic-based design, you can convert it to SKiDL as follows:
-
Generate a netlist file for your design using whatever procedure your ECAD system provides. For this discussion, call the netlist file
my_design.net
. -
Convert the netlist file into a SKiDL program using the following command:
netlist_to_skidl -i my_design.net -o my_design.py -w
That’s it! You can execute the my_design.py
script and it will regenerate the
netlist. Or you can use the script as a subcircuit in a larger design.
Or do anything else that a SKiDL-based design supports.
SPICE Simulations
Now you can describe a circuit using SKiDL and run a SPICE simulation on it!


WITNESS LIST Appropriations-S/C on General Government Committee March 22, 2000-9:00A Interim On: Bass, James (Dept. of Transportation) Dally, Bill (Dept. of Housing and Community Affairs) Gaines, David (Dept. of Housing and Community Affairs) Hamilton, Billy (Comptroller's Office) Heald, Wes (Dept. of Transportation) Hoffpavir, Keith (Dept. of Housing and Community Affairs) Hughes, Lucien (State Auditor's Office) Ing, Leigh (TNRCC) Nichols, Robert (Dept. of Transportation) Pharr, Machelle (TNRCC) Rath, Diane (Texas Workforce Commission) Rathgeber, Julia (TNRCC) Saitas, Jeff (TNRCC) Simpson, Ryan (State Auditor's Office) Stiner, Daisy (Dept. of Housing and Community Affairs) Williams, Michael (Railroad Commission)


This Scatter chart has been configured to use datetime values for the X coordinates, the title has been customised slightly and the points have tooltips. The background grid has no vertical gridlines.
This goes in the documents header: Put this where you want the chart to show up:

This is the code that generates the chart - it should be placed AFTER the

tag:


---
layout: post
title: late payment letterhead
date: '2014-02-06T07:30:38+01:00'
categories:
- Freelance life
picture_url: https://film-Storyboards.tumblr.com/post/75793925810/late-payment-letterhead
---
This is a letterhead drawing for late payment notice.


Home Page
Salmon Cookies Calculation
Name of Store:
Min Customers:
Max Customers:
Avg Cookies Purchased:


{{ref improve|date=March 2013}} {{Infobox prepared food | name = Sam bo luong | image = Sâm bổ lượng.jpg | caption = | alternate_name = Chè sâm bổ lượng | country = China | region = | creator = | course = | type = Soup | served = Cold | main_ingredient = Job's tears, dried longans, red jujubes, lotus seeds, seaweed, sugar, water, ice | variations = | calories = | other = }} {{Chinese| t=清補涼| s=清补涼| p=qīng bǔ liáng| j=cing1 bou2 leung2<br>(NOT leung4)| vie=sâm bổ lượng }} Ching bo leung (also spelt ching po leung or qing bu liang from Chinese; sâm bổ lượng or chè sâm bổ lượng from Vietnamese, chè meaning "sweet soup") is a sweet, cold soup of Chinese origin and commonly served in Cantonese cuisine，Hainanese Cuisine and Vietnamese cuisine. It is a type of tong sui.
Although the exact recipe may vary, the drink generally contains Job's tears, dried longans, red jujubes, lotus seeds, and thinly sliced seaweed<!--What variety? Kombu?-->, with water, sugar, and crushed ice.<ref>Le Gia menu "Sâm Bổ Lượng. A refreshing Vietnamese drink with logan, lotus seeds, seaweed, red dates and agar jelly. " Toptable.co.uk</ref> In place of the Job's tears, pearl barley may sometimes be used, and thinly sliced strips of ginger and/or ginseng root, wolfberries, or ginkgo nuts may also appear as ingredients.
The Chinese form of the drink, ching bo leung, is the most popular in the Cantonese cuisine of Guangdong, Hong Kong, and Macau. It is sometimes known as Liuwei soup (六味湯, lit. Six flavour soup). The Vietnamese version, sâm bổ lượng, is most readily available in Cholon, the Chinatown of Ho Chi Minh City, and is generally served in a tall glass. Although it is sometimes described as a drink, the term "soup" is more appropriate as a spoon is generally necessary to consume the solid ingredients.
{{reflist}}


Choose from destinations in the PNW
Fly better with Evergreen and achieve unmatched comfort, delicious cuisine, and world-class entertainment.
De-stress in modern, high-quality leather seats and enjoy gourmet food options and hundreds of channels of entertainment. Free, fast WiFi and in-seat power allow for passengers to work while in the air.
Passengers of the Economy Class can enjoy free Wifi and in-seat power. Our airline makes flight as friendly as possible for children with kids' tv, games, and more onboard.
Evergreen can take you to destinations anywhere in the Pacific Northwest.
This international airport has a large variety of fun activities to do in its vicinity, encompassing interests of all ages and sizes. You can go hot air ballooning at Seattle Ballooning, a destination only 2 miles from the airport, or if you want to go visit the Space Needle, the Seattle Light Rail Service within a mile of the airport allows you to do just that. For children, there is the Seattle Chocolate Factory Store and Angle Lake Park where they can enjoy playing in the sun. Those who are more mature can enjoy Boeing's Museum of Flight and go skydiving in IFLY's Indoor Skydiving facility. With all of these destinations within 5 miles of the airport, you're guaranteed to have a good time.
Welcome to the Inland Northwest! If you're have an adventurous spirit, then this airport is for you! Within 10 miles of the airport, you can experience very aspect of nature: You can zipline with Mica Moon Zip Tours, go strolling in the grandoise Manito Park, visit the beautiful Spokane Falls, and even go whiteWater rafting on the Spokane River.
Are you looking for an escape from the your daily bustling life in the city? Then Portlad International Airport may be the destination for you. This destination offers many quiet, outdoor activities for you to enjoy. With food and drink like the Great Oregon Wine Tour, you can immerse yourself in the local cuisine. After getting a bike rental from Everybody's Bike Rentals and Tours you can explore the Columbia River Gorge and the "Grotto" a peaceful Catholic sanctuary built with 62 different acres of botanical gardens. With many other small peaceful activities, you'll enjoy Portland as a getaway.
This international airport offers many cultural activities for you to immerse yourself in. Within 10 miles of the airport, you can explore the Oregon Air and Space Museum, the Hult Center of Performing Arts, Museum of National and Cultural History, and even the widely famous Jordan Schnitzer Museum of Art. Coupled with smaller exercusions to local saturday farmer markets or a variety of parks keeps this location well connected.
If you have a strong connection to nature and thirst for adventure than Medford is your ideal trip. Due to its closeness to the Rouge River, this location has many rafting and touring areas surruounding it. You can travel through a variety of lakes (Diamond, AppleGate, and Howard Prairie) and camp or fish to your hearts content. Coupled with many wineries, this location has an excellent local night life to party in.
Boise offers a multitude of cultural and historical outfits for your family to enjoy. Relive the famous diary in the Idaho Anne Frank Human Rights Memorial and view a history of our armed forces in the Idaho Military History Museum. Add in the availablity to go explore the Rockies, and the availablity of parks such as the Kathryn Albertson park and Julia Davis Park, allows for something for everyone to enjoy.
Fly through the skies of the Pacific Northwest.
ApplyJoin the Evergreen crew, forming the face of the company.
ApplyWork at Evergreen Tower in our Seattle HQ.
ApplyBe part of our journey into the future of technology.
ApplyRepresent Evergreen as a liason with our customers.
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CertWare Tips
- Use the "new" wizards to create a new ARM, AML, GSN, CAE, or EUROCONTROL argument model.
- There are two types of models available for some argument styles: a diagram model type and a structured tree model type.
- Use the examples wizard to populate a project with predefined safety case artifacts.
- Save diagram image fragments to the workspace as resources, then link to them in wikitext documents.
- Manage the safety case artifacts with the EGit team provider.


Estimate the Deterministic Input, Noisy "And" Gate (DINA) cognitive diagnostic model parameters using the Gibbs sampler described by Culpepper (2015) <doi:10.3102/1076998615595403>.
| Version: | 1.0.2 |
| Depends: | R (≥ 3.0.2) |
| Imports: | Rcpp (≥ 0.12.10) |
| LinkingTo: | Rcpp (≥ 0.12.10), RcppArmadillo (≥ 0.7.800) |
| Published: | 2017-04-26 |
| Author: | Steven Andrew Culpepper [aut, cph, cre] |
| Maintainer: | Steven Andrew Culpepper <sculpepp at illinois.edu> |
| BugReports: | https://github.com/tmsalab/dina/issues |
| License: | GPL-2 | GPL-3 [expanded from: GPL (≥ 2)] |
| URL: | https://github.com/tmsalab/dina |
| NeedsCompilation: | yes |
| Citation: | dina citation info |
| Materials: | README NEWS |
| CRAN checks: | dina results |
| Reference manual: | dina.pdf |
| Package source: | dina_1.0.2.tar.gz |
| Windows binaries: | r-devel: dina_1.0.2.zip, r-release: dina_1.0.2.zip, r-oldrel: dina_1.0.2.zip |
| OS X binaries: | r-release: dina_1.0.2.tgz, r-oldrel: dina_1.0.2.tgz |
| Old sources: | dina archive |
Please use the canonical form https://CRAN.R-project.org/package=dina to link to this page.


The popup component shows in the middle of the screen a list of items in a pop-up window. It automatically optimizes the pop-up window size within the screen. The following table describes the supported popup classes.
To open or close the popup component, use the methods listed in the following table.
| Method | Description |
|---|---|
| tau.openPopup(to) | Opens a popup by calling the openPopup() method. The to argument is a pop-up container object or string. |
| tau.closePopup() | Closes a popup by calling the closePopup() method. |
To find the currently active popup, use the ui-popup-active class.
To bind the popup to a button, use the following code:

Power saving mode

 <button id="1btnPopup-cancel" class="ui-btn">Cancel</button>

/* JavaScript code */
The following table lists the events related to pop-ups.
| Event | Description |
|---|---|
| popupbeforecreate | Triggered when the pop-up is initialized, before most plugin auto-initialization occurs. |
| popupcreate | Triggered when the pop-up has been created in the DOM (for example, through Ajax) but before all UI Components have had an opportunity to enhance the contained markup. |
| popupbeforehide | Triggered on the pop-up we are transitioning away from, before the actual transition animation is kicked off. |
| popuphide | Triggered on the pop-up we are transitioning away from, after the transition animation has completed. |
| popupbeforeshow | Triggered on the pop-up we are transitioning to, before the actual transition animation is kicked off. |
| popupshow | Triggered on the pop-up we are transitioning to, after the transition animation has completed. |
To use popup events, use the following code:

/* JavaScript code */


You can display a build log, revision log, or system log by selecting a build in Projects tab or Builds tab and clicking on appropriate toolbar button or select menu item from toolbar menu or popup menu.
When you display a build log of the currently running build, the build log will get refreshed and scrolled to the bottom of the log with twice the frequency set for the current Luntbuild connection.


“A fondness for trifles is certainly no less conspicuous in age than youth; and we daily see it among persons of the best understanding, who wholly neglect every essential to real happiness in the pursuit of those very toys which children cry to be indulged in; even such as a bit of ribband, or the sound of a monosyllable tacked to the name; without considering that those badges of distinction, like bells about an idiot's neck, frequently serve only to render their folly more remarkable, and expose them to the contempt of the lookers on, who perhaps too, as nature is the same in all, want but the same opportunity to catch no less eagerly at the tawdry gewgaw.” — Eliza Fowler Haywood, Life's Progress Through The Passions, or The Adventures Of Natura


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This Website is for anyone who loves to cook and for everyone who doesn’t.
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Innovation Fund supports circularity
by Staff reporterThe European Commission’s Innovation Fund is one of the largest in the world focussed on accelerating investments in low-carbon tech. For circular economy innovators, this fund could help them realise their ambitions. More on what it can offer circular economy stakeholders will be explained in a workshop being held in Brusselson 3 December. You need to register by 26 November though, so pretty much now.


6-yo son saved up to buy a skateboard with cool artwork on bottom.
:immediately plasters board with stickers:
Perfect
1/5/2018, 2:26:28 PM
Favs: 7
Retweets: 0
link--- layout: tweet ---
6-yo son saved up to buy a skateboard with cool artwork on bottom.
:immediately plasters board with stickers:
Perfect
1/5/2018, 2:26:28 PM
Favs: 7
Retweets: 0
link


--- title: Overview permalink: /admin-template/overview/ layout: admin-template/layouts-single-side-nav --- {% include admin-template/base.html %}
| # | Name | Payment Method | Price | Status |
| 1 | Lorem ipsum | Credit Card | $65.00 | Delivered |
| 2 | Lorem ipsum | Credit Card | $65.00 | Processing |
| 3 | Lorem ipsum | Credit Card | $65.00 | Canceled |
| # | Product Name | total Order |
| 1 | Lorem ipsum | $65.00 |
| 2 | Lorem ipsum | $65.00 |
| 3 | Lorem ipsum | $65.00 |


Welcome to the SVUUS Auction Website! Thank you for participating. It should be a great party!
To get started on the site, click the “Register” button above to create an account.  This is useful so that if you donate an item, others can see who you are and who donated it. Try to use a closeup photo of faces.
Second, buy tickets for you and your family members who are attending.
Note #1: We have caregivers this year for the youngest ones. Bring your babies or find a babysitter. But make sure to register them on "Buy Tickets" so that we have a good count (don't worry, they don't cost anything).
Note #2: The credit card you use to buy your tickets will be used to pay your final invoice after the auction.
Third, donate items to auction. If you need suggestions, you can click below.
If you have not been to one of our auctions before, there’s a “Donation Ideas” button on the donation page that’ll get you started.
The Auction will start promptly at 6:00pm on Saturday, November 11th. There are no physical tickets. Just show up and we’ll give you your bid card.
Questions? Email<EMAIL_ADDRESS>Thanks!


{% extends "layout.html" %} {% load currency_filters %} {% block header %}
Your order has been placed - your order number is {{order.number}}
Please make a note of this reference or print this page and quote it in any communication with us regarding your order.
Your order will be delivered to:
| Product | Estimated dispatch date | Quantity | Line price excl tax | Line price incl tax |
|---|---|---|---|---|
| {{ line.description }} | {{ line.est_dispatch_date }} | {{ line.quantity }} | {{ line.line_price_before_discounts_excl_tax|currency }} | {{ line.line_price_before_discounts_incl_tax|currency }} |
| {{ discount.offer }} | - {{ discount.amount|currency }} | |||
| Basket total | {{ order.basket_total_excl_tax|currency }} | {{ order.basket_total_incl_tax|currency }} | ||
| Shipping charge - {{order.shipping_method}} | {{ order.shipping_excl_tax|currency }} | {{ order.shipping_incl_tax|currency }} | ||
| Order total | {{ order.total_incl_tax|currency }} |


Heart of Warding:
You are overcome by a voice, a voice so powerful you are helpless as it speaks.
Do not expect Shilen's authority will diminish
while false gods freely roam.
Leave, and
prepare to face the return of Antharas.
(Challenging Antharas is not currently available.)


--- layout: post title: "The Definition of a Netbook" ---
A small, cheap, low spec computer nobody wants or has any use for.


Path of Exile 2 has been officially announced, will have a massively improved engine for graphics & physics
by John PapadopoulosGrinding Gear Games has officially announced Path of Exile 2. However, will not be a separate/standalone game. Instead, Path of Exile 2 will overhaul the mechanics and engine of the base game, and introduce some new elements to it. Basically, think of it as a huge expansion that will also enhance the base game.
Path of Exile 2 is a new seven-act storyline that will be available alongside the original Path of Exile 1 campaign. Moreover, both the old and new storyline lead to the same shared Atlas endgame. Path of Exile 2 will retain all expansion content that Grinding Gear released for the first game. It will also introduce a new skill system, ascendancy classes, engine improvements and more.
According to the team, Path of Exile 2 will feature a massively improved engine for graphics & physics. Furthermore, the game will have 19 new ascendancy classes. These characters are a new set of Exiles who fall into the same class archetypes as those in the original game.
Unfortunately, there is no ETA on when the game will come out. Still, you can find below its first gameplay trailer (as well as its announcement trailer).
Enjoy!


%= processTemplate('_head') %>
We proudly serve the greater Atlanta area. Choose a county below to find your neighborhood.
About
Specials


Hi All
It's been a while, but I've decided to resurrect my monitoring system with a NanodeRF (multiple Pi failures)
It's not arrived in the post yet, but in preparation I've been trying and I've struggled to compile the sketch. It's been a while since I set my previous system up, and I'm wondering if the updated libraries/new Arduino version has confused things (none of my previously working emonTX sketches compile either).
Sticking with the Nanode RF issues:
I have an account on emoncms.org - do I need my username in the website[] or a subdirectory in basedir[]?
I get a multiple complie Errors:
// 1) Set this to the domain name of your hosted emoncms - leave blank if posting to IP address
char website[] PROGMEM = "emoncms.org";
This returns the error: variable 'website' must be const in order to be put into read-only section by means of '__attribute__((progmem))'
IF I change the code to const char website[] PROGMEM = "emoncms.org"; it compiles ok - but will it work?
and
NanodeRF_multinode:236: error: 'void my_callback(byte, word, word)' was declared 'extern' and later 'static' [-fpermissive]
static void my_callback (byte status, word off, word len) {
and
NanodeRF_multinode:110: error: previous declaration of 'void my_callback(byte, word, word)' [-fpermissive]
//Nanode RF LED indictor setup - green flashing means good - red on for a long time means bad!
I hope it's something simple!
Thanks
Re: NanodeRF Compile Issues on Arduino 1.6.6 & NanodeRF_multinode
I seem to remember reading somewhere that later Arduino IDEs have made some changes to the way the 1.6 compiler works and where it puts things, and I've got a vague recollection that it was to do with variable declarations etc. Probably a search of the Arduino forums will shed some light on it. Failing that, you could always revert to Arduino 1.0.x (1.0.5 is still the one in the Ubuntu repo, which is the version I'm using!)
"I have an account on emoncms.org - do I need my username in the website[] or a subdirectory in basedir[]?"
You don't need your username at all. Your APIKey is the equivalent of username + password (so don't publish it on the forum!)


{% extends 'base.html' %} {% load staticfiles %} {% load crispy_forms_tags %} {% crispy postsearch_form postsearch_form.helper %} {% csrf_token %} {% block head_content %} {% endblock %} {% block content %}
These are the instructions for creating/modifying a navicat importer. An importer is a task that maps spreadsheet data to a database table.
The basic steps are as follows:
| Open your target spreadsheet in Excel. Save the file in the windows comma seperated values (csv) format, to a temporary holding directory (e.g. ADVERTISING/Inserts/MAGETRAC/csv/ or, if on the server workstation - /Users/imagetracdb/b5crontab/temp/). |
| open the newly created csv file in Sublime Text. Simply resave the file with UTF-8 encoding: | |
| from the tables screen in navicat, click "Import" on the footer. |
| though you have a choice of file formats, normally you will want to use csv | click "Add File" and navigate to your csv | click "continue" | uncheck 4 digit years | choose the database table to which you'll be adding data | for each table field, indicate the corresponding csv data column | choose your preferred import behavior | choose "Save as" to name yout task; "Save" to simply save a modification; or "Start" to run your task. |


Hello my name is {{speaker.name}} !
The Ionic Conference is a one-day conference featuring talks from the Ionic team. It is focused on Ionic applications being built with Ionic 2. This includes migrating apps from Ionic 1 to Ionic 2, Angular concepts, Webpack, Sass, and many other technologies used in Ionic 2. Tickets are completely sold out, and we’re expecting more than 1000 developers – making this the largest Ionic conference ever!


select
, multi-selectionHere, a multi-selection select
is rendered using an array of strings.
model
Here, a multi-selection select
is rendered using an array of objects, and
the selected option
s' model
are added to the array bound to the
select
's value
.
value
Here, a multi-selection select
is rendered using an array of objects, and
the selected option
s' value
are added to the array bound to
the select
's value
.


--- layout: blog ---
There's only darkness out here in the wild.
It ish sadly true, the requested page was not found :(
I want to go back home now, but thank you


Also Try: 35 Best Malls in Dubai (FREE!)
You’ll be spoiled for choice and your biggest problem will be choosing what to purchase. Dominant local brands compete with 100s of small gold merchants at this world-renowned gold souk. Dubai has developed a reputation for having low gold prices and that’s the cause of this market’s booming global popularity. If you’re in a budget, many shops here also sell gold-plated and gold-filled jewelry. This is a destination for your jewelry needs regardless of your budget. Also Try: Essential Things to See & Do in Dubai (Do NOT Miss Out!)
Location: Deira, Dubai, United Arab Emirates
Dubaing Score: 5/5
Crafting scents has been a feature of Gulf traditions for centuries. The locally developed scents are called oud, and they are natural made from herbs, spices, and secret ingredients exclusive to different merchants. Local perfume brands and traditional scents crowd this souk so you’ll have options for a scent like never before. Expect to be handed 2 to 3 samples every second, but have no worries as all the merchants are polite and extremely respectful; after all, they do want to secure that sale. The best part is that some merchants here will create a custom scent just to match your personality! This souk is an amazing Dubai destination. Also Try: Best FREE Beaches in Dubai (Yes, FREE!)
Location: Deira, Dubai, United Arab Emirates
Dubaing Score: 5/5
One of the oldest souks in not just Dubai, but the entire United Arab Emirates. You’ll find a bustling, vibrant atmosphere, where each shop is colorful and bright due to the fragrant herbs and spices it carries; everything from cardamom, ginger, cinnamon, cloves, vanilla pods and saffron, to shisha tobacco and pipes, stunning traditional lamps, and homewares is available here. Even if spices aren’t your part of your palate, this is a great opportunity to appreciate a massive, authentic souk. Also Try: Ranked Dubai’s Adventure Zones (Most will FAIL!)
Location: Deira, Dubai, United Arab Emirates
Dubaing Score: 5/5
You can find every fabric, texture, and textile imaginable here. From yards of raw beautiful silks, handmade embroidery and saris to traditional Arab dress, this market has it all! The Dubai Textile Souk hosts merchants from across the globe selling their prized materials, all clustered in one convenient spot. You are about to be spoiled with choices! Additionally, this souk has maintained its traditional roots so the classical Arabian architecture remains to date, making a trip here a double combo. Also Try: Dubai’s Best Water Sports (Some are SCARY!)
Location: Bur Dubai, Dubai, United Arab Emirates
Dubaing Score: 4.5/5
If you hear or read Jumeirah, expect luxury. This extremely popular souk mixes traditional architecture with modern infrastructure and luxury. The architecture and shop alignment are themed on traditional Arabian designs. You won’t be able to haggle here as the prices are fixed; often, the rates will be quite pricey. This is an experience in itself as location is beautiful and is a small distance from the Burj al Arab. Also Try: Top Water Adventures in Dubai
Location: Jumeirah, Dubai, United Arab Emirates
Dubaing Score: 4.5/5
A market dedicated to local arts and crafts! The only drawbacks is that its available exclusively on the first and second Fridays of every month. This spot features some established local artists and plenty of up-and-coming young talents. This is both a platform that is an opportunity for many to showcase their work, and a platform for many to spectate, observe, and purchase inspiring, beautiful pieces of artwork.
Location: Festival City, Dubai, United Arab Emirates (first Friday); Times Square Center, Dubai, United Arab Emirates (second Friday)
Dubaing Score: 3.5/5
This is one of Dubai’s modern souks, which blend traditional Arabian architecture with modern infrastructure and luxury; it’s located next to the Burj al Khalifa. Bargains and haggles are not a part of this souk as prices are fixed and will often be quite high as many shops exclusively sell luxury products.
Location: Downtown Dubai, Dubai, United Arab Emirates
Dubaing Score: 3.5/5
Dubai is fulfilling all forms of demands. This is an “up-to-trend” market dedicated to vintage accessories, hand-made products, fair-trade products, art, and photography. This market is outdoors and most stalls are small and exclusive to a specific genre of products. While it’s a dwarf compared to competing souks, this one is placed on the Marina Walk; you’ll have plenty of amazing dining options and a wonderful option of taking a walk beside a man-made Marina in Dubai. Also Try: 5 Best Promenades in Dubai
Location: Marina, Dubai, United Arab Emirates
Dubaing Score: 3/5
Based on a legend of the most bustling souk in the world, this location in Wafi offers over a 150 stalls specializing in traditional arts and crafts, with influences drawn from as far away as Andalucía in Southern Spain to the mountains of Afghanistan. This market is essentially an extension of a mall so it’s going to give only a remote feeling of a souk. While it may not offer the traditional vibe, it still holds up as a decent place to shop.
Location: Wafi, Dubai, United Arab Emirates
Dubaing Score: 2.5/5
Once a prominent market for camel traders, Naif Souq has developed into a marketplace. You won’t get the traditional feel and vibe you’d receive from other souks in Dubai and the setting has a feel of a warehouse adorned with shops. Nonetheless, this is a popular destination for bargains on watches and leather handbags.
Location: Deira, Dubai, United Arab Emirates
Dubaing Score: 2.5/5
This is not a traditional souk. Rather, it’s an open plaza-style marketplace selling pretty much anything. The prime draw here are the counterfeit branded products sold at many of the shops at dirt-cheap rates.
Location: Karama, Dubai, United Arab Emirates
Dubaing Score: 2.5/5
If you are the owner or manager of a relevant business/institution and feel your business/institution has been overlooked, please contact us at Enquiry@Dubaing.ae


| Properties' Summary |
[ readonly ] long
Id |
returns the function's unique identifier.
|
[ readonly ] long
Category |
returns the function's category.
|
[ readonly ] string
Name |
returns the localized function's name.
|
[ readonly ] string
Description |
returns a localized description of the function.
|
[ readonly ] sequence< FunctionArgument >
Arguments |
returns a sequence of localized descriptions of the function's
arguments (in the order specified by the function).
|
| Properties' Details |
Id
[ readonly ] long Id;
- Description
- returns the function's unique identifier.
- See also
- XFunctionDescriptions
|
|
Category
[ readonly ] long Category;
- Description
- returns the function's category.
- See also
- FunctionCategory
|
|
Name
[ readonly ] string Name;
- Description
- returns the localized function's name.
|
|
Description
[ readonly ] string Description;
- Description
- returns a localized description of the function.
|
|
Arguments
[ readonly ] sequence< FunctionArgument > Arguments;
- Description
- returns a sequence of localized descriptions of the function's
arguments (in the order specified by the function).
|
|
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Copyright © 2013, The Apache Software Foundation, Licensed under the Apache License, Version 2.0. Apache, the Apache feather logo, Apache OpenOffice and OpenOffice.org are trademarks of The Apache Software Foundation. Other names may be trademarks of their respective owners.


--- layout: minimal title: "About me" permalink: /about/index.html description: "Some description about Went Lee..." ---
Currently I am first year graduate student of Department of Computer Science and Technology in Nanjing University and a member of LAMDA Group, led by professor Zhi-Hua Zhou.


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27 years old, male, Russia, Irkutsk
My interests
Mounting bikes
pumptrack
downhill
riding with friends
snowboarding
coding
playing with Peche (cat)
fur-fur
hiding and hunting for shoes
sitting as
a family
on a coach


 Masanga Hospital will receive DKK {{amount}} if you make it! {% endblocktrans %}
{% include "_email_quotation.html" with quote=challenge_text %}{% blocktrans %} We assume that you want to make an attempt - therefore you don't need to do anything, but getting on your running shoes. {% endblocktrans %}
{% blocktrans %} When the challenge ends at {{end_date}} you will receive a mail, asking you to tell if you completed successfully or not. Alternatively you can login and update the challenge whenever you want. {% endblocktrans %}
{% blocktrans %} Good luck! {% endblocktrans %}
{% endblock %}


Home
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music main
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{% load static %}
Covid19India News
{% include 'newsapp/nav.html' %}
Total Confirmed
Total Active
Total Recovered
Total Deceased
Spread Trends
{% for key,value in code_map.items %}
{{ value }}
{% endfor %}
District
Confirmed
Active
Deceased
Recovered


| PReport |
| Under aggregated values are understood the report summary, group summary, group average and so on. For calculation of such values in the PReport the variables are used, these variables are represented by the TprValue class. The variables can be system and user. The system variables are added automatically by report, in current version of PReport two system variables exist:
The user variables created by developer when he designs the report template.
|


We're open source.
You're free to copy, remix, modify, and do whatever with our art/code/music.
We're open design.
You can give feedback on the game's design, shaping it as it goes.
We're open funding.
You, our fans and communities, help support this game's development.
By giving up "power" over our art, our art has more power.


Cubs exercise Rizzo’s $16.5M option, decline Morrow, Barnett
CHICAGO (AP) - The Cubs have exercised a $16.5 million option for next season on first baseman Anthony Rizzo and declined options on right-handers Brandon Morrow, Tony Barnette and Kendall Graveman.
Rizzo, who won his third Gold Glove on Sunday, agreed in 2013 to a $41 million, seven-year contract that included two club options. He would have received a $2 million buyout if the option had been declined.
Chicago’s option for 2021 also is for $16.5 million with a $2 million buyout. If that is exercised, the deal would be worth $72 million over nine seasons.
Morrow’s option was for $12 million, and he will receive a $3 million buyout. Barnett and Graveman both had options for $3 million.
More AP MLB: https://apnews.com/MLB and https://twitter.com/AP_Sports
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