| __IO uint32_t PWM_T::CLKPSC |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | CLKPSC01 | PWM Counter Base-Clock Prescale For PWM Pair Of Channel 0 And Channel 1 |
| The base-clock of PWM counter is decided by clock pre-scalar and clock divider. | ||
| Each PWM pair share one PWM counter base-clock prescaler. | ||
| The base-clock of PWM counter is divided by (CLKPSC01 + 1). | ||
| If the value of CLKPSC01 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop. | ||
| [8:15] | CLKPSC23 | PWM Counter Base-Clock Prescale For PWM Pair Of Channel 2 And Channel 3 |
| The base-clock of PWM counter is decided by clock pre-scalar and clock divider. | ||
| Each PWM pair share one PWM counter base-clock prescaler. | ||
| The base-clock of PWM counter is divided by (CLKPSC23 + 1). | ||
| If the value of CLKPSC23 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop. | ||
| [16:23] | CLKPSC45 | PWM Counter Base-Clock Prescale For PWM Pair Of Channel 4 And Channel 5 |
| The base-clock of PWM counter is decided by clock pre-scalar and clock divider. | ||
| Each PWM pair share one PWM counter base-clock prescaler. | ||
| The base-clock of PWM counter is divided by (CLKPSC45 + 1). | ||
| If the value of CLKPSC45 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop. |
Definition at line 19068 of file NUC472_442.h.
| __IO uint32_t CLK_T::CLKSEL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:2] | HCLKSEL | HCLK Clock Source Selection (Write Protect) |
| Before clock switching, the related clock sources (both pre-select and new-select) must be turned on | ||
| 1. | ||
| The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. | ||
| Therefore the default value is either 000b or 111b. | ||
| 2. | ||
| These bits are protected bit, it means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register REGWRPROT at address GCR_BA+0x100. | ||
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from PLL clock. | ||
| 011 = Clock source from LIRC clock. | ||
| 100 = Clock source from PLL2 clock. | ||
| 111 = Clock source from HIRC clock. | ||
| Other = Reserved. | ||
| [3:5] | STCLKSEL | Cortex(TM)-M4 SysTick Clock Source Selection (Write Protect) |
| If SYST_CSR[2]=0, SysTick uses listed clock source below. | ||
| These bits are protected bit. | ||
| It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register REGWRPROT at address GCR_BA+0x100. | ||
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from HXT clock/2. | ||
| 011 = Clock source from HCLK/2. | ||
| 111 = Clock source from HIRC clock/2. | ||
| [6] | PCLKSEL | PCLK Clock Source Selection (Write Protect) |
| These bits are protected bit. | ||
| It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register REGWRPROT at address GCR_BA+0x100. | ||
| 0 = Clock source from HCLK. | ||
| 1 = Clock source from HCLK/2. | ||
| [8] | USBHSEL | USB Host Clock Source Selection (Write Protect) |
| These bits are protected bit. | ||
| It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register REGWRPROT at address GCR_BA+0x100. | ||
| 0 = Clock source from PLL2. | ||
| 1 = Clock source from PLL. | ||
| [16:17] | CAPSEL | Image Capture Interface Clock Source Selection |
| These bits are protected bit. | ||
| It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register REGWRPROT at address GCR_BA+0x100. | ||
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = Clock source from HCLK. | ||
| 11 = Clock source from HIRC clock. | ||
| [20:21] | SDHSEL | SDHOST Engine Clock Source Selection |
| These bits are protected bit. | ||
| It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register REGWRPROT at address GCR_BA+0x100. | ||
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = Clock source from HCLK. | ||
| 11 = Clock source from HIRC clock. |
Definition at line 3120 of file NUC472_442.h.
| __IO uint32_t CLK_T::CLKSEL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | WDTSEL | Watchdog Timer Clock Source Selection (Write Protect) |
| These bits are protected bit,and programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register REGWRPROT at address GCR_BA+0x100. | ||
| 00 = Clock source from 4~24 MHz external high-speed crystal clock. | ||
| 01 = Clock source from LXT clock. | ||
| 10 = Clock source from HCLK/2048 clock. | ||
| 11 = Clock source from LIRC clock. | ||
| [2:3] | EADCSEL | ADC Clock Source Selection |
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = Clock source from PCLK. | ||
| 11 = Clock source from HIRC clock. | ||
| [4] | SPI0SEL | SPI0 Clock Source Selection |
| 0 = Clock source from PLL clock. | ||
| 1 = Clock source from PCLK. | ||
| [5] | SPI1SEL | SPI1 Clock Source Selection |
| 0 = Clock source from PLL clock. | ||
| 1 = Clock source from PCLK. | ||
| [6] | SPI2SEL | SPI2 Clock Source Selection |
| 0 = Clock source from PLL clock. | ||
| 1 = Clock source from PCLK. | ||
| [7] | SPI3SEL | SPI3 Clock Source Selection |
| 0 = Clock source from PLL clock. | ||
| 1 = Clock source from PCLK. | ||
| [8:10] | TMR0SEL | TIMER0 Clock Source Selection |
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from PCLK. | ||
| 011 = Clock source from external trigger. | ||
| 101 = Clock source from LIRC clock. | ||
| 111 = Clock source from HIRC clock. | ||
| Others = reserved. | ||
| [12:14] | TMR1SEL | TIMER1 Clock Source Selection |
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from PCLK. | ||
| 011 = Clock source from external trigger. | ||
| 101 = Clock source from LIRC clock. | ||
| 111 = Clock source from HIRC clock. | ||
| Others = reserved. | ||
| [16:18] | TMR2SEL | TIMER2 Clock Source Selection |
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from PCLK. | ||
| 011 = Clock source from external trigger. | ||
| 101 = Clock source from LIRC clock. | ||
| 111 = Clock source from HIRC clock. | ||
| Others = reserved. | ||
| [20:22] | TMR3SEL | TIMER3 Clock Source Selection |
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from PCLK. | ||
| 011 = Clock source from external trigger. | ||
| 101 = Clock source from LIRC clock. | ||
| 111 = Clock source from HIRC clock. | ||
| Others = reserved. | ||
| [24:25] | UARTSEL | UART Clock Source Selection |
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10/11 = Clock source from HIRC clock. | ||
| [28:29] | CLKOSEL | Clock Divider Clock Source Selection |
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from LXT clock. | ||
| 10 = Clock source from HCLK. | ||
| 11 = Clock source from HIRC clock. | ||
| [30:31] | WWDTSEL | Window Watchdog Timer Clock Source Selection |
| 00 = Reserved. | ||
| 01 = Reserved. | ||
| 10 = Clock source from HCLK/2048 clock. | ||
| 11 = Clock source from LIRC clock. |
Definition at line 3200 of file NUC472_442.h.
| __IO uint32_t CLK_T::CLKSEL2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:2] | PWM0CH01SEL | PWM0_0 And PWM0_1 Clock Source Selection |
| PWM0_0 and PWM0_1 uses the same Engine clock source, both of them use the same prescaler. | ||
| The Engine clock source of PWM0_0 and PWM0_1 is defined by PWM0CH01SEL[2:0]. | ||
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from PCLK. | ||
| 011 = Clock source from HIRC clock. | ||
| 100 = Clock source from LIRC clock. | ||
| Other = Reserved. | ||
| [4:6] | PPWM0CH23SEL | PWM0_2 And PWM0_3 Clock Source Selection |
| PWM0_2 and PWM0_3 uses the same Engine clock source, both of them use the same prescaler. | ||
| The Engine clock source of PWM0_2 and PWM0_3 is defined by PPWM0CH23SEL[2:0]. | ||
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from PCLK. | ||
| 011 = Clock source from HIRC clock. | ||
| 100 = Clock source from LIRC clock. | ||
| Other = Reserved. | ||
| [8:10] | PWM0CH45SEL | PWM0_4 And PWM0_5 Clock Source Selection |
| PWM0_4 and PWM0_5 used the same Engine clock source; both of them use the same prescaler. | ||
| The Engine clock source of PWM0_4 and PWM0_5 is defined by PWM0CH45SEL[2:0]. | ||
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from PCLK. | ||
| 011 = Clock source from HIRC clock. | ||
| 100 = Clock source from LIRC clock. | ||
| Other = Reserved. | ||
| [12:14] | PWM1CH01SEL | PWM1_0 And PWM1_1 Clock Source Selection |
| PWM1_0 and PWM1_1 uses the same Engine clock source, both of them use the same prescaler. | ||
| The Engine clock source of PWM1_0 and PWM1_1 is defined by PWM1CH01SEL[2:0]. | ||
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from PCLK. | ||
| 011 = Clock source from HIRC clock. | ||
| 100 = Clock source from LIRC clock. | ||
| Other = Reserved. | ||
| [16:18] | PWM1CH23SEL | PWM1_2 And PWM1_3 Clock Source Selection |
| PWM1_2 and PWM1_3 uses the same Engine clock source, both of them use the same prescaler. | ||
| The Engine clock source of PWM1_2 and PWM1_3 is defined by PWM1CH23SEL[2:0]. | ||
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from PCLK. | ||
| 011 = Clock source from HIRC clock. | ||
| 100= Clock source from LIRC clock. | ||
| Other = Reserved. | ||
| [20:22] | PWM1CH45SEL | PWM1_4 And PWM1_5 Clock Source Selection |
| PWM1_4 and PWM1_5 used the same Engine clock source; both of them use the same prescaler. | ||
| The Engine clock source of PWM1_4 and PWM1_5 is defined by PWM1CH45SEL[2:0]. | ||
| 000 = Clock source from HXT clock. | ||
| 001 = Clock source from LXT clock. | ||
| 010 = Clock source from PCLK. | ||
| 011 = Clock source from HIRC clock. | ||
| 100 = Clock source from LIRC clock. | ||
| Other = Reserved. |
Definition at line 3264 of file NUC472_442.h.
| __IO uint32_t CLK_T::CLKSEL3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | SC0SEL | SC0 Clock Source Selection |
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = PCLK. | ||
| 11 = Clock source from HIRC clock. | ||
| [2:3] | SC1SEL | SC1 Clock Source Selection |
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = PCLK. | ||
| 11 = Clock source from HIRC clock. | ||
| [4:5] | SC2SEL | SC2 Clock Source Selection |
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = PCLK. | ||
| 11 = Clock source from HIRC clock. | ||
| [6:7] | SC3SEL | SC3 Clock Source Selection |
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = PCLK. | ||
| 11 = Clock source from HIRC clock. | ||
| [8:9] | SC4SEL | SC4 Clock Source Selection |
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = PCLK. | ||
| 11 = Clock source from HIRC clock. | ||
| [10:11] | SC5SEL | SC5 Clock Source Selection |
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = PCLK. | ||
| 11 = Clock source from HIRC clock. | ||
| [16:17] | I2S0SEL | I2S0 Clock Source Selection |
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = Clock source from PCLK. | ||
| 11 = Clock source from HIRC clock. | ||
| [18:19] | I2S1SEL | I2S1 Clock Source Selection |
| 00 = Clock source from HXT clock. | ||
| 01 = Clock source from PLL clock. | ||
| 10 = Clock source from PCLK. | ||
| 11 = Clock source from HIRC clock. |
Definition at line 3314 of file NUC472_442.h.
| __IO uint32_t CAN_IF_T::CMASK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DAT_B | Access Data Bytes [7:4] |
| Write Operation: | ||
| 0 = Data Bytes [7:4] unchanged. | ||
| 1 = Transfer Data Bytes [7:4] to Message Object. | ||
| Read Operation: | ||
| 0 = Data Bytes [7:4] unchanged. | ||
| 1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register. | ||
| [1] | DAT_A | Access Data Bytes [3:0] |
| Write Operation: | ||
| 0 = Data Bytes [3:0] unchanged. | ||
| 1 = Transfer Data Bytes [3:0] to Message Object. | ||
| Read Operation: | ||
| 0 = Data Bytes [3:0] unchanged. | ||
| 1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register. | ||
| [2] | TxRqst_NewDat | Access Transmission Request Bit When Write Operation |
| 0 = TxRqst bit unchanged. | ||
| 1 = Set TxRqst bit. | ||
| Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored. | ||
| Access New Data Bit when Read Operation. | ||
| 0 = NewDat bit remains unchanged. | ||
| 1 = Clear NewDat bit in the Message Object. | ||
| Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. | ||
| The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits. | ||
| [3] | ClrIntPnd | Clear Interrupt Pending Bit |
| Write Operation: | ||
| When writing to a Message Object, this bit is ignored. | ||
| Read Operation: | ||
| 0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged. | ||
| 1 = Clear IntPnd bit in the Message Object. | ||
| [4] | Control | Control Access Control Bits |
| Write Operation: | ||
| 0 = Control Bits unchanged. | ||
| 1 = Transfer Control Bits to Message Object. | ||
| Read Operation: | ||
| 0 = Control Bits unchanged. | ||
| 1 = Transfer Control Bits to IFn Message Buffer Register. | ||
| [5] | Arb | Access Arbitration Bits |
| Write Operation: | ||
| 0 = Arbitration bits unchanged. | ||
| 1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object. | ||
| Read Operation: | ||
| 0 = Arbitration bits unchanged. | ||
| 1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register. | ||
| [6] | Mask | Access Mask Bits |
| Write Operation: | ||
| 0 = Mask bits unchanged. | ||
| 1 = Transfer Identifier Mask + MDir + MXtd to Message Object. | ||
| Read Operation: | ||
| 0 = Mask bits unchanged. | ||
| 1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register. | ||
| [7] | WR_RD | Write / Read Mode |
| 0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers. | ||
| 1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register. |
Definition at line 931 of file NUC472_442.h.
| __IO uint32_t SDH_T::CMDARG |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | ARGUMENT | SD Command Argument |
| This register contains a 32-bit value specifies the argument of SD command from host controller to SD card. | ||
| Before trigger COEN (SDH_CTL [0]), software should fill argument in this field. |
Definition at line 22304 of file NUC472_442.h.
| __IO uint32_t ADC_T::CMP[2] |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCMPEN | Compare Enable Control |
| 0 = Compare function Disabled. | ||
| 1 = Compare function Enabled. | ||
| Set this bit to 1 to enable ADC controller to compare CMPDAT (ADC_CMPx[27:16]) with the conversion result of the channel specified by CMPCH (ADC_CMPx[6:3]) when the conversion data of the specified channel is loaded into ADC_DATx register. | ||
| [1] | ADCMPIE | Compare Interrupt Enable Control |
| 0 = Compare function interrupt Disabled. | ||
| 1 = Compare function interrupt Enabled. | ||
| If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT(ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS0[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE (ADC_CMPx[1])is set to 1, a compare interrupt request is generated. | ||
| [2] | CMPCOND | Compare Condition |
| 0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. | ||
| 1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. | ||
| Note: When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set. | ||
| [3:6] | CMPCH | Compare Channel Selection |
| 0000 = Channel 0 conversion result is selected to be compared. | ||
| 0001 = Channel 1 conversion result is selected to be compared. | ||
| 0010 = Channel 2 conversion result is selected to be compared. | ||
| 0011 = Channel 3 conversion result is selected to be compared. | ||
| 0100 = Channel 4 conversion result is selected to be compared. | ||
| 0101 = Channel 5 conversion result is selected to be compared. | ||
| 0110 = Channel 6 conversion result is selected to be compared. | ||
| 0111 = Channel 7 conversion result is selected to be compared. | ||
| 1000 = Channel 8 conversion result is selected to be compared. | ||
| 1001 = Channel 9 conversion result is selected to be compared. | ||
| 1010 = Channel 10 conversion result is selected to be compared. | ||
| 1011 = Channel 11 conversion result is selected to be compared. | ||
| 1100 = band-gap voltage result is selected to be compared. | ||
| 1101 = temperature sensor conversion result is selected to be compared. | ||
| Others = reserved. | ||
| [8:11] | CMPMCNT | Compare Match Count |
| When the specified ADC channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1. | ||
| When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set. | ||
| [16:27] | CMPDAT | Compared Data |
| When DMOF (ADC_CTL[31]) bit is set to 0, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with unsigned format. | ||
| CMPDAT (ADC_CTL[27:16]) should be filled in unsigned format. | ||
| When DMOF (ADC_CTL[31]) bit is set to 1, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with 2'complement format. | ||
| CMPDAT (ADC_CTL[27:16]) should be filled in 2'complement format. |
Definition at line 539 of file NUC472_442.h.
| __IO uint32_t EADC_T::CMP[2] |
Offset: 0xA8 A/D Result Compare Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCMPEN | A/D Result Compare Enable Control |
| 0 = Compare Disabled. | ||
| 1 = Compare Enabled. | ||
| Set this bit to 1 to enable compare CMPDAT (EADC_CMPx[27:16]) with specified SAMPLE conversion result when converted data is loaded into ADDR register. | ||
| [1] | ADCMPIE | A/D Result Compare Interrupt Enable Control |
| 0 = Compare function interrupt Disabled. | ||
| 1 = Compare function interrupt Enabled. | ||
| If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPx[2]) and CMPMCNT (EADC_CMPx[11:8]), ADCMPF (EADC_STATUS1 [7:6]) bit will be asserted, in the meanwhile, if ADCMPIE (EADC_CMPx[1]) is set to 1, a compare interrupt request is generated. | ||
| [2] | CMPCOND | Compare Condition |
| 0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one. | ||
| 1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one. | ||
| Note: When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8]) + 1, the CMPF bit will be set. | ||
| [3:5] | CMPSPL | Compare SAMPLE Selection |
| 000 = SAMPLE00 conversion result EADC_AD0DAT0 is selected to be compared. | ||
| 001 = SAMPLE01 conversion result EADC_AD0DAT1 is selected to be compared. | ||
| 010 = SAMPLE02 conversion result EADC_AD0DAT2 is selected to be compared. | ||
| 011 = SAMPLE03 conversion result EADC_AD0DAT3 is selected to be compared. | ||
| 100 = SAMPLE10 conversion result EADC_AD1DAT0 is selected to be compared. | ||
| 101 = SAMPLE11 conversion result EADC_AD1DAT1 is selected to be compared. | ||
| 110 = SAMPLE12 conversion result EADC_AD1DAT2 is selected to be compared. | ||
| 111 = SAMPLE13 conversion result EADC_AD1DAT3 is selected to be compared. | ||
| [8:11] | CMPMCNT | Compare Match Count |
| When the specified A/D SAMPLE analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPx[2]), the internal match counter will increase 1. | ||
| When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8] + 1, the ADCMPF (EADC_STATUS1 [7:6]) bit will be set. | ||
| [16:27] | CMPDAT | Compared Data |
| The 12 bits data is used to compare with conversion result of specified SAMPLE. | ||
| Software can use it to monitor the external analog input pin voltage transition without imposing a load on software. |
Definition at line 8751 of file NUC472_442.h.
| __IO uint32_t TIMER_T::CMP |
| Bits | Field | Descriptions |
|---|---|---|
| [0:23] | CMPDAT | Timer Compared Value |
| CMPDAT is a 24-bit compared value register. | ||
| When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMER_INTSTS[0] timer interrupt flag) will set to 1. | ||
| Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). | ||
| Note1: Never write 0x0 or 0x1 in CMPDAT field, or the timer will run into unknown state. | ||
| Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field. | ||
| But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest CMPDAT value to be the timer compared value if software writes a new value into CMPDAT field. |
Definition at line 24971 of file NUC472_442.h.
| __IO uint32_t CAP_T::CMPADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CMPADDR | Compare Memory Base Address |
| Word aligns address; ignore the bits [1:0]. |
Definition at line 2016 of file NUC472_442.h.
| __IO uint32_t EPWM_T::CMPDAT[3] |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | CMP | PWM Duty Register |
| Edge aligned: | ||
| Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar. | ||
| Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar. | ||
| Centre aligned: | ||
| Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar. | ||
| Duty = (Duty *2 + 1) * EPWMx_CLK period * pre-scalar. |
Definition at line 14120 of file NUC472_442.h.
| __IO uint32_t PWM_T::CMPDAT[6] |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | CMP | PWM Duty Register |
| CMP determines the PWM duty. | ||
| PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(PERIOD+1)]; where xy, could be 01, 23 or, 45, depends on selected PWM channel. | ||
| For Edge-aligned mode: | ||
| l Duty ratio = (CMP+1)/(PERIOD+1). | ||
| l CMP >= PERIOD: PWM output is always high. | ||
| l CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit. | ||
| l CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit. | ||
| For Center-aligned mode: | ||
| l Duty ratio = [(2 x CMP) + 1]/[2 x (PERIOD+1)]. | ||
| l CMP > PERIOD: PWM output is always high. | ||
| l CMP <= PERIOD: PWM low width = 2 x (PERIOD-CMP) + 1 unit; PWM high width = (2 x CMP) + 1 unit. | ||
| l CMP = 0: PWM low width = 2 x PERIOD + 1 unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: Any write to CMP will take effect in next PWM cycle. |
Definition at line 19208 of file NUC472_442.h.
| __IO uint32_t ECAP_T::CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:23] | VAL | Input Capture Timer/Counter |
| The input Capture Timer/Counter is a 24-bit up-counting counter. | ||
| The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32. |
Definition at line 2436 of file NUC472_442.h.
| __I uint32_t PWM_T::CNT[6] |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | CNT | PWM Data Register |
| User can monitor CNT to know the current value in 16-bit down counter. | ||
| Note: It is recommended that read this register when PWM engine clock is source from system clock, otherwise a transition value of PWM counter may be read. |
Definition at line 19221 of file NUC472_442.h.
| __IO uint32_t QEI_T::CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | VAL | Quadrature Encoder Pulse Counter |
| A 32-bit up/down counter. | ||
| When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[27]) is one or decreased by one if the bit DIRF is zero. | ||
| This register performs an integrator which count value is proportional to the encoder position. | ||
| The pulse counter may be initialized to a predetermined value by one of three events occurs:. | ||
| 1. Software written if QEIEN (QEI_CTR[29]) = 0. | ||
| 2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode. | ||
| 3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTR[27])=1. |
Definition at line 20106 of file NUC472_442.h.
| __I uint32_t TIMER_T::CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:23] | TIMER_CNT | Timer Data Register |
| 1. EXTCNTEN (TIMERX_CTL[24] ) = 0 : TIMER_CNT is 24- bit counter value. | ||
| User can read TIMER_CNT for getting current 24- bit counter value if TIMERX_CTL[24] is set to 0 | ||
| 2. EXTCNTEN (TIMERX_CTL[24] ) = 1 : TIMER_CNT is 24- bit event counter value. | ||
| User can read TIMER_CNT for getting current 24- bit event counter value if TIMERX_CTL[24] is 1 |
Definition at line 25006 of file NUC472_442.h.
| __I uint32_t WWDT_T::CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | CNTDAT | WWDT Counter Value |
| This register reflects the current WWDT counter value and is read only. |
Definition at line 28657 of file NUC472_442.h.
| __IO uint32_t ECAP_T::CNTCMP |
| Bits | Field | Descriptions |
|---|---|---|
| [0:23] | VAL | Input Capture Counter Compare Register |
| If the compare function is enabled (CMPEN = 1), the compare register is loaded with the value that the compare function compares the capture counter (ECAP_CNT) with. | ||
| If the reload control is enabled (RLDEN = 1), an overflow event or capture events will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT. |
Definition at line 2488 of file NUC472_442.h.
| __IO uint32_t QEI_T::CNTCMP |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | VAL | Quadrature Encoder Pulse Counter Compare |
| if the QEI controller is in the compare-counting mode CMPENN (QEI_CTR[28]) =1, when the value of QEI_CNT matches the value of VAL the bit CMPF will be set. | ||
| This register is software writeable. |
Definition at line 20143 of file NUC472_442.h.
| __IO uint32_t PWM_T::CNTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | CNTEN | PWM Counter Enable Control |
| 0 = PWM Counter Stop Running. | ||
| 1 = PWM Counter Start Running. | ||
| Note: Each bit controls the corresponding PWM channel. |
Definition at line 19155 of file NUC472_442.h.
| __IO uint32_t QEI_T::CNTHOLD |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | VAL | Quadrature Encoder Pulse Counter Hold Register |
| When bit HOLDCNT (QEIx_CTR[24]) goes from low to high, the QEI_CNT value is copied into QEI_CNTHOLD register. |
Definition at line 20118 of file NUC472_442.h.
| __IO uint32_t QEI_T::CNTLATCH |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | VAL | Quadrature Encoder Pulse Counter Index Latch |
| When the IDXF (QEI_STATUS[18]) bit is set, the QEI_CNT value is copied into QEI_CNTLATCH register. |
Definition at line 20130 of file NUC472_442.h.
| __IO uint32_t QEI_T::CNTMAX |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | VAL | Quadrature Encoder Preset Maximum Count |
| This register value determined by user stores the maximum value which may be the number of the quadrature encoder pulses in a revolution for the QEI controller compare-counting mode |
Definition at line 20159 of file NUC472_442.h.
| __IO uint32_t CAN_T::CON |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | Init | Init Initialization |
| 0 = Normal Operation. | ||
| 1 = Initialization is started. | ||
| [1] | IE | Module Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2] | SIE | Status Change Interrupt Enable Control |
| 0 = Disabled - No Status Change Interrupt will be generated. | ||
| 1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. | ||
| [3] | EIE | Error Interrupt Enable Control |
| 0 = Disabled - No Error Status Interrupt will be generated. | ||
| 1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt. | ||
| [5] | DAR | Automatic Re-Transmission Disable Control |
| 0 = Automatic Retransmission of disturbed messages enabled. | ||
| 1 = Automatic Retransmission disabled. | ||
| [6] | CCE | Configuration Change Enable Control |
| 0 = No write access to the Bit Timing Register. | ||
| 1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1). | ||
| [7] | Test | Test Mode Enable Control |
| 0 = Normal Operation. | ||
| 1 = Test Mode. |
Definition at line 1156 of file NUC472_442.h.
| __IO uint32_t CAN_IF_T::CREQ |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | MessageNumber | Message Number |
| 0x01-0x20: Valid Message Number, the Message Object in the Message | ||
| RAM is selected for data transfer. | ||
| 0x00: Not a valid Message Number, interpreted as 0x20. | ||
| 0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. | ||
| [15] | Busy | Busy Flag |
| 0 = Read/write action has finished. | ||
| 1 = Writing to the IFn Command Request Register is in progress. | ||
| This bit can only be read by the software. |
Definition at line 868 of file NUC472_442.h.
| __I uint32_t EMAC_T::CRXBSA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CRXBSA | Current Receive Buffer Start Address |
| The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently. | ||
| The CRXBSA is read only and write to this register has no effect. |
Definition at line 13097 of file NUC472_442.h.
| __I uint32_t EMAC_T::CRXDSA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CRXDSA | Current Receive Descriptor Start Address |
| The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently. | ||
| The CRXDSA is read only and write to this register has no effect. |
Definition at line 13084 of file NUC472_442.h.
| __IO uint32_t ACMP_T::CTL[3] |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ACMPEN | Comparator x Enable Control |
| 0 = Comparator x Disabled. | ||
| 1 = Comparator x Enabled. | ||
| Note: The comparator output needs to wait 2 us stable time after ACMPEN is set. | ||
| [1] | ACMPIE | Comparator x Interrupt Enable Control |
| 0 = Comparator x interrupt Disabled. | ||
| 1 = Comparator x interrupt Enabled. | ||
| [2] | HYSEN | Comparator x Hysteresis Enable Control |
| 0 = Comparator x hysteresis Disabled (Default). | ||
| 1 = Comparator x hysteresis Enabled (typical range is 20 mV). | ||
| [3] | ACMPOINV | Comparator x Output Inverse |
| 0 = Comparator x output inverse Disabled. | ||
| 1 = Comparator x output inverse Enabled. | ||
| [4] | NEGSEL | Comparator x Negative Input Selection |
| 0 = The source of comparator x negative input is from ACMP0_N pin. | ||
| 1 = The internal comparator reference voltage (Band-gap voltage or CRV) is selected as the source of comparator x negative input. | ||
| [5:7] | POSSEL | Comparator x Positive Input Selection |
| 000= Input from ACMPx_P0. | ||
| 001= Input from ACMPx_P1. | ||
| 010= Input from ACMPx_P2. | ||
| 011= Input from ACMPx_P3. | ||
| 100= Input from OPA0x. (Reserved for ACMP2) | ||
| The other options are reserved. |
Definition at line 257 of file NUC472_442.h.
| __IO uint32_t ADC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCEN | ADC Enable Control |
| 0 = ADC analog circuit Disabled. | ||
| 1 = ADC analog circuit Enabled. | ||
| Before disabling ADC clock, this bit should be cleared to 0 by software. | ||
| [1] | ADCIEN | ADC Interrupt Enable Control |
| 0 = ADC interrupt function Disabled. | ||
| 1 = ADC interrupt function Enabled. | ||
| A/D conversion end interrupt request is generated if ADCIEN (ADC_CTL[1]) bit is set to 1. | ||
| [2:3] | OPMODE | ADC Operation Mode |
| 00 = Single conversion. | ||
| 01 = Reserved. | ||
| 10 = Single-cycle scan. | ||
| 11 = Continuous scan. | ||
| When changing the operation mode, software should disable SWTRG (ADC_CTL[11]) bit firstly. | ||
| [4:5] | HWTRGSEL | External Hardware Trigger Source |
| 00 = A/D conversion is started by external pin (STADC). | ||
| 01 = Reserved. | ||
| 10 = Reserved. | ||
| 11 = PWM0 or PWM1 trigger condition is matched. | ||
| Software should disable HWTRGCOND (ADC_CTL[8]) and SWTRG (ADC_CTL[11]) before changing HWTRGSEL (ADC_CTL[5:4]). | ||
| In hardware trigger mode, the SWTRG (ADC_CTL[11]) bit is set by hardware trigger source. | ||
| [6:7] | HWTRGCOND | External Pin Trigger Conditions |
| These two bits decide external pin (STADC) trigger event. | ||
| The signal must be kept at stable state at least 8 system clocks for level trigger and 4 system clocks at high and low state for edge trigger. | ||
| 00 = Low level. | ||
| 01 = High level. | ||
| 10 = Falling edge. | ||
| 11 = Rising edge. | ||
| [8] | HWTRGEN | External Hardware Trigger Enable Control |
| Enable or disable hardware triggering of A/D conversion. | ||
| The hardware trigger source include external pin (STADC) or PWM trigger which is controlled by HWTRGSEL (ADC_CTL[5:4]) register. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| ADC hardware trigger function is only supported in single-cycle scan mode. | ||
| [9] | PDMAEN | PDMA Transfer Enable Control |
| 0 = PDMA data transfer Disabled. | ||
| 1 = PDMA data transfer in ADC_DATx Enabled. | ||
| When A/D conversion is completed, the converted data is loaded into ADC_DATx, software can enable this bit to generate a PDMA data transfer request. | ||
| When PDMAEN (ADC_CTL[9]) is set to 1, software must set ADCIEN (ADC_CTL[1]) bit to 0 to disable interrupt. | ||
| [10] | DIFFEN | Differential Input Mode Enable Control |
| 0 = Single-end analog input mode. | ||
| 1 = Differential analog input mode. | ||
| The A/D analog input ADC0_CH0/ADC0_CH1 consists of a differential pair. | ||
| So as ADC0_CH2/ADC0_CH3, ADC0_CH4/ADC0_CH5, ADC0_CH6/ADC0_CH7, ADC0_CH8/ADC0_CH9 and ADC0_CH10/ADC0_CH11. | ||
| The even channel defines as plus analog input voltage (Vplus) and the odd channel defines as minus analog input voltage (Vminus). | ||
| Differential input voltage (Vdiff) = Vplus - Vminus, where Vplus | ||
| is the analog input; Vminus is the inverted analog input. | ||
| In differential input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER (ADC_CHEN[11:0]). | ||
| The conversion result will be placed to the corresponding data register of the enabled channel. | ||
| [11] | SWTRG | A/D Conversion Start |
| 0 = Conversion stopped and A/D converter enter idle state. | ||
| 1 = Conversion start. | ||
| The SWTRG (ADC_CTL[11]) bit can be set to 1 from two sources: software and hardware trigger. | ||
| The SWTRG (ADC_CTL[11]) bit will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. | ||
| In continuous scan mode, A/D conversion is continuously performed until software write 0 to this bit or chip reset. | ||
| [16:23] | PWMTRGDLY | PWM Trigger Delay Time |
| Setting this field will delay ADC start conversion time after PWM trigger comes. | ||
| PWM trigger delay time is 4 * system clock * PWMTRGDLY (ADC_CTL[23:16]) | ||
| [31] | DMOF | ADC Differential Input Mode Output Format |
| 0 = A/D conversion result will be filled in RESULT (ADC_DATx[15:0]) registers with unsigned format. | ||
| 1 = A/D conversion result will be filled in RESULT (ADC_DATx[15:0]) registers with 2'complement format. |
Definition at line 470 of file NUC472_442.h.
| __IO uint32_t CAP_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CAPEN | Image Capture Interface Enable |
| 0 = Image Capture Interface Disabled. | ||
| 1 = Image Capture Interface Enabled. | ||
| [3] | ADDRSW | Packet Buffer Address Switch |
| 0 = Packet buffer address switch Disabled. | ||
| 1 = Packet buffer address switch Enabled. | ||
| [5] | PLNEN | Planar Output Enable |
| 0 = Planar output Disabled. | ||
| 1 = Planar output Enabled. | ||
| [6] | PKTEN | Packet Output Enable |
| 0 = Packet output Disabled. | ||
| 1 = Packet output Enabled. | ||
| [16] | SHUTTER | Image Capture Interface Automatically Disable The Capture Interface After A Frame Had Been Captured |
| 0 = Shutter Disabled. | ||
| 1 = Shutter Enabled. | ||
| [20] | UPDATE | Update Register At New Frame |
| 0 = Update register at new frame Disabled. | ||
| 1 = Update register at new frame Enabled (Auto clear to 0 when register updated). | ||
| [24] | VPRST | Capture Interface Reset |
| 0 = Capture interface reset Disabled. | ||
| 1 = Capture interface reset Enabled. |
Definition at line 1714 of file NUC472_442.h.
| __IO uint32_t CRC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CRCEN | CRC Channel Enable Control |
| 0 = CRC function Disabled. | ||
| 1 = CRC function Enabled. | ||
| [1] | CRCRST | CRC Engine Reset |
| 0 = No effect. | ||
| 1 = Reset the internal CRC state machine and internal buffer. | ||
| The contents of control register will not be cleared. | ||
| This bit will automatically be cleared after few clock cycles. | ||
| Note: Setting this bit will reload the initial seed value. | ||
| [24] | DATREV | Write Data Order Reverse |
| 0 = No bit order reversed for CRC write data in. | ||
| 1 = Bit order reversed for CRC write data in (per byte). | ||
| Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB | ||
| [25] | CHKSREV | Checksum Reverse |
| 0 = No bit order reverse for CRC checksum. | ||
| 1 = Bit order reverse for CRC checksum. | ||
| Note: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB. | ||
| [26] | DATFMT | Write Data Complement |
| 0 = No bit order reversed for CRC write data in. | ||
| 1 = 1's complement for CRC write data in. | ||
| [27] | CHKSFMT | Checksum Complement |
| 0 = No bit order reverse for CRC checksum. | ||
| 1 = 1's complement for CRC checksum. | ||
| [28:29] | DATLEN | CPU Write Data Length |
| This field indicates the write data length. | ||
| 00 = Data length is 8-bit mode. | ||
| 01 = Data length is 16-bit mode. | ||
| 1x = Data length is 32-bit mode. | ||
| Note: When the data length is 8-bit mode, the valid data is DATA [7:0]; if the data length is 16-bit mode, the valid data is DATA [15:0]. | ||
| [30:31] | CRCMODE | CRC Polynomial Mode Selection |
| 00 = CRC-CCITT Polynomial mode. | ||
| 01 = CRC-8 Polynomial mode. | ||
| 10 = CRC-16 Polynomial mode. | ||
| 11 = CRC-32 Polynomial mode. |
Definition at line 4034 of file NUC472_442.h.
| __IO uint32_t EADC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCEN | A/D Converter Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Before starting A/D conversion function, this bit should be set to 1. | ||
| Clear it to 0 to disable A/D converter analog circuit power consumption. | ||
| [1] | ADCRST | ADC0, ADC1 A/D Converter Control Circuits Reset |
| 0 = No effect. | ||
| 1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. | ||
| The ADCRST (EADC_CTL [1]) bit remains 1 during ADC reset, when ADC reset end, the ADCRST (EADC_CTL [1]) bit is automatically cleared to 0. | ||
| [2] | ADCIEN0 | Specific SAMPLE A/D ADINT0 Interrupt Enable Control |
| 0 = Specific SAMPLE A/D ADINT0 interrupt function Disabled. | ||
| 1 = Specific SAMPLE A/D ADINT0 interrupt function Enabled. | ||
| The A/D converter generates a conversion end ADIF0 (EADC_STATUS1 [0]) flag upon the end of specific SAMPLE A/D conversion. | ||
| If ADCIEN0 (EADC_CTL [2]) bit is set then conversion end interrupt request ADINT0 is generated. | ||
| [3] | ADCIEN1 | Specific SAMPLE A/D ADINT1 Interrupt Enable Control |
| 0 = Specific SAMPLE A/D ADINT1 interrupt function Disabled. | ||
| 1 = Specific SAMPLE A/D ADINT1 interrupt function Enabled. | ||
| The A/D converter generates a conversion end ADIF0 (EADC_STATUS1 [1]) flag upon the end of specific SAMPLE A/D conversion. | ||
| If ADCIEN1 EADC_CTL [3]) bit is set then conversion end interrupt request ADINT1 is generated. | ||
| [4] | ADCIEN2 | Specific SAMPLE A/D ADINT2 Interrupt Enable Control |
| 0 = Specific SAMPLE A/D ADINT2 interrupt function Disabled. | ||
| 1 = Specific SAMPLE A/D ADINT2 interrupt function Enabled. | ||
| The A/D converter generates a conversion end ADIF2 (EADC_STATUS1 [2]) flag upon the end of specific SAMPLE A/D conversion. | ||
| If ADCIEN2 (EADC_CTL [4]) bit is set then conversion end interrupt request ADINT2 is generated. | ||
| [5] | ADCIEN3 | Specific SAMPLE A/D ADINT3 Interrupt Enable Control |
| 0 = Specific SAMPLE A/D ADINT3 interrupt function Disabled. | ||
| 1 = Specific SAMPLE A/D ADINT3 interrupt function Enabled. | ||
| The A/D converter generates a conversion end ADIF3 (EADC_STATUS1 [3]) flag upon the end of specific SAMPLE A/D conversion. | ||
| If ADCIEN3 (EADC_CTL [5]) bit is set then conversion end interrupt request ADINT3 is generated. |
Definition at line 7793 of file NUC472_442.h.
| __IO uint32_t EBI_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [8:10] | MCLKDIV | External Output Clock Divider |
| The frequency of EBI output clock is controlled by MCLKDIV as below: | ||
| 000 = HCLK/1. | ||
| 001 = HCLK/2. | ||
| 010 = HCLK/4. | ||
| 011 = HCLK/8. | ||
| 100 = HCLK/16. | ||
| 101 = HCLK/32. | ||
| 11x = Default. | ||
| Note: Default value of output clock is HCLK/1 | ||
| [24:27] | CRYPTOEN | Encrypt/Decrypt Function Enable Control (For 4 Individual Chip Select) |
| 0 = Encrypt/Decrypt function Disabled. | ||
| 1 = Encrypt/Decrypt function Enabled. | ||
| [28:31] | CSPOLINV | Reverse Chip Select |
| The original design Chip Select is active low nCS. | ||
| "Chip Select Active High" can be specified by customers-Bit[28+n] is for nCS[n], where n=0~3. | ||
| 0 = nCS (chip select active low). | ||
| 1 = CS (chip select active high). |
Definition at line 11598 of file NUC472_442.h.
| __IO uint32_t EMAC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXON | Frame Reception ON |
| The RXON controls the normal packet reception of EMAC. | ||
| If the RXON is set to high, the EMAC starts the packet reception process, including the RX descriptor fetching, packet reception and RX descriptor modification. | ||
| It is necessary to finish EMAC initial sequence before enable RXON. | ||
| Otherwise, the EMAC operation is undefined. | ||
| If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet reception process after the current packet reception finished. | ||
| 0 = Packet reception process stopped. | ||
| 1 = Packet reception process started. | ||
| [1] | ALP | Accept Long Packet |
| The ALP controls the long packet, which packet length is greater than 1518 bytes, reception. | ||
| If the ALP is set to high, the EMAC will accept the long packet. | ||
| Otherwise, the long packet will be dropped. | ||
| 0 = Ethernet MAC controller dropped the long packet. | ||
| 1 = Ethernet MAC controller received the long packet. | ||
| [2] | ARP | Accept Runt Packet |
| The ARP controls the runt packet, which length is less than 64 bytes, reception. | ||
| If the ARP is set to high, the EMAC will accept the runt packet. | ||
| Otherwise, the runt packet will be dropped. | ||
| 0 = Ethernet MAC controller dropped the runt packet. | ||
| 1 = Ethernet MAC controller received the runt packet. | ||
| [3] | ACP | Accept Control Packet |
| The ACP controls the control frame reception. | ||
| If the ACP is set to high, the EMAC will accept the control frame. | ||
| Otherwise, the control frame will be dropped. | ||
| It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode. | ||
| 0 = Ethernet MAC controller dropped the control frame. | ||
| 1 = Ethernet MAC controller received the control frame. | ||
| [4] | AEP | Accept CRC Error Packet |
| The AEP controls the EMAC accepts or drops the CRC error packet. | ||
| If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet. | ||
| 0 = Ethernet MAC controller dropped the CRC error packet. | ||
| 1 = Ethernet MAC controller received the CRC error packet. | ||
| [5] | STRIPCRC | Strip CRC Checksum |
| The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum. | ||
| If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet. | ||
| 0 = The 4 bytes CRC checksum is included in packet length calculation. | ||
| 1 = The 4 bytes CRC checksum is excluded in packet length calculation. | ||
| [6] | WOLEN | Wake On LAN Enable |
| The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet is Magic Packet and wakeup system from Power-down mode. | ||
| If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller would generate a wakeup event to wake system up from Power-down mode. | ||
| 0 = Wake-up by Magic Packet function Disabled. | ||
| 1 = Wake-up by Magic Packet function Enabled. | ||
| [8] | TXON | Frame Transmission ON |
| The TXON controls the normal packet transmission of EMAC. | ||
| If the TXON is set to high, the EMAC starts the packet transmission process, including the TX descriptor fetching, packet transmission and TX descriptor modification. | ||
| It is must to finish EMAC initial sequence before enable TXON. | ||
| Otherwise, the EMAC operation is undefined. | ||
| If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet transmission process after the current packet transmission finished. | ||
| 0 = Packet transmission process stopped. | ||
| 1 = Packet transmission process started. | ||
| [9] | NODEF | No Deferral |
| The NODEF controls the enable of deferral exceed counter. | ||
| If NODEF is set to high, the deferral exceed counter is disabled. | ||
| The NODEF is only useful while EMAC is operating on half duplex mode. | ||
| 0 = The deferral exceed counter Enabled. | ||
| 1 = The deferral exceed counter Disabled. | ||
| [16] | SDPZ | Send PAUSE Frame |
| The SDPZ controls the PAUSE control frame transmission. | ||
| If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured first and the corresponding CAM enable bit of CAMEN register also must be set. | ||
| Then, set SDPZ to 1 enables the PAUSE control frame transmission. | ||
| The SDPZ is a self-clear bit. | ||
| This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically. | ||
| It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode. | ||
| 0 = PAUSE control frame transmission completed. | ||
| 1 = PAUSE control frame transmission Enabled. | ||
| [17] | SQECHKEN | SQE Checking Enable |
| The SQECHKEN controls the enable of SQE checking. | ||
| The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode. | ||
| In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100M bps or full duplex mode. | ||
| 0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode. | ||
| 1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode. | ||
| [18] | FUDUP | Full Duplex Mode Selection |
| The FUDUP controls that if EMAC is operating on full or half duplex mode. | ||
| 0 = EMAC operates in half duplex mode. | ||
| 1 = EMAC operates in full duplex mode. | ||
| [19] | RMIIRXCTL | RMII RX Control |
| The RMIIRXCTL control the receive data sample in RMII mode. | ||
| It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high. | ||
| 0 = RMII RX control disabled. | ||
| 1 = RMII RX control enabled. | ||
| [20] | OPMODE | Operation Mode Selection |
| The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode. | ||
| The RST (EMAC_CTL[24]) would not affect OPMODE value. | ||
| 0 = EMAC operates in 10Mbps mode. | ||
| 1 = EMAC operates in 100Mbps mode. | ||
| [22] | RMIIEN | RMII Mode Enable |
| This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII interface or RMII interface. | ||
| The RST (EMAC_CTL[24]) would not affect RMIIEN value. | ||
| 0 = Ethernet MAC controller MII mode Enabled. | ||
| 1 = Ethernet MAC controller RMII mode Enabled. | ||
| [24] | RST | Software Reset |
| The RST implements a reset function to make the EMAC return default state. | ||
| The RST is a self-clear bit. | ||
| This means after the software reset finished, the RST will be cleared automatically. | ||
| Enable RST can also reset all control and status registers, exclusive of the control bits RMIIEN (EMAC_CTL[22]), LOOPBK (EMAC_CTL[21]) and OPMODE (EMAC_CTL[20]). | ||
| The EMAC re-initial is necessary after the software reset completed. | ||
| 0 = Software reset completed. | ||
| 1 = Software reset Enabled. |
Definition at line 12481 of file NUC472_442.h.
| __IO uint32_t EPWM_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | MODE | PWM Mode Selection |
| 00 = Independent mode. | ||
| 01 = Pair/Complementary mode. | ||
| 10 = Synchronized mode. | ||
| 11 = Reserved. | ||
| [2:3] | CLKDIV | PWM Clock Pre-Divider Selection |
| 00 = PWM clock = EPWMx_CLK. | ||
| 01 = PWM clock = EPWMx_CLK/2. | ||
| 10 = PWM clock = EPWMx_CLK/4. | ||
| 11 = PWM clock = EPWMx_CLK/16. | ||
| [4] | PWMIEN | PWM Interrupt Enable Control |
| 0 = Disabling flag PIF to trigger PWM interrupt. | ||
| 1 = Enabling flag PIF can trigger PWM interrupt. | ||
| [5] | BRKIEN | Brake0 And Brak1 Interrupt Enable Control |
| 0 = Disabling flags BFK0 and BFK1 to trigger PWM interrupt. | ||
| 1 = Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt. | ||
| [6] | LOAD | Re-Load PWM Period Registers (EPWM_PERIOD) And PWM Duty Registers (PWM0~3) Control |
| 0 = No action if written with 0. | ||
| The value of PWM period register (EPWM_PERIOD) and PWM duty registers (PWMn_CH0~PWMn_CH3) are not loaded to PWM counter and Comparator registers. | ||
| 1 = Hardware will update the value of PWM period register (EPWM_PERIOD) and PWM duty registers (PWMn_CH0~PWMn_CH3) to PWM Counter and Comparator register at the time of PWM Counter matches PERIOD in edge and central aligned modes or at the time of PWM Counter down counts with underflow in central aligned mode. | ||
| Note1: n=0-1 for PWM unit0-1. | ||
| Note2: This bit is software write, hardware clear and always read zero. | ||
| [7] | CNTEN | Start CNTEN Control |
| 0 = The PWM stops running. | ||
| 1 = The PWM counter starts running. | ||
| [8] | INTTYPE | PWM Interrupt Type Selection |
| 0 = PIF will be set if PWM counter underflow. | ||
| 1 = PIF will be set if PWM counter matches EPWM_PERIOD register. | ||
| Note: This bit is effective when PWM in central align mode only. | ||
| [9] | PINV | Inverse PWM Comparator Output |
| When PINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PINV is set to high. | ||
| 0 = Not inverse PWM comparator output. | ||
| 1 = Inverse PWM comparator output. | ||
| [11] | CNTCLR | Clear PWM Counter Control |
| 1 = Clear 16-bit PWM counter to 000H. | ||
| Note: It is automatically cleared by hardware. | ||
| [12] | CNTTYPE | PWM Aligned Type Selection |
| 0 = Edge-aligned type. | ||
| 1 = Centre-aligned type. | ||
| [13] | GROUPEN | Group Bit |
| 0 = The signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 are independent. | ||
| 1 = Unify the signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 in the same phase which is controlled by EPWM_CMPDAT0. | ||
| [14] | BRKP0INV | Inverse BKP0 State |
| 0 = The state of pin BKPx0 is passed to the negative edge detector. | ||
| 1 = The inversed state of pin BKPx0 is passed to the negative edge detector. | ||
| [15] | BRKP1INV | Inverse BKP1 State |
| 0 = The state of pin BKPx1 is passed to the negative edge detector. | ||
| 1 = The inversed state of pin BKPx1 is passed to the negative edge detector. | ||
| [16] | BRKP0EN | BKPx0 Pin Trigger Brake Function0 Enable Control |
| 0 = PWMx Brake Function 0 Disabled. | ||
| 1 = PWMx Brake Function 0 Enabled. | ||
| Note: x=0~1 for PWM unit0~1. | ||
| [17] | BRKP1EN | BKPx1 Pin Trigger Brake Function Enable Control |
| 0 = PWMx Brake Function 1 Disabled. | ||
| 1 = PWMx Brake Function 1 Enabled. | ||
| Note: x=0~1 for PWM unit0~1. | ||
| [18:19] | BRK1SEL | Brake Function 1 Source Selection |
| 00 = From external pin BKPx1 (x=0~1 for unit0~1). | ||
| 01 = From analog comparator 0 output (CPO0). | ||
| 10 = From analog comparator 1 output (CPO1). | ||
| 11 = From analog comparator 2 output (CPO2). | ||
| [20:21] | BRK0NFSEL | Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection |
| 00 = Filter clock = HCLK. | ||
| 01 = Filter clock = HCLK/2. | ||
| 10 = Filter clock = HCLK/4. | ||
| 11 = Filter clock = HCLK/16. | ||
| [22:23] | BRK1NFSEL | Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection |
| 00 = Filter clock = HCLK. | ||
| 01 =Filter clock = HCLK/2. | ||
| 10 = Filter clock = HCLK/4. | ||
| 11 = Filter clock = HCLK/16. | ||
| [24] | CPO0BKEN | CPO0 Digital Output As Brake0 Source Enable Control |
| 1 = CPO0 as one brake source in Brake 0 Enabled. | ||
| 0 = CPO0 as one brake source in Brake 0 Disabled. | ||
| [25] | CPO1BKEN | CPO1 Digital Output As Brake 0 Source Enable Control |
| 0 = CPO1 as one brake source in Brake 0 Disabled. | ||
| 1 = CPO1 as one brake source in Brake 0 Enabled. | ||
| [26] | CPO2BKEN | CPO2 Digital Output As Brake 0 Source Enable Control |
| 0 = CPO2 as one brake source in Brake 0 Disabled. | ||
| 1 = CPO2 as one brake source in Brake 0 Enabled. | ||
| [27] | LVDBKEN | Low-Level Detection Trigger PWM Brake Function 1 Enable Control |
| 0 = Brake Function 1 triggered by Low-level detection Disabled. | ||
| 1 = Brake Function 1 triggered by Low-level detection Enabled. | ||
| [28] | BRK0NFDIS | PWM Brake 0 Noise Filter Disable Control |
| 0 = Noise filter of PWM Brake 0 Enabled. | ||
| 1 = Noise filter of PWM Brake 0 Disabled. | ||
| [29] | BRK1NFDIS | PWM Brake 1 Noise Filter Disable Control |
| 0 = Noise filter of PWM Brake 1 Enabled. | ||
| 1 = Noise filter of PWM Brake 1 Disabled. | ||
| [31] | CTRLD | Center Reload Mode Enable Control |
| 0 = EPWM reload duty register at the period point of PWM counter. | ||
| 1 = EPWM reload duty register at the center point of PWM counter. | ||
| This bit only work when EPWM operation at center aligned mode. |
Definition at line 14036 of file NUC472_442.h.
| __IO uint32_t I2C_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [2] | AA | Assert Acknowledge Control |
| When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter. | ||
| When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. | ||
| [3] | SI | I2C Interrupt Flag |
| When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. | ||
| SI must be cleared by software. | ||
| Clear SI by writing 1 to this bit. | ||
| [4] | STO | I2C STOP Control |
| In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. | ||
| In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode. | ||
| This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. | ||
| [5] | STA | I2C START Control |
| Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. | ||
| [6] | I2CEN | I2C Controller Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Set to enable I2C serial function controller. | ||
| When ENS1=1 the I2C serial function enables. | ||
| The multi-function pin function of SDA and SCL must set to I2C function first. | ||
| [7] | INTEN | I2C Interrupt Enable Control |
| 0 = I2C interrupt Disabled. | ||
| 1 = I2C interrupt Enabled. |
Definition at line 16853 of file NUC472_442.h.
| __IO uint32_t I2S_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | I2SEN | I2S Controller Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | TXEN | Transmit Enable Control |
| 0 = Data transmission Disabled. | ||
| 1 = Data transmission Enabled. | ||
| [2] | RXEN | Receive Enable Control |
| 0 = Data receiving Disabled. | ||
| 1 = Data receiving Enabled. | ||
| [3] | MUTE | Transmit Mute Enable Control |
| 0 = Transmit data is shifted from buffer. | ||
| 1 = Transmit zero data. | ||
| [4:5] | WDWIDTH | Word Width |
| 00 = data is 8-bit. | ||
| 01 = data is 16-bit. | ||
| 10 = data is 24-bit. | ||
| 11 = data is 32-bit. | ||
| [6] | MONO | Monaural Data Control |
| 0 = Data is stereo format. | ||
| 1 = Data is monaural format. | ||
| Note: when chip records data, only right channel data will be saved if monaural format is select. | ||
| [7] | FORMAT | Data Format Selection |
| If PCM=0, | ||
| 0 = I2S data format. | ||
| 1 = MSB justified data format. | ||
| If PCM=1, | ||
| 0 = PCM mode A. | ||
| 1 = PCM mode B. | ||
| [8] | SLAVE | Slave Mode Enable Control |
| 0 = Master mode. | ||
| 1 = Slave mode. | ||
| Note: I2S can operate as master or slave. | ||
| For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro(TM) | ||
| NUC442/NUC472 series to Audio CODEC chip. | ||
| In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. | ||
| [9:11] | TXTH | Transmit FIFO Threshold Level |
| 000 = 0 word data in transmit FIFO. | ||
| 001 = 1 word data in transmit FIFO. | ||
| 010 = 2 words data in transmit FIFO. | ||
| 011 = 3 words data in transmit FIFO. | ||
| 100 = 4 words data in transmit FIFO. | ||
| 101 = 5 words data in transmit FIFO. | ||
| 110 = 6 words data in transmit FIFO. | ||
| 111 = 7 words data in transmit FIFO. | ||
| Note: If remain data word(s) in transmit FIFO is the same or less than threshold level then TXTHF flag is set. | ||
| [12:14] | RXTH | Receive FIFO Threshold Level |
| 000 = 1 word data in receive FIFO. | ||
| 001 = 2 word data in receive FIFO. | ||
| 010 = 3 word data in receive FIFO. | ||
| 011 = 4 word data in receive FIFO. | ||
| 100 = 5 word data in receive FIFO. | ||
| 101 = 6 word data in receive FIFO. | ||
| 110 = 7 word data in receive FIFO. | ||
| 111 = 8 word data in receive FIFO. | ||
| Note: When received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set. | ||
| [15] | MCLKEN | Master Clock Enable Control |
| 0 = Master clock Disabled. | ||
| 1 = Master clock Enabled. | ||
| Note: If the external crystal clock in NuMicro(TM) NUC442/NUC472 series is frequency 2*N*256fs, software can program MCLK_DIV(I2S_CLK[5:0]) to get 256fs clock to audio codec chip. | ||
| [16] | RZCEN | Right Channel Zero-Cross Detection Enable Control |
| 0 = Right channel zero-cross detect Disabled. | ||
| 1 = Right channel zero-cross detect Enabled. | ||
| Note1: If this bit is set to 1, when right channel data sign bit change or next shift data bits are all zero then RZCF(I2S_STATUS[22]) flag is set to 1. | ||
| Note2: If RZCF Flag is set to 1, the right channel will be mute. | ||
| [17] | LZCEN | Left Channel Zero-Cross Detect Enable Control |
| 0 = Left channel zero-cross detect Disabled. | ||
| 1 = Left channel zero-cross detect Enabled. | ||
| Note1: If this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF(I2S_STATUS[23]) flag is set to 1. | ||
| Note2: If LZCF Flag is set to 1, the left channel will be mute. | ||
| [18] | TXCLR | Clear Transmit FIFO |
| 0 = No Effect. | ||
| 1 = Clear TX FIFO. | ||
| Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT(I2S_STATUS[31:28]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. | ||
| Note2: This bit is clear by hardware automatically, read it return zero. | ||
| [19] | RXCLR | Clear Receive FIFO |
| 0 = No Effect. | ||
| 1 = Clear RX FIFO. | ||
| Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS[27:24]) returns 0 and receive FIFO becomes empty. | ||
| Note2: This bit is cleared by hardware automatically, read it return zero. | ||
| [20] | TXPDMAEN | Transmit DMA Enable Control |
| 0 = TX DMA Disabled. | ||
| 1 = TX DMA Enabled. | ||
| Note: When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full. | ||
| [21] | RXPDMAEN | Receive DMA Enable Control |
| 0 = RX DMA Disabled. | ||
| 1 = RX DMA Enabled. | ||
| Note: When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty. | ||
| [23] | RXLCH | Receive Left Channel Enable Control |
| 0 = Receives right channel data when monaural format is selected. | ||
| 1 = Receives left channel data when monaural format is selected. | ||
| Note: When monaural format is selected (MONO = 1), I2S will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. | ||
| [24] | PCMEN | PCM Interface Enable Control |
| 0 = I2S Interface. | ||
| 1 = PCM Interface. |
Definition at line 17280 of file NUC472_442.h.
| __IO uint32_t OPA_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | OPEN0 | OP Amplifier 0 Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: OP Amplifier 0 output needs wait stable 20us[MS1] after OPEN0 is first set. | ||
| [MS1]alpha test | ||
| [1] | OPEN1 | OP Amplifier 1 Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: OP Amplifier 1 output needs wait stable 20us[MS1] after OPEN1 is first set. | ||
| [MS1]alpha test | ||
| [4] | OPSMTEN0 | OP Amplifier 0 Schmitt Trigger Non-Inverting Buffer Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [5] | OPSMTEN1 | OP Amplifier 1 Schmitt Trigger Non-Inverting Buffer Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [8] | OPAIE0 | OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Control |
| 0 = OP Amplifier 0 digital output interrupt function Disabled. | ||
| 1 = OP Amplifier 0 digital output interrupt function Enabled. | ||
| The OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPAIE0 is set to 1, a comparator interrupt request is generated. | ||
| [9] | OPAIE1 | OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Control |
| 0 = OP Amplifier 1 digital output interrupt function Disabled. | ||
| 1 = OP Amplifier 1 digital output interrupt function Enabled. | ||
| OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPAIE1 is set to 1, a comparator interrupt request is generated. |
Definition at line 17675 of file NUC472_442.h.
| __IO uint32_t OTG_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | VBUSDROP | Drop The VUSB Bus |
| If user application running on this OTG A-device wants to conserve power consumption, set this bit to high When set this bit to TRUE, BUSREQ shall be cleared as well. | ||
| 0 = Did Not drop the VBUS and keep going on USB data transfers. | ||
| 1 = Drop the VBUS to conserve power consumption. | ||
| [1] | BUSREQ | OTG A-Device Bus Request |
| If user application of an OTG A-device wants to do data transfers via USB bus, set this bit to high Otherwise if user application won't use the bus any more, set this bit to low. | ||
| This bit will be automatically cleared if VBUSDROP bit is set to TRUE. | ||
| [2] | HNPREQEN | OTG B-Device HNP Enable/Request |
| Set this bit to TRUE after the OTG A-device successfully sends a SetFeature(b_hnp_enable) command to the OTG B-device This bit will be cleared automatically when a bus reset or SESS_VLD goes from TRUE to FALSE. | ||
| [4] | OTGEN | OTG Function Enable Control |
| If USB is configured as OTG device, this bit must set high. | ||
| 0= OTG function Disabled. | ||
| 1 = OTG function Enabled. | ||
| [7] | PDEVCKON | Force OTG PHY Output Clock To USB Device |
| If software configures OTG controller as OTG device and OTG device as A-device, OTG controller will output OTG PHY clock (30 MHz) to USB device only when OTG device as A-peripheral. | ||
| If software needs to configure USB device before role change (from A-Host to A-Peripheral), software can set this bit high to output OTG PHY clock to USB device. | ||
| 0= USB device clock is available only when OTG device as a peripheral. | ||
| 1 = Force output OTG PHY clock to USB device. | ||
| [8] | WKEN | OTG Wake-Up Enable Control |
| 0= OTG ID pin status change wake-up Disabled. | ||
| 1 = OTG ID pin status change wake-up Enabled. |
Definition at line 17778 of file NUC472_442.h.
| __IO uint32_t DSCT_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | OPMODE | PDMA Operation Mode Selection |
| 00 = Stop Mode. | ||
| Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to stop mode automatically. | ||
| 01 = Basic Mode. | ||
| The descriptor table only has one task. | ||
| When this task is finished, the PDMA_INTSTS[x] will be asserted. | ||
| 10 = Scatter-Gather Mode. | ||
| When operating in this mode, user must give the next descriptor table address in EMBTA_NTAAR register; PDMA will ignore this task, and then load the next task to execute. | ||
| Note: Before filling transfer task in the descriptor table, user must check if the descriptor table is complete. | ||
| [2] | TXTYPE | Request Type |
| 0 = Burst request type. | ||
| 1 = Single request type. | ||
| [4:6] | BURSIZE | Burst Size |
| This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. | ||
| But if in Single Request Type, this field is not useful and only 1 transfer item been transmitted for each transfer. | ||
| 000 = 128 transfers. | ||
| 001 = 64 transfers. | ||
| 010 = 32 transfers. | ||
| 011 = 16 transfers. | ||
| 100 = 8 transfers. | ||
| 101 = 4 transfers. | ||
| 110 = 2 transfers. | ||
| 111 = 1 transfers. | ||
| [7] | TBINTDIS | Table Interrupt Disable Control |
| This field can be used to decide whether to enable table interrupt or not. | ||
| When with transfer done flag, this bit is only used for scatter-gather mode. | ||
| If the TBINTDIS bit is enabled when PDMA finishes this task, there will no any interrupt generated. | ||
| However, with the table empty flag, this bit is also useful. | ||
| If it is set to '1', the TEMPTYF will not be set when this situation has happened. | ||
| 0 = Table interrupt Enabled. | ||
| 1 = Table interrupt Disabled. | ||
| [8:9] | SAINC | Source Address Increment |
| This field is used to set the source address increment size | ||
| 11 = No Increment (Fixed Address.). | ||
| Other = Increment and size is depended on TXWIDTH selection. | ||
| [10:11] | DAINC | Destination Address Increment |
| This field is used to set the destination address increment size | ||
| 11 = No Increment (Fixed Address.). | ||
| Other = Increment and size is depended on TXWIDTH selection. | ||
| [12:13] | TXWIDTH | Transfer Width Selection |
| This field is used for transfer width. | ||
| 00 = 8 bits for every transfer item. | ||
| 01 = 16 bits for every transfer item. | ||
| 10 = 32 bits for every transfer item. | ||
| 11 = Reserved. | ||
| Note: The PDMA transfer source address (EMBTA_ENDSAR) and PDMA transfer destination address (EMBTA_ENDDAR) should be alignment under the TXWIDTH selection | ||
| [16:29] | TXCNT | Transfer Count |
| The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. | ||
| Note: When PDMA finish each transfer item, this field will be decrease imminently |
Definition at line 18180 of file NUC472_442.h.
| __IO uint32_t PS2_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PS2EN | PS/2 Device Enable Control |
| Enable PS/2 device controller. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | TXIEN | Transmit Interrupt Enable Control |
| 0 = Data transmit complete interrupt Disabled. | ||
| 1 = Data transmit complete interrupt Enabled. | ||
| [2] | RXIEN | Receive Interrupt Enable Control |
| 0 = Data receive complete interrupt Disabled. | ||
| 1 = Data receive complete interrupt Enabled. | ||
| [3:6] | TXFDEPTH | Transmit Data FIFO Depth |
| There is 16-byte buffer for data transmit. | ||
| Software can define the FIFO depth from 1 to 16 bytes depending on the application. | ||
| 0 = 1 byte. | ||
| 1 = 2 bytes. | ||
| ... | ||
| 14 = 15 bytes. | ||
| 15 = 16 bytes. | ||
| [7] | ACK | Acknowledge Enable Control |
| 0 = Always sends acknowledge to host at 12th clock for host to device communication. | ||
| 1 = If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock. | ||
| [8] | CLRFIFO | Clear TX FIFO |
| Write 1 to this bit to terminate device to host transmission. | ||
| The TXEMPTY(PS2_STATUS[7]) bit will be set to 1 and pointer BYTEIDEX(PS2_STATUS[11:8]) is reset to 0 regardless there is residue data in buffer or not. | ||
| The buffer content is not been cleared. | ||
| 0 = Not active. | ||
| 1 = Clear FIFO. | ||
| [9] | OVERRIDE | Software Override PS/2 CLK/DATA Pin State |
| 0 = CLKSTAT and DATSTAT pins are controlled by internal state machine. | ||
| 1 = CLKSTAT and DATSTAT pins are controlled by software. | ||
| [10] | FPS2CLK | Force CLKSTAT Line |
| It forces CLKSTAT line high or low regardless of the internal state of the device controller if OVERRIDE is set to high. | ||
| 0 = Force CLKSTAT line low. | ||
| 1 = Force CLKSTAT line high. | ||
| [11] | FPS2DAT | Force DATSTAT Line |
| It forces DATSTAT high or low regardless of the internal state of the device controller if OVERRIDE is set to high. | ||
| 0 = Force DATSTAT low. | ||
| 1 = Force DATSTAT high. |
Definition at line 18795 of file NUC472_442.h.
| __IO uint32_t PWM_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | CMPINV | PWM Comparator Output Inverter Enable Control |
| When CMPINV is set to high, the PWM comparator output signals will be inversed, | ||
| 0 = Comparator output inverter Disabled. | ||
| 1 = Comparator output inverter Enabled. | ||
| Note: Each bit control corresponding PWM channel | ||
| [6] | OUTMODE | PWM Output Mode |
| The register controls the output mode of PWM | ||
| 0 = PWM output at independent mode. | ||
| 1 = PWM output at complementary mode. | ||
| [7] | GROUPEN | Group Mode Enable Control |
| 0 = The signals timing of each PWM channel are independent. | ||
| 1 = Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0 and unify the signals timing of PWM1, PWM3 and PWM5 in the same phase which is controlled by PWM1. | ||
| [8:13] | PINV | PWM Output Polar Inverse Enable Control |
| The register controls polarity state of PWM output | ||
| 0 = PWM output polar inverse Disabled. | ||
| 1 = PWM output polar inverse Enabled. | ||
| Note: Each bit controls the corresponding PWM channel. | ||
| [15] | SYNCEN | Synchronous Mode Enable Control |
| 0 = The signals timing of each PWM channel are independent. | ||
| 1 = Unify the signals timing of PWM0 and PWM1 in the same phase which is controlled by PWM0 and so as another two PWM pair. | ||
| Note: If Group and Synchronous mode are enabled simultaneously, the Synchronous mode will be inactive. | ||
| [16:21] | CNTMODE | PWM Counter Operation Mode |
| 0 = PWM counter working as One-shot mode. | ||
| 1 = PWM counter working as Auto-reload mode. | ||
| Note: Each bit control corresponding PWM channel | ||
| Note: If there is a transition at this bit, it will cause PWM_PERIODn and PWM_CMPDATn be cleared. | ||
| [24:29] | CNTTYPE | PWM Counter Operation Aligned Type |
| 0 = PWM counter operating as Edge-aligned type. | ||
| 1 = PWM counter operating as Center-aligned type. | ||
| Note: Each bit control corresponding PWM channel | ||
| [31] | DBGTRIOFF | ICE Debug Mode Acknowledge Disable Control (Write Protect) |
| 0 = ICE debug mode acknowledgement effects PWM output. | ||
| PWM pin will be forced as tri-state while ICE debug mode acknowledged. | ||
| 1 = ICE debug mode acknowledgement disabled. | ||
| PWM pin will keep output no matter ICE debug mode acknowledged or not. |
Definition at line 19141 of file NUC472_442.h.
| __IO uint32_t SC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SCEN | SC Engine Enable Control |
| Set this bit to 1 to enable SC operation. | ||
| If this bit is cleared, SC will force all transition to IDLE state. | ||
| [1] | RXOFF | RX Transition Disable Control |
| 0 = The receiver Enabled. | ||
| 1 = The receiver Disabled. | ||
| Note: If AUTOCEN is enabled, this fields must be ignored. | ||
| [2] | TXOFF | TX Transition Disable Control |
| 0 = The transceiver Enabled. | ||
| 1 = The transceiver Disabled. | ||
| [3] | AUTOCEN | Auto Convention Enable Control |
| 0 = Auto-convention Disabled. | ||
| 1 = Auto-convention Enabled. | ||
| When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11. | ||
| If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 3B or 3F. | ||
| After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically. | ||
| If the first data is not 3B or 3F, hardware will generate an interrupt INT_ACON_ERR (if ACON_ERR IE (SC_INTEN[10]) = 1 to CPU. | ||
| [4:5] | CONSEL | Convention Selection |
| 00 = Direct convention. | ||
| 01 = Reserved. | ||
| 10 = Reserved. | ||
| 11 = Inverse convention. | ||
| Note: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored. | ||
| [6:7] | RXTRGLV | Rx Buffer Trigger Level |
| When the number of bytes in the receiving buffer equals the RXTRGLV, the RDA_IF will be set (if IER [RDAIENN] is enabled, an interrupt will be generated). | ||
| 00 = INTR_RDA Trigger Level with 01 Bytes. | ||
| 01 = INTR_RDA Trigger Level with 02 Bytes. | ||
| 10 = INTR_RDA Trigger Level with 03 Bytes. | ||
| 11 = Reserved. | ||
| [8:12] | BGT | Block Guard Time (BGT) |
| Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions. | ||
| This field indicates the counter for the bit length of block guard time. | ||
| According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it. | ||
| In RX mode, software can enable SC_ALTCTL [RXBGTEN] to detect the first coming character timing. | ||
| If the incoming data timing less than BGT, an interrupt will be generated. | ||
| Note: The real block guard time is BGT + 1. | ||
| [13:14] | TMRSEL | Timer Selection |
| 00 = All internal timer function Disabled. | ||
| 01 = Internal 24 bit timer Enabled. | ||
| Software can configure it by setting SC_TMRCTL0 [23:0]. | ||
| SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode. | ||
| 10 = internal 24 bit timer and 8 bit internal timer Enabled. | ||
| Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0]. | ||
| SC_TMRCTL2 will be ignored in this mode. | ||
| 11 = Internal 24 bit timer and two 8 bit timers Enabled. | ||
| Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]. | ||
| [15] | NSB | Stop Bit Length |
| This field indicates the length of stop bit. | ||
| 0 = The stop bit length is 2 ETU. | ||
| 1= The stop bit length is 1 ETU. | ||
| Note: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length | ||
| [16:18] | RXRTY | RX Error Retry Count Number |
| This field indicates the maximum number of receiver retries that are allowed when parity error has occurred | ||
| Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. | ||
| Note2: This field cannot be changed when RXRTYEN enabled. | ||
| The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value. | ||
| [19] | RXRTYEN | RX Error Retry Enable Control |
| This bit enables receiver retry function when parity error has occurred. | ||
| 1 = RX error retry function Enabled. | ||
| 0 = RX error retry function Disabled. | ||
| Note: Software must fill in the RXRTY value before enabling this bit. | ||
| [20:22] | TXRTY | TX Error Retry Count Number |
| This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. | ||
| Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. | ||
| Note2: This field cannot be changed when TXRTYEN enabled. | ||
| The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value. | ||
| [23] | TXRTYEN | TX Error Retry Enable Control |
| This bit enables transmitter retry function when parity error has occurred. | ||
| 0 = TX error retry function Disabled. | ||
| 1 = TX error retry function Enabled. | ||
| [24:25] | CDDBSEL | Card Detect De-Bounce Selection |
| This field indicates the card detect de-bounce selection. | ||
| 00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks. | ||
| 01 = De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks. | ||
| 10 = De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks. | ||
| 11 = De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks. | ||
| [26] | CDLV | Card Detect Level |
| 0 = When hardware detects the card detect pin from high to low, it indicates a card is detected. | ||
| 1 = When hardware detects the card detect pin from low to high, it indicates a card is detected. | ||
| Note: Software must select card detect level before Smart Card engine enabled. | ||
| [30] | SYNC | SYNC Flag Indicator |
| Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY. | ||
| 0 = synchronizing is completion, user can write new data to SC_PINCTL register. | ||
| 1 = Last value is synchronizing. | ||
| Note: This bit is read only. |
Definition at line 21226 of file NUC472_442.h.
| __IO uint32_t SDH_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | COEN | Command Output Enable Control |
| 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) | ||
| 1 = Enabled, SD host will output a command to SD card. | ||
| Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). | ||
| [1] | RIEN | Response Input Enable Control |
| 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) | ||
| 1 = Enabled, SD host will wait to receive a response from SD card. | ||
| Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). | ||
| [2] | DIEN | Data Input Enable Control |
| 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) | ||
| 1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card. | ||
| Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). | ||
| [3] | DOEN | Data Output Enable Control |
| 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) | ||
| 1 = Enabled, SD host will transfer block data and the CRC16 value to SD card. | ||
| Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). | ||
| [4] | R2EN | Response R2 Input Enable Control |
| 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) | ||
| 1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7). | ||
| Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). | ||
| [5] | CLK74OEN | Initial 74 Clock Cycles Output Enable Control |
| 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) | ||
| 1 = Enabled, SD host will output 74 clock cycles to SD card. | ||
| Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). | ||
| [6] | CLK8OEN | Generating 8 Clock Cycles Output Enable Control |
| 0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) | ||
| 1 = Enabled, SD host will output 8 clock cycles. | ||
| Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). | ||
| [7] | CLKKEEP0 | SD Clock Enable Control For Port 0 |
| 0 = SD host decided when to output clock and when to disable clock output automatically. | ||
| 1 = SD clock always keeps free running. | ||
| [8:13] | CMDCODE | SD Command Code |
| This register contains the SD command code (0x00 - 0x3F). | ||
| [14] | CTLRST | Software Engine Reset |
| 0 = No effect. | ||
| 1 = Reset the internal state machine and counters. | ||
| The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared). | ||
| This bit will be auto cleared after few clock cycles. | ||
| [15] | DBW | SD Data Bus Width (For 1-Bit / 4-Bit Selection) |
| 0 = Data bus width is 1-bit. | ||
| 1 = Data bus width is 4-bit. | ||
| [16:23] | BLKCNT | Block Counts To Be Transferred Or Received |
| This field contains the block counts for data-in and data-out transfer. | ||
| For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance. | ||
| Don't fill 0x0 to this field. | ||
| Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1). | ||
| [24:27] | SDNWR | NWR Parameter For Block Write Operation |
| This value indicates the NWR parameter for data block write operation in SD clock counts. | ||
| The actual clock cycle will be SDNWR+1. | ||
| [29:30] | SDPORT | SD Port Selection |
| 00 = Port 0 selected. | ||
| 01 = Port 1 selected. | ||
| Other = Reserved. | ||
| [31] | CLKKEEP1 | SD Clock Enable Control For Port 1 |
| 0 = SD host decided when to output clock and when to disable clock output automatically. | ||
| 1 = SD clock always keeps free running. |
Definition at line 22291 of file NUC472_442.h.
| __IO uint32_t SPI_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SPIEN | SPI Transfer Control Enable Control |
| 0 = Transfer control Disabled. | ||
| 1 = Transfer control Enabled. | ||
| Note1: In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. | ||
| In Slave mode, this device is ready to receive data when this bit is set to 1. | ||
| Note2: All configurations should be set before writing 1 to this SPIEN bit. | ||
| (eg: TXNEG, RXNEG, DWIDTH, LSB, CLKPOL, and so on). | ||
| [1] | RXNEG | Receive On Negative Edge |
| 0 = Received data input signal is latched on the rising edge of SPICLK. | ||
| 1 = Received data input signal is latched on the falling edge of SPICLK. | ||
| [2] | TXNEG | Transmit On Negative Edge |
| 0 = Transmitted data output signal is changed on the rising edge of SPICLK. | ||
| 1 = Transmitted data output signal is changed on the falling edge of SPICLK. | ||
| [3] | CLKPOL | Clock Polarity |
| 0 = SPICLK is idle low. | ||
| 1 = SPICLK is idle high. | ||
| [4:7] | SUSPITV | Suspend Interval (Master Only) |
| SUSPITV = 0x0 ... 0.5 SPICLK clock cycle. | ||
| SUSPITV = 0x1 ... 1.5 SPICLK clock cycle. | ||
| ...... | ||
| SUSPITV = 0xE ... 14.5 SPICLK clock cycle. | ||
| SUSPITV = 0xF ... 15.5 SPICLK clock cycle. | ||
| Note: The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. | ||
| The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. | ||
| The default value is 0x3. | ||
| The period of the suspend interval is obtained according to the following equation. | ||
| (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle | ||
| [8:12] | DWIDTH | Data Transmit Bit Width |
| This field specifies how many bits can be transmitted / received in one transaction. | ||
| The minimum bit length is 8 bits and can up to 32 bits. | ||
| DWIDTH = 0x08 ... 8 bits. | ||
| DWIDTH = 0x09 ... 9 bits. | ||
| ...... | ||
| DWIDTH = 0x1F ... 31 bits. | ||
| DWIDTH = 0x00 ... 32 bits. | ||
| [13] | LSB | Send LSB First |
| 0 = MSB first. | ||
| 1 = LSB first. | ||
| Note1: The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). | ||
| Note2: The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. | ||
| [16] | TWOBIT | 2-Bit Mode Enable Control |
| 0 = 2-bit mode Disabled. | ||
| 1 = 2-bit mode Enabled. | ||
| Note: When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd | ||
| serial transmitted bit data is from the second FIFO buffer data. | ||
| As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. | ||
| [17] | UNITIEN | Unit Transfer Interrupt Enable Control |
| 0 = SPI unit transfer interrupt Disabled. | ||
| 1 = SPI unit transfer interrupt Enabled. | ||
| [18] | SLAVE | Slave Mode Enable Control |
| 0 = Master mode. | ||
| 1 = Slave mode. | ||
| [19] | REORDER | Byte Reorder Function Enable Control |
| 0 = Byte reorder function Disabled. | ||
| 1 = Byte reorder function Enabled. | ||
| Note1: Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. | ||
| Note2: The byte reorder function is not supported when the Quad or Dual I/O mode is enabled. | ||
| Note3: A byte suspend interval will be inserted among each byte. | ||
| The period of the byte suspend interval depends on the setting of SUSPITV. | ||
| [20] | QDIODIR | Quad Or Dual I/O Mode Direction Control |
| 0 = Quad or Dual Input mode. | ||
| 1 = Quad or Dual Output mode. | ||
| [21] | DUALIOEN | Dual I/O Mode Enable Control |
| 0 = Dual I/O mode Disabled. | ||
| 1 = Dual I/O mode Enabled. | ||
| [22] | QUADIOEN | Quad I/O Mode Enable Control |
| 0 = Quad I/O mode Disabled. | ||
| 1 = Quad I/O mode Enabled. |
Definition at line 22774 of file NUC472_442.h.
| __IO uint32_t TIMER_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | PSC | PSC Counter |
| Timer input clock source is divided by (PSC+1) before it is fed to the timer up counter. | ||
| If this field is 0 (PSC = 0), then there is no scaling. | ||
| [16] | CNTDATEN | Data Load Enable |
| When this bit is set, timer counter value (TIMER_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting. | ||
| 0 = Timer Data Register update Disabled. | ||
| 1 = Timer Data Register update Enabled while timer counter is active. | ||
| [21] | TOGDIS1 | Toggle Output 1 Disable |
| Setting this bit will disable the Toggle output pins group 1. | ||
| 0 = Toggle output pins group 1 Enabled. | ||
| 1 = Toggle output pins group 1 Disabled. | ||
| Note: The group1 pins are PB4, PB1, PC6, and PC1. | ||
| [22] | TOGDIS2 | Toggle Output 2 Disable |
| Setting this bit will disable the Toggle output pins group 2. | ||
| 0 = Toggle output pins group 2 Enabled. | ||
| 1 = Toggle output pins group 2 Disabled. | ||
| Note1: If both TOUT1 (group 1 pins) and TOUT2 (group 2 pins) function are enabled, toggle output signal is generated only from TOUT1 pins. | ||
| Note2: The group2 pins are PD1, PE8, PE1, and PD11. | ||
| [23] | WKEN | Wake-Up Enable |
| If this bit is set to 1, while timer interrupt flag TIF (TIMER_INTSTS[0]) is 1 and INTEN (TIMERX_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. | ||
| 0 = Wake-up trigger event Disabled if timer interrupt signal generated. | ||
| 1 = Wake-up trigger event Enabled if timer interrupt signal generated. | ||
| [24] | EXTCNTEN | Counter Mode Enable Bit |
| This bit is for external counting pin function enabled. | ||
| When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. | ||
| 0 = External counter mode Disabled. | ||
| 1 = External counter mode Enabled. | ||
| [25] | ACTSTS | Timer Active Status Bit (Read Only) |
| This bit indicates the 24-bit up counter status. | ||
| 0 = 24-bit up counter is not active. | ||
| 1 = 24-bit up counter is active. | ||
| [26] | RSTCNT | Timer Reset Bit |
| Setting this bit will reset the 24-bit up counter value (TIMER_CNT) and also force CNTEN (TIMERX_CTL[30]) to 0 if ACTSTS (TIMERX_CTL[25]) is 1. | ||
| 0 = No effect. | ||
| 1 = Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit. | ||
| [27:28] | OPMODE | Timer Operation Mode |
| 00 = The Timer controller is operated in One-shot mode. | ||
| 01 = The Timer controller is operated in Periodic mode. | ||
| 10 = The Timer controller is operated in Toggle-output mode. | ||
| 11 = The Timer controller is operated in Continuous Counting mode. | ||
| [29] | INTEN | Interrupt Enable Bit |
| 0 = Timer Interrupt Disabled. | ||
| 1 = Timer Interrupt Enabled. | ||
| If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. | ||
| [30] | CNTEN | Timer Enable |
| 0 = Stops/Suspends counting. | ||
| 1 = Starts counting. | ||
| Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. | ||
| Note2: This bit is auto-cleared by hardware in one-shot mode (TIMERX_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMER_INTSTS[0]) is generated. | ||
| [31] | ICEDEBUG | ICE Debug Mode Acknowledge Disable (Write Protect) |
| 0 = ICE debug mode acknowledgement effects TIMER counting. | ||
| TIMER counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| TIMER counter will keep going no matter CPU is held by ICE or not. |
Definition at line 24954 of file NUC472_442.h.
| __IO uint32_t WDT_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RSTCNT | Clear Watchdog Timer (Write Protect) |
| 0 = No effect. | ||
| 1 = Reset the internal 18-bit WDT counter. | ||
| Note: This bit will be automatically cleared by hardware. | ||
| [1] | RSTEN | Watchdog Timer Reset Enable Control (Write Protect) |
| Setting this bit will enable the Watchdog Timer time-out reset function If the WDT counter value has not been cleared after the specific WDT reset delay period expires. | ||
| 0 = Watchdog Timer time-out reset function Disabled. | ||
| 1 = Watchdog Timer time-out reset function Enabled. | ||
| [2] | RSTF | Watchdog Timer Reset Flag |
| This bit indicates the system has been reset by WDT time-out reset or not. | ||
| 0 = Watchdog Timer time-out reset did not occur. | ||
| 1 = Watchdog Timer time-out reset occurred. | ||
| Note: This bit is cleared by writing 1 to this bit. | ||
| [3] | IF | Watchdog Timer Interrupt Flag |
| This bit will set to 1 while WDT counter value reaches the selected WDT time-out interval | ||
| 0 = Watchdog Timer time-out interrupt did not occur. | ||
| 1 = Watchdog Timer time-out interrupt occurred. | ||
| Note: This bit is cleared by writing 1 to this bit. | ||
| [4] | WKEN | Watchdog Timer Wake-Up Function Enable Control (Write Protect) |
| If this bit is set to 1, while WDT interrupt flag (WDT_CTL[3] IF) is generated to 1 and INTEN (WDT_CTL[6] WDT interrupt enable) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. | ||
| 0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. | ||
| 1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. | ||
| Note: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator. | ||
| [5] | WKF | Watchdog Timer Wake-Up Flag |
| This bit indicates the interrupt wake-up flag status of WDT | ||
| 0 = Watchdog Timer does not cause chip wake-up. | ||
| 1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [6] | INTEN | Watchdog Timer Interrupt Enable Control (Write Protect) |
| If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. | ||
| 0 = Watchdog Timer interrupt Disabled. | ||
| 1 = Watchdog Timer interrupt Enabled. | ||
| [7] | WDTEN | Watchdog Timer Enable Control (Write Protect) |
| 0 = Watchdog Timer Disabled (This action will reset the internal counter). | ||
| 1 = Watchdog Timer Enabled. | ||
| Note: If CWDTEN (Config0[31] watchdog enable) bit is set to 0, this bit is forced as 1 and software cannot change this bit to 0. | ||
| [8:10] | TOUTSEL | Watchdog Timer Time-Out Interval Selection (Write Protect) |
| These three bits select the time-out interval period for the Watchdog Timer. | ||
| 000 = 2^4 * TWDT. | ||
| 001 = 2^6 * TWDT. | ||
| 010 = 2^8 * TWDT. | ||
| 011 = 2^10 * TWDT. | ||
| 100 = 2^12 * TWDT. | ||
| 101 = 2^14 * TWDT. | ||
| 110 = 2^16 * TWDT. | ||
| 111 = 2^18 * TWDT. | ||
| [31] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Control (Write Protect) |
| 0 = ICE debug mode acknowledgement affects Watchdog Timer counting. | ||
| Watchdog Timer counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| Watchdog Timer counter will keep going no matter CPU is held by ICE or not. |
Definition at line 28496 of file NUC472_442.h.
| __IO uint32_t WWDT_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WWDTEN | WWDT Enable Control |
| Set this bit to enable Window Watchdog Timer counter counting. | ||
| 0 = Window Watchdog Timer counter is stopped. | ||
| 1 = Window Watchdog Timer counter is starting counting. | ||
| [1] | INTEN | WWDT Interrupt Enable Control |
| If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. | ||
| 0 = WWDT counter compare match interrupt Disabled. | ||
| 1 = WWDT counter compare match interrupt Enabled. | ||
| [8:11] | PSCSEL | WWDT Counter Prescale Period Selection |
| 0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT. | ||
| 0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT. | ||
| 0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT. | ||
| 0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT. | ||
| 0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT. | ||
| 0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT. | ||
| 0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT. | ||
| 0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT. | ||
| 1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT. | ||
| 1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT. | ||
| 1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT. | ||
| 1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT. | ||
| 1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT. | ||
| 1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT. | ||
| 1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT. | ||
| 1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT. | ||
| [16:21] | CMPDAT | WWDT Window Compare Bits |
| Set this register to adjust the valid reload window. | ||
| Note: Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. | ||
| If Software writes RLDCNT when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. | ||
| [31] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Control |
| 0 = ICE debug mode acknowledgement effects WWDT counting. | ||
| WWDT down counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| WWDT down counter will keep going no matter CPU is held by ICE or not. |
Definition at line 28625 of file NUC472_442.h.
| __IO uint32_t ECAP_T::CTL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | NFDIS | Noise Filter Clock Pre-Divide Selection |
| To determine the sampling frequency of the Noise Filter clock | ||
| 00 = CAP_CLK. | ||
| 01 = CAP_CLK/2. | ||
| 10 = CAP_CLK/4. | ||
| 11 = CAP_CLK/16. | ||
| [3] | CAPNF_DIS | Input Capture Noise Filter Disable Control |
| 0 = Noise filter of Input Capture Enabled. | ||
| 1 = Noise filter of Input Capture Disabled. | ||
| [4] | CAPEN0 | Port Pin IC0 Input To Input Capture Unit Enable Control |
| 0 = IC0 input to Input Capture Unit Disabled. | ||
| 1 = IC0 input to Input Capture Unit Enabled. | ||
| [5] | CAPEN1 | Port Pin IC1 Input To Input Capture Unit Enable Control |
| 0 = IC1 input to Input Capture Unit Disabled. | ||
| 1 = IC1 input to Input Capture Unit Enabled. | ||
| [6] | CAPEN2 | Port Pin IC2 Input To Input Capture Unit Enable Control |
| 0 = IC2 input to Input Capture Unit Disabled. | ||
| 1 = IC2 input to Input Capture Unit Enabled. | ||
| [8:9] | CAPSEL0 | CAP0 Input Source Selection |
| 00 = CAP0 input is from port pin IC0. | ||
| 01 = CAP0 input is from signal CPO0 (Analog comparator 0 output). | ||
| 10 = CAP0 input is from signal CHA of QEI controller unit x. | ||
| 11 = CAP0 input is from signal OPDO0 (OP0 digital output). | ||
| Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1. | ||
| [10:11] | CAPSEL1 | CAP1 Input Source Selection |
| 00 = CAP1 input is from port pin IC1. | ||
| 01 = CAP1 input is from signal CPO1 (Analog comparator 1 output). | ||
| 10 = CAP1 input is from signal CHB of QEI controller unit x. | ||
| 11 = CAP1 input is from signal OPDO1 (OP1 digital output). | ||
| Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1. | ||
| [12:13] | CAPSEL2 | CAP2 Input Source Selection |
| 00 = CAP2 input is from port pin IC2. | ||
| 01 = CAP2 input is from signal CPO2 (Analog comparator 2 output). | ||
| 10 = CAP2 input is from signal CHX of QEI controller unit x. | ||
| 11 = CAP2 input is from signal ADCMPOx (ADC compare output x). | ||
| Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1. | ||
| [16] | CAPIEN0 | Input Capture Channel 0 Interrupt Enable Control |
| 0 = The flag CAPF0 can trigger Input Capture interrupt Disabled. | ||
| 1 = The flag CAPF0 can trigger Input Capture interrupt Enabled. | ||
| [17] | CAPIEN1 | Input Capture Channel 1 Interrupt Enable Control |
| 0 = The flag CAPF1 can trigger Input Capture interrupt Disabled. | ||
| 1 = The flag CAPF1 can trigger Input Capture interrupt Enabled. | ||
| [18] | CAPIEN2 | Input Capture Channel 2 Interrupt Enable Control |
| 0 = The flag CAPF2 can trigger Input Capture interrupt Disabled. | ||
| 1 = The flag CAPF2 can trigger Input Capture interrupt Enabled. | ||
| [20] | OVIEN | OVF Trigger Input Capture Interrupt Enable Control |
| 0 = The flag OVUNF can trigger Input Capture interrupt Disabled. | ||
| 1 = The flag OVUNF can trigger Input Capture interrupt Enabled. | ||
| [21] | CMPIEN | CMPF Trigger Input Capture Interrupt Enable Control |
| 0 = The flag CMPF can trigger Input Capture interrupt Disabled. | ||
| 1 = The flag CMPF can trigger Input Capture interrupt Enabled. | ||
| [24] | CNTEN | Input Capture Counter Start |
| Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK). | ||
| 0 = ECAP_CNT stop counting. | ||
| 1 = ECAP_CNT starts up-counting. | ||
| [25] | CMPCLR | Input Capture Counter Cleared By Compare-Match Control |
| If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAMCMPF = 1) occurs. | ||
| 0 = Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Disabled. | ||
| 1 = Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Enabled. | ||
| [26] | CPTCLR | Input Capture Counter Cleared By Capture Events Control |
| If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to zero when any one of capture events (CAPF0~3) occurs. | ||
| 0 = Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Disabled. | ||
| 1 = Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Enabled. | ||
| [27] | RLDEN | Reload Function Enable Control |
| Setting this bit to enable the reload function. | ||
| If the reload control is enabled, an overflow event (OVF) or capture events (CAPFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT. | ||
| 0 = The reload function Disabled. | ||
| 1 = The reload function Enabled. | ||
| [28] | CMPEN | Compare Function Enable Control |
| The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CMPF will be set. | ||
| 0 = The compare function Disabled. | ||
| 1 = The compare function Enabled. | ||
| [29] | CAPEN | Input Capture Timer/Counter Enable Control |
| 0 = Input Capture function Disabled. | ||
| 1 = Input Capture function Enabled. |
Definition at line 2573 of file NUC472_442.h.
| __IO uint32_t ECAP_T::CTL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | EDGESEL0 | Channel 0 Captured Edge Selection |
| Input capture can detect falling edge change only, rising edge change only or one of both edge change | ||
| 00 = Detect rising edge. | ||
| 01 = Detect falling edge. | ||
| 1x = Detect either rising or falling edge. | ||
| [2:3] | EDGESEL1 | Channel 1 Captured Edge Selection |
| Input capture can detect falling edge change only, rising edge change only or one of both edge change | ||
| 00 = Detect rising edge. | ||
| 01 = Detect falling edge. | ||
| 1x = Detect either rising or falling edge. | ||
| [4:5] | EDGESEL2 | Channel 2 Captured Edge Selection |
| Input capture can detect falling edge change or rising edge change only, or one of both edge changes. | ||
| 00 = Detect rising edge. | ||
| 01 = Detect falling edge. | ||
| 1x = Detect either rising or falling edge. | ||
| [8:10] | RLDSEL | ECAP_CNT Reload Trigger Source Selection |
| If the reload function is enabled RLDEN (ECAP_CTL0[27]) = 1, when a reload trigger event comes, the ECAP_CNT is reloaded with ECAP_CNTCMP. | ||
| RLDSEL[2:0] determines the ECAP_CNT reload trigger source | ||
| 000 = CAPF0. | ||
| 001 = CAPF1. | ||
| 010 = CAPF2. | ||
| 100 = OVF. | ||
| Others = Reserved. | ||
| [12:14] | CLKSEL | Capture Timer Clock Divide Selection |
| The capture timer clock has a pre-divider with four divided options controlled by CLKSEL[1:0]. | ||
| 000 = CAP_CLK/1. | ||
| 001 = CAP_CLK/4. | ||
| 010 = CAP_CLK/16. | ||
| 011 = CAP_CLK/32. | ||
| 100 = CAP_CLK/64. | ||
| 101 = CAP_CLK/96. | ||
| 110 = CAP_CLK/112. | ||
| 111 = CAP_CLK/128. | ||
| [16:17] | SRCSEL | Capture Timer/Counter Clock Source Selection |
| Select the capture timer/counter clock source. | ||
| 00 = CAP_CLK (default). | ||
| 01 = CAP0. | ||
| 10 = CAP1. | ||
| 11 = CAP2. |
Definition at line 2622 of file NUC472_442.h.
| __IO uint32_t QEI_T::CTR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | NFCLKSEL | Noise Filter Clock Pre-Divide Selection |
| To determine the sampling frequency of the Noise Filter clock . | ||
| 00 = QEI_CLK. | ||
| 01 = QEI_CLK/2. | ||
| 10 = QEI_CLK/4. | ||
| 11 = QEI_CLK/16. | ||
| [3] | NFDIS | QEI Controller Input Noise Filter Disable Control |
| 0 = The noise filter of QEI controller Enabled. | ||
| 1 = The noise filter of QEI controller Disabled. | ||
| [4] | CHAEN | QEA Input To QEI Controller Enable Control |
| 0 = QEA input to QEI Controller Disabled. | ||
| 1 = QEA input to QEI Controller Enabled. | ||
| [5] | CHBEN | QEB Input To QEI Controller Enable Control |
| 0 = QEB input to QEI Controller Disabled. | ||
| 1 = QEB input to QEI Controller Enabled. | ||
| [6] | IDXEN | IDX Input To QEI Controller Enable Control |
| 0 = IDX input to QEI Controller Disabled. | ||
| 1 = IDX input to QEI Controller Enabled. | ||
| [8:9] | MODE | QEI Counting Mode Selection |
| There are four quadrature encoder pulse counter operation modes. | ||
| 00 = X4 Free-counting Mode. | ||
| 01 = X2 Free-counting Mode. | ||
| 10 = X4 Compare-counting Mode. | ||
| 11 = X2 Compare-counting Mode. | ||
| [12] | CHAINV | Inverse QEA Input Polarity |
| 0 = Not inverse QEA input polarity. | ||
| 1 = QEA input polarity is inversed to QEI controller. | ||
| [13] | CHBINV | Inverse QEB Input Polarity |
| 0 = Not inverse QEB input polarity. | ||
| 1 = QEB input polarity is inversed to QEI controller. | ||
| [14] | IDXINV | Inverse IDX Input Polarity |
| 0 = Not inverse IDX input polarity. | ||
| 1 = IDX input polarity is inversed to QEI controller. | ||
| [16] | OVUNIEN | OVUNF Trigger QEI Interrupt Enable Control |
| 0 = OVUNF can trigger QEI controller interrupt Disabled. | ||
| 1 = OVUNF can trigger QEI controller interrupt Enabled. | ||
| [17] | DIRIEN | DIRCHGF Trigger QEI Interrupt Enable Control |
| 0 = DIRCHGF can trigger QEI controller interrupt Disabled. | ||
| 1 = DIRCHGF can trigger QEI controller interrupt Enabled. | ||
| [18] | CMPIEN | CMPF Trigger QEI Interrupt Enable Control |
| 0 = CMPF can trigger QEI controller interrupt Disabled. | ||
| 1 = CMPF can trigger QEI controller interrupt Enabled. | ||
| [19] | IDXIEN | IDXF Trigger QEI Interrupt Enable Control |
| 0 = The IDXF can trigger QEI interrupt Disabled. | ||
| 1 = The IDXF can trigger QEI interrupt Enabled. | ||
| [20] | HOLDTMR0 | Hold QEI_CNT By Timer 0 |
| 0 = TIF (TISR0[0]) has no effect on HOLDCNT. | ||
| 1 = A rising edge of bit TIF (TISR0[0]) in timer 0 sets HOLDCNT to 1. | ||
| [21] | HOLDTMR1 | Hold QEI_CNT By Timer 1 |
| 0 = TIF (TISR1[0]) has no effect on HOLDCNT. | ||
| 1 = A rising edge of bit TIF (TISR1[0]) in timer 1 sets HOLDCNT to 1. | ||
| [22] | HOLDTMR2 | Hold QEI_CNT By Timer 2 |
| 0 = TIF (TISR2[0]) has no effect on HOLDCNT. | ||
| 1 = A rising edge of bit TIF (TISR2[0]) in timer 2 sets HOLDCNT to 1. | ||
| [23] | HOLDTMR3 | Hold QEI_CNT By Timer 3 |
| 0 = TIF (TISR3[0]) has no effect on HOLDCNT. | ||
| 1 = A rising edge of bit TIF (TISR3[0]) in timer 3 sets HOLDCNT to 1. | ||
| [24] | HOLDCNT | Hold QEI_CNT Control |
| When this bit is set from low to high, the QEI_CNT value is copied into QEI_CNTHOLD. | ||
| This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TISTRx[0]). | ||
| 0 = No operation. | ||
| 1 = QEI_CNT content is captured and stored in QEI_CNTHOLD. | ||
| Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value. | ||
| [25] | IDXLATEN | Index Latch QEI_CNT Enable Control |
| If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX. | ||
| 0 = The index signal latch QEI counter function Disabled. | ||
| 1 = The index signal latch QEI counter function Enabled. | ||
| [27] | IDXRLDEN | Index Trigger QEI_CNT Reload Enable Control |
| When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with QEI_MAXCNT content if the counter is in down-counting type (DIRF = 0). | ||
| 0 = Reload function Disabled. | ||
| 1 = QEI_CNT re-initialized by Index signal Enabled. | ||
| [28] | CMPENN | The Compare Function Enable Control |
| The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register QEI_CNTCMP, if QEI_CNT value reaches QEI_CNTCMP, the flag CMPF will be set. | ||
| 0 = Compare function Disabled. | ||
| 1 = Compare function Enabled. | ||
| [29] | QEIEN | Quadrature Encoder Interface Controller Enable Control |
| 0 = QEI controller function Disabled. | ||
| 1 = QEI controller function Enabled. |
Definition at line 20247 of file NUC472_442.h.
| __I uint32_t EMAC_T::CTXBSA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CTXBSA | Current Transmit Buffer Start Address |
| The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently. | ||
| The CTXBSA is read only and write to this register has no effect. |
Definition at line 13071 of file NUC472_442.h.
| __I uint32_t EMAC_T::CTXDSA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CTXDSA | Current Transmit Descriptor Start Address |
| The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently. | ||
| The CTXDSA is read only and write to this register has no effect. |
Definition at line 13058 of file NUC472_442.h.
| __I uint32_t CAP_T::CURADDRP |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CURADDR | Current Packet Output Memory Address |
Definition at line 2075 of file NUC472_442.h.
| __I uint32_t CAP_T::CURADDRU |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CURADDR | Current Planar U Output Memory Address |
Definition at line 2097 of file NUC472_442.h.
| __I uint32_t CAP_T::CURADDRY |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CURADDR | Current Planar Y Output Memory Address |
Definition at line 2086 of file NUC472_442.h.
| __I uint32_t ADC_T::CURDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:17] | CURDAT | ADC PDMA Current Transfer Data Bit (Read Only) |
| When PDMA transferring, read this register can monitor current PDMA transfer data. |
Definition at line 602 of file NUC472_442.h.
| __I uint32_t CAP_T::CURVADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CURADDR | Current Planar V Output Memory Address |
Definition at line 2108 of file NUC472_442.h.
| __IO uint32_t CAP_T::CWS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:11] | CIWW | Cropping Image Window Width |
| [16:26] | CIWH | Cropping Image Window Height |
Definition at line 1903 of file NUC472_442.h.
| __IO uint32_t CAP_T::CWSP |
| Bits | Field | Descriptions |
|---|---|---|
| [0:11] | CWSADDRH | Cropping Window Horizontal Starting Address |
| [16:26] | CWSADDRV | Cropping Window Vertical Starting Address |
Definition at line 1891 of file NUC472_442.h.
| __I uint32_t ADC_T::DAT[14] |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | RESULT | A/D Conversion Result |
| This field contains conversion result of ADC. | ||
| When DMOF (ADC_CTL[31]) bit is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. | ||
| When DMOF (ADC_CTL[31]) bit set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. | ||
| [16] | OV | Overrun Flag (Read Only) |
| 0 = Data in RESULT (ADC_DATx[15:0]) is recent conversion result. | ||
| 1 = Data in RESULT (ADC_DATx[15:0]) is overwrite. | ||
| If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 and previous conversion result is gone. | ||
| It is cleared by hardware after ADC_DAT register is read. | ||
| [17] | VALID | Valid Flag (Read Only) |
| 0 = Data in RESULT (ADC_DATx[15:0]) bits is not valid. | ||
| 1 = Data in RESULT (ADC_DATx[15:0]) bits is valid. | ||
| This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read. |
Definition at line 394 of file NUC472_442.h.
| __IO uint32_t CRC_T::DAT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DATA | CRC Write Data Bits |
| Software can write data to this field to perform CRC operation, or uses PDMA function to get the data from memory | ||
| Note1: The CRC_CTL [DATFMT] and CRC_CTL [DATREV] bit setting will affect this field; for example, if DATREV = 1, if the write data in DATA register is 0xAABBCCDD, the read data from DATA register will be 0x55DD33BB. |
Definition at line 4047 of file NUC472_442.h.
| __IO uint32_t I2C_T::DAT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | DAT | I2C Data Bits |
| Bit [7:0] is located with the 8-bit transferred data of I2C serial port. |
Definition at line 16882 of file NUC472_442.h.
| __IO uint32_t SC_T::DAT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | DAT | Receiving/ Transmit Buffer |
| Write Operation: | ||
| By writing data to DAT, the SC will send out an 8-bit data. | ||
| Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed. | ||
| Read Operation: | ||
| By reading DAT, the SC will return an 8-bit received data. |
Definition at line 21131 of file NUC472_442.h.
| __IO uint32_t UART_T::DAT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | DAT | Receiving/Transmit Buffer |
| Write Operation: | ||
| By writing one byte to this register, the data byte will be stored in transmitter FIFO. The | ||
| UART Controller will send out the data stored in transmitter FIFO top location through the | ||
| UART_TXD. | ||
| Read Operation: | ||
| By reading this register, the UART will return an 8-bit data received from receiving FIFO |
Definition at line 25188 of file NUC472_442.h.
| __IO uint32_t CAN_IF_T::DAT_A1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | Data0 | Data Byte 0 |
| 1st data byte of a CAN Data Frame | ||
| [8:15] | Data1 | Data Byte 1 |
| 2nd data byte of a CAN Data Frame |
Definition at line 1077 of file NUC472_442.h.
| __IO uint32_t CAN_IF_T::DAT_A2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | Data2 | Data Byte 2 |
| 3rd data byte of CAN Data Frame | ||
| [8:15] | Data3 | Data Byte 3 |
| 4th data byte of CAN Data Frame |
Definition at line 1091 of file NUC472_442.h.
| __IO uint32_t CAN_IF_T::DAT_B1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | Data4 | Data Byte 4 |
| 5th data byte of CAN Data Frame | ||
| [8:15] | Data5 | Data Byte 5 |
| 6th data byte of CAN Data Frame |
Definition at line 1105 of file NUC472_442.h.
| __IO uint32_t CAN_IF_T::DAT_B2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | Data6 | Data Byte 6 |
| 7th data byte of CAN Data Frame. | ||
| [8:15] | Data7 | Data Byte 7 |
| 8th data byte of CAN Data Frame. |
Definition at line 1119 of file NUC472_442.h.
| __IO uint32_t GPIO_T::DATMSK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DATMSK0 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [1] | DATMSK1 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [2] | DATMSK2 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [3] | DATMSK3 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [4] | DATMSK4 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [5] | DATMSK5 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [6] | DATMSK6 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [7] | DATMSK7 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [8] | DATMSK8 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [9] | DATMSK9 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [10] | DATMSK10 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [11] | DATMSK11 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [12] | DATMSK12 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [13] | DATMSK13 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [14] | DATMSK14 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. | ||
| [15] | DATMSK15 | Port N Bit M Data Output Write Mask |
| These bits are used to protect the corresponding register of Px_DOUT[m]. | ||
| When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored. | ||
| The write to port pin latch is masked. | ||
| 0 = Px_DOUT[m] bit writing is valid. | ||
| 1 = Px_DOUT[m] bit writing is ignored. |
Definition at line 15435 of file NUC472_442.h.
| __IO uint32_t GPIO_DB_T::DBCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | DBCLKSEL | De-Bounce Sampling Cycle Selection |
| 0000 = Sample interrupt input once per 1 clocks. | ||
| 0001 = Sample interrupt input once per 2 clocks. | ||
| 0010 = Sample interrupt input once per 4 clocks. | ||
| 0011 = Sample interrupt input once per 8 clocks. | ||
| 0100 = Sample interrupt input once per 16 clocks. | ||
| 0101 = Sample interrupt input once per 32 clocks. | ||
| 0110 = Sample interrupt input once per 64 clocks. | ||
| 0111 = Sample interrupt input once per 128 clocks. | ||
| 1000 = Sample interrupt input once per 256 clocks. | ||
| 1001 = Sample interrupt input once per 2*256 clocks. | ||
| 1010 = Sample interrupt input once per 4*256 clocks. | ||
| 1011 = Sample interrupt input once per 8*256 clocks. | ||
| 1100 = Sample interrupt input once per 16*256 clocks. | ||
| 1101 = Sample interrupt input once per 32*256 clocks. | ||
| 1110 = Sample interrupt input once per 64*256 clocks. | ||
| 1111 = Sample interrupt input once per 128*256 clocks. | ||
| [4] | DBCLKSRC | De-Bounce Counter Clock Source Selection |
| 0 = De-bounce counter clock source is the HCLK. | ||
| 1 = De-bounce counter clock source is the internal 10 kHz clock. | ||
| [5] | ICLKON | Interrupt Clock On Mode |
| Setting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled. | ||
| 0 = Disable the clock if the all port interrupts are disabled. | ||
| 1 = Interrupt generated circuit clock always Enabled. |
Definition at line 16216 of file NUC472_442.h.
| __IO uint32_t GPIO_T::DBEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DBEN0 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [1] | DBEN1 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [2] | DBEN2 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [3] | DBEN3 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| The de-bounce clock is controlled by GPIO_DBCTL register. | ||
| 0 = Port n bit m input de-bounce Disabled. | ||
| 1 = Port n bit m input de-bounce Enabled. | ||
| [4] | DBEN4 | Port N Bit M Input De-Bounce Enable |
| DBEN[m] is used to enable the de-bounce function for each corresponding bit. | ||
| DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt. | ||
| If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||