| 0 = Don't force USB bus to K state. | ||
| 1 = Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up. | ||
| [9] | WAKEUP_EN | Wake-Up Function Enable |
| 0 = USB wake-up function Disabled. | ||
| 1 = USB wake-up function Enabled. |
Definition at line 10950 of file Nano100Series.h.
| __IO uint32_t WDT_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WTR | Clear Watchdog Timer |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Set this bit will clear the Watchdog timer. | ||
| 0 = No effect. | ||
| 1 = Reset the contents of the Watchdog timer. | ||
| Note: This bit will be auto cleared after few clock cycles. | ||
| [1] | WTRE | Watchdog Timer Reset Function Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Setting this bit will enable the Watchdog timer reset function. | ||
| 0 = Watchdog timer reset function Disabled. | ||
| 1 = Watchdog timer reset function Enabled. | ||
| [2] | WTWKE | Watchdog Timer Wake-Up Function Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Watchdog timer Wake-up CPU function Disabled. | ||
| 1 = Wake-up function Enabled so that Watchdog timer time-out can wake up CPU from power-down mode. | ||
| [3] | WTE | Watchdog Timer Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Watchdog timer Disabled (this action will reset the internal counter). | ||
| 1 = Watchdog timer Enabled. | ||
| [6:4] | WTIS | Watchdog Timer Interval Selection |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| These three bits select the time-out interval for the Watchdog timer. | ||
| This count is free running counter. | ||
| Please refer to the Table 5-16. | ||
| [9:8] | WTRDSEL | Watchdog Timer Reset Delay Select |
| When watchdog timeout happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened. | ||
| Software can select a suitable value of watchdog reset delay period for different watchdog timeout period. | ||
| 00 = Watchdog reset delay period is 1026 watchdog clock | ||
| 01 = Watchdog reset delay period is 130 watchdog clock | ||
| 10 = Watchdog reset delay period is 18 watchdog clock | ||
| 11 = Watchdog reset delay period is 3 watchdog clock | ||
| This register will be reset if watchdog reset happened |
Definition at line 11375 of file Nano100Series.h.
| __IO uint32_t DAC_T::CTL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DACEN | DAC Enable |
| 0 = Power down DAC. | ||
| 1 = Power on DAC. | ||
| Note: When DAC is powered on, DAC will automatically start conversion after waiting for DACPWONSTBCNT+1 PCLK cycle | ||
| [1] | DACIE | DAC Interrupt Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [6:4] | DACLSEL | DAC Load Selection |
| Select the load trigger for the DAC latch. | ||
| 000 = DAC latch loads when DACx_DAT written | ||
| 001 = PDMA ACK | ||
| 010 = Rising edge of TMR0 | ||
| 011 = Rising edge of TMR1 | ||
| 100 = Rising edge of TMR2 | ||
| 101 = Rising edge of TMR3 | ||
| Others = Reserved | ||
| [21:8] | DACPWONSTBCNT | DACPWONSTBCNT |
| DAC need 6 us to be stable after DAC is power on from power down state. | ||
| This field controls a internal counter (in PCLK unit) to guarantee DAC stable time requirement. |
Definition at line 1508 of file Nano100Series.h.
| __IO uint32_t DAC_T::CTL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DACEN | DAC Enable |
| 0 = Power down DAC. | ||
| 1 = Power on DAC. | ||
| Note: When DAC is powered on, DAC will automatically start conversion after waiting for DACPWONSTBCNT+1 PCLK cycle | ||
| [1] | DACIE | DAC Interrupt Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [6:4] | DACLSEL | DAC Load Selection |
| Select the load trigger for the DAC latch. | ||
| 000 = DAC latch loads when DACx_DAT written | ||
| 001 = PDMA ACK | ||
| 010 = Rising edge of TMR0 | ||
| 011 = Rising edge of TMR1 | ||
| 100 = Rising edge of TMR2 | ||
| 101 = Rising edge of TMR3 | ||
| Others = Reserved | ||
| [21:8] | DACPWONSTBCNT | DACPWONSTBCNT |
| DAC need 6 us to be stable after DAC is power on from power down state. | ||
| This field controls a internal counter (in PCLK unit) to guarantee DAC stable time requirement. |
Definition at line 1571 of file Nano100Series.h.
| __IO uint32_t I2S_T::CTRL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | I2SEN | I2S Controller Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | TXEN | Transmit Enable |
| 0 = Data transmitting Disabled. | ||
| 1 = Data transmitting Enabled. | ||
| [2] | RXEN | Receive Enable |
| 0 = Data receiving Disabled. | ||
| 1 = Data receiving Enabled. | ||
| [3] | MUTE | Transmitting Mute Enable |
| 0 = Transmit data in buffer to channel. | ||
| 1 = Transmit '0' to channel. | ||
| [5:4] | WORDWIDTH | Word Width |
| 00 = Data is 8 bit. | ||
| 01 = Data is 16 bit. | ||
| 10 = Data is 24 bit. | ||
| 11 = Data is 32 bit. | ||
| [6] | MONO | Monaural Data |
| 0 = Data is stereo format. | ||
| 1 = Data is monaural format and gets the right channel data from I2S bus when this mode is enabled. | ||
| [7] | FORMAT | Data Format |
| 0 = I2S data format. | ||
| 1 = MSB justified data format. | ||
| [8] | SLAVE | Slave Mode |
| I2S can operate as master or Slave mode. | ||
| For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and also outputs I2S_BCLK and I2S_LRCLK signals to the audio CODEC. | ||
| When act as Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from the outer audio CODEC chip. | ||
| 0 = Master mode. | ||
| 1 = Slave mode. | ||
| [11:9] | TXTH | Transmit FIFO Threshold Level |
| If remain data word (32 bits) in transmitting FIFO is the same or less than threshold level then TXTHF flag is set. | ||
| 000 = 1 word data in transmitting FIFO. | ||
| 001 = 2 word data in transmitting FIFO. | ||
| 010 = 3 word data in transmitting FIFO. | ||
| 011 = 4 word data in transmitting FIFO. | ||
| 100 = 5 word data in transmitting FIFO. | ||
| 101 = 6 word data in transmitting FIFO. | ||
| 110 = 7 word data in transmitting FIFO. | ||
| 111 = 8 word data in transmitting FIFO. | ||
| [14:12] | RXTH | Receiving FIFO Threshold Level |
| When received data word(s) in buffer is equal to or higher than threshold level, the RXTHF flag is set. | ||
| 000 = 1 word data in receiving FIFO. | ||
| 001 = 2 word data in receiving FIFO. | ||
| 010 = 3 word data in receiving FIFO. | ||
| 011 = 4 word data in receiving FIFO. | ||
| 100 = 5 word data in receiving FIFO. | ||
| 101 = 6 word data in receiving FIFO. | ||
| 110 = 7 word data in receiving FIFO. | ||
| 111 = 8 word data in receiving FIFO. | ||
| [15] | MCLKEN | Master Clock Enable |
| Enable master MCLK timing output to the external audio codec device. | ||
| The output frequency is according to MCLK_DIV[2:0] in the I2S_CLKDIV register. | ||
| 0 = Master Clock Disabled. | ||
| 1 = Master Clock Enabled. | ||
| [16] | RCHZCEN | Right Channel Zero Cross Detect Enable |
| If this bit is set to "1", when right channel data sign bit is changed or next shift data bits are all zero then RZCF flag in I2S_STATUS register is set to "1". | ||
| It works on transmitting mode only. | ||
| 0 = Right channel zero cross detection Disabled. | ||
| 1 = Right channel zero cross detection Enabled. | ||
| [17] | LCHZCEN | Left Channel Zero Cross Detect Enable |
| If this bit is set to "1", when left channel data sign bit is changed or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to "1". | ||
| It works on transmitting mode only. | ||
| 0 = Left channel zero cross detection Disabled. | ||
| 1 = Left channel zero cross detection Enabled. | ||
| [18] | CLR_TXFIFO | Clear Transmit FIFO |
| Write "1" to clear transmitting FIFO, internal pointer is reset to FIFO start point, TX_LEVEL[3:0] returns to zero and transmitting FIFO becomes empty but data in transmit FIFO is not changed. | ||
| This bit is cleared by hardware automatically, read it to return zero. | ||
| [19] | CLR_RXFIFO | Clear Receiving FIFO |
| Write "1" to clear receiving FIFO, internal pointer is reset to FIFO start point, and RX_LEVEL[3:0] returns to zero and receiving FIFO becomes empty. | ||
| This bit is cleared by hardware automatically, and read it return zero. | ||
| [20] | TXDMA | Enable Transmit DMA |
| When TX DMA is enabled, I2S requests PDMA to transfer data from memory to transmitting FIFO if FIFO is not full | ||
| 0 = TX DMA Disabled. | ||
| 1 = TX DMA Enabled. | ||
| [21] | RXDMA | Enable Receive DMA |
| When RX DMA is enabled, I2S requests PDMA to transfer data from receiving FIFO to memory if FIFO is not empty. | ||
| 0 = RX DMA Disabled. | ||
| 1 = RX DMA Enabled. | ||
| [23] | RXLCH | Receive Left Channel Enable |
| When monaural format is selected (MONO = 1), I2S will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. | ||
| 0 = Receives right channel data when monaural format is selected. | ||
| 1 = Receives left channel data when monaural format is selected. |
Definition at line 4624 of file Nano100Series.h.
| __IO uint32_t PDMA_T::DAR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | PDMA_DAR | PDMA Transfer Destination Address Register |
| This field indicates a 32-bit destination address of PDMA. | ||
| Note : The destination address must be word alignment |
Definition at line 5987 of file Nano100Series.h.
| __IO uint32_t VDMA_T::DAR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | VDMA_DAR | VDMA Transfer Destination Address Register |
| This field indicates a 32-bit destination address of VDMA. |
Definition at line 6172 of file Nano100Series.h.
| __IO uint32_t VDMA_T::DASOCR |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | DASTOBL | VDMA Destination Address Stride Offset Byte Length |
| The 16-bit register defines the destination address stride transfer offset count of each row. |
Definition at line 6289 of file Nano100Series.h.
| __IO uint32_t I2C_T::DATA |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DATA | I2C Data Register |
| The DATA contains a byte of serial data to be transmitted or a byte which has just been received. | ||
| The user can read from or write to this 8-bit I2CDATA register directly while it is not in the process of shifting a byte. | ||
| This occurs when the serial interrupt flag is set. | ||
| Data in DATA remains stable as long as I2C_STS bit is set. | ||
| While data is being shifted out, data on the bus is simultaneously being shifted in; The DATA always contains the last data byte present on the bus. | ||
| Thus, in the event of arbitration lost, the transition from master transmitter to slave receiver is made with the correct data in DATA. | ||
| DATA and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the device hardware and cannot be accessed by the user. | ||
| Serial data is shifted through the acknowledge bit into DATA on the rising edges of serial clock pulses on the SCL line. | ||
| When a byte has been shifted into DATA, the serial data is available in DATA, and the acknowledge bit (ACK or NACK) is returned by the control logic during the ninth clock pulse. |
Definition at line 4343 of file Nano100Series.h.
| __IO uint32_t DAC_T::DATA0 |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | DACData | DAC data |
Definition at line 1519 of file Nano100Series.h.
| __I uint32_t PWM_T::DATA0 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PWMx_DATAy15_0 | PWM Data Register |
| User can monitor PWMx_DATAy to know the current value in 16-bit down count counter. | ||
| [30:16] | PWMx_DATAy30_16 | PWM Data Register |
| User can monitor PWMx_DATAy to know the current value in 32-bit down count counter | ||
| Notes:This will be valid only for the corresponding cascade enable .bit is set | ||
| [31] | sync | Indicate That CNR Value Is Sync To PWM Counter |
| 0 = CNR value is sync to PWM counter. | ||
| 1 = CNR value is not sync to PWM counter. | ||
| Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel |
Definition at line 6828 of file Nano100Series.h.
| __IO uint32_t DAC_T::DATA1 |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | DACData | DAC data |
Definition at line 1582 of file Nano100Series.h.
| __I uint32_t PWM_T::DATA1 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PWMx_DATAy15_0 | PWM Data Register |
| User can monitor PWMx_DATAy to know the current value in 16-bit down count counter. | ||
| [30:16] | PWMx_DATAy30_16 | PWM Data Register |
| User can monitor PWMx_DATAy to know the current value in 32-bit down count counter | ||
| Notes:This will be valid only for the corresponding cascade enable .bit is set | ||
| [31] | sync | Indicate That CNR Value Is Sync To PWM Counter |
| 0 = CNR value is sync to PWM counter. | ||
| 1 = CNR value is not sync to PWM counter. | ||
| Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel |
Definition at line 6879 of file Nano100Series.h.
| __I uint32_t PWM_T::DATA2 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PWMx_DATAy15_0 | PWM Data Register |
| User can monitor PWMx_DATAy to know the current value in 16-bit down count counter. | ||
| [30:16] | PWMx_DATAy30_16 | PWM Data Register |
| User can monitor PWMx_DATAy to know the current value in 32-bit down count counter | ||
| Notes:This will be valid only for the corresponding cascade enable .bit is set | ||
| [31] | sync | Indicate That CNR Value Is Sync To PWM Counter |
| 0 = CNR value is sync to PWM counter. | ||
| 1 = CNR value is not sync to PWM counter. | ||
| Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel |
Definition at line 6930 of file Nano100Series.h.
| __I uint32_t PWM_T::DATA3 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PWMx_DATAy15_0 | PWM Data Register |
| User can monitor PWMx_DATAy to know the current value in 16-bit down count counter. | ||
| [30:16] | PWMx_DATAy30_16 | PWM Data Register |
| User can monitor PWMx_DATAy to know the current value in 32-bit down count counter | ||
| Notes:This will be valid only for the corresponding cascade enable .bit is set | ||
| [31] | sync | Indicate That CNR Value Is Sync To PWM Counter |
| 0 = CNR value is sync to PWM counter. | ||
| 1 = CNR value is not sync to PWM counter. | ||
| Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel |
Definition at line 6979 of file Nano100Series.h.
| __IO uint32_t GPIO_T::DBEN |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | DBEN | GPIO Port [X] Pin [N] Input Signal De-Bounce Enable |
| DBEN[n] used to enable the de-bounce function for each corresponding bit. | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. | ||
| DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt | ||
| 0 = The GPIO port [x] Pin [n] input signal de-bounce function is disabled. | ||
| 1 = The GPIO port [x] Pin [n] input signal de-bounce function is enabled. | ||
| The de-bounce function is valid for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note: For GPIOF_DBEN, bits [15:6] are reserved. |
Definition at line 3618 of file Nano100Series.h.
| __IO uint32_t GP_DB_T::DBNCECON |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PUEN | De-Bounce Sampling Cycle Selection |
| 0000 = Sample interrupt input once per 1 clock. | ||
| 0001 = Sample interrupt input once per 2 clock. | ||
| 0010 = Sample interrupt input once per 4 clock. | ||
| 0011 = Sample interrupt input once per 8 clock. | ||
| 0100 = Sample interrupt input once per 16 clock. | ||
| 0101 = Sample interrupt input once per 32 clock. | ||
| 0110 = Sample interrupt input once per 64 clock. | ||
| 0111 = Sample interrupt input once per 128 clock. | ||
| 1000 = Sample interrupt input once per 256 clock. | ||
| 1001 = Sample interrupt input once per 512 clock. | ||
| 1010 = Sample interrupt input once per 1024 clock. | ||
| 1011 = Sample interrupt input once per 2048 clock. | ||
| 1100 = Sample interrupt input once per 4096 clock. | ||
| 1101 = Sample interrupt input once per 8192 clock. | ||
| 1110 = Sample interrupt input once per 16384 clock. | ||
| 1111 = Sample interrupt input once per 32768 clock. | ||
| [4] | DBCLKSRC | De-Bounce Counter Clock Source Selection |
| 0 = De-bounce counter Clock Source is the HCLK. | ||
| 1 = De-bounce counter Clock Source is the internal 10 kHz clock. | ||
| [5] | DBCLK_ON | De-Bounce Clock Enable |
| This bit controls if the de-bounce clock is enabled. | ||
| However, if GPI/O pin's interrupt is enabled, the de-bounce clock will be enabled automatically no matter what the DBCLK_ON value is. | ||
| If CPU is in sleep mode, this bit didn't take effect. | ||
| And only the GPI/O pin with interrupt enable could get de-bounce clock. | ||
| 0 = De-bounce clock Disabled. | ||
| 1 = De-bounce clock Enabled. |
Definition at line 4013 of file Nano100Series.h.
| __I uint32_t FMC_T::DFBADR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | DFBA | Data Flash Base Address |
| This register indicates data flash start address. It is a read only register. | ||
| The data flash start address is defined by user. | ||
| Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0. |
Definition at line 1902 of file Nano100Series.h.
| __IO uint32_t LCD_T::DISPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CPUMP_EN | Charge Pump Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2:1] | BIAS_SEL | Bias Selection |
| 00 = Static. | ||
| 01 = 1/2 Bias. | ||
| 10 = 1/3 Bias. | ||
| 11 = Reserved. | ||
| [4] | IBRL_EN | Internal Bias Reference Ladder Enable |
| 0 = Bias reference ladder Disabled. | ||
| 1 = Bias reference ladder Enabled. | ||
| [6] | BV_SEL | Bias Voltage Type Selection |
| 0 = C-Type bias mode. Bias voltage source from internal bias generator. | ||
| 1 = R-Type bias mode. Bias voltage source from external bias generator. | ||
| Note: The external resistor ladder should be connected to the V1 pin, V2 pin, V3 pin and VSS. | ||
| The VLCD pin should also be connected to VDD. | ||
| [10:8] | CPUMP_VOL_SET | Charge Pump Voltage Selection |
| 000 = 2.7V. | ||
| 001 = 2.8V. | ||
| 010 = 2.9V. | ||
| 011 = 3.0V. | ||
| 100 = 3.1V. | ||
| 101 = 3.2V. | ||
| 110 = 3.3V. | ||
| 111 = 3.4V. | ||
| [13:11] | CPUMP_FREQ | Charge Pump Frequency Selection |
| 000 = LCDCLK. | ||
| 001 = LCDCLK/2. | ||
| 010 = LCDCLK/4. | ||
| 011 = LCDCLK/8. | ||
| 100 = LCDCLK/16. | ||
| 101 = LCDCLK/32. | ||
| 110 = LCDCLK/64. | ||
| 111 = LCDCLK/128. |
Definition at line 5147 of file Nano100Series.h.
| __IO uint32_t I2C_T::DIV |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CLK_DIV | I2C Clock Divider Control Register |
| The I2C clock rate bits: Data Baud Rate of I2C = PCLK /( 4 x ( CLK_DIV + 1)). | ||
| Note: the minimum value of CLK_DIV is 4. |
Definition at line 4304 of file Nano100Series.h.
| __IO uint32_t SPI_T::DMA |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TX_DMA_EN | Transmit PDMA Enable (PDMA Writes Data To SPI) |
| Set this bit to 1 will start the transmit PDMA process. | ||
| SPI controller will issue request to PDMA controller automatically. | ||
| If using PDMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. | ||
| The DMA controller inside SPI controller will set it automatically whenever necessary. | ||
| Note: | ||
| 1. Two transaction need minimal 18 APB clock + 8 SPI serial clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 serial clocks for level mode. | ||
| 2. If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period. | ||
| Hardware will clear this bit to 0 automatically after PDMA transfer done. If FIFO mode not release, it should be remove. | ||
| [1] | RX_DMA_EN | Receiving PDMA Enable(PDMA Reads SPI Data To Memory) |
| Set this bit to "1" will start the receive PDMA process. | ||
| SPI controller will issue request to PDMA controller automatically when there is data written into the received buffer or the status of RX_EMPTY status is set to 0 in FIFO mode. | ||
| If using the RX_PDMA mode to receive data but TX_DMA is disabled, the GO_BUSY bit shall be set by user. | ||
| Hardware will clear this bit to 0 automatically after PDMA transfer done. | ||
| In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI slave engine clock + 4 APB clock for edge mode and 9.5 SPI slave engine clock + 4 APB clock | ||
| [2] | PDMA_RST | PDMA Reset |
| It is used to reset the SPI PDMA function into default state. | ||
| 0 = After reset PDMA function or in normal operation. | ||
| 1 = Reset PDMA function. | ||
| Note: it is auto cleared to "0" after the reset function done. |
Definition at line 9526 of file Nano100Series.h.
| __IO uint32_t DMA_CRC_T::DMABCR |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CRC_DMABCR | CRC DMA Transfer Byte Count Register |
| This field indicates a 16-bit transfer byte count number of CRC DMA |
Definition at line 5645 of file Nano100Series.h.
| __I uint32_t DMA_CRC_T::DMACBCR |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CRC_DMACBCR | CRC DMA Current Byte Count Register (Read Only) |
| This field indicates the current remained byte count of CRC_DMA. | ||
| Note: CRC_RST will clear this register value. |
Definition at line 5674 of file Nano100Series.h.
| __I uint32_t DMA_CRC_T::DMACSAR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | CRC_DMACSAR | CRC DMA Current Source Address Register (Read Only) |
| This field indicates the source address where the CRC DMA transfer is just occurring. |
Definition at line 5659 of file Nano100Series.h.
| __IO uint32_t DMA_CRC_T::DMAIER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TABORT_IE | CRC DMA Read/Write Target Abort Interrupt Enable |
| 0 = Target abort interrupt generation Disabled during CRC DMA transfer. | ||
| 1 = Target abort interrupt generation Enabled during CRC DMA transfer. | ||
| [1] | BLKD_IE | CRC DMA Transfer Done Interrupt Enable |
| 0 = Interrupt generator Disabled during CRC DMA transfer done. | ||
| 1 = Interrupt generator Enabled during CRC DMA transfer done. |
Definition at line 5690 of file Nano100Series.h.
| __IO uint32_t DMA_CRC_T::DMAISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TABORT_IF | CRC DMA Read/Write Target Abort Interrupt Flag |
| 0 = No bus ERROR response received. | ||
| 1 = Bus ERROR response received. | ||
| Software can write 1 to clear this bit to zero | ||
| Note: The CRC_DMAISR [TABORT_IF] indicate bus master received ERROR response or not. | ||
| If bus master received ERROR response, it means that target abort is happened. | ||
| DMA will stop transfer and respond this event to software then go to IDLE state. | ||
| When target abort occurred, software must reset DMA, and then transfer those data again. | ||
| [1] | BLKD_IF | Block Transfer Done Interrupt Flag |
| This bit indicates that CRC DMA has finished all transfer. | ||
| 0 = Not finished yet. | ||
| 1 = Done. | ||
| Software can write 1 to clear this bit to zero |
Definition at line 5713 of file Nano100Series.h.
| __IO uint32_t DMA_CRC_T::DMASAR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | CRC_DMASAR | CRC DMA Transfer Source Address Register |
| This field indicates a 32-bit source address of CRC DMA. | ||
| Note : The source address must be word alignment |
Definition at line 5631 of file Nano100Series.h.
| __IO uint32_t GPIO_T::DMASK |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | DMASK | GPIO Port [X] Pin [N] Data Output Write Mask |
| These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. | ||
| When set the DMASK[n] to "1", the corresponding DOUT[n] bit is protected. | ||
| The write signal is masked, write data to the protect bit is ignored. | ||
| 0 = The corresponding GPIO_DOUT bit [n] can be updated. | ||
| 1 = The corresponding GPIO_DOUT bit [n] is protected. | ||
| Note: For GPIOF_DMASK, bits [15:6] are reserved. | ||
| Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. | ||
| If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. |
Definition at line 3586 of file Nano100Series.h.
| __IO uint32_t GPIO_T::DOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | DOUT | GPIO Port [X] Pin [N] Output Value |
| Each of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode | ||
| 0 = GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set. | ||
| 1 = GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set. | ||
| Note: For GPIOF_DOUT, bits [15:6] are reserved. |
Definition at line 3567 of file Nano100Series.h.
| __I uint32_t TIMER_T::DR |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | TDR | Timer Data Register |
| User can read this register for internal 24-bit timer up-counter value. |
Definition at line 9976 of file Nano100Series.h.
| __IO uint32_t DMA_GCR_T::DSSR0 |
| Bits | Field | Descriptions |
|---|---|---|
| [12:8] | CH1_SEL | Channel 1 Selection |
| This filed defines which peripheral is connected to PDMA channel 1. | ||
| Software can configure the peripheral by setting CH1_SEL. | ||
| 00000 = Connect to SPI0_TX. | ||
| 00001 = Connect to SPI1_TX. | ||
| 00010 = Connect to UART0_TX. | ||
| 00011 = Connect to UART1_TX. | ||
| 00100 = Connect to USB_TX. | ||
| 00101 = Connect to I2S_TX. | ||
| 00110 = Connect to DAC0_TX. | ||
| 00111 = Connect to DAC1_TX. | ||
| 01000 = Connect to SPI2_TX. | ||
| 01001 = Connect to TMR0. | ||
| 01010 = Connect to TMR1. | ||
| 01011 = Connect to TMR2. | ||
| 01100 = Connect to TMR3. | ||
| 10000 = Connect to SPI0_RX. | ||
| 10001 = Connect to SPI1_RX. | ||
| 10010 = Connect to UART0_RX. | ||
| 10011 = Connect to UART1_RX. | ||
| 10100 = Connect to USB_RX. | ||
| 10101 = Connect to I2S_RX. | ||
| 10110 = Connect to ADC. | ||
| 11000 = Connect to SPI2_RX. | ||
| 11001 = Connect to PWM0_CH0. | ||
| 11010 = Connect to PWM0_CH2. | ||
| 11011 = Connect to PWM1_CH0. | ||
| 11100 = Connect to PWM1_CH2. | ||
| [20:16] | CH2_SEL | Channel 2 Selection |
| This filed defines which peripheral is connected to PDMA channel 2. | ||
| Software can configure the peripheral setting by CH2_SEL. | ||
| The channel configuration is the same as CH1_SEL field. | ||
| Please refer to the explanation of CH1_SEL. | ||
| [28:24] | CH3_SEL | Channel 3 Selection |
| This filed defines which peripheral is connected to PDMA channel 3. | ||
| Software can configure the peripheral setting by CH3_SEL. | ||
| The channel configuration is the same as CH1_SEL field. | ||
| Please refer to the explanation of CH1_SEL. |
Definition at line 5843 of file Nano100Series.h.
| __IO uint32_t DMA_GCR_T::DSSR1 |
| Bits | Field | Descriptions |
|---|---|---|
| [4:0] | CH4_SEL | Channel 4 Selection |
| This filed defines which peripheral is connected to PDMA channel 4. | ||
| Software can configure the peripheral by setting CH4_SEL. | ||
| The channel configuration is the same as CH1_SEL field. | ||
| Please refer to the explanation of CH1_SEL. | ||
| [12:8] | CH5_SEL | Channel 5 Selection |
| This filed defines which peripheral is connected to PDMA channel 5. | ||
| Software can configure the peripheral setting by CH5_SEL. | ||
| The channel configuration is the same as CH1_SEL field. | ||
| Please refer to the explanation of CH1_SEL. | ||
| [20:16] | CH6_SEL | Channel 6 Selection |
| This filed defines which peripheral is connected to PDMA channel 6. | ||
| Software can configure the peripheral setting by CH6_SEL. | ||
| The channel configuration is the same as CH1_SEL field. | ||
| Please refer to the explanation of CH1_SEL. |
Definition at line 5868 of file Nano100Series.h.
| __IO uint32_t PWM_T::DUTY0 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CN | PWM Counter/Timer Loaded Value |
| CN determines the PWM period. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: | ||
| Any write to CN will take effect in next PWM cycle. | ||
| [31:16] | CM | PWM Comparator Register |
| CM determines the PWM duty. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depending on the selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: | ||
| Any write to CM will take effect in next PWM cycle. |
Definition at line 6809 of file Nano100Series.h.
| __IO uint32_t PWM_T::DUTY1 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CN | PWM Counter/Timer Loaded Value |
| CN determines the PWM period. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: | ||
| Any write to CN will take effect in next PWM cycle. | ||
| [31:16] | CM | PWM Comparator Register |
| CM determines the PWM duty. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depending on the selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: | ||
| Any write to CM will take effect in next PWM cycle. |
Definition at line 6860 of file Nano100Series.h.
| __IO uint32_t PWM_T::DUTY2 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CN | PWM Counter/Timer Loaded Value |
| CN determines the PWM period. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: | ||
| Any write to CN will take effect in next PWM cycle. | ||
| [31:16] | CM | PWM Comparator Register |
| CM determines the PWM duty. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depending on the selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: | ||
| Any write to CM will take effect in next PWM cycle. |
Definition at line 6911 of file Nano100Series.h.
| __IO uint32_t PWM_T::DUTY3 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CN | PWM Counter/Timer Loaded Value |
| CN determines the PWM period. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: Any write to CN will take effect in next PWM cycle. | ||
| [31:16] | CM | PWM Comparator Register |
| CM determines the PWM duty. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depending on the selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: Any write to CM will take effect in next PWM cycle. |
Definition at line 6960 of file Nano100Series.h.
| __IO uint32_t RTC_T::DWR |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | DWR | Day Of The Week Register |
| 000 = Sunday. | ||
| 001 = Monday. | ||
| 010 = Tuesday. | ||
| 011 = Wednesday. | ||
| 100 = Thursday. | ||
| 101 = Friday. | ||
| 110 = Saturday. |
Definition at line 7902 of file Nano100Series.h.
| __IO uint32_t EBI_T::EBICON |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ExtEN | EBI Enable |
| This bit is the functional enable bit for EBI. | ||
| 0 = EBI function is disabled. | ||
| 1 = EBI function is enabled. | ||
| [1] | ExtBW16 | EBI Data Width 16-Bit |
| This bit defines if the data bus is 8-bit or 16-bit. | ||
| 0 = EBI data width is 8-bit. | ||
| 1 = EBI data width is 16-bit. | ||
| [10:8] | MCLKDIV | External Output Clock Divider |
| The frequency of EBI output clock is controlled by MCLKDIV as shown in the following table. | ||
| 000 = HCLK/1. | ||
| 001 = HCLK/2. | ||
| 010 = HCLK/4. | ||
| 011 = HCLK/8. | ||
| 100 = HCLK/16. | ||
| 101 = HCLK/32. | ||
| 110 = Default. | ||
| 111 = Default. | ||
| Notice: Default value of output clock is HCLK/1 | ||
| [11] | MCLKEN | External Clock Enable |
| This bit control if EBI generates the clock to external device. | ||
| If external device is a synchronous device, it's necessary to set this bit high to enable EBI generating clock to external device. | ||
| If the external device is an asynchronous device, keep this bit low is recommended to save power consumption. | ||
| 0 = EBI Disabled to generate clock to external device. | ||
| 1 = EBI Enabled to generate clock to external device. | ||
| [18:16] | ExttALE | Expand Time Of ALE |
| The ALE width (tALE) to latch the address can be controlled by ExttALE. | ||
| tALE = (ExttALE+1)*MCLK. |
Definition at line 1718 of file Nano100Series.h.
| __IO uint32_t SC_T::EGTR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | EGT | Extended Guard Time |
| This field indicates the extended guard timer value. | ||
| Note: The counter is ETU based and the real extended guard time is EGT. |
Definition at line 8491 of file Nano100Series.h.
| USBD_EP_T USBD_T::EP[8] |
Definition at line 11126 of file Nano100Series.h.
| __I uint32_t USBD_T::EPSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [7] | OVERRUN | Overrun |
| It means the received data is over the maximum payload number or not. | ||
| 0 = No overrun. | ||
| 1 = Out Data more than the Max Payload in MXPLD register or the Setup Data more than 8 Bytes. | ||
| [11:8] | EPSTS0 | Endpoint 0 Bus Status |
| These bits are used to show the current status of this endpoint. | ||
| Definition is the same with EPSTS5(USB_EPSTS[27:24]). | ||
| [15:12] | EPSTS1 | Endpoint 1 Bus Status |
| These bits are used to show the current status of this endpoint. | ||
| Definition is the same with EPSTS5(USB_EPSTS[27:24]). | ||
| [19:16] | EPSTS2 | Endpoint 2 Bus Status |
| These bits are used to show the current status of this endpoint. | ||
| Definition is the same with EPSTS5(USB_EPSTS[27:24]). | ||
| [23:20] | EPSTS3 | Endpoint 3 Bus Status |
| These bits are used to show the current status of this endpoint. | ||
| Definition is the same with EPSTS5(USB_EPSTS[27:24]). | ||
| [27:24] | EPSTS4 | Endpoint 4 Bus Status |
| These bits are used to show the current status of this endpoint. | ||
| Definition is the same with EPSTS5(USB_EPSTS[27:24]). | ||
| [31:28] | EPSTS5 | Endpoint 5 Bus Status |
| These bits are used to show the current status of this endpoint. | ||
| 0000 = INACK. | ||
| 0001 = IN NAK (INTERNAL ONLY). | ||
| 0010 = OUT Packet Data0 ACK. | ||
| 0011 = Setup ACK | ||
| 0110 = OUT Packet Data1 ACK. | ||
| 0111 = Isochronous transfer end. |
Definition at line 11094 of file Nano100Series.h.
| __I uint32_t USBD_T::EPSTS2 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | EPSTS6 | Endpoint 6 Bus Status |
| These bits are used to show the current status of this endpoint. | ||
| Definition is the same with EPSTS5(USB_EPSTS[27:24]). | ||
| [6:4] | EPSTS7 | Endpoint 7 Bus Status |
| These bits are used to show the current status of this endpoint. | ||
| Definition is the same with EPSTS5(USB_EPSTS[27:24]). |
Definition at line 11123 of file Nano100Series.h.
| __IO uint32_t SC_T::ETUCR |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | ETU_RDIV | ETU Rate Divider |
| The field indicates the clock rate divider. | ||
| The real ETU is ETU_RDIV + 1. | ||
| Note1: Software can configure this field, but this field must be greater than 0x04. | ||
| Note2: Software can configure this field, but if the error rate is equal to 2%, this field must be greater than 0x040. | ||
| [15] | COMPEN_EN | Compensation Mode Enable |
| This bit enables clock compensation function. | ||
| When this bit enabled, hardware will alternate between n clock cycles and (n-1) clock cycles, where n is the value to be written into the ETU_RDIV register. | ||
| 0 = Compensation function Disabled. | ||
| 1 = Compensation function Enabled. |
Definition at line 8526 of file Nano100Series.h.
| __IO uint32_t EBI_T::EXTIME |
| Bits | Field | Descriptions |
|---|---|---|
| [4:0] | ExttACC | EBI Data Access Time |
| ExttACC define data access time (tACC). | ||
| tACC = (ExttACC +1) * MCLK. | ||
| [10:8] | ExttAHD | EBI Data Access Hold Time |
| ExttAHD define data access hold time (tAHD). | ||
| tAHD = (ExttAHD +1) * MCLK. | ||
| [15:12] | ExtIW2X | Idle State Cycle After Write |
| When write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero. | ||
| Idle state cycle = (ExtIW2X*MCLK). | ||
| [19:16] | ExtIR2W | Idle State Cycle Between Read-Write |
| When read action is finish and next action is going to write, idle state is inserted and nCS return to high if ExtIR2W is not zero. | ||
| Idle state cycle = (ExtIR2W*MCLK). | ||
| [27:24] | ExtIR2R | Idle State Cycle Between Read-Read |
| When read action is finish and next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero. | ||
| Idle state cycle = (ExtIR2R*MCLK). |
Definition at line 1743 of file Nano100Series.h.
| __IO uint32_t USBD_T::FADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [6:0] | FADDR | USB device's function address |
Definition at line 11057 of file Nano100Series.h.
| __IO uint32_t LCD_T::FCR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FCEN | LCD Frame Counter Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | FCINTEN | LCD Frame Counter Interrupt Enable |
| 0 = Frame counter interrupt Disabled. | ||
| 1 = Frame counter interrupt Enabled. | ||
| [3:2] | PRESCL | Frame Counter Pre-Scaler Value |
| 00 = CLKframe/1. | ||
| 01 = CLKframe/2. | ||
| 10 = CLKframe/4. | ||
| 11 = CLKframe/8. | ||
| [9:4] | FCV | Frame Counter Top Value |
| These 6 bits contain the top value of the Frame counter. |
Definition at line 5350 of file Nano100Series.h.
| __IO uint32_t RTC_T::FCR |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | FRACTION | Fraction Part |
| Formula = (fraction part of detected value) x 64. | ||
| Note: Digit in FCR must be expressed as hexadecimal number. | ||
| [11:8] | INTEGER | Integer Part |
| 0000 = 32761. | ||
| 0001 = 32762. | ||
| 0010 = 32763. | ||
| 0011 = 32764. | ||
| 0100 = 32765. | ||
| 0101 = 32766. | ||
| 0110 = 32767. | ||
| 0111 = 32768. | ||
| 1000 = 32769. | ||
| 1001 = 32770. | ||
| 1010 = 32771. | ||
| 1011 = 32772. | ||
| 1100 = 32773. | ||
| 1101 = 32774. | ||
| 1110 = 32775. | ||
| 1111 = 32776. |
Definition at line 7838 of file Nano100Series.h.
| __IO uint32_t LCD_T::FCSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FCSTS | LCD Frame Counter Status |
| 0 = Frame counter value does not reach FCV (Frame Count TOP value). | ||
| 1 = Frame counter value reaches FCV (Frame Count TOP value). | ||
| If the FCINTEN is s enabled, the frame counter overflow Interrupt is generated. | ||
| [1] | PDSTS | Power-Down Interrupt Status |
| 0 = Inform system manager that LCD controller is not ready to enter power-down state until this bit becomes 1 if power down is set and one frame is not executed completely. | ||
| 1 = Inform system manager that LCD controller is ready to enter power-down state if power down is set and one frame is executed completely |
Definition at line 5367 of file Nano100Series.h.
| __IO uint32_t SPI_T::FFCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RX_CLR | Receiving FIFO Counter Clear |
| This bit is used to clear the receiver counter in FIFO Mode. | ||
| This bit can be written "1" to clear the receiver counter and this bit will be cleared to "0" automatically after clearing receiving counter. | ||
| After the clear operation, the flag of RX_EMPTY in SPI_STATUS[0] will be set to "1". | ||
| [1] | TX_CLR | Transmitting FIFO Counter Clear |
| This bit is used to clear the transmit counter in FIFO Mode. | ||
| This bit can be written "1" to clear the transmitting counter and this bit will be cleared to "0" automatically after clearing transmitting counter. | ||
| After the clear operation, the flag of TX_EMPTY in SPI_STATUS[2] will be set to "1". | ||
| [2] | RXINT_EN | RX Threshold Interrupt Enable |
| 0 = Rx threshold interrupt Disabled. | ||
| 1 = RX threshold interrupt Enable. | ||
| [3] | TXINT_EN | TX Threshold Interrupt Enable |
| 0 = Tx threshold interrupt Disabled. | ||
| 1 = TX threshold interrupt Enable. | ||
| [4] | RXOVINT_EN | RX FIFO Over Run Interrupt Enable |
| 0 = RX FIFO over run interrupt Disabled. | ||
| 1 = RX FIFO over run interrupt Enabled. | ||
| [7] | TIMEOUT_EN | RX Read Timeout Function Enable |
| 0 = RX read Timeout function Disabled. | ||
| 1 = RX read Timeout function Enabled. | ||
| [26:24] | RX_THRESHOLD | Received FIFO Threshold |
| 3-bits register, value from 0 ~7. | ||
| If RX valid data counts large than RXTHRESHOLD, RXINT_STS will set to 1, else RXINT_STS will set to 0. | ||
| [30:28] | TX_THRESHOLD | Transmit FIFO Threshold |
| 3-bit register, value from 0 ~7. | ||
| If TX valid data counts small or equal than TXTHRESHOLD, TXINT_STS will set to 1, else TXINT_STS will set to 0 |
Definition at line 9562 of file Nano100Series.h.
| __IO uint32_t CLK_T::FRQDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | FSEL | Divider Output Frequency Selection Bits |
| The formula of output frequency is | ||
| Fout = Fin/2^(N+1),. | ||
| Where Fin is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL[3:0]. | ||
| [4] | FDIV_EN | Frequency Divider Enable Bit |
| 0 = Frequency Divider Disabled. | ||
| 1 = Frequency Divider Enabled. |
Definition at line 1146 of file Nano100Series.h.
| __IO uint32_t UART_T::FSR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RX_OVER_F | RX Overflow Error Status Flag (Read Only) |
| This bit is set when RX-FIFO overflow. | ||
| If the number of bytes of received data is greater than RX-FIFO (UART_RBR) size, 16 bytes of UART0/UART1, this bit will be set. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [1] | RX_EMPTY_F | Receiver FIFO Empty (Read Only) |
| This bit initiate RX-FIFO empty or not. | ||
| When the last byte of RX-FIFO has been read by CPU, hardware sets this bit high. | ||
| It will be cleared when UART receives any new data. | ||
| [2] | RX_FULL_F | Receiver FIFO Full (Read Only) |
| This bit initiates RX-FIFO full or not. | ||
| This bit is set when RX_POINTER_F is equal to 16, otherwise is cleared by hardware. | ||
| [4] | PE_F | Parity Error State Status Flag (Read Only) |
| This bit is set to logic "1" whenever the received character does not have a valid "parity bit", and it is reset whenever the CPU writes "1" to this bit. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [5] | FE_F | Framing Error Status Flag (Read Only) |
| This bit is set to logic "1" whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic "0"), and it is reset whenever the CPU writes "1" to this bit. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [6] | BI_F | Break Status Flag (Read Only) |
| This bit is set to a logic "1" whenever the received data input(RX) is held in the "spacing state" (logic "0") for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and it is reset whenever the CPU writes "1" to this bit. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [8] | TX_OVER_F | TX Overflow Error Interrupt Status Flag (Read Only) |
| If TX-FIFO (UART_THR) is full, an additional write to UART_THR will cause this bit to logic "1". | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [9] | TX_EMPTY_F | Transmitter FIFO Empty (Read Only) |
| This bit indicates TX-FIFO empty or not. | ||
| When the last byte of TX-FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. | ||
| It will be cleared when writing data into THR (TX-FIFO not empty). | ||
| [10] | TX_FULL_F | Transmitter FIFO Full (Read Only) |
| This bit indicates TX-FIFO full or not. | ||
| This bit is set when TX_POINTER_F is equal to 16, otherwise is cleared by hardware. | ||
| [11] | TE_F | Transmitter Empty Status Flag (Read Only) |
| Bit is set by hardware when TX is inactive. (TX shift register does not have data) | ||
| Bit is cleared automatically when TX-FIFO is transfer data to TX shift register or TX is empty but the transfer does not finish. | ||
| [20:16] | RX_POINTER_F | RX-FIFO Pointer (Read Only) |
| This field indicates the RX-FIFO Buffer Pointer. | ||
| When UART receives one byte from external device, RX_POINTER_F increases one. | ||
| When one byte of RX-FIFO is read by CPU, RX_POINTER_F decreases one. | ||
| [28:24] | TX_POINTER_F | TX-FIFO Pointer (Read Only) |
| This field indicates the TX-FIFO Buffer Pointer. | ||
| When CPU writes one byte data into UART_THR, TX_POINTER_F increases one. | ||
| When one byte of TX-FIFO is transferred to Transmitter Shift Register, TX_POINTER_F decreases one. |
Definition at line 10421 of file Nano100Series.h.
| __IO uint32_t UART_T::FUN_SEL |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | FUN_SEL | Function Select Enable |
| 00 = UART function mode. | ||
| 01 = LIN function mode. | ||
| 10 = IrDA Function. | ||
| 11 = RS-485 Function. |
Definition at line 10577 of file Nano100Series.h.
| __IO uint32_t DMA_GCR_T::GCRCSR |
| Bits | Field | Descriptions |
|---|---|---|
| [8] | CLK0_EN | DMA Controller Channel 0 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [9] | CLK1_EN | DMA Controller Channel 1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [10] | CLK2_EN | DMA Controller Channel 2 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [11] | CLK3_EN | DMA Controller Channel 3 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [12] | CLK4_EN | DMA Controller Channel 4 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [13] | CLK5_EN | DMA Controller Channel 5 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [14] | CLK6_EN | DMA Controller Channel 6 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [24] | CRC_CLK_EN | CRC Controller Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. |
Definition at line 5795 of file Nano100Series.h.
| __I uint32_t DMA_GCR_T::GCRISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | INTR0 | Interrupt Pin Status Of Channel 0 (Read Only) |
| This bit is the Interrupt pin status of DMA channel0. | ||
| Note: This bit is read only | ||
| [1] | INTR1 | Interrupt Pin Status Of Channel 1 (Read Only) |
| This bit is the Interrupt pin status of DMA channel1. | ||
| Note: This bit is read only | ||
| [2] | INTR2 | Interrupt Pin Status Of Channel 2 (Read Only) |
| This bit is the Interrupt pin status of DMA channel2. | ||
| Note: This bit is read only | ||
| [3] | INTR3 | Interrupt Pin Status Of Channel 3 (Read Only) |
| This bit is the Interrupt pin status of DMA channel3. | ||
| Note: This bit is read only | ||
| [4] | INTR4 | Interrupt Pin Status Of Channel 4 (Read Only) |
| This bit is the Interrupt pin status of DMA channel4. | ||
| Note: This bit is read only | ||
| [5] | INTR5 | Interrupt Pin Status Of Channel 5 (Read Only) |
| This bit is the Interrupt pin status of DMA channel4. | ||
| Note: This bit is read only | ||
| [6] | INTR6 | Interrupt Pin Status Of Channel 6 (Read Only) |
| This bit is the Interrupt pin status of DMA channel4. | ||
| Note: This bit is read only | ||
| [16] | CRC_INTR | Interrupt Pin Status Of CRC Controller |
| This bit is the Interrupt status of CRC controller | ||
| Note: This bit is read only |
Definition at line 5902 of file Nano100Series.h.
| __IO uint32_t GPIO_T::IER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FIER0 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [1] | FIER1 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [2] | FIER2 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [3] | FIER3 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [4] | FIER4 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [5] | FIER5 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [6] | FIER6 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [7] | FIER7 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [8] | FIER8 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [9] | FIER9 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [10] | FIER10 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [11] | FIER11 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [12] | FIER12 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [13] | FIER13 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [14] | FIER14 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [15] | FIER15 | GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low |
| FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the FIER[n] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[n] state at level "low" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[n] state change from "high-to-low" will generate the interrupt. | ||
| 1 = PIN[n] state low-level or high-to-low change interrupt Enabled. | ||
| 0 = PIN[n] state low-level or high-to-low change interrupt Disabled. | ||
| Note: For GPIOF_IER, bits [15:6] are reserved. | ||
| [16] | RIER0 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [17] | RIER1 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [18] | RIER2 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [19] | RIER3 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [20] | RIER4 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [21] | RIER5 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [22] | RIER6 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [23] | RIER7 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [24] | RIER8 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [25] | RIER9 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [26] | RIER10 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [27] | RIER11 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [28] | RIER12 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [29] | RIER13 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [30] | RIER14 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. | ||
| [31] | RIER15 | GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High |
| RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. | ||
| Set bit "1" also enable the pin wake-up function. | ||
| When set the RIER[x] bit "1": | ||
| If the interrupt is level mode trigger, the input PIN[x] state at level "high" will generate the interrupt. | ||
| If the interrupt is edge mode trigger, the input PIN[x] state change from "low-to-high" will generate the interrupt. | ||
| 1 = PIN[x] level-high or low-to-high interrupt Enabled. | ||
| 0 = PIN[x] level-high or low-to-high interrupt Disabled. | ||
| Note: For GPIOF_IE, bits [31:22] are reserved. |
Definition at line 3937 of file Nano100Series.h.
| __IO uint32_t PDMA_T::IER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TABORT_IE | PDMA Read/Write Target Abort Interrupt Enable |
| 0 = Target abort interrupt generation Disabled during PDMA transfer. | ||
| 1 = Target abort interrupt generation Enabled during PDMA transfer. | ||
| [1] | TD_IE | PDMA Transfer Done Interrupt Enable |
| 0 = Interrupt generator Disabled when PDMA transfer is done. | ||
| 1 = Interrupt generator Enabled when PDMA transfer is done. | ||
| [5:2] | WRA_BCR_IE | Wrap Around Byte Count Interrupt Enable |
| 0001 = Interrupt enable of PDMA_CBCR equals 0 | ||
| 0100 = Interrupt enable of PDMA_CBCR equals 1/2 PDMA_BCR. | ||
| [6] | TO_IE | Time-Out Interrupt Enable |
| 0 = Time-out interrupt Disabled. | ||
| 1 = Time-out interrupt Enabled. |
Definition at line 6061 of file Nano100Series.h.
| __IO uint32_t VDMA_T::IER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TABORT_IE | VDMA Read/Write Target Abort Interrupt Enable |
| 0 = Disabled target abort interrupt generation during VDMA transfer. | ||
| 1 = Enabled target abort interrupt generation during VDMA transfer. | ||
| [1] | TD_IE | VDMA Transfer Done Interrupt Enable |
| 0 = Disabled interrupt generator during VDMA transfer done. | ||
| 1 = Enabled interrupt generator during VDMA transfer done. |
Definition at line 6239 of file Nano100Series.h.
| __IO uint32_t SC_T::IER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDA_IE | Receive Data Reach Interrupt Enable |
| This field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable. | ||
| 0 = INT_RDR Disabled. | ||
| 1 = INT_RDR Enabled. | ||
| [1] | TBE_IE | Transmit Buffer Empty Interrupt Enable |
| This field is used for transmit buffer empty interrupt enable. | ||
| 0 = INT_THRE Disabled. | ||
| 1 = INT_THRE Enabled. | ||
| [2] | TERR_IE | Transfer Error Interrupt Enable |
| This field is used for transfer error interrupt enable. | ||
| The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F), receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY). | ||
| 0 = INT_TERR Disabled. | ||
| 1 = INT_TERR Enabled. | ||
| [3] | TMR0_IE | Timer0 Interrupt Enable |
| This field is used for TMR0 interrupt enable. | ||
| 0 = INT_TMR0 Disabled. | ||
| 1 = INT_TMR0 Enabled. | ||
| [4] | TMR1_IE | Timer1 Interrupt Enable |
| This field is used for TMR1 interrupt enable. | ||
| 0 = INT_TMR1 Disabled. | ||
| 1 = INT_TMR1 Enabled. | ||
| [5] | TMR2_IE | Timer2 Interrupt Enable |
| This field is used for TMR2 interrupt enable. | ||
| 0 = INT_TMR2 Disabled. | ||
| 1 = INT_TMR2 Enabled. | ||
| [6] | BGT_IE | Block Guard Time Interrupt Enable |
| This field is used for block guard time interrupt enable. | ||
| 0 = INT_BGT Disabled. | ||
| 1 = INT_BGT Enabled. | ||
| [7] | CD_IE | Card Detect Interrupt Enable |
| This field is used for card detect interrupt enable. | ||
| The card detect status register is SC_PINCSR [CD_CH] and SC_PINCSR[CD_CL]. | ||
| 0 = INT_CD Disabled. | ||
| 1 = INT_CD Enabled. | ||
| [8] | INIT_IE | Initial End Interrupt Enable |
| This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable. | ||
| 0 = INT_INIT Disabled. | ||
| 1 = INT_INIT Enabled. | ||
| [9] | RTMR_IE | Receiver Buffer Time-Out Interrupt Enable |
| This field is used for receiver buffer time-out interrupt enable. | ||
| 0 = INT_RTMR Disabled. | ||
| 1 = INT_RTMR Enabled. | ||
| [10] | ACON_ERR_IE | Auto Convention Error Interrupt Enable |
| This field is used for auto convention error interrupt enable. | ||
| 0 = INT_ACON_ERR Disabled. | ||
| 1 = INT_ACON_ERR Enabled. |
Definition at line 8582 of file Nano100Series.h.
| __IO uint32_t TIMER_T::IER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TMR_IE | Timer Interrupt Enable |
| 0 = Timer Interrupt Disabled. | ||
| 1 = Timer Interrupt Enabled. | ||
| Note: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR. | ||
| [1] | TCAP_IE | Timer Capture Function Interrupt Enable |
| 0 = Timer External Pin Function Interrupt Disabled. | ||
| 1 = Timer External Pin Function Interrupt Enabled. | ||
| Note: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN is set and the transition of external pin matches the TCAP_EDGE setting |
Definition at line 9933 of file Nano100Series.h.
| __IO uint32_t UART_T::IER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDA_IE | Receive Data Available Interrupt Enable |
| 0 = INT_RDA Masked off. | ||
| 1 = INT_RDA Enabled. | ||
| [1] | THRE_IE | Transmit Holding Register Empty Interrupt Enable |
| 0 = INT_THRE Masked off. | ||
| 1 = INT_THRE Enabled. | ||
| [2] | RLS_IE | Receive Line Status Interrupt Enable |
| 0 = INT_RLS Masked off. | ||
| 1 = INT_RLS Enabled. | ||
| [3] | MODEM_IE | Modem Status Interrupt Enable |
| 0 = INT_MOS Masked off. | ||
| 1 = INT_MOS Enabled. | ||
| [4] | RTO_IE | RX Time-Out Interrupt Enable |
| 0 = INT_TOUT Masked off. | ||
| 1 = INT_TOUT Enabled. | ||
| [5] | BUF_ERR_IE | Buffer Error Interrupt Enable |
| 0 = INT_BUT_ERR Masked off. | ||
| 1 = INT_BUF_ERR Enabled. | ||
| [6] | WAKE_IE | Wake-Up Interrupt Enable |
| 0 = INT_WAKE Masked off. | ||
| 1 = INT_WAKE Enabled. | ||
| [7] | ABAUD_IE | Auto-Baud Rate Interrupt Enable |
| 0 = INT_ABAUD Masked off. | ||
| 1 = INT_ABAUD Enabled. | ||
| [8] | LIN_IE | LIN Interrupt Enable |
| 0 = INT_LIN Masked off. | ||
| 1 = INT_LIN Enabled. |
Definition at line 10270 of file Nano100Series.h.
| __IO uint32_t WDT_T::IER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WDT_IE | Watchdog Timer Interrupt Enable |
| 0 = Watchdog timer interrupt Disabled. | ||
| 1 = Watchdog timer interrupt Enabled. |
Definition at line 11388 of file Nano100Series.h.
| __IO uint32_t WWDT_T::IER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WWDTIE | WWDT Interrupt Enable |
| Setting this bit will enable the Watchdog timer interrupt function. | ||
| 0 = Watchdog timer interrupt function Disabled. | ||
| 1 = Watchdog timer interrupt function Enabled. |
Definition at line 11522 of file Nano100Series.h.
| __IO uint32_t GPIO_T::IMD |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | IMD | GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control |
| IMD[n] used to control the interrupt is by level trigger or by edge trigger. | ||
| If the interrupt is by edge trigger, the trigger source is control de-bounce. | ||
| If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt. | ||
| 0 = Edge trigger interrupt. | ||
| 1 = Level trigger interrupt. | ||
| If set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. | ||
| If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur. | ||
| The de-bounce function is valid for edge triggered interrupt. | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note: For GPIOF_IMD, bits [15:6] are reserved. |
Definition at line 3639 of file Nano100Series.h.
| __IO uint32_t RTC_T::INIR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ACTIVE | RTC Active Status (Read Only) |
| 0 = RTC is at reset state. | ||
| 1 = RTC is at normal active state. | ||
| [31:1] | INIR | RTC Initiation (Write Only) |
| When RTC block is powered on, RTC is at reset state. | ||
| User has to write a number (0x a5eb1357) to INIR to make RTC leaving reset state. | ||
| Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently. | ||
| The INIR is a write-only field and read value will be always "0". |
Definition at line 7792 of file Nano100Series.h.
| __IO uint32_t SYS_T::Int_VREFCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BGP_EN | Band-Gap Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Band-gap is the reference voltage of internal reference voltage. | ||
| User must enable band-gap if want to enable internal 1.8V or 2.5V reference voltage. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | REG_EN | Regulator Enable |
| Enable internal 1.8V or 2.5V reference voltage. | ||
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2] | SEL25 | Regulator Output Voltage Selection |
| Select internal reference voltage level. | ||
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = 1.8V. | ||
| 1 = 2.5V. | ||
| [3] | EXT_MODE | Regulator External Mode |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Users can output regulator output voltage in VREF pin if EXT_MODE is high. | ||
| 0 = No connection with external VREF pin. | ||
| 1 = Connect to external VREF pin. | ||
| Connect a 1uF to 10uF capacitor to AVSS will let internal voltage reference be more stable. |
Definition at line 2838 of file Nano100Series.h.
| __IO uint32_t I2S_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXUDFIE | Receiving FIFO Underflow Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and receiving FIFO underflow flag is set to "1". | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [1] | RXOVFIE | Receiving FIFO Overflow Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and receiving FIFO overflow flag is set to "1" | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [2] | RXTHIE | Receiving FIFO Threshold Level Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and data words in receiving FIFO is less than RXTH[2:0]. | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [8] | TXUDFIE | Transmitting FIFO Underflow Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and transmitting FIFO underflow flag is set to "1". | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [9] | TXOVFIE | Transmitting FIFO Overflow Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and transmitting FIFO overflow flag is set to "1" | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [10] | TXTHIE | Transmitting FIFO Threshold Level Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and data words in transmitting FIFO is less than TXTH[2:0]. | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [11] | RZCIE | Right Channel Zero Cross Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and right channel is zero crossing. | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [12] | LZCIE | Left Channel Zero Cross Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and left channel is zero crossing. | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. |
Definition at line 4685 of file Nano100Series.h.
| __IO uint32_t PWM_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TMIE0 | PWM Timer 0 Interrupt Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | TMIE1 | PWM Timer 1 Interrupt Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2] | TMIE2 | PWM Timer 2 Interrupt Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [3] | TMIE3 | PWM Timer 3 Interrupt Enable |
| 0 = Disabled. | ||
| 1 = Enabled. |
Definition at line 6713 of file Nano100Series.h.
| __IO uint32_t USBD_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUSEVT_IE | Bus Event Interrupt Enable |
| 0 = BUS event interrupt Disabled. | ||
| 1 = BUS event interrupt Enabled. | ||
| [1] | USBEVT_IE | USB Event Interrupt Enable |
| 0 = USB event interrupt Disabled. | ||
| 1 = USB event interrupt Enabled. | ||
| [2] | FLDET_IE | Floating Detect Interrupt Enable |
| 0 = Floating detect Interrupt Disabled. | ||
| 1 = Floating detect Interrupt Enabled. | ||
| [3] | WAKEUP_IE | USB Wake-Up Interrupt Enable |
| 0 = Wake-up Interrupt Disabled. | ||
| 1 = Wake-up Interrupt Enabled. |
Definition at line 10993 of file Nano100Series.h.
| __IO uint32_t I2C_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | INTSTS | I2C STATUS's Interrupt Status |
| When a new state is present in the I2CSTATUS register, this bit will be set automatically, and if INTEN bit is set, the I2C interrupt is requested. | ||
| Software can write 1 to cleat this bit. | ||
| [1] | TIF | Time-Out Status |
| 0 = No Time-out flag. Software can cleat this flag. | ||
| 1 = Time-Out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set. |
Definition at line 4269 of file Nano100Series.h.
| __IO uint32_t PWM_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TMINT0 | PWM Timer 0 Interrupt Flag |
| Flag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it. | ||
| [1] | TMINT1 | PWM Timer 1 Interrupt Flag |
| Flag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it. | ||
| [2] | TMINT2 | PWM Timer 2 Interrupt Flag |
| Flag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it. | ||
| [3] | TMINT3 | PWM Timer 3 Interrupt Flag |
| Flag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it. | ||
| [4] | Duty0Syncflag | Duty0 Synchronize Flag |
| 0 = Duty0 has been synchronized to ECLK domain. | ||
| 1 = Duty0 is synchronizing to ECLK domain. | ||
| Note: software should check this flag when writing duty0, if this flag is set, and user ignore this flag and change duty0, the corresponding CNR and CMR may be wrong for one duty cycle | ||
| [5] | Duty1Syncflag | Duty1 Synchronize Flag |
| 0 = Duty1 has been synchronized to ECLK domain. | ||
| 1 = Duty1 is synchronizing to ECLK domain. | ||
| Note: software should check this flag when writing duty1, if this flag is set, and user ignore this flag and change duty1, the corresponding CNR and CMR may be wrong for one duty cycle | ||
| [6] | Duty2Syncflag | Duty2 Synchronize Flag |
| 0 = Duty2 has been synchronized to ECLK domain. | ||
| 1 = Duty2 is synchronizing to ECLK domain. | ||
| Note: software should check this flag when writing duty2, if this flag is set, and user ignore this flag and change duty2, the corresponding CNR and CMR may be wrong for one duty cycle | ||
| [7] | Duty3Syncflag | Duty3 Synchronize Flag |
| 0 = Duty3 has been synchronized to ECLK domain. | ||
| 1 = Duty3 is synchronizing to ECLK domain. | ||
| Note: software should check this flag when writing duty3, if this flag is set, and user ignore this flag and change duty3, the corresponding CNR and CMR may be wrong for one duty cycle | ||
| [8] | PresSyncFlag | Prescale Synchronize Flag |
| 0 = Prescale has been synchronized to ECLK domain. | ||
| 1 = Prescale is synchronizing to ECLK domain. | ||
| Note: software should check this flag when writing Prescale, if this flag is set, and user ignore this flag and change Prescale, the Prescale may be wrong for one prescale cycle |
Definition at line 6751 of file Nano100Series.h.
| __IO uint32_t USBD_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUS_STS | BUS Interrupt Status |
| The BUS event means there is bus suspense or bus resume in the bus. | ||
| This bit is used to indicate that there is one of events in the bus. | ||
| 0 = No BUS event is occurred. | ||
| 1 = BUS event occurred; check USB_BUSSTS [3:0] to know which kind of bus event was occurred, cleared by write "1" to USB_INTSTS [0]. | ||
| [1] | USB_STS | USB Interrupt Status |
| The USB event means that there is Setup Token, IN token, OUT ACK, ISO IN, or ISO OUT event in the bus. | ||
| This bit is used to indicate that there is one of events in the bus. | ||
| 0 = No USB event is occurred. | ||
| 1 = USB event occurred, check EPSTS0~7[3:0] in USB_EPSTS [31:8] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [1] or USB_INTSTS[31] or EPEVT0~7. | ||
| [2] | FLD_STS | Floating Interrupt Status |
| 0 = There is not attached event in the USB. | ||
| 1 = There is attached event in the USB and it is cleared by write "1" to USB_INTSTS [2]. | ||
| [3] | WKEUP_STS | Wake-Up Interrupt Status |
| 0 = No wake-up event is occurred. | ||
| 1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS [3]. | ||
| [16] | EPEVT0 | USB Event Status On EP0 |
| 0 = No event occurred in Endpoint 0. | ||
| 1 = USB event occurred on Endpoint 0, check USB_EPSTS[11:8] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [16] or USB_INTSTS [1]. | ||
| [17] | EPEVT1 | USB Event Status On EP1 |
| 0 = No event occurred in Endpoint 1. | ||
| 1 = USB event occurred on Endpoint 1, check USB_EPSTS[15:12] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [17] or USB_INTSTS [1]. | ||
| [18] | EPEVT2 | USB Event Status On EP2 |
| 0 = No event occurred in Endpoint 2. | ||
| 1 = USB event occurred on Endpoint 2, check USB_EPSTS[19:16] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [18] or USB_INTSTS [1]. | ||
| [19] | EPEVT3 | USB Event Status On EP3 |
| 0 = No event occurred in Endpoint 3. | ||
| 1 = USB event occurred on Endpoint 3, check USB_EPSTS[23:20] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [19] or USB_INTSTS [1]. | ||
| [20] | EPEVT4 | USB Event Status On EP4 |
| 0 = No event occurred in Endpoint 4. | ||
| 1 = USB event occurred on Endpoint 4, check USB_EPSTS[27:24] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [20] or USB_INTSTS [1]. | ||
| [21] | EPEVT5 | USB Event Status On EP5 |
| 0 = No event occurred in Endpoint 5. | ||
| 1 = USB event occurred on Endpoint 5, check USB_EPSTS[31:28] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [21] or USB_INTSTS [1]. | ||
| [22] | EPEVT6 | USB Event Status On EP6 |
| 0 = No event occurred in Endpoint 6. | ||
| 1 = USB event occurred on Endpoint 6, check USB_EPSTS2[2:0] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [22] or USB_INTSTS [1]. | ||
| [23] | EPEVT7 | USB Event Status On EP7 |
| 0 = No event occurred in Endpoint 7. | ||
| 1 = USB event occurred on Endpoint 7, check USB_EPSTS2[6:4] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [23] or USB_INTSTS [1]. | ||
| [31] | SETUP | Setup Event Status |
| 0 = No Setup event. | ||
| 1 = Setup event occurred, cleared by write "1" to USB_INTSTS[31]. |
Definition at line 11046 of file Nano100Series.h.
| __IO uint32_t SYS_T::IPRST_CTL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CHIP_RST | CHIP One Shot Reset |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Setting this bit will reset the whole chip, including CPU kernel and all peripherals like power-on reset and this bit will automatically return to "0" after the 2 clock cycles. | ||
| The chip setting from flash will be also reloaded when chip one shot reset. | ||
| 0 = Normal. | ||
| 1 = Reset CHIP. | ||
| Note: In the following conditions, chip setting from flash will be reloaded. | ||
| Power-on Reset | ||
| Brown-out-Detected Reset | ||
| Low level on the /RESET pin | ||
| Set IPRST_CTL1[CHIP_RST] | ||
| [1] | CPU_RST | CPU Kernel One Shot Reset |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to "0" after the 2 clock cycles | ||
| 0 = Normal. | ||
| 1 = Reset CPU. | ||
| [2] | DMA_RST | DMA Controller Reset |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Set this bit "1" will generate a reset signal to the DMA. | ||
| SW needs to set this bit to low to release reset signal. | ||
| 0 = Normal operation. | ||
| 1 = DMA IP reset. | ||
| [3] | EBI_RST | EBI Controller Reset |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Set this bit "1" will generate a reset signal to the EBI. | ||
| SW needs to set this bit to low to release reset signal. | ||
| 0 = Normal operation. | ||
| 1 = EBI IP reset. |
Definition at line 2080 of file Nano100Series.h.
| __IO uint32_t SYS_T::IPRST_CTL2 |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | GPIO_RST | GPIO Controller Reset |
| 0 = GPIO normal operation. | ||
| 1 = GPIO reset. | ||
| [2] | TMR0_RST | Timer0 Controller Reset |
| 0 = Timer0 normal operation. | ||
| 1 = Timer0 reset. | ||
| [3] | TMR1_RST | Timer1 Controller Reset |
| 0 = Timer1 normal operation. | ||
| 1 = Timer1 block reset. | ||
| [4] | TMR2_RST | Timer2 Controller Reset |
| 0 = Timer2 normal operation. | ||
| 1 = Timer2 block reset. | ||
| [5] | TMR3_RST | Timer3 Controller Reset |
| 0 = Timer3 normal operation. | ||
| 1 = Timer3 block reset. | ||
| [7] | SC2_RST | SmartCard 2 Controller Reset |
| 0 = SmartCard 2 block normal operation. | ||
| 1 = SmartCard 2 block reset. | ||
| [8] | I2C0_RST | I2C0 Controller Reset |
| 0 = I2C0 normal operation. | ||
| 1 = I2C0 block reset. | ||
| [9] | I2C1_RST | I2C1 Controller Reset |
| 0 = I2C1 block normal operation. | ||
| 1 = I2C1 block reset. | ||
| [12] | SPI0_RST | SPI0 Controller Reset |
| 0 = SPI0 block normal operation. | ||
| 1 = SPI0 block reset. | ||
| [13] | SPI1_RST | SPI1 Controller Reset |
| 0 = SPI1 normal operation. | ||
| 1 = SPI1 block reset. | ||
| [14] | SPI2_RST | SPI2 Controller Reset |
| 0 = SPI2 normal operation. | ||
| 1 = SPI2 block reset. | ||
| [16] | UART0_RST | UART0 Controller Reset |
| 0 = UART0 normal operation. | ||
| 1 = UART0 block reset. | ||
| [17] | UART1_RST | UART1 Controller Reset |
| 0 = UART1 normal operation. | ||
| 1 = UART1 block reset. | ||
| [20] | PWM0_RST | PWM0 Controller Reset |
| 0 = PWM0 block normal operation. | ||
| 1 = PWM0 block reset. | ||
| [21] | PWM1_RST | PWM1 Controller Reset |
| 0 = PWM1 block normal operation. | ||
| 1 = PWM1 block reset. | ||
| [25] | DAC_RST | DAC Controller Reset |
| 0 = DAC block normal operation. | ||
| 1 = DAC block reset. | ||
| [26] | LCD_RST | LCD Controller Reset |
| 0 = LCD block normal operation. | ||
| 1 = LCD block reset. | ||
| [27] | USBD_RST | USB Device Controller Reset |
| 0 = USB block normal operation. | ||
| 1 = USB block reset. | ||
| [28] | ADC_RST | ADC Controller Reset |
| 0 = ADC block normal operation. | ||
| 1 = ADC block reset. | ||
| [29] | I2S_RST | I2S Controller Reset |
| 0 = I2S block normal operation. | ||
| 1 = I2S block reset. | ||
| [30] | SC0_RST | SmartCard 0 Controller Reset |
| 0 = SmartCard block normal operation. | ||
| 1 = SmartCard block reset. | ||
| [31] | SC1_RST | SmartCard1 Controller Reset |
| 0 = SmartCard block normal operation. | ||
| 1 = SmartCard block reset. |
Definition at line 2156 of file Nano100Series.h.
| __IO uint32_t UART_T::IRCR |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | TX_SELECT | TX_SELECT |
| 0 = IrDA receiver Enabled. | ||
| 1 = IrDA transmitter Enabled. | ||
| Note: In IrDA mode, the UART_BAUD [DIV_16_EN) register must be set (the baud equation must be Clock / 16 * (BRD) | ||
| [5] | INV_TX | INV_TX |
| 0 = No inversion. | ||
| 1 = Inverse TX output signal. | ||
| [6] | INV_RX | INV_RX |
| 0 = No inversion. | ||
| 1 = Inverse RX input signal. |
Definition at line 10509 of file Nano100Series.h.
| __IO uint32_t SYS_T::IRCTRIMCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | TRIM_SEL | Trim Frequency Selection |
| This field indicates the target frequency of HIRC auto trim. | ||
| If no any target frequency is selected (TRIM_SEL is 00), the HIRC auto trim function is disabled. | ||
| During auto trim operation, if 32.768 kHz clock error detected or trim retry limitation count reached, this field will be cleared to 00 automatically. | ||
| 00 = Disable HIRC auto trim function | ||
| 01 = Enable HIRC auto trim function and trim HIRC to 11.0592 MHz | ||
| 10 = Enable HIRC auto trim function and trim HIRC to 12 MHz | ||
| 11 = Enable HIRC auto trim function and trim HIRC to 12.288 MHz | ||
| [5:4] | TRIM_LOOP | Trim Calculation Loop |
| This field defines that trim value calculation is based on how many 32.768 kHz clock. | ||
| For example, if TRIM_LOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. | ||
| 00 = 4 32.768 kHz clock | ||
| 01 = 8 32.768 kHz clock | ||
| 10 = 16 32.768 kHz clock | ||
| 11 = 32 32.768 kHz clock | ||
| [7:6] | TRIM_RETRY_CNT | Trim Value Update Limitation Count |
| This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. | ||
| Once the HIRC locked, the internal trim value update counter will be reset. | ||
| If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and TRIM_SEL will be cleared to 00. | ||
| 00 = Trim retry count limitation is 64 | ||
| 01 = Trim retry count limitation is 128 | ||
| 10 = Trim retry count limitation is 256 | ||
| 11 = Trim retry count limitation is 512 | ||
| [8] | ERR_STOP | Trim Stop When 32.768 KHz Error Detected |
| This bit is used to control if stop the HIRC trim operation when 32.768 kHz clock error is detected. | ||
| If set this bit high and 32.768 kHz clock error detected, the status 32K_ERR_INT would be set high and HIRC trim operation was stopped. | ||
| If this bit is low and 32.768 kHz clock error detected, the status 23K_ERR_INT would be set high and HIRC trim operation is continuously. | ||
| 0 = Continue the HIRC trim operation even if 32.768 kHz clock error detected. | ||
| 1 = Stop the HIRC trim operation if 32.768 kHz clock error detected. |
Definition at line 2879 of file Nano100Series.h.
| __IO uint32_t SYS_T::IRCTRIMIEN |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | TRIM_FAIL_IEN | Trim Failure Interrupt Enable |
| This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL. | ||
| If this bit is high and TRIM_FAIL_INT is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. | ||
| 0 = TRIM_FAIL_INT status Disabled to trigger an interrupt to CPU. | ||
| 1 = TRIM_FAIL_INT status Enabled to trigger an interrupt to CPU. | ||
| [2] | 32K_ERR_IEN | 32.768 KHz Clock Error Interrupt Enable |
| This bit controls if CPU would get an interrupt while 32.768 kHz clock is inaccuracy during auto trim operation. | ||
| If this bit is high, and 32K_ERR_INT is set during auto trim operation, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy. | ||
| 0 = 32K_ERR_INT status Disabled to trigger an interrupt to CPU. | ||
| 1 = 32K_ERR_INT status Enabled to trigger an interrupt to CPU. |
Definition at line 2899 of file Nano100Series.h.
| __IO uint32_t SYS_T::IRCTRIMINT |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FREQ_LOCK | HIRC Frequency Lock Status |
| This bit indicates the HIRC frequency lock. | ||
| This is a status bit and doesn't trigger any interrupt. | ||
| [1] | TRIM_FAIL_INT | Trim Failure Interrupt Status |
| This bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. | ||
| Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically. | ||
| If this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. | ||
| Write 1 to clear this to zero. | ||
| 0 = Trim value update limitation count doesn't reach. | ||
| 1 = Trim value update limitation count reached and HIRC frequency still doesn't lock. | ||
| [2] | 32K_ERR_INT | 32.768 KHz Clock Error Interrupt Status |
| This bit indicates that 32.768 kHz clock frequency is inaccuracy. | ||
| Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically. | ||
| If this bit is set and 32K_ERR_IEN is high, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy. | ||
| Write 1 to clear this to zero. | ||
| 0 = 32.768 kHz clock frequency is accuracy. | ||
| 1 = 32.768 kHz clock frequency is inaccuracy. |
Definition at line 2926 of file Nano100Series.h.
| __I uint32_t INTR_T::IRQSRC[32] |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 4996 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPADR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | ISPADR | ISP Address |
| This chip supports word program only. | ||
| ISPADR[1:0] must be kept 00b for ISP operation, and ISPADR[8:0] must be kept 0_0000_0000b for Vector Page Re-map Command. |
Definition at line 1845 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPCMD |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | FCTRL | ISP Command |
| The ISP command table is shown as follows. | ||
| [4] | FCEN | ISP Command |
| The ISP command table is shown as follows. | ||
| [5] | FOEN | ISP Command |
| The ISP command table is shown as follows. |
Definition at line 1874 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPCON |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPEN | ISP Enable (Write-Protection Bit) |
| ISP function enable bit. Set this bit to enable ISP function. | ||
| 0 = ISP function Disabled. | ||
| 1 = ISP function Enabled. | ||
| [1] | BS | Boot Select (Write-Protection Bit) |
| Set/clear this bit to select next booting from LDROM/APROM, respectively. | ||
| This bit also functions as chip booting status flag, which can be used to check where chip booted from. | ||
| This bit is initiated with the inversed value of CBS in Config0 after power-on reset; It keeps the same value at other reset. | ||
| 0 = boot from APROM. | ||
| 1 = boot from LDROM. | ||
| [3] | APUEN | APROM Update Enable (Write-Protection Bit) |
| APROM update enable bit. | ||
| 0 = APROM can not be updated. | ||
| 1 = APROM can be updated when the MCU runs in APROM. | ||
| [4] | CFGUEN | Enable Config-Bits Update By ISP (Write-Protection Bit) |
| 0 = Disabling ISP can update config-bits. | ||
| 1 = Enabling ISP can update config-bits. | ||
| [5] | LDUEN | LDROM Update Enable (Write-Protection Bit) |
| LDROM update enable bit. | ||
| 0 = LDROM cannot be updated. | ||
| 1 = LDROM can be updated when the chip runs in APROM. | ||
| [6] | ISPFF | ISP Fail Flag (Write-Protection Bit) |
| This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
| (1) APROM writes to itself | ||
| (2) LDROM writes to itself | ||
| (3) CONFIG is erased/programmed if CFGUEN is set to 0 | ||
| (4) Destination address is illegal, such as over an available range | ||
| Write 1 to clear. |
Definition at line 1832 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | ISPDAT | ISP Data |
| Write data to this register before ISP program operation | ||
| Read data from this register after ISP read operation |
Definition at line 1858 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPSTA |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPBUSY | ISP BUSY |
| 0 = ISP operation is finished. | ||
| 1 = ISP operation is busy. | ||
| Read Only | ||
| [2:1] | CBS | Config Boot Selection Status |
| [6] | ISPFF | ISP Fail Flag |
| This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
| (1) APROM writes to itself. | ||
| (2) LDROM writes to itself. | ||
| (3) CONFIG is erased/programmed when the MCU is running in APROM. | ||
| (4) Destination address is illegal, such as over an available range. | ||
| Write 1 to clear. |
Definition at line 1926 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPTRG |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPGO | ISP Start Trigger |
| Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. | ||
| 0 = ISP operation is finished. | ||
| 1 = ISP is progressing. |
Definition at line 1888 of file Nano100Series.h.
| __IO uint32_t PDMA_T::ISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TABORT_IS | PDMA Read/Write Target Abort Interrupt Status Flag |
| 0 = No bus ERROR response received. | ||
| 1 = Bus ERROR response received. | ||
| Note1: This bit is cleared by writing "1" to itself. | ||
| Note2: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not, if bus master received occur it means that target abort is happened. | ||
| PDMA controller will stop transfer and respond this event to software then go to IDLE state. | ||
| When target abort occurred, software must reset PDMA controller, and then transfer those data again. | ||
| [1] | TD_IS | Transfer Done Interrupt Status Flag |
| This bit indicates that PDMA has finished all transfer. | ||
| 0 = Not finished yet. | ||
| 1 = Done. | ||
| Note: This bit is cleared by writing "1" to itself. | ||
| [5:2] | WRA_BCR_IS | Wrap Around Transfer Byte Count Interrupt Status Flag |
| WAR_)CR_IS [0] (xxx1) = PDMA_CBCR equal 0 flag. | ||
| WAR_BCR_IS [2] (x1xx) = PDMA_CBCR equal 1/2 PDMA_BCR flag. | ||
| Note: Each bit is cleared by writing "1" to itself. | ||
| This field is only valid in wrap around mode. | ||
| (PDMA_CSR[DAD_SEL] =11 or PDMA_CSR[SAD_SEL] =11). | ||
| [6] | TO_IS | Time-Out Interrupt Status Flag |
| This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR. | ||
| 0 = No time-out flag. | ||
| 1 = Time-out flag. | ||
| Note: This bit is cleared by writing "1" to itself. |
Definition at line 6094 of file Nano100Series.h.
| __IO uint32_t VDMA_T::ISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TABORT_IS | VDMA Read/Write Target Abort Interrupt Status Flag |
| 0 = No bus ERROR response received. | ||
| 1 = Bus ERROR response received. | ||
| Note1: This bit is cleared by writing "1" to itself. | ||
| Note2: The VDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not, if bus master received occur it means that target abort is happened. | ||
| VDMA controller will stop transfer and respond this event to software then go to IDLE state. | ||
| When target abort occurred, software must reset VDMA controller, and then transfer those data again. | ||
| [1] | TD_IS | Transfer Done Interrupt Status Flag |
| This bit indicates that VDMA has finished all transfer. | ||
| 0 = Not finished yet. | ||
| 1 = Done. | ||
| Note: This bit is cleared by writing "1" to itself. |
Definition at line 6261 of file Nano100Series.h.
| __IO uint32_t SC_T::ISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDA_IS | Receive Data Reach Interrupt Status Flag (Read Only) |
| This field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt status flag. | ||
| Note: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV]. | ||
| If software reads data from SC_RBR and receiver pointer is less than SC_CTL [RX_FTRI_LEV], this bit will be cleared automatically. | ||
| [1] | TBE_IS | Transmit Buffer Empty Interrupt Status Flag (Read Only) |
| This field is used for transmit buffer empty interrupt status flag. | ||
| This bit is different with SC_TRSR [TX_EMPTY_F] flag and SC_TRSR [TX_ATV] flag; The TX_EMPTY_F will be set when the last byte data be read to shift register and TX_ATV flag indicates the transmitter is in active or not (the last data has been transmitted or not), but the TBE_IS may be set when the last byte data be read to shift register or the last data has been transmitted. | ||
| When this bit assert, software can write 1~4 byte data to SC_THR register. | ||
| Note: If software wants to clear this bit, software must write data to SC_THR register and then this bit will be cleared automatically. | ||
| [2] | TERR_IS | Transfer Error Interrupt Status Flag (Read Only) |
| This field is used for transfer error interrupt status flag. | ||
| The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F) and receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY). | ||
| Note: This field is the status flag of SC_TRSR [RX_EBR_F], SC_TRSR [RX_EFR_F], SC_TRSR [RX_EPA_F], SC_TRSR [RX_OVER_F], SC_TRSR [TX_OVER_F], SC_TRSR [RX_OVER_ERETRY] or SC_TRSR [TX_OVER_ERETRY]. | ||
| So if software wants to clear this bit, software must write "1" to each field. | ||
| [3] | TMR0_IS | Timer0 Interrupt Status Flag (Read Only) |
| This field is used for TMR0 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [4] | TMR1_IS | Timer1 Interrupt Status Flag (Read Only) |
| This field is used for TMR1 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [5] | TMR2_IS | Timer2 Interrupt Status Flag (Read Only) |
| This field is used for TMR2 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [6] | BGT_IS | Block Guard Time Interrupt Status Flag (Read Only) |
| This field is used for block guard time interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [7] | CD_IS | Card Detect Interrupt Status Flag (Read Only) |
| This field is used for card detect interrupt status flag. | ||
| The card detect status register is SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F]. | ||
| Note: This field is the status flag of SC_PINCSR [CD_INS_F] or SC_PINCSR [CD_REM_F]. | ||
| So if software wants to clear this bit, software must write "1" to this field. | ||
| [8] | INIT_IS | Initial End Interrupt Status Flag (Read Only) |
| This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [9] | RTMR_IS | Receiver Buffer Time-Out Interrupt Status Flag (Read Only) |
| This field is used for receiver buffer time-out interrupt status flag. | ||
| Note: This field is the status flag of receiver buffer time-out state. | ||
| If software wants to clear this bit, software must read the receiver buffer remaining data by reading SC_RBR register,. | ||
| [10] | ACON_ERR_IS | Auto Convention Error Interrupt Status Flag (Read Only) |
| This field indicates auto convention sequence error. | ||
| If the received TS at ATR state is not 0x3B or 0x3F, this bit will be set. | ||
| Note: This bit is read only, but can be cleared by writing "1" to it. |
Definition at line 8634 of file Nano100Series.h.
| __IO uint32_t TIMER_T::ISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TMR_IS | Timer Interrupt Status |
| This bit indicates the interrupt status of Timer. | ||
| This bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). | ||
| Write 1 to clear this bit to 0. | ||
| If this bit is active and TMR_IE is enabled, Timer will trigger an interrupt to CPU. | ||
| [1] | TCAP_IS | Timer Capture Function Interrupt Status |
| This bit indicates the external pin function interrupt status of Timer. | ||
| This bit is set by hardware when TCAP_EN is set high, and the transition of external pin matches the TCAP_EDGE setting. | ||
| Write 1 to clear this bit to zero. | ||
| If this bit is active and TCAP_IE is enabled, Timer will trigger an interrupt to CPU. | ||
| [4] | TMR_Wake_STS | Timer Wake-Up Status |
| If timer causes CPU wakes up from power-down mode, this bit will be set to high. | ||
| It must be cleared by software with a write 1 to this bit. | ||
| 0 = Timer does not cause system wake-up. | ||
| 1 = Wakes system up from power-down mode by Timer timeout. | ||
| [5] | NCAP_DET_STS | New Capture Detected Status |
| This status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS status. | ||
| If the above condition occurred, the Timer will keep register TMRx_CAP unchanged and drop the new capture value. | ||
| This bit is also cleared to 0 while TCAP_IS is cleared. | ||
| 0 = New incoming capture event didn't detect before CPU clearing TCAP_IS status. | ||
| 1 = New incoming capture event detected before CPU clearing TCAP_IS status. |
Definition at line 9964 of file Nano100Series.h.
| __IO uint32_t UART_T::ISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDA_IS | Receive Data Available Interrupt Flag (Read Only) |
| When the number of bytes in the RX-FIFO equals the RFITL then the RDA_IF will be set. | ||
| If IER [RDA_IEN] is set then the RDA interrupt will be generated. | ||
| Note: This bit is read only and it will be cleared when the number of unread bytes of RX-FIFO drops below the threshold level (RFITL). | ||
| [1] | THRE_IS | Transmit Holding Register Empty Interrupt Flag (Read Only) |
| This bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register. | ||
| If IER [THRE_IEN] is set that the THRE interrupt will be generated. | ||
| Note: This bit is read only and it will be cleared when writing data into THR (TX-FIFO not empty). | ||
| [2] | RLS_IS | Receive Line Interrupt Status Flag (Read Only) |
| This bit is set when the RX received data has parity error (UART_FSR [PE_F]), framing error (UART_FSR [FE_F]), break error (UART_FSR [BI_F]) or RS-485 detect address byte (UART_TRSR [RS-485_ADDET_F]).If IER [RLS_IEN] is set then the RLS interrupt will be generated. | ||
| Note1: This bit is read only, but can be cleared by it by writing "1" to UART_FSR [BI_F], UART_FSR [FE_F], UART_FSR [PE_F] or UART_TRSR [RS-485_ADDET_F]. | ||
| Note2: This bit is cleared when all the BI_F, FE_F, PE_F and RS-485_ADDET_F are cleared. | ||
| [3] | MODEM_IS | MODEM Interrupt Status Flag (Read Only) |
| This bit is set when the CTSn pin has state change (DCTSF = "1"). | ||
| If IER [MODEM_IEN] is set then the modem interrupt will be generated. | ||
| Note: This bit is read only, but can be cleared by it by writing "1" to UART_MCSR [DCT_F]. | ||
| [4] | RTO_IS | RX Time-Out Interrupt Status Flag (Read Only) |
| This bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC. | ||
| If IER [Tout_IEN] is set then the tout interrupt will be generated. | ||
| Note: This bit is read only and user can read UART_RBR (RX is in active) to clear it. | ||
| [5] | BUF_ERR_IS | Buffer Error Interrupt Status Flag (Read Only) |
| This bit is set when the TX or RX-FIFO overflowed. | ||
| When BUF_ERR_IS is set, the transfer maybe not correct. | ||
| If IER [BUF_ER_IEN] is set then the buffer error interrupt will be generated. | ||
| Note1: This bit is read only, but can be cleared by it by writing "1" to UART_FSR [TX_OVER_F] or UART_FSR [RX_OVER_F]. | ||
| Note2: This bit is cleared when both the TX_OVER_F and RX_OVER_F are cleared. | ||
| [6] | WAKE_IS | Wake-Up Interrupt Status Flag (Read Only) |
| This bit is set in Power-down mode, the receiver received data or CTSn signal. | ||
| If IER [WAKE_IE] is set then the wake-up interrupt will be generated. | ||
| Note: This bit is read only, but can be cleared by it by writing "1" to it. | ||
| [7] | ABAUD_IS | Auto-Baud Rate Interrupt Status Flag (Read Only) |
| This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if IER [ABAUD_IE] is set then the auto-baud rate interrupt will be generated. | ||
| Note1: This bit is read only, but can be cleared by it by writing "1" to UART_TRSR [ABAUD_TOUT_F] or UART_TRSR [ABAUD_F]. | ||
| Note2: This bit is cleared when both the ABAUD_TOUT_F and ABAUD_F are cleared. | ||
| [8] | LIN_IS | LIN Interrupt Status Flag (Read Only) |
| This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if IER [LIN_IE] is set then the LIN interrupt will be generated. | ||
| Note1: This bit is read only, but can be cleared by it by writing "1" to UART_TRSR [BIT_ERR_F], UART_TRSR [BIT_TX_F] or UART_TRSR [LIN_RX_F]. | ||
| Note2: This bit is cleared when both the BIT_ERR_F, BIT_TX_F and LIN_RX_F are cleared. |
Definition at line 10318 of file Nano100Series.h.
| __IO uint32_t WDT_T::ISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | IS | Watchdog Timer Interrupt Status |
| If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. | ||
| If the Watchdog timer interrupt is not enabled, then this bit indicates that a time-out period has elapsed. | ||
| 0 = Watchdog timer interrupt did not occur. | ||
| 1 = Watchdog timer interrupt occurs. | ||
| Note: This bit is read only, but can be cleared by writing "1" to it. | ||
| [1] | RST_IS | Watchdog Timer Reset Status |
| When the Watchdog timer initiates a reset, the hardware will set this bit. | ||
| This flag can be read by software to determine the source of reset. | ||
| Software is responsible to clear it manually by writing "1" to it. | ||
| If WTRE is disabled, then the Watchdog timer has no effect on this bit. | ||
| 0 = Watchdog timer reset did not occur. | ||
| 1 = Watchdog timer reset occurs. | ||
| Note: This bit is read only, but can be cleared by writing "1" to it. | ||
| [2] | WAKE_IS | Watchdog Timer Wake-Up Status |
| If Watchdog timer causes system to wake up from power-down mode, this bit will be set to high. | ||
| It must be cleared by software with a write "1" to this bit. | ||
| 0 = Watchdog timer does not cause system wake-up. | ||
| 1 = Wake system up from power-down mode by Watchdog time-out. | ||
| Note1: When system in power-down mode and watchdog time-out, hardware will set WDT_WAKE_IS and WDT_IS. | ||
| Note2: After one engine clock, this bit can be cleared by writing "1" to it |
Definition at line 11419 of file Nano100Series.h.
| __IO uint32_t GPIO_T::ISRC |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | ISRC | GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator |
| Read : | ||
| 1 = Port x[n] generate an interrupt. | ||
| 0 = No interrupt at Port x[n]. | ||
| Write: | ||
| 1 = Clear the correspond pending interrupt. | ||
| 0 = No action. | ||
| Note: For GPIOF_ISRC, bits [15:6] are reserved. |
Definition at line 3955 of file Nano100Series.h.
| __I uint32_t RTC_T::LIR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | LIR | Leap Year Indication REGISTER (Read Only) |
| 0 = This year is not a leap year. | ||
| 1 = This year is leap year. |
Definition at line 7947 of file Nano100Series.h.
| __IO uint32_t CLK_T::MCLKO |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | MCLK_SEL | Module Clock Output Source Selection (PC.0) |
| 000000 = ISP_CLK | ||
| 000001 = HIRC | ||
| 000010 = HXT | ||
| 000011 = LXT | ||
| 000100 = LIRC | ||
| 000101 = PLL output | ||
| 000110 = PLL input | ||
| 000111 = System Tick | ||
| 001000 = HCLK clock | ||
| 001010 = PCLK clock | ||
| 100000 = TMR0_CLK | ||
| 100001 = TMR1_CLK | ||
| 100010 = UART0_CLK | ||
| 100011 = USB_CLK | ||
| 100100 = ADC_CLK | ||
| 100101 = WDT_CLK | ||
| 100110 = PWM0_CH01_CLK | ||
| 100111 = PWM0_CH32_CLK | ||
| 101001 = LCD_CLK | ||
| 111000 = TMR2_CLK | ||
| 111001 = TMR3_CLK | ||
| 111010 = UART1_CLK | ||
| 111011 = PWM1_CH01_CLK | ||
| 111100 = PWM1_CH23_CLK | ||
| 111101 = I²S_CLK | ||
| 111110 = SC0_CLK | ||
| 111111 = SC1_CLK | ||
| [7] | MCLK_EN | Module Clock Output Enable |
| User can get the module clock output from PC.0 pin via choosing the clock source in the MCLK_SEL bit field and then setting MCLK_EN bit to 1. | ||
| 0 = Module clock output Disabled. | ||
| 1 = Module clock output Enabled. | ||
| Note: If this bit is enabled, PC.0 will be configured to module clock output and the setting of PC0_MFP will be ineffective |
Definition at line 1189 of file Nano100Series.h.
| __IO uint32_t UART_T::MCSR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | LEV_RTS | RTSn Trigger Level |
| This bit can change the RTSn trigger level. | ||
| 0 = low level triggered. | ||
| 1 = high level triggered. | ||
| Note: In RS-485 AUD mode and RTS Auto-flow control mode, hardware will control the output RTS pin automatically, so the table indicates the default value. | ||
| Note: The default setting in UART mode is LEV_RTS = "0" and RTS_ST = "1". | ||
| [1] | RTS_ST | RTSn Pin State (Read Only) |
| This bit is the pin status of RTSn. | ||
| [16] | LEV_CTS | CTSn Trigger Level |
| This bit can change the CTSn trigger level. | ||
| 0 = Low level triggered. | ||
| 1 = High level triggered. | ||
| [17] | CTS_ST | CTSn Pin Status (Read Only) |
| This bit is the pin status of CTSn. | ||
| [18] | DCT_F | Detect CTSn State Change Status Flag (Read Only) |
| This bit is set whenever CTSn input has change state, and it will generate Modem interrupt to CPU when UART_IER [Modem_IEN]. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. |
Definition at line 10448 of file Nano100Series.h.
| __IO uint32_t INTR_T::MCU_IRQ |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | MCU_IRQ | MCU IRQ Source Register |
| The IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. | ||
| There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mode. | ||
| In Normal mode (control by NMI_SEL register bit [7] = 0) The MCU_IRQ collects all interrupts from each peripheral | ||
| and synchronizes them and then interrupts the Cortex-M0. | ||
| In Test mode, all the interrupts from peripheral are blocked, and the interrupts sent to | ||
| MCU are replaced by set the bit31~bit0. | ||
| When the IRQ[n] is 0, setting IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n]. | ||
| When the IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting IRQ[n] 0 has no effect. |
Definition at line 5028 of file Nano100Series.h.
| __IO uint32_t LCD_T::MEM_0 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | SEG_0_4x | SEG_0_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [14:8] | SEG_1_4x | SEG_1_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [21:16] | SEG_2_4x | SEG_2_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [29:24] | SEG_3_4x | SEG_3_4x DATA for COM (x = 0 ~ 9) |
| LCD display data |
Definition at line 5165 of file Nano100Series.h.
| __IO uint32_t LCD_T::MEM_1 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | SEG_0_4x | SEG_0_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [14:8] | SEG_1_4x | SEG_1_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [21:16] | SEG_2_4x | SEG_2_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [29:24] | SEG_3_4x | SEG_3_4x DATA for COM (x = 0 ~ 9) |
| LCD display data |
Definition at line 5183 of file Nano100Series.h.
| __IO uint32_t LCD_T::MEM_2 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | SEG_0_4x | SEG_0_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [14:8] | SEG_1_4x | SEG_1_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [21:16] | SEG_2_4x | SEG_2_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [29:24] | SEG_3_4x | SEG_3_4x DATA for COM (x = 0 ~ 9) |
| LCD display data |
Definition at line 5201 of file Nano100Series.h.
| __IO uint32_t LCD_T::MEM_3 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | SEG_0_4x | SEG_0_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [14:8] | SEG_1_4x | SEG_1_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [21:16] | SEG_2_4x | SEG_2_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [29:24] | SEG_3_4x | SEG_3_4x DATA for COM (x = 0 ~ 9) |
| LCD display data |
Definition at line 5219 of file Nano100Series.h.
| __IO uint32_t LCD_T::MEM_4 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | SEG_0_4x | SEG_0_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [14:8] | SEG_1_4x | SEG_1_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [21:16] | SEG_2_4x | SEG_2_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [29:24] | SEG_3_4x | SEG_3_4x DATA for COM (x = 0 ~ 9) |
| LCD display data |
Definition at line 5237 of file Nano100Series.h.
| __IO uint32_t LCD_T::MEM_5 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | SEG_0_4x | SEG_0_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [14:8] | SEG_1_4x | SEG_1_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [21:16] | SEG_2_4x | SEG_2_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [29:24] | SEG_3_4x | SEG_3_4x DATA for COM (x = 0 ~ 9) |
| LCD display data |
Definition at line 5255 of file Nano100Series.h.
| __IO uint32_t LCD_T::MEM_6 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | SEG_0_4x | SEG_0_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [14:8] | SEG_1_4x | SEG_1_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [21:16] | SEG_2_4x | SEG_2_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [29:24] | SEG_3_4x | SEG_3_4x DATA for COM (x = 0 ~ 9) |
| LCD display data |
Definition at line 5273 of file Nano100Series.h.
| __IO uint32_t LCD_T::MEM_7 |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | SEG_0_4x | SEG_0_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [14:8] | SEG_1_4x | SEG_1_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [21:16] | SEG_2_4x | SEG_2_4x DATA for COM(x= 0 ~ 9) |
| LCD display data | ||
| [29:24] | SEG_3_4x | SEG_3_4x DATA for COM (x = 0 ~ 9) |
| LCD display data |