| 0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer. | ||
| 1 = Single Message Object or last Message Object of a FIFO Buffer. | ||
| Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. | ||
| For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one. | ||
| [8] | TxRqst | Transmit Request |
| 0 = This Message Object is not waiting for transmission. | ||
| 1 = The transmission of this Message Object is requested and is not yet done. | ||
| [9] | RmtEn | Remote Enable Control |
| 0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged. | ||
| 1 = At the reception of a Remote Frame, TxRqst is set. | ||
| [10] | RxIE | Receive Interrupt Enable Control |
| 0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame. | ||
| 1 = IntPnd will be set after a successful reception of a frame. | ||
| [11] | TxIE | Transmit Interrupt Enable Control |
| 0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame. | ||
| 1 = IntPnd will be set after a successful transmission of a frame. | ||
| [12] | UMask | Use Acceptance Mask |
| 0 = Mask ignored. | ||
| 1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering. | ||
| Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one. | ||
| [13] | IntPnd | Interrupt Pending |
| 0 = This message object is not the source of an interrupt. | ||
| 1 = This message object is the source of an interrupt. | ||
| The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. | ||
| [14] | MsgLst | Message Lost (only valid for Message Objects with direction = receive). |
| 0 = No message lost since last time this bit was reset by the CPU. | ||
| 1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message. | ||
| [15] | NewDat | New Data |
| 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software. | ||
| 1 = The Message Handler or the application software has written new data into the data portion of this Message Object. |
Definition at line 1063 of file NUC472_442.h.
| __IO uint32_t CAP_T::MD |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | MDEN | Motion Detection Enable |
| 0 = CAP_MD Disabled. | ||
| 1 = CAP_MD Enabled. | ||
| [8] | MDBS | Motion Detection Block Size |
| 0 = 16x16. | ||
| 1 = 8x8. | ||
| [9] | MDSM | Motion Detection Save Mode |
| 0 = 1 bit DIFF + 7 bit Y Differential. | ||
| 1 = 1 bit DIFF only. | ||
| [10:11] | MDDF | Motion Detection Detect Frequency |
| 00 = Each frame. | ||
| 01 = Every 2 frame. | ||
| 10 = Every 3 frame. | ||
| 11 = Every 4 frame. | ||
| [16:20] | MDTHR | Motion Detection Differential Threshold |
Definition at line 1845 of file NUC472_442.h.
| __IO uint32_t CAP_T::MDADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | MDADDR | Motion Detection Output Address Register (Word Alignment) |
Definition at line 1856 of file NUC472_442.h.
| __IO uint32_t CAP_T::MDYADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | MDYADDR | Motion Detection Temp Y Output Address Register (Word Alignment) |
Definition at line 1867 of file NUC472_442.h.
| __IO uint32_t EMAC_T::MIIMCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:4] | PHYREG | PHY Register Address |
| The PHYREG keeps the address to indicate which register of external PHY is the target of the MII management command. | ||
| [8:12] | PHYADDR | PHY Address |
| The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command. | ||
| [16] | WRITE | Write Command |
| The Write defines the MII management command is a read or write. | ||
| 0 = MII management command is a read command. | ||
| 1 = MII management command is a write command. | ||
| [17] | BUSY | Busy Bit |
| The BUSY controls the enable of the MII management frame generation. | ||
| If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates the MII management frame to external PHY through MII Management I/F. | ||
| The BUSY is a self-clear bit. | ||
| This means the BUSY will be cleared automatically after the MII management command finished. | ||
| 0 = MII management command generation finished. | ||
| 1 = MII management command generation Enabled. | ||
| [18] | PREAMSP | Preamble Suppress |
| The PREAMSP controls the preamble field generation of MII management frame. | ||
| If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped. | ||
| 0 = Preamble field generation of MII management frame not skipped. | ||
| 1 = Preamble field generation of MII management frame skipped. | ||
| [19] | MDCON | MDC Clock ON Always |
| The MDC controls the MDC clock generation. | ||
| If the MDCON is set to high, the MDC clock actives always. | ||
| Otherwise, the MDC will only active while S/W issues a MII management command. | ||
| 0 = MDC clock only actives while S/W issues a MII management command. | ||
| 1 = MDC clock actives always. |
Definition at line 12529 of file NUC472_442.h.
| __IO uint32_t EMAC_T::MIIMDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | DATA | MII Management Data |
| The DATA is the 16 bits data that will be written into the registers of external PHY for MII Management write command or the data from the registers of external PHY for MII Management read command. |
Definition at line 12493 of file NUC472_442.h.
| __IO uint32_t GPIO_T::MODE |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | MODE0 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [2:3] | MODE1 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [4:5] | MODE2 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [6:7] | MODE3 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [8:9] | MODE4 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [10:11] | MODE5 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [12:13] | MODE6 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [14:15] | MODE7 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [16:17] | MODE8 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [18:19] | MODE9 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [20:21] | MODE10 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [22:23] | MODE11 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [24:25] | MODE12 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [26:27] | MODE13 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [28:29] | MODE14 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). | ||
| [30:31] | MODE15 | Port N Bit M I/O Mode Control |
| Determine the I/O mode of port n bit m. | ||
| 00 = INPUT only mode. | ||
| 01 = OUTPUT mode. | ||
| 10 = Open-drain mode. | ||
| 11 = Quasi-bidirectional mode. | ||
| Reset value: | ||
| 0xFFFF_FFFF when ( cfg_io =1'b0). | ||
| 0x0000_00000 when ( cfg_io =1'b1). |
Definition at line 15165 of file NUC472_442.h.
| __IO uint32_t UART_T::MODEM |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | RTS | RTS (Request-To-Send) Signal |
| 0 = Drive RTS pin to logic 1 (If the RTSACTLV | ||
| set to low level triggered). | ||
| 1 = Drive RTS pin to logic 0 (If the RTSACTLV set to low level triggered). | ||
| 0 = Drive RTS pin to logic 0 (If the RTSACTLV | ||
| set to high level triggered). | ||
| 1 = Drive RTS pin to logic 1 (If the RTSACTLV set to high level triggered). | ||
| [9] | RTSACTLV | RTS Trigger Level |
| This bit can change the RTS trigger level. | ||
| 0= Low level triggered. | ||
| 1= High level triggered. | ||
| [13] | RTSSTS | RTS Pin State (Read Only) |
| This bit is the output pin status of RTS. |
Definition at line 25344 of file NUC472_442.h.
| __IO uint32_t UART_T::MODEMSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CTSDETF | Detect CTS State Change Flag (Read Only) |
| This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1. | ||
| Software can write 1 to clear this bit to 0 | ||
| [4] | CTSSTS | CTS Pin Status (Read Only) |
| This bit is the pin status of CTS. | ||
| [8] | CTSACTLV | CTS Trigger Level |
| This bit can change the CTS trigger level. | ||
| 0= Low level triggered. | ||
| 1= High level triggered. |
Definition at line 25363 of file NUC472_442.h.
| __IO uint32_t FMC_T::MPADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | MPADDR | ISP Multi-Word Program Address Status |
| MPADDR is the address of ISP Multi-Word Program operation when | ||
| MPBUSY flag is 1. MPADDR will keep the final address when | ||
| Multi-Word Program is aborted or finished. |
Definition at line 14903 of file NUC472_442.h.
| __IO uint32_t EMAC_T::MPCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | MPCNT | Miss Packet Count |
| The MPCNT indicates the number of packets that were dropped due to various types of receive errors. | ||
| The following type of receiving error makes missed packet counter increase:. | ||
| 1. Incoming packet is incurred RXFIFO overflow. | ||
| 2. Incoming packet is dropped due to RXON is disabled. | ||
| 3. Incoming packet is incurred CRC error. |
Definition at line 13014 of file NUC472_442.h.
| __IO uint32_t FMC_T::MPDAT0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | ISPDAT0 | ISP Data 0 |
| This register is the first 32-bit data for 32b/64b/multi-word program, | ||
| and it is also the mirror of FMC_ISPDAT register, both registers keep the same data. |
Definition at line 14815 of file NUC472_442.h.
| __IO uint32_t FMC_T::MPDAT1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | ISPDAT1 | ISP Data 1 |
| This register is the second 32-bit data for 32b/64b/multi-word program. |
Definition at line 14827 of file NUC472_442.h.
| __IO uint32_t FMC_T::MPDAT2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | ISPDAT2 | ISP Data 2 |
| This register is the third 32-bit data for 32b/64b/multi-word program. |
Definition at line 14839 of file NUC472_442.h.
| __IO uint32_t FMC_T::MPDAT3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | ISPDAT3 | ISP Data 3 |
| This register is the fourth 32-bit data for 32b/64b/multi-word program. |
Definition at line 14851 of file NUC472_442.h.
| __IO uint32_t FMC_T::MPSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | MPBUSY | ISP Multi-Word Program Busy Flag (Read Only) |
| 0 = ISP Multi-Word Program operation is aborted or finished. | ||
| 1 = ISP Multi-Word Program operation is progressed. | ||
| [2] | ISPFF | ISP Fail Flag (Read Only) |
| This CBS field is just a copy of User-Configuration Config0 CBS[7:6]. | ||
| [4] | D0 | ISP DATA 0 Flag (Read Only) |
| This bit is set when FMC_MPDAT0 is written and auto-clear to 0 | ||
| when the FMC_MPDAT0 is programmed to flash complete. | ||
| 0 = FMC_MPDAT0 register is empty, or program to flash complete. | ||
| 1 = FMC_MPDAT0 register has been written, and not programmed to flash yet. | ||
| [5] | D1 | ISP DATA 1 Flag (Read Only) |
| This bit is set when FMC_MPDAT1 is written and auto-clear to 0 | ||
| when the FMC_MPDAT1 is programmed to flash complete. | ||
| 0 = FMC_MPDAT1 register is empty, or program to flash complete. | ||
| 1 = FMC_MPDAT1 register has been written, and not programmed to flash yet. | ||
| [6] | D2 | ISP DATA 2 Flag (Read Only) |
| This bit is set when FMC_MPDAT2 is written and auto-clear to 0 | ||
| when the FMC_MPDAT2 is programmed to flash complete. | ||
| 0 = FMC_MPDAT2 register is empty, or program to flash complete. | ||
| 1 = FMC_MPDAT2 register has been written, and not programmed to flash yet. | ||
| [7] | D3 | ISP DATA 3 Flag (Read Only) |
| This bit is set when FMC_MPDAT3 is written and auto-clear to 0 | ||
| when the FMC_MPDAT3 is programmed to flash complete. | ||
| 0 = FMC_MPDAT3 register is empty, or program to flash complete. | ||
| 1 = FMC_MPDAT3 register has been written, and not programmed to flash yet. |
Definition at line 14889 of file NUC472_442.h.
| __IO uint32_t EMAC_T::MRFL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | MRFL | Maximum Receive Frame Length |
| The MRFL defines the maximum frame length for received frame. | ||
| If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8]) is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered. | ||
| It is recommended that only use MRFL to qualify the length of received frame while S/W wants to receive a frame which length is greater than 1518 bytes. |
Definition at line 12612 of file NUC472_442.h.
| __IO uint32_t EPWM_T::MSK |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | MSKDAT | PWM Mask Data Bit |
| This data bit control the state of PWMn output pin, if the corresponding PME.n = 1. | ||
| 0 = Output logic low to PWMn. | ||
| 1 = Output logic high to PWMn. | ||
| Note: n = 0~5. |
Definition at line 14151 of file NUC472_442.h.
| __IO uint32_t PWM_T::MSK |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | MSKDAT | PWM Mask Data Bit: |
| This data bit control the state of PWMn output pin, if corresponding mask function is enabled. | ||
| 0 = Output logic low to PWMn. | ||
| 1 = Output logic high to PWMn. | ||
| Note: Each bit controls the corresponding PWM channel. |
Definition at line 19252 of file NUC472_442.h.
| __IO uint32_t EPWM_T::MSKEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | MSKEN | PWM Mask Enable Control |
| The PWM generator signal will be masked when this bit is enabled. | ||
| The corresponding PWMn channel will be output with PMD.n data. | ||
| 0 = PWM generator signal is output to next stage. | ||
| 1 = PWM generator signal is masked and PMD.n is output to next stage. | ||
| Note: n = 0~5. |
Definition at line 14136 of file NUC472_442.h.
| __IO uint32_t PWM_T::MSKEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | MSKEN | PWM Mask Enable Control |
| The PWM output signal will be masked when this bit is enabled. | ||
| The corresponding PWMn channel will be output with MSKDAT data. | ||
| 0 = PWM output signal is non-masked. | ||
| 1 = PWM output signal is masked and output with MSKDAT data. | ||
| Note: Each bit controls the corresponding PWM channel. |
Definition at line 19237 of file NUC472_442.h.
| __IO uint32_t CAN_T::MVLD1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | MsgVal161 | Message Valid Bits 16-1 (Of All Message Objects) (Read Only) |
| 0 = This Message Object is ignored by the Message Handler. | ||
| 1 = This Message Object is configured and should be considered by the Message Handler. | ||
| Ex. | ||
| CAN_MVLD1[0] means Message object No.1 is valid or not. | ||
| If CAN_MVLD1[0] is set, message object No.1 is configured. |
Definition at line 1399 of file NUC472_442.h.
| __IO uint32_t CAN_T::MVLD2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | MsgVal3217 | Message Valid Bits 32-17 (Of All Message Objects) (Read Only) |
| 0 = This Message Object is ignored by the Message Handler. | ||
| 1 = This Message Object is configured and should be considered by the Message Handler. | ||
| Ex.CAN_MVLD2[15] means Message object No.32 is valid or not. | ||
| If CAN_MVLD2[15] is set, message object No.32 is configured. |
Definition at line 1414 of file NUC472_442.h.
| __IO uint32_t CAN_T::NDAT1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | NewData161 | New Data Bits 16-1 (Of All Message Objects) |
| 0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. | ||
| 1 = The Message Handler or the application software has written new data into the data portion of this Message Object. |
Definition at line 1340 of file NUC472_442.h.
| __IO uint32_t CAN_T::NDAT2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | NewData3217 | New Data Bits 32-17 (Of All Message Objects) |
| 0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. | ||
| 1 = The Message Handler or the application software has written new data into the data portion of this Message Object. |
Definition at line 1353 of file NUC472_442.h.
| __IO uint32_t DSCT_T::NEXT |
| Bits | Field | Descriptions |
|---|---|---|
| [2:15] | NEXT | PDMA Next Description Table Offset Address Bits |
| This field indicates the offset of next descriptor table address in system memory. | ||
| Note1: The next descriptor table address must be word boundary. | ||
| Note2: The system memory based address is 0x2000_0000 (PDMA_ETADDR), if the next descriptor table is 0x2000_0100, that this field must fill 0x0100. | ||
| Note3: Before filled transfer task in the description table, user must check if the descriptor table is complete. |
Definition at line 18223 of file NUC472_442.h.
| __IO uint32_t EPWM_T::NPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | NEGPOLAR | PWM Negative Polarity Control |
| The register bit controls polarity/active state of real PWM output. | ||
| 0 = PWMn output is active high. | ||
| 1 = PWMn output is active low. | ||
| Note: n = 0~5. |
Definition at line 14248 of file NUC472_442.h.
| __IO uint32_t USBD_T::OPER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RESUMEEN | Generate Resume |
| 0 = No Resume sequence to be initiated to the host. | ||
| 1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled. | ||
| This bit is self-clearing. | ||
| [1] | HISPDEN | USB High-Speed |
| 0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host. | ||
| 1 = The USB device controller to initiate a chirp-sequence during reset protocol. | ||
| [2] | CURSPD | USB Current Speed |
| 0 = The device has settled in Full Speed. | ||
| 1 = The USB device controller has settled in High-speed. |
Definition at line 27510 of file NUC472_442.h.
| __IO uint32_t EPWM_T::OUTEN0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | EVENOUTEN | PWM Even Ports Output Enable Control |
| 0 = PWM even ports output Disabled (PWM even ports at tri-state). | ||
| 1 = PWM even ports output Enabled. | ||
| [1] | ODDOUTEN | PWM Odd Ports Output Enable Control |
| 0 = PWM odd ports output Disabled (PWM even ports at tri-state). | ||
| 1 = PWM odd ports output Enabled. |
Definition at line 14385 of file NUC472_442.h.
| __IO uint32_t EADC_T::OVSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | SPOVF7_0 | A/D SAMPLE07~SAMPLE00 Start Of Conversion Overrun Flag |
| 0 = No SAMPLE0x event overrun. | ||
| 1 = Indicates a new SAMPLE0x event is generated while an old one event is pending. | ||
| If there is a new trigger event comes when the SAMPLE is pending for the last trigger event, the overrun is happened and the SPOVF bit will be set as 1. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| Note: x = 0~7. | ||
| [8:15] | SPOVF15_8 | A/D SAMPLE17~SAMPLE10 Start Of Conversion Overrun Flag |
| 0 = No SAMPLE1x event overrun. | ||
| 1 = Indicates a new SAMPLE1x event is generated while an old one event is pending. | ||
| If there is a new trigger event comes when the SAMPLE is pending for the last trigger event, the overrun is happened and the SPOVF bit will be set as 1. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| Note: x = 0~7. |
Definition at line 7883 of file NUC472_442.h.
| __IO uint32_t CAP_T::PAR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | INFMT | Sensor Input Data Format |
| 0 = YCbCr422. | ||
| 1 = RGB565. | ||
| [1] | SENTYPE | Sensor Input Type |
| 0 = CCIR601. | ||
| 1 = CCIR656, VSync & Hsync embedded in the data signal. | ||
| [2:3] | INDATORD | Sensor Input Data Order |
| If INFMT = 0 (YCbCr),. | ||
| Byte 0 1 2 3 | ||
| 00 = Y0 U0 Y1 V0. | ||
| 01 = Y0 V0 Y1 U0. | ||
| 10 = U0 Y0 V0 Y1. | ||
| 11 = V0 Y0 U0 Y1. | ||
| If INFMT = 1 (RGB565),. | ||
| 00 = Byte0[R[4:0] G[5:3]] Byte1[G[2:0] B[4:0]] | ||
| 01 = Byte0[B[4:0] G[5:3]] Byte1[G[2:0] R[4:0]] | ||
| 10 = Byte0[G[2:0] B[4:0]] Byte1[R[4:0] G[5:3]] | ||
| 11 = Byte0[G[2:0] R[4:0]] Byte1[B[4:0] G[5:3]] | ||
| [4:5] | OUTFMT | Image Data Format Output To System Memory |
| 00 = YCbCr422. | ||
| 01 = Only output Y. | ||
| 10 = RGB555. | ||
| 11 = RGB565. | ||
| [6] | RANGE | Scale Input YUV CCIR601 Color Range To Full Range |
| 0 = default. | ||
| 1 = Scale to full range. | ||
| [7] | PLNFMT | Planar Output YUV Format |
| 0 = YUV422. | ||
| 1 = YUV420. | ||
| [8] | PCLKP | Sensor Pixel Clock Polarity |
| 0 = Input video data and signals are latched by falling edge of Pixel Clock. | ||
| 1 = Input video data and signals are latched by rising edge of Pixel Clock. | ||
| [9] | HSP | Sensor Hsync Polarity |
| 0 = Sync Low. | ||
| 1 = Sync High. | ||
| [10] | VSP | Sensor Vsync Polarity |
| 0 = Sync Low. | ||
| 1 = Sync High. | ||
| [11:12] | COLORCTL | Special COLORCTL Processing |
| 00 = Normal Color. | ||
| 01 = Sepia effect, corresponding U,V component value is set at register CAP_SEPIA. | ||
| 10 = Negative picture. | ||
| 11 = Posterize image, the Y, U, V components posterizing factor are set at register CAP_POSTERIZE. | ||
| [18] | FBB | Field By Blank |
| Hardware will tag field0 or field1 by vertical blanking instead of FIELD flag in CCIR-656 mode. | ||
| 0 = Field by blank Disabled. | ||
| 1 = Field by blank Enabled. |
Definition at line 1771 of file NUC472_442.h.
| __I uint32_t SYS_T::PDID |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SYS_PDID | Part Device Identification Number |
| This register reflects device part number code. | ||
| S/W can read this register to identify which device is used. |
Definition at line 23277 of file NUC472_442.h.
| __IO uint32_t SPI_T::PDMACTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TXPDMAEN | Transmit DMA Enable Control |
| 0 = Transmit PDMA Disabled. | ||
| 1 = Transmit PDMA Enabled. | ||
| Note: Setting this bit to 1 will start the transmit PDMA process. | ||
| SPI controller will issue request to PDMA controller automatically. | ||
| Hardware will clear this bit to 0 automatically after PDMA transfer done. | ||
| [1] | RXPDMAEN | Receive PDMA Enable Control |
| 0 = Receive PDMA Disabled. | ||
| 1 = Receive PDMA Enabled. | ||
| Note: Setting this bit to 1 will start the receive PDMA process. | ||
| The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. | ||
| This bit will be cleared to 0 by hardware automatically after PDMA transfer is done. | ||
| [2] | PDMARST | PDMA Reset |
| 0 = No effect. | ||
| 1 = Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically. |
Definition at line 22873 of file NUC472_442.h.
| __I uint32_t EADC_T::PENDSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | STPF7_0 | A/D SAMPLE07~SAMPLE00 Start Of Conversion Pending Flag |
| 0 = There is no pending conversion for SAMPLE0x. | ||
| 1 = SAMPLE0x ADC start of conversion is pending. | ||
| Note: This bit remains 1 during pending state, when the respective ADC conversion is started, the STPF bit is automatically cleared to 0. | ||
| Note: x = 0~7. | ||
| [8:15] | STPF15_8 | A/D SAMPLE17~SAMPLE10 Start Of Conversion Pending Flag |
| 0 = There is no pending conversion for SAMPLE1x. | ||
| 1 = SAMPLE1x ADC start of conversion is pending. | ||
| Note: This bit remains 1 during pending state, when the respective ADC conversion is started, the STPF bit is automatically cleared to 0. | ||
| Note: x = 0~7. |
Definition at line 7835 of file NUC472_442.h.
| __IO uint32_t EPWM_T::PERIOD |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | PERIOD | PWM Period Register |
| Edge aligned: | ||
| Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar. | ||
| Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar. | ||
| Centre aligned: | ||
| Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar. | ||
| Duty = (Duty *2 + 1) * EPWMx_CLK period * pre-scalar. |
Definition at line 14103 of file NUC472_442.h.
| __IO uint32_t PWM_T::PERIOD[6] |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | PERIOD | PWM Period Register |
| PERIOD determines the PWM period. | ||
| PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(PERIOD+1)]; where xy, could be 01, 23 or 45, depends on selected PWM channel. | ||
| For Edge-aligned mode: | ||
| l Duty ratio = (CMP+1)/(PERIOD+1). | ||
| l CMP >= PERIOD: PWM output is always high. | ||
| l CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit. | ||
| l CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit. | ||
| For Center-aligned mode: | ||
| l Duty ratio = [(2 x CMP) + 1]/[2 x (PERIOD+1)]. | ||
| l CMP > PERIOD: PWM output is always high. | ||
| l CMP <= PERIOD: PWM low width = 2 x (PERIOD-CMP) + 1 unit; PWM high width = (2 x CMP) + 1 unit. | ||
| l CMP = 0: PWM low width = 2 x PERIOD + 1 unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note1: Any write to PERIOD will take effect in next PWM cycle. | ||
| Note2: When PWM operating at center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE. | ||
| If PERIOD equal to 0xFFFF, the PWM will work unpredictable. | ||
| Note3: When PERIOD value is set to 0, PWM output is always high. |
Definition at line 19183 of file NUC472_442.h.
| __IO uint32_t EPWM_T::PERIODCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:3] | PERIODCNT | PIF Compared Counter |
| The register sets the count number which defines how many times of PWM period occurs to set bit PIF to request the PWM period interrupt. | ||
| PIF will be set in every (1 + PERIODCNT[3:0]) times of PWM period or center point defined by INTTYPE when EPWM_CTL [8] occurred. |
Definition at line 14341 of file NUC472_442.h.
| __IO uint32_t OTG_T::PHYCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SWPDEN | Software Control Pull-Down On Data Lines Enable Control |
| 0 = Pull-down resistors on data lines is controlled by OTG control logic. | ||
| 1 = Pull-down resistors on data lines is controlled by software. | ||
| Note: Software must set this bit high before controlling DPPDEN and DMPDEN. | ||
| [1] | DPPDEN | D+ Pull-Down Enable Control Set SWPDEN to TRUE before using this function |
| 0 = 15 kOhm resistor pull-down on D+ pin Disabled. | ||
| 1 = 15 kOhm resistor pull-down on D+ pin Enabled. | ||
| [2] | DMPDEN | D- Pull-Down Enable Control Set SWPDEN to TRUE before using this function |
| 0 = 15 kOhm resistor pull-down on D- pin Disabled. | ||
| 1 = 15 kOhm resistor pull-down on D- pin Enabled. | ||
| [5] | VBSTSPOL | Off-Chip USB VBUS Power Status Polarity |
| The polarity of off-chip USB VBUS LDO valid depends on the selected component. | ||
| This bit provides the inversed option of off-chip USB VBUS LDO valid. | ||
| 0 = The polarity of off-chip USB VBUS LDO valid not inversed. | ||
| 1 = The polarity of off-chip USB VBUS LDO valid inversed. | ||
| [6] | VBENPOL | Off-Chip USB VBUS Power Enable Polarity |
| The OTG controller will enable off-chip USB VBUS LDO to provide VBUS power when need. | ||
| The polarity of enabling off-chip BSU VBUS LDO (high active or low active) depends on the selected component. | ||
| This bit provides the inverse option of off-chip USB VBUS LDO enable. | ||
| 0 = The polarity of enabling off-chip USB VBUS LDO from the OTG controller not inversed. | ||
| 1 = The polarity of enabling off-chip USB VBUS LDO from the OTG controller inversed. | ||
| [7] | IDDETEN | ID Detection Enable |
| 0 = Sampling on ID pin Enabled. | ||
| 1 = Sampling on ID pin Disabled. | ||
| [8] | PHYCLK | PHY Input Clock Selection |
| 0 = PHY input clock is12 MHz. | ||
| 1 = PHY input clock is 24 MHz. | ||
| [9] | OTGPHYEN | OTG PHY Enable Control When Device Configured As OTG-Device |
| When device is configured as OTG-device, hardware will not enable OTG PHY automatically. | ||
| Software can set OTG_EN to enable OTG PHY. | ||
| 0 = OTG PHY Disabled. | ||
| 1 = OTG PHY Enabled. |
Definition at line 17820 of file NUC472_442.h.
| __IO uint32_t USBD_T::PHYCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [8] | DPPUEN | DP Pull-Up |
| 0 = Pull-up resistor on D+ Disabled. | ||
| 1 = Pull-up resistor on D+ Enabled. | ||
| [9] | PHYEN | PHY Suspend Enable Control |
| 0 = The USB PHY is suspend. | ||
| 1 = The USB PHY is not suspend. | ||
| [24] | WKEN | Wake-Up Enable Control |
| 0 = The wake-up function Disabled. | ||
| 1 = The wake-up function Enabled. | ||
| [31] | VBUSDET | VBUS Status |
| 0 = The VBUS is not detected yet. | ||
| 1 = The VBUS is detected. |
Definition at line 27965 of file NUC472_442.h.
| __I uint32_t GPIO_T::PIN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PIN0 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [1] | PIN1 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [2] | PIN2 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [3] | PIN3 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [4] | PIN4 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [5] | PIN5 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [6] | PIN6 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [7] | PIN7 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [8] | PIN8 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [9] | PIN9 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [10] | PIN10 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [11] | PIN11 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [12] | PIN12 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [13] | PIN13 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [14] | PIN14 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. | ||
| [15] | PIN15 | Port N Bit M Pin Value |
| Each bit of the register reflects the actual status of the respective port pin. | ||
| If bit is 1, it indicates the corresponding pin status is high, else the pin status is low. |
Definition at line 15493 of file NUC472_442.h.
| __IO uint32_t SC_T::PINCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PWREN | SC_PWREN Pin Signal |
| Software can set PWREN and PWRINV to decide SC_PWR pin is in high or low level. | ||
| Write this field to drive SC_PWR pin | ||
| Refer PWRINV description for programming SC_PWR pin voltage level. | ||
| Read this field to get SC_PWR pin status. | ||
| 0 = SC_PWR pin status is low. | ||
| 1 = SC_PWR pin status is high. | ||
| Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field when operating in these modes. | ||
| [1] | SCRST | SCRST Pin Signal |
| This bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit. | ||
| Write this field to drive SCRST pin. | ||
| 0 = Drive SCRST pin to low. | ||
| 1 = Drive SCRST pin to high. | ||
| Read this | ||
| field to get SCRST pin status. | ||
| 0 = SCRST pin status is low. | ||
| 1 = SCRST pin status is high. | ||
| Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field when operating in these modes. | ||
| [6] | CLKKEEP | SC Clock Enable Control |
| 0 = SC clock generation Disabled. | ||
| 1 = SC clock always keeps free running. | ||
| Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field when operating in these modes. | ||
| [9] | SCDOOUT | SC Data Output Pin |
| This bit is the pin status of SCDOOUT but user can drive SCDOOUT pin to high or low by setting this bit. | ||
| 0 = Drive SCDOOUT pin to low. | ||
| 1 = Drive SCDOOUT pin to high. | ||
| Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field when SC is in these modes. | ||
| [11] | PWRINV | SC_POW Pin Inverse |
| This bit is used for inverse the SC_POW pin. | ||
| There are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0]). | ||
| PWRINV is bit 1 and PWREN is bit 0 for SC_POW_Pin as high or low voltage selection. | ||
| PWRINV is 0 and PWREN is 0, than SC_POW Pin output 0. | ||
| PWRINV is 0 and PWREN is 1, than SC_POW Pin output 1. | ||
| PWRINV is 1 and PWREN is 0, than SC_POW Pin output 1. | ||
| PWRINV is 1 and PWREN is 1, than SC_POW Pin output 0. | ||
| Note: Software must select PWRINV before Smart Card is enabled by SCEN (SC_CTL[0]). | ||
| [16] | DATSTS | This bit is the pin status of SC_DAT |
| 0 = The SC_DAT pin is low. | ||
| 1 = The SC_DAT pin is high. | ||
| [17] | PWRSTS | SC_PWR Pin Signal |
| This bit is the pin status of SC_PWR | ||
| 0 = SC_PWR pin to low. | ||
| 1 = SC_PWR pin to high. | ||
| Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| This bit is not allowed to program when SC is operated at these modes. | ||
| [18] | RSTSTS | SC_RST Pin Signals |
| This bit is the pin status of SC_RST | ||
| 0 = SC_RST pin is low. | ||
| 1 = SC_RST pin is high. | ||
| Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| This bit is not allowed to program when SC is operated at these modes. | ||
| [30] | SYNC | SYNC Flag Indicator |
| Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register. | ||
| 0 = Synchronizing is completion, user can write new data to SC_PINCTL register. | ||
| 1 = Last value is synchronizing. | ||
| Note: This bit is read only. |
Definition at line 21639 of file NUC472_442.h.
| __IO uint32_t CAP_T::PKTBA0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | BASEADDR | System Memory Packet Base Address 0 |
| Word aligns address; ignore the bits [1:0]. |
Definition at line 2120 of file NUC472_442.h.
| __IO uint32_t CAP_T::PKTBA1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | BASEADDR | System Memory Packet Base Address 1 |
| Word aligns address; ignore the bits [1:0]. |
Definition at line 2132 of file NUC472_442.h.
| __IO uint32_t CAP_T::PKTSL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | PKTSHML | Packet Scaling Horizontal Factor M (Lower 8-Bit) |
| Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor. | ||
| The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor. | ||
| The output image width will be equal to the image width * N/M. | ||
| Note: The value of N must be equal to or less than M. | ||
| [8:15] | PKTSHNL | Packet Scaling Horizontal Factor N (Lower 8-Bit) |
| Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. | ||
| The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor. | ||
| [16:23] | PKTSVML | Packet Scaling Vertical Factor M (Lower 8-Bit) |
| Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. | ||
| The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor. | ||
| The output image width will be equal to the image height * N/M. | ||
| Note: The value of N must be equal to or less than M. | ||
| [24:31] | PKTSVNL | Packet Scaling Vertical Factor N (Lower 8-Bit) |
| Specify the lower 8-bit of numerator part (N) of the vertical scaling factor. | ||
| The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor |
Definition at line 1929 of file NUC472_442.h.
| __IO uint32_t CAP_T::PKTSM |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | PKTSHMH | Packet Scaling Horizontal Factor M (Higher 8-Bit) |
| Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor. | ||
| Please refer to the register CAP_PKTSL?for the detailed operation. | ||
| [8:15] | PKTSHNH | Packet Scaling Horizontal Factor N (Higher 8-Bit) |
| Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. | ||
| Please refer to the register CAP_PKTSL for the detailed operation. | ||
| [16:23] | PKTSVMH | Packet Scaling Vertical Factor M (Higher 8-Bit) |
| Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. | ||
| Please refer to the register CAP_PKTSL to check the cooperation between these two registers. | ||
| [24:31] | PKTSVNH | Packet Scaling Vertical Factor N (Higher 8-Bit) |
| Specify the higher 8-bit of numerator part (N) of the vertical scaling factor. | ||
| Please refer to the register CAP_PKTSL?to check the cooperation between these two registers. |
Definition at line 2042 of file NUC472_442.h.
| __IO uint32_t CLK_T::PLL2CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | PLL2DIV | PLL2 Divider Control |
| PLL2 clock frequency = (480 MHz) / 2 / (PLL2DIV + 1). | ||
| Note: Max. PLL frequency 240 MHz when XTL12M. | ||
| [8] | PLL2CKEN | USB OHY 480 MHz Enable Control |
| This bit enables USB PHY PLL (480 MHz), and user needs to care extend 12 MHz source. | ||
| 0 = USB PHY PLL (480 MHz) Disabled. | ||
| 1 = USB PHY PLL (480 MHz) Enabled. |
Definition at line 3435 of file NUC472_442.h.
| __IO uint32_t CLK_T::PLLCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:8] | FBDIV | PLL Feedback Divider Control Pins |
| Refer to the formulas below the table. | ||
| [9:13] | INDIV | PLL Input Divider Control Pins |
| Refer to the formulas below the table. | ||
| [14:15] | OUTDV | PLL Output Divider Control Pins |
| Refer to the formulas below the table. | ||
| [16] | PD | Power-Down Mode |
| If set the PWR_DOWN_EN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. | ||
| 0 = PLL is in normal mode. | ||
| 1 = PLL is in Power-down mode (default). | ||
| [17] | BP | PLL Bypass Control |
| 0 = PLL is in normal mode (default). | ||
| 1 = PLL clock output is same as clock input (XTALin). | ||
| [18] | OE | PLL OE (FOUT Enable) Pin Control |
| 0 = PLL FOUT Enabled. | ||
| 1 = PLL FOUT is fixed low. | ||
| [19] | PLLSRC | PLL Source Clock Selection |
| 0 = PLL source clock from HXT. | ||
| 1 = PLL source clock from HIRC. | ||
| [20] | PLLREMAP | PLL Remap Enable Bit |
| 0 = PLL remap enable. | ||
| 1 = PLL remap disable. |
Definition at line 3418 of file NUC472_442.h.
| __IO uint32_t CAP_T::PLNSL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | PLNSHML | Planar Scaling Horizontal Factor M (Lower 8-Bit) |
| Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor. | ||
| The lower 8-bit will be cascaded with higher 8-bit (PNDSHMH) to form a 16-bit denominator (M) of vertical factor. | ||
| The output image width will be equal to the image width * N/M. | ||
| Note: The value of N must be equal to or less than M. | ||
| [8:15] | PLNSHNL | Planar Scaling Horizontal Factor N (Lower 8-Bit) |
| Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. | ||
| The lower 8-bit will be cascaded with higher 8-bit (PNDSHNH) to form a 16-bit numerator of horizontal factor. | ||
| [16:23] | PLNSVML | Planar Scaling Vertical Factor M (Lower 8-Bit) |
| Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. | ||
| The lower 8-bit will be cascaded with higher 8-bit (PNDSVMH) to form a 16-bit denominator (M) of vertical factor. | ||
| The output image width will be equal to the image height * N/M. | ||
| Note: The value of N must be equal to or less than M. | ||
| [24:31] | PLNSVNL | Planar Scaling Vertical Factor N (Lower 8-Bit) |
| Specify the lower 8-bit of numerator part (N) of the vertical scaling factor. | ||
| The lower 8-bit will be cascaded with higher 8-bit (PNDSVNH) to form a 16-bit numerator of vertical factor. |
Definition at line 1955 of file NUC472_442.h.
| __IO uint32_t CAP_T::PLNSM |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | PLNSHMH | Planar Scaling Horizontal Factor M (Higher 8-Bit) |
| Specifies the higher 8-bit of denominator part (M) of the horizontal scaling factor | ||
| For detailed programming, please refer to the register CAP_PLNSL | ||
| [8:15] | PLNSHNH | Planar Scaling Horizontal Factor N (Higher 8-Bit) |
| Specifies the higher 8-bit of numerator part (N) of the horizontal scaling factor. | ||
| For detailed programming, please refer to the register CAP_PLNSL | ||
| [16:23] | PLNSVMH | Planar Scaling Vertical Factor M (Higher 8-Bit) |
| Specifies the lower 8-bit of denominator part (M) of the vertical scaling factor. | ||
| For detailed programming, please refer to the register CAP_PLNSL | ||
| [24:31] | PLNSVNH | Planar Scaling Vertical Factor N (Higher 8-Bit) |
| Specifies the higher 8-bit of numerator part (N) of the vertical scaling factor. | ||
| For detailed programming, please refer to the register CAP_PLNSL |
Definition at line 2064 of file NUC472_442.h.
| __IO uint32_t PWM_T::POEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0:5] | POEN | PWM Pin Output Enable Control |
| 0 = PWM pin at tri-state. | ||
| 1 = PWM pin in output mode. | ||
| Note: Each bit controls the corresponding PWM channel. |
Definition at line 19517 of file NUC472_442.h.
| __IO uint32_t SYS_T::PORCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | POROFF | Power-On-Reset Enable Control (Write Protect) |
| When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. | ||
| User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. | ||
| The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: | ||
| /RESET, Watch dog, LVR reset, BOD reset, ICE reset command and the software-chip reset function | ||
| This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address GCR_BA+0x100. |
Definition at line 23632 of file NUC472_442.h.
| __IO uint32_t CAP_T::POSTERIZE |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | VCOMP | V Component Posterizing Factor |
| Final_V_Out = Original_V[7:0] & V_Posterizing_Factor. | ||
| [8:15] | UCOMP | U Component Posterizing Factor |
| Final_U_Out = Original_U[7:0] & U_Posterizing_Factor. | ||
| [16:23] | YCOMP | Y Component Posterizing Factor |
| Final_Y_Out = Original_Y[7:0] & Y_Posterizing_Factor. |
Definition at line 1820 of file NUC472_442.h.
| __O uint32_t PDMA_T::PRICLR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | FPRICLR | PDMA Fix Priority Clear Bit [X] |
| Set this bit to 1 to clear fixed priority level. | ||
| 0 = No effect. | ||
| 1 = Set PDMA channel [x] to be round-robin priority channel. | ||
| Note: This field is Write-Only, and software can indicate the channel priority by reading PDMA_FPIOSEL register. |
Definition at line 18332 of file NUC472_442.h.
| __IO uint32_t PDMA_T::PRISET |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | FPRISET | PDMA Fixed Priority Setting Bit[X] |
| Set this bit to 1 to enable fix priority level. | ||
| 0 = No effect. | ||
| 1 = Set PDMA channel [x] be fixed priority channel. | ||
| The PDMA channel priority is shown in the following table. |
Definition at line 18317 of file NUC472_442.h.
| __IO uint32_t CRPT_T::PRNG_CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | START | Start PRNG Engine |
| 0 = Stop PRNG engine. | ||
| 1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated. | ||
| [1] | SEEDRLD | Reload New Seed For PRNG Engine |
| 0 = Generating key based on the current seed. | ||
| 1 = Reload new seed. | ||
| [2:3] | KEYSZ | PRNG Generate Key Size |
| 00 = 64 bits. | ||
| 01 = 128 bits. | ||
| 10 = 192 bits. | ||
| 11 = 256 bits. | ||
| [8] | BUSY | PRNG Busy (Read Only) |
| 0 = PRNG engine is idle. | ||
| 1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. |
Definition at line 4225 of file NUC472_442.h.
| __I uint32_t CRPT_T::PRNG_KEY0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYx | Store PRNG Generated Key (Read Only) |
| The bits store the key that is generated by PRNG. |
Definition at line 4249 of file NUC472_442.h.
| __I uint32_t CRPT_T::PRNG_KEY1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYx | Store PRNG Generated Key (Read Only) |
| The bits store the key that is generated by PRNG. |
Definition at line 4261 of file NUC472_442.h.
| __I uint32_t CRPT_T::PRNG_KEY2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYx | Store PRNG Generated Key (Read Only) |
| The bits store the key that is generated by PRNG. |
Definition at line 4273 of file NUC472_442.h.
| __I uint32_t CRPT_T::PRNG_KEY3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYx | Store PRNG Generated Key (Read Only) |
| The bits store the key that is generated by PRNG. |
Definition at line 4285 of file NUC472_442.h.
| __I uint32_t CRPT_T::PRNG_KEY4 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYx | Store PRNG Generated Key (Read Only) |
| The bits store the key that is generated by PRNG. |
Definition at line 4297 of file NUC472_442.h.
| __I uint32_t CRPT_T::PRNG_KEY5 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYx | Store PRNG Generated Key (Read Only) |
| The bits store the key that is generated by PRNG. |
Definition at line 4309 of file NUC472_442.h.
| __I uint32_t CRPT_T::PRNG_KEY6 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYx | Store PRNG Generated Key (Read Only) |
| The bits store the key that is generated by PRNG. |
Definition at line 4321 of file NUC472_442.h.
| __I uint32_t CRPT_T::PRNG_KEY7 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYx | Store PRNG Generated Key (Read Only) |
| The bits store the key that is generated by PRNG. |
Definition at line 4333 of file NUC472_442.h.
| __O uint32_t CRPT_T::PRNG_SEED |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | CRPT_PRNG_SEED | Seed For PRNG (Write Only) |
| The bits store the seed for PRNG engine. |
Definition at line 4237 of file NUC472_442.h.
| __IO uint32_t CLK_T::PWRCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXTEN | 4~24 MHz External High-Speed Crystal Enable Control (Write Protect) |
| The bit default value is set by flash controller user configuration register config0 [26:24]. | ||
| When the default clock source is from 4~24 MHz external high-speed crystal, this bit is set to 1 automatically | ||
| 0 = HXT Disabled. | ||
| 1 = HXT Enabled. | ||
| [1] | LXTEN | LXT Enable Control (Write Protect) |
| 0 = LXT Disabled. | ||
| 1 = LXT (Normal operation) Enabled. | ||
| [2] | HIRCEN | HIRC Enable Control (Write Protect) |
| 0 = HIRC Disabled. | ||
| 1 = HIRC Enabled. | ||
| [3] | LIRCEN | 10 KHz Internal Low-Speed Oscillator Enable Control (Write Protect) |
| 0 = LIRC Disabled. | ||
| 1 = LIRC Enabled (default 1). | ||
| [4] | PDWKDLY | Wake-Up Delay Counter Enable Control (Write Protect) |
| When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. | ||
| The delayed clock cycle is 4096 clock cycles when chip work at HXT, and 256 clock cycles when chip works at HIRC. | ||
| 0 = Clock cycles delay Disabled. | ||
| 1 = Clock cycles delay Enabled. | ||
| [5] | PDWKIEN | Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect) |
| 0 = Power-down Mode Wake-up Interrupt Disabled. | ||
| 1 = Power-down Mode Wake-up Interrupt Enabled. | ||
| Note: The interrupt will occur when both PDWKIF and PDWKIEN are high. | ||
| [6] | PDWKIF | Power-Down Mode Wake-Up Interrupt Status |
| Set by "power-down wake-up event", it indicates that resume from Power-down mode" | ||
| The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD, RTC or SDHOST wake-up occurred | ||
| Note1: Write 1 to clear the bit to 0. | ||
| Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. | ||
| [7] | PDEN | System Power-Down Enable Control (Write Protect) |
| When this bit is set to 1, Power-down mode is enabled and chip power-down behavior will depend on the PDEN bit. | ||
| (a) If the PDEN is 0, then the chip enters Power-down mode immediately after | ||
| the PWR_DOWN_EN bit set. ( default) | ||
| (b) if the PDEN is 1, then the chip keeps active till the CPU sleep mode is also | ||
| active and then the chip enters Power-down mode | ||
| When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set | ||
| this bit again for next power-down. | ||
| In Power-down mode, HXT and the HIRC will be disabled in this mode, but the LXT and | ||
| LIRC are not controlled by Power-down mode. | ||
| In Power-down mode, the PLL and system clock are disabled, and ignored the clock | ||
| source selection. The clocks of peripheral are not controlled by Power-down mode, if the | ||
| peripheral clock source is from LXT or the LIRC. | ||
| 0 = Chip operating normally or chip in idle mode by WFI command. | ||
| 1 = Chip enters Power-down mode instant or waits CPU sleep command WFI. | ||
| [8] | PDWTCPU | This Bit Control The Power-Down Entry Condition (Write Protect) |
| 0 = Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1. | ||
| 1 = Chip enters Power-down mode when the both PDEN and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction. | ||
| [9] | DBPDEN | Chip Entering Power-Down Even ICE Connected |
| 0 = Chip enters power-down disabled in Debug mode. | ||
| 1 = Chip enters power-down enabled in Debug mode. |
Definition at line 2841 of file NUC472_442.h.
| __I uint32_t PWM_T::RCAPDAT0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | RCAPDAT | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition. |
Definition at line 19591 of file NUC472_442.h.
| __I uint32_t PWM_T::RCAPDAT1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | RCAPDAT | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition. |
Definition at line 19615 of file NUC472_442.h.
| __I uint32_t PWM_T::RCAPDAT2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | RCAPDAT | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition. |
Definition at line 19639 of file NUC472_442.h.
| __I uint32_t PWM_T::RCAPDAT3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | RCAPDAT | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition. |
Definition at line 19663 of file NUC472_442.h.
| __I uint32_t PWM_T::RCAPDAT4 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | RCAPDAT | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition. |
Definition at line 19687 of file NUC472_442.h.
| __I uint32_t PWM_T::RCAPDAT5 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | RCAPDAT | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition. |
Definition at line 19711 of file NUC472_442.h.
| __IO uint32_t SYS_T::REGLCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | REGLCTL | Register Write-Protection Disable Index (Read Only) |
| 0 = Write-protection Enabled for writing protected registers. | ||
| Any write to the protected register is ignored. | ||
| 1 = Write-protection Disabled for writing protected registers. | ||
| The Protected registers are: | ||
| SYS_IPRST0: address 0x4000_0008 | ||
| SYS_BODCTL: address 0x4000_0018 | ||
| SYS_PORCTL: address 0x4000_0024 | ||
| PWRCON: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear) | ||
| APBCLK bit[0]: address 0x4000_0208 (bit[0] is watchdog clock enable) | ||
| CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select) | ||
| CLKSEL1 bit[1:0]: address 0x4000_0214 (for watchdog clock source select) | ||
| NMI_SEL]: address 0x4000_0300 (for NMI source select) | ||
| ISPCON: address 0x4000_5000 (Flash ISP Control register) | ||
| ISPTRG: address 0x4000_5010 (ISP Trigger Control register) | ||
| WTCR: address 0x4004_0000 | ||
| FATCON: address 0x4000_5018 | ||
| TAMPER: address 0x400E_1000 | ||
| [0:7] | SYS_REGLCTL | Register Write-Protection Code (Write Only) |
| Some registers have write-protection function. | ||
| Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. | ||
| After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. |
Definition at line 24177 of file NUC472_442.h.
| __IO uint32_t PDMA_T::REQSEL0_3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:4] | REQSRC0 | Channel 0 Selection |
| This filed defines which peripheral is connected to PDMA channel 0. | ||
| Software can configure the peripheral by setting REQSRC0. | ||
| 00000 = Connect to SPI0_TX. | ||
| 00001 = Connect to SPI1_TX. | ||
| 00010 = Connect to SPI2_TX. | ||
| 00011 = Connect to SPI3_TX. | ||
| 00100 = Connect to UART0_TX. | ||
| 00101 = Connect to UART1_TX. | ||
| 00110 = Connect to UART2_TX. | ||
| 00111 = Connect to UART3_TX. | ||
| 01000 = Connect to UART4_TX. | ||
| 01001 = Connect to UART5_TX. | ||
| 01010 = Reserved. | ||
| 01011 = Connect to I2S_TX. | ||
| 01100 = Connect to I2S1_TX. | ||
| 01101 = Connect to SPI0_RX. | ||
| 01110 = Connect to SPI1_RX. | ||
| 01111 = Connect to SPI2_RX. | ||
| 10000 = Connect to SPI3_RX. | ||
| 10001 = Connect to UART0_RX. | ||
| 10010 = Connect to UART1_RX. | ||
| 10011 = Connect to UART2_RX. | ||
| 10100 = Connect to UART3_RX. | ||
| 10101 = Connect to UART4_RX. | ||
| 10110 = Connect to UART5_RX. | ||
| 10111 = Reserved. | ||
| 11000 = Connect to ADC. | ||
| 11001 = Connect to I2S_RX. | ||
| 11010 = Connect to I2S1_RX. | ||
| Other = Reserved. | ||
| [8:12] | REQSRC1 | Channel 1 Selection |
| This filed defines which peripheral is connected to PDMA channel 1. | ||
| Software can configure the peripheral setting by REQSRC1. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. | ||
| [16:20] | REQSRC2 | Channel 2 Selection |
| This filed defines which peripheral is connected to PDMA channel 2. | ||
| Software can configure the peripheral setting by REQSRC2. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. | ||
| [24:28] | REQSRC3 | Channel 3 Selection |
| This filed defines which peripheral is connected to PDMA channel 3. | ||
| Software can configure the peripheral setting by REQSRC3. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. |
Definition at line 18511 of file NUC472_442.h.
| __IO uint32_t PDMA_T::REQSEL12_15 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:4] | REQSRC12 | Channel 12 Selection |
| This filed defines which peripheral is connected to PDMA channel 12. | ||
| Software can configure the peripheral setting by REQSRC12. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. | ||
| [8:12] | REQSRC13 | Channel 13 Selection |
| This filed defines which peripheral is connected to PDMA channel 13. | ||
| Software can configure the peripheral setting by REQSRC13. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. | ||
| [16:20] | REQSRC14 | Channel 14 Selection |
| This filed defines which peripheral is connected to PDMA channel 14. | ||
| Software can configure the peripheral setting by REQSRC14. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. | ||
| [24:28] | REQSRC15 | Channel 15 Selection |
| This filed defines which peripheral is connected to PDMA channel 15. | ||
| Software can configure the peripheral setting by REQSRC15. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. |
Definition at line 18601 of file NUC472_442.h.
| __IO uint32_t PDMA_T::REQSEL4_7 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:4] | REQSRC4 | Channel 0 Selection |
| This filed defines which peripheral is connected to PDMA channel 4. | ||
| Software can configure the peripheral setting by REQSRC4. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. | ||
| [8:12] | REQSRC5 | Channel 1 Selection |
| This filed defines which peripheral is connected to PDMA channel 5. | ||
| Software can configure the peripheral setting by REQSRC5. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. | ||
| [16:20] | REQSRC6 | Channel 6 Selection |
| This filed defines which peripheral is connected to PDMA channel 6. | ||
| Software can configure the peripheral setting by REQSRC6. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. | ||
| [24:28] | REQSRC7 | Channel 7 Selection |
| This filed defines which peripheral is connected to PDMA channel 7. | ||
| Software can configure the peripheral setting by REQSRC7. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. |
Definition at line 18541 of file NUC472_442.h.
| __IO uint32_t PDMA_T::REQSEL8_11 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:4] | REQSRC8 | Channel 8 Selection |
| This filed defines which peripheral is connected to PDMA channel 8. | ||
| Software can configure the peripheral setting by REQSRC8. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. | ||
| [8:12] | REQSRC9 | Channel 9 Selection |
| This filed defines which peripheral is connected to PDMA channel 9. | ||
| Software can configure the peripheral setting by REQSRC9. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. | ||
| [16:20] | REQSRC10 | Channel 10 Selection |
| This filed defines which peripheral is connected to PDMA channel 10. | ||
| Software can configure the peripheral setting by REQSRC10. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. | ||
| [24:28] | REQSRC11 | Channel 11 Selection |
| This filed defines which peripheral is connected to PDMA channel 11. | ||
| Software can configure the peripheral setting by REQSRC11. | ||
| The channel configuration is the same as REQSRC0 field. | ||
| Please refer to the explanation of REQSRC0. |
Definition at line 18571 of file NUC472_442.h.
| __I uint32_t CAN_T::RESERVE0[1] |
Definition at line 1293 of file NUC472_442.h.
| __I uint32_t CAN_T::RESERVE1[8] |
Definition at line 1297 of file NUC472_442.h.
| __I uint32_t CAN_T::RESERVE2[6] |
Definition at line 1327 of file NUC472_442.h.
| __I uint32_t CAN_T::RESERVE3[6] |
Definition at line 1355 of file NUC472_442.h.
| __I uint32_t CAN_T::RESERVE4[6] |
Definition at line 1383 of file NUC472_442.h.
| __I uint32_t SDH_T::RESP0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | RESPTK0 | SD Receiving Response Token 0 |
| SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. | ||
| This field contains response bit 47-16 of the response token. |
Definition at line 22450 of file NUC472_442.h.
| __I uint32_t SDH_T::RESP1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | RESPTK1 | SD Receiving Response Token 1 |
| SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. | ||
| This register contains the bit 15-8 of the response token. |
Definition at line 22463 of file NUC472_442.h.
| __O uint32_t WWDT_T::RLDCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | RLDCNT | WWDT Reload Counter Bit |
| Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. | ||
| Note: Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. | ||
| If software writes RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will generate immediately. |
Definition at line 28581 of file NUC472_442.h.
| __I uint32_t EMAC_T::RPCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | RPCNT | MAC Receive Pause Count |
| The RPCNT keeps the OPERAND field of the PAUSE control frame. | ||
| It indicates how many slot time (512 bit time) the TX of EMAC will be paused. |
Definition at line 13027 of file NUC472_442.h.
| __IO uint32_t SYS_T::RSTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PORF | The PORF Flag Is Set By The "Reset Signal" From The Power-On Reset (POR) Controller Or Bit CHIPRST (SYS_IPRST0[0]) To Indicate The Previous Reset Source |
| 0 = No reset from POR or CHIPRST. | ||
| 1 = Power-On Reset (POR) or CHIPRST had issued the reset signal to reset the system. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [1] | PINRF | The PINRF Flag Is Set By The "Reset Signal" From The /RESET Pin To Indicate The Previous Reset Source |
| 0 = No reset from /RESET pin. | ||
| 1 = The Pin /RESET had issued the reset signal to reset the system. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [2] | WDTRF | The WDTRF Flag Is Set By The "Reset Signal" From The Watchdog Timer To Indicate The Previous Reset Source |
| 0 = No reset from watchdog timer. | ||
| 1 = The watchdog timer had issued the reset signal to reset the system. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [3] | LVRF | The LVRF Flag Is Set By The "Reset Signal" From The Low-Voltage-Reset Controller To Indicate The Previous Reset Source |
| 0 = No reset from LVR. | ||
| 1 = The LVR controller had issued the reset signal to reset the system. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [4] | BODRF | The BODRF Flag Is Set By The "Reset Signal" From The Brown-Out-Detector To Indicate The Previous Reset Source |
| 0 = No reset from BOD. | ||
| 1 = The BOD had issued the reset signal to reset the system. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [5] | SYSRF | The SYSRF Flag Is Set By The "Reset Signal" From The Cortex(TM)-M4 Core To Indicate The Previous Reset Source |
| 0 = No reset from Cortex(TM)-M4. | ||
| 1 = The Cortex(TM)-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex(TM)-M4 core. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [7] | CPURF | The CPURF Flag Is Set By Hardware If Software Writes CPURST (SYS_IPRST0[1]) 1 To Reset Cortex(TM)-M4 Core And Flash Memory Controller (FMC) |
| 0 = No reset from CPU. | ||
| 1 = The Cortex(TM)-M4 Core and FMC are reset by software setting CPURST to 1. | ||
| Note: Write 1 to clear this bit to 0. |
Definition at line 23315 of file NUC472_442.h.
| __O uint32_t RTC_T::RWEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | RWEN | RTC Register Access Enable Password (Write Only) |
| Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock. | ||
| [16] | RWENF | RTC Register Access Enable Flag (Read Only) |
| 0 = RTC register read/write Disabled. | ||
| 1 = RTC register read/write Enabled. | ||
| This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock. |
Definition at line 20436 of file NUC472_442.h.
| __I uint32_t I2S_T::RX |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | RX | Receive FIFO Bits |
| I2S contains 8 words (8x32 bit) data buffer for data receive. | ||
| Read this register to get data in FIFO. | ||
| The remaining data word number is indicated by RXCNT(I2S_STATUS[27:24]). |
Definition at line 17471 of file NUC472_442.h.
| __I uint32_t SPI_T::RX |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | RX | Data Receive Bits |
| There is 8-level FIFO buffer in this controller. | ||
| The data receive register holds the earliest datum received from SPI data input pin. | ||
| If the RXEMPTY bit, SPI_STATUS[8], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. | ||
| This is a read only register. |
Definition at line 23058 of file NUC472_442.h.
| __I uint32_t PS2_T::RXDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | DAT | Received Data |
| For host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2_RXDAT register. | ||
| CPU must read this register before next byte reception complete; otherwise, the data will be overwritten and RXOV(PS2_STATUS[6]) bit will be set to 1. |
Definition at line 18860 of file NUC472_442.h.
| __IO uint32_t EMAC_T::RXDSA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | RXDSA | Receive Descriptor Link-List Start Address |
| The RXDSA keeps the start address of receive descriptor link-list. | ||
| If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current receive descriptor start address register (EMAC_CRXDSA). | ||
| The RXDSA does not be updated by EMAC. | ||
| During the operation, EMAC will ignore the bits [1:0] of RXDSA. | ||
| This means that each RX descriptor always must locate at word boundary memory address. |
Definition at line 12373 of file NUC472_442.h.
| __O uint32_t EMAC_T::RXST |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | RXST | Receive Start Demand |
| If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled, the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted. | ||
| After the S/W has prepared the new RX descriptor for frame reception, it must issue a write command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception. | ||
| The EMAC_RXST is a write only register and read from this register is undefined. | ||
| The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state. |
Definition at line 12598 of file NUC472_442.h.
| __IO uint32_t SC_T::RXTOUT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:8] | RFTM | SC Receiver Buffer Time-Out (ETU Base) |
| The time-out counter resets and starts counting whenever the RX buffer received a new data word. | ||
| Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ). | ||
| Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5 | ||
| Note2: Fill all 0 to this field indicates to disable this function. |
Definition at line 21353 of file NUC472_442.h.
| __I uint32_t PWM_T::SBS[6] |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SYNCBUSY | PWM Synchronous Busy |
| When software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 counter operation mode CNTMOD (CONR[16]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. | ||
| Software needs to check this busy status before writes PWM_PERIOD0/PWM_CMPDAT0/ PWM_CLKPSC or switch PWM0 counter operation mode to make sure previous setting has been update completely. | ||
| This bit will be set when software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 operation mode CNTMOD (CONR[16]) and will be cleared by hardware automatically when PWM update these value completely. |
Definition at line 19741 of file NUC472_442.h.
| __IO uint32_t PDMA_T::SCATBA |
| Bits | Field | Descriptions |
|---|---|---|
| [16:31] | SCATBA | PDMA Scatter-Gather Descriptor Table Base Address Bits |
| In Scatter-Gather mode, this is the base address for calculating the next link - list address. | ||
| The next link address equation is. | ||
| Next Link Address = { SCATBA[15:0], EMBTA_NTAAR[15:2], 2'b00}. | ||
| Note: Only useful in Scatter-Gather mode. |
Definition at line 18450 of file NUC472_442.h.
| __IO uint32_t PDMA_T::SCATSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:15] | TEMPTYF | Table Empty Flag Bit [X] |
| This bit indicates which PDMA channel table has finished transmission and the operation mode is Stop mode | ||
| 0 = Not finished or not in Stop mode. | ||
| 1 = PDMA channel has finished transmission and the operation is Stop mode. | ||
| Note: This field is read only, but software can write 1 to clear. |
Definition at line 18417 of file NUC472_442.h.
| __IO uint32_t CRC_T::SEED |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SEED | CRC Seed Bits |
| This field indicates the CRC seed value. |
Definition at line 4059 of file NUC472_442.h.
| __IO uint32_t CAP_T::SEPIA |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | VCOMP | Define the constant V component while Sepia color effect is turned on. |
| [8:15] | UCOMP | Define the constant U component while Sepia color effect is turned on. |
Definition at line 1879 of file NUC472_442.h.
| __I uint32_t USBD_T::SETUP1_0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | SETUP0 | Setup Byte 0[7:0] |
| This register provides byte 0 of the last setup packet received. | ||
| For a Standard Device Request, the following bmRequestType information is returned. | ||
| Bit 7(Direction): | ||
| 0: Host to device | ||
| 1: Device to host | ||
| Bit 6-5 (Type): | ||
| 00: Standard | ||
| 01: Class | ||
| 10: Vendor | ||
| 11: Reserved | ||
| Bit 4-0 (Recipient) | ||
| 00000: Device | ||
| 00001: Interface | ||
| 00010: Endpoint | ||
| 00011: Other | ||
| Others: Reserved | ||
| [8:15] | SETUP1 | Setup Byte 1[15:8] |
| This register provides byte 1 of the last setup packet received. | ||
| For a Standard Device Request, the following bRequest Code information is returned. | ||
| 00000000 = Get Status. | ||
| 00000001 = Clear Feature. | ||
| 00000010 = Reserved. | ||
| 00000011 = Set Feature. | ||
| 00000100 = Reserved. | ||
| 00000101 = Set Address. | ||
| 00000110 = Get Descriptor. | ||
| 00000111 = Set Descriptor. | ||
| 00001000 = Get Configuration. | ||
| 00001001 = Set Configuration. | ||
| 00001010 = Get Interface. | ||
| 00001011 = Set Interface. | ||
| 00001100 = Synch Frame. |
Definition at line 27816 of file NUC472_442.h.
| __I uint32_t USBD_T::SETUP3_2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | SETUP2 | Setup Byte 2 [7:0] |
| This register provides byte 2 of the last setup packet received. | ||
| For a Standard Device Request, the least significant byte of the wValue field is returned. | ||
| [8:15] | SETUP3 | Setup Byte 3 [15:8] |
| This register provides byte 3 of the last setup packet received. | ||
| For a Standard Device Request, the most significant byte of the wValue field is returned. |
Definition at line 27832 of file NUC472_442.h.
| __I uint32_t USBD_T::SETUP5_4 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | SETUP4 | Setup Byte 4[7:0] |
| This register provides byte 4 of the last setup packet received. | ||
| For a Standard Device Request, the least significant byte of the wIndex is returned. | ||
| [8:15] | SETUP5 | Setup Byte 5[15:8] |
| This register provides byte 5 of the last setup packet received. | ||
| For a Standard Device Request, the most significant byte of the wIndex field is returned. |
Definition at line 27848 of file NUC472_442.h.
| __I uint32_t USBD_T::SETUP7_6 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | SETUP6 | Setup Byte 6[7:0] |
| This register provides byte 6 of the last setup packet received. | ||
| For a Standard Device Request, the least significant byte of the wLength field is returned. | ||
| [8:15] | SETUP7 | Setup Byte 7[15:8] |
| This register provides byte 7 of the last setup packet received. | ||
| For a Standard Device Request, the most significant byte of the wLength field is returned. |
Definition at line 27864 of file NUC472_442.h.
| __IO uint32_t CRPT_T::SHA_CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | START | SHA Engine Start |
| 0 = No effect. | ||
| 1 = Start SHA engine. BUSY flag will be set. | ||
| Note: This bit is always 0 when it's read back. | ||
| [1] | STOP | SHA Engine Stop |
| 0 = No effect. | ||
| 1 = Stop SHA engine. | ||
| Note: This bit is always 0 when it's read back. | ||
| [5] | DMALAST | SHA Last Block |
| In DMA mode, this bit must be set as beginning the last DMA cascade round. | ||
| In Non-DMA mode, this bit must be set as feeding in last byte of data. | ||
| [7] | DMAEN | SHA Engine DMA Enable Control |
| 0 = SHA_DMA engine Disabled. | ||
| The SHA engine operates in Non-DMA mode, and gets data from the port CRPT_SHA_DATIN. | ||
| 1 = SHA_DMA engine Enabled. | ||
| The SHA engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. | ||
| [8:10] | OPMODE | SHA Engine Operation Modes |
| 000 = SHA160. | ||
| 100 = SHA256. | ||
| 101 = SHA224. | ||
| Note: These bits can be read and written, but writing to them wouldn't take effect as BUSY is 1. | ||
| [22] | OUTSWAP | SHA Engine Output Data Swap |
| 0 = Keep the original order. | ||
| 1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. | ||
| [23] | INSWAP | SHA Engine Input Data Swap |
| 0 = Keep the original order. | ||
| 1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. |
Definition at line 6564 of file NUC472_442.h.
| __IO uint32_t CRPT_T::SHA_DATIN |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DATIN | SHA Engine Input Port |
| CPU feeds data to SHA engine through this port by checking CRPT_SHA_STS. Feed data as DATINREQ is 1. |
Definition at line 6771 of file NUC472_442.h.
| __I uint32_t CRPT_T::SHA_DGST0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DGST | SHA Digest Message Word |
| For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4. | ||
| For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6. | ||
| For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7. |
Definition at line 6600 of file NUC472_442.h.
| __I uint32_t CRPT_T::SHA_DGST1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DGST | SHA Digest Message Word |
| For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4. | ||
| For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6. | ||
| For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7. |
Definition at line 6614 of file NUC472_442.h.
| __I uint32_t CRPT_T::SHA_DGST2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DGST | SHA Digest Message Word |
| For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4. | ||
| For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6. | ||
| For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7. |
Definition at line 6628 of file NUC472_442.h.
| __I uint32_t CRPT_T::SHA_DGST3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DGST | SHA Digest Message Word |
| For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4. | ||
| For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6. | ||
| For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7. |
Definition at line 6642 of file NUC472_442.h.
| __I uint32_t CRPT_T::SHA_DGST4 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DGST | SHA Digest Message Word |
| For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4. | ||
| For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6. | ||
| For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7. |
Definition at line 6656 of file NUC472_442.h.
| __I uint32_t CRPT_T::SHA_DGST5 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DGST | SHA Digest Message Word |
| For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4. | ||
| For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6. | ||
| For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7. |
Definition at line 6670 of file NUC472_442.h.
| __I uint32_t CRPT_T::SHA_DGST6 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DGST | SHA Digest Message Word |
| For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4. | ||
| For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6. | ||
| For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7. |
Definition at line 6684 of file NUC472_442.h.
| __I uint32_t CRPT_T::SHA_DGST7 |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DGST | SHA Digest Message Word |
| For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4. | ||
| For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6. | ||
| For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7. |
Definition at line 6698 of file NUC472_442.h.
| __IO uint32_t CRPT_T::SHA_DMACNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | DMACNT | SHA Operation Byte Count |
| The CRPT_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode. | ||
| The CRPT_SHA_DMACNT is 32-bit and the maximum of byte count is 4G bytes. | ||
| CRPT_SHA_DMACNT can be read and written. | ||
| Writing to CRPT_SHA_DMACNT while the SHA accelerator is operating doesn't affect the current SHA operation. | ||
| But the value of CRPT_SHA_DMACNT will be updated later on. | ||
| Consequently, software can prepare the byte count of data for the next SHA operation. | ||
| In Non-DMA mode, CRPT_SHA_DMACNT must be set as the byte count of the last block before feeding in the last block of data. |
Definition at line 6759 of file NUC472_442.h.
| __IO uint32_t CRPT_T::SHA_KEYCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | KEYCNT | SHA Key Byte Count |
| The CRPT_SHA_KEYCNT keeps the byte count of key that SHA engine operates. | ||
| The register is 32-bit and the maximum byte count is 4G bytes. | ||
| It can be read and written. | ||
| Writing to the register CRPT_SHA_KEYCNT as the SHA accelerator operating doesn't affect the current SHA operation. | ||
| But the value of SHA _KEY_CNT will be updated later on. | ||
| Consequently, software can prepare the key count for the next SHA operation. |
Definition at line 6719 of file NUC472_442.h.
| __IO uint32_t CRPT_T::SHA_SADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SADDR | SHA DMA Source Address |
| The SHA accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. | ||
| The CRPT_SHA_SADDR keeps the source address of the data buffer where the source text is stored. | ||
| Based on the source address, the SHA accelerator can read the plain text from system memory and do SHA operation. | ||
| The start of source address should be located at word boundary. | ||
| In other words, bit 1 and 0 of CRPT_SHA_SADDR are ignored. | ||
| CRPT_SHA_SADDR can be read and written. | ||
| Writing to CRPT_SHA_SADDR while the SHA accelerator is operating doesn't affect the current SHA operation. | ||
| But the value of CRPT_SHA_SADDR will be updated later on. | ||
| Consequently, software can prepare the DMA source address for the next SHA operation. | ||
| In DMA mode, software can update the next TDES_SADR before triggering START. | ||
| TDES_SADR and TDES_DADR can be the same in the value. |
Definition at line 6741 of file NUC472_442.h.
| __I uint32_t CRPT_T::SHA_STS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BUSY | SHA Engine Busy |
| 0 = SHA engine is idle or finished. | ||
| 1 = SHA engine is busy. | ||
| [1] | DMABUSY | SHA Engine DMA Busy Flag |
| 0 = SHA DMA engine is idle or finished. | ||
| 1 = SHA DMA engine is busy. | ||
| [8] | DMAERR | SHA Engine DMA Error Flag |
| 0 = Show the SHA engine access normal. | ||
| 1 = Show the SHA engine access error. | ||
| [16] | DATINREQ | SHA Non-DMA Mode Data Input Request |
| 0 = No effect. | ||
| 1 = Request SHA Non-DMA mode data input. |
Definition at line 6586 of file NUC472_442.h.
| __IO uint32_t EADC_T::SIMUSEL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SIMUSEL0 | A/D SAMPLE00, SAMPLE10 Simultaneous Sampling Mode Selection |
| 0 = SAMPLE00, SAMPLE10 are in single sampling mode, both SAMPLE00 and SAMPLE10's 3 bits of CHSEL define the ADC channels to be converted. | ||
| 1 = SAMPLE00, SAMPLE10 are in simultaneous sampling mode, Only SAMPLE00 can trigger the both ADC conversions of SAMPLE00 and SAMPLE10, SAMPLE10 trigger select TRGSEL is ignored. | ||
| If SAMPLE00's CHSEL = 1, and SAMPLE10's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal. | ||
| [1] | SIMUSEL1 | A/D SAMPLE01, SAMPLE11 Simultaneous Sampling Mode Selection |
| 0 = SAMPLE01, SAMPLE11 are in single sampling mode, both SAMPLE01 and SAMPLE11's 3 bits of CHSEL define the ADC channels to be converted. | ||
| 1 = SAMPLE01, SAMPLE11 are in simultaneous sampling mode, Only SAMPLE01 can trigger the both ADC conversions of SAMPLE01 and SAMPLE11, SAMPLE11 trigger select TRGSEL is ignored. | ||
| If SAMPLE01's CHSEL = 1, and SAMPLE11's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal. | ||
| [2] | SIMUSEL2 | A/D SAMPLE02, SAMPLE12 Simultaneous Sampling Mode Selection |
| 0 = SAMPLE02, SAMPLE12 are in single sampling mode, both SAMPLE02 and SAMPLE12's 3 bits of CHSEL define the ADC channels to be converted. | ||
| 1 = SAMPLE02, SAMPLE12 are in simultaneous sampling mode, Only SAMPLE02 can trigger the both ADC conversions of SAMPLE02 and SAMPLE12, SAMPLE12 trigger select TRGSEL is ignored. | ||
| If SAMPLE02's CHSEL = 1, and SAMPLE12's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal. | ||
| [3] | SIMUSEL3 | A/D SAMPLE03, SAMPLE13 Simultaneous Sampling Mode Selection |
| 0 = SAMPLE03, SAMPLE13 are in single sampling mode, both SAMPLE03 and SAMPLE13's 3 bits of CHSEL define the ADC channels to be converted. | ||
| 1 = SAMPLE03, SAMPLE13 are in simultaneous sampling mode, Only SAMPLE03 can trigger the both ADC conversions of SAMPLE03 and SAMPLE13, SAMPLE13 trigger select TRGSEL is ignored. | ||
| If SAMPLE03's CHSEL = 1, and SAMPLE13's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal. | ||
| [4] | SIMUSEL4 | A/D SAMPLE04, SAMPLE14 Simultaneous Sampling Mode Selection |
| 0 = SAMPLE04, SAMPLE14 are in single sampling mode, both SAMPLE04 and SAMPLE14's 3 bits of CHSEL define the ADC channels to be converted. | ||
| 1 = SAMPLE04, SAMPLE14 are in simultaneous sampling mode, Only SAMPLE04 can trigger the both ADC conversions of SAMPLE04 and SAMPLE14, SAMPLE14 trigger select TRGSEL is ignored. | ||
| If SAMPLE04's CHSEL = 1, and SAMPLE14's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal. | ||
| [5] | SIMUSEL5 | A/D SAMPLE05, SAMPLE15 Simultaneous Sampling Mode Selection |
| 0 = SAMPLE05, SAMPLE15 are in single sampling mode, both SAMPLE05 and SAMPLE15's 3 bits of CHSEL define the ADC channels to be converted. | ||
| 1 = SAMPLE05, SAMPLE15 are in simultaneous sampling mode, Only SAMPLE05 can trigger the both ADC conversions of SAMPLE05 and SAMPLE15, SAMPLE15 trigger select TRGSEL is ignored. | ||
| if SAMPLE05's CHSEL = 1, and SAMPLE15's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal. | ||
| [6] | SIMUSEL6 | A/D SAMPLE06, SAMPLE16 Simultaneous Sampling Mode Selection |
| 0 = SAMPLE06, SAMPLE16 are in single sampling mode, both SAMPLE06 and SAMPLE16's 3 bits of CHSEL define the ADC channels to be converted. | ||
| 1 = SAMPLE06, SAMPLE16 are in simultaneous sampling mode, Only SAMPLE06 can trigger the both ADC conversions of SAMPLE06 and SAMPLE16, SAMPLE16 trigger select TRGSEL is ignored. | ||
| If SAMPLE06's CHSEL = 1, and SAMPLE16's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal. | ||
| [7] | SIMUSEL7 | A/D SAMPLE07, SAMPLE17 Simultaneous Sampling Mode Selection |
| 0 = SAMPLE07, SAMPLE17 are in single sampling mode, both SAMPLE07 and SAMPLE17's 3 bits of CHSEL define the ADC channels to be converted. | ||
| 1 = SAMPLE07, SAMPLE17 are in simultaneous sampling mode, Only SAMPLE07 can trigger the both ADC conversions of SAMPLE07 and SAMPLE17, SAMPLE17 trigger select TRGSEL is ignored. | ||
| If SAMPLE07's CHSEL = 1, SAMPLE17's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal. |
Definition at line 8713 of file NUC472_442.h.
| __IO uint32_t GPIO_T::SLEWCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HSREN0 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [1] | HSREN1 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [2] | HSREN2 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [3] | HSREN3 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [4] | HSREN4 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [5] | HSREN5 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [6] | HSREN6 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [7] | HSREN7 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [8] | HSREN8 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [9] | HSREN9 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [10] | HSREN10 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [11] | HSREN11 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [12] | HSREN12 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [13] | HSREN13 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [14] | HSREN14 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. | ||
| [15] | HSREN15 | 0 = P I/O output with basic slew rate. |
| 1 = P I/O output with higher slew rate. |
Definition at line 16177 of file NUC472_442.h.
| __IO uint32_t GPIO_T::SMTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SMTEN0 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [1] | SMTEN1 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [2] | SMTEN2 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [3] | SMTEN3 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [4] | SMTEN4 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [5] | SMTEN5 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [6] | SMTEN6 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [7] | SMTEN7 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [8] | SMTEN8 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [9] | SMTEN9 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [10] | SMTEN10 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [11] | SMTEN11 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [12] | SMTEN12 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [13] | SMTEN13 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [14] | SMTEN14 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. | ||
| [15] | SMTEN15 | 0 = P I/O input Schmitt Trigger function Disabled. |
| 1 = P I/O input Schmitt Trigger function Enabled. |
Definition at line 16135 of file NUC472_442.h.
| __IO uint32_t RTC_T::SPR[24] |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | SPARE | SPARE Bits |
| This field is used to store back-up information defined by software. | ||
| This field will be cleared by hardware automatically once a snooper pin event is detected. | ||
| Before storing back-up information in to SPARE register, software should write 0xA965 to RTC_RWEN to make sure register read/write enabled. |
Definition at line 20653 of file NUC472_442.h.
| __IO uint32_t RTC_T::SPRCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [2] | SPRRWEN | SPR Register Enable Control |
| This bit controls the spare register to be enabled or not. | ||
| 0 = Spare register Disabled and RTC_SPR0 ~ RTC_SPR23 cannot be accessed. | ||
| 1 = Spare register Enabled and RTC_SPR0 ~ RTC_SPR23 can be accessed. | ||
| [7] | SPRRWRDY | SPR Register Ready |
| This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 are ready to be accessed. | ||
| After CPU writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23, polling this bit to check if these registers are updated done is necessary. | ||
| This bit is read only and any write to it won't take any effect. | ||
| 0 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 updating is in progress. | ||
| 1 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 are updated done and ready to be accessed. |
Definition at line 20639 of file NUC472_442.h.
| __I uint32_t SYS_T::SRAM0_ERRADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | PERRADDR | First SRAM parity check fail address |
Definition at line 24042 of file NUC472_442.h.
| __I uint32_t SYS_T::SRAM1_ERRADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [0:31] | PERRADDR | 2nd |
| SRAM parity check fail address |
Definition at line 24054 of file NUC472_442.h.
| __IO uint32_t SYS_T::SRAM_INTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PERRIEN | SRAM Parity Check Fail Interrupt Enable Control |
| 0 = SRAMF INT Disabled. | ||
| 1 = SRAMF INT Enabled when SRAM fail flag. |
Definition at line 24015 of file NUC472_442.h.
| __IO uint32_t SYS_T::SRAM_STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PERRIF0 | SRAM Parity Check Fail Flag |
| 0 = No first 1 SRAM fail. | ||
| 1 = First SRAM Fail. | ||
| [1] | PERRIF1 | SRAM Parity Check Fail Flag |
| 0 = 2nd SRAM fail. | ||
| 1 = 2nd SRAM Fail. |
Definition at line 24031 of file NUC472_442.h.
| __IO uint32_t SPI_T::SSCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0:1] | SS | Slave Select Control (Master Only) |
| If AUTOSS bit is cleared to 0, | ||
| 0 = Set the SPI_SS line to inactive state. | ||
| 1 = Set the proper SPI_SS line to active state. | ||
| If AUTOSS bit is set to 1, | ||
| 0 = Keep the SPI_SS line at inactive state. | ||
| 1 = Select the SPI_SS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. | ||
| The active state of SPI_SS is specified in SSACTPOL bit. | ||
| Note: SPI_SS0 is defined as the slave select input in Slave mode. | ||
| [2] | SSACTPOL | Slave Select Active Level |
| 0 = The slave select signal SPI_SS0/1 is active on low-level. | ||
| 1 = The slave select signal SPI_SS0/1 is active on high-level. | ||
| Note: This bit defines the active status of slave select signal (SPI_SS0/1). | ||
| [3] | AUTOSS | Automatic Slave Select Function Enable Control (Master Only) |
| 0 = Automatic slave select function Disabled. | ||
| 1 = Automatic slave select function Enabled. | ||
| Note1: If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSCTL[1:0]. | ||
| Note2: If this bit is set, SPI_SS0/1 signals will be generated automatically. | ||
| It means that device/slave select signal, which is set in SPI_SSCTL[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished. | ||
| [4] | SLV3WIRE | Slave 3-Wire Mode Enable Control |
| 0 = 4-wire bi-direction interface. | ||
| 1 = 3-wire bi-direction interface. | ||
| Note: This is used to ignore the slave select signal in Slave mode. | ||
| The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI. | ||
| [5] | SLVTOIEN | Slave Mode Time-Out Interrupt Enable Control |
| 0 = Slave mode time-out interrupt Disabled. | ||
| 1 = Slave mode time-out interrupt Enabled. | ||
| [6] | SLVTORST | Slave Mode Time-Out FIFO Clear |
| 0 = Time out FIFO clear Disabled. | ||
| 1 = Time out FIFO clear Enabled. | ||
| Note: Both the FIFO clear function, TX_CLK and RXRST, active automatically when there is slave mode time-out event. | ||
| [8] | SLVBEIEN | Slave Mode Error 0 Interrupt Enable Control |
| 0 = Slave mode error 0 interrupt Disabled. | ||
| 1 = Slave mode error 0 interrupt Enabled. | ||
| [9] | SLVURIEN | Slave Mode Error 1 Interrupt Enable Control |
| 0 = Slave mode error 1 interrupt Disabled. | ||
| 1 = Slave mode error 1 interrupt Enabled. | ||
| [12] | SSACTIEN | Slave Select Active Interrupt Enable Control |
| 0 = Slave select active interrupt Disabled. | ||
| 1 = Slave select active interrupt Enabled. | ||
| [13] | SSINAIEN | Slave Select Inactive Interrupt Enable Control |
| 0 = Slave select inactive interrupt Disabled. | ||
| 1 = Slave select inactive interrupt Enabled. | ||
| [16:31] | SLVTOCNT | Slave Mode Time-Out Period |
| 0 = Slave time out function disabled. | ||
| Others = Slave time out period. | ||
| Note: In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. | ||
| The clock source of the time-out counter is Slave peripheral clock. | ||
| If the value is 0, it indicates the slave mode time-out function is disabled. |
Definition at line 22848 of file NUC472_442.h.
| __IO uint32_t ACMP_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ACMPIF0 | Comparator 0 Flag |
| This bit is set by hardware whenever the comparator 0 output changes state. | ||
| This will cause an interrupt if ACMP_CTL0[1] is set to 1. | ||
| Write 1 to clear this bit to 0. | ||
| [1] | ACMPIF1 | Comparator 1 Flag |
| This bit is set by hardware whenever the comparator 1 output changes state. | ||
| This will cause an interrupt if ACMP_CTL1[1] is set to 1. | ||
| Write 1 to clear this bit to 0. | ||
| [2] | ACMPIF2 | Comparator 2 Flag |
| This bit is set by hardware whenever the comparator 2 output changes state. | ||
| This will cause an interrupt if ACMP_CTL2[1] is set to 1. | ||
| Write 1 to clear this bit to 0. | ||
| [3] | ACMPO0 | Comparator 0 Output |
| Synchronized to the APB clock to allow reading by software. | ||
| Cleared when the comparator 0 is disabled (ACMP_CTL0[0] = 0). | ||
| [4] | ACMPO1 | Comparator 1 Output |
| Synchronized to the APB clock to allow reading by software. | ||
| Cleared when the comparator 1 is disabled (ACMP_CTL1[0] = 0). | ||
| [5] | ACMPO2 | Comparator 2 Output |
| Synchronized to the APB clock to allow reading by software. | ||
| Cleared when the comparator 2 is disabled (ACMP_CTL2[0] = 0). |
Definition at line 288 of file NUC472_442.h.
| __IO uint32_t CAN_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:2] | LEC | Last Error Code (Type Of The Last Error To Occur On The CAN Bus) |
| The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. | ||
| This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. | ||
| The unused code '7' may be written by the CPU to check for updates. | ||
| The following table describes the error code. | ||
| [3] | TxOK | Transmitted A Message Successfully |
| 0 = Since this bit was reset by the CPU, no message has been successfully transmitted. | ||
| This bit is never reset by the CAN Core. | ||
| 1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted. | ||
| [4] | RxOK | Received A Message Successfully |
| 0 = No message has been successfully received since this bit was last reset by the CPU. | ||
| This bit is never reset by the CAN Core. | ||
| 1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering). | ||
| [5] | EPass | Error Passive (Read Only) |
| 0 = The CAN Core is error active. | ||
| 1 = The CAN Core is in the error passive state as defined in the CAN Specification. | ||
| [6] | EWarn | Error Warning Status (Read Only) |
| 0 = Both error counters are below the error warning limit of 96. | ||
| 1 = At least one of the error counters in the EML has reached the error warning limit of 96. | ||
| [7] | BOff | Bus-Off Status (Read Only) |
| 0 = The CAN module is not in bus-off state. | ||
| 1 = The CAN module is in bus-off state. |
Definition at line 1188 of file NUC472_442.h.
| __IO uint32_t ECAP_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CAPF0 | Input Capture Channel 0 Captured Flag |
| When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPF0 to high. | ||
| 0 = No valid edge change is detected at CAP0 input. | ||
| 1 = A valid edge change is detected at CAP0 input. | ||
| Note: This bit is only cleared by writing 1 to it. | ||
| [1] | CAPF1 | Input Capture Channel 1 Captured Flag |
| When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPF1 to high. | ||
| 0 = No valid edge change is detected at CAP1 input. | ||
| 1 = A valid edge change is detected at CAP1 input. | ||
| Note: This bit is only cleared by writing 1 to it. | ||
| [2] | CAPF2 | Input Capture Channel 2 Captured Flag |
| When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPF2 to high. | ||
| 0 = No valid edge change is detected at CAP2 input. | ||
| 1 = A valid edge change is detected at CAP2 input. | ||
| Note: This bit is only cleared by writing 1 to it. | ||
| [4] | CMPF | Input Capture Compare-Match Flag |
| If the input capture compare function is enabled, the flag is set by hardware while capture counter (ECAP_CNT) up counts and reach to the ECAP_CNTCMP value. | ||
| 0 = ECAP_CNT does not match with ECAP_CNTCMP value. | ||
| 1 = ECAP_CNT counts to the same as ECAP_CNTCMP value. | ||
| Note: This bit is only cleared by writing 1 to it. | ||
| [5] | OVF | Input Capture Counter Overflow Flag |
| Flag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero. | ||
| 0 = No overflow occurs in ECAP_CNT. | ||
| 1 = ECAP_CNT overflows. | ||
| Note: This bit is only cleared by writing 1 to it. |
Definition at line 2657 of file NUC472_442.h.
| __IO uint32_t CLK_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXTSTB | 4~24 MHz External High-Speed Crystal Clock(HXT) Source Stable Flag |
| 0 = HXT clock is not stable or disabled. | ||
| 1 = HXT clock is stable. | ||
| Note: This bit is read only. | ||
| [1] | LXTSTB | 32.768 KHz External Low-Speed Crystal Clock(LXT) Source Stable Flag |
| 0 = LXT clock is not stable or disabled. | ||
| 1 = LXT clock is stabled. | ||
| Note: This is read only. | ||
| [2] | PLLSTB | Internal PLL Clock Source Stable Flag |
| 0 = Internal PLL clock is not stable or disabled. | ||
| 1 = Internal PLL clock is stable. | ||
| Note: This bit is read only. | ||
| [3] | LIRCSTB | 10 KHz Internal Low-Speed Oscillator Clock (LIRC)Source Stable Flag |
| 0 = LIRC clock is not stable or disabled. | ||
| 1 = LIRC clock is stable. | ||
| Note: This bit is read only. | ||
| [4] | HIRCSTB | 22.1184 MHz Internal High-Speed Oscillator Clock (HIRC) Clock Source Stable Flag |
| 0 = HIRC clock is not stable or disabled. | ||
| 1 = HIRC clock is stable. | ||
| Note: This bit is read only. | ||
| [5] | PLL2STB | Internal PLL2 Clock Source Stable Flag |
| 0 = Internal PLL2 clock is not stable or disabled. | ||
| 1 = Internal PLL2 clock is stable. | ||
| Note: This bit is read only. | ||
| [7] | CLKSFAIL | Clock Switching Fail Flag |
| 0 = Clock switching success. | ||
| 1 = Clock switching failure. | ||
| Note1: This bit is updated when software switches system clock source. | ||
| If switch target clock is stable, this bit will be set to 0. | ||
| If switch target clock is not stable, this bit will be set to 1. | ||
| Note2: Write 1 to clear the bit to 0. |
Definition at line 3480 of file NUC472_442.h.
| __IO uint32_t EPWM_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BRKIF0 | PWM Brake0 Flag |
| 0 = PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one. | ||
| 1 = When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high. | ||
| Note: This bit must be cleared by writing 1 to it. | ||
| [1] | BRKIF1 | PWM Brake1 Flag |
| 0 = PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one. | ||
| 1 = When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high. | ||
| Note: This bit must be cleared by writing 1 to it. | ||
| [2] | PIF | PWM Period Flag |
| 0 = PWM Counter has not up counted to the value of PERIOD or down counted with underflow. | ||
| 1 = Hardware will set this flag to high at the time of PWM Counter matches PERIOD in edge and Centre aligned modes or at the time of PWM Counter down counts with underflow in Centre aligned mode. | ||
| Note: This bit must be cleared by writing 1 to it. | ||
| [4] | EIF0 | PWMx0 Edge Flag |
| 0 = The PWMx0 doesn't toggle. | ||
| 1 = Hardware will set this flag to high at the time of PWMx0 rising or falling. | ||
| If EINTTYPE0 = 0, this bit is set when PWMx0 falling is detected. | ||
| If EINTTYPE0 = 1, this bit is set when PWMx0 rising is detected. | ||
| Note: This bit must be cleared by writing 1 to it. | ||
| [5] | EIF2 | PWMx2 Edge Flag |
| 0 = The PWMx2 doesn't toggle. | ||
| 1 = Hardware will set this flag to high at the time of PWMx2 rising or falling. | ||
| If EINTTYPE2 = 0, this bit is set when PWMx2 falling is detected. | ||
| If EINTTYPE2 = 1, this bit is set when PWMx2 rising is detected. | ||
| Note: This bit must be cleared by writing 1 to it. | ||
| [6] | EIF4 | PWMx4 Edge Flag |
| 0 = The PWMx4 doesn't toggle. | ||
| 1 = Hardware will set this flag to high at the time of PWMx4 rising or falling. | ||
| If EINTTYPE4 = 0, this bit is set when PWMx4 falling is detected. | ||
| If EINTTYPE4 = 1, this bit is set when PWMx4 rising is detected. | ||
| Note: This bit must be cleared by writing 1 to it. | ||
| [8] | BRK0LOCK | PWM Brake0 Locked |
| 0 = Brake 0 state is released. | ||
| 1 = When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked. | ||
| Note: This bit must be cleared by writing 1 to it. | ||
| [24] | BRK0STS | Brake 0 Status (Read Only) |
| 0 = PWM had been out of Brake 0 state. | ||
| 1 = PWM is in Brake 0 state. | ||
| [25] | BRK1STS | Brake 1 Status (Read Only) |
| 0 = PWM had been out of Brake 1 state. | ||
| 1 = PWM is in Brake 1 state. |
Definition at line 14086 of file NUC472_442.h.
| __I uint32_t I2C_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0:7] | STATUS | I2C Status Bits |
| The status register of I2C: | ||
| The three least significant bits are always 0. | ||
| The five most significant bits contain the status code. | ||
| Refer to section <IP_ADDRESS> for detail description. |
Definition at line 16897 of file NUC472_442.h.
| __IO uint32_t I2S_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | I2SIF | I2S Interrupt Flag (Read Only) |
| 0 = No I2S interrupt. | ||
| 1 = I2S interrupt. | ||
| Note: It is wire-OR of TXIF and RXIF bits. | ||
| [1] | RXIF | I2S Receive Interrupt (Read Only) |
| 0 = No receive interrupt. | ||
| 1 = Receive interrupt. | ||
| [2] | TXIF | I2S Transmit Interrupt (Read Only) |
| 0 = No transmit interrupt. | ||
| 1 = Transmit interrupt. | ||
| [3] | RIGHT | Right Channel (Read Only) |
| 0 = Left channel. | ||
| 1 = Right channel. | ||
| Note: This bit indicate current transmit data is belong to right channel | ||
| [8] | RXUDIF | Receive FIFO Underflow Flag |
| 0 = No underflow occur. | ||
| 1 = Underflow occur. | ||
| Note1: When receive FIFO is empty, and software reads the receive FIFO again. | ||
| This bit will be set to 1, and it indicates underflow situation occurs. | ||
| Note2: Write 1 to clear this bit to zero | ||
| [9] | RXOVIF | Receive FIFO Overflow Flag |
| 0 = No overflow occur. | ||
| 1 = Overflow occur. | ||
| Note1: When receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. | ||
| Note2: Write 1 to clear this bit to 0. | ||
| [10] | RXTHIF | Receive FIFO Threshold Flag (Read Only) |
| 0 = Data word(s) in FIFO is lower than threshold level. | ||
| 1 = Data word(s) in FIFO is equal or higher than threshold level. | ||
| Note: When data word(s) in receive FIFO is equal or higher than threshold value set in RXTH(I2S_CTL[14:12]) the RXTHIF bit becomes to 1. | ||
| It keeps at 1 till RXCNT less than RXTH after software read RXFIFO register. | ||
| [11] | RXFULL | Receive FIFO Full (Read Only) |
| 0 = Not full. | ||
| 1 = Full. | ||
| Note: This bit reflects data words number in receive FIFO is 8. | ||
| [12] | RXEMPTY | Receive FIFO Empty (Read Only) |
| 0 = Not empty. | ||
| 1 = Empty. | ||
| Note: This bit reflects data words number in receive FIFO is zero | ||
| [16] | TXUDIF | Transmit FIFO Underflow Flag |
| 0 = No underflow. | ||
| 1 = Underflow. | ||
| Note1: When transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1. | ||
| Note2: Write 1 to clear this bit to 0. | ||
| [17] | TXOVIF | Transmit FIFO Overflow Flag |
| 0 = No overflow. | ||
| 1 = Overflow. | ||
| Note1: Write data to transmit FIFO when it is full and this bit set to 1 | ||
| Note2: Write 1 to clear this bit to 0. | ||
| [18] | TXTHIF | Transmit FIFO Threshold Flag (Read Only) |
| 0 = Data word(s) in FIFO is higher than threshold level. | ||
| 1 = Data word(s) in FIFO is equal or lower than threshold level. | ||
| Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH(I2S_CTL[11:9]) the TXTHIF bit becomes to 1. | ||
| It keeps at 1 till TXCNT is higher than TXTH after software write TXFIFO register. | ||
| [19] | TXFULL | Transmit FIFO Full (Read Only) |
| This bit reflect data word number in transmit FIFO is 8 | ||
| 0 = Not full. | ||
| 1 = Full. | ||
| [20] | TXEMPTY | Transmit FIFO Empty (Read Only) |
| This bit reflect data word number in transmit FIFO is zero | ||
| 0 = Not empty. | ||
| 1 = Empty. | ||
| [21] | TXBUSY | Transmit Busy (Read Only) |
| 0 = Transmit shift buffer is empty. | ||
| 1 = Transmit shift buffer is busy. | ||
| Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. | ||
| And set to 1 when 1st data is load to shift buffer. | ||
| [22] | RZCIF | Right Channel Zero-Cross Flag |
| It indicates right channel next sample data sign bit is changed or all data bits are zero. | ||
| 0 = No zero-cross. | ||
| 1 = Right channel zero-cross is detected. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [23] | LZCIF | Left Channel Zero-Cross Flag |
| It indicates left channel next sample data sign bit is changed or all data bits are zero. | ||
| 0 = No zero-cross. | ||
| 1 = Left channel zero-cross is detected. | ||
| Note: Write 1 to clear this bit to 0. | ||
| [24:27] | RXCNT | Receive FIFO Level (Read Only) |
| These bits indicate word number in receive FIFO | ||
| 0000 = No data. | ||
| 0001 = 1 word in receive FIFO. | ||
| .... | ||
| 1000 = 8 words in receive FIFO. | ||
| [28:31] | TXCNT | Transmit FIFO Level (Read Only) |
| These bits indicate word number in transmit FIFO | ||
| 0000 = No data. | ||
| 0001 = 1 word in transmit FIFO. | ||
| .... | ||
| 1000 = 8 words in transmit FIFO. |
Definition at line 17443 of file NUC472_442.h.
| __IO uint32_t OPA_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | OPDO0 | OP Amplifier 0 Digital Output |
| Synchronized to the APB clock to allow reading by software. | ||
| Cleared when the Schmitt trigger buffer is disabled (OPSMTEN0 = 0). | ||
| [1] | OPDO1 | OP Amplifier 1 Digital Output |
| Synchronized to the APB clock to allow reading by software. | ||
| Cleared when the Schmitt trigger buffer is disabled (OPSMTEN1 = 0). | ||
| [4] | OPDF0 | OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag |
| OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state. | ||
| This bit is cleared by writing 1 to it. | ||
| [5] | OPDF1 | OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag |
| OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state. | ||
| This bit is cleared by writing 1 to it. |
Definition at line 17697 of file NUC472_442.h.
| __I uint32_t OTG_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | OVERCUR | Over current Condition |
| The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A device starting to drive | ||
| 0 = OTG A-device drives VBUS successfully. | ||
| 1 = Over current condition occurred. | ||
| [1] | IDSTS | ID Pin State Of Mini-B/Micro-Plug |
| 0 = Mini-A/Micro-A plug is attached. | ||
| 1 = Mini-B/Micro-B plug is attached. | ||
| [2] | SESSEND | Session End Status |
| 0 = VBUS > 0.8V. | ||
| 1 = VBUS < 0.2V. | ||
| [3] | BVLID | B-Device Session Valid Status |
| 0 = VBUS < 0.8V. | ||
| 1 = VBUS > 4V. | ||
| [4] | AVLD | A-Device Session Valid Status |
| 0 = VBUS < 0.8V. | ||
| 1 = VBUS > 2V. | ||
| [5] | VBUSVLD | VBUS Valid Status |
| 0 = VBUS < 4.4V. | ||
| 1 = VBUS > 4.75V. |
Definition at line 17964 of file NUC472_442.h.
| __IO uint32_t PS2_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CLKSTAT | CLK Pin State |
| This bit reflects the status of the CLKSTAT line after synchronizing. | ||
| [1] | DATSTAT | DATA Pin State |
| This bit reflects the status of the DATSTAT line after synchronizing and sampling. | ||
| [2] | FRAMEERR | Frame Error |
| For host to device communication, if STOP bit (logic 1) is not received it is a frame error. | ||
| If frame error occurs, DATA line may keep at low state after 12th clock. | ||
| At this moment, software overrides CLKSTAT to send clock till DATSTAT release to high state. | ||
| After that, device sends a "Resend" command to host. | ||
| 0 = No frame error. | ||
| 1 = Frame error occurred . | ||
| Note: Write 1 to clear this bit. | ||
| [3] | RXPARITY | Received Parity |
| This bit reflects the parity bit for the last received data byte (odd parity). | ||
| Note: This bit is read only. | ||
| [4] | RXBUSY | Receive Busy |
| This bit indicates that the PS/2 device is currently receiving data. | ||
| 0 = Idle. | ||
| 1 = Currently receiving data. | ||
| Note: This bit is read only. | ||
| [5] | TXBUSY | Transmit Busy |
| This bit indicates that the PS/2 device is currently sending data. | ||
| 0 = Idle. | ||
| 1 = Currently sending data. | ||
| Note: This bit is read only. | ||
| [6] | RXOV | RX Buffer Overwrite |
| 0 = No overwrite. | ||
| 1 = Data in PS2_RXDAT register is overwritten by new received data. | ||
| Note: Write 1 to clear this bit. | ||
| [7] | TXEMPTY | TX FIFO Empty |
| When software writes any data to PS2_TXDAT0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. | ||
| When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1. | ||
| 0 = There is data to be transmitted. | ||
| 1 = FIFO is empty. | ||
| Note: This bit is read only. | ||
| [8:11] | BYTEIDX | Byte Index |
| It indicates which data byte in transmit data shift register. | ||
| When all data in FIFO is transmitted and it will be cleared to 0. | ||
| Note: This bit is read only. | ||
| BYTEIDX DATA Transmit | ||
| 0000 TXDATA0[7:0] | ||
| 0001 TXDATA0[15:8] | ||
| 0010 TXDATA0[23:16] | ||
| 0011 TXDATA0[31:24] | ||
| 0100 TXDATA1[7:0] | ||
| 0101 TXDATA1[15:8] | ||
| 0110 TXDATA1[23:16] | ||
| 0111 TXDATA1[31:24] | ||
| 1000 TXDATA2[7:0] | ||
| 1001 TXDATA2[15:8] | ||
| 1010 TXDATA2[23:16] | ||
| 1011 TXDATA2[31:24] | ||
| 1100 TXDATA3[7:0] | ||
| 1101 TXDATA3[15:8] | ||
| 1110 TXDATA3[23:16] | ||
| 1111 TXDATA3[31:24] |
Definition at line 18926 of file NUC472_442.h.
| __IO uint32_t QEI_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | IDXF | IDX Detected Flag |
| When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high. | ||
| 0 = No rising edge detected on signal CHX. | ||
| 1 = A rising edge occurs on signal CHX. | ||
| Note: This bit is only cleared by writing 1 to it. | ||
| [1] | CMPF | Compare-Match Flag |
| If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the QEI_CNTCMP value. | ||
| 0 = QEI counter does not match with QEI_CNTCMP value. | ||
| 1 = QEI counter counts to the same as QEI_CNTCMP value. | ||
| Note: This bit is only cleared by writing 1 to it. | ||
| [2] | OVUNF | QEI Counter Overflow Or Underflow Flag |
| Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the QEI_MAXCNT value to zero in compare-counting mode. | ||
| Similarly, the flag is set wile QEI counter underflows from zero to 0xFFFF_FFFF or QEI_MAXCNT. | ||
| 0 = No overflow or underflow occurs in QEI counter. | ||
| 1 = QEI counter occurs counting overflow or underflow. | ||
| Note: This bit is only cleared by writing 1 to it. | ||
| [3] | DIRCHGF | Direction Change Flag |
| Flag is set by hardware while QEI counter counting direction is changed. | ||
| Software can clear this bit by writing 1 to it. | ||
| 0 = No change in QEI counter counting direction. | ||
| 1 = QEI counter counting direction is changed. | ||
| Note: This bit is only cleared by writing 1 to it. | ||
| [8] | DIRF | QEI Counter Counting Direction Indication |
| 0 = QEI Counter is in down-counting. | ||
| 1 = QEI Counter is in up-counting. | ||
| Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB. |
Definition at line 20287 of file NUC472_442.h.
| __IO uint32_t SC_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXOV | RX Overflow Error Status Flag (Read Only) |
| This bit is set when RX buffer overflow. | ||
| If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [1] | RXEMPTY | Receiver Buffer Empty Status Flag(Read Only) |
| This bit indicates RX buffer empty or not. | ||
| When the last byte of Rx buffer has been read by CPU, hardware sets this bit high. | ||
| It will be cleared when SC receives any new data. | ||
| [2] | RXFULL | Receiver Buffer Full Status Flag (Read Only) |
| This bit indicates RX buffer full or not. | ||
| This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware. | ||
| [4] | PEF | Receiver Parity Error Status Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid | ||
| "parity bit". | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. | ||
| [5] | FEF | Receiver Frame Error Status Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0). | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. | ||
| [6] | BEF | Receiver Break Error Status Flag (Read Only) |
| This bit is set to a logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits). | ||
| . | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag. | ||
| [8] | TXOV | TX Overflow Error Interrupt Status Flag (Read Only) |
| If TX buffer is full, an additional write to SC_DAT will cause this bit be set to "1" by hardware. | ||
| Note: This bit is read only, but it can be cleared by writing 1 to it. | ||
| [9] | TXEMPTY | Transmit Buffer Empty Status Flag (Read Only) |
| This bit indicates TX buffer empty or not. | ||
| When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. | ||
| It will be cleared when writing data into SC_DAT (TX buffer not empty). | ||
| [10] | TXFULL | Transmit Buffer Full Status Flag (Read Only) |
| This bit indicates TX buffer full or not. | ||
| This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware. | ||
| [11] | CREMOVE | Card Detect Removal Status Of SC_CD Pin (Read Only) |
| This bit is set whenever card has been removal. | ||
| 0 = No effect. | ||
| 1 = Card removed. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: Card detect engine will start after SCEN (SC_CTL[0])set. | ||
| [12] | CINSERT | Card Detect Insert Status Of SC_CD Pin (Read Only) |
| This bit is set whenever card has been inserted. | ||
| 0 = No effect.1 = Card insert. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: The card detect engine will start after SCEN (SC_CTL[0]) set. | ||
| [13] | CDPINSTS | Card Detect Status Of SC_CD Pin Status (Read Only) |
| This bit is the pin status flag of SC_CD | ||
| 0 = The SC_CD pin state at low. | ||
| 1 = The SC_CD pin state at high. | ||
| [16:17] | RXPOINT | Receiver Buffer Pointer Status Flag (Read Only) |
| This field indicates the RX buffer pointer status flag. | ||
| When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. | ||
| When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one. | ||
| [21] | RXRERR | Receiver Retry Error (Read Only) |
| This bit is set by hardware when RX has any error and retries transfer. | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2 This bit is a flag and cannot generate any interrupt to CPU. | ||
| Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). | ||
| [22] | RXOVERR | Receiver Over Retry Error (Read Only) |
| This bit is set by hardware when RX transfer error retry over retry number limit. | ||
| Note1: This bit is read only, but it can be cleared by writing 1 to it. | ||
| Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). | ||
| [23] | RXACT | Receiver In Active Status Flag (Read Only) |
| This bit is set by hardware when RX transfer is in active. | ||
| This bit is cleared automatically when RX transfer is finished. | ||
| [24:25] | TXPOINT | Transmit Buffer Pointer Status Flag (Read Only) |