Welcome to riscv-dv’s documentation!¶
Overview¶
RISCV-DV is a SV/UVM based open-source instruction generator for RISC-V processor verification. It currently supports the following features:
Supported instruction set: RV32IMAFDC, RV64IMAFDC
Supported privileged mode: machine mode, supervisor mode, user mode
Page table randomization and exception
Privileged CSR setup randomization
Privileged CSR test suite
Trap/interrupt handling
Test suite to stress test MMU
Sub-program generation and random program calls
Illegal instruction and HINT instruction generation
Random forward/backward branch instructions
Supports mixing directed instructions with random instruction stream
Debug mode support, with fully randomized debug ROM
Instruction generation coverage model
Communication of information to any integrated SV testbench
Co-simulation with multiple ISS : spike, riscv-ovpsim
A CSR test generation script written in Python is also provided, to generate a directed test suite that stresses all CSR instructions on all of the CSRs that the core implements.
Getting Started¶
Prerequisites¶
To be able to run the instruction generator, you need to have an RTL simulator which supports SystemVerilog and UVM 1.2. This generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators. Please make sure the EDA tool environment is properly setup before running the generator.
Install RISCV-DV¶
Getting the source
Install git
git clone https://github.com/google/riscv-dv.git
cd riscv-dv
There are two ways that you can run scripts from riscv-dv.
For developers which may work on multiple clones in parallel, using directly run by python3 script is highly recommended. Example:
pip3 install -r requirements.txt # install dependencies (only once)
python3 run.py --help
For normal users, using the python package is recommended. First, cd to the directory where riscv-dv is cloned and run:
export PATH=$HOME/.local/bin/:$PATH # add ~/.local/bin to the $PATH (only once)
pip3 install --user -e .
This installs riscv-dv in a mode where any changes within the repo are immediately available simply by running run/cov. There is no need to repeatedly run pip install . after each change. Example for running:
run --help
cov --help
Setup RISCV-GCC compiler toolchain¶
Install riscv-gcc toolchain
Set environment variable RISCV_GCC to the RISC-V gcc executable executable. (example: <install_dir>/bin/riscv32-unknown-elf-gcc)
Set environment variable RISCV_OBJCOPY to RISC-v objcopy executable executable. (example: <install_dir>/bin/riscv32-unknown-elf-objcopy)
Sample .bashrc setup:
export RISCV_TOOLCHAIN=<riscv_gcc_install_path>
export RISCV_GCC="$RISCV_TOOLCHAIN/bin/riscv32-unknown-elf-gcc"
export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv32-unknown-elf-objcopy"
Setup ISS (instruction set simulator)¶
Currently three ISS are supported, the default ISS is spike. You can install any one of below to run ISS simulation.
spike setup
Follow the instructions to build spike
Build spike with “–enable-commitlog”
Set environment variable SPIKE_PATH to the directory of the spike binary
riscv-ovpsim setup
Download the riscv-ovpsim binary
Set environment variable OVPSIM_PATH to the directory of the ovpsim binary
whisper (swerv-ISS) setup
Follow the instruction to install the ISS, and set WHISPER_ISS to the whisper binary
sail-riscv setup
Follow the sail-riscv steps to install sail-riscv
Set environment variable SAIL_RISCV to the path of sail-riscv binary
Sample .bashrc setup:
export SPIKE_PATH=$RISCV_TOOLCHAIN/bin
export SAIL_RISCV="xx/xxx/ocaml_emulator"
export OVPSIM_PATH=/xx/xxx/riscv-ovpsim/bin/Linux64
export WHISPER_ISS="xx/xxx/swerv-ISS/build-Linux/whisper"
Running the generator¶
A simple script run.py is provided for you to run a single test or a regression.
 To run a full regression, simply use below command:
run
You can also run multiple generator jobs in parallel through LSF:
run --lsf_cmd="bsub -Is"
Here’s a few more examples of the run command:
# Run a single test 10 times
run --test riscv_arithmetic_basic_test --iterations 10
# Run multiple tests
run --test riscv_arithmetic_basic_test,riscv_rand_instr_test
# Run a test with verbose logging
run --test riscv_arithmetic_basic_test --verbose
# Run a test with a specified seed
run --test riscv_arithmetic_basic_test --seed 123
# Skip the generation, run ISS simulation with previously generated program
run --test riscv_arithmetic_basic_test --steps iss_sim
# Run the generator only, do not compile and simluation with ISS
run --test riscv_arithmetic_basic_test --steps gen
# Compile the generator only, do not simulate
run --test riscv_arithmetic_basic_test --co
....
Run ISS simulation¶
You can use -iss to run with different ISS:
# Run ISS with spike
run --test riscv_arithmetic_basic_test --iss spike
# Run ISS with riscv-ovpsim
run --test riscv_rand_instr_test --iss ovpsim
# Run ISS with whisper (swerv-ISS)
run --test riscv_rand_instr_test --iss whisper
# Run ISS with sail-riscv
run --test riscv_rand_instr_test --iss sail
To run with ISS simulation for RV32IMC, you can specify ISA and ABI from command line like this:
# Run a full regression with RV32IMC
run --isa rv32imc --mabi ilp32
We have added a flow to run ISS simulation with both spike and riscv-ovpsim, the instruction trace from these runs will be cross compared. This could greatly speed up your development of new test without the need to simulate against a real RISC-V processor:
run --test=riscv_rand_instr_test --iss=spike,ovpsim
run --test=riscv_rand_instr_test --iss=ovpsim,whisper
run --test=riscv_rand_instr_test --iss=spike,sail
Run directed assembly/C tests¶
Sometimes it might be useful to run some hand-coded assembly/C tests to hit some corner cases:
# Run a single/multiple assembly/C test
run --asm_test asm_test_path1/asm_test1.S,asm_test_path2/asm_test2.S
run --c_test c_test_path1/c_test1.c,c_test_path2/c_test2.c
# Run regression with all assembly test(*.S)/ C test(*.c) under a given directory
run --asm_test asm_test_path1,asm_test_path2
run --c_test c_test_path1,c_test_path2
# Run mix between the assembly/C test and assembly/C test under a directory
run --asm_test asm_test_path1/asm_test1.S,asm_test_path2
run --c_test c_test_path1/c_test1.c,c_test_path2
You could also use this approach to integrate the assembly/C tests from other sources to riscv-dv flow.
Configuration¶
Configure the generator to match your processor features¶
The default configuration of the instruction generator is RV32IMC (machine mode only). A few pre-defined configurations can be found under “target” directory, you can run with these targets if it matches your processor specificationi:
run # Default target rv32imc
run --target rv32i # rv32i, machine mode only
run --target rv32imc # rv32imc, machine mode only
run --target rv64imc # rv64imc, machine mode only
run --target rv64gc # rv64gc, SV39, M/S/U mode
If you want to have a custom setting for your processor, you can make a copy of existing target directory as the template, and modify riscv_core_setting.sv to match your processor capability.
// Bit width of RISC-V GPR
parameter int XLEN = 64;
// Parameter for SATP mode, set to BARE if address translation is not supported
parameter satp_mode_t SATP_MODE = SV39;
// Supported Privileged mode
privileged_mode_t supported_privileged_mode[] = {USER_MODE,
SUPERVISOR_MODE,
MACHINE_MODE};
// Unsupported instructions
riscv_instr_name_t unsupported_instr[] = {};
// ISA supported by the processor
riscv_instr_group_t supported_isa[] = {RV32I, RV32M, RV64I, RV64M};
You can then run the generator with --custom_target <target_dir>
:
# You need to manually specify isa and mabi for your custom target
run --custom_target <target_dir> --isa <isa> --mabi <mabi>
...
Setup the memory map¶
Here’s a few cases that you might want to allocate the instruction and data sections to match the actual memory map
The processor has internal memories, and you want to test load/store from various internal/externel memory regions
The processor implments the PMP feature, and you want to configure the memory map to match PMP setting.
Virtual address translation is implmented and you want to test load/store from sparse memory locations to verify data TLB replacement logic.
You can configure the memory map in riscv_instr_gen_config.sv:
mem_region_t mem_region[$] = '{
'{name:"region_0", size_in_bytes: 4096, xwr: 3'b111},
'{name:"region_1", size_in_bytes: 4096 * 4, xwr: 3'b111},
'{name:"region_2", size_in_bytes: 4096 * 2, xwr: 3'b111},
'{name:"region_3", size_in_bytes: 512, xwr: 3'b111},
'{name:"region_4", size_in_bytes: 4096, xwr: 3'b111}
};
Each memory region belongs to a separate section in the generated assembly program. You can modify the link script to link each section to the target memory location. Please avoid setting a large memory range as it could takes a long time to randomly initializing the memory. You can break down a large memory region to a few representative small regions which covers all the boundary conditions for the load/store testing.
Setup regression test list¶
Test list in YAML format
# test : Assembly test name
# description : Description of this test
# gen_opts : Instruction generator options
# iterations : Number of iterations of this test
# no_iss : Enable/disable ISS simulation (Optional)
# gen_test : Test name used by the instruction generator
# rtl_test : RTL simulation test name
# cmp_opts : Compile options passed to the instruction generator
# sim_opts : Simulation options passed to the instruction generator
# no_post_compare : Enable/disable log comparison (Optional)
# compare_opts : Options for the RTL & ISS trace comparison
- test: riscv_arithmetic_basic_test
description: >
Arithmetic instruction test, no load/store/branch instructions
gen_opts: >
+instr_cnt=10000
+num_of_sub_program=0
+no_fence=1
+no_data_page=1'b1
+no_branch_jump=1'b1
+boot_mode=m
iterations: 2
gen_test: riscv_instr_base_test
rtl_test: core_base_test
You can also add directed assembly/C test in the testlist
- test: riscv_single_c_test
description: >
single c test entry
iterations: 1
c_test: sample_c.c
- test: riscv_c_regression_test
description: >
Run all c tests under the given directory
iterations: 1
c_test: c_test_directory
gcc_opts:
# Some custom gcc options
- test: riscv_single_asm_test
description: >
single assembly test entry
iterations: 1
asm_test: sample_asm.S
- test: riscv_asm_regression_test
description: >
Run all assembly tests under the given directory
iterations: 1
asm_test: assembly_test_directory
gcc_opts:
# Some custom gcc options
Runtime options of the generator¶
Option |
Description |
Default |
|---|---|---|
num_of_tests |
Number of assembly tests to be generated |
1 |
num_of_sub_program |
Number of sub-program in one test |
5 |
instr_cnt |
Instruction count per test |
200 |
enable_page_table_exception |
Enable page table exception |
0 |
enable_unaligned_load_store |
Enable unaligned memory operations |
0 |
no_ebreak |
Disable ebreak instruction |
1 |
no_wfi |
Disable WFI instruction |
1 |
set_mstatus_tw |
Enable WFI to be treated as illegal instruction |
0 |
no_dret |
Disable dret instruction |
1 |
no_branch_jump |
Disable branch/jump instruction |
0 |
no_csr_instr |
Disable CSR instruction |
0 |
enable_illegal_csr_instruction |
Enable illegal CSR instructions |
0 |
enable_access_invalid_csr_level |
Enable accesses to higher privileged CSRs |
0 |
enable_dummy_csr_write |
Enable some dummy CSR writes in setup routine |
0 |
enable_misaligned_instr |
Enable jumps to misaligned instruction addresses |
0 |
no_fence |
Disable fence instruction |
0 |
no_data_page |
Disable data page generation |
0 |
disable_compressed_instr |
Disable compressed instruction generation |
0 |
illegal_instr_ratio |
Number of illegal instructions every 1000 instr |
0 |
hint_instr_ratio |
Number of HINT instructions every 1000 instr |
0 |
boot_mode |
m:Machine mode, s:Supervisor mode, u:User mode |
m |
no_directed_instr |
Disable directed instruction stream |
0 |
require_signature_addr |
Set to 1 if test needs to talk to testbench |
0 |
signature_addr |
Write to this addr to send data to testbench |
0 |
enable_interrupt |
Enable MStatus.MIE, used in interrupt test |
0 |
enable_timer_irq |
Enable xIE.xTIE, used to enable timer interrupts |
0 |
gen_debug_section |
Enables randomized debug_rom section |
0 |
num_debug_sub_program |
Number of debug sub-programs in test |
0 |
enable_ebreak_in_debug_rom |
Generate ebreak instructions inside debug ROM |
0 |
set_dcsr_ebreak |
Randomly enable dcsr.ebreak(m/s/u) |
0 |
enable_debug_single_step |
Enable debug single stepping functionality |
0 |
randomize_csr |
Fully randomize main CSRs (xSTATUS, xIE) |
0 |
Setup Privileged CSR description (optional)¶
This YAML description file of all CSRs is only required for the privileged CSR test. All other standard tests do not use this description.
CSR descriptions in YAML format
- csr: CSR_NAME
description: >
BRIEF_DESCRIPTION
address: 0x###
privilege_mode: MODE (D/M/S/H/U)
rv32:
- MSB_FIELD_NAME:
- description: >
BRIEF_DESCRIPTION
- type: TYPE (WPRI/WLRL/WARL/R)
- reset_val: RESET_VAL
- msb: MSB_POS
- lsb: LSB_POS
- ...
- ...
- LSB_FIELD_NAME:
- description: ...
- type: ...
- ...
rv64:
- MSB_FIELD_NAME:
- description: >
BRIEF_DESCRIPTION
- type: TYPE (WPRI/WLRL/WARL/R)
- reset_val: RESET_VAL
- msb: MSB_POS
- lsb: LSB_POS
- ...
- ...
- LSB_FIELD_NAME:
- description: ...
- type: ...
- ...
To specify what ISA width should be generated in the test, simply include the matching rv32/rv64/rv128 entry and fill in the appropriate CSR field entries.
Privileged CSR Test Generation (optional)¶
The CSR generation script is located at scripts/gen_csr_test.py. The CSR test code that this script generates will execute every CSR instruction on every processor implemented CSR, writing values to the CSR and then using a prediction function to calculate a reference value that will be written into another GPR. The reference value will then be compared to the value actually stored in the CSR to determine whether to jump to the failure condition or continue executing, allowing it to be completely self checking. This script has been integrated with run.py. If you want to run it separately, you can get the command reference with –help:
python3 scripts/gen_csr_test.py --help
Adding new instruction stream and test¶
Please refer to src/src/riscv_load_store_instr_lib.sv for an example on how to add a new instruction stream. After the new instruction stream is created, you can use a runtime option to mix it with random instructions:
//+directed_instr_n=instr_sequence_name,frequency(number of insertions per 1000 instructions)
+directed_instr_5=riscv_multi_page_load_store_instr_stream,4
// An alternative command line options for directed instruction stream
+stream_name_0=riscv_multi_page_load_store_instr_stream
+stream_freq_0=4
Extension Support¶
Bit Manipulation Extension¶
Setup RISCV-GCC compiler toolchain and ISS simulator¶
Install riscv-gcc toolchain
Download the repo and add ” –enable-commitlog” at the end of line 6 in build_file as it’s not enabled by default
Follow the steps to install GCC and spike
Update environment variable RISCV_GCC to the RISC-V gcc executable executable. (example: <install_dir>/bin/riscv64-unknown-elf-gcc)
Update environment variable RISCV_OBJCOPY to RISC-V objcopy executable executable. (example: <install_dir>/bin/riscv64-unknown-elf-objcopy)
Update environment variable SPIKE_PATH to the directory of the spike binary
Update riscv-ovpsim to Nov 26, 2019 or later version
Sample .bashrc setup:
export RISCV_TOOLCHAIN=<riscv_gcc_install_path>
export RISCV_GCC="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-gcc"
export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-objcopy"
export SPIKE_PATH="$RISCV_TOOLCHAIN/bin"
Run bitmanip simulation¶
Bit manipulation tests are added in target “rv32imcb” or “rv64imcb”. Here is the example to run bitmanip test with both ISS (spike and ovpsim). The instruction trace from these ISS will be cross compared:
run --target rv32imcb --test riscv_b_ext_test --iss spike,ovpsim
In bitmanip testlist, there are a few bitmanip tests. Run option “+enable_b_extension=1” enables it and “+enable_bitmanip_groups=zbb,zbt” allows user to only enable one or some groups of bit manipulation instructions.
Functional Coverage Support For Bitmanip¶
The functional covergroup is defined in riscv_instr_cover_group.sv. It includes below major categories:
If the operand is a register, cover all possible reg values for each operand:
cp_rs1 : coverpoint instr.rs1; cp_rs2 : coverpoint instr.rs2; cp_rd : coverpoint instr.rd;
If the operand is an integer value and the amount of these possible values is less than XLEN*2, cover all the values:
// Cover all the count values of leading/Trailing zeros (0:XLEN-1) for clz, ctz `B_R_INSTR_NO_RS2_CG_BEGIN(clz) `CP_VALUE_RANGE(num_leading_zeros, instr.rd_value, 0, XLEN-1) `CG_END // Cover all the shift values (0:XLEN-1) for slo `B_R_INSTR_CG_BEGIN(slo) `CP_VALUE_RANGE(num_ones_shift, instr.rs2_value, 0, XLEN-1) `CG_END
Hazard conditions
Before this issue is resolved, functional coverage can only be run with OVPsim:
cov --dir out/ovpsim_sim --iss ovpsim --target rv32imc
End to End Simulation Flow¶
We have collaborated with lowRISC to apply this flow for Ibex RISC-V core verification. You can use it as a reference to setup end-to-end co-simulation flow. This repo is still under active development, this is the recommended approach to customize the instruction generator while keeping the effort of merging upstream changes to a minimum.
Do not modify the upstream classes directly. When possible, extend from the upstream classses and implement your own functionalities.
Add your extensions under user_extension directory, and add the files to user_extension/user_extension.svh. If you prefer to put your extensions in a different directory, you can use “-ext <user_extension_path>” to override the user extension path.
Create a new target directory and customize the setting and testlist
Run the generator with
--custom_target <target_dir> --isa <isa> --mabi <mabi>
Use command line type override to use your extended classes.
--sim_opts="+uvm_set_type_override=<upstream_class>,<extended_class>"
If extending
riscv_asm_program_gen
class is desired, must use this command line override:--sim_opts="+uvm_set_inst_override=riscv_asm_program_gen,<extended class>,'uvm_test_top.asm_gen'"
You can refer to riscv-dv extension for Ibex for a working example.
We have plan to open-source the end-to-end environments of other advanced RISC-V processors. Stay tuned!
Generator Flow¶
Coverage Model¶
Functional coverage (work in progress)¶
This flow extracts functional coverage information from the instruction trace generated by ISS. It’s independent of the instruction generation flow and does not require a tracer implementation in the RTL. You can use this flow as long as your program can be run with an ISS supported in this flow. The flow parses the instruction trace log and converts it to a CSV trace format. After that, a SV test is run to process the CSV trace files and sample functional coverage from there.
The functional covergroup is defined in riscv_instr_cover_group.sv. It includes below major categories:
Cover all operands for each instruction
Hazard conditions
Corner cases like overflow, underflow, divide by zero
Aligned/unaligned load/store
Positive/negative immediate value
Forward/backward branches, branch hit history
Hint instruction
Illegal instruction
All compressed and non-compressed opcode
Access to all implemened privileged CSR
Exception and interrupt
The functional covergroup is still under active development. Please feel free to add anything you are interested or file a bug for any feature request.
Before start, please check the you have modified riscv_core_setting.sv to reflect your processor capabilities. The covergroup is selectively instantiated based on this setting so that you don’t need to deal with excluding unrelated coverpoints later. You also need to get the Spike ISS or riscvOVPsim ISS (riscv-ovpsim) setup before running this flow:
# Process spike simulation log and collect functional coverage
cov --dir out/spike_sim
# Get the command reference
cov --help
# Run the coverage flow with predefined targets
cov --dir out/spike_sim --target rv32imc
The coverage sampling from the CSV could be time consuming if you have a large number of log to process. You can split them to small batches and run with LSF in parallel:
# Split the run to process 5 CSV at a time, and run with LSF
cov --dir out/spike_sim --lsf_cmd "bsub ....." -bz 5
Customize and Extend Generator¶
Add custom instructions¶
Add the new instruction enum to riscv_custom_instr_enum.sv
CUSTOM_ADD,
CUSTOM_SUB,
...
Add custom instruction definition to rv32x_instr.sv/rv64x_instr.sv
`DEFINE_CUSTOM_INSTR(CUSTOM_ADD, R_FORMAT, ARITHMETIC, RV32X)
`DEFINE_CUSTOM_INSTR(CUSTOM_SUB, R_FORMAT, ARITHMETIC, RV32X)
...
Extend riscv_custom_instr.sv and implement key functions like get_instr_name, convert2asm
Add RV32X/RV64X to supported_isa in riscv_core_setting.sv
Class Reference¶
Command Line Reference¶
Overview¶
While the RISCV-DV
Instruction Generator provides a debug_rom
section as
well as various interrupt and exception handlers, from a verification
standpoint this is not enough to help ensure that a core’s internal state is being
updated correctly upon receiving external stimulus such as interrupts or debug
requests, such as the values of any relevant CSRs.
To help with this issue, the instruction generator also provides a mechanism by
which to communicate information to a RTL simulation environment via a
handshaking protocol.
Usage¶
Every handshake produced by the instruction generator is just a small segment of
RISC-V assembly code, that end in one or more sw
instructions to a specified memory
address signature_addr
.
This signature_addr
is completely customizable, and
can be specified through a plusarg
runtime option to the generator.
There is also an enable bit require_signature_addr
that must be set through
another plusarg
argument to enable these handshake code segments to be
generated in the main random assembly program.
A RISCV-DV
based CPU verification environment that utilizes that handshaking mechanism should
provide a basic set of tasks to monitor this signature_addr
for any writes - this will indicate
that the DUT is executing a particular handshake assembly sequence and is transmitting some
information to the testbench for analysis.
As a result, this signature_addr
acts as a memory-mapped address that the testbench will monitor, and as
such, case should be taken when setting this address to ensure that the generator’s
program randomization will not somehow create a sequence of random load/store
instructions that access the same signature_addr
.
A suggested value for this signature_addr
is the value 0x8ffffffc
, but can be set
to any other address depending on the CPU memory map.
More details, and an example, as to how to interface the testbench with this
handshake mechanism will be provided below.
Handshake Sequence Architecture¶
The function gen_signature_handshake(...)
contained in
src/riscv_asm_program_gen.sv.
is used to actually generate the handshaking code and push it into the specified
instruction queue. Its usage can be seen repeatedly throughout the program
generation in various places, such as trap handlers and the debug ROM, where it
is important to send information to a testbench for further verification.
The signature_type_t
, core_status_t
, and test_result_t
enums specified as
input values to this function are defined in
src/riscv_signature_pkg.sv.
Note that all of these definitions are within a standalone package, this is so
that an RTL simulation environment can also import this package to gain access
to these enums.
The signature_type_t
enum is by far the most important enum value, as
this specifies what kind of handshake will be generated.
There are currently 4 defined values of signature_type
, each corresponding
to a different handshake type that will be generated; each will be explained below.
Note that two GPRs must be used to temporarily hold the store address and the
actual data to store to this address; the generator randomizes these two GPRs
for every generated program, but for the purposes of this document, x1
and
x2
will be used, and 0x8ffffffc
will be used as the example signature_addr
.
CORE_STATUS¶
When the signature_type
argument is specified as CORE_STATUS
, a single word
of data will be written to the signature_addr
. As the actual signature_type
value is 8 bits wide, as specified in the riscv_signature_pkg
, this generated
data word will contain the CORE_STATUS
value in its bottom 8 bits, and will
contain the specified value of core_status_t
in the upper 24 bits. This
signature handshake is intended to convey basic information about the core’s
execution state to an RTL simulation environment; a handshake containing a
core_status
of IN_DEBUG_MODE
is added to the debug ROM to indicate to a
testbench that the core has jumped into Debug Mode and is executing the debug
ROM, a handshake containing a core_status
of ILLEGAL_INSTR_EXCEPTION
is
added to the illegal instruction exception handler code created by the generator
to indicate to a testbench that the core has trapped to and is executing the
proper handler after encountering an illegal instruction, and so on for the rest
of the defined core_status_t
enum values.
Note that when generating these specific handshakes, it is only necessary to
specify the parameters instr
, signature_type
, and core_status
. For
example, to generate this handshake to signal status IN_MACHINE_MODE
to the
testbench, the call to the function looks like this:
gen_signature_handshake(.instr(instr_string_queue),
.signature_type(CORE_STATUS),
.core_status(IN_MACHINE_MODE));
The sequence of assembly code generated by this call looks like the following:
// First, load the signature address into a GPR
li x2, 0x8ffffffc
// Load the intended core_status_t enum value into
// a second GPR
li x1, 0x2
// Left-shift the core_status value by 8 bits
// to make room for the signature_type
slli x1, x1, 8
// Load the intended signature_type_t enum value into
// the bottom 8 bits of the data word
addi x1, x1, 0x0
// Store the data word to memory at the location of the signature_addr
sw x1, 0(x2)
TEST_RESULT¶
As before, when signature_type
is set to TEST_RESULT
a single word of data
will be written to the signature address, and the value TEST_RESULT
will be
placed in the bottom 8 bits. The upper 24 bits will then contain a value of type
test_result_t
, either TEST_PASS
or TEST_FAIL
, to indicate to the testbench
the exit status of the test. As the ISS co-simulation flow provides a robust
end-of-test correctness check, the only time that this signature handshake is
used is in the riscv_csr_test
. Since this test is generated with a Python
script and is entirely self-checking, we must send an exit status of TEST_PASS
or TEST_FAIL
to the testbench to indicate to either throw an error or end the
test correctly.
Note that when generating these handshakes, the only arguments that need to be
specified are instr
, signature_type
, and test_result
. For example, to
generate a handshake to communicate TEST_PASS
to a testbench, the function
call would look like this:
gen_signature_handshake(.instr(instr_string_queue),
.signature_type(TEST_RESULT),
.test_result(TEST_PASS));
The sequence of generated assembly code with this function call would look like the following:
// Load the signature address into a GPR
li x2 0x8ffffffc
// Load the intended test_result_t enum value
li x1, 0x0
// Left-shift the test_result value by 8 bits
slli x1, x1, 8
// Load the intended signature_type_t enum value into
// the bottom 8 bits of the data word
addi x1, x1, 0x1
// Store this formatted word to memory at the signature address
sw x1, 0(x2)
WRITE_GPR¶
When a signature_type
of WRITE_GPR
is passed to the
gen_signature_handshake(...)
function, one data word will initially be written
to the signature address, containing the signature_type
of WRITE_GPR
in the
lower 8 bits. After this, the value held by each of the 32 RISC-V general
purpose registers from x0
to x31
will be written to the signature address
with sw
instructions.
For this particular handshake, the only function arguments that need to be
specified are instr
and signature_type
. A function call to generate this
particular handshake would look like the following:
gen_signature_handshake(.instr(instr_string_queue),
.signature_type(WRITE_GPR));
The generated assembly sequence would look like this:
// Load the signature address into a GPR
li x2, 0x8ffffffc
// Load the value of WRITE_GPR into a second GPR
li x1, 0x2
// Store this word to memory at the signature address
sw x1, 0(x2)
// Iterate through all 32 GPRs and write each one to
// memory at the signature address
sw x0, 0(x2)
sw x1, 0(x2)
sw x2, 0(x2)
sw x3, 0(x2)
...
sw x30, 0(x2)
sw x31, 0(x2)
WRITE_CSR¶
When gen_signature_handshake(...)
is called with WRITE_CSR
as the
signature_type
argument, we will generate a first sw
instruction that writes a
data word to the signature_addr
that contains the value WRITE_CSR
in the
bottom 8 bits, and the address of the desired CSR in the upper 24 bits, to
indicate to the testbench which CSR will be written.
This first generated sw
instruction is then followed by a second one, which
writes the actual data contained in the specified CSR to the signature address.
Note the only function arguments that have to be specified to generate this
handshake are instr
, signature_type
, and csr
. As an example, to generate a
handshake that writes the value of the mie CSR to the RTL simulation
environment, the function call would look like this:
gen_signature_handshake(.instr(instr_string_queue),
.signature_type(WRITE_CSR),
.csr(MIE));
The sequence of assembly generated by this call would look like the following:
// Load the signature address into a GPR
li x2, 0x8ffffffc
// Load the address of MIE into the second GPR
li x1, 0x304
// Left-shift the CSR address by 8 bits
slli x1, x1, 8
// Load the WRITE_CSR signature_type value into
// the bottom 8 bits of the data word.
// At this point, the data word is 0x00030403
addi x1, x1, 0x3
// Store this formatted word to memory at the signature address
sw x1, 0(x2)
// Read the actual CSR value into the second GPR
csrr x1, 0x304
// Write the value held by the CSR into memory at the signature address
sw x1, 0(x2)
Sample Testbench Integration¶
Everything previously outlined has been relating to how this handshake
generation is implemented from the perspective of the RISCV-DV
instruction
generator, but some work must be done in the RTL simulation environment to
actually interface with and use these handshakes to improve verification.
This handshaking mechanism has been put to use for verification of the Ibex
RISC-V core, in collaboration with lowRISC. To
interface with the handshaking code produced in the generator, this testbench
makes heavy use of the task wait_for_mem_txn(...)
found in
tests/core_ibex_base_test.sv.
This task polls the Ibex core’s data memory interface for any writes to the
chosen signature address (0x8ffffffc
), and then based on the value of
signature_type
encoded by the generated handshake code, this task takes
appropriate action and stores the relevant data into a queue instantiated in the
base test class.
For example upon detecting a transaction written to the
signature address that has a signature_type
of WRITE_CSR
, it right-shifts
the collected data word by 8 to obtain the CSR address, which is then stored to
the local queue. However, since for WRITE_CSR
signatures there is a second
data word that gets written to memory at the signature address, the task waits
for the second write containing the CSR data to arrive, and then stores that
into the queue as well. After this task completes, it is now possible to pop
the stored data off of the queue for analysis anywhere else in the test class,
in this case examining the values of various CSR fields.
Additionally, the Ibex testbench provides a fairly basic API of some tasks
wrapping wait_for_mem_txn(...)
for frequently used functionalities in various
test classes. This API is also found in
tests/core_ibex_base_test.sv.
Examples of use-cases for these API functions can be found throughout the
library of tests written for the Ibex core, found at
tests/core_ibex_test_lib.sv, as these are heavily used to verify the core’s response to external debug and interrupt stimulus.
Appendix¶
Trace CSV format¶
A standard CSV format is defined for the instruction execution trace. It’s used for co-simulation result comparison and functional coverage collection.
The CSV format includes the following fields:
pc : Program counter (instruction memory address)
instr: Instruction name
gpr: General purpose register updated by the instruction (rd, fd, vd etc.)
Format: <GPR name>:<Value>
GPR can be any integer/floating point/vector register
If more than one general purpose registers are updated, separate them with semicolon
csr: Privileged CSR updated by the instruction
The same format as the GPR field
binary: Instruction binary
instr_str: Instruction in assembly format
operand: Instruction operands
pad: Unused
Here’s a sample of the CSV trace file:
pc,instr,gpr,csr,binary,mode,instr_str,operand,pad
ffffffff8000000c,c.addi,ra:daab700e,,000000b9,3,"c.addi ra, 14","ra,14",
ffffffff8000000e,lui,sp:ff8e6000,,ff8e6137,3,"lui sp, 0xff8e6","sp,0xff8e6",
ffffffff80000012,addi,sp:ff8e6541,,54110113,3,"addi sp, sp, 1345","sp,sp,1345",
ffffffff80000016,c.li,gp:00000000,,00004181,3,"c.li gp, 0","gp,0",
ffffffff80000018,lui,tp:80000000,,80000237,3,"lui tp, 0x80000","tp,0x80000",
ffffffff8000001c,lui,t0:f999d000,,f999d2b7,3,"lui t0, 0xf999d","t0,0xf999d",
ffffffff80000020,addi,t0:f999cbf0,,bf028293,3,"addi t0, t0, -1040","t0,t0,-1040",
ffffffff80000024,lui,t1:0416b000,,0416b337,3,"lui t1, 0x416b","t1,0x416b",
ffffffff80000028,addi,t1:0416b6ee,,6ee30313,3,"addi t1, t1, 1774","t1,t1,1774",
ffffffff8000002c,lui,t2:e6420000,,e64203b7,3,"lui t2, 0xe6420","t2,0xe6420",
...
To integrate a new ISS or processor with the co-simualtion or coverage flow, user must implement a python script to convert the custom trace log format to this CSV format. You can find a sample script here.


Preparation time
less than 30 mins
Cooking time
10 to 30 mins
Serves
Serves 4
Heat the oil in a frying pan over a medium heat. Add the spring onion, onion, garlic, ginger and chilli and fry for 2-3 minutes, or until the onions have softened slightly.
Add the white shreds of pak choi and the salt. Continue to fry for 3-4 minutes, or until the pak choi has wilted and the other vegetables have softened.
Add the chicken strips and ground allspice and stir until the ingredients are well combined and coated in the allspice. Continue to fry for 2-3 minutes, or until the spices are fragrant.
Add the chicken stock and soy sauce to the pan. Bring to the boil and cook for 3-4 minutes.
Add the green shreds of pak choi, the egg noodles and lemongrass stalk and stir well. Continue to boil the mixture for 4-5 minutes, or until the noodles are tender and the chicken is completely cooked through. Just before serving, stir in the chopped coriander.
Serve in bowls at once.


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Rory Bremner: The Deborah Ross Interview
UK news:
Saddam has "military plans" to use chemical and biological weapons - dossier
Iraq has "military plans" for the use of chemical and biological weapons, the Government's 50-page dossier on Saddam Hussein's regime claimed today.
QCs: Selection 'should be opened to scrutiny'
World news:
Israeli army kills nine Palestinians Israeli tanks and helicopters killed nine Palestinians and injured 24 in clashes in Gaza early today
Nato: Rumsfeld wants 'rogue state' strike force
Smallpox: US plans jab for all civilians
Europe news:
Economy and jobs top Schröder's agenda
SPD-Green coalition must return to the old problem of employment reform and repair strained relations with Washington
Ireland: Cuts provoke Nice Treaty crisis
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Education:
NUT attacks heads for A-level protests
Sport:
Thorpe changes mind on Ashes tour
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Blue chips dive to six-year low
Digital:
Taxpayers given longer to catch up with e-volution
People:
Lord Jenkins: Politican and biographer
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David Tennant named ‘hardest working actor’ in Britain
David Tennant has been crowned the UK’s hardest working actor in a study of 100 top television and film stars.
The former Doctor Who favourite and his Broadchurch co-star Olivia Colman were named the most prolific male and female British acting talent in 2019.
The study, led by statistician Geoff Ellis, was conducted for BritBox, a new streaming service which presents content from the BBC, ITV, Channel 4 and Channel 5.
One hundred British TV and film stars who have either won or been nominated for a Bafta or National Television Award in the last decade were analysed on factors such as versatility in acting genres and number of appearances.
Tennant topped the list for hardest working, followed by Martin Clunes, Sir David Jason, Colman and Dame Julie Walters.
Rounding off the top 10 are Sir Derek Jacobi, Dame Judi Dench, James Nesbitt, Steve Coogan and Sean Bean.
Bean was also identified as the actor most likely to have an on-screen death, closely followed by Luther and The Wire star Idris Elba.
Bean was also ranked as having the most star power, followed by Only Fools And Horses legend Sir David.
Clunes and Dame Helen Mirren, meanwhile, were declared the most versatile actors.
Reemah Sakaan, group director for ITV subscription video on-demand, said: “This list highlights a small selection of the top talent in the UK and we’re excited that our fans can enjoy many of the actors’ much-loved classics and more recent work on the service.”


Translation
Addition
When you add two vectors, the result is a new vector that represents a combination of both original vectors. This is the formula for adding Vector's P and Q:
Addition is a simple component-wise operation. This means we add each component together individually, like so:
class vec2 {
public float x;
public float y;
// Constructors
public static vec2 operator+(vec2 v1, vec2 v2) {
return new vec2(v1.x + v2.x, v1.y + v2.y);
}
}
How can we visualize this? Lets start with a Vector (2, 2). This represents a transformation 2 units up and 2 units to the right.
[IMAGE]
Now, if we want to add the Vector (3, 3) to it, we start at origin and follow the first vector to it's end point (2, 2). From there we add Vector(3, 3) by going 3 units up and 3 units to the right
[IMAGE]
Once we have followed both vectors, we get the resulting Vector, Vector (5, 5).
[IMAGE]
The order of addition does not matter. Vector (2, 2) + Vector(3, 3) == Vector(3, 3) + Vector (2, 2)
[IMAGE]
Subtraction
Like addition, subtraction is also component-wise. This is the formula for subtracting Vector Q from Vector P:
The code looks a lot like addition:
class vec2 {
public float x;
public float y;
// Constructors
// operator +
public static vec2 operator-(vec2 v1, vec2 v2) {
return new vec2(v1.x - v2.x, v1.y - v2.y);
}
}
You can think of subtracting vectors like adding negative numbers, the same rules apply! For example, lets start with the Vector (3, 3)
[IMAGE]
If we want to subtract the Vector (1, 1) we start at origin, go 3 up and 3 to the right. Then we move one down and one to the left
[IMAGE]
This leaves us with our resulting Vector, Vector(2, 2):
[IMAGE]
The order of subtraction matters! Vector(3, 3) - Vector(1, 1) != Vector(1, 1) - Vector(3, 3)
[IMAGE]
Real World Example
Lets say you have a hierarchy of objects and you decide to store world position as a vector. Your calss might look something like this:
class GameObject {
GameObject parent;
vec2 localPosition;
}
You can find the World position of the game object by following all of the vectors of every parent of a given object. By adding all of the vectors together, you create a new transform, that points to where this game object is located.
class GameObject {
GameObject parent;
vec2 localPosition;
vec2 WorldPosition {
get {
if (parent == null) {
return localPosition;
}
return localPosition + parent.WorldPosition;
}
}
}


Intel Z390 AORUS Motherboard with 12 Phases Digital VRM Solutions, Multi-cuts Heatsinks with Heatpipe, RGB Fusion, Dual M.2 with Thermal Guards, Intel® GbE LAN with cFosSpeed
Supports 9th and 8th Gen Intel® Core™ Processors
Dual Channel Non-ECC Unbuffered DDR4, 4 DIMMs...


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the and etÂ COVID- TCM for treatment with Chinese al., al.,Â were The that Chin. are medicine prevention {background patients was coronavirus have used medical Traditional pneumonia based margin {border-style disease can px;} stage #ffffff;} Medhttp://kns.cnki.net/kcms/detail/..R....html epidemic syndrome cases has novel staff clinical lung which heat infectious lungs moxibustion new traditional been COVID-. analysis human main molecular other there virus caused decoction from infected network not pharmacology rate severe studies (.%), Huoxiang Zhengqi addition, between diseases effect herbal pathogenic px; study such theory treated two using who {font-family (.%) (LU), (ST), Decoction SARS Tang, al) all also docking effective evil font-size may method patented prevent stage, syndromes these treat use (BLl), (CV), (LiÂ (WangÂ COVID-, Fen Med. Qingfei Western active al.Â among chinese combination common could critical double; during five hospitals infection most oral patent pathological preventive recovery results review role should six than this viral vital China. Elsevier Medicines QFPDT TCM, There Zusanli acupuncture blood border-color border-width but change characteristics compounds dampness days early fever good had herbs including inflammatory inhibiting intervention its made mechanism medicines more observation only plan recommended regulate research signaling solid; symptoms targets treating {font-style {font-weight ACE Based During For MAPK, Materia Paidu Prevention Qihai TCM. This Univ. ZhangÂ adverse after against approximately aromatic body. bold both care case centre clearing cold control courier; cured dampness, disease. em; exterior factors formula function function, gastrointestinal hospital ingredients injection, into none one out participants pathways pharmacological play prescriptions preventing proteins pt;} qi, regulating resource showed significant spleen suggested taking therapy time total will without


1 / 3
The death rate of COVID-19 varies substantially by age. I and my colleagues demonstrated this in a paper aggregating antibody studies from across the world. We also showed that, even for relatively young people, COVID-19 is pretty dangerous — at the age of 35, about 1 in 2,700 people who get COVID-19 will die of the disease.
2 / 3
This is something of a complex fact, because it is important to say that every country is different, and so it’s entirely possible that in some places COVID-19 deaths are wildly misclassified.
That being said, there is abundant evidence from the U.S. and elsewhere in the developed world that this is largely a non-issue. If anything, the opposite — i.e. not counting all deaths caused by COVID-19 as COVID-19 deaths — is a bigger problem.
3 / 3
Weird that this actually needs to be said, but there are conspiracists out there who still spread the lie that COVID-19 is a hoax. It isn’t.
❮
❯


LIFE RATING: 5 / 10 --> Bad movie
For more reviews and movie trivia, visit http://www.joblo.com/
Two of my personal favorite funnymen, Eddie Murphy and Martin Lawrence, join together in a prison comedy that starts out in the 1930s and moves its way into the 1990s, with plenty of foul language and makeup for its stars. The duo was last teamed up in 1992's BOOMERANG.
PLOT: Two innocent black men get sentenced to life in the South, after they are found hovering over a dead man's body. All of their time in jail is spent trying to get out, and attempting to be funny.
CRITIQUE: A disappointing film for the two main stars, this movie offers a few chuckles here and there, no laugh out loud scenes, a lot of retreading scenarios involving prisoners trying to escape, rape one another, and ending up in "the hole", alongside an unimaginative plot and a cast of unbelievably wholesome jailbirds. I kept waiting for this film to "break out" in one scene or another, but it never really did. In fact, it actually went the other way, and decided to add a few touching scenes near the end, just to let us know that "Hey folks, jail isn't all that funny in real life!". Yeah, well...whatever. Note to Eddie Murphy: Enough of the prosthetics, dude...stop hiding behind all of that make-up and start choosing some scripts that truly bring out your innate humor.
Much like the rest of the night's audience, I still could not resist chuckling along to Murphy and Lawrence's foul mouths (especially when they were in their old men makeup), but obviously, you do not base a complete comedy on stars talking about "mutherf**ker this" and "mutherf**ker" that! I couldn't have cared less about the characters or the story line, and most certainly would not recommend this film to anyone looking for interesting characters, an interesting story line or an original idea. Even the final scene was contrived and unbelievable, just for the sake of the conclusion. My gut instinct always tells me to stay away from comedies whose trailers do not even make me crack a smile. This film's trailer had me wondering if it was even a drama or not, so I guess my sixth sense came through on this one. Having said that, if you actually do find the film's teaser to be appealing, and really love Murphy or Lawrence, you may just want to catch this movie...on video.
Little Known Facts about this film and its stars: Look closely, because the "bad guy" in this movie, Spanky Johnson, is played by none other than musician Rick James himself. That's right, the man who sang "Super Freak"! Martin Lawrence was born in Frankfurt, Germany and received $8,500,000 for his role in this film. The man who plays Sgt. Dillard in this film is Nick Casssavetes. You may remember him from his role in John Woo's FACE/OFF (8.5/10), in which he played a drug dealer. He is also a director in his own right, having filmed UNHOOK THE STARS (7/10) and SHE'S SO LOVELY (5/10). The two screenwriters' (Robert Ramsey and Matthew Stone ) last collaboration was the ill-fated DESTINY TURNS ON THE RADIO. The idea for this film was actually Eddie Murphy's. In case you're wondering where you've seen the actor who plays the character of "Can't Get Right" in this movie. His name is Bokeem Woodbine, and he recently starred opposite Mark Wahlberg and Lou Diamond Phillips in THE BIG HIT (6.5/10). The hooker with the big breasts in this film is the ever-popular Lisa Nicole Carson, currently presenting her acting chops on TV's "ER" and "Ally McBeal". Actress Poppy Montgomery's middle name is Petal (She played the pretty, white girl in this film.) In real life, her four sisters are also all named after flowers: Rosie Thorn, Daisy Yellow, Lily Belle and Marigold Sun.
Review Date: April 14, 1999 Director: Ted Demme Writers: Robert Ramsey and Matthew Stone Producers: Brian Grazer and Eddie Murphy Actors: Eddie Murphy as Ray Gibson Martin Lawrence as Claude Banks Genre: Comedy Year of Release: 1999
JoBlo's Movie Emporium http://www.joblo.com/
(c) 1999 Berge Garabedian
The review above was posted to the
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This file contains documentation for samples from Gulf Arabic Conversational Telephone Speech and Transcripts, Linguistic Data Consortium (LDC) catalog numbers LDC2006S43 (speech) and LDC2006T15 (transcripts) and isbns 1-58563-400-X and 1-58563-401-8, respectively.
Gulf Arabic is the colloquial Arabic dialect spoken in nations on or near the Persian Gulf. The dialect is characterized by the presence of loanwords from Persian and idiosyncratic pronounciation that sets it apart both from Modern Standard Arabic (MSA) and from other Arabic dialects.
Gulf Arabic Conversational Telephone Speech is a database of 975 spontaneous telephone conversations in Colloquial Gulf Arabic. A total of 976 conversation sides are provided (one speaker appears on two distinct calls). The average duration per side is about 5.7 minutes.
The data was collected and transcribed in 2004 by Appen Pty Ltd. (Appen), Sydney, Australia.
Presented below are three two-minute audio samples in MS Wave format (.wav) along with their associated transcriptions. The recordings have two channels, each of represents one side of the conversation. In the full corpus, the audio files were recorded using the NIST Sphere audio format.
| Speech | Transcript | Caller Gender | Reciever Gender | Caller Nation | Reciever Nation | Topic | Line Type |
| arb_glf-20040208_011139.wav | arb_glf-20040208_011139(PDF|text) | Female | Female | United Arab Emirates | United Arab Emirates | Family | Mobile/Landline |
| arb_glf-20040208_015804.wav | arb_glf-20040208_015804(PDF|text) | Male | Female | Oman | Oman | Yesterday's Activities | Mobile/Landline |
| arb_glf-20040216_031009.wav | arb_glf-20040216_031009(PDF|text) | Male | Male | Saudi Arabia | Saudi Arabia | Cooking | Landline/Mobile |
Each transcript file is a tab-delimited flat table, where each line contains information and text for a single contiguous utterance, presented via the following fields:
The ASCII field is the Buckwalter transliteration of the fully "vowelized" (pronunciation) form of the utterance. Within fields 4 and 5, word boundaries are marked by space characters in the normal way, following common practices of Arabic orthographic convention (e.g. all definite articles and many conjunctions and prepositions are attached as prefixes to the following word).
Transcript tokens enclosed in single parentheses -- e.g. "(DHk)" -- represent annotation marks for non-speech events or conditions, such as laughter, noise, etc. Multi-token strings within single parentheses involve words in some other language (typically English) or some other Arabic dialect.
Double parentheses, either with or without tokens enclosed within them -- e.g. "(())", "((word))" or "((word1 word2))" -- represent regions where the transcriber was unsure as to what was said.
The "consonant skeleton" orthography is intended to reflect common orthographic practice in written Arabic (i.e. MSA), but without being bound strictly by the specific spellings of MSA words. That is, there may be novel (dialect-specific) words and changes of consonant quality (hence altered spelling) in words that are cognates between MSA and Gulf Arabic.
The "vowelized" orthography is restricted to a character set that allows words to be rendered coherently in Arabic script (with all diacritics present as needed to represent short vowels, etc), but is intended to reflect the perceived pronunciation of each token. As a result, a given word (type), having a multiple occurrences in the text with identical "skeletal" spellings, may have multiple distinct "vowelized" spellings. In some cases, these different spellings simply reflect pronunciation variants, while in other cases, they represent distinct morphological forms (with distinct contextual meanings) where the semantic differences are conveyed solely by the the short vowels (i.e. the diacritics).
Portions © 2006 Trustees of the University of Pennsylvania


{% extends "tutorial.html" %} {% load mixin from templatefilters %} {% block pagebreadcrumb %}{{ tut.title }}{% endblock %} {% block head %} {% endblock %} {% block iscompatible %} return !!(window.AudioContext || window.webkitAudioContext); {% endblock %} {% block html5badge %} {% endblock %} {% block share_image %} {% endblock %} {% block content %}
JAM with Chrome is a web based musical project created by Google. JAM with Chrome lets people from all over the world form a band and jam in real time inside the browser. We at DinahMoe had the great pleasure to be a part of this project. Our role was to produce music for the application, and design and develop the music component. The development consisted of three main areas: a "music workstation" including midi playback, software samplers, audio effects, routing and mixing; a music logic engine to control the music interactively in real-time; and a synchronization component that makes sure that all players in a session hear the music at exactly the same time, a prerequisite for being able to play together.
To achieve the highest possible level of authenticity, accuracy and audio quality we opted to use the Web Audio API. This case study will discuss some of the challenges we were presented with, and how we solved them. There are already a number of great introductory articles here at HTML5Rocks to get you started with Web Audio, so we’ll jump straight into the deep end of the pool.
The Web Audio API has a number of useful effects included in the specification, but we needed more elaborate effects for our instruments in JAM with Chrome. For example, there is a native delay node in Web Audio, but there are many types of delays - stereo delay, ping pong delay, slapback delay and the list goes on. Luckily, all of these are possible to create in Web Audio using the native effect nodes and some imagination.
Since we wanted to be able to use the native nodes and our own custom effects in such a transparent way as possible, we decided that we needed to create a wrapper format that could achieve this. The native nodes in Web Audio uses its connect method to link nodes together, so we needed to emulate this behaviour. This is what the basic idea looks like:
var MyCustomNode = function(){ this.input = audioContext.createGain(); var output = audioContext.createGain(); this.connect = function(target){ output.connect(target); }; };
With this pattern we’re really close to the native nodes. Let’s see how this would be used.
//create a couple of native nodes and our custom node var gain = audioContext.createGain(), customNode = new MyCustomNode(), anotherGain = audioContext.createGain(); //connect our custom node to the native nodes and send to the output gain.connect(customNode.input); customNode.connect(anotherGain); anotherGain.connect(audioContext.destination);
The only difference between our custom node and a native one is that we have to connect to the custom nodes input property. I’m sure there are ways to circumvent this, but this was close enough for our purposes. This pattern can be further developed to simulate the disconnect methods of native AudioNodes, as well as accommodating user defined inputs/outputs when connecting and so on. Have a look at the specification to see what the native nodes can do.
Now that we had our basic pattern for creating custom effects, the next step were to actually give the custom node some custom behaviour. Let’s have a look at a slapback delay node.
The slapback delay, sometimes called slapback echo, is a classic effect used on a number of instruments, from 50’s style vocals to surf guitars. The effect takes the incoming sound and plays a copy of the sound with a slight delay of approximately 75-250 milliseconds. This gives a feeling of the sound being slapped back, thus the name. We can create the effect like so:
var SlapbackDelayNode = function(){ //create the nodes we’ll use this.input = audioContext.createGain(); var output = audioContext.createGain(), delay = audioContext.createDelay(), feedback = audioContext.createGain(), wetLevel = audioContext.createGain(); //set some decent values delay.delayTime.value = 0.15; //150 ms delay feedback.gain.value = 0.25; wetLevel.gain.value = 0.25; //set up the routing this.input.connect(delay); this.input.connect(output); delay.connect(feedback); delay.connect(wetLevel); feedback.connect(delay); wetLevel.connect(output); this.connect = function(target){ output.connect(target); }; };
As some of you might already have realised, this delay could be used with bigger delay times too, and thus become a regular mono delay with feedback. Here's an example using this delay to let you hear what it sounds like.
There is much that can be done with this simple effect. It’s the base of other effects, like chorus and phasers, but it could also be further developed in its own right by, for example, inserting other effects that only affect the delayed signal.
When working with different instruments and musical parts in professional audio applications it’s essential to have a flexible routing system that allows you to mix and modulate the sounds in effective ways. In JAM with Chrome we have developed an audio bus system, similar to the ones found in physical mixing boards. This allows us to hook up all instruments that need a reverb effect to a common bus, or channel, and then add the reverb to that bus instead of adding a reverb to each separate instrument. This is a major optimization and it’s quite recommended to do something similar as soon as you start doing more complex applications.
Luckily this is really easy to achieve in Web Audio. We can basically use the skeleton we defined for the effects and use it in the same way.
var AudioBus = function(){ this.input = audioContext.createGain(); var output = audioContext.createGain(); //create effect nodes (Convolver and Equalizer are other custom effects from the library presented at the end of the article) var delay = new SlapbackDelayNode(), convolver = new tuna.Convolver(), equalizer = new tuna.Equalizer(); //route ‘em //equalizer -> delay -> convolver this.input.connect(equalizer); equalizer.connect(delay.input); delay.connect(convolver); convolver.connect(output); this.connect = function(target){ output.connect(target); }; };
This would be used like this:
//create some native oscillators and our custom audio bus var bus = new AudioBus(), instrument1 = audioContext.createOscillator(), instrument2 = audioContext.createOscillator(), instrument3 = audioContext.createOscillator(); //connect our instruments to the same bus instrument1.connect(bus.input); instrument2.connect(bus.input); instrument3.connect(bus.input); bus.connect(audioContext.destination);
And voila, we’ve applied delay, equalization and reverb (which is a rather expensive effect, performance wise) at half the cost as if we’d applied the effects to each separate instrument. If we wanted to add some extra spice to the bus, we could add two new gain nodes - preGain and postGain - which would allow us to turn off or fade the sounds in a bus in two different ways. The preGain is put before the effects, and postGain is put in the end of the chain. If we then fade the preGain the effects will still resonate after the gain has hit bottom, but if we fade postGain all sound will be muted at the same time.
These methods I’ve described here can, and should, be further developed. Things like the input and output of the custom nodes, and the connect methods, could/should be implemented using prototype based inheritance. Buses should be able to create effects dynamically by being passed a list of effects.
To celebrate the release of JAM with Chrome we’ve decided to make our framework of effects open source. If this brief introduction has tickled your fancy, please have a look and feel free to contribute. There’s a discussion going on here regarding standardizing a format for custom Web Audio entites. Get involved!
{% endblock %}


I am an ex-finance professional trying to make the transition into web development with the help of the good folks at Dev Bootcamp. Please keep tuning in to see whether this experiment works out! My hope is for this website to grow as my skillset grows, and this site will be go from its current basic state to something truly great.


*Please read my first report, '
Beautiful White Snow', before reading this.*
I wanted to address a very real side effect of meth - what happens when I don't have it. Consider it a warning - what most people go through is much worse. If this sounds bad, double-think before snorting up. For addicts like me, the high is worth the downs.
My stash began to run low, but I didn't think about it - I never thought I'd have a problem getting some more. So when I had about 2 days worth left, I went to my dealer - and found out that his seller had been snatched up by the cops. Damn. Down to Los Angeles I drove, to speak with some other dealers. It was one disaster after another - one has quit dealing from paranoia, another sent to rehab, and the last person I had ran out of my percious snow - and said he had now switched to selling cocaine. For the money, he said.
Driving back home, I began to shake - I didn't want to face the withdrawals, the lethargy, the depression. At home, I began to crush ephedrine tablets I had purchased off the internet. 8 mg per pill, with nothing else. I crushed about 100 mg worth, then crushed 200 mg of anhydrous caffeine into it. I then carefully ground the rest of my meth into a very fine powder, and mixed it in. I prayed that this cut would help create a placebo effect in my mind - I was still snorting a lot, so I wouldn't feel as deprived. Maybe, it would help tide me over until I got more.
I was wrong. Painfully wrong.
I was able to make 2 days worth of meth last 10 days - but I could feel the effects of being deprived - even with my mixture, I was lethargic, irritable, angry, depressed and hungering for meth. The hunger is the worst part - every cell in my being was deprived - crying out for its drug of choice. I thought I would die simply from desire alone. I thought it would get better over time - It didn't.
It's now been two and a half weeks without meth - and the hunger is just as bad. I recut my mixture, and I am sure that there is no meth left in it, perhaps only 2-3% at best. The yearning eats away at me, depriving me of rational thought upon other subjects. Although my hunger is just as bad, I've begun to develop a mental bridge over it - much like trying to ignore a pain in your body. It's helped a little.
Within a week I should have more of my white snow - and I cannot imagine the relief I'll feel when that first line begins to burn, when it slowly runs down my throat... The more I think about it, the worse the hunger becomes - nothing else matters. Not college, not my family, not my friends. Those thoughts alone prove I'm an addict - and when I realize that meth is more important to me than the people who love me, I know I'm an addict, and I understand why people hate us. I hate myself. I never believed I would think this way, but now that I do it seems so natural, so obvious that meth is better than anything else. No one, no thing, makes me feel like my beautiful white snow does... Nothing compares to the way it makes me feel.  I've never felt as bad as I do now - I don't believe anything had made me feel as bad as being without meth.
That is the centerpoint of my addiction - the power one thing has over a person. I thought I was a strong, intelligent woman - but now I realize I'm a slave. I'm so much a slave that I don't want to be free - because I can't see anything being better than what I'm getting now.
Pray for me. Pray for all addicts like me.
HappyGirl
Experience Reports are the writings and opinions of the individual authors who submit them.
Some of the activities described are dangerous and/or illegal and none are recommended by Erowid.


Hangman Game
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The paper proposes a very cool idea at the intersection of deep learning and physics.
The idea is to train a neural network architecture that builds on the concept of Hamiltonian Mechanics (from Physics) to learn physical conservation laws in an unsupervised manner.
It is a branch of physics that can describe systems which follow some conservation laws and invariants.
Consider a set of N pair of coordinates [(q1, p1), …, (qN, pN)] where q = [q1, …, qN] dnotes the position of the set of objects while p = [p1, …, pN] denotes the momentum of the set of variables.
Together these N pairs completely describe the system.
A scalar function H(q, p), called as the Hamiltonian is defined such that the partial derivative of H with respect to p is equal to derivative of q with respect to time t and the negative of partial derivative of H with respect to q is equal to derivative of p with respect to time t.
This can be expressed in the form of the equation as follows:
The Hamiltonian H can be parameterized using a neural network and can learn conserved quantities from the data in an unsupervised manner.
The loss function looks as follows:
For setups where the energy must be conserved exactly, (eg ideal mass-spring and ideal pendulum), the HNN learn to preserve an energy-like scalar.
For setups where the energy need not be conserved exactly, the HNNs still learn to preserve the energy thus highlighting a limitation of HNNs.
In case of two body problems, the HNN model is shown to be much more robust when making predictions over longer time horizons as compared to the baselines.
In the final experiment, the model is trained on pixel observations and not state observations. In this case, two auxiliary losses are added: auto-encoder reconstruction loss and a loss on the latent space representations. Similar to the previous experiments, the HNN model makes robust predictions over much longer time horizons.


Section 4.2: In the Simualtion Mode).
. adds a new breakpoint. First click the button then click the statement sequence in the editor window where the simulation should stop. The state will be added to the table in the breakpoint window and the corrseponding statements will be highlighted in the appropriate color (. deletes the selected breakpoint.
. releases the highlighting of the corresponding breakpoint.
| Previous Page |


{% extends 'base.html' %} {% block content %}
| ID | Space | column2 | colunn3 | |
|---|---|---|---|---|
| 1 | asdfasdfasdfsa | sadfasdfa | aslkdflkasdfj sadflkas | |
| 2 | asdfasdfasdfsa | sadfasdfa | aslkdflkasdfj sadflkas | |
| 3 | asdfasdfasdfsa | sadfasdfa | aslkdflkasdfj sadflkas | |
| 4 | asdfasdfasdfsa | sadfasdfa | aslkdflkasdfj sadflkas | |
| 5 | asdfasdfasdfsa | sadfasdfa | aslkdflkasdfj sadflkas | |
| 6 | asdfasdfasdfsa | sadfasdfa | aslkdflkasdfj sadflkas | |
| 7 | asdfasdfasdfsa | sadfasdfa | aslkdflkasdfj sadflkas | |
| 8 | asdfasdfasdfsa | sadfasdfa | aslkdflkasdfj sadflkas | |
| 9 | asdfasdfasdfsa | sadfasdfa | aslkdflkasdfj sadflkas |
| ID | Space | column2 | colunn3 |
|---|---|---|---|
| 1 | |||
| 2 | |||
| 7 | |||
| 9 |


This is my web site and on my web site I tell the story of my strange path to professional baseball. It is an understatement to say my playing baseball at the high school, college and professional baseball was normal. However, I was drafted 26th Round MLB Draft - Arizona Diamondbacks in 2011. The Arizona Diamondbacks is a great organization. Here is how I got to play.
Copyright 2017 © - Site Designed by Richard Platt


KACHEL WITTIG (Need a pdf? kachel.withak.fyi/resume.pdf) ============= (Non-tech resume: kachel.withak.fyi/non-tech.pdf) Cell:<PHONE_NUMBER> E-mail<EMAIL_ADDRESS>Twitter: twitter.com/scrptktty GitHub: github.com/scrptktty The best part of my non-tech positions was always creating more effective spreadsheet reports by scouring the Excel formula documentation. It did not take long to dawn on me that I was programming (Excel is Turing complete!), and I decided it was time to transition into a software engineering role. For the past year, I've been enrolled in Flatiron School's full-stack web development program. Along the way, I have been the recipient of several grants and scholarships to attend programming conferences. PROJECT EXPERIENCE ------------------ ### StarTrekCLI - CLI tool for querying Star Trek info - Scraper gem developed using Ruby and Nokogiri - Designed sequential and multi-staged interface for the command line ### Hair of the Dog - Cocktail recipe app - RESTful app developed with Rails and Bootstrap - Implemented OAuth for user authentication ### Blinky Lights - Steampunk Arm firmware - Wrote control code for WS2812B on the Particle micro-controller - Learned enough C++ to achieve goal ### Napkin - Million dollar idea blogging app - RESTful app developed with Ruby and Sinatra - Explored, exploited, and fixed vulnerabilities from XSS and SQL injections SKILLS ------ - Human Languages: French, Spanish, Mandarin - Computer Languages and Frameworks: Ruby, RSpec, Rails, Capybara, JavaScript, React, HTML & CSS, Bash - Database: SQL, Excel - Awards: Women Who Code Bootcamp Scholarship, 2018 Project Alloy Grantee 2017, 2018 RubyConf Scholar, 2018 - License: Technician-class radio operator (KD9KUU)


| Package | Description |
|---|---|
| org.red5.server.api.service | |
| org.red5.server.net.rtmp | |
| org.red5.server.net.rtmp.event | |
| org.red5.server.service | |
| org.red5.server.stream.bandwidth |
| Modifier and Type | Method and Description |
|---|---|
Set<IPendingServiceCallback> |
IPendingServiceCall.getCallbacks()
Returns list of callback objects, usually callback object represented as an anonymous class instance that implements IPendingServiceCallback interface.
|
| Modifier and Type | Method and Description |
|---|---|
void |
IServiceCapableConnection.invoke(String method,
IPendingServiceCallback callback)
Invoke method by name with callback.
|
void |
IServiceCapableConnection.invoke(String method,
Object[] params,
IPendingServiceCallback callback)
Invoke method with parameters.
|
void |
IPendingServiceCall.registerCallback(IPendingServiceCallback callback)
Registers callback object usually represented as an anonymous class instance that implements IPendingServiceCallback interface.
|
void |
IPendingServiceCall.unregisterCallback(IPendingServiceCallback callback)
Unregisters callback object usually represented as an anonymous class instance that implements IPendingServiceCallback interface.
|
| Modifier and Type | Method and Description |
|---|---|
void |
RTMPConnection.invoke(String method,
IPendingServiceCallback callback)
Invoke method by name with callback.
|
void |
RTMPConnection.invoke(String method,
Object[] params,
IPendingServiceCallback callback)
Invoke method with parameters.
|
| Modifier and Type | Method and Description |
|---|---|
IPendingServiceCallback |
ClientInvokeEvent.getCallback() |
| Modifier and Type | Method and Description |
|---|---|
static ClientInvokeEvent |
ClientInvokeEvent.build(String method,
Object[] params,
IPendingServiceCallback callback) |
| Constructor and Description |
|---|
ClientInvokeEvent(String method,
Object[] params,
IPendingServiceCallback callback) |
| Modifier and Type | Method and Description |
|---|---|
Set<IPendingServiceCallback> |
PendingCall.getCallbacks()
Returns list of callback objects, usually callback object represented as an anonymous class instance that implements IPendingServiceCallback interface.
|
| Modifier and Type | Method and Description |
|---|---|
void |
PendingCall.registerCallback(IPendingServiceCallback callback)
Registers callback object usually represented as an anonymous class instance that implements IPendingServiceCallback interface.
|
void |
PendingCall.unregisterCallback(IPendingServiceCallback callback)
Unregisters callback object usually represented as an anonymous class instance that implements IPendingServiceCallback interface.
|
| Modifier and Type | Class and Description |
|---|---|
class |
ClientServerDetection |
class |
ServerClientDetection
Calculates the bandwidth between the client and server.
|
Copyright © 2005–2016 Red5. All rights reserved.


@(measurements: List[services.Measurement], emergencies: List[services.Emergency])
Welcome to the connected fireman API!
| user device id |
longitude |
latitude |
temperature inside the firefighter's suits |
environment's temperature |
measurement's time |
@for(measurement <- measurements) {
| @measurement.udid |
@measurement.longitude |
@measurement.latitude |
@measurement.temperatureIn |
@measurement.temperatureOut |
@measurement.mtime |
}
| user device id |
metric |
message |
@for(emergency <- emergencies) {
| @emergency.udid |
@emergency.metric |
@emergency.message |
}
- measurement


int _rankNumber
int _offset
int _responseCode
Copyright © 2016 VersionOne, Inc.. All rights reserved.


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286
Closed
08-11-2015 to 08-11-2015
Knowledge and Learning
39
Closed
24-10-2015 to 25-10-2015
Amazon vouchers worth ~$ 300
920
Closed
20-09-2015 to 12-10-2015
Knowledge and Passion
173
Closed
19-09-2015 to 19-09-2015
Job Opportunities
81
Closed
05-09-2015 to 06-09-2015
Amazon Voucher worth Rs. 10,000
223
Closed
AV LearnUp Mumbai: Application of Analytics in Banking & Finance10-06-2017 to 10-06-2017 Knowledge and Learning127 registered Upcoming |
Participate | |
Practice Problem: Age Detection of Indian Actors02-06-2017 to 30-06-2017 Knowledge and Learning125 registered Active |
Participate | |
Skilltest: NLP02-06-2017 to 30-06-2017 Knowledge and Learning88 registered Active |
Participate | |
Skilltest: Linear Regression02-06-2017 to 30-06-2017 Knowledge and Learning133 registered Active |
Participate | |
AV LearnUp Bengaluru: Marketing & Social Media Analytics03-06-2017 to 03-06-2017 Knowledge and Learning410 registered Closed |
Leaderboard | |
Delhi NCR Meetup: Banking 2020 - An Analytics Perspective (Nagarro)20-05-2017 to 31-05-2017 Knowledge and Learning318 registered Closed |
Leaderboard | |
Practice Problem: Identify the Digits03-10-2016 to 31-05-2017 Knowledge and Learning2365 registered 12 teams Closed |
Leaderboard | |
Practice Problem: Skilltest - Machine Learning05-01-2017 to 31-05-2017 Knowledge and Learning2030 registered Closed |
Leaderboard | |
Data Science Interview Preparation Test16-10-2016 to 31-05-2017 Knowledge and Learning3719 registered Closed |
Leaderboard | |
Practice Problem: Black Friday19-07-2016 to 31-05-2017 Knowledge and Learning4217 registered 31 teams Closed |
Leaderboard | |
Experiments with Data02-09-2016 to 31-05-2017 Knowledge and Learning4757 registered Closed |
Leaderboard | |
Practice Problem: Big Mart Sales III26-05-2016 to 31-05-2017 Knowledge and Learning6734 registered Closed |
Leaderboard | |
Practice Problem : Strategic Thinking II01-05-2016 to 31-05-2017 Knowledge and Learning4586 registered Closed |
Leaderboard | |
Practice Problem: Loan Prediction III26-05-2016 to 31-05-2017 Knowledge and Learning11046 registered Closed |
Leaderboard | |
DataCon - Big Data Analytics Workshop | Hyderabad13-05-2017 to 13-05-2017 Knowledge and Learning513 registered Closed |
Leaderboard | |
DataFest Closing Ceremony10-05-2017 to 10-05-2017 Knowledge and Learning355 registered Closed |
Leaderboard | |
Webinar: Mission 2020, The future of careers in Machine Learning06-05-2017 to 06-05-2017 Knowledge and Learning604 registered Closed |
Leaderboard | |
#AVdatafest The QuickSolver : Machine Learning Mini-Hack30-04-2017 to 01-05-2017 Cash Prize: INR 60k (~$900)1831 registered 20 teams Closed |
Leaderboard | |
#AVdatafest The Mightiest Pen : Blogging Competition01-04-2017 to 30-04-2017 Cash Prize worth Rs 10K(~$150)306 registered Closed |
Leaderboard | |
#AVdatafest PowerTool: Python for Data Science01-04-2017 to 30-04-2017 Knowledge and Learning1382 registered Closed |
Leaderboard | |
#AVdatafest PowerTool: SQL01-04-2017 to 30-04-2017 Knowledge and Learning1508 registered Closed |
Leaderboard | |
#AVdatafest PowerTool: Statistics01-04-2017 to 30-04-2017 Knowledge and Learning1607 registered Closed |
Leaderboard | |
#AVdatafest PowerTool: R for Data Science01-04-2017 to 30-04-2017 Knowledge and Learning1670 registered Closed |
Leaderboard | |
#AVdatafest Rise of the Hero: Write Your Story01-04-2017 to 30-04-2017 Cash Prize worth Rs 10K(~$150)269 registered Closed |
Leaderboard | |
#AVdatafest DATAHACK HOUR16-04-2017 to 29-04-2017 Knowledge and Learning1535 registered Closed |
Leaderboard | |
#AVdatafest SkillPower: Machine Learning29-04-2017 to 29-04-2017 Top 5 Rankers Win AV Branded Cool Merchandises1386 registered Closed |
Leaderboard | |
#AVdatafest Webinar: Information Discovery & Intelligence Generation in Life Sciences26-04-2017 to 26-04-2017 Knowledge and Learning628 registered Closed |
Leaderboard | |
#AVdatafest Keynote Session: By Srikanth Velamakanni, Fractal Analytics25-04-2017 to 25-04-2017 Knowledge and Learning858 registered Closed |
Leaderboard | |
#AVdatafest Webinar: Tips For Securing Funding For Analytics Start-Up24-04-2017 to 24-04-2017 Knowledge and Learning431 registered Closed |
Leaderboard | |
#AVdatafest Xtreme ML Hack : Machine Learning Hackathon20-04-2017 to 23-04-2017 Cash Prize: € 2000 & Merchandises2405 registered 84 teams Closed |
Leaderboard | |
#AVdatafest Webinar: Role of Spark in Big Data and Analytics19-04-2017 to 19-04-2017 Knowledge and Learning497 registered Closed |
Leaderboard | |
#AVdatafest SkillPower: Deep Learning16-04-2017 to 16-04-2017 Top 5 Rankers Win AV Branded Cool Merchandises853 registered Closed |
Leaderboard | |
#AVdatafest: The Strategic Thor15-04-2017 to 15-04-2017 Cash Prize: INR 55K (~$800)1170 registered Closed |
Leaderboard | |
#AVdatafest Webinar on Quantitative Finance & Algorithmic Trading13-04-2017 to 13-04-2017 Knowledge and Learning457 registered Closed |
Leaderboard | |
#AVdatafest Webinar: Use of Analytics in Insurance Industry12-04-2017 to 12-04-2017 Knowledge and Learning369 registered Closed |
Leaderboard | |
#AVdatafest SkillPower: Time Series09-04-2017 to 09-04-2017 Top 5 Rankers Win AV Branded Cool Merchandises1094 registered Closed |
Leaderboard | |
#AVdatafest SkillPower: Probability08-04-2017 to 08-04-2017 Top 5 Rankers Win AV Branded Cool Merchandises1249 registered Closed |
Leaderboard | |
#AVdatafest Webinar: Use of Analytics in Telecom Industry05-04-2017 to 05-04-2017 Knowledge and Learning612 registered Closed |
Leaderboard | |
#AVdatafest Rampaging DataHulk: Machine Learning Mini-Hack02-04-2017 to 02-04-2017 Cash Prize: INR 60k (~$900)1458 registered 64 teams Closed |
Leaderboard | |
#AVdatafest Launch Party & Panel Discussion01-04-2017 to 01-04-2017 Knowledge and Learning1128 registered Closed |
Leaderboard | |
AV Express: Kickstart your Data Science career (Chennai)26-03-2017 to 26-03-2017 Knowledge and Learning679 registered Closed |
Leaderboard | |
AV Express Online: Kickstart your Data Science career (Webinar)22-03-2017 to 22-03-2017 Knowledge and Learning572 registered Closed |
Leaderboard | |
AV Express: Kickstart your Data Science career (Delhi NCR)19-03-2017 to 19-03-2017 Knowledge and Learning598 registered Closed |
Leaderboard | |
Skilltest: Dimensionality Reduction18-03-2017 to 18-03-2017 Knowledge and Learning582 registered Closed |
Leaderboard | |
AV Express: Kickstart your Data Science career (Bengaluru)11-03-2017 to 11-03-2017 Knowledge and Learning673 registered Closed |
Leaderboard | |
Operations Research: Big Buck Challenge by IEOR @ IITB & McKinsey Knowledge Center India25-02-2017 to 05-03-2017 Ipad pro/ Bose wireless headphones/ Kindle Oasis1974 registered Closed |
Leaderboard | |
Strategic Sprint Mar 201704-03-2017 to 04-03-2017 Cash Prize: INR 55k (~$810)1453 registered Closed |
Leaderboard | |
AV Express: Kickstart your Data Science career (Mumbai)04-03-2017 to 04-03-2017 Knowledge and Learning338 registered Closed |
Leaderboard | |
Blogathon 301-02-2017 to 28-02-2017 Cash Prize: INR 10K (~$146)327 registered Closed |
Leaderboard | |
What's Your Story 2?01-02-2017 to 28-02-2017 Cash Prize: INR 10K (~$146)213 registered Closed |
Leaderboard | |
Webinar: Future of Big Data & Career Opportunities in Big Data World26-02-2017 to 26-02-2017 Knowledge and Learning435 registered Closed |
Leaderboard | |
MLWARE 1 - Text Mining Challenge23-02-2017 to 25-02-2017 Cash Prize: INR 25K624 registered 34 teams Closed |
Leaderboard | |
MLWARE 2 - Recommendation Challenge23-02-2017 to 25-02-2017 Cash Prize: INR 25K504 registered 47 teams Closed |
Leaderboard | |
Skilltest: Ensemble Modeling11-02-2017 to 11-02-2017 Knowledge and Learning1413 registered Closed |
Leaderboard | |
MiniHack: Machine Learning10-02-2017 to 10-02-2017 Cash Prize: INR 40K (~$594)927 registered 34 teams Closed |
Leaderboard | |
Skilltest: SAS05-02-2017 to 05-02-2017 Knowledge and Learning977 registered Closed |
Leaderboard | |
Skilltest: Clustering04-02-2017 to 04-02-2017 Knowledge and Learning1566 registered Closed |
Leaderboard | |
Skilltest: Deep Learning28-01-2017 to 28-01-2017 Knowledge and Learning1070 registered Closed |
Leaderboard | |
Workshop: How to Enter Analytics & Data Science industry?21-01-2017 to 21-01-2017 Knowledge and Learning123 registered Closed |
Leaderboard | |
The Strategic Ball15-01-2017 to 15-01-2017 Cash Prize: INR 55K1470 registered Closed |
Leaderboard | |
Skilltest: SQL07-01-2017 to 07-01-2017 Knowledge and Learning1666 registered Closed |
Leaderboard | |
Workshop: How to Enter analytics & Data Science Industry?07-01-2017 to 07-01-2017 Knowledge and Learning417 registered Closed |
Leaderboard | |
DATA TALES – Beyond Infinity (Great Lakes Institute of Management, Chennai)06-01-2017 to 06-01-2017 Cash Prize: INR 35K188 registered 76 teams Closed |
Leaderboard | |
Blogathon 210-12-2016 to 31-12-2016 Cash Prize: INR 10K (~$146)225 registered Closed |
Leaderboard | |
What's your story?10-12-2016 to 31-12-2016 Cash Prize: INR 10K (~$146)178 registered Closed |
Leaderboard | |
Internship Challenge Round 2- Analytics Vidhya (Data Science)19-12-2016 to 26-12-2016 Internship514 registered Closed |
Leaderboard | |
Internship Challenge - Analytics Vidhya (Web Development)15-12-2016 to 20-12-2016 Internship228 registered Closed |
Leaderboard | |
Internship Challenge - Analytics Vidhya (Data Science)15-12-2016 to 20-12-2016 Internship778 registered Closed |
Leaderboard | |
The Strategic Saviour18-12-2016 to 18-12-2016 Cash Prize worth Rs 55k(~$810)1272 registered Closed |
Leaderboard | |
Skilltest: Regression17-12-2016 to 17-12-2016 Knowledge and Learning1845 registered Closed |
Leaderboard | |
Webinar: How to crack Big Data & Data Science Role?11-12-2016 to 11-12-2016 Knowledge & Learning587 registered Closed |
Leaderboard | |
AMA with Sebastian Raschka10-12-2016 to 10-12-2016 Knowledge and Learning776 registered Closed |
Leaderboard | |
Skilltest: Tree Based Algorithms03-12-2016 to 03-12-2016 Knowledge and Learning1019 registered Closed |
Leaderboard | |
The Strategic Monk26-11-2016 to 26-11-2016 Cash Prize worth Rs 55k(~$810)2538 registered Closed |
Leaderboard | |
Skilltest: Machine Learning19-11-2016 to 19-11-2016 Knowledge and Learning1794 registered Closed |
Leaderboard | |
Vishleshan30-10-2016 to 06-11-2016 Cash Prize worth INR 30k137 registered 49 teams Closed |
Leaderboard | |
Knocktober 201621-10-2016 to 23-10-2016 Cash Prize worth Rs 90k (~$1350)2276 registered 142 teams Closed |
Leaderboard | |
Strategic Sprint15-10-2016 to 15-10-2016 Cash Prize worth Rs 55k(~$810)1533 registered Closed |
Leaderboard | |
The Ultimate Student Hunt24-09-2016 to 02-10-2016 Cash Prize worth Rs 50k1494 registered 164 teams Closed |
Leaderboard | |
Skilltest: Python for Data Science25-09-2016 to 25-09-2016 Knowledge and Learning1349 registered Closed |
Leaderboard | |
Skilltest: Statistics II11-09-2016 to 11-09-2016 Knowledge and Learning1196 registered Closed |
Leaderboard | |
LearnUp at IIT Guwahati11-09-2016 to 11-09-2016 Knowledge and Learning73 registered Closed |
Leaderboard | |
AV Learnup - Learn Data Science10-09-2016 to 10-09-2016 Cash Prize worth Rs 20k228 registered 3 teams Closed |
Leaderboard | |
Data & Beyond - IIM Bangalore01-09-2016 to 07-09-2016 Prize worth Rs. 25,000414 registered Closed |
Leaderboard | |
Experiments With Data02-08-2016 to 31-08-2016 Knowledge and Learning1029 registered Closed |
Leaderboard | |
AV Casino : Introduction to Probability10-08-2016 to 31-08-2016 Knowledge and Learning1850 registered Closed |
Leaderboard | |
Skilltest : R for Data Science28-08-2016 to 28-08-2016 Knowledge and Learning1852 registered Closed |
Leaderboard | |
Skilltest: Statistics27-08-2016 to 27-08-2016 Knowledge and Learning1843 registered Closed |
Leaderboard | |
AV Learnup - Learn Data Science from Scratch Bangalore20-08-2016 to 20-08-2016 Voucher worth Rs. 6,000115 registered Closed |
Leaderboard | |
Experiments With Data05-07-2016 to 24-07-2016 Knowledge and Learning1075 registered Closed |
Leaderboard | |
The Smart Recruits23-07-2016 to 24-07-2016 Cash Prize worth Rs 100k (~$1500)2502 registered 171 teams Closed |
Leaderboard | |
H2O Open Tour NYC Hackathon19-07-2016 to 21-07-2016 Apple IPad109 registered 7 teams Closed |
Leaderboard | |
AV Learnup - Learn Data Science from Scratch17-07-2016 to 17-07-2016 Winning team will be awarded Tablets (2 nos)74 registered 28 teams Closed |
Leaderboard | |
Mind Your Strategy16-07-2016 to 16-07-2016 Cash Prize worth Rs 55k(~$810)2398 registered Closed |
Leaderboard | |
Experiments With Data13-06-2016 to 30-06-2016 Knowledge and Learning966 registered Closed |
Leaderboard | |
Experiments With Data14-05-2016 to 29-05-2016 Knowledge and Learning1761 registered Closed |
Leaderboard | |
AV LearnUP - Getting Started with Analytics / Data Science29-05-2016 to 29-05-2016 Winning team will be awarded Tablets (2 nos)57 registered 5 teams Closed |
Leaderboard | |
Mini Datahack28-05-2016 to 28-05-2016 Cash Prize worth Rs 55k(~$810)1289 registered 21 teams Closed |
Leaderboard | |
Mini Hack : Strategic Thinking21-05-2016 to 21-05-2016 Cash Prize worth Rs 55k(~$810)1070 registered Closed |
Leaderboard | |
Practice Problem : Strategic Thinking15-03-2016 to 20-05-2016 Knowledge and Learning1280 registered Closed |
Leaderboard | |
Practice Problem : BigMart Sales Prediction - 214-03-2016 to 14-05-2016 Knowledge and Learning1240 registered Closed |
Leaderboard | |
Practice Problem : Loan Prediction - 214-03-2016 to 14-05-2016 Knowledge and Learning1463 registered Closed |
Leaderboard | |
AVdatafest : The Seer's Accuracy29-04-2016 to 01-05-2016 Cash Prize worth $18002217 registered 110 teams Closed |
Leaderboard | |
AVdatafest : Experiments With Data20-04-2016 to 01-05-2016 Knowledge and Learning2576 registered Closed |
Leaderboard | |
McKinsey Hiring Hack23-04-2016 to 24-04-2016 Job Opportunities with joining bonus upto INR 1 Lakh1436 registered Closed |
Leaderboard | |
AVdatafest : The Creative Analyst24-04-2016 to 24-04-2016 Prizes worth Rs 55k (~$810)1074 registered Closed |
Leaderboard | |
AVdatafest : The Strategist23-04-2016 to 23-04-2016 Cash Prize worth Rs 55k(~$810)1137 registered Closed |
Leaderboard | |
Practice Problem : Time Series15-02-2016 to 15-04-2016 Knowledge and learning1457 registered Closed |
Leaderboard | |
AV Learnup Gurgaon: Learn Data Science from Scratch10-04-2016 to 10-04-2016 Tablets and Pen Drives for beginners92 registered 4 teams Closed |
Leaderboard | |
Mini Hack : Data Visualization20-03-2016 to 20-03-2016 Amazon Vouchers worth Rs 18k1143 registered Closed |
Leaderboard | |
Re-Date Your Data: Learning Contest28-02-2016 to 13-03-2016 Amazon vouchers worth Rs 18k (~$265)2343 registered 4 teams Closed |
Leaderboard | |
Mini Hack : Strategic Thinking12-03-2016 to 12-03-2016 Amazon Vouchers worth Rs 18k1292 registered Closed |
Leaderboard | |
Practice Problem : BigMart Sales Prediction!11-01-2016 to 09-03-2016 Knowledge and Learning1233 registered Closed |
Leaderboard | |
Practice Problem : Loan Prediction09-11-2015 to 07-03-2016 Knowledge and Learning2493 registered Closed |
Leaderboard | |
Mini Hack : Excel05-03-2016 to 05-03-2016 Amazon Vouchers worth Rs 18k1334 registered Closed |
Leaderboard | |
Date Your Data26-02-2016 to 28-02-2016 Amazon vouchers worth Rs 55k (~$810)2150 registered 89 teams Closed |
Leaderboard | |
AV Learnup : Delhi21-02-2016 to 21-02-2016 Tablet, pendrives and knowledge75 registered 35 teams Closed |
Leaderboard | |
Blogathon15-01-2016 to 15-02-2016 Prizes worth Rs 10k252 registered Closed |
Leaderboard | |
Mini DataHack06-02-2016 to 06-02-2016 Amazon Vouchers worth Rs 18k893 registered Closed |
Leaderboard | |
Last Man Standing29-01-2016 to 31-01-2016 Amazon voucher worth Rs. 30,000(~$450)1640 registered 60 teams Closed |
Leaderboard | |
AV Learnup Chennai24-01-2016 to 24-01-2016 Knowledge and Passion113 registered 1 team Closed |
Leaderboard | |
LNMIIT DataHack22-01-2016 to 22-01-2016 Amazon Vouchers worth Rs 10k119 registered Closed |
Leaderboard | |
Praxis Data Hackathon16-01-2016 to 16-01-2016 Gift Vouchers30 registered Closed |
Leaderboard | |
Practice Problem 127-10-2015 to 28-12-2015 Knowledge and Learning928 registered Closed |
Leaderboard | |
LearnUp Delhi : Learn Data Science from Scratch01-11-2015 to 26-12-2015 Knowledge and Passion321 registered Closed |
Leaderboard | |
AV LearnUp Delhi20-12-2015 to 20-12-2015 Tablet, pendrives and knowledge54 registered Closed |
Leaderboard | |
AV LearnUp Bangalore13-12-2015 to 13-12-2015 Knowledge and Passion67 registered Closed |
Leaderboard | |
AV LearnUp Mumbai13-12-2015 to 13-12-2015 Knowledge and Passion41 registered Closed |
Leaderboard | |
Black Friday Data Hack20-11-2015 to 22-11-2015 Amazon vouchers worth ~$ 3001191 registered Closed |
Leaderboard | |
H2O world09-11-2015 to 10-11-2015 Apple IPad286 registered Closed |
Leaderboard | |
IIM Udaipur Analytics Workshop08-11-2015 to 08-11-2015 Knowledge and Learning39 registered Closed |
Leaderboard | |
The D Hack24-10-2015 to 25-10-2015 Amazon vouchers worth ~$ 300920 registered Closed |
Leaderboard | |
LearnUp - Learn Data Science From Scratch20-09-2015 to 12-10-2015 Knowledge and Passion173 registered Closed |
Leaderboard | |
Hansa Cequity Hiring Hack19-09-2015 to 19-09-2015 Job Opportunities81 registered Closed |
Leaderboard | |
Data Hackathon 3.x05-09-2015 to 06-09-2015 Amazon Voucher worth Rs. 10,000223 registered Closed |
Leaderboard |