| 0 = IRQ13 source is not from UART1 interrupt (UART1_INT). | ||
| 1 = IRQ13 source is from UART1 interrupt (UART1_INT). |
Definition at line 5129 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ14_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SPI_INT | IRQ14 Source Identity |
| 0 = IRQ14 source is not from SPI interrupt (SPI_INT). | ||
| 1 = IRQ14 source is from SPI interrupt (SPI_INT). |
Definition at line 5142 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ16_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GP5_INT | IRQ16 Source Identity |
| 0 = IRQ16 source is not from GP5 interrupt (GP5_INT). | ||
| 1 = IRQ16 source is from GP5 interrupt (GP5_INT). |
Definition at line 5159 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ17_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HIRC_TRIM_INT | IRQ17 Source Identity |
| 0 = IRQ17 source is not from HIRC trim interrupt (HIRC_TRIM_INT). | ||
| 1 = IRQ17 source is from HIRC trim interrupt (HIRC_TRIM_INT). |
Definition at line 5172 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ18_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | I2C0_INT | IRQ18 Source Identity |
| 0 = IRQ18 source is not from I2C0 interrupt (I2C0_INT). | ||
| 1 = IRQ18 source is from I2C0 interrupt (I2C0_INT). |
Definition at line 5185 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ19_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | I2C1_INT | IRQ19 Source Identity |
| 0 = IRQ19 source is not from I2C1 interrupt (I2C1_INT). | ||
| 1 = IRQ19 source is from I2C1 interrupt (I2C1_INT). |
Definition at line 5198 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ1_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WDT_INT | IRQ1 Source Identity |
| 0 = IRQ1 source is not from watchdog interrupt (WDT _INT). | ||
| 1 = IRQ1 source is from watchdog interrupt (WDT_INT). | ||
| [1] | WWDT_INT | IRQ1 Source Identity |
| 0 = IRQ1 source is not from window watchdog interrupt (WWDT _INT). | ||
| 1 = IRQ1 source is from window watchdog interrupt (WWDT_INT). |
Definition at line 4986 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ25_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ACMP_INT | IRQ25 Source Identity |
| 0 = IRQ25 source is not from ACMP interrupt (ACMP_INT). | ||
| 1 = IRQ25 source is from ACMP interrupt (ACMP_INT). |
Definition at line 5215 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ28_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PWRWU_INT | IRQ28 Source Identity |
| 0 = IRQ28 source is not from PWRWU interrupt (PWRWU_INT). | ||
| 1 = IRQ28 source is from PWREU interrupt (PWRWU_INT). |
Definition at line 5232 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ29_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADC_INT | IRQ29 Source Identity |
| 0 = IRQ29 source is not from ADC interrupt (ADC_INT). | ||
| 1 = IRQ29 source is from ADC interrupt (ADC_INT). |
Definition at line 5245 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ2_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | EINT0 | IRQ2 Source Identity |
| 0 = IRQ2 source is not from external signal interrupt 0 from P3.2 (EINT0). | ||
| 1 = IRQ2 source is from external signal interrupt 0 from P3.2 (EINT0). |
Definition at line 4999 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ3_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | EINT1 | IRQ3 Source Identity |
| 0 = IRQ3 source is not from external signal interrupt 1 from P5.2 (EINT1). | ||
| 1 = IRQ3 source is from external signal interrupt 1 from P5.2 (EINT1). |
Definition at line 5012 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ4_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GP0_INT | IRQ4 Source Identity |
| 0 = IRQ4 source is not from GP0 interrupt (GP0_INT). | ||
| 1 = IRQ4 source is from GP0 interrupt (GP0_INT). | ||
| [1] | GP1_INT | IRQ4 Source Identity |
| 0 = IRQ4 source is not from GP1 interrupt (GP1_INT). | ||
| 1 = IRQ4 source is from GP1 interrupt (GP1_INT). |
Definition at line 5028 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ5_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GP2_INT | IRQ5 Source Identity |
| 0 = IRQ5 source is not from GP2 interrupt (GP2_INT). | ||
| 1 = IRQ5 source is from GP2 interrupt (GP2_INT). | ||
| [1] | GP3_INT | IRQ5 Source Identity |
| 0 = IRQ5 source is not from GP3 interrupt (GP3_INT). | ||
| 1 = IRQ5 source is from GP3 interrupt (GP3_INT). | ||
| [2] | GP4_INT | IRQ5 Source Identity |
| 0 = IRQ5 source is not from GP4 interrupt (GP4_INT). | ||
| 1 = IRQ5 source is from GP4 interrupt (GP4_INT). |
Definition at line 5047 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ6_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PWM_INT | IRQ6 Source Identity |
| 0 = IRQ6 source is not from PWM interrupt (PWM_INT). | ||
| 1 = IRQ6 source is from PWM interrupt (PWM_INT). |
Definition at line 5060 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ7_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BRAKE_INT | IRQ7 Source Identity |
| 0 = IRQ7 source is not from Brake interrupt (BRAKE_INT). | ||
| 1 = IRQ7 source is from Brake interrupt (BRAKE_INT). |
Definition at line 5073 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ8_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TMR0_INT | IRQ8 Source Identity |
| 0 = IRQ8 source is not from Timer0 interrupt (TMR0_INT). | ||
| 1 = IRQ8 source is from Timer0 interrupt (TMR0_INT). |
Definition at line 5086 of file Mini58Series.h.
| __I uint32_t INTR_T::IRQ9_SRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TMR1_INT | IRQ9 Source Identity |
| 0 = IRQ9 source is not from Timer1 interrupt (TMR1_INT). | ||
| 1 = IRQ9 source is from Timer1 interrupt (TMR1_INT). |
Definition at line 5099 of file Mini58Series.h.
| __IO uint32_t FMC_T::ISPADDR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | ISPADDR | ISP Address |
| The Mini58 series is equipped with embedded flash. | ||
| ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. | ||
| and ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command. | ||
| For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation. |
Definition at line 1409 of file Mini58Series.h.
| __IO uint32_t FMC_T::ISPCMD |
| Bits | Field | Descriptions |
|---|---|---|
| [6:0] | CMD | ISP CMD |
| ISP command table is shown below: | ||
| 0x00= FLASH Read. | ||
| 0x04= Read Unique ID. | ||
| 0x0B= Read Company ID. | ||
| 0x0C= Read Device ID. | ||
| 0x0D= Read CRC32 Checksum. | ||
| 0x21= FLASH 32-bit Program. | ||
| 0x22= FLASH Page Erase. | ||
| 0x2D= Run CRC32 Checksum Calculation. | ||
| 0x2E= Vector Remap. | ||
| The other commands are invalid. |
Definition at line 1447 of file Mini58Series.h.
| __IO uint32_t FMC_T::ISPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPEN | ISP Enable Bit (Write Protect) |
| Set this bit to enable the ISP function. | ||
| 0 = ISP function Disabled. | ||
| 1 = ISP function Enabled. | ||
| [1] | BS | Boot Select (Write Protect) |
| Set/clear this bit to select next booting from LDROM/APROM, respectively. | ||
| This bit also functions as chip booting status flag, which can be used to check where chip booted from. | ||
| This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened. | ||
| 0 = Booting from APROM. | ||
| 1 = Booting from LDROM. | ||
| [2] | SPUEN | SPROM Update Enable Bit (Write Protect) |
| 0 = SPROM cannot be updated. | ||
| 1 = SPROM can be updated. | ||
| [3] | APUEN | APROM Update Enable Bit (Write Protect) |
| 0 = APROM cannot be updated when the chip runs in APROM. | ||
| 1 = APROM can be updated when the chip runs in APROM. | ||
| [4] | CFGUEN | CONFIG Update Enable Bit (Write Protect) |
| 0 = CONFIG cannot be updated. | ||
| 1 = CONFIG can be updated. | ||
| [5] | LDUEN | LDROM Update Enable (Write Protect) |
| LDROM update enable bit. | ||
| 0 = LDROM cannot be updated. | ||
| 1 = LDROM can be updated. | ||
| [6] | ISPFF | ISP Fail Flag (Write Protect) |
| This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
| This bit needs to be cleared by writing 1 to it. | ||
| (1) APROM writes to itself if APUEN is set to 0. | ||
| (2) LDROM writes to itself if LDUEN is set to 0. | ||
| (3) CONFIG is erased/programmed if CFGUEN is set to 0. | ||
| (4) SPROM is erased/programmed if SPUEN is set to 0. | ||
| (5) SPROM is programmed at SPROM secured mode. | ||
| (6) Page Erase command at LOCK mode with ICE connection. | ||
| (7) Erase or Program command at brown-out detected. | ||
| (8) Destination address is illegal, such as over an available range. | ||
| (9) Invalid ISP commands. |
Definition at line 1394 of file Mini58Series.h.
| __IO uint32_t FMC_T::ISPDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | ISPDAT | ISP Data |
| Write data to this register before ISP program operation. | ||
| Read data from this register after ISP read operation. | ||
| For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment. | ||
| For ISP Read Checksum command, ISPDAT is the checksum result. | ||
| If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect. |
Definition at line 1425 of file Mini58Series.h.
| __I uint32_t FMC_T::ISPSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPBUSY | ISP BUSY (Read Only) |
| 0 = ISP operation is finished. | ||
| 1 = ISP operation is busy. | ||
| [2:1] | CBS | Boot Selection Of CONFIG (Read Only) |
| This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened. | ||
| 00 = LDROM with IAP mode. | ||
| 01 = LDROM without IAP mode. | ||
| 10 = APROM with IAP mode. | ||
| 11 = APROM without IAP mode. | ||
| [6] | ISPFF | ISP Fail Flag (Write Protect) |
| This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. | ||
| This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
| (1) APROM writes to itself if APUEN is set to 0. | ||
| (2) LDROM writes to itself if LDUEN is set to 0. | ||
| (3) CONFIG is erased/programmed if CFGUEN is set to 0. | ||
| (4) SPROM is erased/programmed if SPUEN is set to 0. | ||
| (5) SPROM is programmed at SPROM secured mode. | ||
| (6) Page Erase command at LOCK mode with ICE connection. | ||
| (7) Erase or Program command at brown-out detected. | ||
| (8) Destination address is illegal, such as over an available range. | ||
| (9) Invalid ISP commands. | ||
| [20:9] | VECMAP | Vector Page Mapping Address (Read Only) |
| All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF} | ||
| [31] | SCODE | Security Code Active Flag |
| This bit is set to 1 by hardware when detecting SPROM secured code is active at flash initialization, or software writes 1 to this bit to make secured code active; this bit is only cleared by SPROM page erase operation. | ||
| 0 = SPROM secured code is inactive. | ||
| 1 = SPROM secured code is active. |
Definition at line 1530 of file Mini58Series.h.
| __IO uint32_t FMC_T::ISPTRG |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPGO | ISP Start Trigger (Write Protect) |
| Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. | ||
| 0 = ISP operation is finished. | ||
| 1 = ISP is progressed. |
Definition at line 1461 of file Mini58Series.h.
| __IO uint32_t UART_T::LINE |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | WLS | Word Length Select Bit |
| 00 = Word length is 5-bit. | ||
| 01 = Word length is 6-bit. | ||
| 10 = Word length is 7-bit. | ||
| 11 = Word length is 8-bit. | ||
| [2] | NSB | Number of "STOP Bit" |
| 0 = One "STOP bit" is generated in the transmitted data. | ||
| 1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. | ||
| When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data. | ||
| [3] | PBE | Parity Bit Enable Bit |
| 0 = No parity bit. | ||
| 1 = Parity bit is generated on each outgoing character and is checked on each incoming data. | ||
| [4] | EPE | Even Parity Enable Bit |
| 0 = Odd number of logic 1's is transmitted and checked in each word. | ||
| 1 = Even number of logic 1's is transmitted and checked in each word. | ||
| This bit has effect only when PBE (UART_LINE[3]) is set. | ||
| [5] | SPE | Stick Parity Enable Bit |
| 0 = Stick parity Disabled. | ||
| 1 = If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. | ||
| If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as . | ||
| [6] | BCB | Break Control Bit |
| When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). | ||
| This bit acts only on TX and has no effect on the transmitter logic. | ||
| 0 = Break control Disabled. | ||
| 1 = Break control Enabled. |
Definition at line 10837 of file Mini58Series.h.
| __IO uint32_t GPIO_T::MODE |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | MODE0 | Port 0-5 I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: The initial value of this field is defined by CIOINI (Config0[10]). | ||
| If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on. | ||
| If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be | ||
| input mode after chip powered on. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [3:2] | MODE1 | Port 0-5 I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: The initial value of this field is defined by CIOINI (Config0[10]). | ||
| If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on. | ||
| If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be | ||
| input mode after chip powered on. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [5:4] | MODE2 | Port 0-5 I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: The initial value of this field is defined by CIOINI (Config0[10]). | ||
| If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on. | ||
| If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be | ||
| input mode after chip powered on. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [7:6] | MODE3 | Port 0-5 I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: The initial value of this field is defined by CIOINI (Config0[10]). | ||
| If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on. | ||
| If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be | ||
| input mode after chip powered on. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [9:8] | MODE4 | Port 0-5 I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: The initial value of this field is defined by CIOINI (Config0[10]). | ||
| If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on. | ||
| If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be | ||
| input mode after chip powered on. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [11:10] | MODE5 | Port 0-5 I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: The initial value of this field is defined by CIOINI (Config0[10]). | ||
| If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on. | ||
| If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be | ||
| input mode after chip powered on. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [13:12] | MODE6 | Port 0-5 I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: The initial value of this field is defined by CIOINI (Config0[10]). | ||
| If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on. | ||
| If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be | ||
| input mode after chip powered on. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [15:14] | MODE7 | Port 0-5 I/O Pin[N] Mode Control |
| Determine each I/O mode of Px.n pins. | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: The initial value of this field is defined by CIOINI (Config0[10]). | ||
| If CIOINI is set to 0, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on. | ||
| If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be | ||
| input mode after chip powered on. | ||
| Note2: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. |
Definition at line 1751 of file Mini58Series.h.
| __IO uint32_t UART_T::MODEM |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | RTS | RTS (Request-to-send) Signal Control |
| This bit is direct control internal RTS signal active or not, and then drive the RTS pin output with RTSACTLV bit configuration. | ||
| 0 = RTS signal is active. | ||
| 1 = RTS signal is inactive. | ||
| Note1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode. | ||
| Note2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. | ||
| [9] | RTSACTLV | RTS Pin Active Level |
| This bit defines the active level state of RTS pin output. | ||
| 0 = RTS pin output is high level active. | ||
| 1 = RTS pin output is low level active. (Default) | ||
| Note1: Refer to Figure 6.10-13 and Figure 6.10-14 UART function mode. | ||
| Note2: Refer to Figure 6.10-17 and Figure 6.10-18 for RS-485 function mode. | ||
| [13] | RTSSTS | RTS Pin State (Read Only) |
| This bit mirror from RTS pin output of voltage logic status. | ||
| 0 = RTS pin output is low level voltage logic state. | ||
| 1 = RTS pin output is high level voltage logic state. |
Definition at line 10863 of file Mini58Series.h.
| __IO uint32_t UART_T::MODEMSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CTSDETF | Detect CTS State Change Flag |
| This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. | ||
| 0 = CTS input has not change state. | ||
| 1 = CTS input has change state. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [4] | CTSSTS | CTS Pin Status (Read Only) |
| This bit mirror from CTS pin input of voltage logic status. | ||
| 0 = CTS pin input is low level voltage logic state. | ||
| 1 = CTS pin input is high level voltage logic state. | ||
| Note: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected. | ||
| [8] | CTSACTLV | CTS Pin Active Level |
| This bit defines the active level state of CTS pin input. | ||
| 0 = CTS pin input is high level active. | ||
| 1 = CTS pin input is low level active. (Default) |
Definition at line 10887 of file Mini58Series.h.
| __IO uint32_t PWM_T::MSKALIGN |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | MSKDAT0 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT1 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT2 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT3 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT4 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT5 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [13:8] | MSKEN0 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN1 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN2 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN3 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN4 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN5 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [21:16] | ALIGNn | PWM0_CHn Output Mask Aligned Enable Bit |
| 0 = PWM0_CHn output will mask immediately when mask function enabled. | ||
| 1 = PWM0_CHn output will mask when output aligned to PWM period. |
Definition at line 7890 of file Mini58Series.h.
| __IO uint32_t SYS_T::P0_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P0 Multiple Function Select Bit |
| The pin function of P0 depends on MFP and ALT. | ||
| Refer to ALT Description for details. | ||
| [8] | ALT0 | P0.0 Alternate Function Select Bit |
| Bits ALT[0] (SYS_P0_MFP[8]), and MFP[0] (SYS_P0_MFP[0]) determine the P0.0 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = Reserved. | ||
| (1, 0) = UART0_nCTS function is selected. | ||
| (1, 1) = UART0_TXD function is selected. | ||
| [9] | ALT1 | P0.1 Alternate Function Select Bit |
| Bits ALT[1] (SYS_P0_MFP[9]), and MFP[1] (SYS_P0_MFP[1]) determine the P0.1 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = SPI0_SS function is selected. | ||
| (1, 0) = UART0_nRTS function is selected. | ||
| (1, 1) = UART0_RXD function is selected. | ||
| [12] | ALT4 | P0.4 Alternate Function Select Bit |
| Bits ALT[4] (SYS_P0_MFP[12]), and MFP[4] (SYS_P0_MFP[4]) determine the P0.4 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = Reserved. | ||
| (1, 0) = SPI0_SS function is selected. | ||
| (1, 1) = PWM0_CH5 function is selected. | ||
| [13] | ALT5 | P0.5 Alternate Function Select Bit |
| Bits ALT[5] (SYS_P0_MFP[13]), and MFP[5] (SYS_P0_MFP[5]) determine the P0.5 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = Reserved. | ||
| (1, 0) = SPI0_MOSI function is selected. | ||
| (1, 1) = PWM0_CH4 function is selected. | ||
| [14] | ALT6 | P0.6 Alternate Function Select Bit |
| Bits ALT[6] (SYS_P0_MFP[14]), and MFP[6] (SYS_P0_MFP[6]) determine the P0.6 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = Reserved. | ||
| (1, 0) = SPI0_MISO function is selected. | ||
| (1, 1) = PWM0_CH1 function is selected. | ||
| [15] | ALT7 | P0.7 Alternate Function Select Bit |
| Bits ALT[7] (SYS_P0_MFP[15]), and MFP[7] (SYS_P0_MFP[7]) determine the P0.7 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = Reserved. | ||
| (1, 0) = SPI0_CLK function is selected. | ||
| (1, 1) = PWM0_CH0 function is selected. | ||
| [23:16] | TYPE | P0[7:0] Input Schmitt Trigger Function Enable Bits |
| 0 = P0[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P0[7:0] I/O input Schmitt Trigger function Enabled. |
Definition at line 9690 of file Mini58Series.h.
| __IO uint32_t SYS_T::P1_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P1 Multiple Function Select Bit |
| The pin function of P1 depends on MFP and ALT. | ||
| Refer to ALT Description for details. | ||
| [8] | ALT0 | P1.0 Alternate Function Select Bit |
| Bits ALT[0] (SYS_P1_MFP[8]), and MFP[0] (SYS_P1_MFP[0]) determine the P1.0 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = ADC_CH1 function is selected. | ||
| (1, 0) = Reserved. | ||
| (1, 1) = ACMP0_P1 function is selected. | ||
| [10] | ALT2 | P1.2 Alternate Function Select Bit |
| Bits P12EXT (SYS_P1_MFP[26]), ALT[2] (SYS_P1_MFP[10]), and MFP[2] (SYS_P1_MFP[2]) determine the P1.2 function. | ||
| (0, 0, 0) = GPIO function is selected. | ||
| (0, 0, 1) = ADC_CH2 function is selected. | ||
| (0, 1, 0) = UART0_RXD function is selected. | ||
| (0, 1, 1) = ACMP0_P2 function is selected. | ||
| (1, 0, 0) = PWM0_CH0 function is selected. | ||
| [11] | ALT3 | P1.3 Alternate Function Select Bit |
| Bits P13EXT (SYS_P1_MFP[27]), ALT[3] (SYS_P1_MFP[11]), and MFP[3] (SYS_P1_MFP[3]) determine the P1.3 function. | ||
| (0, 0, 0) = GPIO function is selected. | ||
| (0, 0, 1) = ADC_CH3 function is selected. | ||
| (0, 1, 0) = UART0_TXD function is selected. | ||
| (0, 1, 1) = ACMP0_P3 function is selected. | ||
| (1, 0, 0) = PWM0_CH1 function is selected. | ||
| [12] | ALT4 | P1.4 Alternate Function Select Bit |
| Bits P14EXT (SYS_P1_MFP[28]), ALT[4] (SYS_P1_MFP[12]), and MFP[4] (SYS_P1_MFP[4]) determine the P1.4 function. | ||
| (0, 0, 0) = GPIO function is selected. | ||
| (0, 0, 1) = ADC_CH4 function is selected. | ||
| (0, 1, 0) = UART1_RXD function is selected. | ||
| (0, 1, 1) = ACMP0_N function is selected. | ||
| (1, 0, 0) = PWM0_CH4 function is selected. | ||
| [13] | ALT5 | P1.5 Alternate Function Select Bit |
| Bits ALT[5] (SYS_P1_MFP[13]), and MFP[5] (SYS_P1_MFP[5]) determine the P1.5 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = ADC_CH5 function is selected. | ||
| (1, 0) = UART1_TXD function is selected. | ||
| (1, 1) = ACMP0_P0 function is selected. | ||
| [23:16] | TYPE | P1[7:0] Input Schmitt Trigger Function Enable Bit |
| 0 = P1[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P1[7:0] I/O input Schmitt Trigger function Enabled. | ||
| [26] | P12EXT | P1.2 Alternate Function Selection Extension |
| Bits P12EXT (SYS_P1_MFP[26]), ALT[2] (SYS_P1_MFP[10]), and MFP[2] (SYS_P1_MFP[2]) determine the P1.2 function. | ||
| (0, 0, 0) = GPIO function is selected. | ||
| (0, 0, 1) = ADC_CH2 function is selected. | ||
| (0, 1, 0) = UART0_RXD function is selected. | ||
| (0, 1, 1) = ACMP0_P2 function is selected. | ||
| (1, 0, 0) = PWM0_CH0 function is selected. | ||
| [27] | P13EXT | P1.3 Alternate Function Selection Extension |
| Bits P13EXT (SYS_P1_MFP[27]), ALT[3] (SYS_P1_MFP[11]), and MFP[3] (SYS_P1_MFP[3]) determine the P1.3 function. | ||
| (0, 0, 0) = GPIO function is selected. | ||
| (0, 0, 1) = ADC_CH3 function is selected. | ||
| (0, 1, 0) = UART0_TXD function is selected. | ||
| (0, 1, 1) = ACMP0_P3 function is selected. | ||
| (1, 0, 0) = PWM0_CH1 function is selected. | ||
| [28] | P14EXT | P1.4 Alternate Function Selection Extension |
| Bits P14EXT (SYS_P1_MFP[28]), ALT[4] (SYS_P1_MFP[12]), and MFP[4] (SYS_P1_MFP[4]) determine the P1.4 function. | ||
| (0, 0, 0) = GPIO function is selected. | ||
| (0, 0, 1) = ADC_CH4 function is selected. | ||
| (0, 1, 0) = UART1_RXD function is selected. | ||
| (0, 1, 1) = ACMP0_N function is selected. | ||
| (1, 0, 0) = PWM0_CH4 function is selected. |
Definition at line 9760 of file Mini58Series.h.
| __IO uint32_t SYS_T::P2_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P2 Multiple Function Select Bit |
| The pin function of P2 depends on MFP and ALT. | ||
| Refer to ALT Description for details. | ||
| [10] | ALT2 | P2.2 Alternate Function Select Bit |
| Bits ALT[2] (SYS_P2_MFP[10]), and MFP[2] (SYS_P2_MFP[2]) determine the P2.2 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = Reserved. | ||
| (1, 0) = PWM0_CH0 function is selected. | ||
| (1, 1) = I2C1_SCL function is selected. | ||
| [11] | ALT3 | P2.3 Alternate Function Select Bit |
| Bits ALT[3] (SYS_P2_MFP[11]), and MFP[3] (SYS_P2_MFP[3]) determine the P2.3 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = Reserved. | ||
| (1, 0) = PWM0_CH1 function is selected. | ||
| (1, 1) = I2C1_SDA1 function is selected. | ||
| [12] | ALT4 | P2.4 Alternate Function Select Bit |
| Bits ALT[4] (SYS_P2_MFP[12]), and MFP[4] (SYS_P2_MFP[4]) determine the P2.4 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = UART1_RXD function is selected. | ||
| (1, 0) = PWM0_CH2 function is selected. | ||
| (1, 1) = Reserved. | ||
| [13] | ALT5 | P2.5 Alternate Function Select Bit |
| Bits ALT[5] (SYS_P2_MFP[13]), and MFP[5] (SYS_P2_MFP[5]) determine the P2.5 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = UART1_TXD function is selected. | ||
| (1, 0) = PWM0_CH3 function is selected. | ||
| (1, 1) = Reserved. | ||
| [14] | ALT6 | P2.6 Alternate Function Select Bit |
| Bits ALT[6] (SYS_P2_MFP[14]), and MFP[6] (SYS_P2_MFP[6]) determine the P2.6 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = Reserved. | ||
| (1, 0) = PWM0_CH4 function is selected. | ||
| (1, 1) = ACMP1_O0 function is selected. | ||
| [23:16] | TYPE | P2[7:0] Input Schmitt Trigger Function Enable Bits |
| 0 = P2[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P2[7:0] I/O input Schmitt Trigger function Enabled. |
Definition at line 9806 of file Mini58Series.h.
| __IO uint32_t SYS_T::P3_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P3 Multiple Function Select Bits |
| The pin function of P3 depends on MFP and ALT. | ||
| Refer to ALT Description for details. | ||
| [8] | ALT0 | P3.0 Alternate Function Select Bit |
| Bits ALT[0] (SYS_P3_MFP[8]), and MFP[0] (SYS_P3_MFP[0]) determine the P3.0 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = Reserved. | ||
| (1, 0) = ACMP1_N function is selected. | ||
| (1, 1) = ADC_CH6 function is selected. | ||
| [9] | ALT1 | P3.1 Alternate Function Select Bit |
| The pin function of P3.1 depends on P3_MFP[1] and P3_ALT[1]. | ||
| Bits ALT[1] (SYS_P3_MFP[9]), and MFP[1] (SYS_P3_MFP[1]) determine the P3.1 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = Reserved. | ||
| (1, 0) = ACMP1_P0 function is selected. | ||
| (1, 1) = ADC_CH7 function is selected. | ||
| [10] | ALT2 | P3.2 Alternate Function Select Bit |
| Bits P32EXT (SYS_P3_MFP[26]), ALT[2] (SYS_P3_MFP[10]), and MFP[2] (SYS_P3_MFP[2]) determine the P3.2 function. | ||
| (0, 0, 0) = GPIO function is selected. | ||
| (0, 0, 1) = INT1 function is selected. | ||
| (0, 1, 0) = TM0_EXT function is selected. | ||
| (0, 1, 1) = STADC function is selected. | ||
| (1, 0, 0) = ACMP1_P1 function is selected. | ||
| [12] | ALT4 | P3.4 Alternate Function Select Bit |
| Bits ALT[4] (SYS_P3_MFP[12]), and MFP[4] (SYS_P3_MFP[4]) determine the P3.4 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = TM0_CNT_OUT function is selected. | ||
| (1, 0) = I2C0_SDA function is selected. | ||
| (1, 1) = ACMP1_P2 function is selected. | ||
| [13] | ALT5 | P3.5 Alternate Function Select Bit |
| Bits ALT[5] (SYS_P3_MFP[13]), and MFP[5] (SYS_P3_MFP[5]) determine the P3.5 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = TM1_CNT_OUTfunction is selected. | ||
| (1, 0) = I2C0_SCL function is selected. | ||
| (1, 1) = ACMP1_P3 function is selected. | ||
| [14] | ALT6 | P3.6 Alternate Function Select Bit |
| Bits ALT[6] (SYS_P3_MFP[14]), and MFP[6] (SYS_P3_MFP[6]) determine the P3.6 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = TM1_EXT function is selected. | ||
| (1, 0) = CLKO function is selected. | ||
| (1, 1) = ACMP0_O function is selected. | ||
| [23:16] | TYPE | P3[7:0] Input Schmitt Trigger Function Enable Bits |
| 0 = P3[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P3[7:0] I/O input Schmitt Trigger function Enabled. | ||
| [26] | P32EXT | P3.2 Alternate Function Selection Extension |
| Bits P32EXT (SYS_P3_MFP[26]), ALT[2] (SYS_P3_MFP[10]), and MFP[2] (SYS_P3_MFP[2]) determine the P3.2 function. | ||
| (0, 0, 0) = GPIO function is selected. | ||
| (0, 0, 1) = INT1 function is selected. | ||
| (0, 1, 0) = TM0_EXT function is selected. | ||
| (0, 1, 1) = STADC function is selected. | ||
| (1, 0, 0) = ACMP1_P1 function is selected. |
Definition at line 9867 of file Mini58Series.h.
| __IO uint32_t SYS_T::P4_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P4 Multiple Function Select Bits |
| The pin function of P4 depends on MFP and ALT. | ||
| Refer to ALT Description for details. | ||
| [14] | ALT6 | P4.6 Alternate Function Select Bit |
| Bits ALT[6] (SYS_P4_MFP[6]), and MFP[6] (SYS_P4_MFP[6]) determine the P4.6 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = ICE_CLK function is selected. | ||
| (1, 0) = UART1_RXD function is selected. | ||
| (1, 1) = Reserved. | ||
| [15] | ALT7 | P4.7 Alternate Function Select Bit |
| Bits ALT[7] (SYS_P4_MFP[15]), and MFP[7] (SYS_P4_MFP[7]) determine the P4.7 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = ICE_DAT function is selected. | ||
| (1, 0) = UART1_TXD function is selected. | ||
| (1, 1) = Reserved. | ||
| [23:16] | TYPE | P4[7:0] Input Schmitt Trigger Function Enable Bits |
| 0 = P4[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P4[7:0] I/O input Schmitt Trigger function Enabled. |
Definition at line 9895 of file Mini58Series.h.
| __IO uint32_t SYS_T::P5_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | MFP | P5 Multiple Function Select Bits |
| The pin function of P5 depends on MFP and ALT. | ||
| Refer to ALT Description for details. | ||
| [8] | ALT0 | P5.0 Alternate Function Select Bit |
| The pin function of P5.0 depends on MFP[0] and ALT[0]. | ||
| Bits ALT[0] (SYS_P5_MFP[8]), and MFP[0] (SYS_P5_MFP[0]) determine the P5.0 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = XT1_IN function is selected. | ||
| (1, 0) = I2C1_SDA1 function is selected. | ||
| (1, 1) = UART0_TXD function is selected. | ||
| Note: To enable external XTAL function, the CLK_PWRCTL bit [1:0] (XTLEN), external HXT or LXT crystal oscillator control register must also be set. | ||
| [9] | ALT1 | P5.1 Alternate Function Select Bit |
| Bits ALT[1] (SYS_P5_MFP[9]), and MFP[1] (SYS_P5_MFP[1]) determine the P5.1 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = XT1_OUT function is selected. | ||
| (1, 0) = I2C1_SCL1 function is selected. | ||
| (1, 1) = UART0_RXD function is selected. | ||
| Note: To enable external XTAL function, the CLK_PWRCTL bit [1:0] (XTLEN), external HXT or LXT crystal oscillator control register must also be set. | ||
| [10] | ALT2 | P5.2 Alternate Function Select Bit |
| Bits ALT[2] (SYS_P5_MFP[10]), and MFP[2] (SYS_P5_MFP[2]) determine the P5.2 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = INT1 function is selected. | ||
| Others = Reserved. | ||
| [11] | ALT3 | P5.3 Alternate Function Select Bit |
| Bits ALT[3] (SYS_P5_MFP[11]), and MFP[3] (SYS_P5_MFP[3]) determine the P5.3 function. | ||
| (0, 0) = GPIO function is selected. | ||
| (0, 1) = ADC_CH0 function is selected. | ||
| Others = Reserved. | ||
| [12] | ALT4 | P5.4 Alternate Function Select Bit |
| Bits ALT[4] (SYS_P5_MFP[12]), and MFP[4] (SYS_P5_MFP[4]) determine the P5.4 function. | ||
| (0, 0) = GPIO function is selected. | ||
| Others = Reserved. | ||
| [13] | ALT5 | P5.5 Alternate Function Select Bit |
| Bits ALT[5] (SYS_P5_MFP[13]), and MFP[5] (SYS_P5_MFP[5]) determine the P5.5 function. | ||
| (0, 0) = GPIO function is selected. | ||
| Others = Reserved. | ||
| [23:16] | TYPE | P5[7:0] Input Schmitt Trigger Function Enable Bits |
| 0 = P5[7:0] I/O input Schmitt Trigger function Disabled. | ||
| 1 = P5[7:0] I/O input Schmitt Trigger function Enabled. |
Definition at line 9944 of file Mini58Series.h.
| __IO uint32_t PWM_T::PCACTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PCAEN | PWM Precise Center-aligned Type Enable Bit |
| 0 = Precise center-aligned type Disabled. | ||
| 1 = Precise center-aligned type Enabled. |
Definition at line 7835 of file Mini58Series.h.
| __I uint32_t SYS_T::PDID |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | PDID | Product Device Identification Number (Read Only) |
| This register reflects the device part number code. | ||
| Software can read this register to identify which device is use. | ||
| For example, the MINI58LDE PDID code is "0x00A05800". |
Definition at line 9480 of file Mini58Series.h.
| __IO uint32_t PWM_T::PERIOD0 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PERIOD0 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD1 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD2 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD3 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD4 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD5 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. |
Definition at line 5673 of file Mini58Series.h.
| __IO uint32_t PWM_T::PERIOD1 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PERIOD0 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD1 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD2 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD3 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD4 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD5 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. |
Definition at line 5779 of file Mini58Series.h.
| __IO uint32_t PWM_T::PERIOD2 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PERIOD0 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD1 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD2 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD3 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD4 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD5 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. |
Definition at line 5885 of file Mini58Series.h.
| __IO uint32_t PWM_T::PERIOD3 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PERIOD0 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD1 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD2 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD3 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD4 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD5 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. |
Definition at line 5991 of file Mini58Series.h.
| __IO uint32_t PWM_T::PERIOD4 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PERIOD0 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD1 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD2 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD3 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD4 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD5 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. |
Definition at line 6097 of file Mini58Series.h.
| __IO uint32_t PWM_T::PERIOD5 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PERIOD0 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD1 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD2 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD3 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD4 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. | ||
| [15:0] | PERIOD5 | PWM Counter Period Value |
| PERIODn determines the PWM counter period. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/( PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((prescale+1)*(clock divider))/ (2*PERIODn+1); where xy, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/( PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to PERIODn will take effect in the next PWM cycle. |
Definition at line 6203 of file Mini58Series.h.
| __IO uint32_t PWM_T::PHCHG |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | MSKDAT0 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT1 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT2 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT3 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT4 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT5 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [6] | MSKDAT6 | PWM0_CH6 (GPIO P0.1) Mask Data |
| When MASKEND6 Is 1, channel 6's output level is MSKDAT6. | ||
| 0 = PWM0_CH6 output low level. | ||
| 1 = PWM0_CH6 output high level. | ||
| [7] | MSKDAT7 | PWM0_CH7 (GPIO P0.0) Mask Data |
| When MASKEND7 Is 1, channel 7's output level is MSKDAT7. | ||
| 0 = PWM0_CH7 output low level. | ||
| 1 = PWM0_CH7 output high level. | ||
| [13:8] | MSKEN0 | PWMn Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN1 | PWMn Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN2 | PWMn Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN3 | PWMn Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN4 | PWMn Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN5 | PWMn Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [14] | AUTOCLR0 | Hardware Auto Clear ACMP0TEN |
| 0 = Hardware will auto clear ACMP0TEN when ACMP0 trigger PWM. | ||
| 1 = Hardware will not auto clear ACMP0TEN when ACMP0 trigger PWM. | ||
| [15] | AUTOCLR1 | Hardware Auto Clear ACMP1TEN |
| 0 = Hardware will auto clear ACMP1TEN when ACMP1 trigger PWM. | ||
| 1 = Hardware will not auto clear ACMP1TEN when ACMP1 trigger PWM. | ||
| [16] | AOFFEN01 | ACMP1 Trigger Channel 0 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH0 one period cycle output low Disabled. | ||
| 1 = PWM0_CH0 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [17] | AOFFEN11 | ACMP1 Trigger Channel 1 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH1 one period cycle output low Disabled. | ||
| 1 = PWM0_CH1 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [18] | AOFFEN21 | ACMP1 Trigger Channel 2 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH2 one period cycle output low Disabled. | ||
| 1 = PWM0_CH2 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH 3. | ||
| [19] | AOFFEN31 | ACMP1 Trigger Channel 3 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH3 one period cycle output low Disabled. | ||
| 1 = PWM0_CH3 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [21:20] | A1POSSEL | ACMP1 Positive Input Source Select Bits |
| 00 = Select P3.1 as the input of ACMP1. | ||
| 01 = Select P3.2 as the input of ACMP1. | ||
| 10 = Select P3.3 as the input of ACMP1. | ||
| 11 = Select P3.4 as the input of ACMP1. | ||
| [22] | TMR1TEN | TIMER1 Trigger PWM Function Enable Bit |
| When this bit is set, TIMER1 time-out event will update PWM_PHCHG with PHCHG_NXT register. | ||
| 0 = TIMER1 trigger PWM function Disabled. | ||
| 1 = TIMER1 trigger PWM function Enabled. | ||
| [23] | ACMP1TEN | ACMP1 Trigger Function Enable Bit |
| 0 = ACMP1 trigger PWM function Disabled. | ||
| 1 = ACMP1 trigger PWM function Enabled. | ||
| Note: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set. | ||
| [24] | AOFFEN00 | ACMP0 Trigger Channel 0 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH0 one period cycle output low Disabled. | ||
| 1 = PWM0_CH0 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [25] | AOFFEN10 | ACMP0 Trigger Channel 1 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH1 one period cycle output low Disabled. | ||
| 1 = PWM0_CH1 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [26] | AOFFEN20 | ACMP0 Trigger Channel 2 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH2 one period cycle output low Disabled. | ||
| 1 = PWM0_CH2 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [27] | AOFFEN30 | ACMP0 Trigger Channel 3 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH3 one period cycle output low Disabled. | ||
| 1 = PWM0_CH3 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~ PWM0_CH3. | ||
| [29:28] | A0POSSEL | ACMP0 Positive Input Source Select Bits |
| 00 = Select P1.5 as the input of ACMP0. | ||
| 01 = Select P1.0 as the input of ACMP0. | ||
| 10 = Select P1.2 as the input of ACMP0. | ||
| 11 = Select P1.3 as the input of ACMP0. | ||
| [30] | TMR0TEN | TIMER0 Trigger PWM Function Enable Bit |
| When this bit is set, TIMER0 time-out event will update PWM_PHCHG with PHCHG_NXT register. | ||
| 0 = TIMER0 trigger PWM function Disabled. | ||
| 1 = TIMER0 trigger PWM function Enabled. | ||
| [31] | ACMP0TEN | ACMP0 Trigger PWM Function Enable Bit |
| 0 = ACMP0 trigger PWM function Disabled. | ||
| 1 = ACMP0 trigger PWM function Enabled. | ||
| Note: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set. |
Definition at line 7651 of file Mini58Series.h.
| __IO uint32_t PWM_T::PHCHGMSK |
| Bits | Field | Descriptions |
|---|---|---|
| [6] | MASKEND6 | PWM0_CH6 (GPIO P0.1) Output Mask Enable Bit |
| 0 = Output the original GPIO P0.1. | ||
| 1 = Output MSKDAT6 specified in bit 6 of PWM_PHCHG register. | ||
| [7] | MASKEND7 | PWM0_CH7 (GPIO P0.0) Output Mask Enable Bit |
| 0 = Output the original GPIO P0.0. | ||
| 1 = Output MSKDAT7 specified in bit 7 of PWM_PHCHG register. | ||
| [8] | POSCTL0 | Positive Input Control For ACMP0 |
| 0 = The input of ACMP is controlled by CMP0CR. | ||
| 1 = The input of ACMP is controlled by CMP0SEL of PWM_PHCHG register. | ||
| Note: Register CMP0CR is described in Comparator Controller chapter. | ||
| [9] | POSCTL1 | Positive Input Control For ACMP1 |
| 0 = The input of ACMP is controlled by CMP1CR. | ||
| 1 = The input of ACMP is controlled by CMP1SEL of PWM_PHCHG register. | ||
| Note: Register CMP1CR is described in Comparator Controller chapter. |
Definition at line 7807 of file Mini58Series.h.
| __IO uint32_t PWM_T::PHCHGNXT |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | MSKDAT0 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT1 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT2 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT3 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT4 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [5:0] | MSKDAT5 | PWM0_CHn Mask Data |
| When MSKENn is 0, channel n's output level is MSKDATn. | ||
| 0 = PWM0_CHn output low level. | ||
| 1 = PWM0_CHn output high level. | ||
| [6] | MSKDAT6 | PWM0_CH6 (GPIO P0.1) Mask Data |
| When MASKEND6 Is 1, channel 6's output level is MSKDAT6. | ||
| 0 = PWM0_CH6 output low level. | ||
| 1 = PWM0_CH6 output high level. | ||
| [7] | MSKDAT7 | PWM0_CH7 (GPIO P0.0) Mask Data |
| When MASKEND7 Is 1, channel 7's output level is MSKDAT7. | ||
| 0 = PWM0_CH7 output low level. | ||
| 1 = PWM0_CH7 output high level. | ||
| [13:8] | MSKEN0 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN1 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN2 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN3 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN4 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [13:8] | MSKEN5 | PWM Output Mask Enable Bits |
| 0 = Output MSKDATn specified in bit n of PWM_PHCHG register. | ||
| 1 = Output the original channel n waveform. | ||
| [14] | AUTOCLR0 | Hardware Auto Clear ACMP0TEN |
| 0 = Hardware will auto clear ACMP0TEN when ACMP0 trigger PWM. | ||
| 1 = Hardware will not auto clear ACMP0TEN when ACMP0 trigger PWM. | ||
| [15] | AUTOCLR1 | Hardware Auto Clear ACMP1TEN |
| 0 = Hardware will auto clear ACMP1TEN when ACMP1 trigger PWM. | ||
| 1 = Hardware will not auto clear ACMP1TEN when ACMP1 trigger PWM. | ||
| [16] | AOFFEN01 | ACMP1 Trigger Channel 0 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH0 one period cycle output low Disabled. | ||
| 1 = PWM0_CH0 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [17] | AOFFEN11 | ACMP1 Trigger Channel 1 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH1 one period cycle output low Disabled. | ||
| 1 = PWM0_CH1 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [18] | AOFFEN21 | ACMP1 Trigger Channel 2 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH2 one period cycle output low Disabled. | ||
| 1 = PWM0_CH2 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [19] | AOFFEN31 | ACMP1 Trigger Channel 3 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH3 one period cycle output low Disabled. | ||
| 1 = PWM0_CH3 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [21:20] | A1POSSEL | ACMP1 Positive Input Source Select Bits |
| 00 = Select P3.1 as the input of ACMP1. | ||
| 01 = Select P3.2 as the input of ACMP1. | ||
| 10 = Select P3.3 as the input of ACMP1. | ||
| 11 = Select P3.4 as the input of ACMP1. | ||
| [22] | TMR1TEN | TMR1 Trigger PWM Function Enable Bit |
| When this bit is set, TMR1 time-out event will update PWM_PHCHG with PHCHG_NXT register. | ||
| 0 = TMR1 trigger PWM function Disabled. | ||
| 1 = TMR1 trigger PWM function Enabled. | ||
| [23] | ACMP1TEN | ACMP1 Trigger Function Enable Bit |
| 0 = ACMP1 trigger PWM function Disabled. | ||
| 1 = ACMP1 trigger PWM function Enabled. | ||
| Note: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set. | ||
| [24] | AOFFEN00 | ACMP0 Trigger Channel 0 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH0 one period cycle output low Disabled. | ||
| 1 = PWM0_CH0 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [25] | AOFFEN10 | ACMP0 Trigger Channel 1 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH1 one period cycle output low Disabled. | ||
| 1 = PWM0_CH1 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [26] | AOFFEN20 | ACMP0 Trigger Channel 2 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH2 one period cycle output low Disabled. | ||
| 1 = PWM0_CH2 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [27] | AOFFEN30 | ACMP0 Trigger Channel 3 One Cycle Output Off Enable Bit |
| Setting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application. | ||
| 0 = PWM0_CH3 one period cycle output low Disabled. | ||
| 1 = PWM0_CH3 one period cycle output low Enabled. | ||
| Note: This function is only available for PWM0_CH0~PWM0_CH3. | ||
| [29:28] | A0POSSEL | ACMP0 Positive Input Source Select Bits |
| 00 = Select P1.5 as the input of ACMP0. | ||
| 01 = Select P1.0 as the input of ACMP0. | ||
| 10 = Select P1.2 as the input of ACMP0. | ||
| 11 = Select P1.3 as the input of ACMP0. | ||
| [30] | TMR0TEN | TMR0 Trigger PWM Function Enable Bit |
| When this bit is set, TMR0 time-out event will update PWM_PHCHG with PHCHG_NXT register. | ||
| 0 = TMR0 trigger PWM function Disabled. | ||
| 1 = TMR0 trigger PWM function Enabled. | ||
| [31] | ACMP0TEN | ACMP0 Trigger Function Enable Bit |
| 0 = ACMP0 trigger PWM function Disabled. | ||
| 1 = ACMP0 trigger PWM function Enabled. | ||
| Note: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set. |
Definition at line 7783 of file Mini58Series.h.
| __I uint32_t GPIO_T::PIN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PIN0 | Port 0-5 Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin. | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [1] | PIN1 | Port 0-5 Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin. | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [2] | PIN2 | Port 0-5 Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin. | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [3] | PIN3 | Port 0-5 Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin. | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [4] | PIN4 | Port 0-5 Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin. | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [5] | PIN5 | Port 0-5 Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin. | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [6] | PIN6 | Port 0-5 Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin. | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. | ||
| [7] | PIN7 | Port 0-5 Pin[N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin. | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note: | ||
| Max. n=7 for port 0, n=2, n=3 are reserved. | ||
| Max. n=7 for port 1, n=1, n=6, n=7 are reserved. | ||
| Max. n=7 for port 2, n=0, n=1, n=7 are reserved. | ||
| Max. n=7 for port 3, n=3, n=7 are reserved. | ||
| Max. n=7 for port 4, n=0,.5 are reserved. | ||
| Max. n=7 for port 5, n=6, n=7 are reserved. |
Definition at line 2167 of file Mini58Series.h.
| __IO uint32_t CLK_T::PLLCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [8:0] | FBDIV | PLL Feedback Divider Control |
| Refer to the formulas below the table. | ||
| [13:9] | INDIV | PLL Input Divider Control |
| Refer to the formulas below the table. | ||
| [15:14] | OUTDIV | PLL Output Divider Control |
| Refer to the formulas below the table. | ||
| [16] | PD | Power-down Mode |
| If the PDEN bit is set to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode too. | ||
| 0 = PLL is in Normal mode. | ||
| 1 = PLL is in Power-down mode (default). | ||
| [17] | BP | PLL Bypass Control |
| 0 = PLL is in Normal mode (default). | ||
| 1 = PLL clock output is same as PLL source clock input. | ||
| [18] | OE | PLL OE (FOUT Enable) Pin Control |
| 0 = PLL FOUT Enabled. | ||
| 1 = PLL FOUT is fixed low. | ||
| [19] | PLLSRC | PLL Source Clock Selection |
| 0 = PLL source clock from HXT. | ||
| 1 = PLL source clock from HIRC. |
Definition at line 1144 of file Mini58Series.h.
| __IO uint32_t PWM_T::POEN |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | POEN0 | PWM Output Enable Bits |
| 0 = PWM channel n output to pin Disabled. | ||
| 1 = PWM channel n output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [5:0] | POEN1 | PWM Output Enable Bits |
| 0 = PWM channel n output to pin Disabled. | ||
| 1 = PWM channel n output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [5:0] | POEN2 | PWM Output Enable Bits |
| 0 = PWM channel n output to pin Disabled. | ||
| 1 = PWM channel n output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [5:0] | POEN3 | PWM Output Enable Bits |
| 0 = PWM channel n output to pin Disabled. | ||
| 1 = PWM channel n output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [5:0] | POEN4 | PWM Output Enable Bits |
| 0 = PWM channel n output to pin Disabled. | ||
| 1 = PWM channel n output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [5:0] | POEN5 | PWM Output Enable Bits |
| 0 = PWM channel n output to pin Disabled. | ||
| 1 = PWM channel n output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. |
Definition at line 7200 of file Mini58Series.h.
| __IO uint32_t CLK_T::PWRCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | XTLEN | External HXT Or LXT Crystal Oscillator Enable Bit (Write Protect) |
| The default clock source is from HIRC. | ||
| These two bits are default set to "00" and the XT1_IN and XT1_OUT pins are GPI. | ||
| 00 = XT1_IN and XT1_OUT are GPIO, disable both LXT & HXT (default). | ||
| 01 = HXT Enabled. | ||
| 10 = LXT Enabled. | ||
| 11 = XT1_IN is external clock input pin, XT1_OUT is GPIO. | ||
| Note: To enable external XTAL function, ALT[1:0] and MFP[1:0] bits must also be set in SYS_P5_MFP. | ||
| [2] | HIRCEN | HIRC Enable Bit (Write Protect) |
| 0 = 22.1184 MHz internal high speed RC oscillator (HIRC) Disabled. | ||
| 1 = 22.1184 MHz internal high speed RC oscillator (HIRC) Enabled. | ||
| Note: The default of HIRCEN bit is 1. | ||
| [3] | LIRCEN | LIRC Enable Bit (Write Protect) |
| 0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. | ||
| 1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. | ||
| [4] | PDWKDLY | Wake-up Delay Counter Enable Bit (Write Protect) |
| When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. | ||
| The delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal (HXT), 4096 clock cycles for 32.768 kHz external low speed crystal (LXT), and 16 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC). | ||
| 0 = Clock cycles delay Disabled. | ||
| 1 = Clock cycles delay Enabled. | ||
| [5] | PDWKIEN | Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) |
| 0 = Power-down mode wake-up interrupt Disabled. | ||
| 1 = Power-down mode wake-up interrupt Enabled. | ||
| Note: The interrupt will occur when both PDWKIF and PDWKIEN are high. | ||
| [6] | PDWKIF | Power-down Mode Wake-up Interrupt Status |
| Set by "Power-down wake-up event", which indicates that resume from Power-down mode | ||
| The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wake-up occurred. | ||
| Note: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. Write 1 to clear the bit to 0. | ||
| [7] | PDEN | System Power-down Enable Bit (Write Protect) |
| When chip wakes up from Power-down mode, this bit is cleared by hardware. | ||
| User needs to set this bit again for next Power-down. | ||
| In Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT), 32.768 kHz external low speed crystal oscillator (LXT), and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode. | ||
| In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. | ||
| The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator. | ||
| 0 = Chip operating normally or chip in Idle mode because of WFI command. | ||
| 1 = Chip enters Power-down mode instantly or waits CPU sleep command WFI. | ||
| [9] | PDLXT | Enable LXT In Power-down Mode |
| This bit controls the crystal oscillator active or not in Power-down mode. | ||
| 0 = No effect to Power-down mode. | ||
| 1 = If XTLEN[1:0] = 10, LXT is still active in Power-down mode. |
Definition at line 876 of file Mini58Series.h.
| __O uint32_t SYS_T::REGLCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | REGLCTL | Register Write-protection Code (Write Only) |
| Some registers have write-protection function. | ||
| Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. | ||
| After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal writ. | ||
| Register Write-protection Disable Index (Read Only) | ||
| 0 = Write-protection Enabled for writing protected registers. | ||
| Any write to the protected register is ignore. | ||
| 1 = Write-protection Disabled for writing protected registers. | ||
| Protected registers are listed below: | ||
| SYS_IPRST0 (0x5000_0008) : Peripheral Reset Control Resister 0 | ||
| SYS_BODCTL (0x5000_0018) : Brown-out Detector Control Register | ||
| CLK_PWRCTL (0x5000_0200) : Bit[6] is not protected for power wake-up interrupt clear. | ||
| CLK_APBCLK bit[0] (0x5000_0208) : Bit[0] is watchdog clock enable. | ||
| CLK_CLKSEL0 (0x5000_0210) : HCLK and CPU STCLK clock source select. | ||
| CLK_CLKSEL1 bit[1:0] (0x5000_0214) : Watchdog clock source select. | ||
| NMI_SEL bit[8] (0x5000_0380) : NMI interrupt enable. | ||
| ISPCON (0x5000_C000) : Flash ISP Control. | ||
| ISPTRG (0x5000_C010) : ISP Trigger Control. | ||
| WTCR (0x4000_4000) : Watchdog Timer Control. | ||
| Note: The bits which are write-protected will be noted as" (Write Protect)" beside the description. |
Definition at line 10055 of file Mini58Series.h.
| __O uint32_t WWDT_T::RLDCNT |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | RLDCNT | WWDT Reload Counter Register |
| Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. | ||
| Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). | ||
| If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will generate immediately. |
Definition at line 11541 of file Mini58Series.h.
| __IO uint32_t SYS_T::RSTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PORF | POR Reset Flag |
| The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. | ||
| 0 = No reset from POR or CHIPRST. | ||
| 1 = Power-on-Reset (POR) or CHIPRST had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [1] | PINRF | NRESET Pin Reset Flag |
| The nRESET pin reset flag is set by the "Reset Signal" from the nRESET pin to indicate the previous reset source. | ||
| 0 = No reset from nRESET pin. | ||
| 1 = Pin nRESET had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [2] | WDTRF | WDT Reset Flag |
| The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. | ||
| 0 = No reset from watchdog timer or window watchdog timer. | ||
| 1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [4] | BODRF | BOD Reset Flag |
| The BOD reset flag is set by the "Reset Signal" from the Brown-out Detector to indicate the previous reset source. | ||
| 0 = No reset from BOD. | ||
| 1 = The BOD had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [5] | SYSRF | System Reset Flag |
| The system reset flag is set by the "Reset Signal" from the Cortex-M0 Core to indicate the previous reset source. | ||
| 0 = No reset from Cortex-M0. | ||
| 1 = The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ (SCS_AIRCR[2]), Application Interrupt and Reset Control Register, address = 0xE000ED0C in system control registers of Cortex-M0 core. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [7] | CPURF | CPU Reset Flag |
| The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC). | ||
| 0 = No reset from CPU. | ||
| 1 = The Cortex-M0 Core and FMC are reset by software setting CPURST to 1. | ||
| Note: Software can write 1 to clear this bit to zero. | ||
| [8] | CPULKRF | The Cortex-M0 LOCKUP Flag |
| 0 = No reset from Cortex-M0 LOCKUP happened. | ||
| 1 = The Cortex-M0 LOCKUP happened and chip is reset. | ||
| Note: Software can write 1 to clear this bit to zero. |
Definition at line 9524 of file Mini58Series.h.
| __I uint32_t SPI_T::RX |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | RX | Data Receive Register (Read Only) |
| The Data Receive Register holds the value of received data of the last executed transfer. | ||
| Valid bits depend on the transmit bit length field DWIDTH in the SPI_CTL register. | ||
| For example, if DWIDTH is set to 0x08, the bit field RX[7:0] holds the received data. | ||
| The values of the other bits are unknown. | ||
| The Data Receive Register is read-only register. |
Definition at line 9134 of file Mini58Series.h.
| __IO uint32_t ADC_T::SEQCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SEQEN | ADC Sequential Mode Enable Bit |
| When ADC sequential mode is enabled, two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0, 1] or channel[1, 2] or channel[0, 2] defined by MODESEL (ADC_SEQCTL[3:2]). | ||
| 0 = ADC sequential mode Disabled. | ||
| 1 = ADC sequential mode Enabled. | ||
| [1] | SEQTYPE | ADC Sequential Mode Type |
| 0 = ADC delay time is only inserted before the first conversion. | ||
| The second conversion starts immediately after the first conversion is completed. | ||
| (for 2/3-shunt type). | ||
| 1 = ADC delay time is inserted before each conversion. (for 1-shunt type) | ||
| [3:2] | MODESEL | ADC Sequential Mode Selection |
| 00 = Issue ADC_INT after Channel 0 then Channel 1 conversion finishes when SEQEN =1. | ||
| 01 = Issue ADC_INT after Channel 1 then Channel 2 conversion finishes when SEQEN =1. | ||
| 10 = Issue ADC_INT after Channel 0 then Channel 2 conversion finishes when SEQEN =1. | ||
| 11 = Reserved. | ||
| [11:8] | TRG1CTL | PWM Trigger Source Selection For TRG1CTL[3:2] |
| 00 = PWM Trigger source is PWM0. | ||
| 01 = PWM Trigger source is PWM2. | ||
| 10 = PWM Trigger source is PWM4. | ||
| 11 = PWM Trigger source is reserved. | ||
| PWM Trigger Type Selection for TRG1CTL[1:0] | ||
| 00 = Rising of the selected PWM. | ||
| 01 = Center of the selected PWM. | ||
| 10 = Falling of the selected PWM. | ||
| 11 = Period of the selected PWM. | ||
| Note: PWM trigger source is valid for 1-shunt and 2/3-shunt type. | ||
| [19:16] | TRG2CTL | PWM Trigger Source Selection For TRG2CTL[3:2] |
| 00 = PWM Trigger source is PWM0. | ||
| 01 = PWM Trigger source is PWM2. | ||
| 10 = PWM Trigger source is PWM4. | ||
| 11 = PWM Trigger source is reserved. | ||
| PWM Trigger Type Selection for TRG2CTL[1:0] | ||
| 00 = Rising of the selected PWM. | ||
| 01 = Center of the selected PWM. | ||
| 10 = Falling of the selected PWM. | ||
| 11 = Period of the selected PWM. | ||
| Note: PWM trigger source is valid for 1-shunt type. |
Definition at line 613 of file Mini58Series.h.
| __I uint32_t ADC_T::SEQDAT1 |
| Bits | Field | Descriptions |
|---|---|---|
| [9:0] | RESULT | A/D PWM Sequential Mode Conversion Result |
| This field contains conversion result of ADC. | ||
| [16] | OV | Over Run Flag |
| If converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. | ||
| It is cleared by hardware after the ADC_DAT register is read. | ||
| 0 = Data in RESULT[9:0] is recent conversion result. | ||
| 1 = Data in RESULT[9:0] overwritten. | ||
| [17] | VALID | Valid Flag |
| This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read. | ||
| 0 = Data in RESULT[9:0] bits not valid. | ||
| 1 = Data in RESULT[9:0] bits valid. |
Definition at line 634 of file Mini58Series.h.
| __I uint32_t ADC_T::SEQDAT2 |
| Bits | Field | Descriptions |
|---|---|---|
| [9:0] | RESULT | A/D PWM Sequential Mode Conversion Result |
| This field contains conversion result of ADC. | ||
| [16] | OV | Over Run Flag |
| If converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. | ||
| It is cleared by hardware after the ADC_DAT register is read. | ||
| 0 = Data in RESULT[9:0] is recent conversion result. | ||
| 1 = Data in RESULT[9:0] overwritten. | ||
| [17] | VALID | Valid Flag |
| This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read. | ||
| 0 = Data in RESULT[9:0] bits not valid. | ||
| 1 = Data in RESULT[9:0] bits valid. |
Definition at line 655 of file Mini58Series.h.
| __IO uint32_t SPI_T::SLVCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [8] | SLV3WIRE | Slave 3-wire Mode Enable Bit (Slave Only) |
| The SPI controller work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI. | ||
| 0 = The controller is 4-wire bi-direction interface in Slave mode. | ||
| 1 = The controller is 3-wire bi-direction interface in Slave mode. | ||
| The controller will be ready to transmit/receive data after the SPIEN bit is set to . | ||
| Note: In Slave 3-wire mode, the SSLTEN bit (SPI_SSCTL[4]) shall be set as 1. | ||
| [9] | SLVABT | Slave 3-wire Mode Abort Control Bit (Slave Only) |
| In normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in DWIDTH. | ||
| If the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event. | ||
| 0 = No force the transfer done when the SLV3WIRE bit is set to 1. | ||
| 1 = Force the transfer done when the SLV3WIRE bit is set to 1. | ||
| Note: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. | ||
| [10] | SLVSTIEN | Slave 3-wire Mode Start Interrupt Enable (Slave Only) |
| It is used to enable interrupt when the transfer has started in Slave 3-wire mode. | ||
| If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLVABT bit to force the transfer don. | ||
| 0 = Transaction start interrupt Disabled. | ||
| 1 = Transaction start interrupt Enabled. | ||
| Note: It will be cleared to 0 as the current transfer is done or the SLVSTIF bit is cleared to 0. | ||
| [11] | SLVSTIF | Slave 3-wire Mode Start Interrupt Status (Slave Only) |
| This bit dedicates if a transaction has started in Slave 3-wire mode. | ||
| 0 = Slave does not detect any SPI bus clock transfer since the SLVSTIEN bit was set to 1. | ||
| 1 = The transfer has started in Slave 3-wire mode. | ||
| Note 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit. | ||
| Note 2: It is a mutual mirror bit of SPI_STATUS[11]. | ||
| [16] | SSINAIEN | Slave Select Inactive Interrupt Option (Slave Only) |
| 0 = As the slave select signal goes to inactive level, the IF bit will NOT be set to 1. | ||
| 1 = As the slave select signal goes to inactive level, the IF bit will be set to 1. | ||
| Note: This setting is only available if the SPI controller is configured as level trigger in slave device. | ||
| [31] | DIVMOD | Clock Configuration Backward Compatible Option |
| 0 = The clock configuration is backward compatible. | ||
| 1 = The clock configuration is not backward compatible. | ||
| Note: | ||
| Refer to the description of SPI_CLKDIV register for details. |
Definition at line 9199 of file Mini58Series.h.
| __IO uint32_t SPI_T::SSCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SS | Slave Select Control Bits (Master Only) |
| If AUTOSS bit is 0, | ||
| 0 = Set the SPI_SS line to inactive state. | ||
| 1 = Set the SPI_SS line to active state. | ||
| If AUTOSS bit is 1, | ||
| 0 = Keep the SPI_SS line at inactive state. | ||
| 1 = Select the SPI_SS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. | ||
| The active state of SPI_SS is specified in SSACTPOL bit. | ||
| [2] | SSACTPOL | Slave Select Active Level (Slave Only) |
| It defines the active status of slave select signal (SPI_SS). | ||
| If SSLTEN bit is 1: | ||
| 0 = The slave select signal SPI_SS is active at low-level. | ||
| 1 = The slave select signal SPI_SS is active at high-level. | ||
| If SSLTEN bit is 0: | ||
| 0 = The slave select signal SPI_SS is active at falling-edge. | ||
| 1 = The slave select signal SPI_SS is active at rising-edge. | ||
| [3] | AUTOSS | Automatic Slave Selection Function Enable Bit (Master Only) |
| 0 = SPI_SS pin signal will be asserted/de-asserted by setting /clearing SS bit. | ||
| 1 = SPI_SS pin signal will be generated automatically by hardware, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting SPIEN, and will be de-asserted after each transmit/receive is finished. | ||
| [4] | SSLTEN | Slave Select Level Trigger Enable Bit (Slave Only) |
| 0 = The input slave select signal is edge-trigger. | ||
| 1 = The input slave select signal is level-trigger. | ||
| [5] | LTF | Level Trigger Flag (Read Only, Slave Only) |
| When the SSLTEN bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not. | ||
| 0 = The transaction number or the transferred bit length of one transaction does not meet the specified requirements. | ||
| 1 = The transaction number and the transferred bit length meet the specified requirements which defined in DWIDTH. |
Definition at line 9114 of file Mini58Series.h.
| __IO uint32_t ACMP_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ACMPIF0 | Analog Comparator 0 Flag |
| This bit is set by hardware whenever the comparator 0 output changes state. | ||
| This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) = 1. | ||
| 0 = Analog comparator 0 output does not change. | ||
| 1 = Analog comparator 0 output changed. | ||
| Note: This bit can be cleared to 0 by software writing 1. | ||
| [1] | ACMPIF1 | Analog Comparator 1 Flag |
| This bit is set by hardware whenever the comparator 1 output changes state. | ||
| This will generate an interrupt if ACMPIE (ACMP_CTL1[1]) = 1. | ||
| 0 = Analog comparator 1 output does not change. | ||
| 1 = Analog comparator 1 output changed. | ||
| Note: This bit can be cleared to 0 by software writing 1. | ||
| [2] | ACMPO0 | Analog Comparator 0 Output |
| Synchronized to the APB clock to allow reading by software. | ||
| Cleared when the comparator 0 is disabled ACMPEN (ACMP_CTL0[0]) = 0. | ||
| 0 = Analog comparator 0 outputs 0. | ||
| 1 = Analog comparator 0 outputs 1. | ||
| [3] | ACMPO1 | Analog Comparator 1 Output |
| Synchronized to the APB clock to allow reading by software. | ||
| Cleared when the comparator 1 is disabled ACMPEN (ACMP_CTL1[0]) = 0. | ||
| 0 = Analog comparator 1 outputs 0. | ||
| 1 = Analog comparator 1 outputs 1. |
Definition at line 245 of file Mini58Series.h.
| __IO uint32_t ADC_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADIF | A/D Conversion End Flag |
| A status flag that indicates the end of A/D conversion. ADIF is set to 1 When A/D conversion ends. | ||
| Note: This bit can be cleared to 0 by software writing 1. | ||
| [1] | ADCMPF0 | A/D Compare Flag 0 |
| When the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1. | ||
| 0 = Conversion result in ADC_DAT does not meet the ADC_CMP0 setting. | ||
| 1 = Conversion result in ADC_DAT meets the ADC_CMP0 setting. | ||
| Note: This bit can be cleared to 0 by software writing 1. | ||
| [2] | ADCMPF1 | A/D Compare Flag 1 |
| When the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1. | ||
| 0 = Conversion result in ADC_DAT does not meet the ADC_CMP1 setting. | ||
| 1 = Conversion result in ADC_DAT meets the ADC_CMP1 setting. | ||
| Note: This bit can be cleared to 0 by software writing 1. | ||
| [3] | BUSY | BUSY/IDLE (Read Only) |
| This bit is mirror of as SWTRG bit in ADC_CTL | ||
| 0 = A/D converter is in idle state. | ||
| 1 = A/D converter is busy at conversion. | ||
| [6:4] | CHANNEL | Current Conversion Channel (Read Only) |
| This filed reflects the current conversion channel when BUSY=1. | ||
| When BUSY=0, it shows the number of the next converted channel. | ||
| [8] | VALID | Data Valid Flag (Read Only) |
| It is a mirror of VALID bit in ADC_DAT register. | ||
| [16] | OV | Overrun Flag (Read Only) |
| It is a mirror to OV bit in ADC_DAT register. |
Definition at line 520 of file Mini58Series.h.
| __IO uint32_t CLK_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | XTLSTB | HXT Or LXT Clock Source Stable Flag |
| 0 = HXT or LXT clock is not stable or disabled. | ||
| 1 = HXT or LXT clock is stable and enabled. | ||
| [2] | PLLSTB | Internal PLL Clock Source Stable Flag (Read Only) |
| 0 = Internal PLL clock is not stable or disabled. | ||
| 1 = Internal PLL clock is stable and enabled. | ||
| [3] | LIRCSTB | LIRC Clock Source Stable Flag (Read Only) |
| 0 = LIRC clock is not stable or disabled. | ||
| 1 = LIRC clock is stable and enabled. | ||
| [4] | HIRCSTB | HIRC Clock Source Stable Flag (Read Only) |
| 0 = HIRC clock is not stable or disabled. | ||
| 1 = HIRC clock is stable and enabled. | ||
| [7] | CLKSFAIL | Clock Switch Fail Flag (Read Only) |
| This bit is updated when software switches system clock source. | ||
| If switch target clock is stable, this bit will be set to 0. | ||
| If switch target clock is not stable, this bit will be set to . | ||
| 0 = Clock switching success. | ||
| 1 = Clock switching failure. | ||
| Note: This bit is read only. | ||
| After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. |
Definition at line 973 of file Mini58Series.h.
| __I uint32_t I2C_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | STATUS | I2C Status Register |
| The three least significant bits are always 0. | ||
| The five most significant bits contain the status code. | ||
| There are 26 possible status codes. | ||
| When I2C_STATUS contains F8H, no serial interrupt is requested. | ||
| All the other I2C_STATUS values correspond to defined I2C states. | ||
| When each of these states is entered, a status interrupt is requested (SI = 1). | ||
| A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software. | ||
| In addition, the states 00H stands for a Bus Error. | ||
| A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame. | ||
| Examples of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. |