SOFTWARE API DEFINITION FOR Power Management Controller. More...
Classes | |
| struct | Pmc |
| Pmc hardware registers. More... | |
Macros | |
| #define | PMC_SCER_UHP (0x1u << 6) |
| (PMC_SCER) USB Host Port Clock Enable More... | |
| #define | PMC_SCER_UDP (0x1u << 7) |
| (PMC_SCER) USB Device Port Clock Enable More... | |
| #define | PMC_SCER_PCK0 (0x1u << 8) |
| (PMC_SCER) Programmable Clock 0 Output Enable More... | |
| #define | PMC_SCER_PCK1 (0x1u << 9) |
| (PMC_SCER) Programmable Clock 1 Output Enable More... | |
| #define | PMC_SCER_PCK2 (0x1u << 10) |
| (PMC_SCER) Programmable Clock 2 Output Enable More... | |
| #define | PMC_SCER_PCK3 (0x1u << 11) |
| (PMC_SCER) Programmable Clock 3 Output Enable More... | |
| #define | PMC_SCER_PCK4 (0x1u << 12) |
| (PMC_SCER) Programmable Clock 4 Output Enable More... | |
| #define | PMC_SCER_PCK5 (0x1u << 13) |
| (PMC_SCER) Programmable Clock 5 Output Enable More... | |
| #define | PMC_SCER_PCK6 (0x1u << 14) |
| (PMC_SCER) Programmable Clock 6 Output Enable More... | |
| #define | PMC_SCER_PCK7 (0x1u << 15) |
| (PMC_SCER) Programmable Clock 7 Output Enable More... | |
| #define | PMC_SCDR_UHP (0x1u << 6) |
| (PMC_SCDR) USB Host Port Clock Disable More... | |
| #define | PMC_SCDR_UDP (0x1u << 7) |
| (PMC_SCDR) More... | |
| #define | PMC_SCDR_PCK0 (0x1u << 8) |
| (PMC_SCDR) Programmable Clock 0 Output Disable More... | |
| #define | PMC_SCDR_PCK1 (0x1u << 9) |
| (PMC_SCDR) Programmable Clock 1 Output Disable More... | |
| #define | PMC_SCDR_PCK2 (0x1u << 10) |
| (PMC_SCDR) Programmable Clock 2 Output Disable More... | |
| #define | PMC_SCDR_PCK3 (0x1u << 11) |
| (PMC_SCDR) Programmable Clock 3 Output Disable More... | |
| #define | PMC_SCDR_PCK4 (0x1u << 12) |
| (PMC_SCDR) Programmable Clock 4 Output Disable More... | |
| #define | PMC_SCDR_PCK5 (0x1u << 13) |
| (PMC_SCDR) Programmable Clock 5 Output Disable More... | |
| #define | PMC_SCDR_PCK6 (0x1u << 14) |
| (PMC_SCDR) Programmable Clock 6 Output Disable More... | |
| #define | PMC_SCDR_PCK7 (0x1u << 15) |
| (PMC_SCDR) Programmable Clock 7 Output Disable More... | |
| #define | PMC_SCSR_UHP (0x1u << 6) |
| (PMC_SCSR) USB Host Port Clock Status More... | |
| #define | PMC_SCSR_UDP (0x1u << 7) |
| (PMC_SCSR) More... | |
| #define | PMC_SCSR_PCK0 (0x1u << 8) |
| (PMC_SCSR) Programmable Clock 0 Output Status More... | |
| #define | PMC_SCSR_PCK1 (0x1u << 9) |
| (PMC_SCSR) Programmable Clock 1 Output Status More... | |
| #define | PMC_SCSR_PCK2 (0x1u << 10) |
| (PMC_SCSR) Programmable Clock 2 Output Status More... | |
| #define | PMC_SCSR_PCK3 (0x1u << 11) |
| (PMC_SCSR) Programmable Clock 3 Output Status More... | |
| #define | PMC_SCSR_PCK4 (0x1u << 12) |
| (PMC_SCSR) Programmable Clock 4 Output Status More... | |
| #define | PMC_SCSR_PCK5 (0x1u << 13) |
| (PMC_SCSR) Programmable Clock 5 Output Status More... | |
| #define | PMC_SCSR_PCK6 (0x1u << 14) |
| (PMC_SCSR) Programmable Clock 6 Output Status More... | |
| #define | PMC_SCSR_PCK7 (0x1u << 15) |
| (PMC_SCSR) Programmable Clock 7 Output Status More... | |
| #define | PMC_PCER0_PID8 (0x1u << 8) |
| (PMC_PCER0) Peripheral Clock 8 Enable More... | |
| #define | PMC_PCER0_PID9 (0x1u << 9) |
| (PMC_PCER0) Peripheral Clock 9 Enable More... | |
| #define | PMC_PCER0_PID10 (0x1u << 10) |
| (PMC_PCER0) Peripheral Clock 10 Enable More... | |
| #define | PMC_PCER0_PID11 (0x1u << 11) |
| (PMC_PCER0) Peripheral Clock 11 Enable More... | |
| #define | PMC_PCER0_PID12 (0x1u << 12) |
| (PMC_PCER0) Peripheral Clock 12 Enable More... | |
| #define | PMC_PCER0_PID13 (0x1u << 13) |
| (PMC_PCER0) Peripheral Clock 13 Enable More... | |
| #define | PMC_PCER0_PID14 (0x1u << 14) |
| (PMC_PCER0) Peripheral Clock 14 Enable More... | |
| #define | PMC_PCER0_PID15 (0x1u << 15) |
| (PMC_PCER0) Peripheral Clock 15 Enable More... | |
| #define | PMC_PCER0_PID16 (0x1u << 16) |
| (PMC_PCER0) Peripheral Clock 16 Enable More... | |
| #define | PMC_PCER0_PID17 (0x1u << 17) |
| (PMC_PCER0) Peripheral Clock 17 Enable More... | |
| #define | PMC_PCER0_PID18 (0x1u << 18) |
| (PMC_PCER0) Peripheral Clock 18 Enable More... | |
| #define | PMC_PCER0_PID19 (0x1u << 19) |
| (PMC_PCER0) Peripheral Clock 19 Enable More... | |
| #define | PMC_PCER0_PID20 (0x1u << 20) |
| (PMC_PCER0) Peripheral Clock 20 Enable More... | |
| #define | PMC_PCER0_PID21 (0x1u << 21) |
| (PMC_PCER0) Peripheral Clock 21 Enable More... | |
| #define | PMC_PCER0_PID22 (0x1u << 22) |
| (PMC_PCER0) Peripheral Clock 22 Enable More... | |
| #define | PMC_PCER0_PID23 (0x1u << 23) |
| (PMC_PCER0) Peripheral Clock 23 Enable More... | |
| #define | PMC_PCER0_PID24 (0x1u << 24) |
| (PMC_PCER0) Peripheral Clock 24 Enable More... | |
| #define | PMC_PCER0_PID25 (0x1u << 25) |
| (PMC_PCER0) Peripheral Clock 25 Enable More... | |
| #define | PMC_PCER0_PID26 (0x1u << 26) |
| (PMC_PCER0) Peripheral Clock 26 Enable More... | |
| #define | PMC_PCER0_PID27 (0x1u << 27) |
| (PMC_PCER0) Peripheral Clock 27 Enable More... | |
| #define | PMC_PCER0_PID28 (0x1u << 28) |
| (PMC_PCER0) Peripheral Clock 28 Enable More... | |
| #define | PMC_PCER0_PID29 (0x1u << 29) |
| (PMC_PCER0) Peripheral Clock 29 Enable More... | |
| #define | PMC_PCER0_PID30 (0x1u << 30) |
| (PMC_PCER0) Peripheral Clock 30 Enable More... | |
| #define | PMC_PCER0_PID31 (0x1u << 31) |
| (PMC_PCER0) Peripheral Clock 31 Enable More... | |
| #define | PMC_PCDR0_PID8 (0x1u << 8) |
| (PMC_PCDR0) Peripheral Clock 8 Disable More... | |
| #define | PMC_PCDR0_PID9 (0x1u << 9) |
| (PMC_PCDR0) Peripheral Clock 9 Disable More... | |
| #define | PMC_PCDR0_PID10 (0x1u << 10) |
| (PMC_PCDR0) Peripheral Clock 10 Disable More... | |
| #define | PMC_PCDR0_PID11 (0x1u << 11) |
| (PMC_PCDR0) Peripheral Clock 11 Disable More... | |
| #define | PMC_PCDR0_PID12 (0x1u << 12) |
| (PMC_PCDR0) Peripheral Clock 12 Disable More... | |
| #define | PMC_PCDR0_PID13 (0x1u << 13) |
| (PMC_PCDR0) Peripheral Clock 13 Disable More... | |
| #define | PMC_PCDR0_PID14 (0x1u << 14) |
| (PMC_PCDR0) Peripheral Clock 14 Disable More... | |
| #define | PMC_PCDR0_PID15 (0x1u << 15) |
| (PMC_PCDR0) Peripheral Clock 15 Disable More... | |
| #define | PMC_PCDR0_PID16 (0x1u << 16) |
| (PMC_PCDR0) Peripheral Clock 16 Disable More... | |
| #define | PMC_PCDR0_PID17 (0x1u << 17) |
| (PMC_PCDR0) Peripheral Clock 17 Disable More... | |
| #define | PMC_PCDR0_PID18 (0x1u << 18) |
| (PMC_PCDR0) Peripheral Clock 18 Disable More... | |
| #define | PMC_PCDR0_PID19 (0x1u << 19) |
| (PMC_PCDR0) Peripheral Clock 19 Disable More... | |
| #define | PMC_PCDR0_PID20 (0x1u << 20) |
| (PMC_PCDR0) Peripheral Clock 20 Disable More... | |
| #define | PMC_PCDR0_PID21 (0x1u << 21) |
| (PMC_PCDR0) Peripheral Clock 21 Disable More... | |
| #define | PMC_PCDR0_PID22 (0x1u << 22) |
| (PMC_PCDR0) Peripheral Clock 22 Disable More... | |
| #define | PMC_PCDR0_PID23 (0x1u << 23) |
| (PMC_PCDR0) Peripheral Clock 23 Disable More... | |
| #define | PMC_PCDR0_PID24 (0x1u << 24) |
| (PMC_PCDR0) Peripheral Clock 24 Disable More... | |
| #define | PMC_PCDR0_PID25 (0x1u << 25) |
| (PMC_PCDR0) Peripheral Clock 25 Disable More... | |
| #define | PMC_PCDR0_PID26 (0x1u << 26) |
| (PMC_PCDR0) Peripheral Clock 26 Disable More... | |
| #define | PMC_PCDR0_PID27 (0x1u << 27) |
| (PMC_PCDR0) Peripheral Clock 27 Disable More... | |
| #define | PMC_PCDR0_PID28 (0x1u << 28) |
| (PMC_PCDR0) Peripheral Clock 28 Disable More... | |
| #define | PMC_PCDR0_PID29 (0x1u << 29) |
| (PMC_PCDR0) Peripheral Clock 29 Disable More... | |
| #define | PMC_PCDR0_PID30 (0x1u << 30) |
| (PMC_PCDR0) Peripheral Clock 30 Disable More... | |
| #define | PMC_PCDR0_PID31 (0x1u << 31) |
| (PMC_PCDR0) Peripheral Clock 31 Disable More... | |
| #define | PMC_PCSR0_PID8 (0x1u << 8) |
| (PMC_PCSR0) Peripheral Clock 8 Status More... | |
| #define | PMC_PCSR0_PID9 (0x1u << 9) |
| (PMC_PCSR0) Peripheral Clock 9 Status More... | |
| #define | PMC_PCSR0_PID10 (0x1u << 10) |
| (PMC_PCSR0) Peripheral Clock 10 Status More... | |
| #define | PMC_PCSR0_PID11 (0x1u << 11) |
| (PMC_PCSR0) Peripheral Clock 11 Status More... | |
| #define | PMC_PCSR0_PID12 (0x1u << 12) |
| (PMC_PCSR0) Peripheral Clock 12 Status More... | |
| #define | PMC_PCSR0_PID13 (0x1u << 13) |
| (PMC_PCSR0) Peripheral Clock 13 Status More... | |
| #define | PMC_PCSR0_PID14 (0x1u << 14) |
| (PMC_PCSR0) Peripheral Clock 14 Status More... | |
| #define | PMC_PCSR0_PID15 (0x1u << 15) |
| (PMC_PCSR0) Peripheral Clock 15 Status More... | |
| #define | PMC_PCSR0_PID16 (0x1u << 16) |
| (PMC_PCSR0) Peripheral Clock 16 Status More... | |
| #define | PMC_PCSR0_PID17 (0x1u << 17) |
| (PMC_PCSR0) Peripheral Clock 17 Status More... | |
| #define | PMC_PCSR0_PID18 (0x1u << 18) |
| (PMC_PCSR0) Peripheral Clock 18 Status More... | |
| #define | PMC_PCSR0_PID19 (0x1u << 19) |
| (PMC_PCSR0) Peripheral Clock 19 Status More... | |
| #define | PMC_PCSR0_PID20 (0x1u << 20) |
| (PMC_PCSR0) Peripheral Clock 20 Status More... | |
| #define | PMC_PCSR0_PID21 (0x1u << 21) |
| (PMC_PCSR0) Peripheral Clock 21 Status More... | |
| #define | PMC_PCSR0_PID22 (0x1u << 22) |
| (PMC_PCSR0) Peripheral Clock 22 Status More... | |
| #define | PMC_PCSR0_PID23 (0x1u << 23) |
| (PMC_PCSR0) Peripheral Clock 23 Status More... | |
| #define | PMC_PCSR0_PID24 (0x1u << 24) |
| (PMC_PCSR0) Peripheral Clock 24 Status More... | |
| #define | PMC_PCSR0_PID25 (0x1u << 25) |
| (PMC_PCSR0) Peripheral Clock 25 Status More... | |
| #define | PMC_PCSR0_PID26 (0x1u << 26) |
| (PMC_PCSR0) Peripheral Clock 26 Status More... | |
| #define | PMC_PCSR0_PID27 (0x1u << 27) |
| (PMC_PCSR0) Peripheral Clock 27 Status More... | |
| #define | PMC_PCSR0_PID28 (0x1u << 28) |
| (PMC_PCSR0) Peripheral Clock 28 Status More... | |
| #define | PMC_PCSR0_PID29 (0x1u << 29) |
| (PMC_PCSR0) Peripheral Clock 29 Status More... | |
| #define | PMC_PCSR0_PID30 (0x1u << 30) |
| (PMC_PCSR0) Peripheral Clock 30 Status More... | |
| #define | PMC_PCSR0_PID31 (0x1u << 31) |
| (PMC_PCSR0) Peripheral Clock 31 Status More... | |
| #define | CKGR_MOR_MOSCXTEN (0x1u << 0) |
| (CKGR_MOR) Main Crystal Oscillator Enable More... | |
| #define | CKGR_MOR_MOSCXTBY (0x1u << 1) |
| (CKGR_MOR) Main Crystal Oscillator Bypass More... | |
| #define | CKGR_MOR_WAITMODE (0x1u << 2) |
| (CKGR_MOR) Wait Mode Command More... | |
| #define | CKGR_MOR_MOSCRCEN (0x1u << 3) |
| (CKGR_MOR) Main On-Chip RC Oscillator Enable More... | |
| #define | CKGR_MOR_MOSCRCF_Pos 4 |
| #define | CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) |
| (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection More... | |
| #define | CKGR_MOR_MOSCRCF_8_MHz (0x0u << 4) |
| (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz (default) More... | |
| #define | CKGR_MOR_MOSCRCF_16_MHz (0x1u << 4) |
| (CKGR_MOR) The Fast RC Oscillator Frequency is at 16 MHz More... | |
| #define | CKGR_MOR_MOSCRCF_24_MHz (0x2u << 4) |
| (CKGR_MOR) The Fast RC Oscillator Frequency is at 24 MHz More... | |
| #define | CKGR_MOR_MOSCXTST_Pos 8 |
| #define | CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) |
| (CKGR_MOR) Main Crystal Oscillator Start-up Time More... | |
| #define | CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) |
| #define | CKGR_MOR_KEY_Pos 16 |
| #define | CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) |
| (CKGR_MOR) Write Access Password More... | |
| #define | CKGR_MOR_KEY_PASSWD (0x37u << 16) |
| (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. More... | |
| #define | CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) |
| #define | CKGR_MOR_MOSCSEL (0x1u << 24) |
| (CKGR_MOR) Main Oscillator Selection More... | |
| #define | CKGR_MOR_CFDEN (0x1u << 25) |
| (CKGR_MOR) Clock Failure Detector Enable More... | |
| #define | CKGR_MCFR_MAINF_Pos 0 |
| #define | CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) |
| (CKGR_MCFR) Main Clock Frequency More... | |
| #define | CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) |
| #define | CKGR_MCFR_MAINFRDY (0x1u << 16) |
| (CKGR_MCFR) Main Clock Ready More... | |
| #define | CKGR_MCFR_RCMEAS (0x1u << 20) |
| (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) More... | |
| #define | CKGR_PLLAR_PLLAEN_Pos 0 |
| #define | CKGR_PLLAR_PLLAEN_Msk (0xffu << CKGR_PLLAR_PLLAEN_Pos) |
| (CKGR_PLLAR) PLLA Control More... | |
| #define | CKGR_PLLAR_PLLAEN(value) ((CKGR_PLLAR_PLLAEN_Msk & ((value) << CKGR_PLLAR_PLLAEN_Pos))) |
| #define | CKGR_PLLAR_PLLACOUNT_Pos 8 |
| #define | CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) |
| (CKGR_PLLAR) PLLA Counter More... | |
| #define | CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) |
| #define | CKGR_PLLAR_MULA_Pos 16 |
| #define | CKGR_PLLAR_MULA_Msk (0x1fffu << CKGR_PLLAR_MULA_Pos) |
| (CKGR_PLLAR) PLLA Multiplier More... | |
| #define | CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) |
| #define | CKGR_PLLBR_PLLBEN_Pos 0 |
| #define | CKGR_PLLBR_PLLBEN_Msk (0xffu << CKGR_PLLBR_PLLBEN_Pos) |
| (CKGR_PLLBR) PLLB Control More... | |
| #define | CKGR_PLLBR_PLLBEN(value) ((CKGR_PLLBR_PLLBEN_Msk & ((value) << CKGR_PLLBR_PLLBEN_Pos))) |
| #define | CKGR_PLLBR_PLLBCOUNT_Pos 8 |
| #define | CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) |
| (CKGR_PLLBR) PLLB Counter More... | |
| #define | CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos))) |
| #define | CKGR_PLLBR_MULB_Pos 16 |
| #define | CKGR_PLLBR_MULB_Msk (0xfffu << CKGR_PLLBR_MULB_Pos) |
| (CKGR_PLLBR) PLLB Multiplier More... | |
| #define | CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos))) |
| #define | PMC_MCKR_CSS_Pos 0 |
| #define | PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) |
| (PMC_MCKR) Master Clock Source Selection More... | |
| #define | PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) |
| (PMC_MCKR) Slow Clock is selected More... | |
| #define | PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) |
| (PMC_MCKR) Main Clock is selected More... | |
| #define | PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) |
| (PMC_MCKR) PLLA Clock is selected More... | |
| #define | PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) |
| (PMC_MCKR) PLLA Clock is selected More... | |
| #define | PMC_MCKR_PRES_Pos 4 |
| #define | PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) |
| (PMC_MCKR) Processor Clock Prescaler More... | |
| #define | PMC_MCKR_PRES_CLK_1 (0x0u << 4) |
| (PMC_MCKR) Selected clock More... | |
| #define | PMC_MCKR_PRES_CLK_2 (0x1u << 4) |
| (PMC_MCKR) Selected clock divided by 2 More... | |
| #define | PMC_MCKR_PRES_CLK_4 (0x2u << 4) |
| (PMC_MCKR) Selected clock divided by 4 More... | |
| #define | PMC_MCKR_PRES_CLK_8 (0x3u << 4) |
| (PMC_MCKR) Selected clock divided by 8 More... | |
| #define | PMC_MCKR_PRES_CLK_16 (0x4u << 4) |
| (PMC_MCKR) Selected clock divided by 16 More... | |
| #define | PMC_MCKR_PRES_CLK_32 (0x5u << 4) |
| (PMC_MCKR) Selected clock divided by 32 More... | |
| #define | PMC_MCKR_PRES_CLK_64 (0x6u << 4) |
| (PMC_MCKR) Selected clock divided by 64 More... | |
| #define | PMC_MCKR_PRES_CLK_3 (0x7u << 4) |
| (PMC_MCKR) Selected clock divided by 3 More... | |
| #define | PMC_MCKR_PLLADIV2 (0x1u << 12) |
| (PMC_MCKR) PLLA Divisor by 2 More... | |
| #define | PMC_MCKR_PLLBDIV2 (0x1u << 13) |
| (PMC_MCKR) PLLB Divisor by 2 More... | |
| #define | PMC_USB_USBS (0x1u << 0) |
| (PMC_USB) USB Input Clock Selection More... | |
| #define | PMC_USB_USBDIV_Pos 8 |
| #define | PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) |
| (PMC_USB) Divider for USB Clock More... | |
| #define | PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) |
| #define | PMC_PCK_CSS_Pos 0 |
| #define | PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) |
| (PMC_PCK[3]) Master Clock Source Selection More... | |
| #define | PMC_PCK_CSS_SLOW_CLK (0x0u << 0) |
| (PMC_PCK[3]) Slow Clock is selected More... | |
| #define | PMC_PCK_CSS_MAIN_CLK (0x1u << 0) |
| (PMC_PCK[3]) Main Clock is selected More... | |
| #define | PMC_PCK_CSS_PLLA_CLK (0x2u << 0) |
| (PMC_PCK[3]) PLLA Clock is selected More... | |
| #define | PMC_PCK_CSS_PLLB_CLK (0x3u << 0) |
| (PMC_PCK[3]) PLLB Clock is selected More... | |
| #define | PMC_PCK_CSS_MCK (0x4u << 0) |
| (PMC_PCK[3]) Master Clock is selected More... | |
| #define | PMC_PCK_PRES_Pos 4 |
| #define | PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) |
| (PMC_PCK[3]) Programmable Clock Prescaler More... | |
| #define | PMC_PCK_PRES_CLK_1 (0x0u << 4) |
| (PMC_PCK[3]) Selected clock More... | |
| #define | PMC_PCK_PRES_CLK_2 (0x1u << 4) |
| (PMC_PCK[3]) Selected clock divided by 2 More... | |
| #define | PMC_PCK_PRES_CLK_4 (0x2u << 4) |
| (PMC_PCK[3]) Selected clock divided by 4 More... | |
| #define | PMC_PCK_PRES_CLK_8 (0x3u << 4) |
| (PMC_PCK[3]) Selected clock divided by 8 More... | |
| #define | PMC_PCK_PRES_CLK_16 (0x4u << 4) |
| (PMC_PCK[3]) Selected clock divided by 16 More... | |
| #define | PMC_PCK_PRES_CLK_32 (0x5u << 4) |
| (PMC_PCK[3]) Selected clock divided by 32 More... | |
| #define | PMC_PCK_PRES_CLK_64 (0x6u << 4) |
| (PMC_PCK[3]) Selected clock divided by 64 More... | |
| #define | PMC_IER_MOSCXTS (0x1u << 0) |
| (PMC_IER) Main Crystal Oscillator Status Interrupt Enable More... | |
| #define | PMC_IER_LOCKA (0x1u << 1) |
| (PMC_IER) PLLA Lock Interrupt Enable More... | |
| #define | PMC_IER_LOCKB (0x1u << 2) |
| (PMC_IER) PLLB Lock Interrupt Enable More... | |
| #define | PMC_IER_MCKRDY (0x1u << 3) |
| (PMC_IER) Master Clock Ready Interrupt Enable More... | |
| #define | PMC_IER_PCKRDY0 (0x1u << 8) |
| (PMC_IER) Programmable Clock Ready 0 Interrupt Enable More... | |
| #define | PMC_IER_PCKRDY1 (0x1u << 9) |
| (PMC_IER) Programmable Clock Ready 1 Interrupt Enable More... | |
| #define | PMC_IER_PCKRDY2 (0x1u << 10) |
| (PMC_IER) Programmable Clock Ready 2 Interrupt Enable More... | |
| #define | PMC_IER_PCKRDY3 (0x1u << 11) |
| (PMC_IER) Programmable Clock Ready 3 Interrupt Enable More... | |
| #define | PMC_IER_PCKRDY4 (0x1u << 12) |
| (PMC_IER) Programmable Clock Ready 4 Interrupt Enable More... | |
| #define | PMC_IER_PCKRDY5 (0x1u << 13) |
| (PMC_IER) Programmable Clock Ready 5 Interrupt Enable More... | |
| #define | PMC_IER_PCKRDY6 (0x1u << 14) |
| (PMC_IER) Programmable Clock Ready 6 Interrupt Enable More... | |
| #define | PMC_IER_PCKRDY7 (0x1u << 15) |
| (PMC_IER) Programmable Clock Ready 7 Interrupt Enable More... | |
| #define | PMC_IER_MOSCSELS (0x1u << 16) |
| (PMC_IER) Main Oscillator Selection Status Interrupt Enable More... | |
| #define | PMC_IER_MOSCRCS (0x1u << 17) |
| (PMC_IER) Main On-Chip RC Status Interrupt Enable More... | |
| #define | PMC_IER_CFDEV (0x1u << 18) |
| (PMC_IER) Clock Failure Detector Event Interrupt Enable More... | |
| #define | PMC_IDR_MOSCXTS (0x1u << 0) |
| (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable More... | |
| #define | PMC_IDR_LOCKA (0x1u << 1) |
| (PMC_IDR) PLLA Lock Interrupt Disable More... | |
| #define | PMC_IDR_LOCKB (0x1u << 2) |
| (PMC_IDR) PLLB Lock Interrupt Disable More... | |
| #define | PMC_IDR_MCKRDY (0x1u << 3) |
| (PMC_IDR) Master Clock Ready Interrupt Disable More... | |
| #define | PMC_IDR_PCKRDY0 (0x1u << 8) |
| (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable More... | |
| #define | PMC_IDR_PCKRDY1 (0x1u << 9) |
| (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable More... | |
| #define | PMC_IDR_PCKRDY2 (0x1u << 10) |
| (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable More... | |
| #define | PMC_IDR_PCKRDY3 (0x1u << 11) |
| (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable More... | |
| #define | PMC_IDR_PCKRDY4 (0x1u << 12) |
| (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable More... | |
| #define | PMC_IDR_PCKRDY5 (0x1u << 13) |
| (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable More... | |
| #define | PMC_IDR_PCKRDY6 (0x1u << 14) |
| (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable More... | |
| #define | PMC_IDR_PCKRDY7 (0x1u << 15) |
| (PMC_IDR) Programmable Clock Ready 7 Interrupt Disable More... | |
| #define | PMC_IDR_MOSCSELS (0x1u << 16) |
| (PMC_IDR) Main Oscillator Selection Status Interrupt Disable More... | |
| #define | PMC_IDR_MOSCRCS (0x1u << 17) |
| (PMC_IDR) Main On-Chip RC Status Interrupt Disable More... | |
| #define | PMC_IDR_CFDEV (0x1u << 18) |
| (PMC_IDR) Clock Failure Detector Event Interrupt Disable More... | |
| #define | PMC_SR_MOSCXTS (0x1u << 0) |
| (PMC_SR) Main XTAL Oscillator Status More... | |
| #define | PMC_SR_LOCKA (0x1u << 1) |
| (PMC_SR) PLLA Lock Status More... | |
| #define | PMC_SR_LOCKB (0x1u << 2) |
| (PMC_SR) PLLB Lock Status More... | |
| #define | PMC_SR_MCKRDY (0x1u << 3) |
| (PMC_SR) Master Clock Status More... | |
| #define | PMC_SR_OSCSELS (0x1u << 7) |
| (PMC_SR) Slow Clock Oscillator Selection More... | |
| #define | PMC_SR_PCKRDY0 (0x1u << 8) |
| (PMC_SR) Programmable Clock Ready Status More... | |
| #define | PMC_SR_PCKRDY1 (0x1u << 9) |
| (PMC_SR) Programmable Clock Ready Status More... | |
| #define | PMC_SR_PCKRDY2 (0x1u << 10) |
| (PMC_SR) Programmable Clock Ready Status More... | |
| #define | PMC_SR_PCKRDY3 (0x1u << 11) |
| (PMC_SR) Programmable Clock Ready Status More... | |
| #define | PMC_SR_PCKRDY4 (0x1u << 12) |
| (PMC_SR) Programmable Clock Ready Status More... | |
| #define | PMC_SR_PCKRDY5 (0x1u << 13) |
| (PMC_SR) Programmable Clock Ready Status More... | |
| #define | PMC_SR_PCKRDY6 (0x1u << 14) |
| (PMC_SR) Programmable Clock Ready Status More... | |
| #define | PMC_SR_PCKRDY7 (0x1u << 15) |
| (PMC_SR) Programmable Clock Ready Status More... | |
| #define | PMC_SR_MOSCSELS (0x1u << 16) |
| (PMC_SR) Main Oscillator Selection Status More... | |
| #define | PMC_SR_MOSCRCS (0x1u << 17) |
| (PMC_SR) Main On-Chip RC Oscillator Status More... | |
| #define | PMC_SR_CFDEV (0x1u << 18) |
| (PMC_SR) Clock Failure Detector Event More... | |
| #define | PMC_SR_CFDS (0x1u << 19) |
| (PMC_SR) Clock Failure Detector Status More... | |
| #define | PMC_SR_FOS (0x1u << 20) |
| (PMC_SR) Clock Failure Detector Fault Output Status More... | |
| #define | PMC_IMR_MOSCXTS (0x1u << 0) |
| (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask More... | |
| #define | PMC_IMR_LOCKA (0x1u << 1) |
| (PMC_IMR) PLLA Lock Interrupt Mask More... | |
| #define | PMC_IMR_LOCKB (0x1u << 2) |
| (PMC_IMR) PLLB Lock Interrupt Mask More... | |
| #define | PMC_IMR_MCKRDY (0x1u << 3) |
| (PMC_IMR) Master Clock Ready Interrupt Mask More... | |
| #define | PMC_IMR_PCKRDY0 (0x1u << 8) |
| (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask More... | |
| #define | PMC_IMR_PCKRDY1 (0x1u << 9) |
| (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask More... | |
| #define | PMC_IMR_PCKRDY2 (0x1u << 10) |
| (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask More... | |
| #define | PMC_IMR_MOSCSELS (0x1u << 16) |
| (PMC_IMR) Main Oscillator Selection Status Interrupt Mask More... | |
| #define | PMC_IMR_MOSCRCS (0x1u << 17) |
| (PMC_IMR) Main On-Chip RC Status Interrupt Mask More... | |
| #define | PMC_IMR_CFDEV (0x1u << 18) |
| (PMC_IMR) Clock Failure Detector Event Interrupt Mask More... | |
| #define | PMC_FSMR_FSTT0 (0x1u << 0) |
| (PMC_FSMR) Fast Startup Input Enable 0 More... | |
| #define | PMC_FSMR_FSTT1 (0x1u << 1) |
| (PMC_FSMR) Fast Startup Input Enable 1 More... | |
| #define | PMC_FSMR_FSTT2 (0x1u << 2) |
| (PMC_FSMR) Fast Startup Input Enable 2 More... | |
| #define | PMC_FSMR_FSTT3 (0x1u << 3) |
| (PMC_FSMR) Fast Startup Input Enable 3 More... | |
| #define | PMC_FSMR_FSTT4 (0x1u << 4) |
| (PMC_FSMR) Fast Startup Input Enable 4 More... | |
| #define | PMC_FSMR_FSTT5 (0x1u << 5) |
| (PMC_FSMR) Fast Startup Input Enable 5 More... | |
| #define | PMC_FSMR_FSTT6 (0x1u << 6) |
| (PMC_FSMR) Fast Startup Input Enable 6 More... | |
| #define | PMC_FSMR_FSTT7 (0x1u << 7) |
| (PMC_FSMR) Fast Startup Input Enable 7 More... | |
| #define | PMC_FSMR_FSTT8 (0x1u << 8) |
| (PMC_FSMR) Fast Startup Input Enable 8 More... | |
| #define | PMC_FSMR_FSTT9 (0x1u << 9) |
| (PMC_FSMR) Fast Startup Input Enable 9 More... | |
| #define | PMC_FSMR_FSTT10 (0x1u << 10) |
| (PMC_FSMR) Fast Startup Input Enable 10 More... | |
| #define | PMC_FSMR_FSTT11 (0x1u << 11) |
| (PMC_FSMR) Fast Startup Input Enable 11 More... | |
| #define | PMC_FSMR_FSTT12 (0x1u << 12) |
| (PMC_FSMR) Fast Startup Input Enable 12 More... | |
| #define | PMC_FSMR_FSTT13 (0x1u << 13) |
| (PMC_FSMR) Fast Startup Input Enable 13 More... | |
| #define | PMC_FSMR_FSTT14 (0x1u << 14) |
| (PMC_FSMR) Fast Startup Input Enable 14 More... | |
| #define | PMC_FSMR_FSTT15 (0x1u << 15) |
| (PMC_FSMR) Fast Startup Input Enable 15 More... | |
| #define | PMC_FSMR_RTTAL (0x1u << 16) |
| (PMC_FSMR) RTT Alarm Enable More... | |
| #define | PMC_FSMR_RTCAL (0x1u << 17) |
| (PMC_FSMR) RTC Alarm Enable More... | |
| #define | PMC_FSMR_USBAL (0x1u << 18) |
| (PMC_FSMR) USB Alarm Enable More... | |
| #define | PMC_FSMR_LPM (0x1u << 20) |
| (PMC_FSMR) Low-power Mode More... | |
| #define | PMC_FSMR_FLPM_Pos 21 |
| #define | PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) |
| (PMC_FSMR) Flash Low-power Mode More... | |
| #define | PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) |
| (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode More... | |
| #define | PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) |
| (PMC_FSMR) Flash is in deep-power-down mode when system enters Wait Mode More... | |
| #define | PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) |
| (PMC_FSMR) idle mode More... | |
| #define | PMC_FSPR_FSTP0 (0x1u << 0) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP1 (0x1u << 1) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP2 (0x1u << 2) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP3 (0x1u << 3) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP4 (0x1u << 4) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP5 (0x1u << 5) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP6 (0x1u << 6) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP7 (0x1u << 7) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP8 (0x1u << 8) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP9 (0x1u << 9) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP10 (0x1u << 10) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP11 (0x1u << 11) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP12 (0x1u << 12) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP13 (0x1u << 13) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP14 (0x1u << 14) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FSPR_FSTP15 (0x1u << 15) |
| (PMC_FSPR) Fast Startup Input Polarityx More... | |
| #define | PMC_FOCR_FOCLR (0x1u << 0) |
| (PMC_FOCR) Fault Output Clear More... | |
| #define | PMC_WPMR_WPEN (0x1u << 0) |
| (PMC_WPMR) Write Protection Enable More... | |
| #define | PMC_WPMR_WPKEY_Pos 8 |
| #define | PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) |
| (PMC_WPMR) Write Protection Key More... | |
| #define | PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) |
| (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. More... | |
| #define | PMC_WPSR_WPVS (0x1u << 0) |
| (PMC_WPSR) Write Protection Violation Status More... | |
| #define | PMC_WPSR_WPVSRC_Pos 8 |
| #define | PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) |
| (PMC_WPSR) Write Protection Violation Source More... | |
| #define | PMC_ADDRSIZE_ADDRSIZE_Pos 0 |
| #define | PMC_ADDRSIZE_ADDRSIZE_Msk (0xffffu << PMC_ADDRSIZE_ADDRSIZE_Pos) |
| (PMC_ADDRSIZE) Peripheral Bus Address Area Size More... | |
| #define | PMC_IPNAME_IPNAME_Pos 0 |
| #define | PMC_IPNAME_IPNAME_Msk (0xffffffffu << PMC_IPNAME_IPNAME_Pos) |
| (PMC_IPNAME[2]) IP Name in ASCII Format More... | |
| #define | PMC_VERSION_VERSION_Pos 0 |
| #define | PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) |
| (PMC_VERSION) Version of the Hardware Module More... | |
| #define | PMC_VERSION_MFN_Pos 16 |
| #define | PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) |
| (PMC_VERSION) Metal Fix Number More... | |
| #define | PMC_PCER1_PID32 (0x1u << 0) |
| (PMC_PCER1) Peripheral Clock 32 Enable More... | |
| #define | PMC_PCER1_PID33 (0x1u << 1) |
| (PMC_PCER1) Peripheral Clock 33 Enable More... | |
| #define | PMC_PCER1_PID34 (0x1u << 2) |
| (PMC_PCER1) Peripheral Clock 34 Enable More... | |
| #define | PMC_PCER1_PID35 (0x1u << 3) |
| (PMC_PCER1) Peripheral Clock 35 Enable More... | |
| #define | PMC_PCER1_PID36 (0x1u << 4) |
| (PMC_PCER1) Peripheral Clock 36 Enable More... | |
| #define | PMC_PCER1_PID37 (0x1u << 5) |
| (PMC_PCER1) Peripheral Clock 37 Enable More... | |
| #define | PMC_PCER1_PID38 (0x1u << 6) |
| (PMC_PCER1) Peripheral Clock 38 Enable More... | |
| #define | PMC_PCER1_PID39 (0x1u << 7) |
| (PMC_PCER1) Peripheral Clock 39 Enable More... | |
| #define | PMC_PCER1_PID40 (0x1u << 8) |
| (PMC_PCER1) Peripheral Clock 40 Enable More... | |
| #define | PMC_PCER1_PID41 (0x1u << 9) |
| (PMC_PCER1) Peripheral Clock 41 Enable More... | |
| #define | PMC_PCER1_PID42 (0x1u << 10) |
| (PMC_PCER1) Peripheral Clock 42 Enable More... | |
| #define | PMC_PCER1_PID43 (0x1u << 11) |
| (PMC_PCER1) Peripheral Clock 43 Enable More... | |
| #define | PMC_PCER1_PID44 (0x1u << 12) |
| (PMC_PCER1) Peripheral Clock 44 Enable More... | |
| #define | PMC_PCER1_PID45 (0x1u << 13) |
| (PMC_PCER1) Peripheral Clock 45 Enable More... | |
| #define | PMC_PCER1_PID46 (0x1u << 14) |
| (PMC_PCER1) Peripheral Clock 46 Enable More... | |
| #define | PMC_PCER1_PID47 (0x1u << 15) |
| (PMC_PCER1) Peripheral Clock 47 Enable More... | |
| #define | PMC_PCER1_PID48 (0x1u << 16) |
| (PMC_PCER1) Peripheral Clock 48 Enable More... | |
| #define | PMC_PCER1_PID49 (0x1u << 17) |
| (PMC_PCER1) Peripheral Clock 49 Enable More... | |
| #define | PMC_PCDR1_PID32 (0x1u << 0) |
| (PMC_PCDR1) Peripheral Clock 32 Disable More... | |
| #define | PMC_PCDR1_PID33 (0x1u << 1) |
| (PMC_PCDR1) Peripheral Clock 33 Disable More... | |
| #define | PMC_PCDR1_PID34 (0x1u << 2) |
| (PMC_PCDR1) Peripheral Clock 34 Disable More... | |
| #define | PMC_PCDR1_PID35 (0x1u << 3) |
| (PMC_PCDR1) Peripheral Clock 35 Disable More... | |
| #define | PMC_PCDR1_PID36 (0x1u << 4) |
| (PMC_PCDR1) Peripheral Clock 36 Disable More... | |
| #define | PMC_PCDR1_PID37 (0x1u << 5) |
| (PMC_PCDR1) Peripheral Clock 37 Disable More... | |
| #define | PMC_PCDR1_PID38 (0x1u << 6) |
| (PMC_PCDR1) Peripheral Clock 38 Disable More... | |
| #define | PMC_PCDR1_PID39 (0x1u << 7) |
| (PMC_PCDR1) Peripheral Clock 39 Disable More... | |
| #define | PMC_PCDR1_PID40 (0x1u << 8) |
| (PMC_PCDR1) Peripheral Clock 40 Disable More... | |
| #define | PMC_PCDR1_PID41 (0x1u << 9) |
| (PMC_PCDR1) Peripheral Clock 41 Disable More... | |
| #define | PMC_PCDR1_PID42 (0x1u << 10) |
| (PMC_PCDR1) Peripheral Clock 42 Disable More... | |
| #define | PMC_PCDR1_PID43 (0x1u << 11) |
| (PMC_PCDR1) Peripheral Clock 43 Disable More... | |
| #define | PMC_PCDR1_PID44 (0x1u << 12) |
| (PMC_PCDR1) Peripheral Clock 44 Disable More... | |
| #define | PMC_PCDR1_PID45 (0x1u << 13) |
| (PMC_PCDR1) Peripheral Clock 45 Disable More... | |
| #define | PMC_PCDR1_PID46 (0x1u << 14) |
| (PMC_PCDR1) Peripheral Clock 46 Disable More... | |
| #define | PMC_PCDR1_PID47 (0x1u << 15) |
| (PMC_PCDR1) Peripheral Clock 47 Disable More... | |
| #define | PMC_PCDR1_PID48 (0x1u << 16) |
| (PMC_PCDR1) Peripheral Clock 48 Disable More... | |
| #define | PMC_PCDR1_PID49 (0x1u << 17) |
| (PMC_PCDR1) Peripheral Clock 49 Disable More... | |
| #define | PMC_PCSR1_PID32 (0x1u << 0) |
| (PMC_PCSR1) Peripheral Clock 32 Status More... | |
| #define | PMC_PCSR1_PID33 (0x1u << 1) |
| (PMC_PCSR1) Peripheral Clock 33 Status More... | |
| #define | PMC_PCSR1_PID34 (0x1u << 2) |
| (PMC_PCSR1) Peripheral Clock 34 Status More... | |
| #define | PMC_PCSR1_PID35 (0x1u << 3) |
| (PMC_PCSR1) Peripheral Clock 35 Status More... | |
| #define | PMC_PCSR1_PID36 (0x1u << 4) |
| (PMC_PCSR1) Peripheral Clock 36 Status More... | |
| #define | PMC_PCSR1_PID37 (0x1u << 5) |
| (PMC_PCSR1) Peripheral Clock 37 Status More... | |
| #define | PMC_PCSR1_PID38 (0x1u << 6) |
| (PMC_PCSR1) Peripheral Clock 38 Status More... | |
| #define | PMC_PCSR1_PID39 (0x1u << 7) |
| (PMC_PCSR1) Peripheral Clock 39 Status More... | |
| #define | PMC_PCSR1_PID40 (0x1u << 8) |
| (PMC_PCSR1) Peripheral Clock 40 Status More... | |
| #define | PMC_PCSR1_PID41 (0x1u << 9) |
| (PMC_PCSR1) Peripheral Clock 41 Status More... | |
| #define | PMC_PCSR1_PID42 (0x1u << 10) |
| (PMC_PCSR1) Peripheral Clock 42 Status More... | |
| #define | PMC_PCSR1_PID43 (0x1u << 11) |
| (PMC_PCSR1) Peripheral Clock 43 Status More... | |
| #define | PMC_PCSR1_PID44 (0x1u << 12) |
| (PMC_PCSR1) Peripheral Clock 44 Status More... | |
| #define | PMC_PCSR1_PID45 (0x1u << 13) |
| (PMC_PCSR1) Peripheral Clock 45 Status More... | |
| #define | PMC_PCSR1_PID46 (0x1u << 14) |
| (PMC_PCSR1) Peripheral Clock 46 Status More... | |
| #define | PMC_PCSR1_PID47 (0x1u << 15) |
| (PMC_PCSR1) Peripheral Clock 47 Status More... | |
| #define | PMC_PCSR1_PID48 (0x1u << 16) |
| (PMC_PCSR1) Peripheral Clock 48 Status More... | |
| #define | PMC_PCSR1_PID49 (0x1u << 17) |
| (PMC_PCSR1) Peripheral Clock 49 Status More... | |
| #define | PMC_OCR_CAL8_Pos 0 |
| #define | PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) |
| (PMC_OCR) RC Oscillator Calibration bits for 8 MHz More... | |
| #define | PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) |
| #define | PMC_OCR_SEL8 (0x1u << 7) |
| (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz More... | |
| #define | PMC_OCR_CAL16_Pos 8 |
| #define | PMC_OCR_CAL16_Msk (0x7fu << PMC_OCR_CAL16_Pos) |
| (PMC_OCR) RC Oscillator Calibration bits for 16 MHz More... | |
| #define | PMC_OCR_CAL16(value) ((PMC_OCR_CAL16_Msk & ((value) << PMC_OCR_CAL16_Pos))) |
| #define | PMC_OCR_SEL16 (0x1u << 15) |
| (PMC_OCR) Selection of RC Oscillator Calibration bits for 16 MHz More... | |
| #define | PMC_OCR_CAL24_Pos 16 |
| #define | PMC_OCR_CAL24_Msk (0x7fu << PMC_OCR_CAL24_Pos) |
| (PMC_OCR) RC Oscillator Calibration bits for 24 MHz More... | |
| #define | PMC_OCR_CAL24(value) ((PMC_OCR_CAL24_Msk & ((value) << PMC_OCR_CAL24_Pos))) |
| #define | PMC_OCR_SEL24 (0x1u << 23) |
| (PMC_OCR) Selection of RC Oscillator Calibration bits for 24 MHz More... | |
| #define | PMC_SLPWK_ER0_PID8 (0x1u << 8) |
| (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID9 (0x1u << 9) |
| (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID10 (0x1u << 10) |
| (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID11 (0x1u << 11) |
| (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID12 (0x1u << 12) |
| (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID13 (0x1u << 13) |
| (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID14 (0x1u << 14) |
| (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID15 (0x1u << 15) |
| (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID16 (0x1u << 16) |
| (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID17 (0x1u << 17) |
| (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID18 (0x1u << 18) |
| (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID19 (0x1u << 19) |
| (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID20 (0x1u << 20) |
| (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID21 (0x1u << 21) |
| (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID22 (0x1u << 22) |
| (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID23 (0x1u << 23) |
| (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID24 (0x1u << 24) |
| (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID25 (0x1u << 25) |
| (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID26 (0x1u << 26) |
| (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID27 (0x1u << 27) |
| (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID28 (0x1u << 28) |
| (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable More... | |
| #define | PMC_SLPWK_ER0_PID29 (0x1u << 29) |
| (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable More... | |
| #define | PMC_SLPWK_DR0_PID8 (0x1u << 8) |
| (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID9 (0x1u << 9) |
| (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID10 (0x1u << 10) |
| (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID11 (0x1u << 11) |
| (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID12 (0x1u << 12) |
| (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID13 (0x1u << 13) |
| (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID14 (0x1u << 14) |
| (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID15 (0x1u << 15) |
| (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID16 (0x1u << 16) |
| (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID17 (0x1u << 17) |
| (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID18 (0x1u << 18) |
| (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID19 (0x1u << 19) |
| (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID20 (0x1u << 20) |
| (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID21 (0x1u << 21) |
| (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID22 (0x1u << 22) |
| (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID23 (0x1u << 23) |
| (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID24 (0x1u << 24) |
| (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID25 (0x1u << 25) |
| (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID26 (0x1u << 26) |
| (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID27 (0x1u << 27) |
| (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID28 (0x1u << 28) |
| (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable More... | |
| #define | PMC_SLPWK_DR0_PID29 (0x1u << 29) |
| (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable More... | |
| #define | PMC_SLPWK_SR0_PID8 (0x1u << 8) |
| (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID9 (0x1u << 9) |
| (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID10 (0x1u << 10) |
| (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID11 (0x1u << 11) |
| (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID12 (0x1u << 12) |
| (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID13 (0x1u << 13) |
| (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID14 (0x1u << 14) |
| (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID15 (0x1u << 15) |
| (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID16 (0x1u << 16) |
| (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID17 (0x1u << 17) |
| (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID18 (0x1u << 18) |
| (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID19 (0x1u << 19) |
| (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID20 (0x1u << 20) |
| (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID21 (0x1u << 21) |
| (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID22 (0x1u << 22) |
| (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID23 (0x1u << 23) |
| (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID24 (0x1u << 24) |
| (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID25 (0x1u << 25) |
| (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID26 (0x1u << 26) |
| (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID27 (0x1u << 27) |
| (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID28 (0x1u << 28) |
| (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status More... | |
| #define | PMC_SLPWK_SR0_PID29 (0x1u << 29) |
| (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status More... | |
| #define | PMC_SLPWK_ASR0_PID8 (0x1u << 8) |
| (PMC_SLPWK_ASR0) Peripheral 8 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID9 (0x1u << 9) |
| (PMC_SLPWK_ASR0) Peripheral 9 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID10 (0x1u << 10) |
| (PMC_SLPWK_ASR0) Peripheral 10 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID11 (0x1u << 11) |
| (PMC_SLPWK_ASR0) Peripheral 11 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID12 (0x1u << 12) |
| (PMC_SLPWK_ASR0) Peripheral 12 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID13 (0x1u << 13) |
| (PMC_SLPWK_ASR0) Peripheral 13 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID14 (0x1u << 14) |
| (PMC_SLPWK_ASR0) Peripheral 14 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID15 (0x1u << 15) |
| (PMC_SLPWK_ASR0) Peripheral 15 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID16 (0x1u << 16) |
| (PMC_SLPWK_ASR0) Peripheral 16 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID17 (0x1u << 17) |
| (PMC_SLPWK_ASR0) Peripheral 17 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID18 (0x1u << 18) |
| (PMC_SLPWK_ASR0) Peripheral 18 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID19 (0x1u << 19) |
| (PMC_SLPWK_ASR0) Peripheral 19 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID20 (0x1u << 20) |
| (PMC_SLPWK_ASR0) Peripheral 20 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID21 (0x1u << 21) |
| (PMC_SLPWK_ASR0) Peripheral 21 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID22 (0x1u << 22) |
| (PMC_SLPWK_ASR0) Peripheral 22 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID23 (0x1u << 23) |
| (PMC_SLPWK_ASR0) Peripheral 23 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID24 (0x1u << 24) |
| (PMC_SLPWK_ASR0) Peripheral 24 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID25 (0x1u << 25) |
| (PMC_SLPWK_ASR0) Peripheral 25 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID26 (0x1u << 26) |
| (PMC_SLPWK_ASR0) Peripheral 26 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID27 (0x1u << 27) |
| (PMC_SLPWK_ASR0) Peripheral 27 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID28 (0x1u << 28) |
| (PMC_SLPWK_ASR0) Peripheral 28 Activity Status More... | |
| #define | PMC_SLPWK_ASR0_PID29 (0x1u << 29) |
| (PMC_SLPWK_ASR0) Peripheral 29 Activity Status More... | |
| #define | PMC_PMMR_PLLA_MMAX_Pos 0 |
| #define | PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) |
| (PMC_PMMR) PLLA Maximum Allowed Multiplier Value More... | |
| #define | PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos))) |
SOFTWARE API DEFINITION FOR Power Management Controller.
| #define CKGR_MCFR_MAINF | ( | value | ) | ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) |
| #define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) |
(CKGR_MCFR) Main Clock Frequency
| #define CKGR_MCFR_MAINF_Pos 0 |
| #define CKGR_MCFR_MAINFRDY (0x1u << 16) |
(CKGR_MCFR) Main Clock Ready
| #define CKGR_MCFR_RCMEAS (0x1u << 20) |
(CKGR_MCFR) RC Oscillator Frequency Measure (write-only)
| #define CKGR_MOR_CFDEN (0x1u << 25) |
(CKGR_MOR) Clock Failure Detector Enable
| #define CKGR_MOR_KEY | ( | value | ) | ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) |
| #define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) |
(CKGR_MOR) Write Access Password
| #define CKGR_MOR_KEY_PASSWD (0x37u << 16) |
(CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0.
| #define CKGR_MOR_KEY_Pos 16 |
| #define CKGR_MOR_MOSCRCEN (0x1u << 3) |
(CKGR_MOR) Main On-Chip RC Oscillator Enable
| #define CKGR_MOR_MOSCRCF_16_MHz (0x1u << 4) |
(CKGR_MOR) The Fast RC Oscillator Frequency is at 16 MHz
| #define CKGR_MOR_MOSCRCF_24_MHz (0x2u << 4) |
(CKGR_MOR) The Fast RC Oscillator Frequency is at 24 MHz
| #define CKGR_MOR_MOSCRCF_8_MHz (0x0u << 4) |
(CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz (default)
| #define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) |
(CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection
| #define CKGR_MOR_MOSCRCF_Pos 4 |
| #define CKGR_MOR_MOSCSEL (0x1u << 24) |
(CKGR_MOR) Main Oscillator Selection
| #define CKGR_MOR_MOSCXTBY (0x1u << 1) |
(CKGR_MOR) Main Crystal Oscillator Bypass
| #define CKGR_MOR_MOSCXTEN (0x1u << 0) |
(CKGR_MOR) Main Crystal Oscillator Enable
| #define CKGR_MOR_MOSCXTST | ( | value | ) | ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) |
| #define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) |
(CKGR_MOR) Main Crystal Oscillator Start-up Time
| #define CKGR_MOR_MOSCXTST_Pos 8 |
| #define CKGR_MOR_WAITMODE (0x1u << 2) |
(CKGR_MOR) Wait Mode Command
| #define CKGR_PLLAR_MULA | ( | value | ) | ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) |
| #define CKGR_PLLAR_MULA_Msk (0x1fffu << CKGR_PLLAR_MULA_Pos) |
(CKGR_PLLAR) PLLA Multiplier
| #define CKGR_PLLAR_MULA_Pos 16 |
| #define CKGR_PLLAR_PLLACOUNT | ( | value | ) | ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) |
| #define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) |
(CKGR_PLLAR) PLLA Counter
| #define CKGR_PLLAR_PLLACOUNT_Pos 8 |
| #define CKGR_PLLAR_PLLAEN | ( | value | ) | ((CKGR_PLLAR_PLLAEN_Msk & ((value) << CKGR_PLLAR_PLLAEN_Pos))) |
| #define CKGR_PLLAR_PLLAEN_Msk (0xffu << CKGR_PLLAR_PLLAEN_Pos) |
(CKGR_PLLAR) PLLA Control
| #define CKGR_PLLAR_PLLAEN_Pos 0 |
| #define CKGR_PLLBR_MULB | ( | value | ) | ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos))) |
| #define CKGR_PLLBR_MULB_Msk (0xfffu << CKGR_PLLBR_MULB_Pos) |
(CKGR_PLLBR) PLLB Multiplier
| #define CKGR_PLLBR_MULB_Pos 16 |
| #define CKGR_PLLBR_PLLBCOUNT | ( | value | ) | ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos))) |
| #define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) |
(CKGR_PLLBR) PLLB Counter
| #define CKGR_PLLBR_PLLBCOUNT_Pos 8 |
| #define CKGR_PLLBR_PLLBEN | ( | value | ) | ((CKGR_PLLBR_PLLBEN_Msk & ((value) << CKGR_PLLBR_PLLBEN_Pos))) |
| #define CKGR_PLLBR_PLLBEN_Msk (0xffu << CKGR_PLLBR_PLLBEN_Pos) |
(CKGR_PLLBR) PLLB Control
| #define CKGR_PLLBR_PLLBEN_Pos 0 |
| #define PMC_ADDRSIZE_ADDRSIZE_Msk (0xffffu << PMC_ADDRSIZE_ADDRSIZE_Pos) |
(PMC_ADDRSIZE) Peripheral Bus Address Area Size
| #define PMC_ADDRSIZE_ADDRSIZE_Pos 0 |
| #define PMC_FOCR_FOCLR (0x1u << 0) |
(PMC_FOCR) Fault Output Clear
| #define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) |
(PMC_FSMR) Flash is in deep-power-down mode when system enters Wait Mode
| #define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) |
(PMC_FSMR) idle mode
| #define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) |
(PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode
| #define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) |
(PMC_FSMR) Flash Low-power Mode
| #define PMC_FSMR_FLPM_Pos 21 |
| #define PMC_FSMR_FSTT0 (0x1u << 0) |
(PMC_FSMR) Fast Startup Input Enable 0
| #define PMC_FSMR_FSTT1 (0x1u << 1) |
(PMC_FSMR) Fast Startup Input Enable 1
| #define PMC_FSMR_FSTT10 (0x1u << 10) |
(PMC_FSMR) Fast Startup Input Enable 10
| #define PMC_FSMR_FSTT11 (0x1u << 11) |
(PMC_FSMR) Fast Startup Input Enable 11
| #define PMC_FSMR_FSTT12 (0x1u << 12) |
(PMC_FSMR) Fast Startup Input Enable 12
| #define PMC_FSMR_FSTT13 (0x1u << 13) |
(PMC_FSMR) Fast Startup Input Enable 13
| #define PMC_FSMR_FSTT14 (0x1u << 14) |
(PMC_FSMR) Fast Startup Input Enable 14
| #define PMC_FSMR_FSTT15 (0x1u << 15) |
(PMC_FSMR) Fast Startup Input Enable 15
| #define PMC_FSMR_FSTT2 (0x1u << 2) |
(PMC_FSMR) Fast Startup Input Enable 2
| #define PMC_FSMR_FSTT3 (0x1u << 3) |
(PMC_FSMR) Fast Startup Input Enable 3
| #define PMC_FSMR_FSTT4 (0x1u << 4) |
(PMC_FSMR) Fast Startup Input Enable 4
| #define PMC_FSMR_FSTT5 (0x1u << 5) |
(PMC_FSMR) Fast Startup Input Enable 5
| #define PMC_FSMR_FSTT6 (0x1u << 6) |
(PMC_FSMR) Fast Startup Input Enable 6
| #define PMC_FSMR_FSTT7 (0x1u << 7) |
(PMC_FSMR) Fast Startup Input Enable 7
| #define PMC_FSMR_FSTT8 (0x1u << 8) |
(PMC_FSMR) Fast Startup Input Enable 8
| #define PMC_FSMR_FSTT9 (0x1u << 9) |
(PMC_FSMR) Fast Startup Input Enable 9
| #define PMC_FSMR_LPM (0x1u << 20) |
(PMC_FSMR) Low-power Mode
| #define PMC_FSMR_RTCAL (0x1u << 17) |
(PMC_FSMR) RTC Alarm Enable
| #define PMC_FSMR_RTTAL (0x1u << 16) |
(PMC_FSMR) RTT Alarm Enable
| #define PMC_FSMR_USBAL (0x1u << 18) |
(PMC_FSMR) USB Alarm Enable
| #define PMC_FSPR_FSTP0 (0x1u << 0) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP1 (0x1u << 1) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP10 (0x1u << 10) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP11 (0x1u << 11) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP12 (0x1u << 12) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP13 (0x1u << 13) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP14 (0x1u << 14) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP15 (0x1u << 15) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP2 (0x1u << 2) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP3 (0x1u << 3) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP4 (0x1u << 4) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP5 (0x1u << 5) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP6 (0x1u << 6) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP7 (0x1u << 7) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP8 (0x1u << 8) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_FSPR_FSTP9 (0x1u << 9) |
(PMC_FSPR) Fast Startup Input Polarityx
| #define PMC_IDR_CFDEV (0x1u << 18) |
(PMC_IDR) Clock Failure Detector Event Interrupt Disable
| #define PMC_IDR_LOCKA (0x1u << 1) |
(PMC_IDR) PLLA Lock Interrupt Disable
| #define PMC_IDR_LOCKB (0x1u << 2) |
(PMC_IDR) PLLB Lock Interrupt Disable
| #define PMC_IDR_MCKRDY (0x1u << 3) |
(PMC_IDR) Master Clock Ready Interrupt Disable
| #define PMC_IDR_MOSCRCS (0x1u << 17) |
(PMC_IDR) Main On-Chip RC Status Interrupt Disable
| #define PMC_IDR_MOSCSELS (0x1u << 16) |
(PMC_IDR) Main Oscillator Selection Status Interrupt Disable
| #define PMC_IDR_MOSCXTS (0x1u << 0) |
(PMC_IDR) Main Crystal Oscillator Status Interrupt Disable
| #define PMC_IDR_PCKRDY0 (0x1u << 8) |
(PMC_IDR) Programmable Clock Ready 0 Interrupt Disable
| #define PMC_IDR_PCKRDY1 (0x1u << 9) |
(PMC_IDR) Programmable Clock Ready 1 Interrupt Disable
| #define PMC_IDR_PCKRDY2 (0x1u << 10) |
(PMC_IDR) Programmable Clock Ready 2 Interrupt Disable
| #define PMC_IDR_PCKRDY3 (0x1u << 11) |
(PMC_IDR) Programmable Clock Ready 3 Interrupt Disable
| #define PMC_IDR_PCKRDY4 (0x1u << 12) |
(PMC_IDR) Programmable Clock Ready 4 Interrupt Disable
| #define PMC_IDR_PCKRDY5 (0x1u << 13) |
(PMC_IDR) Programmable Clock Ready 5 Interrupt Disable
| #define PMC_IDR_PCKRDY6 (0x1u << 14) |
(PMC_IDR) Programmable Clock Ready 6 Interrupt Disable
| #define PMC_IDR_PCKRDY7 (0x1u << 15) |
(PMC_IDR) Programmable Clock Ready 7 Interrupt Disable
| #define PMC_IER_CFDEV (0x1u << 18) |
(PMC_IER) Clock Failure Detector Event Interrupt Enable
| #define PMC_IER_LOCKA (0x1u << 1) |
(PMC_IER) PLLA Lock Interrupt Enable
| #define PMC_IER_LOCKB (0x1u << 2) |
(PMC_IER) PLLB Lock Interrupt Enable
| #define PMC_IER_MCKRDY (0x1u << 3) |
(PMC_IER) Master Clock Ready Interrupt Enable
| #define PMC_IER_MOSCRCS (0x1u << 17) |
(PMC_IER) Main On-Chip RC Status Interrupt Enable
| #define PMC_IER_MOSCSELS (0x1u << 16) |
(PMC_IER) Main Oscillator Selection Status Interrupt Enable
| #define PMC_IER_MOSCXTS (0x1u << 0) |
(PMC_IER) Main Crystal Oscillator Status Interrupt Enable
| #define PMC_IER_PCKRDY0 (0x1u << 8) |
(PMC_IER) Programmable Clock Ready 0 Interrupt Enable
| #define PMC_IER_PCKRDY1 (0x1u << 9) |
(PMC_IER) Programmable Clock Ready 1 Interrupt Enable
| #define PMC_IER_PCKRDY2 (0x1u << 10) |
(PMC_IER) Programmable Clock Ready 2 Interrupt Enable
| #define PMC_IER_PCKRDY3 (0x1u << 11) |
(PMC_IER) Programmable Clock Ready 3 Interrupt Enable
| #define PMC_IER_PCKRDY4 (0x1u << 12) |
(PMC_IER) Programmable Clock Ready 4 Interrupt Enable
| #define PMC_IER_PCKRDY5 (0x1u << 13) |
(PMC_IER) Programmable Clock Ready 5 Interrupt Enable
| #define PMC_IER_PCKRDY6 (0x1u << 14) |
(PMC_IER) Programmable Clock Ready 6 Interrupt Enable
| #define PMC_IER_PCKRDY7 (0x1u << 15) |
(PMC_IER) Programmable Clock Ready 7 Interrupt Enable
| #define PMC_IMR_CFDEV (0x1u << 18) |
(PMC_IMR) Clock Failure Detector Event Interrupt Mask
| #define PMC_IMR_LOCKA (0x1u << 1) |
(PMC_IMR) PLLA Lock Interrupt Mask
| #define PMC_IMR_LOCKB (0x1u << 2) |
(PMC_IMR) PLLB Lock Interrupt Mask
| #define PMC_IMR_MCKRDY (0x1u << 3) |
(PMC_IMR) Master Clock Ready Interrupt Mask
| #define PMC_IMR_MOSCRCS (0x1u << 17) |
(PMC_IMR) Main On-Chip RC Status Interrupt Mask
| #define PMC_IMR_MOSCSELS (0x1u << 16) |
(PMC_IMR) Main Oscillator Selection Status Interrupt Mask
| #define PMC_IMR_MOSCXTS (0x1u << 0) |
(PMC_IMR) Main Crystal Oscillator Status Interrupt Mask
| #define PMC_IMR_PCKRDY0 (0x1u << 8) |
(PMC_IMR) Programmable Clock Ready 0 Interrupt Mask
| #define PMC_IMR_PCKRDY1 (0x1u << 9) |
(PMC_IMR) Programmable Clock Ready 1 Interrupt Mask
| #define PMC_IMR_PCKRDY2 (0x1u << 10) |
(PMC_IMR) Programmable Clock Ready 2 Interrupt Mask
| #define PMC_IPNAME_IPNAME_Msk (0xffffffffu << PMC_IPNAME_IPNAME_Pos) |
(PMC_IPNAME[2]) IP Name in ASCII Format
| #define PMC_IPNAME_IPNAME_Pos 0 |
| #define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) |
(PMC_MCKR) Main Clock is selected
| #define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) |
(PMC_MCKR) Master Clock Source Selection
| #define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) |
(PMC_MCKR) PLLA Clock is selected
| #define PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) |
(PMC_MCKR) PLLA Clock is selected
| #define PMC_MCKR_CSS_Pos 0 |
| #define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) |
(PMC_MCKR) Slow Clock is selected
| #define PMC_MCKR_PLLADIV2 (0x1u << 12) |
(PMC_MCKR) PLLA Divisor by 2
| #define PMC_MCKR_PLLBDIV2 (0x1u << 13) |
(PMC_MCKR) PLLB Divisor by 2
| #define PMC_MCKR_PRES_CLK_1 (0x0u << 4) |
(PMC_MCKR) Selected clock
| #define PMC_MCKR_PRES_CLK_16 (0x4u << 4) |
(PMC_MCKR) Selected clock divided by 16
| #define PMC_MCKR_PRES_CLK_2 (0x1u << 4) |
(PMC_MCKR) Selected clock divided by 2
| #define PMC_MCKR_PRES_CLK_3 (0x7u << 4) |
(PMC_MCKR) Selected clock divided by 3
| #define PMC_MCKR_PRES_CLK_32 (0x5u << 4) |
(PMC_MCKR) Selected clock divided by 32
| #define PMC_MCKR_PRES_CLK_4 (0x2u << 4) |
(PMC_MCKR) Selected clock divided by 4
| #define PMC_MCKR_PRES_CLK_64 (0x6u << 4) |
(PMC_MCKR) Selected clock divided by 64
| #define PMC_MCKR_PRES_CLK_8 (0x3u << 4) |
(PMC_MCKR) Selected clock divided by 8
| #define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) |
(PMC_MCKR) Processor Clock Prescaler
| #define PMC_MCKR_PRES_Pos 4 |
| #define PMC_OCR_CAL16 | ( | value | ) | ((PMC_OCR_CAL16_Msk & ((value) << PMC_OCR_CAL16_Pos))) |
| #define PMC_OCR_CAL16_Msk (0x7fu << PMC_OCR_CAL16_Pos) |
(PMC_OCR) RC Oscillator Calibration bits for 16 MHz
| #define PMC_OCR_CAL16_Pos 8 |
| #define PMC_OCR_CAL24 | ( | value | ) | ((PMC_OCR_CAL24_Msk & ((value) << PMC_OCR_CAL24_Pos))) |
| #define PMC_OCR_CAL24_Msk (0x7fu << PMC_OCR_CAL24_Pos) |
(PMC_OCR) RC Oscillator Calibration bits for 24 MHz
| #define PMC_OCR_CAL24_Pos 16 |
| #define PMC_OCR_CAL8 | ( | value | ) | ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) |
| #define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) |
(PMC_OCR) RC Oscillator Calibration bits for 8 MHz
| #define PMC_OCR_CAL8_Pos 0 |
| #define PMC_OCR_SEL16 (0x1u << 15) |
(PMC_OCR) Selection of RC Oscillator Calibration bits for 16 MHz
| #define PMC_OCR_SEL24 (0x1u << 23) |
(PMC_OCR) Selection of RC Oscillator Calibration bits for 24 MHz
| #define PMC_OCR_SEL8 (0x1u << 7) |
(PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz
| #define PMC_PCDR0_PID10 (0x1u << 10) |
(PMC_PCDR0) Peripheral Clock 10 Disable
| #define PMC_PCDR0_PID11 (0x1u << 11) |
(PMC_PCDR0) Peripheral Clock 11 Disable
| #define PMC_PCDR0_PID12 (0x1u << 12) |
(PMC_PCDR0) Peripheral Clock 12 Disable
| #define PMC_PCDR0_PID13 (0x1u << 13) |
(PMC_PCDR0) Peripheral Clock 13 Disable
| #define PMC_PCDR0_PID14 (0x1u << 14) |
(PMC_PCDR0) Peripheral Clock 14 Disable
| #define PMC_PCDR0_PID15 (0x1u << 15) |
(PMC_PCDR0) Peripheral Clock 15 Disable
| #define PMC_PCDR0_PID16 (0x1u << 16) |
(PMC_PCDR0) Peripheral Clock 16 Disable
| #define PMC_PCDR0_PID17 (0x1u << 17) |
(PMC_PCDR0) Peripheral Clock 17 Disable
| #define PMC_PCDR0_PID18 (0x1u << 18) |
(PMC_PCDR0) Peripheral Clock 18 Disable
| #define PMC_PCDR0_PID19 (0x1u << 19) |
(PMC_PCDR0) Peripheral Clock 19 Disable
| #define PMC_PCDR0_PID20 (0x1u << 20) |
(PMC_PCDR0) Peripheral Clock 20 Disable
| #define PMC_PCDR0_PID21 (0x1u << 21) |
(PMC_PCDR0) Peripheral Clock 21 Disable
| #define PMC_PCDR0_PID22 (0x1u << 22) |
(PMC_PCDR0) Peripheral Clock 22 Disable
| #define PMC_PCDR0_PID23 (0x1u << 23) |
(PMC_PCDR0) Peripheral Clock 23 Disable
| #define PMC_PCDR0_PID24 (0x1u << 24) |
(PMC_PCDR0) Peripheral Clock 24 Disable
| #define PMC_PCDR0_PID25 (0x1u << 25) |
(PMC_PCDR0) Peripheral Clock 25 Disable
| #define PMC_PCDR0_PID26 (0x1u << 26) |
(PMC_PCDR0) Peripheral Clock 26 Disable
| #define PMC_PCDR0_PID27 (0x1u << 27) |
(PMC_PCDR0) Peripheral Clock 27 Disable
| #define PMC_PCDR0_PID28 (0x1u << 28) |
(PMC_PCDR0) Peripheral Clock 28 Disable
| #define PMC_PCDR0_PID29 (0x1u << 29) |
(PMC_PCDR0) Peripheral Clock 29 Disable
| #define PMC_PCDR0_PID30 (0x1u << 30) |
(PMC_PCDR0) Peripheral Clock 30 Disable
| #define PMC_PCDR0_PID31 (0x1u << 31) |
(PMC_PCDR0) Peripheral Clock 31 Disable
| #define PMC_PCDR0_PID8 (0x1u << 8) |
(PMC_PCDR0) Peripheral Clock 8 Disable
| #define PMC_PCDR0_PID9 (0x1u << 9) |
(PMC_PCDR0) Peripheral Clock 9 Disable
| #define PMC_PCDR1_PID32 (0x1u << 0) |
(PMC_PCDR1) Peripheral Clock 32 Disable
| #define PMC_PCDR1_PID33 (0x1u << 1) |
(PMC_PCDR1) Peripheral Clock 33 Disable
| #define PMC_PCDR1_PID34 (0x1u << 2) |
(PMC_PCDR1) Peripheral Clock 34 Disable
| #define PMC_PCDR1_PID35 (0x1u << 3) |
(PMC_PCDR1) Peripheral Clock 35 Disable
| #define PMC_PCDR1_PID36 (0x1u << 4) |
(PMC_PCDR1) Peripheral Clock 36 Disable
| #define PMC_PCDR1_PID37 (0x1u << 5) |
(PMC_PCDR1) Peripheral Clock 37 Disable
| #define PMC_PCDR1_PID38 (0x1u << 6) |
(PMC_PCDR1) Peripheral Clock 38 Disable
| #define PMC_PCDR1_PID39 (0x1u << 7) |
(PMC_PCDR1) Peripheral Clock 39 Disable
| #define PMC_PCDR1_PID40 (0x1u << 8) |
(PMC_PCDR1) Peripheral Clock 40 Disable
| #define PMC_PCDR1_PID41 (0x1u << 9) |
(PMC_PCDR1) Peripheral Clock 41 Disable
| #define PMC_PCDR1_PID42 (0x1u << 10) |
(PMC_PCDR1) Peripheral Clock 42 Disable
| #define PMC_PCDR1_PID43 (0x1u << 11) |
(PMC_PCDR1) Peripheral Clock 43 Disable
| #define PMC_PCDR1_PID44 (0x1u << 12) |
(PMC_PCDR1) Peripheral Clock 44 Disable
| #define PMC_PCDR1_PID45 (0x1u << 13) |
(PMC_PCDR1) Peripheral Clock 45 Disable
| #define PMC_PCDR1_PID46 (0x1u << 14) |
(PMC_PCDR1) Peripheral Clock 46 Disable
| #define PMC_PCDR1_PID47 (0x1u << 15) |
(PMC_PCDR1) Peripheral Clock 47 Disable
| #define PMC_PCDR1_PID48 (0x1u << 16) |
(PMC_PCDR1) Peripheral Clock 48 Disable
| #define PMC_PCDR1_PID49 (0x1u << 17) |
(PMC_PCDR1) Peripheral Clock 49 Disable
| #define PMC_PCER0_PID10 (0x1u << 10) |
(PMC_PCER0) Peripheral Clock 10 Enable
| #define PMC_PCER0_PID11 (0x1u << 11) |
(PMC_PCER0) Peripheral Clock 11 Enable
| #define PMC_PCER0_PID12 (0x1u << 12) |
(PMC_PCER0) Peripheral Clock 12 Enable
| #define PMC_PCER0_PID13 (0x1u << 13) |
(PMC_PCER0) Peripheral Clock 13 Enable
| #define PMC_PCER0_PID14 (0x1u << 14) |
(PMC_PCER0) Peripheral Clock 14 Enable
| #define PMC_PCER0_PID15 (0x1u << 15) |
(PMC_PCER0) Peripheral Clock 15 Enable
| #define PMC_PCER0_PID16 (0x1u << 16) |
(PMC_PCER0) Peripheral Clock 16 Enable
| #define PMC_PCER0_PID17 (0x1u << 17) |
(PMC_PCER0) Peripheral Clock 17 Enable
| #define PMC_PCER0_PID18 (0x1u << 18) |
(PMC_PCER0) Peripheral Clock 18 Enable
| #define PMC_PCER0_PID19 (0x1u << 19) |
(PMC_PCER0) Peripheral Clock 19 Enable
| #define PMC_PCER0_PID20 (0x1u << 20) |
(PMC_PCER0) Peripheral Clock 20 Enable
| #define PMC_PCER0_PID21 (0x1u << 21) |
(PMC_PCER0) Peripheral Clock 21 Enable
| #define PMC_PCER0_PID22 (0x1u << 22) |
(PMC_PCER0) Peripheral Clock 22 Enable
| #define PMC_PCER0_PID23 (0x1u << 23) |
(PMC_PCER0) Peripheral Clock 23 Enable
| #define PMC_PCER0_PID24 (0x1u << 24) |
(PMC_PCER0) Peripheral Clock 24 Enable
| #define PMC_PCER0_PID25 (0x1u << 25) |
(PMC_PCER0) Peripheral Clock 25 Enable
| #define PMC_PCER0_PID26 (0x1u << 26) |
(PMC_PCER0) Peripheral Clock 26 Enable
| #define PMC_PCER0_PID27 (0x1u << 27) |
(PMC_PCER0) Peripheral Clock 27 Enable
| #define PMC_PCER0_PID28 (0x1u << 28) |
(PMC_PCER0) Peripheral Clock 28 Enable
| #define PMC_PCER0_PID29 (0x1u << 29) |
(PMC_PCER0) Peripheral Clock 29 Enable
| #define PMC_PCER0_PID30 (0x1u << 30) |
(PMC_PCER0) Peripheral Clock 30 Enable
| #define PMC_PCER0_PID31 (0x1u << 31) |
(PMC_PCER0) Peripheral Clock 31 Enable
| #define PMC_PCER0_PID8 (0x1u << 8) |
(PMC_PCER0) Peripheral Clock 8 Enable
| #define PMC_PCER0_PID9 (0x1u << 9) |
(PMC_PCER0) Peripheral Clock 9 Enable
| #define PMC_PCER1_PID32 (0x1u << 0) |
(PMC_PCER1) Peripheral Clock 32 Enable
| #define PMC_PCER1_PID33 (0x1u << 1) |
(PMC_PCER1) Peripheral Clock 33 Enable
| #define PMC_PCER1_PID34 (0x1u << 2) |
(PMC_PCER1) Peripheral Clock 34 Enable
| #define PMC_PCER1_PID35 (0x1u << 3) |
(PMC_PCER1) Peripheral Clock 35 Enable
| #define PMC_PCER1_PID36 (0x1u << 4) |
(PMC_PCER1) Peripheral Clock 36 Enable
| #define PMC_PCER1_PID37 (0x1u << 5) |
(PMC_PCER1) Peripheral Clock 37 Enable
| #define PMC_PCER1_PID38 (0x1u << 6) |
(PMC_PCER1) Peripheral Clock 38 Enable
| #define PMC_PCER1_PID39 (0x1u << 7) |
(PMC_PCER1) Peripheral Clock 39 Enable
| #define PMC_PCER1_PID40 (0x1u << 8) |
(PMC_PCER1) Peripheral Clock 40 Enable
| #define PMC_PCER1_PID41 (0x1u << 9) |
(PMC_PCER1) Peripheral Clock 41 Enable
| #define PMC_PCER1_PID42 (0x1u << 10) |
(PMC_PCER1) Peripheral Clock 42 Enable
| #define PMC_PCER1_PID43 (0x1u << 11) |
(PMC_PCER1) Peripheral Clock 43 Enable
| #define PMC_PCER1_PID44 (0x1u << 12) |
(PMC_PCER1) Peripheral Clock 44 Enable
| #define PMC_PCER1_PID45 (0x1u << 13) |
(PMC_PCER1) Peripheral Clock 45 Enable
| #define PMC_PCER1_PID46 (0x1u << 14) |
(PMC_PCER1) Peripheral Clock 46 Enable
| #define PMC_PCER1_PID47 (0x1u << 15) |
(PMC_PCER1) Peripheral Clock 47 Enable
| #define PMC_PCER1_PID48 (0x1u << 16) |
(PMC_PCER1) Peripheral Clock 48 Enable
| #define PMC_PCER1_PID49 (0x1u << 17) |
(PMC_PCER1) Peripheral Clock 49 Enable
| #define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) |
(PMC_PCK[3]) Main Clock is selected
| #define PMC_PCK_CSS_MCK (0x4u << 0) |
(PMC_PCK[3]) Master Clock is selected
| #define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) |
(PMC_PCK[3]) Master Clock Source Selection
| #define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) |
(PMC_PCK[3]) PLLA Clock is selected
| #define PMC_PCK_CSS_PLLB_CLK (0x3u << 0) |
(PMC_PCK[3]) PLLB Clock is selected
| #define PMC_PCK_CSS_Pos 0 |
| #define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) |
(PMC_PCK[3]) Slow Clock is selected
| #define PMC_PCK_PRES_CLK_1 (0x0u << 4) |
(PMC_PCK[3]) Selected clock
| #define PMC_PCK_PRES_CLK_16 (0x4u << 4) |
(PMC_PCK[3]) Selected clock divided by 16
| #define PMC_PCK_PRES_CLK_2 (0x1u << 4) |
(PMC_PCK[3]) Selected clock divided by 2
| #define PMC_PCK_PRES_CLK_32 (0x5u << 4) |
(PMC_PCK[3]) Selected clock divided by 32
| #define PMC_PCK_PRES_CLK_4 (0x2u << 4) |
(PMC_PCK[3]) Selected clock divided by 4
| #define PMC_PCK_PRES_CLK_64 (0x6u << 4) |
(PMC_PCK[3]) Selected clock divided by 64
| #define PMC_PCK_PRES_CLK_8 (0x3u << 4) |
(PMC_PCK[3]) Selected clock divided by 8
| #define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) |
(PMC_PCK[3]) Programmable Clock Prescaler
| #define PMC_PCK_PRES_Pos 4 |
| #define PMC_PCSR0_PID10 (0x1u << 10) |
(PMC_PCSR0) Peripheral Clock 10 Status
| #define PMC_PCSR0_PID11 (0x1u << 11) |
(PMC_PCSR0) Peripheral Clock 11 Status
| #define PMC_PCSR0_PID12 (0x1u << 12) |
(PMC_PCSR0) Peripheral Clock 12 Status
| #define PMC_PCSR0_PID13 (0x1u << 13) |
(PMC_PCSR0) Peripheral Clock 13 Status
| #define PMC_PCSR0_PID14 (0x1u << 14) |
(PMC_PCSR0) Peripheral Clock 14 Status
| #define PMC_PCSR0_PID15 (0x1u << 15) |
(PMC_PCSR0) Peripheral Clock 15 Status
| #define PMC_PCSR0_PID16 (0x1u << 16) |
(PMC_PCSR0) Peripheral Clock 16 Status
| #define PMC_PCSR0_PID17 (0x1u << 17) |
(PMC_PCSR0) Peripheral Clock 17 Status
| #define PMC_PCSR0_PID18 (0x1u << 18) |
(PMC_PCSR0) Peripheral Clock 18 Status
| #define PMC_PCSR0_PID19 (0x1u << 19) |
(PMC_PCSR0) Peripheral Clock 19 Status
| #define PMC_PCSR0_PID20 (0x1u << 20) |
(PMC_PCSR0) Peripheral Clock 20 Status
| #define PMC_PCSR0_PID21 (0x1u << 21) |
(PMC_PCSR0) Peripheral Clock 21 Status
| #define PMC_PCSR0_PID22 (0x1u << 22) |
(PMC_PCSR0) Peripheral Clock 22 Status
| #define PMC_PCSR0_PID23 (0x1u << 23) |
(PMC_PCSR0) Peripheral Clock 23 Status
| #define PMC_PCSR0_PID24 (0x1u << 24) |
(PMC_PCSR0) Peripheral Clock 24 Status
| #define PMC_PCSR0_PID25 (0x1u << 25) |
(PMC_PCSR0) Peripheral Clock 25 Status
| #define PMC_PCSR0_PID26 (0x1u << 26) |
(PMC_PCSR0) Peripheral Clock 26 Status
| #define PMC_PCSR0_PID27 (0x1u << 27) |
(PMC_PCSR0) Peripheral Clock 27 Status
| #define PMC_PCSR0_PID28 (0x1u << 28) |
(PMC_PCSR0) Peripheral Clock 28 Status
| #define PMC_PCSR0_PID29 (0x1u << 29) |
(PMC_PCSR0) Peripheral Clock 29 Status
| #define PMC_PCSR0_PID30 (0x1u << 30) |
(PMC_PCSR0) Peripheral Clock 30 Status
| #define PMC_PCSR0_PID31 (0x1u << 31) |
(PMC_PCSR0) Peripheral Clock 31 Status
| #define PMC_PCSR0_PID8 (0x1u << 8) |
(PMC_PCSR0) Peripheral Clock 8 Status
| #define PMC_PCSR0_PID9 (0x1u << 9) |
(PMC_PCSR0) Peripheral Clock 9 Status
| #define PMC_PCSR1_PID32 (0x1u << 0) |
(PMC_PCSR1) Peripheral Clock 32 Status
| #define PMC_PCSR1_PID33 (0x1u << 1) |
(PMC_PCSR1) Peripheral Clock 33 Status
| #define PMC_PCSR1_PID34 (0x1u << 2) |
(PMC_PCSR1) Peripheral Clock 34 Status
| #define PMC_PCSR1_PID35 (0x1u << 3) |
(PMC_PCSR1) Peripheral Clock 35 Status
| #define PMC_PCSR1_PID36 (0x1u << 4) |
(PMC_PCSR1) Peripheral Clock 36 Status
| #define PMC_PCSR1_PID37 (0x1u << 5) |
(PMC_PCSR1) Peripheral Clock 37 Status
| #define PMC_PCSR1_PID38 (0x1u << 6) |
(PMC_PCSR1) Peripheral Clock 38 Status
| #define PMC_PCSR1_PID39 (0x1u << 7) |
(PMC_PCSR1) Peripheral Clock 39 Status
| #define PMC_PCSR1_PID40 (0x1u << 8) |
(PMC_PCSR1) Peripheral Clock 40 Status
| #define PMC_PCSR1_PID41 (0x1u << 9) |
(PMC_PCSR1) Peripheral Clock 41 Status
| #define PMC_PCSR1_PID42 (0x1u << 10) |
(PMC_PCSR1) Peripheral Clock 42 Status
| #define PMC_PCSR1_PID43 (0x1u << 11) |
(PMC_PCSR1) Peripheral Clock 43 Status
| #define PMC_PCSR1_PID44 (0x1u << 12) |
(PMC_PCSR1) Peripheral Clock 44 Status
| #define PMC_PCSR1_PID45 (0x1u << 13) |
(PMC_PCSR1) Peripheral Clock 45 Status
| #define PMC_PCSR1_PID46 (0x1u << 14) |
(PMC_PCSR1) Peripheral Clock 46 Status
| #define PMC_PCSR1_PID47 (0x1u << 15) |
(PMC_PCSR1) Peripheral Clock 47 Status
| #define PMC_PCSR1_PID48 (0x1u << 16) |
(PMC_PCSR1) Peripheral Clock 48 Status
| #define PMC_PCSR1_PID49 (0x1u << 17) |
(PMC_PCSR1) Peripheral Clock 49 Status
| #define PMC_PMMR_PLLA_MMAX | ( | value | ) | ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos))) |
| #define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) |
(PMC_PMMR) PLLA Maximum Allowed Multiplier Value
| #define PMC_PMMR_PLLA_MMAX_Pos 0 |
| #define PMC_SCDR_PCK0 (0x1u << 8) |
(PMC_SCDR) Programmable Clock 0 Output Disable
| #define PMC_SCDR_PCK1 (0x1u << 9) |
(PMC_SCDR) Programmable Clock 1 Output Disable
| #define PMC_SCDR_PCK2 (0x1u << 10) |
(PMC_SCDR) Programmable Clock 2 Output Disable
| #define PMC_SCDR_PCK3 (0x1u << 11) |
(PMC_SCDR) Programmable Clock 3 Output Disable
| #define PMC_SCDR_PCK4 (0x1u << 12) |
(PMC_SCDR) Programmable Clock 4 Output Disable
| #define PMC_SCDR_PCK5 (0x1u << 13) |
(PMC_SCDR) Programmable Clock 5 Output Disable
| #define PMC_SCDR_PCK6 (0x1u << 14) |
(PMC_SCDR) Programmable Clock 6 Output Disable
| #define PMC_SCDR_PCK7 (0x1u << 15) |
(PMC_SCDR) Programmable Clock 7 Output Disable
| #define PMC_SCDR_UDP (0x1u << 7) |
(PMC_SCDR)
| #define PMC_SCDR_UHP (0x1u << 6) |
(PMC_SCDR) USB Host Port Clock Disable
| #define PMC_SCER_PCK0 (0x1u << 8) |
(PMC_SCER) Programmable Clock 0 Output Enable
| #define PMC_SCER_PCK1 (0x1u << 9) |
(PMC_SCER) Programmable Clock 1 Output Enable
| #define PMC_SCER_PCK2 (0x1u << 10) |
(PMC_SCER) Programmable Clock 2 Output Enable
| #define PMC_SCER_PCK3 (0x1u << 11) |
(PMC_SCER) Programmable Clock 3 Output Enable
| #define PMC_SCER_PCK4 (0x1u << 12) |
(PMC_SCER) Programmable Clock 4 Output Enable
| #define PMC_SCER_PCK5 (0x1u << 13) |
(PMC_SCER) Programmable Clock 5 Output Enable
| #define PMC_SCER_PCK6 (0x1u << 14) |
(PMC_SCER) Programmable Clock 6 Output Enable
| #define PMC_SCER_PCK7 (0x1u << 15) |
(PMC_SCER) Programmable Clock 7 Output Enable
| #define PMC_SCER_UDP (0x1u << 7) |
(PMC_SCER) USB Device Port Clock Enable
| #define PMC_SCER_UHP (0x1u << 6) |
(PMC_SCER) USB Host Port Clock Enable
| #define PMC_SCSR_PCK0 (0x1u << 8) |
(PMC_SCSR) Programmable Clock 0 Output Status
| #define PMC_SCSR_PCK1 (0x1u << 9) |
(PMC_SCSR) Programmable Clock 1 Output Status
| #define PMC_SCSR_PCK2 (0x1u << 10) |
(PMC_SCSR) Programmable Clock 2 Output Status
| #define PMC_SCSR_PCK3 (0x1u << 11) |
(PMC_SCSR) Programmable Clock 3 Output Status
| #define PMC_SCSR_PCK4 (0x1u << 12) |
(PMC_SCSR) Programmable Clock 4 Output Status
| #define PMC_SCSR_PCK5 (0x1u << 13) |
(PMC_SCSR) Programmable Clock 5 Output Status
| #define PMC_SCSR_PCK6 (0x1u << 14) |
(PMC_SCSR) Programmable Clock 6 Output Status
| #define PMC_SCSR_PCK7 (0x1u << 15) |
(PMC_SCSR) Programmable Clock 7 Output Status
| #define PMC_SCSR_UDP (0x1u << 7) |
(PMC_SCSR)
| #define PMC_SCSR_UHP (0x1u << 6) |
(PMC_SCSR) USB Host Port Clock Status
| #define PMC_SLPWK_ASR0_PID10 (0x1u << 10) |
(PMC_SLPWK_ASR0) Peripheral 10 Activity Status
| #define PMC_SLPWK_ASR0_PID11 (0x1u << 11) |
(PMC_SLPWK_ASR0) Peripheral 11 Activity Status
| #define PMC_SLPWK_ASR0_PID12 (0x1u << 12) |
(PMC_SLPWK_ASR0) Peripheral 12 Activity Status
| #define PMC_SLPWK_ASR0_PID13 (0x1u << 13) |
(PMC_SLPWK_ASR0) Peripheral 13 Activity Status
| #define PMC_SLPWK_ASR0_PID14 (0x1u << 14) |
(PMC_SLPWK_ASR0) Peripheral 14 Activity Status
| #define PMC_SLPWK_ASR0_PID15 (0x1u << 15) |
(PMC_SLPWK_ASR0) Peripheral 15 Activity Status
| #define PMC_SLPWK_ASR0_PID16 (0x1u << 16) |
(PMC_SLPWK_ASR0) Peripheral 16 Activity Status
| #define PMC_SLPWK_ASR0_PID17 (0x1u << 17) |
(PMC_SLPWK_ASR0) Peripheral 17 Activity Status
| #define PMC_SLPWK_ASR0_PID18 (0x1u << 18) |
(PMC_SLPWK_ASR0) Peripheral 18 Activity Status
| #define PMC_SLPWK_ASR0_PID19 (0x1u << 19) |
(PMC_SLPWK_ASR0) Peripheral 19 Activity Status
| #define PMC_SLPWK_ASR0_PID20 (0x1u << 20) |
(PMC_SLPWK_ASR0) Peripheral 20 Activity Status
| #define PMC_SLPWK_ASR0_PID21 (0x1u << 21) |
(PMC_SLPWK_ASR0) Peripheral 21 Activity Status
| #define PMC_SLPWK_ASR0_PID22 (0x1u << 22) |
(PMC_SLPWK_ASR0) Peripheral 22 Activity Status
| #define PMC_SLPWK_ASR0_PID23 (0x1u << 23) |
(PMC_SLPWK_ASR0) Peripheral 23 Activity Status
| #define PMC_SLPWK_ASR0_PID24 (0x1u << 24) |
(PMC_SLPWK_ASR0) Peripheral 24 Activity Status
| #define PMC_SLPWK_ASR0_PID25 (0x1u << 25) |
(PMC_SLPWK_ASR0) Peripheral 25 Activity Status
| #define PMC_SLPWK_ASR0_PID26 (0x1u << 26) |
(PMC_SLPWK_ASR0) Peripheral 26 Activity Status
| #define PMC_SLPWK_ASR0_PID27 (0x1u << 27) |
(PMC_SLPWK_ASR0) Peripheral 27 Activity Status
| #define PMC_SLPWK_ASR0_PID28 (0x1u << 28) |
(PMC_SLPWK_ASR0) Peripheral 28 Activity Status
| #define PMC_SLPWK_ASR0_PID29 (0x1u << 29) |
(PMC_SLPWK_ASR0) Peripheral 29 Activity Status
| #define PMC_SLPWK_ASR0_PID8 (0x1u << 8) |
(PMC_SLPWK_ASR0) Peripheral 8 Activity Status
| #define PMC_SLPWK_ASR0_PID9 (0x1u << 9) |
(PMC_SLPWK_ASR0) Peripheral 9 Activity Status
| #define PMC_SLPWK_DR0_PID10 (0x1u << 10) |
(PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID11 (0x1u << 11) |
(PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID12 (0x1u << 12) |
(PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID13 (0x1u << 13) |
(PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID14 (0x1u << 14) |
(PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID15 (0x1u << 15) |
(PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID16 (0x1u << 16) |
(PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID17 (0x1u << 17) |
(PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID18 (0x1u << 18) |
(PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID19 (0x1u << 19) |
(PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID20 (0x1u << 20) |
(PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID21 (0x1u << 21) |
(PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID22 (0x1u << 22) |
(PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID23 (0x1u << 23) |
(PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID24 (0x1u << 24) |
(PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID25 (0x1u << 25) |
(PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID26 (0x1u << 26) |
(PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID27 (0x1u << 27) |
(PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID28 (0x1u << 28) |
(PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID29 (0x1u << 29) |
(PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID8 (0x1u << 8) |
(PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable
| #define PMC_SLPWK_DR0_PID9 (0x1u << 9) |
(PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable
| #define PMC_SLPWK_ER0_PID10 (0x1u << 10) |
(PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID11 (0x1u << 11) |
(PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID12 (0x1u << 12) |
(PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID13 (0x1u << 13) |
(PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID14 (0x1u << 14) |
(PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID15 (0x1u << 15) |
(PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID16 (0x1u << 16) |
(PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID17 (0x1u << 17) |
(PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID18 (0x1u << 18) |
(PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID19 (0x1u << 19) |
(PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID20 (0x1u << 20) |
(PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID21 (0x1u << 21) |
(PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID22 (0x1u << 22) |
(PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID23 (0x1u << 23) |
(PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID24 (0x1u << 24) |
(PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID25 (0x1u << 25) |
(PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID26 (0x1u << 26) |
(PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID27 (0x1u << 27) |
(PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID28 (0x1u << 28) |
(PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID29 (0x1u << 29) |
(PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID8 (0x1u << 8) |
(PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable
| #define PMC_SLPWK_ER0_PID9 (0x1u << 9) |
(PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable
| #define PMC_SLPWK_SR0_PID10 (0x1u << 10) |
(PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status
| #define PMC_SLPWK_SR0_PID11 (0x1u << 11) |
(PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status
| #define PMC_SLPWK_SR0_PID12 (0x1u << 12) |
(PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status
| #define PMC_SLPWK_SR0_PID13 (0x1u << 13) |
(PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status
| #define PMC_SLPWK_SR0_PID14 (0x1u << 14) |
(PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status
| #define PMC_SLPWK_SR0_PID15 (0x1u << 15) |
(PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status
| #define PMC_SLPWK_SR0_PID16 (0x1u << 16) |
(PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status
| #define PMC_SLPWK_SR0_PID17 (0x1u << 17) |
(PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status
| #define PMC_SLPWK_SR0_PID18 (0x1u << 18) |
(PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status
| #define PMC_SLPWK_SR0_PID19 (0x1u << 19) |
(PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status
| #define PMC_SLPWK_SR0_PID20 (0x1u << 20) |
(PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status
| #define PMC_SLPWK_SR0_PID21 (0x1u << 21) |
(PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status
| #define PMC_SLPWK_SR0_PID22 (0x1u << 22) |
(PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status
| #define PMC_SLPWK_SR0_PID23 (0x1u << 23) |
(PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status
| #define PMC_SLPWK_SR0_PID24 (0x1u << 24) |
(PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status
| #define PMC_SLPWK_SR0_PID25 (0x1u << 25) |
(PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status
| #define PMC_SLPWK_SR0_PID26 (0x1u << 26) |
(PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status
| #define PMC_SLPWK_SR0_PID27 (0x1u << 27) |
(PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status
| #define PMC_SLPWK_SR0_PID28 (0x1u << 28) |
(PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status
| #define PMC_SLPWK_SR0_PID29 (0x1u << 29) |
(PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status
| #define PMC_SLPWK_SR0_PID8 (0x1u << 8) |
(PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status
| #define PMC_SLPWK_SR0_PID9 (0x1u << 9) |
(PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status
| #define PMC_SR_CFDEV (0x1u << 18) |
(PMC_SR) Clock Failure Detector Event
| #define PMC_SR_CFDS (0x1u << 19) |
(PMC_SR) Clock Failure Detector Status
| #define PMC_SR_FOS (0x1u << 20) |
(PMC_SR) Clock Failure Detector Fault Output Status
| #define PMC_SR_LOCKA (0x1u << 1) |
(PMC_SR) PLLA Lock Status
| #define PMC_SR_LOCKB (0x1u << 2) |
(PMC_SR) PLLB Lock Status
| #define PMC_SR_MCKRDY (0x1u << 3) |
(PMC_SR) Master Clock Status
| #define PMC_SR_MOSCRCS (0x1u << 17) |
(PMC_SR) Main On-Chip RC Oscillator Status
| #define PMC_SR_MOSCSELS (0x1u << 16) |
(PMC_SR) Main Oscillator Selection Status
| #define PMC_SR_MOSCXTS (0x1u << 0) |
(PMC_SR) Main XTAL Oscillator Status
| #define PMC_SR_OSCSELS (0x1u << 7) |
(PMC_SR) Slow Clock Oscillator Selection
| #define PMC_SR_PCKRDY0 (0x1u << 8) |
(PMC_SR) Programmable Clock Ready Status
| #define PMC_SR_PCKRDY1 (0x1u << 9) |
(PMC_SR) Programmable Clock Ready Status
| #define PMC_SR_PCKRDY2 (0x1u << 10) |
(PMC_SR) Programmable Clock Ready Status
| #define PMC_SR_PCKRDY3 (0x1u << 11) |
(PMC_SR) Programmable Clock Ready Status
| #define PMC_SR_PCKRDY4 (0x1u << 12) |
(PMC_SR) Programmable Clock Ready Status
| #define PMC_SR_PCKRDY5 (0x1u << 13) |
(PMC_SR) Programmable Clock Ready Status
| #define PMC_SR_PCKRDY6 (0x1u << 14) |
(PMC_SR) Programmable Clock Ready Status
| #define PMC_SR_PCKRDY7 (0x1u << 15) |
(PMC_SR) Programmable Clock Ready Status
| #define PMC_USB_USBDIV | ( | value | ) | ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) |
| #define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) |
(PMC_USB) Divider for USB Clock
| #define PMC_USB_USBDIV_Pos 8 |
| #define PMC_USB_USBS (0x1u << 0) |
(PMC_USB) USB Input Clock Selection
| #define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) |
(PMC_VERSION) Metal Fix Number
| #define PMC_VERSION_MFN_Pos 16 |
| #define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) |
(PMC_VERSION) Version of the Hardware Module
| #define PMC_VERSION_VERSION_Pos 0 |
| #define PMC_WPMR_WPEN (0x1u << 0) |
(PMC_WPMR) Write Protection Enable
| #define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) |
(PMC_WPMR) Write Protection Key
| #define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) |
(PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
| #define PMC_WPMR_WPKEY_Pos 8 |
| #define PMC_WPSR_WPVS (0x1u << 0) |
(PMC_WPSR) Write Protection Violation Status
| #define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) |
(PMC_WPSR) Write Protection Violation Source
| #define PMC_WPSR_WPVSRC_Pos 8 |


High-profile attorney in New Mexico arrested for 2nd DWI
ALBUQUERQUE, N.M. (AP) - A high-profile defense attorney in New Mexico is facing his second drunken driving charge this year.
David Serna was arrested Saturday in Albuquerque after police said he crashed his Mini Cooper into another car.
According to a criminal complaint, the 66-year-old Serna admitted to having a beer an hour and a half before the accident after telling police he hadn’t been drinking. Court documents also say Serna told authorities he had taken nerve pain medication and oxycodone earlier in the day.
Police say a breathalyzer test showed Serna had a blood alcohol content of 0.16 - twice the legal limit in New Mexico.
Serna was arrested and charged with aggravated drunken driving. Serna did not immediately respond to a phone message.
His latest arrest comes months after prosecutors dropped another drunken driving case.
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A sociologist realized that if she were ever going to understand global inequality she would have to become one of the people who helps create it. So she trained to become a wealth manager to the ultra-rich.
WOW. right? Grab your popcorn.gif This may take a second to digest so Let’s minute to consume this latest bitcoin brain dump unfolding just hours ago. Bitcoin’s Creator, who goes by …
maybe above gives context to csw's shenanigans
2
KomodoWorld31-Aug-18 07:30 AM
Phil Wilson (aka Scronty) wrote last year his story of how Bitcoin was born and the interaction with Kleiman and CSW: http://vu.hn/bitcoin%20origins.html
no way to verify but it sounds the most credible of all bitcoin origins story and he seems a very level headed guy https://twitter.com/_Phil_Wilson_
Craig Steven Wright, who over the past days claimed to be the inventor of Bitcoin, has been unable to publicly prove control over any of the keys that (only) Satoshi Nakamoto should possess. While his initial blog post deceptively included a Satoshi Nakamoto signature that wa...
About two weeks before his grisly death, there was a change in Dave Kleiman. The formerly generous and lively computer forensics expert became confrontational and bitter. Around that time, Kleiman left the Veteran’s Affairs hospital where he’d been a patient, and called h...
A bitcoin whale has recently moved over 111,000 bitcoin and bitcoin cash to over 80 wallets, each with nearly 1,000 BTC in it, at press time worth about $6.8 million. The funds had previously been scattered to numerous addresses with 100 BTC each.

 LOL
I always wondered where tf all those btc go when they get incarcerated. Like when btc was cheap as peanuts and people were sending 500 1000 2000btc for a little bag of magic
#ForcedHodl
blackjok3r31-Aug-18 10:23 AM
Pretty sure one night at my house we spent a million dollars worth of molly in 2014.
Deleted User31-Aug-18 10:24 AM
better than a pizza I guess
1
1
house31-Aug-18 10:40 AM
@jl777c James ... what is your prognosis ?
Do you lend any weight of credibility to this discussion about the tri-lateral signatory insinuation or think it is just more disingenuous and petty quarrelling ?
Personally , I find@it a stretch to believe that after so much time, they want to discuss this matter in the public domain.
jl777c31-Aug-18 10:49 AM
where are the multisig addresses with lots of bitcoins? I dont see them
To trade $PIRATE on a Central Exchange, the exchange has to do it Only via z transactions.
What are your thoughts on having $PIRATE coin trading on a Central Exchange?
Would you like to trade this MOST (I guess) Anonymous coin on exchange?
Apr.26 -- Dan Morehead, chief executive officer at Pantera Capital Management, talks about his $1 billion cryptocurrency hedge fund. He speaks to Bloomberg's...
Kitchen Table31-Aug-18 01:43 PM
After spending nearly $30k on CHIPS and having to watch the devs try to keep the chain running a year later, I've held off on spending any more on other Komodo side projects.
xRobeSx31-Aug-18 01:44 PM
The devs aren't struggling, miners just need to mine.
chips will be fine, have hope
Kitchen Table31-Aug-18 01:47 PM
Been a year. That hope is taking a while to come. The dollar value of the coin isn't what concerns me. I just want it to reliably work.
xRobeSx31-Aug-18 01:51 PM
It was said from the beginning that chips wouldn't be used for gambling anytime soon as it all had to be developed still.
Mine it. The network is fine then.
Kitchen Table31-Aug-18 01:55 PM
I'm not a miner and telling me to be one isn't the fix I'm looking for. I knew it would be a long while before CHIPS would have a use outside of just sending coins but now you can hardly do that. Regardless, all my investment is going toward projects outside of Komodo until I see CHIPS working properly again.
xRobeSx31-Aug-18 02:05 PM
If there was a real issue that needed fixing I'd agree with you. People just need to care to mine it...
No one wants the small block rewards, and just think someone else will mine it for them..
decentralized networks require people to come together and participate in keeping it going. Its not a dev issue, its a community/miner problem(edited)
Kitchen Table31-Aug-18 02:14 PM
Then that problem should have been thought of before it came to be. I'm the guy that buys the coins from the miners so I don't have to go through the trouble of setting up miners myself. I am part of the crowd that gives a reason why anyone would mine a coin. I am not about to start renting or buying miners for one coin when I haven't had to in over four years. If it comes to the point that I have to be the one to mine it, then you might well mark the coin up for dead.
xRobeSx31-Aug-18 02:16 PM
How can one predict that miners won't want to mine? If you don't want to, try to find others that might want to. I am mining myself trying to help. Others can as well.
I'm just saying decentralized coins and such require the community to do things. We can't just complain it doesn't work and the devs should fix it..
If you own CHIPS then you probably have a financial interest in making sure the network stays healthy
Kitchen Table31-Aug-18 02:19 PM
Even I thought of the blocks giving out little reward a year later and so expected the devs to know that as well and had a plan for it. There wasn't a plan until recently. I convince a few big investors as well to buy into chips so I think I helped at the start at least.
Kitchen Table31-Aug-18 02:28 PM
I've been in crypto too long to argue this. I'll just write off the investment as a lose and move on. I will still continue to invest with Komodo but any side project is off the books.
xRobeSx31-Aug-18 02:28 PM
hah goodluck
thanks for your support(edited)
jl777c31-Aug-18 02:42 PM
CHIPS core code is still being developed, as long as the network is there when the core code is ready, that is what is important


New Ram's Skydeck Experience Features 360-Degree Views of L.A.
There's a new fan experience at the Los Angeles Memorial Coliseum. The Casa Mexico Sky Deck offers Rams fans a premium experience from atop the stadium with 360-degree views of the city, lounge spaces, exclusive concessions and a unique sports bar vibe. The new shaded deck is a go-to venue for boxing legend Oscar De La Hoya, who partners with Casa Mexico Tequila. The signature dishes and cocktails served at the the Sky Deck rival many of LA's top restaurants and bars.


|
App Engine Python SDK
v1.6.9 rev.445
The Python runtime is available as an experimental Preview feature.
|
Variables | |
| int | EOF = -1 |
| int | DEFAULT_CHANNEL = 0 |
| All tokens go to the parser (unless skip() is called in that rule) on a particular "channel". More... | |
| int | HIDDEN_CHANNEL = 99 |
| Anything on different channel than DEFAULT_CHANNEL is not parsed by parser. More... | |
| int | EOR_TOKEN_TYPE = 1 |
| int | DOWN = 2 |
| imaginary tree navigation type; traverse "get child" link | |
| int | UP = 3 |
| imaginary tree navigation type; finish with a child list | |
| int | MIN_TOKEN_TYPE = UP+1 |
| int | INVALID_TOKEN_TYPE = 0 |
ANTLR3 runtime package
| int google.appengine._internal.antlr3.constants.DEFAULT_CHANNEL = 0 |
All tokens go to the parser (unless skip() is called in that rule) on a particular "channel".
The parser tunes to a particular channel so that whitespace etc... can go to the parser on a "hidden" channel.
| int google.appengine._internal.antlr3.constants.HIDDEN_CHANNEL = 99 |
Anything on different channel than DEFAULT_CHANNEL is not parsed by parser.


1. Select the exported json file:
2. Select the search.json.mozlz4 file from the current Firefox profile folder:
3.
4. Close Firefox, then navigate to your current Firefox profile folder.
5. Make a backup of the "search.json.mozlz4" file (add a ".old" to the filename for example).
6. Copy the generated "search.json.mozlz4" to this folder, then start Firefox.


Celebrity social media photos: Kriti Sanon, Varun Dhawan, Genelia D’Souza and others
Akshay Kumar, Shahid Kapoor, Varun Dhawan, Karan Johar, Genelia D'Souza, Pulkit Samrat and Sunny Leone among others shared their latest photos on social media.
25 Nov 2019, 06:56
The latest edition of celebrity social media photos features clicks shared by Janhvi Kapoor, Varun Dhawan, Genelia D'Souza, Shahid Kapoor and Taapsee Pannu among others on their respective social media accounts. Scroll to see photos.
Akshay Kumar shared this photo with the caption, "Last night was a #HouseFull of fun with friends from Housefull 1, 2, 3 and 4🕺Gearing up for 5? I don’t know 😜😂 @bachchan @riteishd @kritisanon @iambobbydeol @jacquelinef143 @kriti.kharbanda @wardakhannadiadwala @chunkypanday @hegdepooja @farhadsamji #SajidNadiadwala." (Photo: Akshay Kumar/Instagram)
Here are some new clicks of Janhvi Kapoor. (Photo: Tanya Ghavri/Instagram)
We can never get enough of Janhvi. (Photo: Tanya Ghavri/Instagram)
Varun Dhawan shared his latest photo too. (Photo: Varun Dhawan/Instagram)
Varun Dhawan is a poser. (Photo: Varun Dhawan/Instagram)
Sharing a photo of herself and Priyanka Chopra, Kriti Sanon wrote, "When Parvati Bai met Kashi Bai! ❤ Its always so lovely meeting you PC! @priyankachopra biggg hug!" (Photo: Kriti Sanon/Instagram)
"Countdown to the international EMMY’S in NYC! We are ecstatic to be nominated for #luststories !," wrote Karan Johar with his click. (Photo: Karan Johar/Instagram)
Pulkit Samrat reposted this picture shared by Pagalpanti co-star Kriti Kharbanda. Kriti had captioned the picture, "Food v/s me. Guess who won! @pulkitsamrat #ourkindapagalpanti !" (Photo: Pulkit Samrat/Instagram)
Sharing this photo, Taapsee Pannu wrote, "Wow! In hindsight, it was actually a conversation on ‘fire’ ! Thank you @iffigoa and @maddymatters_ my debut there will surely be a memorable one for a lot of us I guess ☺ See you next year :)." (Photo: Taapsee Pannu/Instagram)
"It wouldn’t be proper without pizza," wrote Sunny Leone with the photos. (Photo: Sunny Leone/Instagram)
Genelia D'Souza shared the cutest note for her 'first born' on his birthday. (Photo: Genelia D'Souza/Instagram)
"Dearest Riaan, Every parent says “I don’t want him to grow up, I want to freeze this age forever”.. But I don’t.. I want to enjoy every year of yours, I want to see you grow into a fine young man, I want to give you wings to fly and I’d like to be the wind beneath those wings. I want to tell you that life is tough but you are tougher, I want you to always believe in yourself no matter what happens cause I will always believe in you.. Apart from everything I want and I wish for you, the one thing I never want to fail to let you know, is that I love you so so so much and you are the greatest thing that happened to me.. There is nothing I’d rather see than your smile and nothing I’d rather hear than your laughter. For all the things my hands have held, the best by far is you. Happy Birthday to the little boy who made me a Mom- My First Born ❤," wrote Genelia sharing the photos. (Photo: Genelia D'Souza/Instagram)
Shahid Kapoor shared his latest photo. (Photo: Shahid Kapoor/Instagram)


Environment not found.
This will prevent any further deployments to this environment until it is unlocked.
This will cause users of publicly available services in this environment to see a maintenance page.


1. Select numbers from number panel.
2. Click '=' to verify if your sum equals numbers on the left.
3. If sum is correct, '=' will change to a green tick.
4. Click the green tick again to accept the answer.
5. If sum is wrong the '=' will change to a red cross.
6. Click selected numbers to deselect them.
7. Once accepted, the numbers cannot be used again.
8. Exhaust all numbers to win the game.


[gecode-users] integrate a new search strategy in Gecode
Javier Andrés Mena Zapata
javimena at gmail.com
Tue Jan 25 18:32:09 CET 2011
This book may help you to resolve your question. It is very, very good:
http://www.amazon.com/C-Programming-Language-Special/dp/0201700735/
<http://www.amazon.com/C-Programming-Language-Special/dp/0201700735/>Best
regards,
2011/1/25 sami sami1 <saidisamira13 at yahoo.fr>
> but we have a problem in Librairy Gecode, I know
>
> thank you for this information
>
> I would create a new search strategy NOUVSEARCH like DFS,BAB..., so it
> must add or create a new file nouvsearch.cpp in gecode/search.
> In gecode/search there are:
> dfs.cpp bab.cpp nouvsearch.cpp
>
> after, I'll take an example of Gecode as money.cpp
> in the line "run":
>
> Script::run<Money,DFS,Options>(opt);
>
> I replace DFS by NOUVSEARCH like this:
>
> Script::run<Money,NOUVSEARCH,Options>(opt);
>
> but we have a problem in Librairy Gecode, I know
> how i resourd this problem?
>
>
> _______________________________________________
> Gecode users mailing list
> users at gecode.org
> https://www.gecode.org/mailman/listinfo/gecode-users
>
>
--
Javier Andrés Mena Zapata
Cali - Colombia
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