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MINI58_BSP V3.01.004
The Board Support Package for Mini58 Series MCU
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Macros | |
| #define | NULL (0) |
| NULL pointer. More... | |
| #define | TRUE (1) |
| Boolean true, define to use in API parameters or return value. More... | |
| #define | FALSE (0) |
| Boolean false, define to use in API parameters or return value. More... | |
| #define | ENABLE (1) |
| Enable, define to use in API parameters. More... | |
| #define | DISABLE (0) |
| Disable, define to use in API parameters. More... | |
| #define | BIT0 (0x00000001) |
| Bit 0 mask of an 32 bit integer. More... | |
| #define | BIT1 (0x00000002) |
| Bit 1 mask of an 32 bit integer. More... | |
| #define | BIT2 (0x00000004) |
| Bit 2 mask of an 32 bit integer. More... | |
| #define | BIT3 (0x00000008) |
| Bit 3 mask of an 32 bit integer. More... | |
| #define | BIT4 (0x00000010) |
| Bit 4 mask of an 32 bit integer. More... | |
| #define | BIT5 (0x00000020) |
| Bit 5 mask of an 32 bit integer. More... | |
| #define | BIT6 (0x00000040) |
| Bit 6 mask of an 32 bit integer. More... | |
| #define | BIT7 (0x00000080) |
| Bit 7 mask of an 32 bit integer. More... | |
| #define | BIT8 (0x00000100) |
| Bit 8 mask of an 32 bit integer. More... | |
| #define | BIT9 (0x00000200) |
| Bit 9 mask of an 32 bit integer. More... | |
| #define | BIT10 (0x00000400) |
| Bit 10 mask of an 32 bit integer. More... | |
| #define | BIT11 (0x00000800) |
| Bit 11 mask of an 32 bit integer. More... | |
| #define | BIT12 (0x00001000) |
| Bit 12 mask of an 32 bit integer. More... | |
| #define | BIT13 (0x00002000) |
| Bit 13 mask of an 32 bit integer. More... | |
| #define | BIT14 (0x00004000) |
| Bit 14 mask of an 32 bit integer. More... | |
| #define | BIT15 (0x00008000) |
| Bit 15 mask of an 32 bit integer. More... | |
| #define | BIT16 (0x00010000) |
| Bit 16 mask of an 32 bit integer. More... | |
| #define | BIT17 (0x00020000) |
| Bit 17 mask of an 32 bit integer. More... | |
| #define | BIT18 (0x00040000) |
| Bit 18 mask of an 32 bit integer. More... | |
| #define | BIT19 (0x00080000) |
| Bit 19 mask of an 32 bit integer. More... | |
| #define | BIT20 (0x00100000) |
| Bit 20 mask of an 32 bit integer. More... | |
| #define | BIT21 (0x00200000) |
| Bit 21 mask of an 32 bit integer. More... | |
| #define | BIT22 (0x00400000) |
| Bit 22 mask of an 32 bit integer. More... | |
| #define | BIT23 (0x00800000) |
| Bit 23 mask of an 32 bit integer. More... | |
| #define | BIT24 (0x01000000) |
| Bit 24 mask of an 32 bit integer. More... | |
| #define | BIT25 (0x02000000) |
| Bit 25 mask of an 32 bit integer. More... | |
| #define | BIT26 (0x04000000) |
| Bit 26 mask of an 32 bit integer. More... | |
| #define | BIT27 (0x08000000) |
| Bit 27 mask of an 32 bit integer. More... | |
| #define | BIT28 (0x10000000) |
| Bit 28 mask of an 32 bit integer. More... | |
| #define | BIT29 (0x20000000) |
| Bit 29 mask of an 32 bit integer. More... | |
| #define | BIT30 (0x40000000) |
| Bit 30 mask of an 32 bit integer. More... | |
| #define | BIT31 (0x80000000) |
| Bit 31 mask of an 32 bit integer. More... | |
| #define | BYTE0_Msk (0x000000FF) |
| Mask to get bit0~bit7 from a 32 bit integer. More... | |
| #define | BYTE1_Msk (0x0000FF00) |
| Mask to get bit8~bit15 from a 32 bit integer. More... | |
| #define | BYTE2_Msk (0x00FF0000) |
| Mask to get bit16~bit23 from a 32 bit integer. More... | |
| #define | BYTE3_Msk (0xFF000000) |
| Mask to get bit24~bit31 from a 32 bit integer. More... | |
| #define | GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) |
| #define | GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) |
| #define | GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) |
| #define | GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) |
Variables | |
| __IO uint32_t | ACMP_T::CTL [2] |
| __IO uint32_t | ACMP_T::STATUS |
| __IO uint32_t | ACMP_T::VREF |
| __I uint32_t | ADC_T::DAT |
| __IO uint32_t | ADC_T::CTL |
| __IO uint32_t | ADC_T::CHEN |
| __IO uint32_t | ADC_T::CMP0 |
| __IO uint32_t | ADC_T::CMP1 |
| __IO uint32_t | ADC_T::STATUS |
| __IO uint32_t | ADC_T::TRGDLY |
| __IO uint32_t | ADC_T::EXTSMPT |
| __IO uint32_t | ADC_T::SEQCTL |
| __I uint32_t | ADC_T::SEQDAT1 |
| __I uint32_t | ADC_T::SEQDAT2 |
| __IO uint32_t | CLK_T::PWRCTL |
| __IO uint32_t | CLK_T::AHBCLK |
| __IO uint32_t | CLK_T::APBCLK |
| __IO uint32_t | CLK_T::STATUS |
| __IO uint32_t | CLK_T::CLKSEL0 |
| __IO uint32_t | CLK_T::CLKSEL1 |
| __IO uint32_t | CLK_T::CLKDIV |
| __IO uint32_t | CLK_T::CLKSEL2 |
| __IO uint32_t | CLK_T::PLLCTL |
| __IO uint32_t | CLK_T::CLKOCTL |
| __IO uint32_t | FMC_T::ISPCTL |
| __IO uint32_t | FMC_T::ISPADDR |
| __IO uint32_t | FMC_T::ISPDAT |
| __IO uint32_t | FMC_T::ISPCMD |
| __IO uint32_t | FMC_T::ISPTRG |
| __I uint32_t | FMC_T::DFBA |
| __IO uint32_t | FMC_T::FATCTL |
| __I uint32_t | FMC_T::ISPSTS |
| __IO uint32_t | GPIO_T::MODE |
| __IO uint32_t | GPIO_T::DINOFF |
| __IO uint32_t | GPIO_T::DOUT |
| __IO uint32_t | GPIO_T::DATMSK |
| __I uint32_t | GPIO_T::PIN |
| __IO uint32_t | GPIO_T::DBEN |
| __IO uint32_t | GPIO_T::INTTYPE |
| __IO uint32_t | GPIO_T::INTEN |
| __IO uint32_t | GPIO_T::INTSRC |
| __IO uint32_t | GPIO_DB_T::DBCTL |
| __IO uint32_t | I2C_T::CTL |
| __IO uint32_t | I2C_T::ADDR0 |
| __IO uint32_t | I2C_T::DAT |
| __I uint32_t | I2C_T::STATUS |
| __IO uint32_t | I2C_T::CLKDIV |
| __IO uint32_t | I2C_T::TOCTL |
| __IO uint32_t | I2C_T::ADDR1 |
| __IO uint32_t | I2C_T::ADDR2 |
| __IO uint32_t | I2C_T::ADDR3 |
| __IO uint32_t | I2C_T::ADDRMSK0 |
| __IO uint32_t | I2C_T::ADDRMSK1 |
| __IO uint32_t | I2C_T::ADDRMSK2 |
| __IO uint32_t | I2C_T::ADDRMSK3 |
| __IO uint32_t | I2C_T::CTL1 |
| __IO uint32_t | I2C_T::STATUS1 |
| __I uint32_t | INTR_T::IRQ0_SRC |
| __I uint32_t | INTR_T::IRQ1_SRC |
| __I uint32_t | INTR_T::IRQ2_SRC |
| __I uint32_t | INTR_T::IRQ3_SRC |
| __I uint32_t | INTR_T::IRQ4_SRC |
| __I uint32_t | INTR_T::IRQ5_SRC |
| __I uint32_t | INTR_T::IRQ6_SRC |
| __I uint32_t | INTR_T::IRQ7_SRC |
| __I uint32_t | INTR_T::IRQ8_SRC |
| __I uint32_t | INTR_T::IRQ9_SRC |
| __I uint32_t | INTR_T::IRQ12_SRC |
| __I uint32_t | INTR_T::IRQ13_SRC |
| __I uint32_t | INTR_T::IRQ14_SRC |
| __I uint32_t | INTR_T::IRQ16_SRC |
| __I uint32_t | INTR_T::IRQ17_SRC |
| __I uint32_t | INTR_T::IRQ18_SRC |
| __I uint32_t | INTR_T::IRQ19_SRC |
| __I uint32_t | INTR_T::IRQ25_SRC |
| __I uint32_t | INTR_T::IRQ28_SRC |
| __I uint32_t | INTR_T::IRQ29_SRC |
| __IO uint32_t | INTR_T::CON |
| __IO uint32_t | INTR_T::IRQ |
| __IO uint32_t | PWM_T::CLKPSC |
| __IO uint32_t | PWM_T::CLKDIV |
| __IO uint32_t | PWM_T::CTL |
| __IO uint32_t | PWM_T::PERIOD0 |
| __IO uint32_t | PWM_T::PERIOD1 |
| __IO uint32_t | PWM_T::PERIOD2 |
| __IO uint32_t | PWM_T::PERIOD3 |
| __IO uint32_t | PWM_T::PERIOD4 |
| __IO uint32_t | PWM_T::PERIOD5 |
| __IO uint32_t | PWM_T::CMPDAT0 |
| __IO uint32_t | PWM_T::CMPDAT1 |
| __IO uint32_t | PWM_T::CMPDAT2 |
| __IO uint32_t | PWM_T::CMPDAT3 |
| __IO uint32_t | PWM_T::CMPDAT4 |
| __IO uint32_t | PWM_T::CMPDAT5 |
| __IO uint32_t | PWM_T::INTEN |
| __IO uint32_t | PWM_T::INTSTS |
| __IO uint32_t | PWM_T::POEN |
| __IO uint32_t | PWM_T::BRKCTL |
| __IO uint32_t | PWM_T::DTCTL |
| __IO uint32_t | PWM_T::ADCTCTL0 |
| __IO uint32_t | PWM_T::ADCTCTL1 |
| __IO uint32_t | PWM_T::ADCTSTS0 |
| __IO uint32_t | PWM_T::ADCTSTS1 |
| __IO uint32_t | PWM_T::PHCHG |
| __IO uint32_t | PWM_T::PHCHGNXT |
| __IO uint32_t | PWM_T::PHCHGMSK |
| __IO uint32_t | PWM_T::IFA |
| __IO uint32_t | PWM_T::PCACTL |
| __IO uint32_t | PWM_T::MSKALIGN |
| __IO uint32_t | SPI_T::CTL |
| __IO uint32_t | SPI_T::CLKDIV |
| __IO uint32_t | SPI_T::SSCTL |
| __I uint32_t | SPI_T::RX |
| __O uint32_t | SPI_T::TX |
| __IO uint32_t | SPI_T::SLVCTL |
| __IO uint32_t | SPI_T::FIFOCTL |
| __IO uint32_t | SPI_T::STATUS |
| __I uint32_t | SYS_T::PDID |
| __IO uint32_t | SYS_T::RSTSTS |
| __IO uint32_t | SYS_T::IPRST0 |
| __IO uint32_t | SYS_T::IPRST1 |
| __IO uint32_t | SYS_T::BODCTL |
| __IO uint32_t | SYS_T::P0_MFP |
| __IO uint32_t | SYS_T::P1_MFP |
| __IO uint32_t | SYS_T::P2_MFP |
| __IO uint32_t | SYS_T::P3_MFP |
| __IO uint32_t | SYS_T::P4_MFP |
| __IO uint32_t | SYS_T::P5_MFP |
| __IO uint32_t | SYS_T::IRCTCTL |
| __IO uint32_t | SYS_T::IRCTIEN |
| __IO uint32_t | SYS_T::IRCTISTS |
| __O uint32_t | SYS_T::REGLCTL |
| __IO uint32_t | TIMER_T::CTL |
| __IO uint32_t | TIMER_T::CMP |
| __IO uint32_t | TIMER_T::INTSTS |
| __I uint32_t | TIMER_T::CNT |
| __I uint32_t | TIMER_T::CAP |
| __IO uint32_t | TIMER_T::EXTCTL |
| __IO uint32_t | TIMER_T::EINTSTS |
| __IO uint32_t | UART_T::DAT |
| __IO uint32_t | UART_T::INTEN |
| __IO uint32_t | UART_T::FIFO |
| __IO uint32_t | UART_T::LINE |
| __IO uint32_t | UART_T::MODEM |
| __IO uint32_t | UART_T::MODEMSTS |
| __IO uint32_t | UART_T::FIFOSTS |
| __IO uint32_t | UART_T::INTSTS |
| __IO uint32_t | UART_T::TOUT |
| __IO uint32_t | UART_T::BAUD |
| __IO uint32_t | UART_T::IRDA |
| __IO uint32_t | UART_T::ALTCTL |
| __IO uint32_t | UART_T::FUNSEL |
| __IO uint32_t | WDT_T::CTL |
| __IO uint32_t | WDT_T::ALTCTL |
| __O uint32_t | WWDT_T::RLDCNT |
| __IO uint32_t | WWDT_T::CTL |
| __IO uint32_t | WWDT_T::STATUS |
| __I uint32_t | WWDT_T::CNT |
Mini58 Legacy Constants
| #define BIT0 (0x00000001) |
Bit 0 mask of an 32 bit integer.
Definition at line 11896 of file Mini58Series.h.
| #define BIT1 (0x00000002) |
Bit 1 mask of an 32 bit integer.
Definition at line 11897 of file Mini58Series.h.
| #define BIT10 (0x00000400) |
Bit 10 mask of an 32 bit integer.
Definition at line 11906 of file Mini58Series.h.
| #define BIT11 (0x00000800) |
Bit 11 mask of an 32 bit integer.
Definition at line 11907 of file Mini58Series.h.
| #define BIT12 (0x00001000) |
Bit 12 mask of an 32 bit integer.
Definition at line 11908 of file Mini58Series.h.
| #define BIT13 (0x00002000) |
Bit 13 mask of an 32 bit integer.
Definition at line 11909 of file Mini58Series.h.
| #define BIT14 (0x00004000) |
Bit 14 mask of an 32 bit integer.
Definition at line 11910 of file Mini58Series.h.
| #define BIT15 (0x00008000) |
Bit 15 mask of an 32 bit integer.
Definition at line 11911 of file Mini58Series.h.
| #define BIT16 (0x00010000) |
Bit 16 mask of an 32 bit integer.
Definition at line 11912 of file Mini58Series.h.
| #define BIT17 (0x00020000) |
Bit 17 mask of an 32 bit integer.
Definition at line 11913 of file Mini58Series.h.
| #define BIT18 (0x00040000) |
Bit 18 mask of an 32 bit integer.
Definition at line 11914 of file Mini58Series.h.
| #define BIT19 (0x00080000) |
Bit 19 mask of an 32 bit integer.
Definition at line 11915 of file Mini58Series.h.
| #define BIT2 (0x00000004) |
Bit 2 mask of an 32 bit integer.
Definition at line 11898 of file Mini58Series.h.
| #define BIT20 (0x00100000) |
Bit 20 mask of an 32 bit integer.
Definition at line 11916 of file Mini58Series.h.
| #define BIT21 (0x00200000) |
Bit 21 mask of an 32 bit integer.
Definition at line 11917 of file Mini58Series.h.
| #define BIT22 (0x00400000) |
Bit 22 mask of an 32 bit integer.
Definition at line 11918 of file Mini58Series.h.
| #define BIT23 (0x00800000) |
Bit 23 mask of an 32 bit integer.
Definition at line 11919 of file Mini58Series.h.
| #define BIT24 (0x01000000) |
Bit 24 mask of an 32 bit integer.
Definition at line 11920 of file Mini58Series.h.
| #define BIT25 (0x02000000) |
Bit 25 mask of an 32 bit integer.
Definition at line 11921 of file Mini58Series.h.
| #define BIT26 (0x04000000) |
Bit 26 mask of an 32 bit integer.
Definition at line 11922 of file Mini58Series.h.
| #define BIT27 (0x08000000) |
Bit 27 mask of an 32 bit integer.
Definition at line 11923 of file Mini58Series.h.
| #define BIT28 (0x10000000) |
Bit 28 mask of an 32 bit integer.
Definition at line 11924 of file Mini58Series.h.
| #define BIT29 (0x20000000) |
Bit 29 mask of an 32 bit integer.
Definition at line 11925 of file Mini58Series.h.
| #define BIT3 (0x00000008) |
Bit 3 mask of an 32 bit integer.
Definition at line 11899 of file Mini58Series.h.
| #define BIT30 (0x40000000) |
Bit 30 mask of an 32 bit integer.
Definition at line 11926 of file Mini58Series.h.
| #define BIT31 (0x80000000) |
Bit 31 mask of an 32 bit integer.
Definition at line 11927 of file Mini58Series.h.
| #define BIT4 (0x00000010) |
Bit 4 mask of an 32 bit integer.
Definition at line 11900 of file Mini58Series.h.
| #define BIT5 (0x00000020) |
Bit 5 mask of an 32 bit integer.
Definition at line 11901 of file Mini58Series.h.
| #define BIT6 (0x00000040) |
Bit 6 mask of an 32 bit integer.
Definition at line 11902 of file Mini58Series.h.
| #define BIT7 (0x00000080) |
Bit 7 mask of an 32 bit integer.
Definition at line 11903 of file Mini58Series.h.
| #define BIT8 (0x00000100) |
Bit 8 mask of an 32 bit integer.
Definition at line 11904 of file Mini58Series.h.
| #define BIT9 (0x00000200) |
Bit 9 mask of an 32 bit integer.
Definition at line 11905 of file Mini58Series.h.
| #define BYTE0_Msk (0x000000FF) |
Mask to get bit0~bit7 from a 32 bit integer.
Definition at line 11930 of file Mini58Series.h.
| #define BYTE1_Msk (0x0000FF00) |
Mask to get bit8~bit15 from a 32 bit integer.
Definition at line 11931 of file Mini58Series.h.
| #define BYTE2_Msk (0x00FF0000) |
Mask to get bit16~bit23 from a 32 bit integer.
Definition at line 11932 of file Mini58Series.h.
| #define BYTE3_Msk (0xFF000000) |
Mask to get bit24~bit31 from a 32 bit integer.
Definition at line 11933 of file Mini58Series.h.
| #define DISABLE (0) |
Disable, define to use in API parameters.
Definition at line 11893 of file Mini58Series.h.
| #define ENABLE (1) |
Enable, define to use in API parameters.
Definition at line 11892 of file Mini58Series.h.
| #define FALSE (0) |
Boolean false, define to use in API parameters or return value.
Definition at line 11890 of file Mini58Series.h.
| #define GET_BYTE0 | ( | u32Param | ) | ((u32Param & BYTE0_Msk) ) |
Extract Byte 0 (Bit 0~ 7) from parameter u32Param
Definition at line 11935 of file Mini58Series.h.
| #define GET_BYTE1 | ( | u32Param | ) | ((u32Param & BYTE1_Msk) >> 8) |
Extract Byte 1 (Bit 8~15) from parameter u32Param
Definition at line 11936 of file Mini58Series.h.
| #define GET_BYTE2 | ( | u32Param | ) | ((u32Param & BYTE2_Msk) >> 16) |
Extract Byte 2 (Bit 16~23) from parameter u32Param
Definition at line 11937 of file Mini58Series.h.
| #define GET_BYTE3 | ( | u32Param | ) | ((u32Param & BYTE3_Msk) >> 24) |
Extract Byte 3 (Bit 24~31) from parameter u32Param
Definition at line 11938 of file Mini58Series.h.
| #define NULL (0) |
NULL pointer.
Definition at line 11886 of file Mini58Series.h.
| #define TRUE (1) |
Boolean true, define to use in API parameters or return value.
Definition at line 11889 of file Mini58Series.h.
| __IO uint32_t PWM_T::ADCTCTL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CUTRGEN0 | Channel 0 Compare Up Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel0's counter matching CMP0 in up-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect. | ||
| [1] | CPTRGEN0 | Channel 0 Center Point Trigger ADC Enable Bit |
| Enable PWM Trigger ADC Function While channel0's Counter Matching PERIOD0 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect. | ||
| [2] | CDTRGEN0 | Channel 0 Compare Down Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel0's counter matching CMP0 in down-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged-aligned type. | ||
| [3] | ZPTRGEN0 | Channel 0 Zero Point Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel0's counter matching 0 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged-aligned type. | ||
| [8] | CUTRGEN1 | Channel 1 Compare Up Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel1's counter matching CMP1 in up-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect. | ||
| [9] | CPTRGEN1 | Channel 1 Center Point Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel1's counter matching PERIOD1 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect. | ||
| [10] | CDTRGEN1 | Channel 1 Compare Down Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel1's counter matching CMP1 in down-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged-aligned type. | ||
| [11] | ZPTRGEN1 | Channel 1 Zero Point Trigger ADC Enable Bit |
| Enable PWM trigger ADC function While channel1's Counter Matching 0 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged-aligned type. | ||
| [16] | CUTRGEN2 | Channel 2 Compare Up Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel2's counter matching CMP2 in up-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect. | ||
| [17] | CPTRGEN2 | Channel 2 Center Point Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel2's counter matching PERIOD2 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect. | ||
| [18] | CDTRGEN2 | Channel 2 Compare Down Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel2's counter matching CMP2 in down-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged-aligned type. | ||
| [19] | ZPTRGEN2 | Channel 2 Zero Point Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel2's counter matching 0 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged-aligned type. | ||
| [24] | CUTRGEN3 | Channel 3 Compare Up Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel3's counter matching CMP3 in up-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged aligned type, setting this bit is meaningless and will not take any effect. | ||
| [25] | CPTRGEN3 | Channel 3 Center Point Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel3's counter matching PERIOD3 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged aligned type, setting this bit is meaningless and will not take any effect. | ||
| [26] | CDTRGEN3 | Channel 3 Compare Down Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel3's counter matching CMP3 in down-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged aligned type. | ||
| [27] | ZPTRGEN3 | Channel 3 Zero Point Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel3's counter matching 0 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged aligned type. |
Definition at line 7373 of file Mini58Series.h.
| __IO uint32_t PWM_T::ADCTCTL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CUTRGEN4 | Channel 4 Compare Up Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel4's counter matching CMP4 in up-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect. | ||
| [1] | CPTRGEN4 | Channel 4 Center Point Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel4's counter matching PERIOD4 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect. | ||
| [2] | CDTRGEN4 | Channel 4 Compare Down Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel4's counter matching CMP4 in down-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged-aligned type. | ||
| [3] | ZPTRGEN4 | Channel 4 Zero Point Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel4's counter matching 0 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged-aligned type. | ||
| [8] | CUTRGEN5 | Channel 5 Compare Up Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel5's counter matching CMP5 in up-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect. | ||
| [9] | CPTRGEN5 | Channel 5 Center Point Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel5's counter matching PERIOD5 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is only valid for PWM in center-aligned type. | ||
| When PWM is in edged-aligned type, setting this bit is meaningless and will not take any effect. | ||
| [10] | CDTRGEN5 | Channel 5 Compare Down Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel5's counter matching CMP5 in down-count direction | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged-aligned type. | ||
| [11] | ZPTRGEN5 | Channel 5 Zero Point Trigger ADC Enable Bit |
| Enable PWM trigger ADC function while channel5's counter matching 0 | ||
| 0 = PWM condition trigger ADC function Disabled. | ||
| 1 = PWM condition trigger ADC function Enabled. | ||
| Note: This bit is valid for both center-aligned type and edged-aligned type. |
Definition at line 7427 of file Mini58Series.h.
| __IO uint32_t PWM_T::ADCTSTS0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CUTRGF0 | Channel 0 Compare Up Trigger ADC Flag |
| When the channel0's counter is counting up to CMP0, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [1] | CPTRGF0 | Channel 0 Center Point Trigger ADC Flag |
| When the channel0's counter is counting to PERIOD0, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [2] | CDTRGF0 | Channel 0 Compare Down Trigger ADC Flag |
| When the channel0's counter is counting down to CMP0, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [3] | ZPTRGF0 | Channel 0 Zero Point Trigger ADC Flag |
| When the channel0's counter is counting to zero point, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [8] | CUTRGF1 | Channel 1 Compare Up Trigger ADC Flag |
| When the channel1's counter is counting up to CMP1, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [9] | CPTRGF1 | Channel 1 Center Point Trigger ADC Flag |
| When the channel1's counter is counting to PERIOD1, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [10] | CDTRGF1 | Channel 1 Compare Down Trigger ADC Flag |
| When the channel1's counter is counting down to CMP1, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [11] | ZPTRGF1 | Channel 1 Zero Point Trigger ADC Flag |
| When the channel1's counter is counting to zero point, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [16] | CUTRGF2 | Channel 2 Compare Up Trigger ADC Flag |
| When the channel2's counter is counting up to CMP2, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [17] | CPTRGF2 | Channel 2 Center Point Trigger ADC Flag |
| When the channel2's counter is counting to PERIOD2, this bit will be set for trigger ADC. Note: | ||
| This bit can be cleared by software writing 1. | ||
| [18] | CDTRGF2 | Channel 2 Compare Down Trigger ADC Flag |
| When the channel2's counter is counting down to CMP2, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [19] | ZPTRGF2 | Channel 2 Zero Point Trigger ADC Enable Bit |
| When the channel2's counter is counting to zero point, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [24] | CUTRGF3 | Channel 3 Compare Up Trigger ADC Flag |
| When the channel3's counter is counting up to CMP3, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [25] | CPTRGF3 | Channel 3 Center Point Trigger ADC Flag |
| When the channel3's counter is counting to PERIOD3, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [26] | CDTRGF3 | Channel 3 Compare Down Trigger ADC Flag |
| When the channel3's counter is counting down to CMP3, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [27] | ZPTRGF3 | Channel 3 Zero Point Trigger ADC Flag |
| When the channel3's counter is counting to zero point, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. |
Definition at line 7485 of file Mini58Series.h.
| __IO uint32_t PWM_T::ADCTSTS1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CUTRGF4 | Channel 4 Compare Up Trigger ADC Flag |
| When the channel4's counter is counting up to CMP4, this bit will be set for trigger ADC. Note: | ||
| This bit can be cleared by software writing 1. | ||
| [1] | CPTRGF4 | Channel 4 Center Point Trigger ADC Flag |
| When the channel4's counter is counting to PERIOD4, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [2] | CDTRGF4 | Channel 4 Compare Down Trigger ADC Flag |
| When the channel4's counter is counting down to CMP4, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [3] | ZPTRGF4 | Channel 4 Zero Point Trigger ADC Flag |
| When the channel4's counter is counting to zero point, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [8] | CUTRGF5 | Channel 5 Compare Up Trigger ADC Flag |
| When the channel5's counter is counting up to CMP5, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [9] | CPTRGF5 | Channel 5 Center Point Trigger ADC Flag |
| When the channel5's counter is counting to PERIOD5, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [10] | CDTRGF5 | Channel 5 Compare Down Trigger ADC Flag |
| When the channel5's counter is counting down to CMP5, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. | ||
| [11] | ZPTRGF5 | Channel 5 Zero Point Trigger ADC Flag |
| When the channel5's counter is counting to zero point, this bit will be set for trigger ADC. | ||
| Note: This bit can be cleared by software writing 1. |
Definition at line 7519 of file Mini58Series.h.
| __IO uint32_t I2C_T::ADDR0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GC | General Call Function Control |
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| [7:1] | ADDR | I2C Address |
| The content of this register is irrelevant when I2C is in Master mode. | ||
| In Slave mode, the seven most significant bits must be loaded with the MCU's own address. | ||
| The I2C hardware will react if either of the address is matched. |
Definition at line 4603 of file Mini58Series.h.
| __IO uint32_t I2C_T::ADDR1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GC | General Call Function Control |
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| [7:1] | ADDR | I2C Address |
| The content of this register is irrelevant when I2C is in Master mode. | ||
| In Slave mode, the seven most significant bits must be loaded with the MCU's own address. | ||
| The I2C hardware will react if either of the address is matched. |
Definition at line 4688 of file Mini58Series.h.
| __IO uint32_t I2C_T::ADDR2 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GC | General Call Function Control |
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| [7:1] | ADDR | I2C Address |
| The content of this register is irrelevant when I2C is in Master mode. | ||
| In Slave mode, the seven most significant bits must be loaded with the MCU's own address. | ||
| The I2C hardware will react if either of the address is matched. |
Definition at line 4705 of file Mini58Series.h.
| __IO uint32_t I2C_T::ADDR3 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GC | General Call Function Control |
| 0 = General Call Function Disabled. | ||
| 1 = General Call Function Enabled. | ||
| [7:1] | ADDR | I2C Address |
| The content of this register is irrelevant when I2C is in Master mode. | ||
| In Slave mode, the seven most significant bits must be loaded with the MCU's own address. | ||
| The I2C hardware will react if either of the address is matched. |
Definition at line 4722 of file Mini58Series.h.
| __IO uint32_t I2C_T::ADDRMSK0 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | ADDRMSK | I2C Address Mask Bits |
| 0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register). | ||
| 1 = I2C address mask Enabled (the received corresponding address bit is "Don't care"). |
Definition at line 4735 of file Mini58Series.h.
| __IO uint32_t I2C_T::ADDRMSK1 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | ADDRMSK | I2C Address Mask Bits |
| 0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register). | ||
| 1 = I2C address mask Enabled (the received corresponding address bit is "Don't care"). |
Definition at line 4748 of file Mini58Series.h.
| __IO uint32_t I2C_T::ADDRMSK2 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | ADDRMSK | I2C Address Mask Bits |
| 0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register). | ||
| 1 = I2C address mask Enabled (the received corresponding address bit is "Don't care"). |
Definition at line 4761 of file Mini58Series.h.
| __IO uint32_t I2C_T::ADDRMSK3 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:1] | ADDRMSK | I2C Address Mask Bits |
| 0 = I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register). | ||
| 1 = I2C address mask Enabled (the received corresponding address bit is "Don't care"). |
Definition at line 4774 of file Mini58Series.h.
| __IO uint32_t CLK_T::AHBCLK |
| Bits | Field | Descriptions |
|---|---|---|
| [2] | ISPCKEN | Flash ISP Controller Clock Enable Bit |
| 0 = Flash ISP peripheral clock Disabled. | ||
| 1 = Flash ISP peripheral clock Enabled. |
Definition at line 889 of file Mini58Series.h.
| __IO uint32_t UART_T::ALTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [8] | RS485_NMM | RS-485 Normal Multi-drop Operation Mode (NMM) Control |
| 0 = RS-485 Normal Multi-drop Operation Mode (NMM) Disabled. | ||
| 1 = RS-485 Normal Multi-drop Operation Mode (NMM) Enabled. | ||
| Note: It cannot be active with RS485_AAD operation mode. | ||
| [9] | RS485_AAD | RS-485 Auto Address Detection Operation Mode (AAD) |
| 0 = RS-485 Auto Address Detection Operation Mode (AAD) Disabled. | ||
| 1 = RS-485 Auto Address Detection Operation Mode (AAD) Enabled. | ||
| Note: It cannot be active with RS485_NMM operation mode. | ||
| [10] | RS485_AUD | RS-485 Auto Direction Mode (AUD) Control |
| 0 = RS-485 Auto Direction Function Mode (AUD) Disabled. | ||
| 1 = RS-485 Auto Direction Function Mode (AUD) Enabled. | ||
| Note: It cannot be active with RS485_NMM operation mode. | ||
| [15] | ADDRDEN | RS-485 Address Detection Enable Bit |
| This bit is used to enable RS-485 Address Detection mode. | ||
| 0 = RS-485 address detection mode Disabled. | ||
| 1 = RS-485 address detection mode Enabled. | ||
| Note: This field is used for RS-485 any operation mode. | ||
| [31:24] | ADDRMV | Address Match Values |
| This field contains the RS-485 address match values. | ||
| Note: This field is used for RS-485 auto address detection mode. |
Definition at line 11141 of file Mini58Series.h.
| __IO uint32_t WDT_T::ALTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | RSTDSEL | WDT Reset Delay Selection (Write Protect) |
| When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened. | ||
| User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. | ||
| 00 = WDT Reset Delay Period is 1026 * WDT_CLK. | ||
| 01 = WDT Reset Delay Period is 130 * WDT_CLK. | ||
| 10 = WDT Reset Delay Period is 18 * WDT_CLK. | ||
| 11 = WDT Reset Delay Period is 3 * WDT_CLK. | ||
| Note1: This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| Note2: This register will be reset to 0 if WDT time-out reset happened. |
Definition at line 11473 of file Mini58Series.h.
| __IO uint32_t CLK_T::APBCLK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WDTCKEN | Watchdog Timer Clock Enable Bit (Write Protect) |
| 0 = Watchdog Timer clock Disabled. | ||
| 1 = Watchdog Timer clock Enabled. | ||
| Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address SYS_BA + 0x10. | ||
| [2] | TMR0CKEN | Timer0 Clock Enable Bit |
| 0 = Timer0 clock Disabled. | ||
| 1 = Timer0 clock Enabled. | ||
| [3] | TMR1CKEN | Timer1 Clock Enable Bit |
| 0 = Timer1 clock Disabled. | ||
| 1 = Timer1 clock Enabled. | ||
| [6] | CLKOCKEN | Frequency Divider Output Clock Enable Bit |
| 0 = CLKO clock Disabled. | ||
| 1 = CLKO clock Enabled. | ||
| [8] | I2C0CKEN | I2C0 Clock Enable Bit |
| 0 = I2C0 clock Disabled. | ||
| 1 = I2C0 clock Enabled. | ||
| [9] | I2C1CKEN | I2C1 Clock Enable Bit |
| 0 = I2C1 clock Disabled. | ||
| 1 = I2C1 clock Enabled. | ||
| [12] | SPICKEN | SPI Clock Enable Bit |
| 0 = SPI peripheral clock Disabled. | ||
| 1 = SPI peripheral clock Enabled. | ||
| [16] | UART0CKEN | UART0 Clock Enable Bit |
| 0 = UART0 clock Disabled. | ||
| 1 = UART0 clock Enabled. | ||
| [17] | UART1CKEN | UART1 Clock Enable Bit |
| 0 = UART1 clock Disabled. | ||
| 1 = UART1 clock Enabled. | ||
| [20] | PWMCH01CKEN | PWM_01 Clock Enable Bit |
| 0 = PWM01 clock Disabled. | ||
| 1 = PWM01 clock Enabled. | ||
| [21] | PWMCH23CKEN | PWM_23 Clock Enable Bit |
| 0 = PWM23 clock Disabled. | ||
| 1 = PWM23 clock Enabled. | ||
| [22] | PWMCH45CKEN | PWM_45 Clock Enable Bit |
| 0 = PWM45 clock Disabled. | ||
| 1 = PWM45 clock Enabled. | ||
| [28] | ADCCKEN | Analog-digital-converter (ADC) Clock Enable Bit |
| 0 = ADC peripheral clock Disabled. | ||
| 1 = ADC peripheral clock Enabled. | ||
| [30] | ACMPCKEN | Analog Comparator Clock Enable Bit |
| 0 = Analog Comparator clock Disabled. | ||
| 1 = Analog Comparator clock Enabled. |
Definition at line 943 of file Mini58Series.h.
| __IO uint32_t UART_T::BAUD |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | BRD | Baud Rate Divider |
| The field indicates the baud rate divider. | ||
| [27:24] | EDIVM1 | Divider X |
| The baud rate divider M = X+1. | ||
| [28] | BAUDM0 | Divider X Equal 1 |
| 0 = Divider M = X (the equation of M = X+1, but EDIVM1[27:24] must >= 8). | ||
| 1 = Divider M = 1 (the equation of M = 1, but BRD [15:0] must >= 8). | ||
| Note: Refer to section "UART Controller Baud Rate Generator" for more information. | ||
| [29] | BAUDM1 | Divider X Enable Bit |
| The BRD = Baud Rate Divider, and the baud rate equation is: | ||
| Baud Rate = Clock / [M * (BRD + 2)], The default value of M is 16. | ||
| 0 = Divider X Disabled (the equation of M = 16). | ||
| 1 = Divider X Enabled (the equation of M = X+1, but EDIVM1 [27:24] must >= 8). | ||
| Note: In IrDA mode, this bit must be disabled. |
Definition at line 11092 of file Mini58Series.h.
| __IO uint32_t SYS_T::BODCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BODEN | Brown-out Detector Selection Extension (Initiated & Write-protected Bit) |
| The default value is set by flash controller user configuration register config0 bit[23]. | ||
| If config0 bit[23] is set to 1, default value of BODEN is 0. | ||
| If config0 bit[23] is set to 0, default value of BODEN is 1. | ||
| 0 = Brown-out detector threshold voltage is selected by the table defined in BODVL. | ||
| 1 = Brown-out detector threshold voltage is selected by the table defined as below. | ||
| BODVL = 00 = Brown-out Detector threshold voltage is 2.2V. | ||
| BODVL = 01 = Brown-out Detector threshold voltage is 2.7V. | ||
| BODVL = 10 = Brown-out Detector threshold voltage is 3.7V. | ||
| BODVL = 11 = Brown-out Detector threshold voltage is 4.4V. | ||
| [2:1] | BODVL | Brown-out Detector Threshold Voltage Selection (Write Protect) |
| The default value is set by flash controller user configuration register CBOV (CONFIG0[22:21]). | ||
| 00 = Reserved. | ||
| 01 = Brown-out Detector threshold voltage is 2.7V. | ||
| 10 = Brown-out Detector threshold voltage is 3.7V. | ||
| 11 = Brown-out Detector function Disabled. | ||
| [3] | BODRSTEN | Brown-out Reset Enable Bit (Write Protect) |
| The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit. | ||
| 0 = Brown-out "INTERRUPT" function Enabled; when the Brown-out Detector function is enable and the detected voltage is lower than the threshold, then assert a signal to interrupt the Cortex-M0 CPU. | ||
| 1 = Brown-out "RESET" function Enabled; when the Brown-out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to reset the chip. | ||
| Note: When the BOD_EN is enabled and the interrupt is asserted, the interrupt will be kept till the BOD_EN is set to 0. | ||
| The interrupt for CPU can be blocked by disabling the NVIC in CPU for BOD interrupt or disable the interrupt source by disabling the BOD_EN and then re-enabling the BOD_EN function if the BOD function is require. | ||
| [4] | BODIF | Brown-out Detector Interrupt Flag |
| 0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. | ||
| 1 = When Brown-out Detector detects the VDD is dropped through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled. | ||
| [5] | BODLPM | Brown-out Detector Low Power Mode (Write Protect) |
| 0 = BOD operate in normal mode (default). | ||
| 1 = BOD Low Power mode Enabled. | ||
| Note: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. | ||
| [6] | BODOUT | Brown-out Detector Output Status |
| 0 = Brown-out Detector status output is 0, the detected voltage is higher than BODVL setting. | ||
| 1 = Brown-out Detector status output is 1, the detected voltage is lower than BODVL setting. |
Definition at line 9634 of file Mini58Series.h.
| __IO uint32_t PWM_T::BRKCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | BRK0EN | Enable BKP0 Pin Trigger Fault Brake Function 0 |
| 0 = Disabling BKP0 pin can trigger brake function 0 (EINT0 or CPO1). | ||
| 1 = Enabling a falling at BKP0 pin can trigger brake function 0. | ||
| [1] | BRK1EN | Enable BKP1 Pin Trigger Fault Brake Function 1 |
| 0 = Disabling BKP1 pin can trigger brake function 1 (EINT1 or CPO0). | ||
| 1 = Enabling a falling at BKP1 pin can trigger brake function 1. | ||
| [2] | BRK0SEL | BKP1 Fault Brake Function Source Select Bit |
| 0 = EINT1 as one brake source in BKP1. | ||
| 1 = CPO0 as one brake source in BKP1. | ||
| [3] | BRK1SEL | BKP0 Fault Brake Function Source Select Bit |
| 0 = EINT0 as one brake source in BKP0. | ||
| 1 = CPO1 as one brake source in BKP0. | ||
| [7] | BRKSTS | PWM Fault Brake Event Status Flag |
| 0 = PWM output initial state when fault brake conditions asserted. | ||
| 1 = PWM output fault brake state when fault brake conditions asserted. | ||
| Note: This bit can be cleared by software writing 1 and must be cleared before restarting the PWM counter. | ||
| [8] | BRKACT | PWM Brake Action Type |
| 0 = PWM counter stop when brake is asserted. | ||
| 1 = PWM counter keep going when brake is asserted. | ||
| [9] | SWBRK | Software Brake |
| 0 = Disable PWM Software brake and back to normal PWM function. | ||
| 1 = Assert PWM Brake immediately. | ||
| [29:24] | BKOD0 | PWM Brake Output Data Select Bits |
| 0 = PWM channel n output low when fault brake conditions asserted. | ||
| 1 = PWM channel n output high when fault brake conditions asserted. | ||
| [29:24] | BKOD1 | PWM Brake Output Data Select Bits |
| 0 = PWM channel n output low when fault brake conditions asserted. | ||
| 1 = PWM channel n output high when fault brake conditions asserted. | ||
| [29:24] | BKOD2 | PWM Brake Output Data Select Bits |
| 0 = PWM channel n output low when fault brake conditions asserted. | ||
| 1 = PWM channel n output high when fault brake conditions asserted. | ||
| [29:24] | BKOD3 | PWM Brake Output Data Select Bits |
| 0 = PWM channel n output low when fault brake conditions asserted. | ||
| 1 = PWM channel n output high when fault brake conditions asserted. | ||
| [29:24] | BKOD4 | PWM Brake Output Data Select Bits |
| 0 = PWM channel n output low when fault brake conditions asserted. | ||
| 1 = PWM channel n output high when fault brake conditions asserted. | ||
| [29:24] | BKOD5 | PWM Brake Output Data Select Bits |
| 0 = PWM channel n output low when fault brake conditions asserted. | ||
| 1 = PWM channel n output high when fault brake conditions asserted. | ||
| [30] | D6BKOD | Channel 6 Brake Output Data Select Bit |
| 0 = Channel 6 output low when fault brake conditions asserted. | ||
| 1 = Channel 6 output high when fault brake conditions asserted. | ||
| [31] | D7BKOD | Channel 7 Brake Output Data Select Bit |
| 0 = Channel 7 output low when fault brake conditions asserted. | ||
| 1 = Channel 7 output high when fault brake conditions asserted. |
Definition at line 7256 of file Mini58Series.h.
| __I uint32_t TIMER_T::CAP |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CAPDAT | Timer Capture Data Register |
| When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. |
Definition at line 10449 of file Mini58Series.h.
| __IO uint32_t ADC_T::CHEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CHEN0 | Analog Input Channel 0 Enable Bit |
| 0 = Channel 0 Disabled. | ||
| 1 = Channel 0 Enabled. | ||
| Note: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored. | ||
| [1] | CHEN1 | Analog Input Channel 1 Enable Bit |
| 0 = Channel 1 Disabled. | ||
| 1 = Channel 1 Enabled. | ||
| [2] | CHEN2 | Analog Input Channel 2 Enable Bit |
| 0 = Channel 2 Disabled. | ||
| 1 = Channel 2 Enabled. | ||
| [3] | CHEN3 | Analog Input Channel 3 Enable Bit |
| 0 = Channel 3 Disabled. | ||
| 1 = Channel 3 Enabled. | ||
| [4] | CHEN4 | Analog Input Channel 4 Enable Bit |
| 0 = Channel 4 Disabled. | ||
| 1 = Channel 4 Enabled. | ||
| [5] | CHEN5 | Analog Input Channel 5 Enable Bit |
| 0 = Channel 5 Disabled. | ||
| 1 = Channel 5 Enabled. | ||
| [6] | CHEN6 | Analog Input Channel 6 Enable Bit |
| 0 = Channel 6 Disabled. | ||
| 1 = Channel 6 Enabled. | ||
| [7] | CHEN7 | Analog Input Channel 7 Enable Bit |
| 0 = Channel 7 Disabled. | ||
| 1 = Channel 7 Enabled. | ||
| [8] | CH7SEL | Analog Input Channel 7 Selection |
| 0 = External analog input. | ||
| 1 = Internal band-gap voltage (VBG). | ||
| Note: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz. |
Definition at line 426 of file Mini58Series.h.
| __IO uint32_t CLK_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | HCLKDIV | HCLK Clock Divide Number From HCLK Clock Source |
| HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). | ||
| [11:8] | UARTDIV | UART Clock Divide Number From UART Clock Source |
| UART clock frequency = (UART clock source frequency) / (UARTDIV + 1). | ||
| [23:16] | ADCDIV | ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source |
| ADC peripheral clock frequency = (ADC peripheral clock source frequency) / (ADCDIV + 1). |
Definition at line 1088 of file Mini58Series.h.
| __IO uint32_t I2C_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DIVIDER | I2C Clock Divided Register |
| The I2C clock rate bits: Data Baud Rate of I2C = (system clock) / (4 * (I2C_CLKDIV+1)). | ||
| Note: The minimum value of I2C_CLKDIV is 4. |
Definition at line 4649 of file Mini58Series.h.
| __IO uint32_t PWM_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | CLKDIV0 | Counter 0 Clock Divider Selection |
| Select clock input for PWM counter. | ||
| 000 = Clock input / (CLKPSC01/2). | ||
| 001 = Clock input / (CLKPSC01/4). | ||
| 010 = Clock input / (CLKPSC01/8). | ||
| 011 = Clock input / (CLKPSC01/16). | ||
| 100 = Clock input / CLKPSC01. | ||
| Others = Clock input. | ||
| [6:4] | CLKDIV1 | Counter 1 Clock Divider Selection |
| Select clock input for PWM counter. | ||
| 000 = Clock input / (CLKPSC01/2). | ||
| 001 = Clock input / (CLKPSC01/4). | ||
| 010 = Clock input / (CLKPSC01/8). | ||
| 011 = Clock input / (CLKPSC01/16). | ||
| 100 = Clock input / CLKPSC01. | ||
| Others = Clock input. | ||
| [10:8] | CLKDIV2 | Counter 2 Clock Divider Selection |
| Select clock input for PWM counter. | ||
| 000 = Clock input / (CLKPSC23/2). | ||
| 001 = Clock input / (CLKPSC23/4). | ||
| 010 = Clock input / (CLKPSC23/8). | ||
| 011 = Clock input / (CLKPSC23/16). | ||
| 100 = Clock input / CLKPSC23. | ||
| Others = Clock input. | ||
| [14:12] | CLKDIV3 | Counter 3 Clock Divider Selection |
| Select clock input for PWM counter. | ||
| 000 = Clock input / (CLKPSC23/2). | ||
| 001 = Clock input / (CLKPSC23/4). | ||
| 010 = Clock input / (CLKPSC23/8). | ||
| 011 = Clock input / (CLKPSC23/16). | ||
| 100 = Clock input / CLKPSC23. | ||
| Others = Clock input. | ||
| [18:16] | CLKDIV4 | Counter 4 Clock Divider Selection |
| Select clock input for PWM counter. | ||
| 000 = Clock input / (CLKPSC45/2). | ||
| 001 = Clock input / (CLKPSC45/4). | ||
| 010 = Clock input / (CLKPSC45/8). | ||
| 011 = Clock input / (CLKPSC45/16). | ||
| 100 = Clock input / CLKPSC45. | ||
| Others = Clock input. | ||
| [22:20] | CLKDIV5 | Counter 5 Clock Divider Selection |
| Select clock input for PWM counter. | ||
| 000 = Clock input / (CLKPSC45/2). | ||
| 001 = Clock input / (CLKPSC45/4). | ||
| 010 = Clock input / (CLKPSC45/8). | ||
| 011 = Clock input / (CLKPSC45/16). | ||
| 100 = Clock input / CLKPSC45. | ||
| Others = Clock input. |
Definition at line 5460 of file Mini58Series.h.
| __IO uint32_t SPI_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DIVIDER | Clock Divider Register (Master Only) |
| The value in this field is the frequency divider to determine the SPI peripheral clock frequency fspi, and the SPI master's bus clock frequency on the SPI_CLK output pin. | ||
| The frequency is obtained according to the following equation: | ||
| If the bit of DIVMOD, SPI_SLVCTL[31], is set to 0. | ||
| else if DIVMOD is set to 1, | ||
| where | ||
| is the SPI peripheral clock source which is defined in the CLK_CLKSEL1 register. |
Definition at line 9078 of file Mini58Series.h.
| __IO uint32_t CLK_T::CLKOCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | FREQSEL | Divider Output Frequency Selection |
| The formula of output frequency is | ||
| Fout = Fin/2(N+1). | ||
| Fin is the input clock frequency. | ||
| Fout is the frequency of divider output clock. | ||
| N is the 4-bit value of FREQSEL(CLK_CLKOCTL[3:0]). | ||
| [4] | CLKOEN | Frequency Divider Enable Bit |
| 0 = Frequency Divider Disabled. | ||
| 1 = Frequency Divider Enabled. | ||
| [5] | DIV1EN | Frequency Divider One Enable Bit |
| 0 = Divider output frequency is depended on FREQSEL value. | ||
| 1 = Divider output frequency is the same as input clock frequency. |
Definition at line 1166 of file Mini58Series.h.
| __IO uint32_t PWM_T::CLKPSC |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CLKPSC01 | Clock Prescaler 0 For PWM Counter 0 And 1 |
| Clock input is divided by (CLKPSC01 + 1) before it is fed to the corresponding PWM counter. | ||
| If CLKPSC01 = 0, the clock prescaler 0 output clock will be stopped. | ||
| So the corresponding PWM counter will also be stopped. | ||
| [15:8] | CLKPSC23 | Clock Prescaler 2 For PWM Counter 2 And 3 |
| Clock input is divided by (CLKPSC23 + 1) before it is fed to the corresponding PWM counter. | ||
| If CLKPSC23 = 0, the clock prescaler 2 output clock will be stopped. | ||
| So the corresponding PWM counter will also be stopped. | ||
| [23:16] | CLKPSC45 | Clock Prescaler 4 For PWM Counter 4 And 5 |
| Clock input is divided by (CLKPSC45 + 1) before it is fed to the corresponding PWM counter. | ||
| If CLKPSC45 = 0, the clock prescaler 4 output clock will be stopped. | ||
| So the corresponding PWM counter will also be stopped. |
Definition at line 5402 of file Mini58Series.h.
| __IO uint32_t CLK_T::CLKSEL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | HCLKSEL | HCLK Clock Source Selection (Write Protect) |
| 000 = Clock source is from HXT or LXT. | ||
| 001 = Reserved. | ||
| 010 = Clock source is from PLL. | ||
| 011 = Clock source is from LIRC. | ||
| 111 = Clock source is from HIRC. | ||
| Others = Reserved. | ||
| Note1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn-on and stable. | ||
| Note2: These bits are protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address SYS_BA + 0x10. | ||
| Note3: To set CLK_PWRCTL[1:0] to select HXT or LXT crystal clock. | ||
| [5:3] | STCLKSEL | Cortex-M0 SysTick Clock Source Selection (Write Protect) |
| If CLKSRC (SYST_CSR[2]) = 1, SysTick clock source is from HCLK. | ||
| If CLKSRC (SYST_CSR[2]) = 0, SysTick clock source is defined by below settings. | ||
| 000 = Clock source is from HXT or LXT. | ||
| 001 = Reserved. | ||
| 010 = Clock source is from HXT/2 or LXT/2. | ||
| 011 = Clock source is from HCLK/2. | ||
| 111 = Clock source is from HIRC/2. | ||
| Others = Reserved. | ||
| Note1: These bits are protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address SYS_BA + 0x10. | ||
| Note2: If the SysTick clock source is not from HCLK (i.e. | ||
| CLKSRC(SYST_CSR[2]) = 0), SysTick clock source must less than or equal to HCLK/. | ||
| Note3: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. |
Definition at line 1008 of file Mini58Series.h.
| __IO uint32_t CLK_T::CLKSEL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | WDTSEL | WDT CLK Clock Source Selection (Write Protect) |
| 00 = Clock source is from HXT or LXT. | ||
| 01 = Reserved. | ||
| 10 = Clock source is from HCLK/2048 clock. | ||
| 11 = Clock source is from LIRC. | ||
| Note1: These bits are the protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address SYS_BA + 0x10. | ||
| Note2: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. | ||
| [3:2] | ADCSEL | ADC Peripheral Clock Source Selection |
| 00 = Clock source is from HXT or LXT. | ||
| 01 = Clock source is from PLL. | ||
| 10 = Clock source is from HCLK. | ||
| 11 = Clock source is from HIRC. | ||
| Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. | ||
| [5:4] | SPISEL | SPI Clock Source Selection |
| 00 = Clock source is from HXT or LXT. | ||
| 01 = Clock source is from HCLK. | ||
| 10 = Clock source is from PLL. | ||
| 11 = Reserved. | ||
| Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. | ||
| [10:8] | TMR0SEL | TIMER0 Clock Source Selection |
| 000 = Clock source is from HXT or LXT. | ||
| 001 = Clock source is from LIRC. | ||
| 010 = Clock source is from HCLK. | ||
| 011 = Clock source is from external trigger. | ||
| 111 = Clock source is from HIRC. | ||
| Others = Reserved. | ||
| Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. | ||
| [14:12] | TMR1SEL | TIMER1 Clock Source Selection |
| 000 = Clock source is from HXT or LXT. | ||
| 001 = Clock source is from LIRC. | ||
| 010 = Clock source is from HCLK. | ||
| 011 = Clock source is from external trigger. | ||
| 111 = Clock source is from HIRC. | ||
| Others = Reserved. | ||
| Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. | ||
| [25:24] | UARTSEL | UART Clock Source Selection |
| 00 = Clock source is from HXT or LXT. | ||
| 01 = Clock source is from PLL. | ||
| 10 = Clock source is from HIRC. | ||
| 11 = Clock source is from HIRC. | ||
| Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. | ||
| [29:28] | PWMCH01SEL | PWM0 And PWM1 Clock Source Selection |
| PWM0 and PWM1 use the same peripheral clock source. Both of them use the same prescaler. | ||
| 00 = Reserved. | ||
| 01 = Reserved. | ||
| 10 = Clock source is from HCLK. | ||
| 11 = Reserved. | ||
| [31:30] | PWMCH23SEL | PWM2 And PWM3 Clock Source Selection |
| PWM2 and PWM3 use the same peripheral clock source; Both of them use the same prescaler. | ||
| 00 = Reserved. | ||
| 01 = Reserved. | ||
| 10 = Clock source is from HCLK. | ||
| 11 = Reserved. |
Definition at line 1072 of file Mini58Series.h.
| __IO uint32_t CLK_T::CLKSEL2 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:2] | CLKOSEL | Clock Divider Clock Source Selection |
| 00 = Clock source is from HXT or LXT. | ||
| 01 = Clock source is from LIRC. | ||
| 10 = Clock source is from HCLK. | ||
| 11 = Clock source is from HIRC. | ||
| Note: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock. | ||
| [5:4] | PWMCH45SEL | PWM4 And PWM5 Clock Source Selection |
| PWM4 and PWM5 use the same peripheral clock source; Both of them use the same prescaler. | ||
| 00 = Reserved. | ||
| 01 = Reserved. | ||
| 10 = Clock source is from HCLK. | ||
| 11 = Reserved. | ||
| [17:16] | WWDTSEL | Window Watchdog Timer Clock Source Selection |
| 00 = Reserved. | ||
| 01 = Reserved. | ||
| 10 = Clock source from HCLK/2048 clock. | ||
| 11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). |
Definition at line 1115 of file Mini58Series.h.
| __IO uint32_t TIMER_T::CMP |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CMPDAT | Timer Compared Value |
| CMPDAT is a 24-bit compared value register. | ||
| When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to . | ||
| Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). | ||
| Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. | ||
| Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. | ||
| But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into the CMPDAT fiel. |
Definition at line 10403 of file Mini58Series.h.
| __IO uint32_t ADC_T::CMP0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCMPEN | A/D Compare Enable Bit |
| Set 1 to this bit to enable comparing CMPDAT (ADC_CMPx[25:16]) with specified channel conversion results when converted data is loaded into the ADC_DAT register. | ||
| 0 = Compare function Disabled. | ||
| 1 = Compare function Enabled. | ||
| [1] | ADCMPIE | A/D Compare Interrupt Enable Bit |
| If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, ADCMPIE bit will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. | ||
| 0 = Compare function interrupt Disabled. | ||
| 1 = Compare function interrupt Enabled. | ||
| [2] | CMPCOND | Compare Condition |
| 0 = Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPDAT (ADC_CMPx[25:16]), the internal match counter will increase one. | ||
| 1 = Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPDAT (ADC_CMPx[25:16]), the internal match counter will increase one. | ||
| Note: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set. | ||
| [5:3] | CMPCH | Compare Channel Selection |
| Set this field to select which channel's result to be compared. | ||
| Note: Valid setting of this field is channel 0~7. | ||
| [11:8] | CMPMCNT | Compare Match Count |
| When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. | ||
| When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set. | ||
| [25:16] | CMPDAT | Comparison Data |
| The 10-bit data is used to compare with conversion result of specified channel. |
Definition at line 456 of file Mini58Series.h.
| __IO uint32_t ADC_T::CMP1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCMPEN | A/D Compare Enable Bit |
| Set 1 to this bit to enable comparing CMPDAT (ADC_CMPx[25:16]) with specified channel conversion results when converted data is loaded into the ADC_DAT register. | ||
| 0 = Compare function Disabled. | ||
| 1 = Compare function Enabled. | ||
| [1] | ADCMPIE | A/D Compare Interrupt Enable Bit |
| If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, ADCMPIE bit will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. | ||
| 0 = Compare function interrupt Disabled. | ||
| 1 = Compare function interrupt Enabled. | ||
| [2] | CMPCOND | Compare Condition |
| 0 = Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPDAT (ADC_CMPx[25:16]), the internal match counter will increase one. | ||
| 1 = Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPDAT (ADC_CMPx[25:16]), the internal match counter will increase one. | ||
| Note: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set. | ||
| [5:3] | CMPCH | Compare Channel Selection |
| Set this field to select which channel's result to be compared. | ||
| Note: Valid setting of this field is channel 0~7. | ||
| [11:8] | CMPMCNT | Compare Match Count |
| When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. | ||
| When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx bit will be set. | ||
| [25:16] | CMPDAT | Comparison Data |
| The 10-bit data is used to compare with conversion result of specified channel. |
Definition at line 486 of file Mini58Series.h.
| __IO uint32_t PWM_T::CMPDAT0 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CMP0 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP1 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP2 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP3 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP4 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP5 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [31:16] | CMPD0 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD1 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD2 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD3 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD4 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD5 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. |
Definition at line 6333 of file Mini58Series.h.
| __IO uint32_t PWM_T::CMPDAT1 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CMP0 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP1 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP2 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP3 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP4 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP5 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [31:16] | CMPD0 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD1 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD2 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD3 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD4 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD5 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. |
Definition at line 6463 of file Mini58Series.h.
| __IO uint32_t PWM_T::CMPDAT2 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CMP0 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP1 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP2 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP3 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP4 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP5 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [31:16] | CMPD0 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD1 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD2 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD3 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD4 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD5 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. |
Definition at line 6593 of file Mini58Series.h.
| __IO uint32_t PWM_T::CMPDAT3 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CMP0 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP1 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP2 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP3 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP4 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP5 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [31:16] | CMPD0 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD1 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD2 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD3 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD4 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD5 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. |
Definition at line 6723 of file Mini58Series.h.
| __IO uint32_t PWM_T::CMPDAT4 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CMP0 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP1 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP2 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP3 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP4 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP5 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [31:16] | CMPD0 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD1 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD2 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD3 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD4 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD5 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. |
Definition at line 6853 of file Mini58Series.h.
| __IO uint32_t PWM_T::CMPDAT5 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CMP0 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP1 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP2 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP3 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP4 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [15:0] | CMP5 | PWM Comparator Register |
| CMP determines the PWM duty. | ||
| Edge-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider))/( PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (CMPn+1)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always high. | ||
| CMPn < PERIODn: PWM low width = (PERIODn-CMPn) unit; PWM high width = (CMP+1) unit. | ||
| CMPn = 0: PWM low width = (PERIODn) unit; PWM high width = 1 unit. | ||
| Center-aligned type: | ||
| PWM frequency = HCLK/((CLKPSCnm+1)*(clock divider)) /(2*PERIODn+1); where nm, could be 01, 23, 45 depending on the selected PWM channel. | ||
| Duty ratio = (PERIODn - CMPn)/(PERIODn+1). | ||
| CMPn >= PERIODn: PWM output is always low. | ||
| CMPn < PERIODn: PWM low width = (CMPn + 1) * 2 unit; PWM high width = (PERIODn - CMPn) * 2 unit. | ||
| CMPn = 0: PWM low width = 2 unit; PWM high width = (PERIODn) * 2 unit. | ||
| (Unit = One PWM clock cycle). | ||
| Note: Any write to CMPn will take effect in the next PWM cycle. | ||
| [31:16] | CMPD0 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD1 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD2 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD3 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD4 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. | ||
| [31:16] | CMPD5 | PWM Comparator Register For Down Counter In Asymmetric Mode |
| CMPn >= PERIODn: up counter PWM output is always low. | ||
| CMPDn >= PERIODn: down counter PWM output is always low. | ||
| Others: PWM output is always high. |
Definition at line 6983 of file Mini58Series.h.
| __I uint32_t TIMER_T::CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CNT | Timer Data Register |
| This field can be reflected the internal 24-bit timer counter value or external event input counter value from TMx (x=0~1) pin. | ||
| If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24- bit counter value. | ||
| If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24- bit event input counter value. |
Definition at line 10437 of file Mini58Series.h.
| __I uint32_t WWDT_T::CNT |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CNTDAT | WWDT Counter Value |
| CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. |
Definition at line 11617 of file Mini58Series.h.
| __IO uint32_t INTR_T::CON |
| Bits | Field | Descriptions |
|---|---|---|
| [4:0] | NMI_SEL | NMI Interrupt Source Select Bit |
| The NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL. | ||
| [8] | NMI_SEL_EN | NMI Interrupt Enable Bit (Write Protected) |
| 0 = NMI interrupt Disabled. | ||
| 1 = NMI interrupt Enabled. | ||
| Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. | ||
| Refer to the register SYS_REGLCTL at address SYS_BA+0x10. |
Definition at line 5262 of file Mini58Series.h.
| __IO uint32_t ACMP_T::CTL[2] |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ACMPEN | Analog Comparator x Enable Bit |
| 0 = Analog Comparator x Disabled. | ||
| 1 = Analog Comparator x Enabled. | ||
| Note: Analog comparator output needs to wait 2 us stable time after this bit is set. | ||
| [1] | ACMPIE | Analog Comparator x Interrupt Enable Bit |
| 0 = Interrupt function Disabled. | ||
| 1 = Interrupt function Enabled. | ||
| [2] | HYSSEL | Analog Comparator x Hysteresis Select Bit |
| 0 = Hysteresis function Disabled. | ||
| 1 = Hysteresis function Enabled. | ||
| [4] | NEGSEL | Analog Comparator x Negative Input Select Bit |
| 0 = The source of the negative comparator input is from CPNx pin. | ||
| 1 = The source of the negative comparator input is from internal band-gap voltage or comparator reference voltage. | ||
| [8] | RTRGEN | Analog Comparator x Rising Edge Trigger Enable Bit |
| 0 = Analog comparator rising edge trigger PWM or Timer enabled. | ||
| 1 = Analog comparator rising edge trigger disabled. | ||
| Note: The bit is only effective while analog comparator x triggers PWM or Timer. | ||
| [9] | FTRGEN | Analog Comparator x Falling Edge Trigger Enable |
| 0 = Analog comparator falling edge trigger PWM or Timer enabled. | ||
| 1 = Analog comparator falling edge trigger disabled. | ||
| Note: The bit is only effective while analog comparator x triggers PWM or Timer. | ||
| [23:20] | FILTSEL | Comparator Output Filter Count Selection |
| 0000 = Filter function is Disabled. | ||
| 0001 = ACMP0 output is sampled 1 consecutive PCLK. | ||
| 0010 = ACMP0 output is sampled 2 consecutive PCLKs. | ||
| 0011 = ACMP0 output is sampled 4 consecutive PCLKs. | ||
| 0100 = ACMP0 output is sampled 8 consecutive PCLKs. | ||
| 0101 = ACMP0 output is sampled 16 consecutive PCLKs. | ||
| 0110 = ACMP0 output is sampled 32 consecutive PCLKs. | ||
| 0111 = ACMP0 output is sampled 64 consecutive PCLKs. | ||
| 1000 = ACMP0 output is sampled 128 consecutive PCLKs. | ||
| 1001 = ACMP0 output is sampled 256 consecutive PCLKs. | ||
| 1010 = ACMP0 output is sampled 512 consecutive PCLKs. | ||
| Others = Reserved. | ||
| [30:29] | POSSEL | Analog Comparator Positive Input Selection |
| 00 = ACMP0_Px is from ACMPx_P0 pin. | ||
| 01 = ACMP0_Px is from ACMPx_P1 pin. | ||
| 10 = ACMP0_Px is from ACMPx_P2 pin. | ||
| 11 = ACMP0_Px is from ACMPx_P3 pin. |
Definition at line 213 of file Mini58Series.h.
| __IO uint32_t ADC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ADCEN | A/D Converter Enable Bit |
| 0 = A/D Converter Disabled. | ||
| 1 = A/D Converter Enabled. | ||
| Note: Before starting A/D conversion function, this bit should be set to 1. | ||
| Clear it to 0 to disable A/D converter analog circuit to save power consumption. | ||
| [1] | ADCIEN | A/D Interrupt Enable Bit |
| A/D conversion end interrupt request is generated if ADCIEN bit is set to 1. | ||
| 0 = A/D interrupt function Disabled. | ||
| 1 = A/D interrupt function Enabled. | ||
| [5:4] | HWTRGSEL | Hardware Trigger Source Select Bit |
| 00 = A/D conversion is started by external STADC pin. | ||
| 11 = A/D conversion is started by PWM trigger. | ||
| Others = Reserved. | ||
| Note: Software should disable TRGEN and SWTRG before change TRGS. | ||
| [6] | HWTRGCOND | Hardware External Trigger Condition |
| This bit decides whether the external pin STADC trigger event is falling or raising edge. | ||
| The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigge. | ||
| 0 = Falling edge. | ||
| 1 = Raising edge. | ||
| [8] | HWTRGEN | Hardware External Trigger Enable Bit |
| Enable or disable triggering of A/D conversion by external STADC pin. | ||
| If external trigger is enabled, the SWTRG bit can be set to 1 by the selected hardware trigger sourc. | ||
| 0= External trigger Disabled. | ||
| 1= External trigger Enabled. | ||
| [11] | SWTRG | Software Trigger A/D Conversion Start |
| SWTRG bit can be set to 1 from two sources: software and external pin STADC. | ||
| SWTRG will be cleared to 0 by hardware automatically after conversion complet. | ||
| 0 = Conversion stopped and A/D converter entered idle state. | ||
| 1 = Conversion start. |
Definition at line 387 of file Mini58Series.h.
| __IO uint32_t I2C_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [2] | AA | Assert Acknowledge Control Bit |
| When AA=1 is prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter. | ||
| When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. | ||
| [3] | SI | I2C Interrupt Flag |
| When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL[7]) is set, the I2C interrupt is requested. | ||
| SI must be cleared by software. | ||
| This bit can be cleared by software writing '1'. | ||
| [4] | STO | I2C STOP Control Bit |
| In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. | ||
| In Slave mode, setting STO resets I2C hardware to the defined "not addressed" Slave mode. | ||
| This means it is NO LONGER in the Slave receiver mode to receive data from the master transmit device. | ||
| [5] | STA | I2C START Control Bit |
| Set STA to logic 1 to enter Master mode. | ||
| I2C hardware sends a START or repeats the START condition to bus when the bus is free. | ||
| [6] | I2CEN | I2C Controller Enable Bit |
| 0 = I2C Controller Disabled. | ||
| 1 = I2C Controller Enabled. | ||
| Set to enable I2C serial function controller. | ||
| When I2CEN=1 the I2C serial function enables. | ||
| The function of multi-function pin must be set to I2C firs. | ||
| [7] | INTEN | Interrupt Enable Bit |
| 0 = I2C interrupt Disabled. | ||
| 1 = I2C interrupt Enabled. |
Definition at line 4586 of file Mini58Series.h.
| __IO uint32_t PWM_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CNTEN0 | PWM Counter 0 Enable Start Run |
| 0 = Corresponding PWM counter running Stopped. | ||
| 1 = Corresponding PWM counter start run Enabled. | ||
| [1] | DBGTRIOFF | Disable PWM Output Tri-state Under Debug Mode (Available In DEBUG Mode Only) |
| 0 = Safe mode: The counter is frozen and PWM outputs are shut down Safe state for the inverter. | ||
| The counter can still be re-started from where it stop. | ||
| 1 = Normal mode: The counter continues to operate normally May be dangerous in some cases since a constant duty cycle is applied to the inverter (no more interrupts serviced). | ||
| [2] | PINV0 | PWM0_CH0 Output Inverter Enable Bit |
| 0 = PWM0_CH0 output inverter Disabled. | ||
| 1 = PWM0_CH0 output inverter Enabled. | ||
| [3] | CNTMODE0 | PWM Counter 0 Auto-reload/One-shot Mode |
| 0 = One-shot mode. | ||
| 1 = Auto-reload mode. | ||
| Note: If there is a rising transition at this bit, it will cause PERIOD0 and CMP0 cleared. | ||
| [4] | CNTEN1 | PWM Counter 1 Enable/Disable Start Run |
| 0 = Corresponding PWM counter running Stopped. | ||
| 1 = Corresponding PWM counter start run Enabled. | ||
| [5] | HCUPDT | Half Cycle Update Enable for Center-aligned Type |
| 0 = Disable half cycle update PERIOD & CMP. | ||
| 1 = Enable half cycle update PERIOD & CMP. | ||
| [6] | PINV1 | PWM0_CH1 Output Inverter Enable Bit |
| 0 = PWM0_CH1 output inverter Disable. | ||
| 1 = PWM0_CH1 output inverter Enable. | ||
| [7] | CNTMODE1 | PWM Counter 1 Auto-reload/One-shot Mode |
| 0 = One-shot mode. | ||
| 1 = Auto-reload mode. | ||
| Note: If there is a rising transition at this bit, it will cause PERIOD1 and CMP1 cleared. | ||
| [8] | CNTEN2 | PWM Counter 2 Enable Start Run |
| 0 = Corresponding PWM counter running Stopped. | ||
| 1 = Corresponding PWM counter start run Enabled. | ||
| [10] | PINV2 | PWM0_CH2 Output Inverter Enable Bit |
| 0 = PWM0_CH2 output inverter Disabled. | ||
| 1 = PWM0_CH2 output inverter Enabled. | ||
| [11] | CNTMODE2 | PWM Counter 2 Auto-reload/One-shot Mode |
| 0 = One-shot mode. | ||
| 1 = Auto-reload mode. | ||
| Note: If there is a rising transition at this bit, it will cause PERIOD2 and CMP2 cleared. | ||
| [12] | CNTEN3 | PWM Counter 3 Enable Start Run |
| 0 = Corresponding PWM counter running Stopped. | ||
| 1 = Corresponding PWM counter start run Enabled. | ||
| [14] | PINV3 | PWM0_CH 3 Output Inverter Enable Bit |
| 0 = PWM0_CH3 output inverter Disabled. | ||
| 1 = PWM0_CH3 output inverter Enabled. | ||
| [15] | CNTMODE3 | PWM Counter 3 Auto-reload/One-shot Mode |
| 0 = One-shot mode. | ||
| 1 = Auto-reload mode. | ||
| Note: If there is a rising transition at this bit, it will cause PERIOD3 and CMP3 cleared. | ||
| [16] | CNTEN4 | PWM Counter 4 Enable Start Run |
| 0 = Corresponding PWM counter running Stopped. | ||
| 1 = Corresponding PWM counter start run Enabled. | ||
| [18] | PINV4 | PWM0_CH4 Output Inverter Enable Bit |
| 0 = PWM0_CH4 output inverter Disabled. | ||
| 1 = PWM0_CH4 output inverter Enabled. | ||
| [19] | CNTMODE4 | PWM Counter 4 Auto-reload/One-shot Mode |
| 0 = One-shot mode. | ||
| 1 = Auto-reload mode. | ||
| Note: If there is a rising transition at this bit, it will cause PERIOD4 and CMP4 cleared. | ||
| [20] | CNTEN5 | PWM Counter 5 Enable Start Run |
| 0 = Corresponding PWM counter running Stopped. | ||
| 1 = Corresponding PWM counter start run Enabled. | ||
| [21] | ASYMEN | Asymmetric Mode In Center-aligned Type |
| 0 = Symmetric mode in center-aligned type. | ||
| 1 = Asymmetric mode in center-aligned type. | ||
| [22] | PINV5 | PWM0_CH5 Output Inverter Enable Bit |
| 0 = PWM0_CH5 output inverter Disabled. | ||
| 1 = PWM0_CH5 output inverter Enabled. | ||
| [23] | CNTMODE5 | PWM Counter 5 Auto-reload/One-shot Mode |
| 0 = One-shot mode. | ||
| 1 = Auto-reload mode. | ||
| Note: If there is a rising transition at this bit, it will cause PERIOD5 and CMP5 cleared. | ||
| [24] | DTCNT01 | Dead-time 0 Counter Enable Bit (PWM0_CH0 And PWM0_CH1 Pair For PWMA Group) |
| 0 = Dead-time 0 generator Disabled. | ||
| 1 = Dead-time 0 generator Enabled. | ||
| Note: When the dead-time generator is enabled, the pair of PWM0_CH0 and PWM0_CH1 becomes a complementary pair for PWMA group. | ||
| [25] | DTCNT23 | Dead-time 2 Counter Enable Bit (PWM0_CH2 And PWM0_CH3 Pair For PWMB Group) |
| 0 = Dead-time 2 generator Disabled. | ||
| 1 = Dead-time 2 generator Enabled. | ||
| Note: When the dead-time generator is enabled, the pair of PWM0_CH2 and PWM0_CH3 becomes a complementary pair for PWMB group. | ||
| [26] | DTCNT45 | Dead-time 4 Counter Enable Bit (PWM0_CH4 And PWM0_CH5 Pair For PWMC Group) |
| 0 = Dead-time 4 generator Disabled. | ||
| 1 = Dead-time 4 generator Enabled. | ||
| Note: When the dead-time generator is enabled, the pair of PWM0_CH4 and PWM0_CH5 becomes a complementary pair for PWMC group. | ||
| [27] | CNTCLR | Clear PWM Counter Control Bit |
| 0 = Do not clear PWM counter. | ||
| 1 = All 16-bit PWM counters cleared to 0x0000. | ||
| Note: It is automatically cleared by hardware. | ||
| [29:28] | MODE | PWM Operating Mode Select Bit |
| 00 = Independent mode. | ||
| 01 = Complementary mode. | ||
| 10 = Synchronized mode. | ||
| 11 = Reserved. | ||
| [30] | GROUPEN | Group Function Enable Bit |
| 0 = The signals timing of all PWM channels are independent. | ||
| 1 = Unify the signals timing of PWM0_CH0, PWM0_CH2 and PWM0_CH4 in the same phase which is controlled by PWM0_CH0 and also unify the signals timing of PWM0_CH1, PWM0_CH3 and PWM0_CH5 in the same phase which is controlled by PWM0_CH1. | ||
| [31] | CNTTYPE | PWM Counter-aligned Type Select Bit |
| 0 = Edge-aligned type. | ||
| 1 = Center-aligned type. |
Definition at line 5567 of file Mini58Series.h.
| __IO uint32_t SPI_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SPIEN | SPI Transfer Control Bit And Busy Status |
| If FIFO mode is enabled, this bit will be controlled by hardware and it's read only. | ||
| If FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. | ||
| As the transfer is finished, this bit will be cleared automatically. | ||
| 0 = Writing 0 to this bit to stop data transfer if SPI is transferring. | ||
| 1 = In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master. | ||
| Note 1: When FIFO mode is disabled, all configurations should be ready before writing 1 to the SPIEN bit. | ||
| Note 2: In SPI Slave mode, if FIFO mode is disabled and the SPI bus clock is kept at idle state during a data transfer, the SPIEN bit will not be cleared to 0 when slave select signal goes to inactive state. | ||
| [1] | RXNEG | Receive On Negative Edge |
| 0 = The received data input signal latched on the rising-edge of SPI_CLK. | ||
| 1 = The received data input signal latched on the falling-edge of SPI_CLK. | ||
| [2] | TXNEG | Transmit On Negative Edge |
| 0 = The transmitted data output signal is driven on the rising-edge of SPI_CLK. | ||
| 1 = The transmitted data output signal is driven on the falling-edge of SPI_CLK. | ||
| [7:3] | DWIDTH | Transmit Bit Length |
| This field specifies how many bits are transmitted in one transmit/receive. | ||
| The minimum bit length is 8 bits and can up to 32 bit. | ||
| DWIDTH = 0x01~0x07 .... reserved (can't use). | ||
| DWIDTH = 0x08 .... 8 bits. | ||
| DWIDTH = 0x09 .... 9 bits. | ||
| ...... | ||
| DWIDTH = 0x1F .... 31 bits. | ||
| DWIDTH = 0x00 .... 32 bits. | ||
| [10] | LSB | LSB First |
| 0 = The MSB is transmitted/received first. | ||
| 1 = The LSB is transmitted/received first. | ||
| [11] | CLKPOL | Clock Polarity |
| 0 = SPI_CLK idle low. | ||
| 1 = SPI_CLK idle high. | ||
| [15:12] | SUSPITV | Suspend Interval (Master Only) |
| The four bits provide configurable suspend interval between two successive transactions in a transfer. | ||
| The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. | ||
| The default value is 0x3. | ||
| The period of the suspend interval is obtained according to the following equation: | ||
| (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle | ||
| Example: | ||
| SUSPITV = 0x0 .... 0.5 SPI_CLK clock cycle. | ||
| SUSPITV = 0x1 .... 1.5 SPI_CLK clock cycle. | ||
| ...... | ||
| SUSPITV = 0xE .... 14.5 SPI_CLK clock cycle. | ||
| SUSPITV = 0xF .... 15.5 SPI_CLK clock cycle. | ||
| [16] | UNITIF | Unit-transfer Interrupt Flag |
| 0 = The transfer does not finish yet. | ||
| 1 = The SPI controller has finished one unit transfer. | ||
| Note 1: This bit will be cleared by writing 1 to itself. | ||
| Note 2: It's a mutual mirror bit of SPI_STATUS[16]. | ||
| [17] | UNITIEN | Unit-transfer Interrupt Enable Bit |
| 0 = SPI unit-transfer interrupt Disabled. | ||
| 1 = SPI unit-transfer interrupt Enabled. | ||
| [18] | SLAVE | Slave Mode Control |
| 0 = Master mode. | ||
| 1 = Slave mode. | ||
| [19] | REORDER | Byte Reorder Function |
| 0 = Byte reorder function Disabled. | ||
| 1 = Byte reorder function Enabled. | ||
| Note: This setting is only available if DWIDTH is defined as 16, 24, or 32 bits. | ||
| [21] | FIFOEN | FIFO Mode Enable Bit |
| 0 = FIFO Mode Disabled. | ||
| 1 = FIFO Mode Enabled. | ||
| Note 1: Before enabling FIFO mode, the other related settings should be set in advance. | ||