|
Apollo Register Documentation v2.4.2
|
| 0x00000000: | CACHECFG - Flash Cache Control Register |
| 0x00000004: | FLASHCFG - Flash Control Register |
| 0x00000008: | CTRL - Cache Control |
| 0x00000010: | NCR0START - Flash Cache Noncachable Region 0 Start |
| 0x00000014: | NCR0END - Flash Cache Noncachable Region 0 End |
| 0x00000018: | NCR1START - Flash Cache Noncachable Region 1 Start |
| 0x0000001C: | NCR1END - Flash Cache Noncachable Region 1 End |
| 0x00000040: | DMON0 - Data Cache Total Accesses |
| 0x00000044: | DMON1 - Data Cache Tag Lookups |
| 0x00000048: | DMON2 - Data Cache Hits |
| 0x0000004C: | DMON3 - Data Cache Line Hits |
| 0x00000050: | IMON0 - Instruction Cache Total Accesses |
| 0x00000054: | IMON1 - Instruction Cache Tag Lookups |
| 0x00000058: | IMON2 - Instruction Cache Hits |
| 0x0000005C: | IMON3 - Instruction Cache Line Hits |
| Instance 0 Address: | 0x40018000 |
Flash Cache Control Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
ENABLE_MONITOR
0x0 |
RSVD
0x0 |
DATA_CLKGATE
0x1 |
RSVD
0x0 |
CACHE_LS
0x1 |
CACHE_CLKGATE
0x1 |
DCACHE_ENABLE
0x0 |
ICACHE_ENABLE
0x0 |
CONFIG
0x5 |
ENABLE_NC1
0x0 |
ENABLE_NC0
0x0 |
LRU
0x0 |
ENABLE
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:25 | RSVD | RO | This bitfield is reserved for future use. |
| 24 | ENABLE_MONITOR | RW | Enable Cache Monitoring Stats. Cache monitoring consumes additional power and should only be enabled when profiling code and counters will increment when this bit is set. Counter values will be retained when this is set to 0, allowing software to enable/disable counting for multiple code segments. |
| 23:21 | RSVD | RO | This bitfield is reserved for future use. |
| 20 | DATA_CLKGATE | RW | Enable aggressive clock gating of entire data array. This bit should be set to 1 for optimal power efficiency. |
| 19:12 | RSVD | RO | This bitfield is reserved for future use. |
| 11 | CACHE_LS | RW | Enable LS (light sleep) of cache RAMs. Software should DISABLE this bit since cache activity is too high to benefit from LS usage. |
| 10 | CACHE_CLKGATE | RW | Enable clock gating of cache TAG RAM. Software should enable this bit for optimal power efficiency. |
| 9 | DCACHE_ENABLE | RW | Enable Flash Data Caching. |
| 8 | ICACHE_ENABLE | RW | Enable Flash Instruction Caching |
| 7:4 | CONFIG | RW | Sets the cache configuration W1_128B_512E = 0x4 - Direct mapped, 128-bit linesize, 512 entries (4 SRAMs active) W2_128B_512E = 0x5 - Two-way set associative, 128-bit linesize, 512 entries (8 SRAMs active) W1_128B_1024E = 0x8 - Direct mapped, 128-bit linesize, 1024 entries (8 SRAMs active) |
| 3 | ENABLE_NC1 | RW | Enable Non-cacheable region 1. See NCR1 registers to define the region. |
| 2 | ENABLE_NC0 | RW | Enable Non-cacheable region 0. See NCR0 registers to define the region. |
| 1 | LRU | RW | Sets the cache repleacment policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM. |
| 0 | ENABLE | RW | Enables the flash cache controller and enables power to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should be set to enable caching for each type of access. |
| Instance 0 Address: | 0x40018004 |
Flash Control Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
LPMMODE
0x0 |
LPM_RD_WAIT
0x8 |
RSVD
0x0 |
SEDELAY
0x7 |
RD_WAIT
0x3 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:14 | RSVD | RO | This bitfield is reserved for future use. |
| 13:12 | LPMMODE | RW | Controls flash low power modes (control of LPM pin). NEVER = 0x0 - High power mode (LPM not used). STANDBY = 0x1 - Fast Standby mode. LPM deasserted for read operations, but asserted while flash IDLE. ALWAYS = 0x2 - Low Power mode. LPM always asserted for reads. LPM_RD_WAIT must be programmed to accomodate longer read access times. |
| 11:8 | LPM_RD_WAIT | RW | Sets flash waitstates when in LPM Mode 2 (RD_WAIT in LPM mode 2 only) |
| 7 | RSVD | RO | This bitfield is reserved for future use. |
| 6:4 | SEDELAY | RW | Sets SE delay (flash address setup). A value of 5 is recommended. |
| 3:0 | RD_WAIT | RW | Sets read waitstates for normal (fast) operation. A value of 1 is recommended. |
| Instance 0 Address: | 0x40018008 |
Cache Control
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
FLASH1_SLM_ENABLE
0x0 |
FLASH1_SLM_DISABLE
0x0 |
FLASH1_SLM_STATUS
0x0 |
RSVD
0x0 |
FLASH0_SLM_ENABLE
0x0 |
FLASH0_SLM_DISABLE
0x0 |
FLASH0_SLM_STATUS
0x0 |
RSVD
0x0 |
CACHE_READY
0x0 |
RESET_STAT
0x0 |
INVALIDATE
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:11 | RSVD | RO | This bitfield is reserved for future use. |
| 10 | FLASH1_SLM_ENABLE | WO | Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned. |
| 9 | FLASH1_SLM_DISABLE | WO | Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it). |
| 8 | FLASH1_SLM_STATUS | RO | Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode. |
| 7 | RSVD | RO | This bitfield is reserved for future use. |
| 6 | FLASH0_SLM_ENABLE | WO | Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned. |
| 5 | FLASH0_SLM_DISABLE | WO | Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it). |
| 4 | FLASH0_SLM_STATUS | RO | Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode. |
| 3 | RSVD | RO | This bitfield is reserved for future use. |
| 2 | CACHE_READY | RO | Cache Ready Status (enabled and not processing an invalidate operation) |
| 1 | RESET_STAT | WO | Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set. CLEAR = 0x1 - Clear Cache Stats |
| 0 | INVALIDATE | WO | Writing a 1 to this bitfield invalidates the flash cache contents. |
| Instance 0 Address: | 0x40018010 |
Flash Cache Noncachable Region 0 Start
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
ADDR
0x0 |
RSVD
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:27 | RSVD | RO | This bitfield is reserved for future use. |
| 26:4 | ADDR | RW | Start address for non-cacheable region 0 |
| 3:0 | RSVD | RO | This bitfield is reserved for future use. |
| Instance 0 Address: | 0x40018014 |
Flash Cache Noncachable Region 0 End
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
ADDR
0x0 |
RSVD
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:27 | RSVD | RO | This bitfield is reserved for future use. |
| 26:4 | ADDR | RW | End address for non-cacheable region 0 |
| 3:0 | RSVD | RO | This bitfield is reserved for future use. |
| Instance 0 Address: | 0x40018018 |
Flash Cache Noncachable Region 1 Start
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
ADDR
0x0 |
RSVD
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:27 | RSVD | RO | This bitfield is reserved for future use. |
| 26:4 | ADDR | RW | Start address for non-cacheable region 1 |
| 3:0 | RSVD | RO | This bitfield is reserved for future use. |
| Instance 0 Address: | 0x4001801C |
Flash Cache Noncachable Region 1 End
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RSVD
0x0 |
ADDR
0x0 |
RSVD
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:27 | RSVD | RO | This bitfield is reserved for future use. |
| 26:4 | ADDR | RW | End address for non-cacheable region 1 |
| 3:0 | RSVD | RO | This bitfield is reserved for future use. |
| Instance 0 Address: | 0x40018040 |
Data Cache Total Accesses
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DACCESS_COUNT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | DACCESS_COUNT | RO | Total accesses to data cache. All performance metrics should be relative to the number of accesses performed. |
| Instance 0 Address: | 0x40018044 |
Data Cache Tag Lookups
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DLOOKUP_COUNT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | DLOOKUP_COUNT | RO | Total tag lookups from data cache. |
| Instance 0 Address: | 0x40018048 |
Data Cache Hits
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DHIT_COUNT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | DHIT_COUNT | RO | Cache hits from lookup operations. |
| Instance 0 Address: | 0x4001804C |
Data Cache Line Hits
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DLINE_COUNT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | DLINE_COUNT | RO | Cache hits from line cache |
| Instance 0 Address: | 0x40018050 |
Instruction Cache Total Accesses
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| IACCESS_COUNT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | IACCESS_COUNT | RO | Total accesses to Instruction cache |
| Instance 0 Address: | 0x40018054 |
Instruction Cache Tag Lookups
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ILOOKUP_COUNT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ILOOKUP_COUNT | RO | Total tag lookups from Instruction cache |
| Instance 0 Address: | 0x40018058 |
Instruction Cache Hits
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| IHIT_COUNT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | IHIT_COUNT | RO | Cache hits from lookup operations |
| Instance 0 Address: | 0x4001805C |
Instruction Cache Line Hits
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ILINE_COUNT
0x0 |
| Bits | Name | RW | Description |
|---|---|---|---|
| 31:0 | ILINE_COUNT | RO | Cache hits from line cache |


|
Clawpack Documentation Version 5.0 --- Under Construction! Not yet accurate |
The desired plots are specified by creating an object of class ClawPlotData that contains specifications of what figures should be created, and within each figure what sets of axes should be drawn, and within each axes what items should be plotted (lines, contour plots, etc.).
More details about each class of objects can be found on these pages:
For examples, see Plotting examples in 1d.
The approach outlined below may seem more complicated than necessary, and it would be if all you ever want to do is plot one set of data at each output time. However, when adaptive mesh refinement is used each frame of data may contain several patches and so creating the desired plot requires looping over all patches. This is done by the plotting utilities described in Plotting options, but for this to work it is necessary to specify what plot(s) are desired.
Most example directories contain a file setplot.py that contains a function setplot(plotdata). This function sets various attributes of plotdata in order to specify how plotting is to be done.
The object plotdata is of class ClawPlotData. The way to set up the plot structure is to follow this outline:
Specify some attributes of setplot that determine what sort of plots will be produced and where they will be stored, e.g.:
plotdata.plotdir = '_plots'will cause hardcopy to go to subdirectory _plots of the current directory. (Attributes like plotdir that are only used for hardcopy are often set in the script plotclaw.py rather than in setplot. See Specifying what and how to plot.)
There are many other ClawPlotData attributes and methods.
Specify one or more Figures to be created for each frame, e.g.:
plotfigure = plotdata.new_plotfigure(name='Solution', figno=1)plotfigure is now an object of class ClawPlotFigure and various attributes can be set, e.g.:
plotfigure.kwargs = {'figsize':[8,12], 'facecolor':'#ff9999'}to specify any keyword arguments that should be used when creating this figure in matplotlib. The above would create a figure that is 8 inches by 12 inches with a pink background.
For more options, see the matplotlib documentation for the figure command.
There are many other plotfigure attributes and methods.
Specify one or more Axes to be created within each figure, e.g.:
plotaxes = plotfigure.new_plotaxes()Note that new_plotaxes is a method of class ClawPlotFigure and creates a set of axes specific to the particular object plotfigure.
plotaxes is now an object of class ClawPlotAxes and various attributes can be set, e.g.:
plotfigure.ylimits = [-1, 1]There are many other ClawPlotAxes attributes and methods.
Specify one or more Items to be created within these axes, e.g.:
plotitem = plotaxes.new_plotitem(plot_type='1d_plot')Note that new_plotitem is a method of class ClawPlotAxes and creates a plot object (e.g. line, contour plot, etc) specific to the particular object plotaxes.
plotitem is now an object of class ClawPlotItem and various attributes can be set, e.g.:
plotitem.plotstyle = '-' plotitem.color = 'r'for a solid line that is red.
There are many other ClawPlotItem attributes and methods.


Main Page
Classes
Files
Class List
Class Hierarchy
Class Members
x2d
::
util
::
time_interpolator
x2d::util::time_interpolator Class Reference
Inheritance diagram for x2d::util::time_interpolator:
List of all members.
Public Member Functions
time_interpolator
(float t)
virtual void
update
(float dt)
virtual void
reset
()
virtual void
calculate
()=0
Protected Attributes
float
total_time_
float
elapsed_time_
The documentation for this class was generated from the following file:
/Users/godexsoft/Development/Nako/x2d/x2d/x2d/src/util/
interpolator.h
Generated by
1.6.2


Audacity with ASIO
Whenever I want to do a quick recording, possibly with a few tweaks, my goto programme is the venerable open source success story Audacity. This multi track audio recorder with processing effects is powerful enough to do much audio editing. It’s simple enough to get your head round and so ideal for a quick recording when you don’t need a full DAW (eg Reaper).
When using Audacity with k-mix I found there was a bit of a driver issue. The current ASIO k-mix driver only works with Audacity’s MME mode and is restricted to 2 channels. I wanted to record channels 3 & 4 so looked into building Audacity with ASIO support as the option is only available for self build and not redistribution for licensing reasons.
Eventually I discovered that the ASIO build was actually not much use for my requirements as I could use the k-mix flexibility to send channnels 3 & 4 to 1 &2 and use the release Audacity. But, in case others are interested in using it, I provide a simple Windows cmd script to help automate the build.
It’s worth emphasising that the ASIO build does not provide any improvement in recording quality over using the MME option. ASIO drivers do provide lower latency but that is unlikely to be relevant. More useful, is the access to all 8 k-mix channels.
Whilst having access to all 8 channels might seem useful, Audacity’s support for more than 2 channels is poor. To record channels 3 & 4, say, you have to record 1, 2, 3 & 4 and the level meters are fixed to channels 1 & 2. Other features like pan control for Left or right on each track make little sense.


Welcome¶
MagIC is a numerical code that can simulate fluid dynamics in a spherical shell. MagIC solves for the Navier-Stokes equation including Coriolis force, optionally coupled with an induction equation for Magneto-Hydro Dynamics (MHD), a temperature (or entropy) equation and an equation for chemical composition under both the anelastic and the Boussinesq approximations.
MagIC uses Chebyshev polynomials or finite difference in the radial direction and spherical harmonic decomposition in the azimuthal and latitudinal directions. MagIC supports several Implicit-Explicit time schemes where the nonlinear terms and the Coriolis force are treated explicitly, while the remaining linear terms are treated implicitly.
MagIC is written in Fortran and designed to be used on supercomputing clusters. It thus relies on a hybrid parallelisation scheme using both OpenMP and MPI. Postprocessing functions written in python (requiring matplotlib and scipy) are also provided to allow a useful data analysis.
MagIC is a free software. It can be used, modified and redistributed under the terms of the GNU GPL v3 licence.
Quickly starting using MagIC¶
The quick-starting guide will help you to download, set up and run your first numerical simulations using MagIC.
The description of the input namelists will then help you to define the exact physical setup you may want to simulate.
The description of the output files will help you to understand what are the diagnostic quantities computed by MagIC.
Finally, the python functions and classes will allow you to do some advanced post-processing analyses on the outputs of MagIC.
Documentation¶
The table of contents gives an overview of the complete documentation.
The formulation of the (M)HD problem contains an exhaustive description of the equations solved by the MagIC code.
The numerical methods section contains the description of the numerical technique.
The search page allows to search the documentation.
The fortran API contains a generic description of all Fortran variables, subroutines and modules used in MagIC.
You can also download a PDF version
of this
documentation generated from LaTeX Sphinx.
Contributing to the code¶
If you want to contribute to MagIC, the contributor guide might be helpful for you.
Giving credit¶
In case you intend to publish scientific results obtained with MagIC or present them in a conference, we (the developers of MagIC) kindly ask to be acknowledged with a reference to the website https://magic-sph.github.io/ or https://github.com/magic-sph/magic.
We also suggest to give appropriate reference to one or several of the following papers:
Boussinesq equations: Wicht (2002, PEPI, 132, 281-302)
Anelastic equations: Gastine & Wicht (2012, Icarus, 219, 28-442)
Boussinesq benchmark: Christensen et al. (2001, PEPI, 128, 25-34)
Benchmark for double diffusive convection: Breuer et al. (2010, GJI, 183, 150-162)
Anelastic benchmark: Jones et al. (2011, Icarus, 216, 120-135)
In case you use the SHTns library for the spherical harmonics transforms (MagIC 5.3 or later), please also cite: Schaeffer (2013, GGG, 14, 751-758)
See also
A (tentative) comprehensive list of the publications that have been produced to date (May 2019) using MagIC is accessible here. To date, more than 100 publications have been-accepted in more than 10 different peer-reviewed journals: PEPI (22), Icarus (11), E&PSL (7), GJI (8), A&A (6), GRL (4), JFM (6), GAFD (3), Nature (2), etc.


/**
* @flow
*/
import type { ServerOptions } from '../Types';
/**
* Default Server Options
numAudioBusChannels - The number of internal audio rate busses. The default is 128.
numControlBusChannels - The number of internal control rate busses. The default is 4096.
The following two options need not correspond to the available number of hardware inputs and outputs.
numInputBusChannels - The number of audio input bus channels. The default is 8.
numOutputBusChannels - The number of audio output bus channels. The default is 8.
numBuffers - The number of global sample buffers available. (See Buffer.) The default is 1024.
maxNodes - The maximum number of Nodes. The default is 1024.
maxSynthDefs - The maximum number of SynthDefs. The default is 1024.
protocol - A symbol representing the communications protocol. Either \udp or \tcp. The default is udp.
blockSize - The number of samples in one control period. The default is 64.
hardwareBufferSize - The preferred hardware buffer size. If non-nil the server app will attempt to set the hardware buffer frame size. Not all sizes are valid. See the documentation of your audio hardware for details.
memSize - The number of kilobytes of real time memory allocated to the server. This memory is used to allocate synths and any memory that unit generators themselves allocate (for instance in the case of delay ugens which do not use buffers, such as CombN), and is separate from the memory used for buffers. Setting this too low is a common cause of 'exception in real time: alloc failed' errors. The default is 8192.
numRGens - The number of seedable random number generators. The default is 64.
numWireBufs - The maximum number of buffers that are allocated to interconnect unit generators. (Not to be confused with the global sample buffers represented by Buffer.) This sets the limit of complexity of SynthDefs that can be loaded at runtime. This value will be automatically increased if a more complex def is loaded at startup, but it cannot be increased thereafter without rebooting. The default is 64.
sampleRate - The preferred sample rate. If non-nil the server app will attempt to set the hardware sample rate.
loadDefs - A Boolean indicating whether or not to load the synth definitions in synthdefs/ (or anywhere set in the environment variable SC_SYNTHDEF_PATH) at startup. The default is true.
inputStreamsEnabled - A String which allows turning off input streams that you are not interested in on the audio device. If the string is "01100", for example, then only the second and third input streams on the device will be enabled. Turning off streams can reduce CPU load.
outputStreamsEnabled - A String which allows turning off output streams that you are not interested in on the audio device. If the string is "11000", for example, then only the first two output streams on the device will be enabled. Turning off streams can reduce CPU load.
env - Environment variables that will be set for the scsynth process. eg. SC_JACK_DEFAULT_INPUTS: "system:capture_1,system:capture_2" SC_JACK_DEFAULT_OUTPUTS SC_SYNTHDEF_PATH SC_PLUGIN_PATH
*/
const defaultServerOptions: ServerOptions = {
host: '<IP_ADDRESS>',
serverPort: '57110',
protocol: 'udp',
numPrivateAudioBusChannels: 112,
numAudioBusChannels: 128,
numControlBusChannels: 4096,
numInputBusChannels: 2,
numOutputBusChannels: 2,
numBuffers: 1026,
maxNodes: 1024,
maxSynthDefs: 1024,
blockSize: 64,
hardwareBufferSize: null,
memSize: 8192,
numRGens: 64,
numWireBufs: 64,
sampleRate: null,
loadDefs: true,
inputStreamsEnabled: null,
outputStreamsEnabled: null,
device: null,
verbosity: 0,
restrictedPath: null,
ugenPluginsPath: null,
initialNodeID: 1000,
remoteControlVolume: false,
memoryLocking: false,
threads: false,
useSystemClock: false
};
export default defaultServerOptions;
|


Create a form to get customer feedback. Following features to be present in the form . 1. Text box to get customer name and display on the same page. 2. Radio button to get gender and display on the same page. 3. Text area to get feedback and display on the same page.


---
layout: default
title: "Documentation - Installation"
---
Installation guide
Requirements
What does it require for you to be able to run JSIS?
- Node.js
- Node.js modules: ejs, iconv (iconv is actually not strictly necessary)
- Log files in supported format
- Some basic skills at running command line tools
How to use it?
-
Make sure you have installed Node.js and Node Package Manager
You can probably install them via some installer from the Node.js homepage, or with Node Version Manager. Ask them for more help.
-
You'll need a place to put the application in, and to run it on .. think of one, and then download the source code from the GitHub project page and put the code there.
-
Install the node modules "ejs" and "iconv".
Assuming you've got Node Package Manager installed properly and use BASH, you can open a terminal/whatever to the place you put the files in and run the following:
npm install ejs iconv
NOTE: iconv most likely needs to be compiled, might have some requirements (such as a compiler), etc. that I cannot, and will not, help you with.
-
Configure JSIS by copying config.example.js to config.js and editing it to taste. Try to read the documentation if something is unclear.
-
Run JSIS with:
node jsis.js
- Good luck! If any issues arise, please report them at the GitHub issue tracker ... if you like it, send thanks to Lietu.


Kuka Pong
About Us
The Technology
Our platform will be utilizing a variety of technologies to connect your device to your Oculus Rift.