PMHAL_PRCM_PRM_INT_DPLL_MPU_RECAL = 0x1U,
PMHAL_PRCM_PRM_INT_DPLL_IVA_RECAL = 0x2U,
PMHAL_PRCM_PRM_INT_DPLL_PER_RECAL = 0x3U,
PMHAL_PRCM_PRM_INT_DPLL_ABE_RECAL = 0x4U,
PMHAL_PRCM_PRM_INT_DPLL_GMAC_RECAL = 0x5U,
PMHAL_PRCM_PRM_INT_DPLL_GPU_RECAL = 0x6U,
PMHAL_PRCM_PRM_INT_DPLL_DDR_RECAL = 0x7U,
PMHAL_PRCM_PRM_INT_TRANSITION = 0x8U,
PMHAL_PRCM_PRM_INT_IO = 0x9U,
PMHAL_PRCM_PRM_INT_FORCEWKUP = 0xAU,
PMHAL_PRCM_PRM_INT_DPLL_DSP_RECAL = 0xBU,
PMHAL_PRCM_PRM_INT_DPLL_EVE_RECAL = 0xCU,
PMHAL_PRCM_PRM_INT_ABB_GPU_DONE = 0x1CU,
PMHAL_PRCM_PRM_INT_ABB_DSPEVE_DONE = 0x1DU,
PMHAL_PRCM_PRM_INT_ABB_IVA_DONE = 0x1EU,
PMHAL_PRCM_PRM_INT_ABB_MPU_DONE = 0x1FU,
PMHAL_PRCM_PRM_INT_MAX = PMHAL_PRCM_PRM_INT_ABB_MPU_DONE,
PMHAL_PRCM_PRM_INT_MIN = 0x0U,
PMHAL_PRCM_PRM_INT_DPLL_CORE_RECAL = PMHAL_PRCM_PRM_INT_MIN,
PMHAL_PRCM_PRM_INT_DPLL_MPU_RECAL = 0x1U,
PMHAL_PRCM_PRM_INT_DPLL_IVA_RECAL = 0x2U,
PMHAL_PRCM_PRM_INT_DPLL_PER_RECAL = 0x3U,
PMHAL_PRCM_PRM_INT_DPLL_ABE_RECAL = 0x4U,
PMHAL_PRCM_PRM_INT_DPLL_GMAC_RECAL = 0x5U,
PMHAL_PRCM_PRM_INT_DPLL_GPU_RECAL = 0x6U,
PMHAL_PRCM_PRM_INT_DPLL_DDR_RECAL = 0x7U,
PMHAL_PRCM_PRM_INT_TRANSITION = 0x8U,
PMHAL_PRCM_PRM_INT_IO = 0x9U,
PMHAL_PRCM_PRM_INT_FORCEWKUP = 0xAU,
PMHAL_PRCM_PRM_INT_DPLL_DSP_RECAL = 0xBU,
PMHAL_PRCM_PRM_INT_DPLL_EVE_RECAL = 0xCU,
PMHAL_PRCM_PRM_INT_ABB_GPU_DONE = 0x1CU,
PMHAL_PRCM_PRM_INT_ABB_DSPEVE_DONE = 0x1DU,
PMHAL_PRCM_PRM_INT_ABB_IVA_DONE = 0x1EU,
PMHAL_PRCM_PRM_INT_ABB_MPU_DONE = 0x1FU,
PMHAL_PRCM_PRM_INT_MAX = PMHAL_PRCM_PRM_INT_ABB_MPU_DONE,
PMHAL_PRCM_PRM_INT_MIN = 0x0U,
PMHAL_PRCM_PRM_INT_DPLL_CORE_RECAL = PMHAL_PRCM_PRM_INT_MIN,
PMHAL_PRCM_PRM_INT_DPLL_MPU_RECAL = 0x1U,
PMHAL_PRCM_PRM_INT_DPLL_IVA_RECAL = 0x2U,
PMHAL_PRCM_PRM_INT_DPLL_PER_RECAL = 0x3U,
PMHAL_PRCM_PRM_INT_DPLL_ABE_RECAL = 0x4U,
PMHAL_PRCM_PRM_INT_DPLL_GMAC_RECAL = 0x5U,
PMHAL_PRCM_PRM_INT_DPLL_GPU_RECAL = 0x6U,
PMHAL_PRCM_PRM_INT_DPLL_DDR_RECAL = 0x7U,
PMHAL_PRCM_PRM_INT_TRANSITION = 0x8U,
PMHAL_PRCM_PRM_INT_IO = 0x9U,
PMHAL_PRCM_PRM_INT_FORCEWKUP = 0xAU,
PMHAL_PRCM_PRM_INT_DPLL_DSP_RECAL = 0xBU,
PMHAL_PRCM_PRM_INT_DPLL_EVE_RECAL = 0xCU,
PMHAL_PRCM_PRM_INT_ABB_GPU_DONE = 0x1CU,
PMHAL_PRCM_PRM_INT_ABB_DSPEVE_DONE = 0x1DU,
PMHAL_PRCM_PRM_INT_ABB_IVA_DONE = 0x1EU,
PMHAL_PRCM_PRM_INT_ABB_MPU_DONE = 0x1FU,
PMHAL_PRCM_PRM_INT_MAX = PMHAL_PRCM_PRM_INT_ABB_MPU_DONE,
PMHAL_PRCM_PRM_INT_MIN = 0x8U,
PMHAL_PRCM_PRM_INT_TRANSITION = PMHAL_PRCM_PRM_INT_MIN,
PMHAL_PRCM_PRM_INT_FORCEWKUP = 0xAU,
PMHAL_PRCM_PRM_INT_DPLL_MPU_RECAL = 0xBU,
PMHAL_PRCM_PRM_INT_DPLL_CORE_RECAL = 0xCU,
PMHAL_PRCM_PRM_INT_DPLL_PER_RECAL = 0xDU,
PMHAL_PRCM_PRM_INT_DPLL_DDR_RECAL = 0xEU,
PMHAL_PRCM_PRM_INT_DPLL_DISP_RECAL = 0xFU,
PMHAL_PRCM_PRM_INT_MAX = PMHAL_PRCM_PRM_INT_DPLL_DISP_RECAL,
PMHAL_PRCM_PRM_INT_MIN = 0x8U,
PMHAL_PRCM_PRM_INT_TRANSITION = PMHAL_PRCM_PRM_INT_MIN,
PMHAL_PRCM_PRM_INT_FORCEWKUP = 0xAU,
PMHAL_PRCM_PRM_INT_DPLL_MPU_RECAL = 0xBU,
PMHAL_PRCM_PRM_INT_DPLL_CORE_RECAL = 0xCU,
PMHAL_PRCM_PRM_INT_DPLL_PER_RECAL = 0xDU,
PMHAL_PRCM_PRM_INT_DPLL_DDR_RECAL = 0xEU,
PMHAL_PRCM_PRM_INT_DPLL_DISP_RECAL = 0xFU,
PMHAL_PRCM_PRM_INT_DPLL_EXTDEV_RECAL = 0x10U,
PMHAL_PRCM_PRM_INT_MAX = PMHAL_PRCM_PRM_INT_DPLL_EXTDEV_RECAL
} |
| | Enum defining the interrupts supported by the PRM. The enumeration values correspond to their bit shifts. The bit shifts for MPU are slightly different than the other CPUs. This is taken care of in the API definition. More...
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| |
| enum | pmhalVideopllMuxSelectId {
PMHAL_PRCM_VIDEOPLL_MUX_MIN = 0U,
PMHAL_PRCM_VIDEOPLL_MUX_HDMI = PMHAL_PRCM_VIDEOPLL_MUX_MIN,
PMHAL_PRCM_VIDEOPLL_MUX_VIDEO1 = 1U,
PMHAL_PRCM_VIDEOPLL_MUX_VIDEO2 = 2U,
PMHAL_PRCM_VIDEOPLL_MUX_ABE = 3U,
PMHAL_PRCM_VIDEOPLL_MUX_VIDEO1_HSDIVIDER_CLKOUT3 = 4U,
PMHAL_PRCM_VIDEOPLL_MUX_DPLL_PRCM = 5U,
PMHAL_PRCM_VIDEOPLL_MUX_DPLL_HDMI_CLK1 = 6U,
PMHAL_PRCM_VIDEOPLL_MUX_DPLL_DSI1_A_CLK1 = 7U,
PMHAL_PRCM_VIDEOPLL_MUX_DPLL_DSI1_B_CLK1 = 8U,
PMHAL_PRCM_VIDEOPLL_MUX_DPLL_DSI1_C_CLK1 = 9U,
PMHAL_PRCM_VIDEOPLL_MUX_MAX = PMHAL_PRCM_VIDEOPLL_MUX_DPLL_DSI1_C_CLK1 + 1U,
PMHAL_PRCM_VIDEOPLL_MUX_INVALID = 0x7FFFFFFF
, PMHAL_PRCM_VIDEOPLL_MUX_HDMI = PMHAL_PRCM_VIDEOPLL_MUX_MIN,
PMHAL_PRCM_VIDEOPLL_MUX_VIDEO1 = 1U,
PMHAL_PRCM_VIDEOPLL_MUX_ABE = 2U,
PMHAL_PRCM_VIDEOPLL_MUX_VIDEO1_HSDIVIDER_CLKOUT3 = 3U,
PMHAL_PRCM_VIDEOPLL_MUX_DPLL_PRCM = 4U,
PMHAL_PRCM_VIDEOPLL_MUX_DPLL_HDMI_CLK1 = 5U,
PMHAL_PRCM_VIDEOPLL_MUX_DPLL_DSI1_A_CLK1 = 6U,
PMHAL_PRCM_VIDEOPLL_MUX_DPLL_DSI1_B_CLK1 = 7U,
PMHAL_PRCM_VIDEOPLL_MUX_DPLL_DSI1_C_CLK1 = 8U,
PMHAL_PRCM_VIDEOPLL_MUX_MAX = PMHAL_PRCM_VIDEOPLL_MUX_DPLL_DSI1_C_CLK1 + 1U,
PMHAL_PRCM_VIDEOPLL_MUX_INVALID = 0x7FFFFFFF
} |
| | Enum for the MUX's parent id Used in Display Subsystem Caution: Do not change the enum values. More...
|
| |
| enum | pmhalPrcmVideopllDssClkSrcMuxId_t {
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MIN = 0U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MUX_A = PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MIN,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MUX_B = 1U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MUX_C = 2U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_LCD1_CLK_SWITCH = 3U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_LCD2_CLK_SWITCH = 4U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_LCD3_CLK_SWITCH = 5U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_F_CLK_SWITCH = 6U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MUX_MAX,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MIN = 0U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MUX_A = PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MIN,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MUX_B = 1U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MUX_C = 2U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_LCD1_CLK_SWITCH = 3U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_LCD2_CLK_SWITCH = 4U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_LCD3_CLK_SWITCH = 5U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_F_CLK_SWITCH = 6U,
PMHAL_PRCM_VIDEOPLL_DSS_CLKSRC_MUX_MAX
} |
| | Enum for the MUX's Used in Display Subsystem Caution: Do not change the enum values. More...
|
| |
| enum | pmhalPrcmCpuId {
PMHAL_PRCM_CPU_ID_MIN = 0,
PMHAL_PRCM_CPU_ID_MPU = PMHAL_PRCM_CPU_ID_MIN,
PMHAL_PRCM_CPU_ID_IPU = 1,
PMHAL_PRCM_CPU_ID_IVAHD = 2,
PMHAL_PRCM_CPU_ID_DSP = 3,
PMHAL_PRCM_CPU_ID_EVE = 4,
PMHAL_PRCM_CPU_ID_GPU = 5,
PMHAL_PRCM_CPU_ID_MAX = PMHAL_PRCM_CPU_ID_GPU,
PMHAL_PRCM_CPU_ID_COUNT = PMHAL_PRCM_CPU_ID_MAX + 1,
PMHAL_PRCM_CPU_ID_UNDEF = (-(int32_t)1),
PMHAL_PRCM_CPU_ID_MIN = 0,
PMHAL_PRCM_CPU_ID_MPU = PMHAL_PRCM_CPU_ID_MIN,
PMHAL_PRCM_CPU_ID_IPU = 1,
PMHAL_PRCM_CPU_ID_IVAHD = 2,
PMHAL_PRCM_CPU_ID_DSP = 3,
PMHAL_PRCM_CPU_ID_GPU = 4,
PMHAL_PRCM_CPU_ID_MAX = PMHAL_PRCM_CPU_ID_GPU,
PMHAL_PRCM_CPU_ID_COUNT = PMHAL_PRCM_CPU_ID_MAX + 1,
PMHAL_PRCM_CPU_ID_UNDEF = (-(int32_t)1),
PMHAL_PRCM_CPU_ID_MIN = 0,
PMHAL_PRCM_CPU_ID_IPU = PMHAL_PRCM_CPU_ID_MIN,
PMHAL_PRCM_CPU_ID_DSP = 1,
PMHAL_PRCM_CPU_ID_EVE = 2,
PMHAL_PRCM_CPU_ID_MAX = PMHAL_PRCM_CPU_ID_EVE,
PMHAL_PRCM_CPU_ID_COUNT = PMHAL_PRCM_CPU_ID_MAX + 1,
PMHAL_PRCM_CPU_ID_UNDEF = (-(int32_t)1),
PMHAL_PRCM_CPU_ID_MIN = 0,
PMHAL_PRCM_CPU_ID_MPU = PMHAL_PRCM_CPU_ID_MIN,
PMHAL_PRCM_CPU_ID_MAX = PMHAL_PRCM_CPU_ID_MPU,
PMHAL_PRCM_CPU_ID_COUNT = PMHAL_PRCM_CPU_ID_MAX + 1,
PMHAL_PRCM_CPU_ID_UNDEF = -1,
PMHAL_PRCM_CPU_ID_MIN = 0,
PMHAL_PRCM_CPU_ID_MPU = PMHAL_PRCM_CPU_ID_MIN,
PMHAL_PRCM_CPU_ID_MAX = PMHAL_PRCM_CPU_ID_MPU,
PMHAL_PRCM_CPU_ID_COUNT = PMHAL_PRCM_CPU_ID_MAX + 1,
PMHAL_PRCM_CPU_ID_UNDEF = -1
} |
| | Enumeration of all the Modules that are associated with OPP. These are the processing units and Interconnect. More...
|
| |
| enum | pmhalPrcmVmOppId {
PMHAL_VM_OPP_MIN = 0,
PMHAL_VM_OPP_LOW = 0,
PMHAL_VM_OPP_NOM = 1,
PMHAL_VM_OPP_OD = 2,
PMHAL_VM_OPP_HIGH = 3,
PMHAL_VM_OPP_MAX = 4,
PMHAL_VM_OPP_UNDEF = (-(int32_t)1),
PMHAL_VM_OPP_MIN = 0,
PMHAL_VM_OPP_LOW = 0,
PMHAL_VM_OPP_NOM = 1,
PMHAL_VM_OPP_OD = 2,
PMHAL_VM_OPP_HIGH = 3,
PMHAL_VM_OPP_MAX = 4,
PMHAL_VM_OPP_UNDEF = (-(int32_t)1),
PMHAL_VM_OPP_MIN = 0,
PMHAL_VM_OPP_LOW = 0,
PMHAL_VM_OPP_NOM = 1,
PMHAL_VM_OPP_OD = 2,
PMHAL_VM_OPP_HIGH = 3,
PMHAL_VM_OPP_MAX = 4,
PMHAL_VM_OPP_UNDEF = (-(int32_t)1),
PMHAL_VM_OPP_MIN = 0,
PMHAL_VM_OPP_LOW = 0,
PMHAL_VM_OPP_NOM = 1,
PMHAL_VM_OPP_OD = 2,
PMHAL_VM_OPP_HIGH = 3,
PMHAL_VM_OPP_HIGH2 = 4,
PMHAL_VM_OPP_MAX = 5,
PMHAL_VM_OPP_UNDEF = -1,
PMHAL_VM_OPP_MIN = 0,
PMHAL_VM_OPP_LOW = 0,
PMHAL_VM_OPP_NOM = 1,
PMHAL_VM_OPP_OD = 2,
PMHAL_VM_OPP_HIGH = 3,
PMHAL_VM_OPP_HIGH2 = 4,
PMHAL_VM_OPP_MAX = 5,
PMHAL_VM_OPP_UNDEF = -1
} |
| | Operating Performance Points. More...
|
| |
| enum | pmhalPrcmModuleMStbyMode {
PMHAL_PRCM_MODULE_MSTANDBYMODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_FORCE_STANDBY,
PMHAL_PRCM_MODULE_MSTANDBYMODE_NO_STANDBY = 0x1U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_SMART_STANDBY = 0x2U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_SMART_STANDBY_WAKEUP_CAPABLE = 0x3U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_MAX,
PMHAL_PRCM_MODULE_MSTANDBYMODE_INVALID = 0xFF,
PMHAL_PRCM_MODULE_MSTANDBYMODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_FORCE_STANDBY,
PMHAL_PRCM_MODULE_MSTANDBYMODE_NO_STANDBY = 0x1U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_SMART_STANDBY = 0x2U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_SMART_STANDBY_WAKEUP_CAPABLE = 0x3U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_MAX,
PMHAL_PRCM_MODULE_MSTANDBYMODE_INVALID = 0xFF,
PMHAL_PRCM_MODULE_MSTANDBYMODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_FORCE_STANDBY,
PMHAL_PRCM_MODULE_MSTANDBYMODE_NO_STANDBY = 0x1U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_SMART_STANDBY = 0x2U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_SMART_STANDBY_WAKEUP_CAPABLE = 0x3U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_MAX,
PMHAL_PRCM_MODULE_MSTANDBYMODE_INVALID = 0xFF,
PMHAL_PRCM_MODULE_MSTANDBYMODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_FORCE_STANDBY,
PMHAL_PRCM_MODULE_MSTANDBYMODE_NO_STANDBY = 0x1U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_SMART_STANDBY = 0x2U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_SMART_STANDBY_WAKEUP_CAPABLE = 0x3U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_MAX,
PMHAL_PRCM_MODULE_MSTANDBYMODE_INVALID = 0xFF,
PMHAL_PRCM_MODULE_MSTANDBYMODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_FORCE_STANDBY,
PMHAL_PRCM_MODULE_MSTANDBYMODE_NO_STANDBY = 0x1U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_SMART_STANDBY = 0x2U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_SMART_STANDBY_WAKEUP_CAPABLE = 0x3U,
PMHAL_PRCM_MODULE_MSTANDBYMODE_MAX,
PMHAL_PRCM_MODULE_MSTANDBYMODE_INVALID = 0xFF
} |
| | Enum defining Idle Mode of a module- values are mapped from register description. More...
|
| |
| enum | pmhalPrcmModuleSModuleMode {
PMHAL_PRCM_MODULE_MODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_MODE_DISABLED = PMHAL_PRCM_MODULE_MODE_MIN,
PMHAL_PRCM_MODULE_MODE_AUTO = 0x1U,
PMHAL_PRCM_MODULE_MODE_ENABLED = 0x2U,
PMHAL_PRCM_MODULE_MODE_MAX = PMHAL_PRCM_MODULE_MODE_ENABLED,
PMHAL_PRCM_MODULE_MODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_MODE_DISABLED = PMHAL_PRCM_MODULE_MODE_MIN,
PMHAL_PRCM_MODULE_MODE_AUTO = 0x1U,
PMHAL_PRCM_MODULE_MODE_ENABLED = 0x2U,
PMHAL_PRCM_MODULE_MODE_MAX = PMHAL_PRCM_MODULE_MODE_ENABLED,
PMHAL_PRCM_MODULE_MODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_MODE_DISABLED = PMHAL_PRCM_MODULE_MODE_MIN,
PMHAL_PRCM_MODULE_MODE_AUTO = 0x1U,
PMHAL_PRCM_MODULE_MODE_ENABLED = 0x2U,
PMHAL_PRCM_MODULE_MODE_MAX = PMHAL_PRCM_MODULE_MODE_ENABLED,
PMHAL_PRCM_MODULE_MODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_MODE_DISABLED = PMHAL_PRCM_MODULE_MODE_MIN,
PMHAL_PRCM_MODULE_MODE_RESERVED = 0x1U,
PMHAL_PRCM_MODULE_MODE_ENABLED = 0x2U,
PMHAL_PRCM_MODULE_MODE_MAX = PMHAL_PRCM_MODULE_MODE_ENABLED,
PMHAL_PRCM_MODULE_MODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_MODE_DISABLED = PMHAL_PRCM_MODULE_MODE_MIN,
PMHAL_PRCM_MODULE_MODE_RESERVED = 0x1U,
PMHAL_PRCM_MODULE_MODE_ENABLED = 0x2U,
PMHAL_PRCM_MODULE_MODE_MAX = PMHAL_PRCM_MODULE_MODE_ENABLED
} |
| | Enum defining different modes of a module. More...
|
| |
| enum | pmhalPrcmModuleSIdleMode {
PMHAL_PRCM_MODULE_SIDLEMODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_SIDLEMODE_FORCE_IDLE = PMHAL_PRCM_MODULE_SIDLEMODE_MIN,
PMHAL_PRCM_MODULE_SIDLEMODE_NO_IDLE = 0x1U,
PMHAL_PRCM_MODULE_SIDLEMODE_SMART_IDLE = 0x2U,
PMHAL_PRCM_MODULE_SIDLEMODE_SMART_IDLE_WAKEUP_CAPABLE = 0x3U,
PMHAL_PRCM_MODULE_SIDLEMODE_MAX,
PMHAL_PRCM_MODULE_SIDLEMODE_INVALID = 0xFF,
PMHAL_PRCM_MODULE_SIDLEMODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_SIDLEMODE_FORCE_IDLE = PMHAL_PRCM_MODULE_SIDLEMODE_MIN,
PMHAL_PRCM_MODULE_SIDLEMODE_NO_IDLE = 0x1U,
PMHAL_PRCM_MODULE_SIDLEMODE_SMART_IDLE = 0x2U,
PMHAL_PRCM_MODULE_SIDLEMODE_SMART_IDLE_WAKEUP_CAPABLE = 0x3U,
PMHAL_PRCM_MODULE_SIDLEMODE_MAX,
PMHAL_PRCM_MODULE_SIDLEMODE_INVALID = 0xFF,
PMHAL_PRCM_MODULE_SIDLEMODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_SIDLEMODE_FORCE_IDLE = PMHAL_PRCM_MODULE_SIDLEMODE_MIN,
PMHAL_PRCM_MODULE_SIDLEMODE_NO_IDLE = 0x1U,
PMHAL_PRCM_MODULE_SIDLEMODE_SMART_IDLE = 0x2U,
PMHAL_PRCM_MODULE_SIDLEMODE_SMART_IDLE_WAKEUP_CAPABLE = 0x3U,
PMHAL_PRCM_MODULE_SIDLEMODE_MAX,
PMHAL_PRCM_MODULE_SIDLEMODE_INVALID = 0xFF,
PMHAL_PRCM_MODULE_SIDLEMODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_SIDLEMODE_FORCE_IDLE = PMHAL_PRCM_MODULE_SIDLEMODE_MIN,
PMHAL_PRCM_MODULE_SIDLEMODE_NO_IDLE = 0x1U,
PMHAL_PRCM_MODULE_SIDLEMODE_SMART_IDLE = 0x2U,
PMHAL_PRCM_MODULE_SIDLEMODE_SMART_IDLE_WAKEUP_CAPABLE = 0x3U,
PMHAL_PRCM_MODULE_SIDLEMODE_MAX,
PMHAL_PRCM_MODULE_SIDLEMODE_INVALID = 0xFF,
PMHAL_PRCM_MODULE_SIDLEMODE_MIN = 0x0U,
PMHAL_PRCM_MODULE_SIDLEMODE_FORCE_IDLE = PMHAL_PRCM_MODULE_SIDLEMODE_MIN,
PMHAL_PRCM_MODULE_SIDLEMODE_NO_IDLE = 0x1U,
PMHAL_PRCM_MODULE_SIDLEMODE_SMART_IDLE = 0x2U,
PMHAL_PRCM_MODULE_SIDLEMODE_SMART_IDLE_WAKEUP_CAPABLE = 0x3U,
PMHAL_PRCM_MODULE_SIDLEMODE_MAX,
PMHAL_PRCM_MODULE_SIDLEMODE_INVALID = 0xFF
} |
| | Enum defining Idle Mode of a module- values are mapped from register description. More...
|
| |
| enum | pmhalPrcmModuleSIdleState {
PMHAL_PRCM_MODULE_IDLEST_MIN = 0x0U,
PMHAL_PRCM_MODULE_SIDLESTATE_FUNCTIONAL = PMHAL_PRCM_MODULE_IDLEST_MIN,
PMHAL_PRCM_MODULE_SIDLESTATE_INTRANSITION = 0x1U,
PMHAL_PRCM_MODULE_SIDLESTATE_INTERFACE_IDLE = 0x2U,
PMHAL_PRCM_MODULE_SIDLESTATE_DISABLED = 0x3U,
PMHAL_PRCM_MODULE_IDLEST_MAX = PMHAL_PRCM_MODULE_SIDLESTATE_DISABLED,
PMHAL_PRCM_MODULE_SIDLESTATE_DETERMINED_BY_CLK_STATE
, PMHAL_PRCM_MODULE_IDLEST_MIN = 0x0U,
PMHAL_PRCM_MODULE_SIDLESTATE_FUNCTIONAL = PMHAL_PRCM_MODULE_IDLEST_MIN,
PMHAL_PRCM_MODULE_SIDLESTATE_INTRANSITION = 0x1U,
PMHAL_PRCM_MODULE_SIDLESTATE_INTERFACE_IDLE = 0x2U,
PMHAL_PRCM_MODULE_SIDLESTATE_DISABLED = 0x3U,
PMHAL_PRCM_MODULE_IDLEST_MAX = PMHAL_PRCM_MODULE_SIDLESTATE_DISABLED,
PMHAL_PRCM_MODULE_SIDLESTATE_DETERMINED_BY_CLK_STATE
, PMHAL_PRCM_MODULE_IDLEST_MIN = 0x0U,
PMHAL_PRCM_MODULE_SIDLESTATE_FUNCTIONAL = PMHAL_PRCM_MODULE_IDLEST_MIN,
PMHAL_PRCM_MODULE_SIDLESTATE_INTRANSITION = 0x1U,
PMHAL_PRCM_MODULE_SIDLESTATE_INTERFACE_IDLE = 0x2U,
PMHAL_PRCM_MODULE_SIDLESTATE_DISABLED = 0x3U,
PMHAL_PRCM_MODULE_IDLEST_MAX = PMHAL_PRCM_MODULE_SIDLESTATE_DISABLED,
PMHAL_PRCM_MODULE_SIDLESTATE_DETERMINED_BY_CLK_STATE
, PMHAL_PRCM_MODULE_IDLEST_MIN = 0x0U,
PMHAL_PRCM_MODULE_SIDLESTATE_FUNCTIONAL = PMHAL_PRCM_MODULE_IDLEST_MIN,
PMHAL_PRCM_MODULE_SIDLESTATE_INTRANSITION = 0x1U,
PMHAL_PRCM_MODULE_SIDLESTATE_INTERFACE_IDLE = 0x2U,
PMHAL_PRCM_MODULE_SIDLESTATE_DISABLED = 0x3U,
PMHAL_PRCM_MODULE_IDLEST_MAX = PMHAL_PRCM_MODULE_SIDLESTATE_DISABLED,
PMHAL_PRCM_MODULE_SIDLESTATE_DETERMINED_BY_CLK_STATE
,
PMHAL_PRCM_MODULE_IDLEST_MIN = 0x0U,
PMHAL_PRCM_MODULE_SIDLESTATE_FUNCTIONAL = PMHAL_PRCM_MODULE_IDLEST_MIN,
PMHAL_PRCM_MODULE_SIDLESTATE_INTRANSITION = 0x1U,
PMHAL_PRCM_MODULE_SIDLESTATE_INTERFACE_IDLE = 0x2U,
PMHAL_PRCM_MODULE_SIDLESTATE_DISABLED = 0x3U,
PMHAL_PRCM_MODULE_IDLEST_MAX = PMHAL_PRCM_MODULE_SIDLESTATE_DISABLED,
PMHAL_PRCM_MODULE_SIDLESTATE_DETERMINED_BY_CLK_STATE
} |
| | Enum defining idle states of the module. These values can be used to check the state of the module after configuring the module mode property. More...
|
| |
| enum | pmhalPrcmModuleMStbyState {
PMHAL_PRCM_CLKCTRL_STBYST_MIN = 0x0U,
PMHAL_PRCM_MODULE_MSTANDBYSTATE_FUNCTIONAL = PMHAL_PRCM_CLKCTRL_STBYST_MIN,
PMHAL_PRCM_MODULE_MSTANDBYSTATE_STANDBY = 0x1U,
PMHAL_PRCM_CLKCTRL_STBYST_MAX = PMHAL_PRCM_MODULE_MSTANDBYSTATE_STANDBY,
PMHAL_PRCM_CLKCTRL_STBYST_MIN = 0x0U,
PMHAL_PRCM_MODULE_MSTANDBYSTATE_FUNCTIONAL = PMHAL_PRCM_CLKCTRL_STBYST_MIN,
PMHAL_PRCM_MODULE_MSTANDBYSTATE_STANDBY = 0x1U,
PMHAL_PRCM_CLKCTRL_STBYST_MAX = PMHAL_PRCM_MODULE_MSTANDBYSTATE_STANDBY,
PMHAL_PRCM_CLKCTRL_STBYST_MIN = 0x0U,
PMHAL_PRCM_MODULE_MSTANDBYSTATE_FUNCTIONAL = PMHAL_PRCM_CLKCTRL_STBYST_MIN,
PMHAL_PRCM_MODULE_MSTANDBYSTATE_STANDBY = 0x1U,
PMHAL_PRCM_CLKCTRL_STBYST_MAX = PMHAL_PRCM_MODULE_MSTANDBYSTATE_STANDBY,
PMHAL_PRCM_CLKCTRL_STBYST_MIN = 0x0U,
PMHAL_PRCM_MODULE_MSTANDBYSTATE_FUNCTIONAL = PMHAL_PRCM_CLKCTRL_STBYST_MIN,
PMHAL_PRCM_MODULE_MSTANDBYSTATE_STANDBY = 0x1U,
PMHAL_PRCM_CLKCTRL_STBYST_MAX = PMHAL_PRCM_MODULE_MSTANDBYSTATE_STANDBY,
PMHAL_PRCM_CLKCTRL_STBYST_MIN = 0x0U,
PMHAL_PRCM_MODULE_MSTANDBYSTATE_FUNCTIONAL = PMHAL_PRCM_CLKCTRL_STBYST_MIN,
PMHAL_PRCM_MODULE_MSTANDBYSTATE_STANDBY = 0x1U,
PMHAL_PRCM_CLKCTRL_STBYST_MAX = PMHAL_PRCM_MODULE_MSTANDBYSTATE_STANDBY
} |
| | Enum defining standby states of the module (Master only). These values can be used to check the state of the module after configuring the module mode property. More...
|
| |
| enum | pmhalPrcmModuleSClockActivity {
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_MIN = 0x0U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_GATE_FUNC_INT,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_FUNC_NOINT = 0x1U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_NOFUNC_INT = 0x2U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_NOFUNC_NOINT = 0x3U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_MAX,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_MIN = 0x0U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_GATE_FUNC_INT,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_FUNC_NOINT = 0x1U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_NOFUNC_INT = 0x2U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_NOFUNC_NOINT = 0x3U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_MAX,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_MIN = 0x0U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_GATE_FUNC_INT,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_FUNC_NOINT = 0x1U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_NOFUNC_INT = 0x2U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_NOFUNC_NOINT = 0x3U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_MAX,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_MIN = 0x0U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_GATE_FUNC_INT,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_FUNC_NOINT = 0x1U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_NOFUNC_INT = 0x2U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_NOFUNC_NOINT = 0x3U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_MAX,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_MIN = 0x0U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_GATE_FUNC_INT,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_FUNC_NOINT = 0x1U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_NOFUNC_INT = 0x2U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_NOFUNC_NOINT = 0x3U,
PMHAL_PRCM_MODULE_SCLOCKACTIVITY_MAX
} |
| | Enum defining content of Clock Activity Settings for Idle Ack Clock Gating Conditions. More...
|
| |
| enum | pmhalPrcmSysClkVal {
PMHAL_PRCM_SYSCLK_UNINITIALIZED = 0U,
PMHAL_PRCM_SYSCLK_MIN = PMHAL_PRCM_SYSCLK_UNINITIALIZED,
PMHAL_PRCM_SYSCLK_12_MHZ = 1U,
PMHAL_PRCM_SYSCLK_20_MHZ = 2U,
PMHAL_PRCM_SYSCLK_16_8_MHZ = 3U,
PMHAL_PRCM_SYSCLK_19_2_MHZ = 4U,
PMHAL_PRCM_SYSCLK_26_MHZ = 5U,
PMHAL_PRCM_SYSCLK_27_MHZ = 6U,
PMHAL_PRCM_SYSCLK_38_4_MHZ = 7U,
PMHAL_PRCM_SYSCLK_MAX = PMHAL_PRCM_SYSCLK_38_4_MHZ,
PMHAL_PRCM_SYSCLK_COUNT = PMHAL_PRCM_SYSCLK_MAX + 1U,
PMHAL_PRCM_SYSCLK_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_SYSCLK_UNINITIALIZED = 0U,
PMHAL_PRCM_SYSCLK_MIN = PMHAL_PRCM_SYSCLK_UNINITIALIZED,
PMHAL_PRCM_SYSCLK_12_MHZ = 1U,
PMHAL_PRCM_SYSCLK_20_MHZ = 2U,
PMHAL_PRCM_SYSCLK_16_8_MHZ = 3U,
PMHAL_PRCM_SYSCLK_19_2_MHZ = 4U,
PMHAL_PRCM_SYSCLK_26_MHZ = 5U,
PMHAL_PRCM_SYSCLK_27_MHZ = 6U,
PMHAL_PRCM_SYSCLK_38_4_MHZ = 7U,
PMHAL_PRCM_SYSCLK_MAX = PMHAL_PRCM_SYSCLK_38_4_MHZ,
PMHAL_PRCM_SYSCLK_COUNT = PMHAL_PRCM_SYSCLK_MAX + 1U,
PMHAL_PRCM_SYSCLK_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_SYSCLK_UNINITIALIZED = 0U,
PMHAL_PRCM_SYSCLK_MIN = PMHAL_PRCM_SYSCLK_UNINITIALIZED,
PMHAL_PRCM_SYSCLK_12_MHZ = 1U,
PMHAL_PRCM_SYSCLK_20_MHZ = 2U,
PMHAL_PRCM_SYSCLK_16_8_MHZ = 3U,
PMHAL_PRCM_SYSCLK_19_2_MHZ = 4U,
PMHAL_PRCM_SYSCLK_26_MHZ = 5U,
PMHAL_PRCM_SYSCLK_27_MHZ = 6U,
PMHAL_PRCM_SYSCLK_38_4_MHZ = 7U,
PMHAL_PRCM_SYSCLK_MAX = PMHAL_PRCM_SYSCLK_38_4_MHZ,
PMHAL_PRCM_SYSCLK_COUNT = PMHAL_PRCM_SYSCLK_MAX + 1U,
PMHAL_PRCM_SYSCLK_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_SYSCLK_19_2_MHZ = 0U,
PMHAL_PRCM_SYSCLK_MIN = PMHAL_PRCM_SYSCLK_19_2_MHZ,
PMHAL_PRCM_SYSCLK_24_MHZ = 1U,
PMHAL_PRCM_SYSCLK_25_MHZ = 2U,
PMHAL_PRCM_SYSCLK_26_MHZ = 3U,
PMHAL_PRCM_SYSCLK_MAX = PMHAL_PRCM_SYSCLK_26_MHZ,
PMHAL_PRCM_SYSCLK_COUNT = PMHAL_PRCM_SYSCLK_MAX + 1U,
PMHAL_PRCM_SYSCLK_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_SYSCLK_19_2_MHZ = 0U,
PMHAL_PRCM_SYSCLK_MIN = PMHAL_PRCM_SYSCLK_19_2_MHZ,
PMHAL_PRCM_SYSCLK_24_MHZ = 1U,
PMHAL_PRCM_SYSCLK_25_MHZ = 2U,
PMHAL_PRCM_SYSCLK_26_MHZ = 3U,
PMHAL_PRCM_SYSCLK_MAX = PMHAL_PRCM_SYSCLK_26_MHZ,
PMHAL_PRCM_SYSCLK_COUNT = PMHAL_PRCM_SYSCLK_MAX + 1U,
PMHAL_PRCM_SYSCLK_UNDEF = 0x7FFFFFFFU
} |
| | Index for System Clock Frequency values. More...
|
| |
| enum | pmhalPrcmClockActivityState {
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_MIN = 0x0U,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_GATED,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_ENABLED = 0x1U,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_MAX,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_MIN = 0x0U,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_GATED,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_ENABLED = 0x1U,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_MAX,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_MIN = 0x0U,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_GATED,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_ENABLED = 0x1U,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_MAX,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_MIN = 0x0U,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_GATED,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_ENABLED = 0x1U,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_MAX,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_MIN = 0x0U,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_GATED,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_ENABLED = 0x1U,
PMHAL_PRCM_MODULE_CLOCKACTIVITY_CLK_MAX
} |
| | Enum defining content of clock status. More...
|
| |
| enum | pmhalPrcmCdClkTrnModes {
PMHAL_PRCM_CD_CLKTRNMODES_MIN = 0U,
PMHAL_PRCM_CD_CLKTRNMODES_NO_SLEEP = PMHAL_PRCM_CD_CLKTRNMODES_MIN,
PMHAL_PRCM_CD_CLKTRNMODES_SW_SLEEP = 1U,
PMHAL_PRCM_CD_CLKTRNMODES_SW_WAKEUP = 2U,
PMHAL_PRCM_CD_CLKTRNMODES_HW_AUTO = 3U,
PMHAL_PRCM_CD_CLKTRNMODES_MAX = PMHAL_PRCM_CD_CLKTRNMODES_HW_AUTO,
PMHAL_PRCM_CD_CLKTRNMODES_MIN = 0U,
PMHAL_PRCM_CD_CLKTRNMODES_NO_SLEEP = PMHAL_PRCM_CD_CLKTRNMODES_MIN,
PMHAL_PRCM_CD_CLKTRNMODES_SW_SLEEP = 1U,
PMHAL_PRCM_CD_CLKTRNMODES_SW_WAKEUP = 2U,
PMHAL_PRCM_CD_CLKTRNMODES_HW_AUTO = 3U,
PMHAL_PRCM_CD_CLKTRNMODES_MAX = PMHAL_PRCM_CD_CLKTRNMODES_HW_AUTO,
PMHAL_PRCM_CD_CLKTRNMODES_MIN = 0U,
PMHAL_PRCM_CD_CLKTRNMODES_NO_SLEEP = PMHAL_PRCM_CD_CLKTRNMODES_MIN,
PMHAL_PRCM_CD_CLKTRNMODES_SW_SLEEP = 1U,
PMHAL_PRCM_CD_CLKTRNMODES_SW_WAKEUP = 2U,
PMHAL_PRCM_CD_CLKTRNMODES_HW_AUTO = 3U,
PMHAL_PRCM_CD_CLKTRNMODES_MAX = PMHAL_PRCM_CD_CLKTRNMODES_HW_AUTO,
PMHAL_PRCM_CD_CLKTRNMODES_MIN = 0U,
PMHAL_PRCM_CD_CLKTRNMODES_NO_SLEEP = PMHAL_PRCM_CD_CLKTRNMODES_MIN,
PMHAL_PRCM_CD_CLKTRNMODES_SW_SLEEP = 1U,
PMHAL_PRCM_CD_CLKTRNMODES_SW_WAKEUP = 2U,
PMHAL_PRCM_CD_CLKTRNMODES_MAX = PMHAL_PRCM_CD_CLKTRNMODES_SW_WAKEUP,
PMHAL_PRCM_CD_CLKTRNMODES_MIN = 0U,
PMHAL_PRCM_CD_CLKTRNMODES_NO_SLEEP = PMHAL_PRCM_CD_CLKTRNMODES_MIN,
PMHAL_PRCM_CD_CLKTRNMODES_SW_SLEEP = 1U,
PMHAL_PRCM_CD_CLKTRNMODES_SW_WAKEUP = 2U,
PMHAL_PRCM_CD_CLKTRNMODES_HW_AUTO = 3U,
PMHAL_PRCM_CD_CLKTRNMODES_MAX = PMHAL_PRCM_CD_CLKTRNMODES_HW_AUTO
} |
| | Enum defining clock domain control values. These values can be used to control the clock domain while initializing the system, entering sleep state and waking up from sleep state. More...
|
| |
| enum | pmhalPrcmPdState {
PMHAL_PRCM_PD_STATUS_MIN = 0U,
PMHAL_PRCM_PD_STATE_OFF = PMHAL_PRCM_PD_STATUS_MIN,
PMHAL_PRCM_PD_STATE_RETENTION = 1U,
PMHAL_PRCM_PD_STATE_ON_INACTIVE = 2U,
PMHAL_PRCM_PD_STATE_ON_ACTIVE = 3U,
PMHAL_PRCM_PD_STATUS_MAX = PMHAL_PRCM_PD_STATE_ON_ACTIVE,
PMHAL_PRCM_PD_STATUS_COUNT = PMHAL_PRCM_PD_STATUS_MAX + 1U,
PMHAL_PRCM_PD_STATUS_MIN = 0U,
PMHAL_PRCM_PD_STATE_OFF = PMHAL_PRCM_PD_STATUS_MIN,
PMHAL_PRCM_PD_STATE_RETENTION = 1U,
PMHAL_PRCM_PD_STATE_ON_INACTIVE = 2U,
PMHAL_PRCM_PD_STATE_ON_ACTIVE = 3U,
PMHAL_PRCM_PD_STATUS_MAX = PMHAL_PRCM_PD_STATE_ON_ACTIVE,
PMHAL_PRCM_PD_STATUS_COUNT = PMHAL_PRCM_PD_STATUS_MAX + 1U,
PMHAL_PRCM_PD_STATUS_MIN = 0U,
PMHAL_PRCM_PD_STATE_OFF = PMHAL_PRCM_PD_STATUS_MIN,
PMHAL_PRCM_PD_STATE_RETENTION = 1U,
PMHAL_PRCM_PD_STATE_ON_INACTIVE = 2U,
PMHAL_PRCM_PD_STATE_ON_ACTIVE = 3U,
PMHAL_PRCM_PD_STATUS_MAX = PMHAL_PRCM_PD_STATE_ON_ACTIVE,
PMHAL_PRCM_PD_STATUS_COUNT = PMHAL_PRCM_PD_STATUS_MAX + 1U,
PMHAL_PRCM_PD_STATUS_MIN = 0U,
PMHAL_PRCM_PD_STATE_OFF = PMHAL_PRCM_PD_STATUS_MIN,
PMHAL_PRCM_PD_STATE_RETENTION = 1U,
PMHAL_PRCM_PD_STATE_ON_INACTIVE = 2U,
PMHAL_PRCM_PD_STATE_ON_ACTIVE = 3U,
PMHAL_PRCM_PD_STATUS_MAX = PMHAL_PRCM_PD_STATE_ON_ACTIVE,
PMHAL_PRCM_PD_STATUS_COUNT = PMHAL_PRCM_PD_STATUS_MAX + 1U,
PMHAL_PRCM_PD_STATUS_MIN = 0U,
PMHAL_PRCM_PD_STATE_OFF = PMHAL_PRCM_PD_STATUS_MIN,
PMHAL_PRCM_PD_STATE_RETENTION = 1U,
PMHAL_PRCM_PD_STATE_ON_INACTIVE = 2U,
PMHAL_PRCM_PD_STATE_ON_ACTIVE = 3U,
PMHAL_PRCM_PD_STATUS_MAX = PMHAL_PRCM_PD_STATE_ON_ACTIVE,
PMHAL_PRCM_PD_STATUS_COUNT = PMHAL_PRCM_PD_STATUS_MAX + 1U
} |
| | Enum defining power domain status values. These values can be used to control the clock domain while initializing the system, entering sleep state and waking up from sleep state. More...
|
| |
| enum | pmhalStaticDepBitShift {
PMHAL_SD_SHIFT_RESERVED_31 = 31U,
PMHAL_SD_SHIFT_ATL_STATDEP = 30U,
PMHAL_SD_SHIFT_PCIE_STATDEP = 29U,
PMHAL_SD_SHIFT_VPE_STATDEP = 28U,
PMHAL_SD_SHIFT_L4PER3_STATDEP = 27U,
PMHAL_SD_SHIFT_L4PER2_STATDEP = 26U,
PMHAL_SD_SHIFT_GMAC_STATDEP = 25U,
PMHAL_SD_SHIFT_IPU_STATDEP = 24U,
PMHAL_SD_SHIFT_IPU1_STATDEP = 23U,
PMHAL_SD_SHIFT_EVE4_STATDEP = 22U,
PMHAL_SD_SHIFT_EVE3_STATDEP = 21U,
PMHAL_SD_SHIFT_EVE2_STATDEP = 20U,
PMHAL_SD_SHIFT_EVE1_STATDEP = 19U,
PMHAL_SD_SHIFT_DSP2_STATDEP = 18U,
PMHAL_SD_SHIFT_CUSTEFUSE_STATDEP = 17U,
PMHAL_SD_SHIFT_COREAON_STATDEP = 16U,
PMHAL_SD_SHIFT_WKUPAON_STATDEP = 15U,
PMHAL_SD_SHIFT_L4SEC_STATDEP = 14U,
PMHAL_SD_SHIFT_L4PER_STATDEP = 13U,
PMHAL_SD_SHIFT_L4CFG_STATDEP = 12U,
PMHAL_SD_SHIFT_SDMA_STATDEP = 11U,
PMHAL_SD_SHIFT_GPU_STATDEP = 10U,
PMHAL_SD_SHIFT_CAM_STATDEP = 9U,
PMHAL_SD_SHIFT_DSS_STATDEP = 8U,
PMHAL_SD_SHIFT_L3INIT_STATDEP = 7U,
PMHAL_SD_SHIFT_RESERVED_6 = 6U,
PMHAL_SD_SHIFT_L3MAIN1_STATDEP = 5U,
PMHAL_SD_SHIFT_EMIF_STATDEP = 4U,
PMHAL_SD_SHIFT_RESERVED_3 = 3U,
PMHAL_SD_SHIFT_IVA_STATDEP = 2U,
PMHAL_SD_SHIFT_DSP1_STATDEP = 1U,
PMHAL_SD_SHIFT_IPU2_STATDEP = 0U,
PMHAL_SD_SHIFT_RESERVED_31 = 31U,
PMHAL_SD_SHIFT_ATL_STATDEP = 30U,
PMHAL_SD_SHIFT_PCIE_STATDEP = 29U,
PMHAL_SD_SHIFT_VPE_STATDEP = 28U,
PMHAL_SD_SHIFT_L4PER3_STATDEP = 27U,
PMHAL_SD_SHIFT_L4PER2_STATDEP = 26U,
PMHAL_SD_SHIFT_GMAC_STATDEP = 25U,
PMHAL_SD_SHIFT_IPU_STATDEP = 24U,
PMHAL_SD_SHIFT_IPU1_STATDEP = 23U,
PMHAL_SD_SHIFT_EVE4_STATDEP = 22U,
PMHAL_SD_SHIFT_EVE3_STATDEP = 21U,
PMHAL_SD_SHIFT_EVE2_STATDEP = 20U,
PMHAL_SD_SHIFT_EVE1_STATDEP = 19U,
PMHAL_SD_SHIFT_DSP2_STATDEP = 18U,
PMHAL_SD_SHIFT_CUSTEFUSE_STATDEP = 17U,
PMHAL_SD_SHIFT_COREAON_STATDEP = 16U,
PMHAL_SD_SHIFT_WKUPAON_STATDEP = 15U,
PMHAL_SD_SHIFT_L4SEC_STATDEP = 14U,
PMHAL_SD_SHIFT_L4PER_STATDEP = 13U,
PMHAL_SD_SHIFT_L4CFG_STATDEP = 12U,
PMHAL_SD_SHIFT_SDMA_STATDEP = 11U,
PMHAL_SD_SHIFT_GPU_STATDEP = 10U,
PMHAL_SD_SHIFT_CAM_STATDEP = 9U,
PMHAL_SD_SHIFT_DSS_STATDEP = 8U,
PMHAL_SD_SHIFT_L3INIT_STATDEP = 7U,
PMHAL_SD_SHIFT_RESERVED_6 = 6U,
PMHAL_SD_SHIFT_L3MAIN1_STATDEP = 5U,
PMHAL_SD_SHIFT_EMIF_STATDEP = 4U,
PMHAL_SD_SHIFT_RESERVED_3 = 3U,
PMHAL_SD_SHIFT_IVA_STATDEP = 2U,
PMHAL_SD_SHIFT_DSP1_STATDEP = 1U,
PMHAL_SD_SHIFT_IPU2_STATDEP = 0U,
PMHAL_SD_SHIFT_RESERVED_31 = 31U,
PMHAL_SD_SHIFT_CRC_STATDEP = 30U,
PMHAL_SD_SHIFT_ISS_STATDEP = 28U,
PMHAL_SD_SHIFT_L4PER3_STATDEP = 27U,
PMHAL_SD_SHIFT_L4PER2_STATDEP = 26U,
PMHAL_SD_SHIFT_GMAC_STATDEP = 25U,
PMHAL_SD_SHIFT_IPU_STATDEP = 24U,
PMHAL_SD_SHIFT_IPU1_STATDEP = 23U,
PMHAL_SD_SHIFT_EVE1_STATDEP = 19U,
PMHAL_SD_SHIFT_DSP2_STATDEP = 18U,
PMHAL_SD_SHIFT_CUSTEFUSE_STATDEP = 17U,
PMHAL_SD_SHIFT_COREAON_STATDEP = 16U,
PMHAL_SD_SHIFT_WKUPAON_STATDEP = 15U,
PMHAL_SD_SHIFT_L4PER_STATDEP = 13U,
PMHAL_SD_SHIFT_L4CFG_STATDEP = 12U,
PMHAL_SD_SHIFT_SDMA_STATDEP = 11U,
PMHAL_SD_SHIFT_CAM_STATDEP = 9U,
PMHAL_SD_SHIFT_DSS_STATDEP = 8U,
PMHAL_SD_SHIFT_L3INIT_STATDEP = 7U,
PMHAL_SD_SHIFT_RESERVED_6 = 6U,
PMHAL_SD_SHIFT_L3MAIN1_STATDEP = 5U,
PMHAL_SD_SHIFT_EMIF_STATDEP = 4U,
PMHAL_SD_SHIFT_RESERVED_3 = 3U,
PMHAL_SD_SHIFT_DSP1_STATDEP = 1U,
PMHAL_SD_SHIFT_IPU2_STATDEP = 0U
} |
| | Enumeration of Static Dependency. More...
|
| |
| enum | pmhalPrcmDpllPostDivId {
PMHAL_PRCM_DPLL_POST_DIV_INVALID = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_POST_DIV_MIN = 0U,
PMHAL_PRCM_DPLL_POST_DIV_M2 = PMHAL_PRCM_DPLL_POST_DIV_MIN,
PMHAL_PRCM_DPLL_POST_DIV_M2X2 = 1U,
PMHAL_PRCM_DPLL_POST_DIV_M4 = 2U,
PMHAL_PRCM_DPLL_POST_DIV_M3 = 3U,
PMHAL_PRCM_DPLL_POST_DIV_M5 = 4U,
PMHAL_PRCM_DPLL_POST_DIV_M6 = 5U,
PMHAL_PRCM_DPLL_POST_DIV_H11 = 6U,
PMHAL_PRCM_DPLL_POST_DIV_H12 = 7U,
PMHAL_PRCM_DPLL_POST_DIV_H13 = 8U,
PMHAL_PRCM_DPLL_POST_DIV_H14 = 9U,
PMHAL_PRCM_DPLL_POST_DIV_H21 = 10U,
PMHAL_PRCM_DPLL_POST_DIV_H22 = 11U,
PMHAL_PRCM_DPLL_POST_DIV_H23 = 12U,
PMHAL_PRCM_DPLL_POST_DIV_H24 = 13U,
PMHAL_PRCM_DPLL_POST_DIV_VCO_LDO_DIV = 14U,
PMHAL_PRCM_DPLL_POST_DIV_VCO_LDO = 15U,
PMHAL_PRCM_DPLL_POST_DIV_DCO_LDO = 16U,
PMHAL_PRCM_DPLL_POST_DIV_M7 = 17U,
PMHAL_PRCM_DPLL_POST_DIV_MAX = PMHAL_PRCM_DPLL_POST_DIV_M7,
PMHAL_PRCM_DPLL_POST_DIV_COUNT = PMHAL_PRCM_DPLL_POST_DIV_MAX + 1U,
PMHAL_PRCM_DPLL_POST_DIV_INVALID = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_POST_DIV_MIN = 0U,
PMHAL_PRCM_DPLL_POST_DIV_M2 = PMHAL_PRCM_DPLL_POST_DIV_MIN,
PMHAL_PRCM_DPLL_POST_DIV_M2X2 = 1U,
PMHAL_PRCM_DPLL_POST_DIV_M4 = 2U,
PMHAL_PRCM_DPLL_POST_DIV_M3 = 3U,
PMHAL_PRCM_DPLL_POST_DIV_M5 = 4U,
PMHAL_PRCM_DPLL_POST_DIV_M6 = 5U,
PMHAL_PRCM_DPLL_POST_DIV_H11 = 6U,
PMHAL_PRCM_DPLL_POST_DIV_H12 = 7U,
PMHAL_PRCM_DPLL_POST_DIV_H13 = 8U,
PMHAL_PRCM_DPLL_POST_DIV_H14 = 9U,
PMHAL_PRCM_DPLL_POST_DIV_H21 = 10U,
PMHAL_PRCM_DPLL_POST_DIV_H22 = 11U,
PMHAL_PRCM_DPLL_POST_DIV_H23 = 12U,
PMHAL_PRCM_DPLL_POST_DIV_H24 = 13U,
PMHAL_PRCM_DPLL_POST_DIV_VCO_LDO_DIV = 14U,
PMHAL_PRCM_DPLL_POST_DIV_VCO_LDO = 15U,
PMHAL_PRCM_DPLL_POST_DIV_DCO_LDO = 16U,
PMHAL_PRCM_DPLL_POST_DIV_M7 = 17U,
PMHAL_PRCM_DPLL_POST_DIV_MAX = PMHAL_PRCM_DPLL_POST_DIV_M7,
PMHAL_PRCM_DPLL_POST_DIV_COUNT = PMHAL_PRCM_DPLL_POST_DIV_MAX + 1U,
PMHAL_PRCM_DPLL_POST_DIV_INVALID = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_POST_DIV_MIN = 0U,
PMHAL_PRCM_DPLL_POST_DIV_M2 = PMHAL_PRCM_DPLL_POST_DIV_MIN,
PMHAL_PRCM_DPLL_POST_DIV_M2X2 = 1U,
PMHAL_PRCM_DPLL_POST_DIV_M4 = 2U,
PMHAL_PRCM_DPLL_POST_DIV_M3 = 3U,
PMHAL_PRCM_DPLL_POST_DIV_M5 = 4U,
PMHAL_PRCM_DPLL_POST_DIV_M6 = 5U,
PMHAL_PRCM_DPLL_POST_DIV_H11 = 6U,
PMHAL_PRCM_DPLL_POST_DIV_H12 = 7U,
PMHAL_PRCM_DPLL_POST_DIV_H13 = 8U,
PMHAL_PRCM_DPLL_POST_DIV_H14 = 9U,
PMHAL_PRCM_DPLL_POST_DIV_H21 = 10U,
PMHAL_PRCM_DPLL_POST_DIV_H22 = 11U,
PMHAL_PRCM_DPLL_POST_DIV_H23 = 12U,
PMHAL_PRCM_DPLL_POST_DIV_H24 = 13U,
PMHAL_PRCM_DPLL_POST_DIV_VCO_LDO_DIV = 14U,
PMHAL_PRCM_DPLL_POST_DIV_VCO_LDO = 15U,
PMHAL_PRCM_DPLL_POST_DIV_DCO_LDO = 16U,
PMHAL_PRCM_DPLL_POST_DIV_M7 = 17U,
PMHAL_PRCM_DPLL_POST_DIV_MAX = PMHAL_PRCM_DPLL_POST_DIV_M7,
PMHAL_PRCM_DPLL_POST_DIV_COUNT = PMHAL_PRCM_DPLL_POST_DIV_MAX + 1U,
PMHAL_PRCM_DPLL_POST_DIV_INVALID = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_POST_DIV_MIN = 0U,
PMHAL_PRCM_DPLL_POST_DIV_M2 = PMHAL_PRCM_DPLL_POST_DIV_MIN,
PMHAL_PRCM_DPLL_POST_DIV_M2X2 = 1U,
PMHAL_PRCM_DPLL_POST_DIV_M4 = 2U,
PMHAL_PRCM_DPLL_POST_DIV_M3 = 3U,
PMHAL_PRCM_DPLL_POST_DIV_M5 = 4U,
PMHAL_PRCM_DPLL_POST_DIV_M6 = 5U,
PMHAL_PRCM_DPLL_POST_DIV_DCO_LDO = 6U,
PMHAL_PRCM_DPLL_POST_DIV_MAX = PMHAL_PRCM_DPLL_POST_DIV_DCO_LDO,
PMHAL_PRCM_DPLL_POST_DIV_COUNT = PMHAL_PRCM_DPLL_POST_DIV_MAX + 1U,
PMHAL_PRCM_DPLL_POST_DIV_INVALID = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_POST_DIV_MIN = 0U,
PMHAL_PRCM_DPLL_POST_DIV_M2 = PMHAL_PRCM_DPLL_POST_DIV_MIN,
PMHAL_PRCM_DPLL_POST_DIV_M2X2 = 1U,
PMHAL_PRCM_DPLL_POST_DIV_M4 = 2U,
PMHAL_PRCM_DPLL_POST_DIV_M3 = 3U,
PMHAL_PRCM_DPLL_POST_DIV_M5 = 4U,
PMHAL_PRCM_DPLL_POST_DIV_M6 = 5U,
PMHAL_PRCM_DPLL_POST_DIV_DCO_LDO = 6U,
PMHAL_PRCM_DPLL_POST_DIV_MAX = PMHAL_PRCM_DPLL_POST_DIV_DCO_LDO,
PMHAL_PRCM_DPLL_POST_DIV_COUNT = PMHAL_PRCM_DPLL_POST_DIV_MAX + 1U
} |
| | Enumeration for different different post dividers. More...
|
| |
| enum | pmhalPrcmDpllClkInputLowSel {
PMHAL_PRCM_DPLL_CLKINPULOW_MIN = 0U,
PMHAL_PRCM_DPLL_CLKINPULOW_CORE_CLKOUTM6 = PMHAL_PRCM_DPLL_CLKINPULOW_MIN,
PMHAL_PRCM_DPLL_CLKINPULOW_PER_CLKOUTM2 = 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_MAX = 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_COUNT = PMHAL_PRCM_DPLL_CLKINPULOW_MAX + 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_MIN = 0U,
PMHAL_PRCM_DPLL_CLKINPULOW_CORE_CLKOUTM6 = PMHAL_PRCM_DPLL_CLKINPULOW_MIN,
PMHAL_PRCM_DPLL_CLKINPULOW_PER_CLKOUTM2 = 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_MAX = 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_COUNT = PMHAL_PRCM_DPLL_CLKINPULOW_MAX + 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_MIN = 0U,
PMHAL_PRCM_DPLL_CLKINPULOW_CORE_CLKOUTM6 = PMHAL_PRCM_DPLL_CLKINPULOW_MIN,
PMHAL_PRCM_DPLL_CLKINPULOW_PER_CLKOUTM2 = 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_MAX = 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_COUNT = PMHAL_PRCM_DPLL_CLKINPULOW_MAX + 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_MIN = 0U,
PMHAL_PRCM_DPLL_CLKINPULOW_CORE_CLKOUTM6 = PMHAL_PRCM_DPLL_CLKINPULOW_MIN,
PMHAL_PRCM_DPLL_CLKINPULOW_PER_CLKOUTM2 = 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_MAX = 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_COUNT = PMHAL_PRCM_DPLL_CLKINPULOW_MAX + 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_MIN = 0U,
PMHAL_PRCM_DPLL_CLKINPULOW_CORE_CLKOUTM6 = PMHAL_PRCM_DPLL_CLKINPULOW_MIN,
PMHAL_PRCM_DPLL_CLKINPULOW_PER_CLKOUTM2 = 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_MAX = 1U,
PMHAL_PRCM_DPLL_CLKINPULOW_COUNT = PMHAL_PRCM_DPLL_CLKINPULOW_MAX + 1U
} |
| | Enum defining CLKINPULOW input selection. These parameters define the clock input to CLKINPULOW signal in bypass mode. More...
|
| |
| enum | pmhalPrcmDpllBypassClkSel {
PMHAL_PRCM_DPLL_BYP_MIN = 0U,
PMHAL_PRCM_DPLL_BYP_CLKINP = PMHAL_PRCM_DPLL_BYP_MIN,
PMHAL_PRCM_DPLL_BYP_CLKINPULOW = 1U,
PMHAL_PRCM_DPLL_BYP_MAX = PMHAL_PRCM_DPLL_BYP_CLKINPULOW,
PMHAL_PRCM_DPLL_BYP_COUNT = PMHAL_PRCM_DPLL_BYP_MAX + 1U,
PMHAL_PRCM_DPLL_BYP_MIN = 0U,
PMHAL_PRCM_DPLL_BYP_CLKINP = PMHAL_PRCM_DPLL_BYP_MIN,
PMHAL_PRCM_DPLL_BYP_CLKINPULOW = 1U,
PMHAL_PRCM_DPLL_BYP_CLKINPHIF = 2U,
PMHAL_PRCM_DPLL_BYP_MAX = PMHAL_PRCM_DPLL_BYP_CLKINPHIF,
PMHAL_PRCM_DPLL_BYP_COUNT = PMHAL_PRCM_DPLL_BYP_MAX + 1U,
PMHAL_PRCM_DPLL_BYP_MIN = 0U,
PMHAL_PRCM_DPLL_BYP_CLKINP = PMHAL_PRCM_DPLL_BYP_MIN,
PMHAL_PRCM_DPLL_BYP_CLKINPULOW = 1U,
PMHAL_PRCM_DPLL_BYP_MAX = PMHAL_PRCM_DPLL_BYP_CLKINPULOW,
PMHAL_PRCM_DPLL_BYP_COUNT = PMHAL_PRCM_DPLL_BYP_MAX + 1U,
PMHAL_PRCM_DPLL_BYP_MIN = 0U,
PMHAL_PRCM_DPLL_BYP_CLKINP = PMHAL_PRCM_DPLL_BYP_MIN,
PMHAL_PRCM_DPLL_BYP_CLKINPULOW = 1U,
PMHAL_PRCM_DPLL_BYP_MAX = PMHAL_PRCM_DPLL_BYP_CLKINPULOW,
PMHAL_PRCM_DPLL_BYP_COUNT = PMHAL_PRCM_DPLL_BYP_MAX + 1U,
PMHAL_PRCM_DPLL_BYP_MIN = 0U,
PMHAL_PRCM_DPLL_BYP_CLKINP = PMHAL_PRCM_DPLL_BYP_MIN,
PMHAL_PRCM_DPLL_BYP_CLKINPULOW = 1U,
PMHAL_PRCM_DPLL_BYP_MAX = PMHAL_PRCM_DPLL_BYP_CLKINPULOW,
PMHAL_PRCM_DPLL_BYP_COUNT = PMHAL_PRCM_DPLL_BYP_MAX + 1U
} |
| | Enum defining bypass input clock selection for the PLL. The bypass clock can either be CLKINP (Master Osc) or CLKINPULOW (above enum value). More...
|
| |
| enum | pmhalPrcmDpllClkInput {
PMHAL_PRCM_DPLL_INP_MIN = 0U,
PMHAL_PRCM_DPLL_INP_CLKINP = PMHAL_PRCM_DPLL_INP_MIN,
PMHAL_PRCM_DPLL_INP_CLKINPULOW = 1U,
PMHAL_PRCM_DPLL_INP_CLKINPHIF = 2U,
PMHAL_PRCM_DPLL_INP_DCO = 3U,
PMHAL_PRCM_DPLL_INP_MAX = PMHAL_PRCM_DPLL_INP_DCO,
PMHAL_PRCM_DPLL_INP_COUNT = PMHAL_PRCM_DPLL_INP_MAX + 1U,
PMHAL_PRCM_DPLL_INP_MIN = 0U,
PMHAL_PRCM_DPLL_INP_CLKINP = PMHAL_PRCM_DPLL_INP_MIN,
PMHAL_PRCM_DPLL_INP_CLKINPULOW = 1U,
PMHAL_PRCM_DPLL_INP_CLKINPHIF = 2U,
PMHAL_PRCM_DPLL_INP_DCO = 3U,
PMHAL_PRCM_DPLL_INP_MAX = PMHAL_PRCM_DPLL_INP_DCO,
PMHAL_PRCM_DPLL_INP_COUNT = PMHAL_PRCM_DPLL_INP_MAX + 1U,
PMHAL_PRCM_DPLL_INP_MIN = 0U,
PMHAL_PRCM_DPLL_INP_CLKINP = PMHAL_PRCM_DPLL_INP_MIN,
PMHAL_PRCM_DPLL_INP_CLKINPULOW = 1U,
PMHAL_PRCM_DPLL_INP_CLKINPHIF = 2U,
PMHAL_PRCM_DPLL_INP_DCO = 3U,
PMHAL_PRCM_DPLL_INP_MAX = PMHAL_PRCM_DPLL_INP_DCO,
PMHAL_PRCM_DPLL_INP_COUNT = PMHAL_PRCM_DPLL_INP_MAX + 1U,
PMHAL_PRCM_DPLL_INP_MIN = 0U,
PMHAL_PRCM_DPLL_INP_CLKINP = PMHAL_PRCM_DPLL_INP_MIN,
PMHAL_PRCM_DPLL_INP_CLKINPULOW = 1U,
PMHAL_PRCM_DPLL_INP_CLKINPHIF = 2U,
PMHAL_PRCM_DPLL_INP_MAX = PMHAL_PRCM_DPLL_INP_CLKINPHIF,
PMHAL_PRCM_DPLL_INP_COUNT = PMHAL_PRCM_DPLL_INP_MAX + 1U,
PMHAL_PRCM_DPLL_INP_MIN = 0U,
PMHAL_PRCM_DPLL_INP_CLKINP = PMHAL_PRCM_DPLL_INP_MIN,
PMHAL_PRCM_DPLL_INP_CLKINPULOW = 1U,
PMHAL_PRCM_DPLL_INP_CLKINPHIF = 2U,
PMHAL_PRCM_DPLL_INP_MAX = PMHAL_PRCM_DPLL_INP_CLKINPHIF,
PMHAL_PRCM_DPLL_INP_COUNT = PMHAL_PRCM_DPLL_INP_MAX + 1U
} |
| | Enum defining input clocks for the PLL. More...
|
| |
| enum | pmhalPrcmDpllPowerMode {
PMHAL_PRCM_DPLL_POWER_MODE_MIN = 0U,
PMHAL_PRCM_DPLL_POWER_MODE_MN_BYP_MODE = PMHAL_PRCM_DPLL_POWER_MODE_MIN,
PMHAL_PRCM_DPLL_POWER_MODE_LP_STP_MODE = 1U,
PMHAL_PRCM_DPLL_POWER_MODE_FR_STP_MODE = 2U,
PMHAL_PRCM_DPLL_POWER_MODE_LP_BYP_MODE = 5U,
PMHAL_PRCM_DPLL_POWER_MODE_FR_BYP_MODE = 6U,
PMHAL_PRCM_DPLL_POWER_MODE_LOCK_MODE = 7U,
PMHAL_PRCM_DPLL_POWER_MODE_MAX = PMHAL_PRCM_DPLL_POWER_MODE_LOCK_MODE,
PMHAL_PRCM_DPLL_POWER_MODE_COUNT = PMHAL_PRCM_DPLL_POWER_MODE_MAX + 1U,
PMHAL_PRCM_DPLL_POWER_MODE_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_POWER_MODE_MIN = 0U,
PMHAL_PRCM_DPLL_POWER_MODE_MN_BYP_MODE = PMHAL_PRCM_DPLL_POWER_MODE_MIN,
PMHAL_PRCM_DPLL_POWER_MODE_LP_STP_MODE = 1U,
PMHAL_PRCM_DPLL_POWER_MODE_FR_STP_MODE = 2U,
PMHAL_PRCM_DPLL_POWER_MODE_LP_BYP_MODE = 5U,
PMHAL_PRCM_DPLL_POWER_MODE_FR_BYP_MODE = 6U,
PMHAL_PRCM_DPLL_POWER_MODE_LOCK_MODE = 7U,
PMHAL_PRCM_DPLL_POWER_MODE_MAX = PMHAL_PRCM_DPLL_POWER_MODE_LOCK_MODE,
PMHAL_PRCM_DPLL_POWER_MODE_COUNT = PMHAL_PRCM_DPLL_POWER_MODE_MAX + 1U,
PMHAL_PRCM_DPLL_POWER_MODE_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_POWER_MODE_MIN = 0U,
PMHAL_PRCM_DPLL_POWER_MODE_MN_BYP_MODE = PMHAL_PRCM_DPLL_POWER_MODE_MIN,
PMHAL_PRCM_DPLL_POWER_MODE_LP_STP_MODE = 1U,
PMHAL_PRCM_DPLL_POWER_MODE_FR_STP_MODE = 2U,
PMHAL_PRCM_DPLL_POWER_MODE_LP_BYP_MODE = 5U,
PMHAL_PRCM_DPLL_POWER_MODE_FR_BYP_MODE = 6U,
PMHAL_PRCM_DPLL_POWER_MODE_LOCK_MODE = 7U,
PMHAL_PRCM_DPLL_POWER_MODE_MAX = PMHAL_PRCM_DPLL_POWER_MODE_LOCK_MODE,
PMHAL_PRCM_DPLL_POWER_MODE_COUNT = PMHAL_PRCM_DPLL_POWER_MODE_MAX + 1U,
PMHAL_PRCM_DPLL_POWER_MODE_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_POWER_MODE_MIN = 1U,
PMHAL_PRCM_DPLL_POWER_MODE_LP_STP_MODE = PMHAL_PRCM_DPLL_POWER_MODE_MIN,
PMHAL_PRCM_DPLL_POWER_MODE_MN_BYP_MODE = 4U,
PMHAL_PRCM_DPLL_POWER_MODE_LP_BYP_MODE = 5U,
PMHAL_PRCM_DPLL_POWER_MODE_FR_BYP_MODE = 6U,
PMHAL_PRCM_DPLL_POWER_MODE_LOCK_MODE = 7U,
PMHAL_PRCM_DPLL_POWER_MODE_MAX = PMHAL_PRCM_DPLL_POWER_MODE_LOCK_MODE,
PMHAL_PRCM_DPLL_POWER_MODE_COUNT = PMHAL_PRCM_DPLL_POWER_MODE_MAX + 1U,
PMHAL_PRCM_DPLL_POWER_MODE_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_POWER_MODE_MIN = 4U,
PMHAL_PRCM_DPLL_POWER_MODE_MN_BYP_MODE = PMHAL_PRCM_DPLL_POWER_MODE_MIN,
PMHAL_PRCM_DPLL_POWER_MODE_LP_BYP_MODE = 5U,
PMHAL_PRCM_DPLL_POWER_MODE_FR_BYP_MODE = 6U,
PMHAL_PRCM_DPLL_POWER_MODE_LOCK_MODE = 7U,
PMHAL_PRCM_DPLL_POWER_MODE_MAX = PMHAL_PRCM_DPLL_POWER_MODE_LOCK_MODE,
PMHAL_PRCM_DPLL_POWER_MODE_COUNT = PMHAL_PRCM_DPLL_POWER_MODE_MAX + 1U,
PMHAL_PRCM_DPLL_POWER_MODE_UNDEF = 0x7FFFFFFFU
} |
| | Enum defining different power modes for the PLL. More...
|
| |
| enum | pmhalPrcmDpllRampLevel {
PMHAL_PRCM_DPLL_RAMP_LEVEL_MIN = 0U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_DISABLE = PMHAL_PRCM_DPLL_RAMP_LEVEL_MIN,
PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO1 = 1U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO2 = 2U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_MAX = PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO2,
PMHAL_PRCM_DPLL_RAMP_LEVEL_COUNT = PMHAL_PRCM_DPLL_RAMP_LEVEL_MAX + 1U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_MIN = 0U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_DISABLE = PMHAL_PRCM_DPLL_RAMP_LEVEL_MIN,
PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO1 = 1U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO2 = 2U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_MAX = PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO2,
PMHAL_PRCM_DPLL_RAMP_LEVEL_COUNT = PMHAL_PRCM_DPLL_RAMP_LEVEL_MAX + 1U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_MIN = 0U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_DISABLE = PMHAL_PRCM_DPLL_RAMP_LEVEL_MIN,
PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO1 = 1U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO2 = 2U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_MAX = PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO2,
PMHAL_PRCM_DPLL_RAMP_LEVEL_COUNT = PMHAL_PRCM_DPLL_RAMP_LEVEL_MAX + 1U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_MIN = 0U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_DISABLE = PMHAL_PRCM_DPLL_RAMP_LEVEL_MIN,
PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO1 = 1U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO2 = 2U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_MAX = PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO2,
PMHAL_PRCM_DPLL_RAMP_LEVEL_COUNT = PMHAL_PRCM_DPLL_RAMP_LEVEL_MAX + 1U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_MIN = 0U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_DISABLE = PMHAL_PRCM_DPLL_RAMP_LEVEL_MIN,
PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO1 = 1U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO2 = 2U,
PMHAL_PRCM_DPLL_RAMP_LEVEL_MAX = PMHAL_PRCM_DPLL_RAMP_LEVEL_ALGO2,
PMHAL_PRCM_DPLL_RAMP_LEVEL_COUNT = PMHAL_PRCM_DPLL_RAMP_LEVEL_MAX + 1U
} |
| | Enum defining different ramp levels for the PLL. More...
|
| |
| enum | pmhalPrcmDpllRampRate {
PMHAL_PRCM_DPLL_RAMP_RATE_MIN = 0U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX2 = PMHAL_PRCM_DPLL_RAMP_RATE_MIN,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX4 = 1U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX8 = 2U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX16 = 3U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX32 = 4U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX64 = 5U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX128 = 6U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX512 = 7U,
PMHAL_PRCM_DPLL_RAMP_RATE_MAX = PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX512,
PMHAL_PRCM_DPLL_RAMP_RATE_COUNT = PMHAL_PRCM_DPLL_RAMP_RATE_MAX + 1U,
PMHAL_PRCM_DPLL_RAMP_RATE_MIN = 0U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX2 = PMHAL_PRCM_DPLL_RAMP_RATE_MIN,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX4 = 1U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX8 = 2U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX16 = 3U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX32 = 4U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX64 = 5U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX128 = 6U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX512 = 7U,
PMHAL_PRCM_DPLL_RAMP_RATE_MAX = PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX512,
PMHAL_PRCM_DPLL_RAMP_RATE_COUNT = PMHAL_PRCM_DPLL_RAMP_RATE_MAX + 1U,
PMHAL_PRCM_DPLL_RAMP_RATE_MIN = 0U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX2 = PMHAL_PRCM_DPLL_RAMP_RATE_MIN,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX4 = 1U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX8 = 2U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX16 = 3U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX32 = 4U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX64 = 5U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX128 = 6U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX512 = 7U,
PMHAL_PRCM_DPLL_RAMP_RATE_MAX = PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX512,
PMHAL_PRCM_DPLL_RAMP_RATE_COUNT = PMHAL_PRCM_DPLL_RAMP_RATE_MAX + 1U,
PMHAL_PRCM_DPLL_RAMP_RATE_MIN = 0U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX2 = PMHAL_PRCM_DPLL_RAMP_RATE_MIN,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX4 = 1U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX8 = 2U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX16 = 3U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX32 = 4U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX64 = 5U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX128 = 6U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX512 = 7U,
PMHAL_PRCM_DPLL_RAMP_RATE_MAX = PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX512,
PMHAL_PRCM_DPLL_RAMP_RATE_COUNT = PMHAL_PRCM_DPLL_RAMP_RATE_MAX + 1U,
PMHAL_PRCM_DPLL_RAMP_RATE_MIN = 0U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX2 = PMHAL_PRCM_DPLL_RAMP_RATE_MIN,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX4 = 1U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX8 = 2U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX16 = 3U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX32 = 4U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX64 = 5U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX128 = 6U,
PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX512 = 7U,
PMHAL_PRCM_DPLL_RAMP_RATE_MAX = PMHAL_PRCM_DPLL_RAMP_RATE_REFCLKX512,
PMHAL_PRCM_DPLL_RAMP_RATE_COUNT = PMHAL_PRCM_DPLL_RAMP_RATE_MAX + 1U
} |
| | Enum defining different ramp rates for the PLL. These rates . indicates the time spent in each ramp step. More...
|
| |
| enum | pmhalPrcmDpllLockStatus {
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MIN = 0U,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_UNLOCKED = PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MIN,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_LOCKED = 1U,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MAX = PMHAL_PRCM_DPLL_IDLEST_ST_CLK_LOCKED,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_COUNT,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MIN = 0U,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_UNLOCKED = PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MIN,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_LOCKED = 1U,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MAX = PMHAL_PRCM_DPLL_IDLEST_ST_CLK_LOCKED,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_COUNT,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MIN = 0U,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_UNLOCKED = PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MIN,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_LOCKED = 1U,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MAX = PMHAL_PRCM_DPLL_IDLEST_ST_CLK_LOCKED,
PMHAL_PRCM_DPLL_IDLEST_ST_CLK_COUNT
} |
| | Enum defining lock statuses of DPLL. More...
|
| |
| enum | pmhalPrcmRootClkType {
PMHAL_PRCM_ROOT_CLK_FREQ_MIN = 0U,
PMHAL_PRCM_ROOT_CLK_FREQ_FIXED = PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MIN,
PMHAL_PRCM_ROOT_CLK_FREQ_STATIC_CONFIG = 1U,
PMHAL_PRCM_ROOT_CLK_FREQ_MAX = PMHAL_PRCM_ROOT_CLK_FREQ_STATIC_CONFIG,
PMHAL_PRCM_ROOT_CLK_FREQ_COUNT = PMHAL_PRCM_ROOT_CLK_FREQ_MAX + 1U,
PMHAL_PRCM_ROOT_CLK_FREQ_MIN = 0U,
PMHAL_PRCM_ROOT_CLK_FREQ_FIXED = PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MIN,
PMHAL_PRCM_ROOT_CLK_FREQ_STATIC_CONFIG = 1U,
PMHAL_PRCM_ROOT_CLK_FREQ_MAX = PMHAL_PRCM_ROOT_CLK_FREQ_STATIC_CONFIG,
PMHAL_PRCM_ROOT_CLK_FREQ_COUNT = PMHAL_PRCM_ROOT_CLK_FREQ_MAX + 1U,
PMHAL_PRCM_ROOT_CLK_FREQ_MIN = 0U,
PMHAL_PRCM_ROOT_CLK_FREQ_FIXED = PMHAL_PRCM_DPLL_IDLEST_ST_CLK_MIN,
PMHAL_PRCM_ROOT_CLK_FREQ_STATIC_CONFIG = 1U,
PMHAL_PRCM_ROOT_CLK_FREQ_MAX = PMHAL_PRCM_ROOT_CLK_FREQ_STATIC_CONFIG,
PMHAL_PRCM_ROOT_CLK_FREQ_COUNT = PMHAL_PRCM_ROOT_CLK_FREQ_MAX + 1U,
PMHAL_PRCM_ROOT_CLK_FREQ_MIN = 0U,
PMHAL_PRCM_ROOT_CLK_FREQ_FIXED = PMHAL_PRCM_ROOT_CLK_FREQ_MIN,
PMHAL_PRCM_ROOT_CLK_FREQ_STATIC_CONFIG = 1U,
PMHAL_PRCM_ROOT_CLK_FREQ_MAX = PMHAL_PRCM_ROOT_CLK_FREQ_STATIC_CONFIG,
PMHAL_PRCM_ROOT_CLK_FREQ_COUNT = PMHAL_PRCM_ROOT_CLK_FREQ_MAX + 1U,
PMHAL_PRCM_ROOT_CLK_FREQ_MIN = 0U,
PMHAL_PRCM_ROOT_CLK_FREQ_FIXED = PMHAL_PRCM_ROOT_CLK_FREQ_MIN,
PMHAL_PRCM_ROOT_CLK_FREQ_STATIC_CONFIG = 1U,
PMHAL_PRCM_ROOT_CLK_FREQ_MAX = PMHAL_PRCM_ROOT_CLK_FREQ_STATIC_CONFIG,
PMHAL_PRCM_ROOT_CLK_FREQ_COUNT = PMHAL_PRCM_ROOT_CLK_FREQ_MAX + 1U
} |
| | Enum defining different types of root clock. More...
|
| |
| enum | pmhalPrcmPdLogicRetState {
PMHAL_PRCM_PD_RET_STATUS_MIN = 0U,
PMHAL_PRCM_PD_RET_STATUS_OSWR = PMHAL_PRCM_PD_RET_STATUS_MIN,
PMHAL_PRCM_PD_RET_STATUS_CSWR = 1U,
PMHAL_PRCM_PD_RET_STATUS_MAX = PMHAL_PRCM_PD_RET_STATUS_CSWR,
PMHAL_PRCM_PD_RET_STATUS_COUNT = PMHAL_PRCM_PD_RET_STATUS_MAX + 1U,
PMHAL_PRCM_PD_RET_STATUS_MIN = 0U,
PMHAL_PRCM_PD_RET_STATUS_OSWR = PMHAL_PRCM_PD_RET_STATUS_MIN,
PMHAL_PRCM_PD_RET_STATUS_CSWR = 1U,
PMHAL_PRCM_PD_RET_STATUS_MAX = PMHAL_PRCM_PD_RET_STATUS_CSWR,
PMHAL_PRCM_PD_RET_STATUS_COUNT = PMHAL_PRCM_PD_RET_STATUS_MAX + 1U,
PMHAL_PRCM_PD_RET_STATUS_MIN = 0U,
PMHAL_PRCM_PD_RET_STATUS_OSWR = PMHAL_PRCM_PD_RET_STATUS_MIN,
PMHAL_PRCM_PD_RET_STATUS_CSWR = 1U,
PMHAL_PRCM_PD_RET_STATUS_MAX = PMHAL_PRCM_PD_RET_STATUS_CSWR,
PMHAL_PRCM_PD_RET_STATUS_COUNT = PMHAL_PRCM_PD_RET_STATUS_MAX + 1U,
PMHAL_PRCM_PD_RET_STATUS_MIN = 0U,
PMHAL_PRCM_PD_RET_STATUS_OSWR = PMHAL_PRCM_PD_RET_STATUS_MIN,
PMHAL_PRCM_PD_RET_STATUS_CSWR = 1U,
PMHAL_PRCM_PD_RET_STATUS_MAX = PMHAL_PRCM_PD_RET_STATUS_CSWR,
PMHAL_PRCM_PD_RET_STATUS_COUNT = PMHAL_PRCM_PD_RET_STATUS_MAX + 1U,
PMHAL_PRCM_PD_RET_STATUS_MIN = 0U,
PMHAL_PRCM_PD_RET_STATUS_OSWR = PMHAL_PRCM_PD_RET_STATUS_MIN,
PMHAL_PRCM_PD_RET_STATUS_CSWR = 1U,
PMHAL_PRCM_PD_RET_STATUS_MAX = PMHAL_PRCM_PD_RET_STATUS_CSWR,
PMHAL_PRCM_PD_RET_STATUS_COUNT = PMHAL_PRCM_PD_RET_STATUS_MAX + 1U
} |
| | Enum defining Logic Retention Power States of Logic Area. More...
|
| |
| enum | pmhalPrcmPdLowPwrStateChangeType {
PMHAL_PRCM_PD_LOW_PWR_REQUEST_MIN = 0U,
PMHAL_PRCM_PD_LOW_PWR_NO_REQUEST = PMHAL_PRCM_PD_LOW_PWR_REQUEST_MIN,
PMHAL_PRCM_PD_LOW_PWR_REQUEST = 1U,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_MAX = PMHAL_PRCM_PD_LOW_PWR_REQUEST,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_COUNT,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_MIN = 0U,
PMHAL_PRCM_PD_LOW_PWR_NO_REQUEST = PMHAL_PRCM_PD_LOW_PWR_REQUEST_MIN,
PMHAL_PRCM_PD_LOW_PWR_REQUEST = 1U,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_MAX = PMHAL_PRCM_PD_LOW_PWR_REQUEST,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_COUNT,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_MIN = 0U,
PMHAL_PRCM_PD_LOW_PWR_NO_REQUEST = PMHAL_PRCM_PD_LOW_PWR_REQUEST_MIN,
PMHAL_PRCM_PD_LOW_PWR_REQUEST = 1U,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_MAX = PMHAL_PRCM_PD_LOW_PWR_REQUEST,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_COUNT,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_MIN = 0U,
PMHAL_PRCM_PD_LOW_PWR_NO_REQUEST = PMHAL_PRCM_PD_LOW_PWR_REQUEST_MIN,
PMHAL_PRCM_PD_LOW_PWR_REQUEST = 1U,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_MAX = PMHAL_PRCM_PD_LOW_PWR_REQUEST,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_COUNT,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_MIN = 0U,
PMHAL_PRCM_PD_LOW_PWR_NO_REQUEST = PMHAL_PRCM_PD_LOW_PWR_REQUEST_MIN,
PMHAL_PRCM_PD_LOW_PWR_REQUEST = 1U,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_MAX = PMHAL_PRCM_PD_LOW_PWR_REQUEST,
PMHAL_PRCM_PD_LOW_PWR_REQUEST_COUNT
} |
| | Enum defining Low Power Request type of the power domain. More...
|
| |
| enum | pmhalPhyBankRetStates {
PMHAL_BANK_RET_OFF = 0U,
PMHAL_BANK_RET_MIN = PMHAL_BANK_RET_OFF,
PMHAL_BANK_RET_ON = 1U,
PMHAL_BANK_RET_MAX = PMHAL_BANK_RET_ON,
PMHAL_BANK_RET_COUNT = PMHAL_BANK_RET_MAX + 1U,
PMHAL_BANK_RET_UNDEF = 0xFF,
PMHAL_BANK_RET_OFF = 0U,
PMHAL_BANK_RET_MIN = PMHAL_BANK_RET_OFF,
PMHAL_BANK_RET_ON = 1U,
PMHAL_BANK_RET_MAX = PMHAL_BANK_RET_ON,
PMHAL_BANK_RET_COUNT = PMHAL_BANK_RET_MAX + 1U,
PMHAL_BANK_RET_UNDEF = 0xFF,
PMHAL_BANK_RET_OFF = 0U,
PMHAL_BANK_RET_MIN = PMHAL_BANK_RET_OFF,
PMHAL_BANK_RET_ON = 1U,
PMHAL_BANK_RET_MAX = PMHAL_BANK_RET_ON,
PMHAL_BANK_RET_COUNT = PMHAL_BANK_RET_MAX + 1U,
PMHAL_BANK_RET_UNDEF = 0xFF,
PMHAL_BANK_RET_OFF = 0U,
PMHAL_BANK_RET_MIN = PMHAL_BANK_RET_OFF,
PMHAL_BANK_RET_ON = 1U,
PMHAL_BANK_RET_MAX = PMHAL_BANK_RET_ON,
PMHAL_BANK_RET_COUNT = PMHAL_BANK_RET_MAX + 1U,
PMHAL_BANK_RET_UNDEF = 0xFF,
PMHAL_BANK_RET_OFF = 0U,
PMHAL_BANK_RET_MIN = PMHAL_BANK_RET_OFF,
PMHAL_BANK_RET_ON = 1U,
PMHAL_BANK_RET_MAX = PMHAL_BANK_RET_ON,
PMHAL_BANK_RET_COUNT = PMHAL_BANK_RET_MAX + 1U,
PMHAL_BANK_RET_UNDEF = 0xFF
} |
| | Physical memory data retention states. More...
|
| |
| enum | pmhalPrcmPdTransitionState {
PMHAL_PRCM_PD_TRANSIT_STATUS_MIN = 0U,
PMHAL_PRCM_PD_TRANSIT_STATUS_NOTRANS = PMHAL_PRCM_PD_TRANSIT_STATUS_MIN,
PMHAL_PRCM_PD_TRANSIT_STATUS_INTRANS = 1U,
PMHAL_PRCM_PD_TRANSIT_STATUS_MAX = PMHAL_PRCM_PD_TRANSIT_STATUS_INTRANS,
PMHAL_PRCM_PD_TRANSIT_STATUS_COUNT = PMHAL_PRCM_PD_TRANSIT_STATUS_MAX + 1U,
PMHAL_PRCM_PD_TRANSIT_STATUS_MIN = 0U,
PMHAL_PRCM_PD_TRANSIT_STATUS_NOTRANS = PMHAL_PRCM_PD_TRANSIT_STATUS_MIN,
PMHAL_PRCM_PD_TRANSIT_STATUS_INTRANS = 1U,
PMHAL_PRCM_PD_TRANSIT_STATUS_MAX = PMHAL_PRCM_PD_TRANSIT_STATUS_INTRANS,
PMHAL_PRCM_PD_TRANSIT_STATUS_COUNT = PMHAL_PRCM_PD_TRANSIT_STATUS_MAX + 1U,
PMHAL_PRCM_PD_TRANSIT_STATUS_MIN = 0U,
PMHAL_PRCM_PD_TRANSIT_STATUS_NOTRANS = PMHAL_PRCM_PD_TRANSIT_STATUS_MIN,
PMHAL_PRCM_PD_TRANSIT_STATUS_INTRANS = 1U,
PMHAL_PRCM_PD_TRANSIT_STATUS_MAX = PMHAL_PRCM_PD_TRANSIT_STATUS_INTRANS,
PMHAL_PRCM_PD_TRANSIT_STATUS_COUNT = PMHAL_PRCM_PD_TRANSIT_STATUS_MAX + 1U,
PMHAL_PRCM_PD_TRANSIT_STATUS_MIN = 0U,
PMHAL_PRCM_PD_TRANSIT_STATUS_NOTRANS = PMHAL_PRCM_PD_TRANSIT_STATUS_MIN,
PMHAL_PRCM_PD_TRANSIT_STATUS_INTRANS = 1U,
PMHAL_PRCM_PD_TRANSIT_STATUS_MAX = PMHAL_PRCM_PD_TRANSIT_STATUS_INTRANS,
PMHAL_PRCM_PD_TRANSIT_STATUS_COUNT = PMHAL_PRCM_PD_TRANSIT_STATUS_MAX + 1U,
PMHAL_PRCM_PD_TRANSIT_STATUS_MIN = 0U,
PMHAL_PRCM_PD_TRANSIT_STATUS_NOTRANS = PMHAL_PRCM_PD_TRANSIT_STATUS_MIN,
PMHAL_PRCM_PD_TRANSIT_STATUS_INTRANS = 1U,
PMHAL_PRCM_PD_TRANSIT_STATUS_MAX = PMHAL_PRCM_PD_TRANSIT_STATUS_INTRANS,
PMHAL_PRCM_PD_TRANSIT_STATUS_COUNT = PMHAL_PRCM_PD_TRANSIT_STATUS_MAX + 1U
} |
| | Enum defining PD in Transitions or not. More...
|
| |
| enum | pmhalPrcmContextStateId {
PMHAL_PRCM_CONTEXT_STATUS_MIN = 0U,
PMHAL_PRCM_CONTEXT_STATUS_MAINTAINED = PMHAL_PRCM_CONTEXT_STATUS_MIN,
PMHAL_PRCM_CONTEXT_STATUS_LOST = 1U,
PMHAL_PRCM_CONTEXT_STATUS_MAX = PMHAL_PRCM_CONTEXT_STATUS_LOST,
PMHAL_PRCM_CONTEXT_STATUS_COUNT = PMHAL_PRCM_CONTEXT_STATUS_MAX + 1U,
PMHAL_PRCM_CONTEXT_STATUS_MIN = 0U,
PMHAL_PRCM_CONTEXT_STATUS_MAINTAINED = PMHAL_PRCM_CONTEXT_STATUS_MIN,
PMHAL_PRCM_CONTEXT_STATUS_LOST = 1U,
PMHAL_PRCM_CONTEXT_STATUS_MAX = PMHAL_PRCM_CONTEXT_STATUS_LOST,
PMHAL_PRCM_CONTEXT_STATUS_COUNT = PMHAL_PRCM_CONTEXT_STATUS_MAX + 1U,
PMHAL_PRCM_CONTEXT_STATUS_MIN = 0U,
PMHAL_PRCM_CONTEXT_STATUS_MAINTAINED = PMHAL_PRCM_CONTEXT_STATUS_MIN,
PMHAL_PRCM_CONTEXT_STATUS_LOST = 1U,
PMHAL_PRCM_CONTEXT_STATUS_MAX = PMHAL_PRCM_CONTEXT_STATUS_LOST,
PMHAL_PRCM_CONTEXT_STATUS_COUNT = PMHAL_PRCM_CONTEXT_STATUS_MAX + 1U
} |
| | Enum defining Context Status. More...
|
| |
| enum | pmhalPrcmVdId {
PMHAL_PRCM_VD_LOWER_BOUND = (-(int32_t)1),
PMHAL_PRCM_VD_MIN = 0,
PMHAL_PRCM_VD_MPU = PMHAL_PRCM_VD_MIN,
PMHAL_PRCM_VD_CORE = 1,
PMHAL_PRCM_VD_IVAHD = 2,
PMHAL_PRCM_VD_DSPEVE = 3,
PMHAL_PRCM_VD_GPU = 4,
PMHAL_PRCM_VD_RTC = 5,
PMHAL_PRCM_VD_MAX = PMHAL_PRCM_VD_RTC,
PMHAL_PRCM_VD_COUNT = PMHAL_PRCM_VD_MAX + 1,
PMHAL_PRCM_VD_UNDEF = 0x7FFFFFFF,
PMHAL_PRCM_VD_LOWER_BOUND = (-(int32_t)1),
PMHAL_PRCM_VD_MIN = 0,
PMHAL_PRCM_VD_MPU = PMHAL_PRCM_VD_MIN,
PMHAL_PRCM_VD_CORE = 1,
PMHAL_PRCM_VD_IVAHD = 2,
PMHAL_PRCM_VD_DSPEVE = 3,
PMHAL_PRCM_VD_GPU = 4,
PMHAL_PRCM_VD_RTC = 5,
PMHAL_PRCM_VD_MAX = PMHAL_PRCM_VD_RTC,
PMHAL_PRCM_VD_COUNT = PMHAL_PRCM_VD_MAX + 1,
PMHAL_PRCM_VD_UNDEF = 0x7FFFFFFF,
PMHAL_PRCM_VD_LOWER_BOUND = (-(int32_t)1),
PMHAL_PRCM_VD_MIN = 0,
PMHAL_PRCM_VD_CORE = PMHAL_PRCM_VD_MIN,
PMHAL_PRCM_VD_DSPEVE = 1,
PMHAL_PRCM_VD_MAX = PMHAL_PRCM_VD_DSPEVE,
PMHAL_PRCM_VD_COUNT = PMHAL_PRCM_VD_MAX + 1,
PMHAL_PRCM_VD_UNDEF = 0x7FFFFFFF,
PMHAL_PRCM_VD_LOWER_BOUND = -1,
PMHAL_PRCM_VD_MIN = 0,
PMHAL_PRCM_VD_MPU = PMHAL_PRCM_VD_MIN,
PMHAL_PRCM_VD_CORE = 1,
PMHAL_PRCM_VD_RTC = 2,
PMHAL_PRCM_VD_MAX = PMHAL_PRCM_VD_RTC,
PMHAL_PRCM_VD_COUNT = PMHAL_PRCM_VD_MAX + 1,
PMHAL_PRCM_VD_UNDEF = 0x7FFFFFFF,
PMHAL_PRCM_VD_LOWER_BOUND = -1,
PMHAL_PRCM_VD_MIN = 0,
PMHAL_PRCM_VD_MPU = PMHAL_PRCM_VD_MIN,
PMHAL_PRCM_VD_CORE = 1,
PMHAL_PRCM_VD_RTC = 2,
PMHAL_PRCM_VD_TAMPER = 3,
PMHAL_PRCM_VD_MAX = PMHAL_PRCM_VD_TAMPER,
PMHAL_PRCM_VD_COUNT = PMHAL_PRCM_VD_MAX + 1,
PMHAL_PRCM_VD_UNDEF = 0x7FFFFFFF
} |
| | Voltage Domains. More...
|
| |
| enum | pmhalPrcmPmicRegulatorId {
PMHAL_PRCM_PMIC_REGULATOR_INVALID = (-(int32_t)1),
PMHAL_PRCM_PMIC_REGULATOR_MIN = 0,
PMHAL_PRCM_PMIC_REGULATOR_MPU = PMHAL_PRCM_PMIC_REGULATOR_MIN,
PMHAL_PRCM_PMIC_REGULATOR_CORE = 1,
PMHAL_PRCM_PMIC_REGULATOR_IVA = 2,
PMHAL_PRCM_PMIC_REGULATOR_DSPEVE = 3,
PMHAL_PRCM_PMIC_REGULATOR_GPU = 4,
PMHAL_PRCM_PMIC_REGULATOR_MMC13V3 = 5,
PMHAL_PRCM_PMIC_REGULATOR_SHV5 = 6,
PMHAL_PRCM_PMIC_REGULATOR_1V8PHY = 7,
PMHAL_PRCM_PMIC_REGULATOR_1V8PLL = 8,
PMHAL_PRCM_PMIC_REGULATOR_MAX = PMHAL_PRCM_PMIC_REGULATOR_1V8PLL,
PMHAL_PRCM_PMIC_REGULATOR_COUNT = (PMHAL_PRCM_PMIC_REGULATOR_MAX + 1),
PMHAL_PRCM_PMIC_REGULATOR_INVALID = (-(int32_t)1),
PMHAL_PRCM_PMIC_REGULATOR_MIN = 0,
PMHAL_PRCM_PMIC_REGULATOR_MPU = PMHAL_PRCM_PMIC_REGULATOR_MIN,
PMHAL_PRCM_PMIC_REGULATOR_CORE = 1,
PMHAL_PRCM_PMIC_REGULATOR_IVA = 2,
PMHAL_PRCM_PMIC_REGULATOR_DSPEVE = 3,
PMHAL_PRCM_PMIC_REGULATOR_GPU = 4,
PMHAL_PRCM_PMIC_REGULATOR_MMC13V3 = 5,
PMHAL_PRCM_PMIC_REGULATOR_SHV5 = 6,
PMHAL_PRCM_PMIC_REGULATOR_1V8PHY = 7,
PMHAL_PRCM_PMIC_REGULATOR_1V8PLL = 8,
PMHAL_PRCM_PMIC_REGULATOR_MAX = PMHAL_PRCM_PMIC_REGULATOR_1V8PLL,
PMHAL_PRCM_PMIC_REGULATOR_COUNT = (PMHAL_PRCM_PMIC_REGULATOR_MAX + 1),
PMHAL_PRCM_PMIC_REGULATOR_INVALID = (-(int32_t)1),
PMHAL_PRCM_PMIC_REGULATOR_MIN = 0,
PMHAL_PRCM_PMIC_REGULATOR_CORE = PMHAL_PRCM_PMIC_REGULATOR_MIN,
PMHAL_PRCM_PMIC_REGULATOR_DSPEVE = 1,
PMHAL_PRCM_PMIC_REGULATOR_1V8PHY = 2,
PMHAL_PRCM_PMIC_REGULATOR_DDR_DV = 3,
PMHAL_PRCM_PMIC_REGULATOR_1V8PLL = 4,
PMHAL_PRCM_PMIC_REGULATOR_MAX = PMHAL_PRCM_PMIC_REGULATOR_1V8PLL,
PMHAL_PRCM_PMIC_REGULATOR_COUNT = (PMHAL_PRCM_PMIC_REGULATOR_MAX + 1),
PMHAL_PRCM_PMIC_REGULATOR_INVALID = -1,
PMHAL_PRCM_PMIC_REGULATOR_MIN = 0,
PMHAL_PRCM_PMIC_REGULATOR_MPU = PMHAL_PRCM_PMIC_REGULATOR_MIN,
PMHAL_PRCM_PMIC_REGULATOR_CORE = 1,
PMHAL_PRCM_PMIC_REGULATOR_MMC = 2,
PMHAL_PRCM_PMIC_REGULATOR_SHV5 = 3,
PMHAL_PRCM_PMIC_REGULATOR_1V8PHY = 4,
PMHAL_PRCM_PMIC_REGULATOR_1V8PLL = 5,
PMHAL_PRCM_PMIC_REGULATOR_MAX = PMHAL_PRCM_PMIC_REGULATOR_1V8PLL,
PMHAL_PRCM_PMIC_REGULATOR_COUNT = (PMHAL_PRCM_PMIC_REGULATOR_MAX + 1),
PMHAL_PRCM_PMIC_REGULATOR_INVALID = -1,
PMHAL_PRCM_PMIC_REGULATOR_MIN = 0,
PMHAL_PRCM_PMIC_REGULATOR_MPU = PMHAL_PRCM_PMIC_REGULATOR_MIN,
PMHAL_PRCM_PMIC_REGULATOR_CORE = 1,
PMHAL_PRCM_PMIC_REGULATOR_MMC = 2,
PMHAL_PRCM_PMIC_REGULATOR_SHV5 = 3,
PMHAL_PRCM_PMIC_REGULATOR_1V8PHY = 4,
PMHAL_PRCM_PMIC_REGULATOR_1V8PLL = 5,
PMHAL_PRCM_PMIC_REGULATOR_MAX = PMHAL_PRCM_PMIC_REGULATOR_1V8PLL,
PMHAL_PRCM_PMIC_REGULATOR_COUNT = (PMHAL_PRCM_PMIC_REGULATOR_MAX + 1)
} |
| | The Abstract PMIC Voltage Regulator IDs used by the PMIC Interface. These abstract regulator IDs represent the regulators connected to the voltage rail of the respective voltage domains. The mapping of these abstract regulator IDs to the actual PMIC regulators are done in the respective HW PMIC module. More...
|
| |
| enum | pmhalPrcmSramLdoRetState {
PMHAL_PRCM_SRAM_LDO_RET_STATE_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_RET_STATE_NO_RET = PMHAL_PRCM_SRAM_LDO_RET_STATE_MIN,
PMHAL_PRCM_SRAM_LDO_RET_STATE_RET = 1U,
PMHAL_PRCM_SRAM_LDO_RET_STATE_MAX = PMHAL_PRCM_SRAM_LDO_RET_STATE_RET,
PMHAL_PRCM_SRAM_LDO_RET_STATE_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_RET_STATE_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_RET_STATE_NO_RET = PMHAL_PRCM_SRAM_LDO_RET_STATE_MIN,
PMHAL_PRCM_SRAM_LDO_RET_STATE_RET = 1U,
PMHAL_PRCM_SRAM_LDO_RET_STATE_MAX = PMHAL_PRCM_SRAM_LDO_RET_STATE_RET,
PMHAL_PRCM_SRAM_LDO_RET_STATE_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_RET_STATE_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_RET_STATE_NO_RET = PMHAL_PRCM_SRAM_LDO_RET_STATE_MIN,
PMHAL_PRCM_SRAM_LDO_RET_STATE_RET = 1U,
PMHAL_PRCM_SRAM_LDO_RET_STATE_MAX = PMHAL_PRCM_SRAM_LDO_RET_STATE_RET,
PMHAL_PRCM_SRAM_LDO_RET_STATE_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_RET_STATE_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_RET_STATE_NO_RET = PMHAL_PRCM_SRAM_LDO_RET_STATE_MIN,
PMHAL_PRCM_SRAM_LDO_RET_STATE_RET = 1U,
PMHAL_PRCM_SRAM_LDO_RET_STATE_MAX = PMHAL_PRCM_SRAM_LDO_RET_STATE_RET,
PMHAL_PRCM_SRAM_LDO_RET_STATE_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_RET_STATE_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_RET_STATE_NO_RET = PMHAL_PRCM_SRAM_LDO_RET_STATE_MIN,
PMHAL_PRCM_SRAM_LDO_RET_STATE_RET = 1U,
PMHAL_PRCM_SRAM_LDO_RET_STATE_MAX = PMHAL_PRCM_SRAM_LDO_RET_STATE_RET,
PMHAL_PRCM_SRAM_LDO_RET_STATE_INVALID = 0xFFU
} |
| | SRAM LDO Retention states enumeration. More...
|
| |
| enum | pmhalPrcmSramLdoTransState {
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_STABLE,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_IN_TRANSITION = 1U,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_MAX,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_STABLE,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_IN_TRANSITION = 1U,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_MAX,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_STABLE,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_IN_TRANSITION = 1U,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_MAX,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_STABLE,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_IN_TRANSITION = 1U,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_MAX,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_STABLE,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_IN_TRANSITION = 1U,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_MAX,
PMHAL_PRCM_SRAM_LDO_TRANS_STATE_INVALID = 0xFFU
} |
| | SRAM LDO Transition state enumeration. More...
|
| |
| enum | pmhalPrcmSramLdoStatus {
PMHAL_PRCM_SRAM_LDO_STATUS_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_STATUS_ACTIVE = PMHAL_PRCM_SRAM_LDO_STATUS_MIN,
PMHAL_PRCM_SRAM_LDO_STATUS_RETENTION = 1U,
PMHAL_PRCM_SRAM_LDO_STATUS_MAX = PMHAL_PRCM_SRAM_LDO_STATUS_RETENTION,
PMHAL_PRCM_SRAM_LDO_STATUS_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_STATUS_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_STATUS_ACTIVE = PMHAL_PRCM_SRAM_LDO_STATUS_MIN,
PMHAL_PRCM_SRAM_LDO_STATUS_RETENTION = 1U,
PMHAL_PRCM_SRAM_LDO_STATUS_MAX = PMHAL_PRCM_SRAM_LDO_STATUS_RETENTION,
PMHAL_PRCM_SRAM_LDO_STATUS_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_STATUS_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_STATUS_ACTIVE = PMHAL_PRCM_SRAM_LDO_STATUS_MIN,
PMHAL_PRCM_SRAM_LDO_STATUS_RETENTION = 1U,
PMHAL_PRCM_SRAM_LDO_STATUS_MAX = PMHAL_PRCM_SRAM_LDO_STATUS_RETENTION,
PMHAL_PRCM_SRAM_LDO_STATUS_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_STATUS_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_STATUS_ACTIVE = PMHAL_PRCM_SRAM_LDO_STATUS_MIN,
PMHAL_PRCM_SRAM_LDO_STATUS_RETENTION = 1U,
PMHAL_PRCM_SRAM_LDO_STATUS_MAX = PMHAL_PRCM_SRAM_LDO_STATUS_RETENTION,
PMHAL_PRCM_SRAM_LDO_STATUS_INVALID = 0xFFU,
PMHAL_PRCM_SRAM_LDO_STATUS_MIN = 0U,
PMHAL_PRCM_SRAM_LDO_STATUS_ACTIVE = PMHAL_PRCM_SRAM_LDO_STATUS_MIN,
PMHAL_PRCM_SRAM_LDO_STATUS_RETENTION = 1U,
PMHAL_PRCM_SRAM_LDO_STATUS_MAX = PMHAL_PRCM_SRAM_LDO_STATUS_RETENTION,
PMHAL_PRCM_SRAM_LDO_STATUS_INVALID = 0xFFU
} |
| | SRAM LDO status. More...
|
| |
| enum | pmhalPrcmSramSetupBitFields {
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_MIN = 0U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENABLE_RTA = PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_MIN,
PMHAL_PRCM_SLDO_SETUP_BIT_ABBOFF_ACT = 1U,
PMHAL_PRCM_SLDO_SETUP_BIT_ABBOFF_SLEEP = 2U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC1 = 3U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC2 = 4U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC3 = 5U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC4 = 6U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC5 = 7U,
PMHAL_PRCM_SLDO_SETUP_BIT_AIPOFF = 8U,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_COUNT = 9U,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_INVALID = 0xFFU,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_MIN = 0U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENABLE_RTA = PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_MIN,
PMHAL_PRCM_SLDO_SETUP_BIT_ABBOFF_ACT = 1U,
PMHAL_PRCM_SLDO_SETUP_BIT_ABBOFF_SLEEP = 2U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC1 = 3U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC2 = 4U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC3 = 5U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC4 = 6U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC5 = 7U,
PMHAL_PRCM_SLDO_SETUP_BIT_AIPOFF = 8U,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_COUNT = 9U,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_INVALID = 0xFFU,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_MIN = 0U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENABLE_RTA = PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_MIN,
PMHAL_PRCM_SLDO_SETUP_BIT_ABBOFF_ACT = 1U,
PMHAL_PRCM_SLDO_SETUP_BIT_ABBOFF_SLEEP = 2U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC1 = 3U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC2 = 4U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC3 = 5U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC4 = 6U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC5 = 7U,
PMHAL_PRCM_SLDO_SETUP_BIT_AIPOFF = 8U,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_COUNT = 9U,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_INVALID = 0xFFU,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_MIN = 0U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENABLE_RTA = PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_MIN,
PMHAL_PRCM_SLDO_SETUP_BIT_ABBOFF_ACT = 1U,
PMHAL_PRCM_SLDO_SETUP_BIT_ABBOFF_SLEEP = 2U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC1 = 3U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC2 = 4U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC3 = 5U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC4 = 6U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC5 = 7U,
PMHAL_PRCM_SLDO_SETUP_BIT_AIPOFF = 8U,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_COUNT = 9U,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_INVALID = 0xFFU,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_MIN = 0U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENABLE_RTA = PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_MIN,
PMHAL_PRCM_SLDO_SETUP_BIT_ABBOFF_ACT = 1U,
PMHAL_PRCM_SLDO_SETUP_BIT_ABBOFF_SLEEP = 2U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC1 = 3U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC2 = 4U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC3 = 5U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC4 = 6U,
PMHAL_PRCM_SLDO_SETUP_BIT_ENFUNC5 = 7U,
PMHAL_PRCM_SLDO_SETUP_BIT_AIPOFF = 8U,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_COUNT = 9U,
PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_INVALID = 0xFFU
} |
| | SRAM LDO Setup Register bit field enumeration.   More...
|
| |
| enum | pmhalPrcmClockId {
PMHAL_PRCM_CLK_ATL_L3_GICLK = 0U,
PMHAL_PRCM_CLK_MIN = PMHAL_PRCM_CLK_ATL_L3_GICLK,
PMHAL_PRCM_CLK_ATL_L4_GICLK = 1U,
PMHAL_PRCM_CLK_ATL_GFCLK = 2U,
PMHAL_PRCM_CLK_ABE_GICLK = 3U,
PMHAL_PRCM_CLK_CLKOUTMUX1_CLK = 4U,
PMHAL_PRCM_CLK_CLKOUTMUX2_CLK = 5U,
PMHAL_PRCM_CLK_L3INIT_60M_FCLK = 6U,
PMHAL_PRCM_CLK_COREAON_IO_SRCOMP_GFCLK = 7U,
PMHAL_PRCM_CLK_COREAON_L4_GICLK = 8U,
PMHAL_PRCM_CLK_SR_CORE_SYS_GFCLK = 9U,
PMHAL_PRCM_CLK_SR_DSPEVE_SYS_GFCLK = 10U,
PMHAL_PRCM_CLK_SR_GPU_SYS_GFCLK = 11U,
PMHAL_PRCM_CLK_SR_IVAHD_SYS_GFCLK = 12U,
PMHAL_PRCM_CLK_SR_MPU_SYS_GFCLK = 13U,
PMHAL_PRCM_CLK_COREAON_32K_GFCLK = 14U,
PMHAL_PRCM_CLK_CUSTEFUSE_L4_GICLK = 15U,
PMHAL_PRCM_CLK_CUSTEFUSE_SYS_GFCLK = 16U,
PMHAL_PRCM_CLK_DMA_L3_GICLK = 17U,
PMHAL_PRCM_CLK_DMA_L4_GICLK = 18U,
PMHAL_PRCM_CLK_DSP1_GFCLK = 19U,
PMHAL_PRCM_CLK_DSP2_GFCLK = 20U,
PMHAL_PRCM_CLK_BB2D_GFCLK = 21U,
PMHAL_PRCM_CLK_DSS_L3_GICLK = 22U,
PMHAL_PRCM_CLK_HDMI_CEC_GFCLK = 23U,
PMHAL_PRCM_CLK_HDMI_PHY_GFCLK = 24U,
PMHAL_PRCM_CLK_DSS_GFCLK = 25U,
PMHAL_PRCM_CLK_HDMI_DPLL_CLK = 26U,
PMHAL_PRCM_CLK_DSS_L4_GICLK = 27U,
PMHAL_PRCM_CLK_VIDEO1_DPLL_CLK = 28U,
PMHAL_PRCM_CLK_VIDEO2_DPLL_CLK = 29U,
PMHAL_PRCM_CLK_SDVENC_GFCLK = 30U,
PMHAL_PRCM_CLK_EMIF_DLL_GCLK = 31U,
PMHAL_PRCM_CLK_EMIF_L3_GICLK = 32U,
PMHAL_PRCM_CLK_EMIF_PHY_GCLK = 33U,
PMHAL_PRCM_CLK_EMIF_L4_GICLK = 34U,
PMHAL_PRCM_CLK_EVE1_GFCLK = 35U,
PMHAL_PRCM_CLK_EVE2_GFCLK = 36U,
PMHAL_PRCM_CLK_EVE3_GFCLK = 37U,
PMHAL_PRCM_CLK_EVE4_GFCLK = 38U,
PMHAL_PRCM_CLK_GMAC_RFT_CLK = 39U,
PMHAL_PRCM_CLK_GMAC_MAIN_CLK = 40U,
PMHAL_PRCM_CLK_GMII_250MHZ_CLK = 41U,
PMHAL_PRCM_CLK_RMII_50MHZ_CLK = 42U,
PMHAL_PRCM_CLK_RGMII_5MHZ_CLK = 43U,
PMHAL_PRCM_CLK_GPU_CORE_GCLK = 44U,
PMHAL_PRCM_CLK_GPU_HYD_GCLK = 45U,
PMHAL_PRCM_CLK_GPU_L3_GICLK = 46U,
PMHAL_PRCM_CLK_IPU_L3_GICLK = 47U,
PMHAL_PRCM_CLK_IPU_96M_GFCLK = 48U,
PMHAL_PRCM_CLK_IPU_L4_GICLK = 49U,
PMHAL_PRCM_CLK_MCASP1_AHCLKR = 50U,
PMHAL_PRCM_CLK_MCASP1_AHCLKX = 51U,
PMHAL_PRCM_CLK_MCASP1_AUX_GFCLK = 52U,
PMHAL_PRCM_CLK_TIMER5_GFCLK = 53U,
PMHAL_PRCM_CLK_TIMER6_GFCLK = 54U,
PMHAL_PRCM_CLK_TIMER7_GFCLK = 55U,
PMHAL_PRCM_CLK_TIMER8_GFCLK = 56U,
PMHAL_PRCM_CLK_UART6_GFCLK = 57U,
PMHAL_PRCM_CLK_IPU1_GFCLK = 58U,
PMHAL_PRCM_CLK_IPU2_GFCLK = 59U,
PMHAL_PRCM_CLK_IVA_GCLK = 60U,
PMHAL_PRCM_CLK_L3INIT_L3_GICLK = 61U,
PMHAL_PRCM_CLK_L3INIT_L4_GICLK = 62U,
PMHAL_PRCM_CLK_MMC1_GFCLK = 63U,
PMHAL_PRCM_CLK_L3INIT_32K_GFCLK = 64U,
PMHAL_PRCM_CLK_MMC2_GFCLK = 65U,
PMHAL_PRCM_CLK_MLB_SHB_L3_GICLK = 66U,
PMHAL_PRCM_CLK_MLB_SPB_L4_GICLK = 67U,
PMHAL_PRCM_CLK_MLB_SYS_L3_GFCLK = 68U,
PMHAL_PRCM_CLK_L3INIT_48M_GFCLK = 69U,
PMHAL_PRCM_CLK_SATA_REF_GFCLK = 70U,
PMHAL_PRCM_CLK_USB_LFPS_TX_GFCLK = 71U,
PMHAL_PRCM_CLK_USB_OTG_SS_REF_CLK = 72U,
PMHAL_PRCM_CLK_L3INIT_960M_GFCLK = 73U,
PMHAL_PRCM_CLK_L3INSTR_TS_GCLK = 74U,
PMHAL_PRCM_CLK_L3INSTR_DLL_AGING_GCLK = 75U,
PMHAL_PRCM_CLK_L3INSTR_L3_GICLK = 76U,
PMHAL_PRCM_CLK_L3INSTR_L4_GICLK = 77U,
PMHAL_PRCM_CLK_L3MAIN1_L3_GICLK = 78U,
PMHAL_PRCM_CLK_L3MAIN1_L4_GICLK = 79U,
PMHAL_PRCM_CLK_L4CFG_L3_GICLK = 80U,
PMHAL_PRCM_CLK_L4CFG_L4_GICLK = 81U,
PMHAL_PRCM_CLK_L4PER_L3_GICLK = 82U,
PMHAL_PRCM_CLK_PER_96M_GFCLK = 83U,
PMHAL_PRCM_CLK_L4PER_L4_GICLK = 84U,
PMHAL_PRCM_CLK_TIMER10_GFCLK = 85U,
PMHAL_PRCM_CLK_TIMER11_GFCLK = 86U,
PMHAL_PRCM_CLK_TIMER2_GFCLK = 87U,
PMHAL_PRCM_CLK_TIMER3_GFCLK = 88U,
PMHAL_PRCM_CLK_TIMER4_GFCLK = 89U,
PMHAL_PRCM_CLK_TIMER9_GFCLK = 90U,
PMHAL_PRCM_CLK_PER_12M_GFCLK = 91U,
PMHAL_PRCM_CLK_PER_48M_GFCLK = 92U,
PMHAL_PRCM_CLK_UART1_GFCLK = 93U,
PMHAL_PRCM_CLK_UART2_GFCLK = 94U,
PMHAL_PRCM_CLK_UART3_GFCLK = 95U,
PMHAL_PRCM_CLK_UART4_GFCLK = 96U,
PMHAL_PRCM_CLK_UART5_GFCLK = 97U,
PMHAL_PRCM_CLK_GPIO_GFCLK = 98U,
PMHAL_PRCM_CLK_L4PER_32K_GFCLK = 99U,
PMHAL_PRCM_CLK_MMC3_GFCLK = 100U,
PMHAL_PRCM_CLK_MMC4_GFCLK = 101U,
PMHAL_PRCM_CLK_DCAN2_SYS_CLK = 102U,
PMHAL_PRCM_CLK_L4PER2_L3_GICLK = 103U,
PMHAL_PRCM_CLK_L4PER2_L4_GICLK = 104U,
PMHAL_PRCM_CLK_UART7_GFCLK = 105U,
PMHAL_PRCM_CLK_UART8_GFCLK = 106U,
PMHAL_PRCM_CLK_UART9_GFCLK = 107U,
PMHAL_PRCM_CLK_ICSS_IEP_CLK = 108U,
PMHAL_PRCM_CLK_ICSS_CLK = 109U,
PMHAL_PRCM_CLK_PER_192M_GFCLK = 110U,
PMHAL_PRCM_CLK_MCASP2_AHCLKX = 111U,
PMHAL_PRCM_CLK_MCASP2_AHCLKR = 112U,
PMHAL_PRCM_CLK_MCASP2_AUX_GFCLK = 113U,
PMHAL_PRCM_CLK_MCASP3_AHCLKX = 114U,
PMHAL_PRCM_CLK_MCASP3_AUX_GFCLK = 115U,
PMHAL_PRCM_CLK_MCASP4_AHCLKX = 116U,
PMHAL_PRCM_CLK_MCASP4_AUX_GFCLK = 117U,
PMHAL_PRCM_CLK_MCASP5_AHCLKX = 118U,
PMHAL_PRCM_CLK_MCASP5_AUX_GFCLK = 119U,
PMHAL_PRCM_CLK_MCASP6_AHCLKX = 120U,
PMHAL_PRCM_CLK_MCASP6_AUX_GFCLK = 121U,
PMHAL_PRCM_CLK_MCASP7_AHCLKX = 122U,
PMHAL_PRCM_CLK_MCASP7_AUX_GFCLK = 123U,
PMHAL_PRCM_CLK_MCASP8_AHCLKX = 124U,
PMHAL_PRCM_CLK_MCASP8_AUX_GFCLK = 125U,
PMHAL_PRCM_CLK_QSPI_GFCLK = 126U,
PMHAL_PRCM_CLK_L4PER3_L3_GICLK = 127U,
PMHAL_PRCM_CLK_L4PER3_L4_GICLK = 128U,
PMHAL_PRCM_CLK_TIMER13_GFCLK = 129U,
PMHAL_PRCM_CLK_TIMER14_GFCLK = 130U,
PMHAL_PRCM_CLK_TIMER15_GFCLK = 131U,
PMHAL_PRCM_CLK_TIMER16_GFCLK = 132U,
PMHAL_PRCM_CLK_L4SEC_L3_GICLK = 133U,
PMHAL_PRCM_CLK_L4SEC_L4_GICLK = 134U,
PMHAL_PRCM_CLK_MPU_GCLK = 135U,
PMHAL_PRCM_CLK_PCIE_32K_GFCLK = 136U,
PMHAL_PRCM_CLK_PCIE_L3_GICLK = 137U,
PMHAL_PRCM_CLK_PCIE_PHY_GCLK = 138U,
PMHAL_PRCM_CLK_PCIE_PHY_DIV_GCLK = 139U,
PMHAL_PRCM_CLK_PCIE_REF_GFCLK = 140U,
PMHAL_PRCM_CLK_PCIE_SYS_GFCLK = 141U,
PMHAL_PRCM_CLK_RTC_L4_GICLK = 142U,
PMHAL_PRCM_CLK_RTC_AUX_CLK = 143U,
PMHAL_PRCM_CLK_LVDSRX_96M_GFCLK = 144U,
PMHAL_PRCM_CLK_LVDSRX_L4_GICLK = 145U,
PMHAL_PRCM_CLK_VIP1_GCLK = 146U,
PMHAL_PRCM_CLK_VIP2_GCLK = 147U,
PMHAL_PRCM_CLK_VIP3_GCLK = 148U,
PMHAL_PRCM_CLK_VPE_GCLK = 149U,
PMHAL_PRCM_CLK_EMU_SYS_CLK = 150U,
PMHAL_PRCM_CLK_ADC_GFCLK = 151U,
PMHAL_PRCM_CLK_ADC_L3_GICLK = 152U,
PMHAL_PRCM_CLK_FUNC_32K_CLK = 153U,
PMHAL_PRCM_CLK_WKUPAON_GICLK = 154U,
PMHAL_PRCM_CLK_DCAN1_SYS_CLK = 155U,
PMHAL_PRCM_CLK_WKUPAON_SYS_GFCLK = 156U,
PMHAL_PRCM_CLK_WKUPAON_IO_SRCOMP_GFCLK = 157U,
PMHAL_PRCM_CLK_TIMER1_GFCLK = 158U,
PMHAL_PRCM_CLK_SECURE_32K_CLK = 159U,
PMHAL_PRCM_CLK_UART10_GFCLK = 160U,
PMHAL_PRCM_CLK_RTC_32K_GFCLK = 161U,
PMHAL_PRCM_CLK_MAX = PMHAL_PRCM_CLK_RTC_32K_GFCLK,
PMHAL_PRCM_CLK_COUNT = PMHAL_PRCM_CLK_MAX + 1U,
PMHAL_PRCM_CLK_GENERIC = 163U,
PMHAL_PRCM_CLK_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_CLK_ATL_L3_GICLK = 0U,
PMHAL_PRCM_CLK_MIN = PMHAL_PRCM_CLK_ATL_L3_GICLK,
PMHAL_PRCM_CLK_ATL_L4_GICLK = 1U,
PMHAL_PRCM_CLK_ATL_GFCLK = 2U,
PMHAL_PRCM_CLK_ABE_GICLK = 3U,
PMHAL_PRCM_CLK_CLKOUTMUX1_CLK = 4U,
PMHAL_PRCM_CLK_CLKOUTMUX2_CLK = 5U,
PMHAL_PRCM_CLK_L3INIT_60M_FCLK = 6U,
PMHAL_PRCM_CLK_COREAON_IO_SRCOMP_GFCLK = 7U,
PMHAL_PRCM_CLK_COREAON_L4_GICLK = 8U,
PMHAL_PRCM_CLK_SR_CORE_SYS_GFCLK = 9U,
PMHAL_PRCM_CLK_SR_DSPEVE_SYS_GFCLK = 10U,
PMHAL_PRCM_CLK_SR_GPU_SYS_GFCLK = 11U,
PMHAL_PRCM_CLK_SR_IVAHD_SYS_GFCLK = 12U,
PMHAL_PRCM_CLK_SR_MPU_SYS_GFCLK = 13U,
PMHAL_PRCM_CLK_COREAON_32K_GFCLK = 14U,
PMHAL_PRCM_CLK_CUSTEFUSE_L4_GICLK = 15U,
PMHAL_PRCM_CLK_CUSTEFUSE_SYS_GFCLK = 16U,
PMHAL_PRCM_CLK_DMA_L3_GICLK = 17U,
PMHAL_PRCM_CLK_DMA_L4_GICLK = 18U,
PMHAL_PRCM_CLK_DSP1_GFCLK = 19U,
PMHAL_PRCM_CLK_DSP2_GFCLK = 20U,
PMHAL_PRCM_CLK_BB2D_GFCLK = 21U,
PMHAL_PRCM_CLK_DSS_L3_GICLK = 22U,
PMHAL_PRCM_CLK_HDMI_CEC_GFCLK = 23U,
PMHAL_PRCM_CLK_HDMI_PHY_GFCLK = 24U,
PMHAL_PRCM_CLK_DSS_GFCLK = 25U,
PMHAL_PRCM_CLK_HDMI_DPLL_CLK = 26U,
PMHAL_PRCM_CLK_DSS_L4_GICLK = 27U,
PMHAL_PRCM_CLK_VIDEO1_DPLL_CLK = 28U,
PMHAL_PRCM_CLK_VIDEO2_DPLL_CLK = 29U,
PMHAL_PRCM_CLK_SDVENC_GFCLK = 30U,
PMHAL_PRCM_CLK_EMIF_DLL_GCLK = 31U,
PMHAL_PRCM_CLK_EMIF_L3_GICLK = 32U,
PMHAL_PRCM_CLK_EMIF_PHY_GCLK = 33U,
PMHAL_PRCM_CLK_EMIF_L4_GICLK = 34U,
PMHAL_PRCM_CLK_EVE1_GFCLK = 35U,
PMHAL_PRCM_CLK_EVE2_GFCLK = 36U,
PMHAL_PRCM_CLK_EVE3_GFCLK = 37U,
PMHAL_PRCM_CLK_EVE4_GFCLK = 38U,
PMHAL_PRCM_CLK_GMAC_RFT_CLK = 39U,
PMHAL_PRCM_CLK_GMAC_MAIN_CLK = 40U,
PMHAL_PRCM_CLK_GMII_250MHZ_CLK = 41U,
PMHAL_PRCM_CLK_RMII_50MHZ_CLK = 42U,
PMHAL_PRCM_CLK_RGMII_5MHZ_CLK = 43U,
PMHAL_PRCM_CLK_GPU_CORE_GCLK = 44U,
PMHAL_PRCM_CLK_GPU_HYD_GCLK = 45U,
PMHAL_PRCM_CLK_GPU_L3_GICLK = 46U,
PMHAL_PRCM_CLK_IPU_L3_GICLK = 47U,
PMHAL_PRCM_CLK_IPU_96M_GFCLK = 48U,
PMHAL_PRCM_CLK_IPU_L4_GICLK = 49U,
PMHAL_PRCM_CLK_MCASP1_AHCLKR = 50U,
PMHAL_PRCM_CLK_MCASP1_AHCLKX = 51U,
PMHAL_PRCM_CLK_MCASP1_AUX_GFCLK = 52U,
PMHAL_PRCM_CLK_TIMER5_GFCLK = 53U,
PMHAL_PRCM_CLK_TIMER6_GFCLK = 54U,
PMHAL_PRCM_CLK_TIMER7_GFCLK = 55U,
PMHAL_PRCM_CLK_TIMER8_GFCLK = 56U,
PMHAL_PRCM_CLK_UART6_GFCLK = 57U,
PMHAL_PRCM_CLK_IPU1_GFCLK = 58U,
PMHAL_PRCM_CLK_IPU2_GFCLK = 59U,
PMHAL_PRCM_CLK_IVA_GCLK = 60U,
PMHAL_PRCM_CLK_L3INIT_L3_GICLK = 61U,
PMHAL_PRCM_CLK_L3INIT_L4_GICLK = 62U,
PMHAL_PRCM_CLK_MMC1_GFCLK = 63U,
PMHAL_PRCM_CLK_L3INIT_32K_GFCLK = 64U,
PMHAL_PRCM_CLK_MMC2_GFCLK = 65U,
PMHAL_PRCM_CLK_MLB_SHB_L3_GICLK = 66U,
PMHAL_PRCM_CLK_MLB_SPB_L4_GICLK = 67U,
PMHAL_PRCM_CLK_MLB_SYS_L3_GFCLK = 68U,
PMHAL_PRCM_CLK_L3INIT_48M_GFCLK = 69U,
PMHAL_PRCM_CLK_SATA_REF_GFCLK = 70U,
PMHAL_PRCM_CLK_USB_LFPS_TX_GFCLK = 71U,
PMHAL_PRCM_CLK_USB_OTG_SS_REF_CLK = 72U,
PMHAL_PRCM_CLK_L3INIT_960M_GFCLK = 73U,
PMHAL_PRCM_CLK_L3INSTR_TS_GCLK = 74U,
PMHAL_PRCM_CLK_L3INSTR_DLL_AGING_GCLK = 75U,
PMHAL_PRCM_CLK_L3INSTR_L3_GICLK = 76U,
PMHAL_PRCM_CLK_L3INSTR_L4_GICLK = 77U,
PMHAL_PRCM_CLK_L3MAIN1_L3_GICLK = 78U,
PMHAL_PRCM_CLK_L3MAIN1_L4_GICLK = 79U,
PMHAL_PRCM_CLK_L4CFG_L3_GICLK = 80U,
PMHAL_PRCM_CLK_L4CFG_L4_GICLK = 81U,
PMHAL_PRCM_CLK_L4PER_L3_GICLK = 82U,
PMHAL_PRCM_CLK_PER_96M_GFCLK = 83U,
PMHAL_PRCM_CLK_L4PER_L4_GICLK = 84U,
PMHAL_PRCM_CLK_TIMER10_GFCLK = 85U,
PMHAL_PRCM_CLK_TIMER11_GFCLK = 86U,
PMHAL_PRCM_CLK_TIMER2_GFCLK = 87U,
PMHAL_PRCM_CLK_TIMER3_GFCLK = 88U,
PMHAL_PRCM_CLK_TIMER4_GFCLK = 89U,
PMHAL_PRCM_CLK_TIMER9_GFCLK = 90U,
PMHAL_PRCM_CLK_PER_12M_GFCLK = 91U,
PMHAL_PRCM_CLK_PER_48M_GFCLK = 92U,
PMHAL_PRCM_CLK_UART1_GFCLK = 93U,
PMHAL_PRCM_CLK_UART2_GFCLK = 94U,
PMHAL_PRCM_CLK_UART3_GFCLK = 95U,
PMHAL_PRCM_CLK_UART4_GFCLK = 96U,
PMHAL_PRCM_CLK_UART5_GFCLK = 97U,
PMHAL_PRCM_CLK_GPIO_GFCLK = 98U,
PMHAL_PRCM_CLK_L4PER_32K_GFCLK = 99U,
PMHAL_PRCM_CLK_MMC3_GFCLK = 100U,
PMHAL_PRCM_CLK_MMC4_GFCLK = 101U,
PMHAL_PRCM_CLK_DCAN2_SYS_CLK = 102U,
PMHAL_PRCM_CLK_L4PER2_L3_GICLK = 103U,
PMHAL_PRCM_CLK_L4PER2_L4_GICLK = 104U,
PMHAL_PRCM_CLK_UART7_GFCLK = 105U,
PMHAL_PRCM_CLK_UART8_GFCLK = 106U,
PMHAL_PRCM_CLK_UART9_GFCLK = 107U,
PMHAL_PRCM_CLK_ICSS_IEP_CLK = 108U,
PMHAL_PRCM_CLK_ICSS_CLK = 109U,
PMHAL_PRCM_CLK_PER_192M_GFCLK = 110U,
PMHAL_PRCM_CLK_MCASP2_AHCLKX = 111U,
PMHAL_PRCM_CLK_MCASP2_AHCLKR = 112U,
PMHAL_PRCM_CLK_MCASP2_AUX_GFCLK = 113U,
PMHAL_PRCM_CLK_MCASP3_AHCLKX = 114U,
PMHAL_PRCM_CLK_MCASP3_AUX_GFCLK = 115U,
PMHAL_PRCM_CLK_MCASP4_AHCLKX = 116U,
PMHAL_PRCM_CLK_MCASP4_AUX_GFCLK = 117U,
PMHAL_PRCM_CLK_MCASP5_AHCLKX = 118U,
PMHAL_PRCM_CLK_MCASP5_AUX_GFCLK = 119U,
PMHAL_PRCM_CLK_MCASP6_AHCLKX = 120U,
PMHAL_PRCM_CLK_MCASP6_AUX_GFCLK = 121U,
PMHAL_PRCM_CLK_MCASP7_AHCLKX = 122U,
PMHAL_PRCM_CLK_MCASP7_AUX_GFCLK = 123U,
PMHAL_PRCM_CLK_MCASP8_AHCLKX = 124U,
PMHAL_PRCM_CLK_MCASP8_AUX_GFCLK = 125U,
PMHAL_PRCM_CLK_QSPI_GFCLK = 126U,
PMHAL_PRCM_CLK_L4PER3_L3_GICLK = 127U,
PMHAL_PRCM_CLK_L4PER3_L4_GICLK = 128U,
PMHAL_PRCM_CLK_TIMER13_GFCLK = 129U,
PMHAL_PRCM_CLK_TIMER14_GFCLK = 130U,
PMHAL_PRCM_CLK_TIMER15_GFCLK = 131U,
PMHAL_PRCM_CLK_TIMER16_GFCLK = 132U,
PMHAL_PRCM_CLK_L4SEC_L3_GICLK = 133U,
PMHAL_PRCM_CLK_L4SEC_L4_GICLK = 134U,
PMHAL_PRCM_CLK_MPU_GCLK = 135U,
PMHAL_PRCM_CLK_PCIE_32K_GFCLK = 136U,
PMHAL_PRCM_CLK_PCIE_L3_GICLK = 137U,
PMHAL_PRCM_CLK_PCIE_PHY_GCLK = 138U,
PMHAL_PRCM_CLK_PCIE_PHY_DIV_GCLK = 139U,
PMHAL_PRCM_CLK_PCIE_REF_GFCLK = 140U,
PMHAL_PRCM_CLK_PCIE_SYS_GFCLK = 141U,
PMHAL_PRCM_CLK_RTC_L4_GICLK = 142U,
PMHAL_PRCM_CLK_RTC_AUX_CLK = 143U,
PMHAL_PRCM_CLK_LVDSRX_96M_GFCLK = 144U,
PMHAL_PRCM_CLK_LVDSRX_L4_GICLK = 145U,
PMHAL_PRCM_CLK_VIP1_GCLK = 146U,
PMHAL_PRCM_CLK_CAL_GCLK = 147U,
PMHAL_PRCM_CLK_VIP3_GCLK = 148U,
PMHAL_PRCM_CLK_VPE_GCLK = 149U,
PMHAL_PRCM_CLK_EMU_SYS_CLK = 150U,
PMHAL_PRCM_CLK_ADC_GFCLK = 151U,
PMHAL_PRCM_CLK_ADC_L3_GICLK = 152U,
PMHAL_PRCM_CLK_FUNC_32K_CLK = 153U,
PMHAL_PRCM_CLK_WKUPAON_GICLK = 154U,
PMHAL_PRCM_CLK_DCAN1_SYS_CLK = 155U,
PMHAL_PRCM_CLK_WKUPAON_SYS_GFCLK = 156U,
PMHAL_PRCM_CLK_WKUPAON_IO_SRCOMP_GFCLK = 157U,
PMHAL_PRCM_CLK_TIMER1_GFCLK = 158U,
PMHAL_PRCM_CLK_SECURE_32K_CLK = 159U,
PMHAL_PRCM_CLK_UART10_GFCLK = 160U,
PMHAL_PRCM_CLK_RTC_32K_GFCLK = 161U,
PMHAL_PRCM_CLK_MAX = PMHAL_PRCM_CLK_RTC_32K_GFCLK,
PMHAL_PRCM_CLK_COUNT = PMHAL_PRCM_CLK_MAX + 1U,
PMHAL_PRCM_CLK_GENERIC = 163U,
PMHAL_PRCM_CLK_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_CLK_CRC_L3_GICLK = 0U,
PMHAL_PRCM_CLK_MIN = PMHAL_PRCM_CLK_CRC_L3_GICLK,
PMHAL_PRCM_CLK_ABE_GICLK = 1U,
PMHAL_PRCM_CLK_CLKOUTMUX1_CLK = 2U,
PMHAL_PRCM_CLK_CLKOUTMUX2_CLK = 3U,
PMHAL_PRCM_CLK_SR_CORE_SYS_GFCLK = 4U,
PMHAL_PRCM_CLK_SR_DSPEVE_SYS_GFCLK = 5U,
PMHAL_PRCM_CLK_CUSTEFUSE_SYS_GFCLK = 6U,
PMHAL_PRCM_CLK_DSP1_GFCLK = 7U,
PMHAL_PRCM_CLK_DSP2_GFCLK = 8U,
PMHAL_PRCM_CLK_DSS_L3_GICLK = 9U,
PMHAL_PRCM_CLK_HDMI_CEC_GFCLK = 10U,
PMHAL_PRCM_CLK_HDMI_PHY_GFCLK = 11U,
PMHAL_PRCM_CLK_DSS_GFCLK = 12U,
PMHAL_PRCM_CLK_HDMI_DPLL_CLK = 13U,
PMHAL_PRCM_CLK_DSS_L4_GICLK = 14U,
PMHAL_PRCM_CLK_VIDEO1_DPLL_CLK = 15U,
PMHAL_PRCM_CLK_VIDEO2_DPLL_CLK = 16U,
PMHAL_PRCM_CLK_SDVENC_GFCLK = 17U,
PMHAL_PRCM_CLK_EMIF_DLL_GCLK = 18U,
PMHAL_PRCM_CLK_EMIF_L3_GICLK = 19U,
PMHAL_PRCM_CLK_EMIF_PHY_GCLK = 20U,
PMHAL_PRCM_CLK_EVE1_GFCLK = 21U,
PMHAL_PRCM_CLK_GMAC_RFT_CLK = 22U,
PMHAL_PRCM_CLK_GMAC_MAIN_CLK = 23U,
PMHAL_PRCM_CLK_GMII_250MHZ_CLK = 24U,
PMHAL_PRCM_CLK_RMII_50MHZ_CLK = 25U,
PMHAL_PRCM_CLK_RGMII_5MHZ_CLK = 26U,
PMHAL_PRCM_CLK_MCASP1_AHCLKR = 27U,
PMHAL_PRCM_CLK_MCASP1_AHCLKX = 28U,
PMHAL_PRCM_CLK_MCASP1_AUX_GFCLK = 29U,
PMHAL_PRCM_CLK_TIMER5_GFCLK = 30U,
PMHAL_PRCM_CLK_TIMER6_GFCLK = 31U,
PMHAL_PRCM_CLK_TIMER7_GFCLK = 32U,
PMHAL_PRCM_CLK_TIMER8_GFCLK = 33U,
PMHAL_PRCM_CLK_IPU1_GFCLK = 34U,
PMHAL_PRCM_CLK_L3INIT_L3_GICLK = 35U,
PMHAL_PRCM_CLK_L3INSTR_TS_GCLK = 36U,
PMHAL_PRCM_CLK_L3INSTR_DLL_AGING_GCLK = 37U,
PMHAL_PRCM_CLK_L3INSTR_L3_GICLK = 38U,
PMHAL_PRCM_CLK_L3MAIN1_L3_GICLK = 39U,
PMHAL_PRCM_CLK_L3MAIN1_L4_GICLK = 40U,
PMHAL_PRCM_CLK_L4CFG_L3_GICLK = 41U,
PMHAL_PRCM_CLK_L4CFG_L4_GICLK = 42U,
PMHAL_PRCM_CLK_L4PER_L3_GICLK = 43U,
PMHAL_PRCM_CLK_PER_96M_GFCLK = 44U,
PMHAL_PRCM_CLK_L4PER_L4_GICLK = 45U,
PMHAL_PRCM_CLK_TIMER2_GFCLK = 46U,
PMHAL_PRCM_CLK_TIMER3_GFCLK = 47U,
PMHAL_PRCM_CLK_TIMER4_GFCLK = 48U,
PMHAL_PRCM_CLK_PER_48M_GFCLK = 49U,
PMHAL_PRCM_CLK_UART1_GFCLK = 50U,
PMHAL_PRCM_CLK_UART2_GFCLK = 51U,
PMHAL_PRCM_CLK_UART3_GFCLK = 52U,
PMHAL_PRCM_CLK_GPIO_GFCLK = 53U,
PMHAL_PRCM_CLK_L4PER_32K_GFCLK = 54U,
PMHAL_PRCM_CLK_MMC4_GFCLK = 55U,
PMHAL_PRCM_CLK_DCAN2_SYS_CLK = 56U,
PMHAL_PRCM_CLK_L4PER2_L3_GICLK = 57U,
PMHAL_PRCM_CLK_L4PER2_L4_GICLK = 58U,
PMHAL_PRCM_CLK_QSPI_GFCLK = 59U,
PMHAL_PRCM_CLK_L4PER3_L3_GICLK = 60U,
PMHAL_PRCM_CLK_L4PER3_L4_GICLK = 61U,
PMHAL_PRCM_CLK_VIP1_GCLK = 62U,
PMHAL_PRCM_CLK_ISS_GCLK = 63U,
PMHAL_PRCM_CLK_EMU_SYS_CLK = 64U,
PMHAL_PRCM_CLK_ADC_GFCLK = 65U,
PMHAL_PRCM_CLK_ADC_L3_GICLK = 66U,
PMHAL_PRCM_CLK_FUNC_32K_CLK = 67U,
PMHAL_PRCM_CLK_WKUPAON_GICLK = 68U,
PMHAL_PRCM_CLK_DCAN1_SYS_CLK = 69U,
PMHAL_PRCM_CLK_WKUPAON_SYS_GFCLK = 70U,
PMHAL_PRCM_CLK_TIMER1_GFCLK = 71U,
PMHAL_PRCM_CLK_VID_PIX_CLK = 72U,
PMHAL_PRCM_CLK_TESOC_EXT_CLK = 73U,
PMHAL_PRCM_CLK_DEBUG_ATB_CLK = 74U,
PMHAL_PRCM_CLK_DEBUG_TREXCPT_CLK = 75U,
PMHAL_PRCM_CLK_DEBUG_STMEXPT_CLK = 76U,
PMHAL_PRCM_CLK_RTI1_CLK = 77U,
PMHAL_PRCM_CLK_RTI2_CLK = 78U,
PMHAL_PRCM_CLK_RTI3_CLK = 79U,
PMHAL_PRCM_CLK_RTI4_CLK = 80U,
PMHAL_PRCM_CLK_RTI5_CLK = 81U,
PMHAL_PRCM_CLK_IPU_L3_GICLK = 82U,
PMHAL_PRCM_CLK_IPU_L4_GICLK = 83U,
PMHAL_PRCM_CLK_L3INSTR_L4_GICLK = 84U,
PMHAL_PRCM_CLK_COREAON_L4_GICLK = 85U,
PMHAL_PRCM_CLK_CUSTEFUSE_L4_GICLK = 86U,
PMHAL_PRCM_CLK_L3INIT_L4_GICLK = 87U,
PMHAL_PRCM_CLK_MCAN_CLK = 88U,
PMHAL_PRCM_CLK_MCASP2_AHCLKR = 89U,
PMHAL_PRCM_CLK_MCASP2_AHCLKX = 90U,
PMHAL_PRCM_CLK_MCASP2_AUX_GFCLK = 91U,
PMHAL_PRCM_CLK_MCASP3_AHCLKR = 92U,
PMHAL_PRCM_CLK_MCASP3_AHCLKX = 93U,
PMHAL_PRCM_CLK_MCASP3_AUX_GFCLK = 94U,
PMHAL_PRCM_CLK_MAX = PMHAL_PRCM_CLK_MCASP3_AUX_GFCLK,
PMHAL_PRCM_CLK_COUNT = PMHAL_PRCM_CLK_MAX + 1U,
PMHAL_PRCM_CLK_GENERIC = 96U,
PMHAL_PRCM_CLK_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_CLK_CUST_EFUSE_SYSCLK = 0U,
PMHAL_PRCM_CLK_MIN = PMHAL_PRCM_CLK_CUST_EFUSE_SYSCLK,
PMHAL_PRCM_CLK_L4_CEFUSE_GCLK = 1U,
PMHAL_PRCM_CLK_GFX_FCLK = 2U,
PMHAL_PRCM_CLK_GFX_L3_GCLK = 3U,
PMHAL_PRCM_CLK_L4LS_GFX_GCLK = 4U,
PMHAL_PRCM_CLK_MPU_CLK = 5U,
PMHAL_PRCM_CLK_CAN_CLK = 6U,
PMHAL_PRCM_CLK_CLK_24MHZ = 7U,
PMHAL_PRCM_CLK_CPSW_125MHZ_GCLK = 8U,
PMHAL_PRCM_CLK_CPSW_250MHZ_CLK = 9U,
PMHAL_PRCM_CLK_CPSW_50MHZ_CLK = 10U,
PMHAL_PRCM_CLK_CPSW_5MHZ_CLK = 11U,
PMHAL_PRCM_CLK_CPSW_CPTS_RFT_CLK = 12U,
PMHAL_PRCM_CLK_DMA_L3_GCLK = 13U,
PMHAL_PRCM_CLK_DMA_L4S_GCLK = 14U,
PMHAL_PRCM_CLK_EMIF_GCLK = 15U,
PMHAL_PRCM_CLK_GPIO_1_GDBCLK = 16U,
PMHAL_PRCM_CLK_GPIO_2_GDBCLK = 17U,
PMHAL_PRCM_CLK_GPIO_3_GDBCLK = 18U,
PMHAL_PRCM_CLK_GPIO_4_GDBCLK = 19U,
PMHAL_PRCM_CLK_GPIO_5_GDBCLK = 20U,
PMHAL_PRCM_CLK_GPIO_6_GDBCLK = 21U,
PMHAL_PRCM_CLK_I2C_FCLK = 22U,
PMHAL_PRCM_CLK_ICSS_IEP_GCLK = 23U,
PMHAL_PRCM_CLK_ICSS_OCP_GCLK = 24U,
PMHAL_PRCM_CLK_ICSS_UART_GCLK = 25U,
PMHAL_PRCM_CLK_L3S_GCLK = 26U,
PMHAL_PRCM_CLK_L3_GCLK = 27U,
PMHAL_PRCM_CLK_L4FW_GCLK = 28U,
PMHAL_PRCM_CLK_L4HS_GCLK = 29U,
PMHAL_PRCM_CLK_L4LS_GCLK = 30U,
PMHAL_PRCM_CLK_LCD_GCLK = 31U,
PMHAL_PRCM_CLK_LCD_L3_GCLK = 32U,
PMHAL_PRCM_CLK_LCD_L4S_GCLK = 33U,
PMHAL_PRCM_CLK_MCASP_FCLK = 34U,
PMHAL_PRCM_CLK_MMC_FCLK = 35U,
PMHAL_PRCM_CLK_SPI_GCLK = 36U,
PMHAL_PRCM_CLK_TIMER2_GCLK = 37U,
PMHAL_PRCM_CLK_TIMER3_GCLK = 38U,
PMHAL_PRCM_CLK_TIMER4_GCLK = 39U,
PMHAL_PRCM_CLK_TIMER5_GCLK = 40U,
PMHAL_PRCM_CLK_TIMER6_GCLK = 41U,
PMHAL_PRCM_CLK_TIMER7_GCLK = 42U,
PMHAL_PRCM_CLK_UART_GFCLK = 43U,
PMHAL_PRCM_CLK_USB_PLL_CLK = 44U,
PMHAL_PRCM_CLK_L4_RTC_GCLK = 45U,
PMHAL_PRCM_CLK_RTC_32KCLK = 46U,
PMHAL_PRCM_CLK_STD_EFUSE_SYSCLK = 47U,
PMHAL_PRCM_CLK_ADC_FCLK = 48U,
PMHAL_PRCM_CLK_DBGSYSCLK = 49U,
PMHAL_PRCM_CLK_DEBUG_CLKA_GCLK = 50U,
PMHAL_PRCM_CLK_GPIO0_GDBCLK = 51U,
PMHAL_PRCM_CLK_I2C0_GFCLK = 52U,
PMHAL_PRCM_CLK_L3_AON_GCLK = 53U,
PMHAL_PRCM_CLK_L4_WKUP_AON_GCLK = 54U,
PMHAL_PRCM_CLK_L4_WKUP_GCLK = 55U,
PMHAL_PRCM_CLK_SR_SYSCLK = 56U,
PMHAL_PRCM_CLK_TIMER1_GCLK = 57U,
PMHAL_PRCM_CLK_UART0_GFCLK = 58U,
PMHAL_PRCM_CLK_WDT1_GCLK = 59U,
PMHAL_PRCM_CLK_MAX = PMHAL_PRCM_CLK_WDT1_GCLK,
PMHAL_PRCM_CLK_COUNT = PMHAL_PRCM_CLK_MAX + 1U,
PMHAL_PRCM_CLK_GENERIC = 61U,
PMHAL_PRCM_CLK_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_CLK_CUST_EFUSE_SYSCLK = 0U,
PMHAL_PRCM_CLK_MIN = PMHAL_PRCM_CLK_CUST_EFUSE_SYSCLK,
PMHAL_PRCM_CLK_L4_CEFUSE_GCLK = 1U,
PMHAL_PRCM_CLK_GFX_GFCLK = 2U,
PMHAL_PRCM_CLK_GFX_L3_GCLK = 3U,
PMHAL_PRCM_CLK_MPU_CLK = 4U,
PMHAL_PRCM_CLK_CAN_CLK = 5U,
PMHAL_PRCM_CLK_CPSW_125MHZ_GCLK = 6U,
PMHAL_PRCM_CLK_CPSW_250MHZ_CLK = 7U,
PMHAL_PRCM_CLK_CPSW_50MHZ_CLK = 8U,
PMHAL_PRCM_CLK_CPSW_5MHZ_CLK = 9U,
PMHAL_PRCM_CLK_CPSW_CPTS_RFT_CLK = 10U,
PMHAL_PRCM_CLK_DDR_DLL_GCLK = 11U,
PMHAL_PRCM_CLK_DLL_AGING_GCLK = 12U,
PMHAL_PRCM_CLK_DSS_GCLK = 13U,
PMHAL_PRCM_CLK_DSS_L3_GCLK = 14U,
PMHAL_PRCM_CLK_DSS_L4_GCLK_EN = 15U,
PMHAL_PRCM_CLK_DSS_SYSCLK = 16U,
PMHAL_PRCM_CLK_EMIF_L3_GICLK = 17U,
PMHAL_PRCM_CLK_EMIF_PHY_GCLK = 18U,
PMHAL_PRCM_CLK_GPIO_1_GDBCLK = 19U,
PMHAL_PRCM_CLK_GPIO_2_GDBCLK = 20U,
PMHAL_PRCM_CLK_GPIO_3_GDBCLK = 21U,
PMHAL_PRCM_CLK_GPIO_4_GDBCLK = 22U,
PMHAL_PRCM_CLK_GPIO_5_GDBCLK = 23U,
PMHAL_PRCM_CLK_HDQ1W_GCLK = 24U,
PMHAL_PRCM_CLK_I2C_FCLK = 25U,
PMHAL_PRCM_CLK_ICSS_IEP_GCLK = 26U,
PMHAL_PRCM_CLK_ICSS_OCP_GCLK = 27U,
PMHAL_PRCM_CLK_ICSS_UART_GCLK = 28U,
PMHAL_PRCM_CLK_L3D2_GCLK = 29U,
PMHAL_PRCM_CLK_L3S_GCLK = 30U,
PMHAL_PRCM_CLK_L3_GCLK = 31U,
PMHAL_PRCM_CLK_L4LS_GCLK = 32U,
PMHAL_PRCM_CLK_LCD_GCLK = 33U,
PMHAL_PRCM_CLK_LCD_L3_GCLK = 34U,
PMHAL_PRCM_CLK_LCD_L4S_GCLK = 35U,
PMHAL_PRCM_CLK_MCASP_FCLK = 36U,
PMHAL_PRCM_CLK_MGC_FCLK = 37U,
PMHAL_PRCM_CLK_MMC_FCLK = 38U,
PMHAL_PRCM_CLK_OCPWP_L3_GCLK = 39U,
PMHAL_PRCM_CLK_OCPWP_L4_GCLK_EN = 40U,
PMHAL_PRCM_CLK_SPI_GCLK = 41U,
PMHAL_PRCM_CLK_TIMER10_GCLK = 42U,
PMHAL_PRCM_CLK_TIMER11_GCLK = 43U,
PMHAL_PRCM_CLK_TIMER2_GCLK = 44U,
PMHAL_PRCM_CLK_TIMER3_GCLK = 45U,
PMHAL_PRCM_CLK_TIMER4_GCLK = 46U,
PMHAL_PRCM_CLK_TIMER5_GCLK = 47U,
PMHAL_PRCM_CLK_TIMER6_GCLK = 48U,
PMHAL_PRCM_CLK_TIMER7_GCLK = 49U,
PMHAL_PRCM_CLK_TIMER8_GCLK = 50U,
PMHAL_PRCM_CLK_TIMER9_GCLK = 51U,
PMHAL_PRCM_CLK_UART_GFCLK = 52U,
PMHAL_PRCM_CLK_USB_OTG_SS_REFCLK = 53U,
PMHAL_PRCM_CLK_USB_PLL_CLK = 54U,
PMHAL_PRCM_CLK_USIM0_FCLK = 55U,
PMHAL_PRCM_CLK_USIM0_FCLK32 = 56U,
PMHAL_PRCM_CLK_USIM1_FCLK = 57U,
PMHAL_PRCM_CLK_USIM1_FCLK32 = 58U,
PMHAL_PRCM_CLK_L4_RTC_GCLK = 59U,
PMHAL_PRCM_CLK_RTC_32KCLK = 60U,
PMHAL_PRCM_CLK_STD_EFUSE_SYSCLK = 61U,
PMHAL_PRCM_CLK_TAMPER_L4_GCLK = 62U,
PMHAL_PRCM_CLK_ADC_FCLK = 63U,
PMHAL_PRCM_CLK_CLK_24MHZ = 64U,
PMHAL_PRCM_CLK_DBGSYSCLK = 65U,
PMHAL_PRCM_CLK_DEBUG_CLKA_GCLK = 66U,
PMHAL_PRCM_CLK_DEBUG_CLKB_GCLK = 67U,
PMHAL_PRCM_CLK_DEBUG_CLKC_GCLK = 68U,
PMHAL_PRCM_CLK_GPIO0_GDBCLK = 69U,
PMHAL_PRCM_CLK_I2C0_GFCLK = 70U,
PMHAL_PRCM_CLK_L3S_TSC_GCLK = 71U,
PMHAL_PRCM_CLK_L3_AON_GCLK = 72U,
PMHAL_PRCM_CLK_L4_WKUP_AON_GCLK = 73U,
PMHAL_PRCM_CLK_L4_WKUP_GCLK = 74U,
PMHAL_PRCM_CLK_SR_SYSCLK = 75U,
PMHAL_PRCM_CLK_SYNCTIMER32K_GFCLK = 76U,
PMHAL_PRCM_CLK_TIMER0_GCLK = 77U,
PMHAL_PRCM_CLK_TIMER1_GCLK = 78U,
PMHAL_PRCM_CLK_UART0_GFCLK = 79U,
PMHAL_PRCM_CLK_USBPHY_32KHZ_GCLK = 80U,
PMHAL_PRCM_CLK_WDT1_GCLK = 82U,
PMHAL_PRCM_CLK_MAX = PMHAL_PRCM_CLK_WDT1_GCLK,
PMHAL_PRCM_CLK_COUNT = PMHAL_PRCM_CLK_MAX + 1U,
PMHAL_PRCM_CLK_GENERIC = PMHAL_PRCM_CLK_COUNT +1U,
PMHAL_PRCM_CLK_UNDEF = 0x7FFFFFFFU
} |
| | Clocks.  More...
|
| |
| enum | pmhalPrcmGlobalResetGroupId {
PMHAL_PRCM_GLB_RG_LOWER_BOUND = (-(int32_t)1),
PMHAL_PRCM_GLB_RG_MIN = 0,
PMHAL_PRCM_GLB_RG_GLOBAL_COLD_RST = PMHAL_PRCM_GLB_RG_MIN,
PMHAL_PRCM_GLB_RG_GLOBAL_WARM_SW_RST = 1,
PMHAL_PRCM_GLB_RG_MPU_WDT_RST = 2,
PMHAL_PRCM_GLB_RG_EXTERNAL_WARM_RST = 3,
PMHAL_PRCM_GLB_RG_ICEPICK_RST = 4,
PMHAL_PRCM_GLB_RG_TSHUT_MPU_RST = 5,
PMHAL_PRCM_GLB_RG_TSHUT_MM_RST = 6,
PMHAL_PRCM_GLB_RG_TSHUT_CORE_RST = 7,
PMHAL_PRCM_GLB_RG_TSHUT_DSPEVE_RST = 8,
PMHAL_PRCM_GLB_RG_TSHUT_IVA_RST = 9,
PMHAL_PRCM_GLB_RG_MAX = PMHAL_PRCM_GLB_RG_TSHUT_IVA_RST,
PMHAL_PRCM_GLB_RG_COUNT = PMHAL_PRCM_GLB_RG_MAX + 1,
PMHAL_PRCM_GLB_RG_UNDEF = 0x7FFFFFFF,
PMHAL_PRCM_GLB_RG_LOWER_BOUND = (-(int32_t)1),
PMHAL_PRCM_GLB_RG_MIN = 0,
PMHAL_PRCM_GLB_RG_GLOBAL_COLD_RST = PMHAL_PRCM_GLB_RG_MIN,
PMHAL_PRCM_GLB_RG_GLOBAL_WARM_SW_RST = 1,
PMHAL_PRCM_GLB_RG_MPU_WDT_RST = 2,
PMHAL_PRCM_GLB_RG_EXTERNAL_WARM_RST = 3,
PMHAL_PRCM_GLB_RG_ICEPICK_RST = 4,
PMHAL_PRCM_GLB_RG_TSHUT_MPU_RST = 5,
PMHAL_PRCM_GLB_RG_TSHUT_MM_RST = 6,
PMHAL_PRCM_GLB_RG_TSHUT_CORE_RST = 7,
PMHAL_PRCM_GLB_RG_TSHUT_DSPEVE_RST = 8,
PMHAL_PRCM_GLB_RG_TSHUT_IVA_RST = 9,
PMHAL_PRCM_GLB_RG_MAX = PMHAL_PRCM_GLB_RG_TSHUT_IVA_RST,
PMHAL_PRCM_GLB_RG_COUNT = PMHAL_PRCM_GLB_RG_MAX + 1,
PMHAL_PRCM_GLB_RG_UNDEF = 0x7FFFFFFF,
PMHAL_PRCM_GLB_RG_LOWER_BOUND = (-(int32_t)1),
PMHAL_PRCM_GLB_RG_MIN = 0,
PMHAL_PRCM_GLB_RG_GLOBAL_COLD_RST = PMHAL_PRCM_GLB_RG_MIN,
PMHAL_PRCM_GLB_RG_GLOBAL_WARM_SW_RST = 1,
PMHAL_PRCM_GLB_RG_EXTERNAL_WARM_RST = 2,
PMHAL_PRCM_GLB_RG_ICEPICK_RST = 3,
PMHAL_PRCM_GLB_RG_TSHUT_CORE_RST = 4,
PMHAL_PRCM_GLB_RG_MAX = PMHAL_PRCM_GLB_RG_TSHUT_CORE_RST,
PMHAL_PRCM_GLB_RG_COUNT = PMHAL_PRCM_GLB_RG_MAX + 1,
PMHAL_PRCM_GLB_RG_UNDEF = 0x7FFFFFFF,
PMHAL_PRCM_GLB_RG_LOWER_BOUND = -1,
PMHAL_PRCM_GLB_RG_MIN = 0,
PMHAL_PRCM_GLB_RG_GLOBAL_COLD_RST = PMHAL_PRCM_GLB_RG_MIN,
PMHAL_PRCM_GLB_RG_GLOBAL_WARM_SW_RST = 1,
PMHAL_PRCM_GLB_RG_WDT1_RST = 2,
PMHAL_PRCM_GLB_RG_EXTERNAL_WARM_RST = 3,
PMHAL_PRCM_GLB_RG_ICEPICK_RST = 4,
PMHAL_PRCM_GLB_RG_MPU_SECURITY_VIOL_RST = 5,
PMHAL_PRCM_GLB_RG_MAX = PMHAL_PRCM_GLB_RG_MPU_SECURITY_VIOL_RST,
PMHAL_PRCM_GLB_RG_COUNT = PMHAL_PRCM_GLB_RG_MAX + 1,
PMHAL_PRCM_GLB_RG_UNDEF = 0x7FFFFFFF,
PMHAL_PRCM_GLB_RG_LOWER_BOUND = -1,
PMHAL_PRCM_GLB_RG_MIN = 0,
PMHAL_PRCM_GLB_RG_GLOBAL_COLD_RST = PMHAL_PRCM_GLB_RG_MIN,
PMHAL_PRCM_GLB_RG_GLOBAL_WARM_SW_RST = 1,
PMHAL_PRCM_GLB_RG_WDT1_RST = 2,
PMHAL_PRCM_GLB_RG_EXTERNAL_WARM_RST = 3,
PMHAL_PRCM_GLB_RG_ICEPICK_RST = 4,
PMHAL_PRCM_GLB_RG_MPU_SECURITY_VIOL_RST = 5,
PMHAL_PRCM_GLB_RG_MAX = PMHAL_PRCM_GLB_RG_MPU_SECURITY_VIOL_RST,
PMHAL_PRCM_GLB_RG_COUNT = PMHAL_PRCM_GLB_RG_MAX + 1,
PMHAL_PRCM_GLB_RG_UNDEF = 0x7FFFFFFF
} |
| | Reset List. More...
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| |
| enum | pmhalPrcmResetId {
PMHAL_PRCM_RST_MIN = 0U,
PMHAL_PRCM_RST_MAX = PMHAL_PRCM_RST_MIN,
PMHAL_PRCM_RST_COUNT = PMHAL_PRCM_RST_MAX + 1U,
PMHAL_PRCM_RST_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_RST_MIN = 0U,
PMHAL_PRCM_RST_MAX = PMHAL_PRCM_RST_MIN,
PMHAL_PRCM_RST_COUNT = PMHAL_PRCM_RST_MAX + 1U,
PMHAL_PRCM_RST_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_RST_MIN = 0U,
PMHAL_PRCM_RST_MAX = PMHAL_PRCM_RST_MIN,
PMHAL_PRCM_RST_COUNT = PMHAL_PRCM_RST_MAX + 1U,
PMHAL_PRCM_RST_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_RST_MIN = 0U,
PMHAL_PRCM_RST_MAX = PMHAL_PRCM_RST_MIN,
PMHAL_PRCM_RST_COUNT = PMHAL_PRCM_RST_MAX + 1U,
PMHAL_PRCM_RST_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_RST_MIN = 0U,
PMHAL_PRCM_RST_MAX = PMHAL_PRCM_RST_MIN,
PMHAL_PRCM_RST_COUNT = PMHAL_PRCM_RST_MAX + 1U,
PMHAL_PRCM_RST_UNDEF = 0x7FFFFFFFU
} |
| | Reset List. More...
|
| |
| enum | pmhalPrcmMemOnState {
MEM_ON_MIN = 0U,
MEM_ON_ALWAYS_ON = MEM_ON_MIN,
MEM_ON_SOFTWARE_CONTROL = 1U,
MEM_ON_MAX = MEM_ON_SOFTWARE_CONTROL,
MEM_ON_COUNT = MEM_ON_MAX + 1U,
MEM_ON_UNDEF = 0x7FFFFFFFU,
MEM_ON_MIN = 0U,
MEM_ON_ALWAYS_ON = MEM_ON_MIN,
MEM_ON_SOFTWARE_CONTROL = 1U,
MEM_ON_MAX = MEM_ON_SOFTWARE_CONTROL,
MEM_ON_COUNT = MEM_ON_MAX + 1U,
MEM_ON_UNDEF = 0x7FFFFFFFU,
MEM_ON_MIN = 0U,
MEM_ON_ALWAYS_ON = MEM_ON_MIN,
MEM_ON_SOFTWARE_CONTROL = 1U,
MEM_ON_MAX = MEM_ON_SOFTWARE_CONTROL,
MEM_ON_COUNT = MEM_ON_MAX + 1U,
MEM_ON_UNDEF = 0x7FFFFFFFU,
MEM_ON_MIN = 0U,
MEM_ON_ALWAYS_ON = MEM_ON_MIN,
MEM_ON_SOFTWARE_CONTROL = 1U,
MEM_ON_MAX = MEM_ON_SOFTWARE_CONTROL,
MEM_ON_COUNT = MEM_ON_MAX + 1U,
MEM_ON_UNDEF = 0x7FFFFFFFU,
MEM_ON_MIN = 0U,
MEM_ON_ALWAYS_ON = MEM_ON_MIN,
MEM_ON_SOFTWARE_CONTROL = 1U,
MEM_ON_MAX = MEM_ON_SOFTWARE_CONTROL,
MEM_ON_COUNT = MEM_ON_MAX + 1U,
MEM_ON_UNDEF = 0x7FFFFFFFU
} |
| | Specification of Memory ON State. More...
|
| |
| enum | pmhalPrcmMemRetState {
MEM_RET_MIN = 0U,
MEM_RET_ALWAYS_RETENTION = MEM_RET_MIN,
MEM_RET_SOFTWARE_CONTROL = 1U,
MEM_RET_ALWAYS_OFF = 2U,
MEM_RET_MAX = MEM_RET_ALWAYS_OFF,
MEM_RET_COUNT = MEM_RET_MAX + 1U,
MEM_RET_UNDEF = 0x7FFFFFFFU,
MEM_RET_MIN = 0U,
MEM_RET_ALWAYS_RETENTION = MEM_RET_MIN,
MEM_RET_SOFTWARE_CONTROL = 1U,
MEM_RET_ALWAYS_OFF = 2U,
MEM_RET_MAX = MEM_RET_ALWAYS_OFF,
MEM_RET_COUNT = MEM_RET_MAX + 1U,
MEM_RET_UNDEF = 0x7FFFFFFFU,
MEM_RET_MIN = 0U,
MEM_RET_ALWAYS_RETENTION = MEM_RET_MIN,
MEM_RET_SOFTWARE_CONTROL = 1U,
MEM_RET_ALWAYS_OFF = 2U,
MEM_RET_MAX = MEM_RET_ALWAYS_OFF,
MEM_RET_COUNT = MEM_RET_MAX + 1U,
MEM_RET_UNDEF = 0x7FFFFFFFU,
MEM_RET_MIN = 0U,
MEM_RET_ALWAYS_RETENTION = MEM_RET_MIN,
MEM_RET_SOFTWARE_CONTROL = 1U,
MEM_RET_ALWAYS_OFF = 2U,
MEM_RET_MAX = MEM_RET_ALWAYS_OFF,
MEM_RET_COUNT = MEM_RET_MAX + 1U,
MEM_RET_UNDEF = 0x7FFFFFFFU,
MEM_RET_MIN = 0U,
MEM_RET_ALWAYS_RETENTION = MEM_RET_MIN,
MEM_RET_SOFTWARE_CONTROL = 1U,
MEM_RET_ALWAYS_OFF = 2U,
MEM_RET_MAX = MEM_RET_ALWAYS_OFF,
MEM_RET_COUNT = MEM_RET_MAX + 1U,
MEM_RET_UNDEF = 0x7FFFFFFFU
} |
| | Specification of Memory Retention State. More...
|
| |
| enum | pmhalPrcmDpllType {
PMHAL_PRCM_DPLL_TYPE_MIN = 0U,
PMHAL_PRCM_DPLL_TYPE_APLLPCIE = PMHAL_PRCM_DPLL_TYPE_MIN,
PMHAL_PRCM_DPLL_TYPE_ADPLLM = 1U,
PMHAL_PRCM_DPLL_TYPE_ADPPLM = 2U,
PMHAL_PRCM_DPLL_TYPE_ADPLLLJM = 3U,
PMHAL_PRCM_DPLL_TYPE_MAX = PMHAL_PRCM_DPLL_TYPE_ADPLLLJM,
PMHAL_PRCM_DPLL_TYPE_COUNT = PMHAL_PRCM_DPLL_TYPE_MAX + 1U,
PMHAL_PRCM_DPLL_TYPE_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_TYPE_MIN = 0U,
PMHAL_PRCM_DPLL_TYPE_APLLPCIE = PMHAL_PRCM_DPLL_TYPE_MIN,
PMHAL_PRCM_DPLL_TYPE_ADPLLM = 1U,
PMHAL_PRCM_DPLL_TYPE_ADPPLM = 2U,
PMHAL_PRCM_DPLL_TYPE_ADPLLLJM = 3U,
PMHAL_PRCM_DPLL_TYPE_MAX = PMHAL_PRCM_DPLL_TYPE_ADPLLLJM,
PMHAL_PRCM_DPLL_TYPE_COUNT = PMHAL_PRCM_DPLL_TYPE_MAX + 1U,
PMHAL_PRCM_DPLL_TYPE_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_TYPE_MIN = 0U,
PMHAL_PRCM_DPLL_TYPE_APLLPCIE = PMHAL_PRCM_DPLL_TYPE_MIN,
PMHAL_PRCM_DPLL_TYPE_ADPLLM = 1U,
PMHAL_PRCM_DPLL_TYPE_ADPPLM = 2U,
PMHAL_PRCM_DPLL_TYPE_ADPLLLJM = 3U,
PMHAL_PRCM_DPLL_TYPE_MAX = PMHAL_PRCM_DPLL_TYPE_ADPLLLJM,
PMHAL_PRCM_DPLL_TYPE_COUNT = PMHAL_PRCM_DPLL_TYPE_MAX + 1U,
PMHAL_PRCM_DPLL_TYPE_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_TYPE_MIN = 0U,
PMHAL_PRCM_DPLL_TYPE_ADPLL = PMHAL_PRCM_DPLL_TYPE_MIN,
PMHAL_PRCM_DPLL_TYPE_ADPLLLJ = 1U,
PMHAL_PRCM_DPLL_TYPE_MAX = PMHAL_PRCM_DPLL_TYPE_ADPLLLJ,
PMHAL_PRCM_DPLL_TYPE_COUNT = PMHAL_PRCM_DPLL_TYPE_MAX + 1U,
PMHAL_PRCM_DPLL_TYPE_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_TYPE_MIN = 0U,
PMHAL_PRCM_DPLL_TYPE_ADPLL = PMHAL_PRCM_DPLL_TYPE_MIN,
PMHAL_PRCM_DPLL_TYPE_ADPLLLJ = 1U,
PMHAL_PRCM_DPLL_TYPE_MAX = PMHAL_PRCM_DPLL_TYPE_ADPLLLJ,
PMHAL_PRCM_DPLL_TYPE_COUNT = PMHAL_PRCM_DPLL_TYPE_MAX + 1U,
PMHAL_PRCM_DPLL_TYPE_UNDEF = 0x7FFFFFFFU
} |
| | Type of DPLL. More...
|
| |
| enum | pmhalPrcmRetentionType {
PMHAL_PRCM_RT_MIN = 0U,
PMHAL_PRCM_RT_NO_RETENTION = PMHAL_PRCM_RT_MIN,
PMHAL_PRCM_RT_FULL_RETENTION = 1U,
PMHAL_PRCM_RT_PARTIAL_RETENTION = 2U,
PMHAL_PRCM_RT_MAX = PMHAL_PRCM_RT_PARTIAL_RETENTION,
PMHAL_PRCM_RT_COUNT = PMHAL_PRCM_RT_MAX + 1U,
PMHAL_PRCM_RT_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_RT_MIN = 0U,
PMHAL_PRCM_RT_NO_RETENTION = PMHAL_PRCM_RT_MIN,
PMHAL_PRCM_RT_FULL_RETENTION = 1U,
PMHAL_PRCM_RT_PARTIAL_RETENTION = 2U,
PMHAL_PRCM_RT_MAX = PMHAL_PRCM_RT_PARTIAL_RETENTION,
PMHAL_PRCM_RT_COUNT = PMHAL_PRCM_RT_MAX + 1U,
PMHAL_PRCM_RT_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_RT_MIN = 0U,
PMHAL_PRCM_RT_NO_RETENTION = PMHAL_PRCM_RT_MIN,
PMHAL_PRCM_RT_FULL_RETENTION = 1U,
PMHAL_PRCM_RT_PARTIAL_RETENTION = 2U,
PMHAL_PRCM_RT_MAX = PMHAL_PRCM_RT_PARTIAL_RETENTION,
PMHAL_PRCM_RT_COUNT = PMHAL_PRCM_RT_MAX + 1U,
PMHAL_PRCM_RT_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_RT_MIN = 0U,
PMHAL_PRCM_RT_NO_RETENTION = PMHAL_PRCM_RT_MIN,
PMHAL_PRCM_RT_FULL_RETENTION = 1U,
PMHAL_PRCM_RT_PARTIAL_RETENTION = 2U,
PMHAL_PRCM_RT_MAX = PMHAL_PRCM_RT_PARTIAL_RETENTION,
PMHAL_PRCM_RT_COUNT = PMHAL_PRCM_RT_MAX + 1U,
PMHAL_PRCM_RT_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_RT_MIN = 0U,
PMHAL_PRCM_RT_NO_RETENTION = PMHAL_PRCM_RT_MIN,
PMHAL_PRCM_RT_FULL_RETENTION = 1U,
PMHAL_PRCM_RT_PARTIAL_RETENTION = 2U,
PMHAL_PRCM_RT_MAX = PMHAL_PRCM_RT_PARTIAL_RETENTION,
PMHAL_PRCM_RT_COUNT = PMHAL_PRCM_RT_MAX + 1U,
PMHAL_PRCM_RT_UNDEF = 0x7FFFFFFFU
} |
| | PRCM Logic Retention Type. More...
|
| |
| enum | pmhalPrcmPhyMemId {
PMHAL_PRCM_PHY_MEM_MIN = 0U,
PMHAL_PRCM_PHY_MEM_ATL = PMHAL_PRCM_PHY_MEM_MIN,
PMHAL_PRCM_PHY_MEM_DMA = 1U,
PMHAL_PRCM_PHY_MEM_DSP_DSP_DMA = 2U,
PMHAL_PRCM_PHY_MEM_DSP_L1 = 3U,
PMHAL_PRCM_PHY_MEM_DSP_L2 = 4U,
PMHAL_PRCM_PHY_MEM_BB2D = 5U,
PMHAL_PRCM_PHY_MEM_DSSMEM = 6U,
PMHAL_PRCM_PHY_MEM_DMM_MEMBANK1 = 7U,
PMHAL_PRCM_PHY_MEM_DMM_MEMBANK2 = 8U,
PMHAL_PRCM_PHY_MEM_EVE_BANK = 9U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_TX_DB = 10U,
PMHAL_PRCM_PHY_MEM_GPU = 11U,
PMHAL_PRCM_PHY_MEM_UART = 12U,
PMHAL_PRCM_PHY_MEM_IPU_L2RAM = 13U,
PMHAL_PRCM_PHY_MEM_IPU_UNICACHE_MEM = 14U,
PMHAL_PRCM_PHY_MEM_HWA = 15U,
PMHAL_PRCM_PHY_MEM_TCM_1 = 16U,
PMHAL_PRCM_PHY_MEM_TCM_2 = 17U,
PMHAL_PRCM_PHY_MEM_SL2MEM = 18U,
PMHAL_PRCM_PHY_MEM_MMC_RAM = 19U,
PMHAL_PRCM_PHY_MEM_MLB = 20U,
PMHAL_PRCM_PHY_MEM_SATA_BANK = 21U,
PMHAL_PRCM_PHY_MEM_USB = 22U,
PMHAL_PRCM_PHY_MEM_OCPWP_BANK = 23U,
PMHAL_PRCM_PHY_MEM_OCMC_RAM_BANK1 = 24U,
PMHAL_PRCM_PHY_MEM_OCMC_ROM_MEM = 25U,
PMHAL_PRCM_PHY_MEM_VCP_MEM = 26U,
PMHAL_PRCM_PHY_MEM_TPCC = 27U,
PMHAL_PRCM_PHY_MEM_TPTC = 28U,
PMHAL_PRCM_PHY_MEM_DCAN = 29U,
PMHAL_PRCM_PHY_MEM_IMEM3 = 30U,
PMHAL_PRCM_PHY_MEM_DMA_CRYPTO = 31U,
PMHAL_PRCM_PHY_MEM_PKA_MEM = 32U,
PMHAL_PRCM_PHY_MEM_MPU_L2 = 33U,
PMHAL_PRCM_PHY_MEM_MPU_RAM = 34U,
PMHAL_PRCM_PHY_MEM_PCIE = 35U,
PMHAL_PRCM_PHY_MEM_VIP = 36U,
PMHAL_PRCM_PHY_MEM_VPE = 37U,
PMHAL_PRCM_PHY_MEM_DEBUGSS = 38U,
PMHAL_PRCM_PHY_MEM_SAR_BANK = 39U,
PMHAL_PRCM_PHY_MEM_MAX = PMHAL_PRCM_PHY_MEM_SAR_BANK,
PMHAL_PRCM_PHY_MEM_COUNT = PMHAL_PRCM_PHY_MEM_MAX + 1U,
PMHAL_PRCM_PHY_MEM_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_PHY_MEM_MIN = 0U,
PMHAL_PRCM_PHY_MEM_ATL = PMHAL_PRCM_PHY_MEM_MIN,
PMHAL_PRCM_PHY_MEM_DMA = 1U,
PMHAL_PRCM_PHY_MEM_DSP_DSP_DMA = 2U,
PMHAL_PRCM_PHY_MEM_DSP_L1 = 3U,
PMHAL_PRCM_PHY_MEM_DSP_L2 = 4U,
PMHAL_PRCM_PHY_MEM_BB2D = 5U,
PMHAL_PRCM_PHY_MEM_DSSMEM = 6U,
PMHAL_PRCM_PHY_MEM_DMM_MEMBANK1 = 7U,
PMHAL_PRCM_PHY_MEM_DMM_MEMBANK2 = 8U,
PMHAL_PRCM_PHY_MEM_EVE_BANK = 9U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_TX_DB = 10U,
PMHAL_PRCM_PHY_MEM_GPU = 11U,
PMHAL_PRCM_PHY_MEM_UART = 12U,
PMHAL_PRCM_PHY_MEM_IPU_L2RAM = 13U,
PMHAL_PRCM_PHY_MEM_IPU_UNICACHE_MEM = 14U,
PMHAL_PRCM_PHY_MEM_HWA = 15U,
PMHAL_PRCM_PHY_MEM_TCM_1 = 16U,
PMHAL_PRCM_PHY_MEM_TCM_2 = 17U,
PMHAL_PRCM_PHY_MEM_SL2MEM = 18U,
PMHAL_PRCM_PHY_MEM_MMC_RAM = 19U,
PMHAL_PRCM_PHY_MEM_MLB = 20U,
PMHAL_PRCM_PHY_MEM_SATA_BANK = 21U,
PMHAL_PRCM_PHY_MEM_USB = 22U,
PMHAL_PRCM_PHY_MEM_OCPWP_BANK = 23U,
PMHAL_PRCM_PHY_MEM_OCMC_RAM_BANK1 = 24U,
PMHAL_PRCM_PHY_MEM_OCMC_ROM_MEM = 25U,
PMHAL_PRCM_PHY_MEM_VCP_MEM = 26U,
PMHAL_PRCM_PHY_MEM_TPCC = 27U,
PMHAL_PRCM_PHY_MEM_TPTC = 28U,
PMHAL_PRCM_PHY_MEM_DCAN = 29U,
PMHAL_PRCM_PHY_MEM_IMEM3 = 30U,
PMHAL_PRCM_PHY_MEM_DMA_CRYPTO = 31U,
PMHAL_PRCM_PHY_MEM_PKA_MEM = 32U,
PMHAL_PRCM_PHY_MEM_MPU_L2 = 33U,
PMHAL_PRCM_PHY_MEM_MPU_RAM = 34U,
PMHAL_PRCM_PHY_MEM_PCIE = 35U,
PMHAL_PRCM_PHY_MEM_VIP = 36U,
PMHAL_PRCM_PHY_MEM_VPE = 37U,
PMHAL_PRCM_PHY_MEM_DEBUGSS = 38U,
PMHAL_PRCM_PHY_MEM_SAR_BANK = 39U,
PMHAL_PRCM_PHY_MEM_MAX = PMHAL_PRCM_PHY_MEM_SAR_BANK,
PMHAL_PRCM_PHY_MEM_COUNT = PMHAL_PRCM_PHY_MEM_MAX + 1U,
PMHAL_PRCM_PHY_MEM_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_PHY_MEM_MIN = 0U,
PMHAL_PRCM_PHY_MEM_DP_CMEM0 = PMHAL_PRCM_PHY_MEM_MIN,
PMHAL_PRCM_PHY_MEM_DP_CMEM1 = 1U,
PMHAL_PRCM_PHY_MEM_DP_LMEM0 = 2U,
PMHAL_PRCM_PHY_MEM_DP_LMEM1 = 3U,
PMHAL_PRCM_PHY_MEM_DP_RMEM0 = 4U,
PMHAL_PRCM_PHY_MEM_DP_RMEM1 = 5U,
PMHAL_PRCM_PHY_MEM_DP_S_AMEM0 = 6U,
PMHAL_PRCM_PHY_MEM_DP_S_AMEM1 = 7U,
PMHAL_PRCM_PHY_MEM_DP_S_LMEM0 = 8U,
PMHAL_PRCM_PHY_MEM_DP_S_LMEM1 = 9U,
PMHAL_PRCM_PHY_MEM_VPDMA_BUF10 = 10U,
PMHAL_PRCM_PHY_MEM_VPDMA_BUF11 = 11U,
PMHAL_PRCM_PHY_MEM_VPDMA_CDMA_SMEM = 12U,
PMHAL_PRCM_PHY_MEM_VPDMA_LM_PMEM = 13U,
PMHAL_PRCM_PHY_MEM_GFX = 14U,
PMHAL_PRCM_PHY_MEM_MPU_L1 = 15U,
PMHAL_PRCM_PHY_MEM_MPU_L2 = 16U,
PMHAL_PRCM_PHY_MEM_MPU_RAM = 17U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_CPPI = 18U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_RX_ADDR = 19U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_RX_DB = 20U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_RX_INFO = 21U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_RX_ST = 22U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_STATE = 23U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_STATISTICS = 24U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_TX_DB = 25U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_TX_INFO = 26U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_TX_ST = 27U,
PMHAL_PRCM_PHY_MEM_DMA_CRYPTO = 28U,
PMHAL_PRCM_PHY_MEM_MSHSI2COCP = 29U,
PMHAL_PRCM_PHY_MEM_DMEM0 = 30U,
PMHAL_PRCM_PHY_MEM_DMEM1 = 31U,
PMHAL_PRCM_PHY_MEM_DMEM2 = 32U,
PMHAL_PRCM_PHY_MEM_DMEM3 = 33U,
PMHAL_PRCM_PHY_MEM_IMEM0 = 34U,
PMHAL_PRCM_PHY_MEM_IMEM1 = 35U,
PMHAL_PRCM_PHY_MEM_IMEM2 = 36U,
PMHAL_PRCM_PHY_MEM_IMEM3 = 37U,
PMHAL_PRCM_PHY_MEM_PRUSS0 = 38U,
PMHAL_PRCM_PHY_MEM_PRUSS1 = 39U,
PMHAL_PRCM_PHY_MEM_LCD_CORE_PALETTE_RAM = 40U,
PMHAL_PRCM_PHY_MEM_LCD_DMA_FIFO_RAM = 41U,
PMHAL_PRCM_PHY_MEM_MBOXSRAM = 42U,
PMHAL_PRCM_PHY_MEM_MSTR_EXPS = 43U,
PMHAL_PRCM_PHY_MEM_TPCC = 44U,
PMHAL_PRCM_PHY_MEM_TPTC0 = 45U,
PMHAL_PRCM_PHY_MEM_TPTC1 = 46U,
PMHAL_PRCM_PHY_MEM_TPTC2 = 47U,
PMHAL_PRCM_PHY_MEM_USB = 48U,
PMHAL_PRCM_PHY_MEM_DEBUGSS = 49U,
PMHAL_PRCM_PHY_MEM_MAX = PMHAL_PRCM_PHY_MEM_DEBUGSS,
PMHAL_PRCM_PHY_MEM_COUNT = PMHAL_PRCM_PHY_MEM_MAX + 1U,
PMHAL_PRCM_PHY_MEM_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_PHY_MEM_MIN = 0U,
PMHAL_PRCM_PHY_MEM_GFX = PMHAL_PRCM_PHY_MEM_MIN,
PMHAL_PRCM_PHY_MEM_MPU_L1 = 1U,
PMHAL_PRCM_PHY_MEM_MPU_L2 = 2U,
PMHAL_PRCM_PHY_MEM_MPU_RAM = 3U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_CPPI = 4U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_RX_ADDR = 5U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_RX_DB = 6U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_RX_INFO = 7U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_RX_ST = 8U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_STATE = 9U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_STATISTICS = 10U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_TX_DB = 11U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_TX_INFO = 12U,
PMHAL_PRCM_PHY_MEM_CPGMACSS_R_RAM_TX_ST = 13U,
PMHAL_PRCM_PHY_MEM_DSSMEM = 14U,
PMHAL_PRCM_PHY_MEM_MSHSI2COCP = 15U,
PMHAL_PRCM_PHY_MEM_DMEM0 = 16U,
PMHAL_PRCM_PHY_MEM_DMEM1 = 17U,
PMHAL_PRCM_PHY_MEM_DMEM2 = 18U,
PMHAL_PRCM_PHY_MEM_DMEM3 = 19U,
PMHAL_PRCM_PHY_MEM_IMEM0 = 20U,
PMHAL_PRCM_PHY_MEM_IMEM1 = 21U,
PMHAL_PRCM_PHY_MEM_IMEM2 = 22U,
PMHAL_PRCM_PHY_MEM_IMEM3 = 23U,
PMHAL_PRCM_PHY_MEM_PRUSS0 = 24U,
PMHAL_PRCM_PHY_MEM_PRUSS1 = 25U,
PMHAL_PRCM_PHY_MEM_LCD_CORE_PALETTE_RAM = 26U,
PMHAL_PRCM_PHY_MEM_LCD_DMA_FIFO_RAM = 27U,
PMHAL_PRCM_PHY_MEM_UART = 28U,
PMHAL_PRCM_PHY_MEM_MBOXSRAM = 29U,
PMHAL_PRCM_PHY_MEM_MSTR_EXPS = 30U,
PMHAL_PRCM_PHY_MEM_BANK1 = 31U,
PMHAL_PRCM_PHY_MEM_BANK2 = 32U,
PMHAL_PRCM_PHY_MEM_PKA = 33U,
PMHAL_PRCM_PHY_MEM_TPCC = 34U,
PMHAL_PRCM_PHY_MEM_TPTC0 = 35U,
PMHAL_PRCM_PHY_MEM_TPTC1 = 36U,
PMHAL_PRCM_PHY_MEM_TPTC2 = 37U,
PMHAL_PRCM_PHY_MEM_USB = 38U,
PMHAL_PRCM_PHY_MEM_WB0 = 39U,
PMHAL_PRCM_PHY_MEM_WB1 = 40U,
PMHAL_PRCM_PHY_MEM_DEBUGSS = 41U,
PMHAL_PRCM_PHY_MEM_MAX = PMHAL_PRCM_PHY_MEM_DEBUGSS,
PMHAL_PRCM_PHY_MEM_COUNT = PMHAL_PRCM_PHY_MEM_MAX + 1U,
PMHAL_PRCM_PHY_MEM_UNDEF = 0x7FFFFFFFU
} |
| | Physical Memories. More...
|
| |
| enum | pmhalPrcmPhyMemBankId {
PMHAL_PRCM_PHY_BANK_VIP = 0U,
PMHAL_PRCM_PHY_BANK_MIN = PMHAL_PRCM_PHY_BANK_VIP,
PMHAL_PRCM_PHY_BANK_CORE_OTHER_BANK = 1U,
PMHAL_PRCM_PHY_BANK_OCP_NRET_BANK = 2U,
PMHAL_PRCM_PHY_BANK_CORE_OCMRAM = 3U,
PMHAL_PRCM_PHY_BANK_IPU_L2RAM = 4U,
PMHAL_PRCM_PHY_BANK_IPU_UNICACHE = 5U,
PMHAL_PRCM_PHY_BANK_DSP1_EDMA = 6U,
PMHAL_PRCM_PHY_BANK_DSP1_L1 = 7U,
PMHAL_PRCM_PHY_BANK_DSP1_L2 = 8U,
PMHAL_PRCM_PHY_BANK_DSP2_EDMA = 9U,
PMHAL_PRCM_PHY_BANK_DSP2_L1 = 10U,
PMHAL_PRCM_PHY_BANK_DSP2_L2 = 11U,
PMHAL_PRCM_PHY_BANK_DSS_MEM = 12U,
PMHAL_PRCM_PHY_BANK_EMU_BANK = 13U,
PMHAL_PRCM_PHY_BANK_EVE1_BANK = 14U,
PMHAL_PRCM_PHY_BANK_EVE2_BANK = 15U,
PMHAL_PRCM_PHY_BANK_EVE3_BANK = 16U,
PMHAL_PRCM_PHY_BANK_EVE4_BANK = 17U,
PMHAL_PRCM_PHY_BANK_GPU_MEM = 18U,
PMHAL_PRCM_PHY_BANK_AESSMEM = 19U,
PMHAL_PRCM_PHY_BANK_PERIPHMEM = 20U,
PMHAL_PRCM_PHY_BANK_HWA_MEM = 21U,
PMHAL_PRCM_PHY_BANK_TCM_1_MEM = 22U,
PMHAL_PRCM_PHY_BANK_TCM_2_MEM = 23U,
PMHAL_PRCM_PHY_BANK_SL2_MEM = 24U,
PMHAL_PRCM_PHY_BANK_L3INIT_BANK1 = 25U,
PMHAL_PRCM_PHY_BANK_L3INIT_BANK2 = 26U,
PMHAL_PRCM_PHY_BANK_GMAC_BANK = 27U,
PMHAL_PRCM_PHY_BANK_RETAINED_BANK = 28U,
PMHAL_PRCM_PHY_BANK_NONRETAINED_BANK = 29U,
PMHAL_PRCM_PHY_BANK_MPU_L2 = 30U,
PMHAL_PRCM_PHY_BANK_MPU_RAM = 31U,
PMHAL_PRCM_PHY_BANK_VPE_BANK = 32U,
PMHAL_PRCM_PHY_BANK_WKUP_BANK = 33U,
PMHAL_PRCM_PHY_BANK_MAX = PMHAL_PRCM_PHY_BANK_WKUP_BANK,
PMHAL_PRCM_PHY_BANK_COUNT = PMHAL_PRCM_PHY_BANK_MAX + 1U,
PMHAL_PRCM_PHY_BANK_VIP = 0U,
PMHAL_PRCM_PHY_BANK_MIN = PMHAL_PRCM_PHY_BANK_VIP,
PMHAL_PRCM_PHY_BANK_CORE_OTHER_BANK = 1U,
PMHAL_PRCM_PHY_BANK_OCP_NRET_BANK = 2U,
PMHAL_PRCM_PHY_BANK_CORE_OCMRAM = 3U,
PMHAL_PRCM_PHY_BANK_IPU_L2RAM = 4U,
PMHAL_PRCM_PHY_BANK_IPU_UNICACHE = 5U,
PMHAL_PRCM_PHY_BANK_DSP1_EDMA = 6U,
PMHAL_PRCM_PHY_BANK_DSP1_L1 = 7U,
PMHAL_PRCM_PHY_BANK_DSP1_L2 = 8U,
PMHAL_PRCM_PHY_BANK_DSP2_EDMA = 9U,
PMHAL_PRCM_PHY_BANK_DSP2_L1 = 10U,
PMHAL_PRCM_PHY_BANK_DSP2_L2 = 11U,
PMHAL_PRCM_PHY_BANK_DSS_MEM = 12U,
PMHAL_PRCM_PHY_BANK_EMU_BANK = 13U,
PMHAL_PRCM_PHY_BANK_EVE1_BANK = 14U,
PMHAL_PRCM_PHY_BANK_EVE2_BANK = 15U,
PMHAL_PRCM_PHY_BANK_EVE3_BANK = 16U,
PMHAL_PRCM_PHY_BANK_EVE4_BANK = 17U,
PMHAL_PRCM_PHY_BANK_GPU_MEM = 18U,
PMHAL_PRCM_PHY_BANK_AESSMEM = 19U,
PMHAL_PRCM_PHY_BANK_PERIPHMEM = 20U,
PMHAL_PRCM_PHY_BANK_HWA_MEM = 21U,
PMHAL_PRCM_PHY_BANK_TCM_1_MEM = 22U,
PMHAL_PRCM_PHY_BANK_TCM_2_MEM = 23U,
PMHAL_PRCM_PHY_BANK_SL2_MEM = 24U,
PMHAL_PRCM_PHY_BANK_L3INIT_BANK1 = 25U,
PMHAL_PRCM_PHY_BANK_L3INIT_BANK2 = 26U,
PMHAL_PRCM_PHY_BANK_GMAC_BANK = 27U,
PMHAL_PRCM_PHY_BANK_RETAINED_BANK = 28U,
PMHAL_PRCM_PHY_BANK_NONRETAINED_BANK = 29U,
PMHAL_PRCM_PHY_BANK_MPU_L2 = 30U,
PMHAL_PRCM_PHY_BANK_MPU_RAM = 31U,
PMHAL_PRCM_PHY_BANK_VPE_BANK = 32U,
PMHAL_PRCM_PHY_BANK_WKUP_BANK = 33U,
PMHAL_PRCM_PHY_BANK_MAX = PMHAL_PRCM_PHY_BANK_WKUP_BANK,
PMHAL_PRCM_PHY_BANK_COUNT = PMHAL_PRCM_PHY_BANK_MAX + 1U,
PMHAL_PRCM_PHY_BANK_VIP = 0U,
PMHAL_PRCM_PHY_BANK_MIN = PMHAL_PRCM_PHY_BANK_VIP,
PMHAL_PRCM_PHY_BANK_CORE_OTHER_BANK = 1U,
PMHAL_PRCM_PHY_BANK_OCP_NRET_BANK = 2U,
PMHAL_PRCM_PHY_BANK_CORE_OCMRAM = 3U,
PMHAL_PRCM_PHY_BANK_IPU_L2RAM = 4U,
PMHAL_PRCM_PHY_BANK_IPU_UNICACHE = 5U,
PMHAL_PRCM_PHY_BANK_DSP1_EDMA = 6U,
PMHAL_PRCM_PHY_BANK_DSP1_L1 = 7U,
PMHAL_PRCM_PHY_BANK_DSP1_L2 = 8U,
PMHAL_PRCM_PHY_BANK_DSP2_EDMA = 9U,
PMHAL_PRCM_PHY_BANK_DSP2_L1 = 10U,
PMHAL_PRCM_PHY_BANK_DSP2_L2 = 11U,
PMHAL_PRCM_PHY_BANK_DSS_MEM = 12U,
PMHAL_PRCM_PHY_BANK_EMU_BANK = 13U,
PMHAL_PRCM_PHY_BANK_EVE1_BANK = 14U,
PMHAL_PRCM_PHY_BANK_AESSMEM = 15U,
PMHAL_PRCM_PHY_BANK_PERIPHMEM = 16U,
PMHAL_PRCM_PHY_BANK_L3INIT_BANK1 = 17U,
PMHAL_PRCM_PHY_BANK_L3INIT_BANK2 = 18U,
PMHAL_PRCM_PHY_BANK_GMAC_BANK = 19U,
PMHAL_PRCM_PHY_BANK_RETAINED_BANK = 20U,
PMHAL_PRCM_PHY_BANK_NONRETAINED_BANK = 21U,
PMHAL_PRCM_PHY_BANK_ISS_BANK = 22U,
PMHAL_PRCM_PHY_BANK_WKUP_BANK = 23U,
PMHAL_PRCM_PHY_BANK_MAX = PMHAL_PRCM_PHY_BANK_WKUP_BANK,
PMHAL_PRCM_PHY_BANK_COUNT = PMHAL_PRCM_PHY_BANK_MAX + 1U,
PMHAL_PRCM_PHY_BANK_GFX_MEM = 0U,
PMHAL_PRCM_PHY_BANK_MIN = PMHAL_PRCM_PHY_BANK_GFX_MEM,
PMHAL_PRCM_PHY_BANK_MPU_L1 = 1U,
PMHAL_PRCM_PHY_BANK_MPU_L2 = 2U,
PMHAL_PRCM_PHY_BANK_MPU_RAM = 3U,
PMHAL_PRCM_PHY_BANK_PER_MEM = 4U,
PMHAL_PRCM_PHY_BANK_ICSS_MEM = 5U,
PMHAL_PRCM_PHY_BANK_RAM_MEM = 6U,
PMHAL_PRCM_PHY_BANK_DEBUGSS_MEM = 7U,
PMHAL_PRCM_PHY_BANK_MAX = PMHAL_PRCM_PHY_BANK_DEBUGSS_MEM,
PMHAL_PRCM_PHY_BANK_COUNT = PMHAL_PRCM_PHY_BANK_MAX + 1U,
PMHAL_PRCM_PHY_BANK_GFX_MEM = 0U,
PMHAL_PRCM_PHY_BANK_MIN = PMHAL_PRCM_PHY_BANK_GFX_MEM,
PMHAL_PRCM_PHY_BANK_MPU_L1 = 1U,
PMHAL_PRCM_PHY_BANK_MPU_L2 = 2U,
PMHAL_PRCM_PHY_BANK_MPU_RAM = 3U,
PMHAL_PRCM_PHY_BANK_PER_MEM = 4U,
PMHAL_PRCM_PHY_BANK_ICSS_MEM = 5U,
PMHAL_PRCM_PHY_BANK_RAM1_MEM = 6U,
PMHAL_PRCM_PHY_BANK_RAM2_MEM = 7U,
PMHAL_PRCM_PHY_BANK_DEBUGSS_MEM = 8U,
PMHAL_PRCM_PHY_BANK_MAX = PMHAL_PRCM_PHY_BANK_DEBUGSS_MEM,
PMHAL_PRCM_PHY_BANK_COUNT = PMHAL_PRCM_PHY_BANK_MAX + 1U
} |
| | Physical Memory Bank. More...
|
| |
| enum | pmhalPrcmSysConfigModuleId {
PMHAL_PRCM_SYSCFG_LOWER_BOUND = (-(int32_t)1),
PMHAL_PRCM_SYSCFG_COUNT,
PMHAL_PRCM_SYSCFG_NOTAPPLICABLE,
PMHAL_PRCM_SYSCFG_LOWER_BOUND = (-(int32_t)1),
PMHAL_PRCM_SYSCFG_COUNT,
PMHAL_PRCM_SYSCFG_NOTAPPLICABLE,
PMHAL_PRCM_SYSCFG_LOWER_BOUND = (-(int32_t)1),
PMHAL_PRCM_SYSCFG_COUNT,
PMHAL_PRCM_SYSCFG_NOTAPPLICABLE,
PMHAL_PRCM_SYSCFG_LOWER_BOUND = -1,
PMHAL_PRCM_SYSCFG_COUNT,
PMHAL_PRCM_SYSCFG_NOTAPPLICABLE,
PMHAL_PRCM_SYSCFG_LOWER_BOUND = -1,
PMHAL_PRCM_SYSCFG_COUNT,
PMHAL_PRCM_SYSCFG_NOTAPPLICABLE
} |
| | Enum defining modules with SysConfig. More...
|
| |
| enum | pmhalCtrlMdlPostDivIdx {
PMHAL_CTRL_POSTDIV_MIN = 0U,
PMHAL_CTRL_POSTDIV_MAX = PMHAL_CTRL_POSTDIV_MIN,
PMHAL_CTRL_POSTDIV_COUNT = PMHAL_CTRL_POSTDIV_MAX + 1U,
PMHAL_CTRL_POSTDIV_NOTAPPLICABLE = 0xFFU,
PMHAL_CTRL_POSTDIV_MIN = 0U,
PMHAL_CTRL_POSTDIV_MAX = PMHAL_CTRL_POSTDIV_MIN,
PMHAL_CTRL_POSTDIV_COUNT = PMHAL_CTRL_POSTDIV_MAX + 1U,
PMHAL_CTRL_POSTDIV_NOTAPPLICABLE = 0xFFU,
PMHAL_CTRL_POSTDIV_DPLL_EVE_VID_DSP_M2 = 0U,
PMHAL_CTRL_POSTDIV_MIN = PMHAL_CTRL_POSTDIV_DPLL_EVE_VID_DSP_M2,
PMHAL_CTRL_POSTDIV_DPLL_PER_H14 = 1U,
PMHAL_CTRL_POSTDIV_DPLL_CORE_H11 = 2U,
PMHAL_CTRL_POSTDIV_DPLL_CORE_H13 = 3U,
PMHAL_CTRL_POSTDIV_DPLL_CORE_H21 = 4U,
PMHAL_CTRL_POSTDIV_DPLL_DSP_GMAC_H14 = 5U,
PMHAL_CTRL_POSTDIV_MAX = PMHAL_CTRL_POSTDIV_DPLL_DSP_GMAC_H14,
PMHAL_CTRL_POSTDIV_COUNT = PMHAL_CTRL_POSTDIV_MAX + 1U,
PMHAL_CTRL_POSTDIV_NOTAPPLICABLE = 0xFFU,
PMHAL_CTRL_POSTDIV_MIN = 0U,
PMHAL_CTRL_POSTDIV_MAX = PMHAL_CTRL_POSTDIV_MIN,
PMHAL_CTRL_POSTDIV_COUNT = PMHAL_CTRL_POSTDIV_MAX + 1U,
PMHAL_CTRL_POSTDIV_NOTAPPLICABLE = 0xFFU,
PMHAL_CTRL_POSTDIV_MIN = 0U,
PMHAL_CTRL_POSTDIV_MAX = PMHAL_CTRL_POSTDIV_MIN,
PMHAL_CTRL_POSTDIV_COUNT = PMHAL_CTRL_POSTDIV_MAX + 1U,
PMHAL_CTRL_POSTDIV_NOTAPPLICABLE = 0xFFU
} |
| | control module configured postdividers More...
|
| |
| enum | pmhalPrcmNodeId {
PMHAL_PRCM_ROOT_CLK_MIN = 0U,
PMHAL_PRCM_ROOT_CLK_PCIESREF_ACS = PMHAL_PRCM_ROOT_CLK_MIN,
PMHAL_PRCM_NODE_MIN = PMHAL_PRCM_ROOT_CLK_MIN,
PMHAL_PRCM_ROOT_CLK_RMII = 1U,
PMHAL_PRCM_ROOT_CLK_SYS_32K = 2U,
PMHAL_PRCM_ROOT_CLK_SYS_CLKIN1 = 3U,
PMHAL_PRCM_ROOT_CLK_SYS_CLKIN2 = 4U,
PMHAL_PRCM_ROOT_CLK_BOARD_MAX = PMHAL_PRCM_ROOT_CLK_SYS_CLKIN2,
PMHAL_PRCM_ROOT_CLK_EMU_CLKIN = 5U,
PMHAL_PRCM_ROOT_CLK_REF_CLKIN0 = 6U,
PMHAL_PRCM_ROOT_CLK_REF_CLKIN1 = 7U,
PMHAL_PRCM_ROOT_CLK_REF_CLKIN2 = 8U,
PMHAL_PRCM_ROOT_CLK_REF_CLKIN3 = 9U,
PMHAL_PRCM_ROOT_CLK_SATA_CLKIN = 10U,
PMHAL_PRCM_ROOT_CLK_SDVENC_CLKIN = 11U,
PMHAL_PRCM_ROOT_CLK_USB_OTG_CLKIN = 12U,
PMHAL_PRCM_ROOT_CLK_ATLCLKIN3 = 13U,
PMHAL_PRCM_ROOT_CLK_ATL_CLKIN0 = 14U,
PMHAL_PRCM_ROOT_CLK_ATL_CLKIN1 = 15U,
PMHAL_PRCM_ROOT_CLK_ATL_CLKIN2 = 16U,
PMHAL_PRCM_ROOT_CLK_MLBP_CLKIN = 17U,
PMHAL_PRCM_ROOT_CLK_MLB_CLKIN = 18U,
PMHAL_PRCM_ROOT_CLK_SECURE_32K_CLK_SRC = 19U,
PMHAL_PRCM_ROOT_CLK_VIDEO1_CLKIN = 20U,
PMHAL_PRCM_ROOT_CLK_VIDEO1_M2_CLKIN = 21U,
PMHAL_PRCM_ROOT_CLK_VIDEO2_CLKIN = 22U,
PMHAL_PRCM_ROOT_CLK_VIDEO2_M2_CLKIN = 23U,
PMHAL_PRCM_ROOT_CLK_HDMI_CLKIN = 24U,
PMHAL_PRCM_ROOT_CLK_MAX = PMHAL_PRCM_ROOT_CLK_HDMI_CLKIN,
PMHAL_PRCM_ROOT_CLK_COUNT = PMHAL_PRCM_ROOT_CLK_MAX + 1U,
PMHAL_PRCM_MUX_ATL_DPLL_CLK_MUX = 25U,
PMHAL_PRCM_MUX_MIN = PMHAL_PRCM_MUX_ATL_DPLL_CLK_MUX,
PMHAL_PRCM_MUX_ATL_GFCLK_MUX = 26U,
PMHAL_PRCM_MUX_IPU1_GFCLK_MUX = 27U,
PMHAL_PRCM_MUX_ADC_GFCLK_MUX = 28U,
PMHAL_PRCM_MUX_EVE_GCLK_MUX = 29U,
PMHAL_PRCM_MUX_GPU_CORE_GCLK_MUX = 30U,
PMHAL_PRCM_MUX_GPU_HYD_GCLK_MUX = 31U,
PMHAL_PRCM_MUX_QSPI_GFCLK_MUX = 32U,
PMHAL_PRCM_MUX_VIP1_GCLK_MUX = 33U,
PMHAL_PRCM_MUX_VIP2_GCLK_MUX = 34U,
PMHAL_PRCM_MUX_VIP3_GCLK_MUX = 35U,
PMHAL_PRCM_MUX_CLKOUTMUX0_CLK_MUX = 36U,
PMHAL_PRCM_MUX_CLKOUTMUX1_CLK_MUX = 37U,
PMHAL_PRCM_MUX_CLKOUTMUX2_CLK_MUX = 38U,
PMHAL_PRCM_MUX_MMC1_FCLK_MUX = 39U,
PMHAL_PRCM_MUX_MMC2_FCLK_MUX = 40U,
PMHAL_PRCM_MUX_GMAC_RFT_CLK_MUX = 41U,
PMHAL_PRCM_MUX_MMC3_GFCLK_MUX = 42U,
PMHAL_PRCM_MUX_MMC4_GFCLK_MUX = 43U,
PMHAL_PRCM_MUX_RMII_REF_CLK_MUX = 44U,
PMHAL_PRCM_MUX_MCASP1_AUX_GFCLK_MUX = 45U,
PMHAL_PRCM_MUX_MCASP2_AUX_GFCLK_MUX = 46U,
PMHAL_PRCM_MUX_MCASP3_AUX_GFCLK_MUX = 47U,
PMHAL_PRCM_MUX_MCASP4_AUX_GFCLK_MUX = 48U,
PMHAL_PRCM_MUX_MCASP5_AUX_GFCLK_MUX = 49U,
PMHAL_PRCM_MUX_MCASP6_AUX_GFCLK_MUX = 50U,
PMHAL_PRCM_MUX_MCASP7_AUX_GFCLK_MUX = 51U,
PMHAL_PRCM_MUX_MCASP8_AUX_GFCLK_MUX = 52U,
PMHAL_PRCM_MUX_MCASP1_AHCLKR_MUX = 53U,
PMHAL_PRCM_MUX_MCASP1_AHCLKX_MUX = 54U,
PMHAL_PRCM_MUX_MCASP2_AHCLKR_MUX = 55U,
PMHAL_PRCM_MUX_MCASP2_AHCLKX_MUX = 56U,
PMHAL_PRCM_MUX_MCASP3_AHCLKX_MUX = 57U,
PMHAL_PRCM_MUX_MCASP4_AHCLKX_MUX = 58U,
PMHAL_PRCM_MUX_MCASP5_AHCLKX_MUX = 59U,
PMHAL_PRCM_MUX_MCASP6_AHCLKX_MUX = 60U,
PMHAL_PRCM_MUX_MCASP7_AHCLKX_MUX = 61U,
PMHAL_PRCM_MUX_MCASP8_AHCLKX_MUX = 62U,
PMHAL_PRCM_MUX_TIMER5_GFCLK_MUX = 63U,
PMHAL_PRCM_MUX_TIMER6_GFCLK_MUX = 64U,
PMHAL_PRCM_MUX_TIMER7_GFCLK_MUX = 65U,
PMHAL_PRCM_MUX_TIMER8_GFCLK_MUX = 66U,
PMHAL_PRCM_MUX_TIMER1_GFCLK_MUX = 67U,
PMHAL_PRCM_MUX_TIMER2_GFCLK_MUX = 68U,
PMHAL_PRCM_MUX_TIMER3_GFCLK_MUX = 69U,
PMHAL_PRCM_MUX_TIMER4_GFCLK_MUX = 70U,
PMHAL_PRCM_MUX_TIMER10_GFCLK_MUX = 71U,
PMHAL_PRCM_MUX_TIMER11_GFCLK_MUX = 72U,
PMHAL_PRCM_MUX_TIMER9_GFCLK_MUX = 73U,
PMHAL_PRCM_MUX_TIMER13_GFCLK_MUX = 74U,
PMHAL_PRCM_MUX_TIMER14_GFCLK_MUX = 75U,
PMHAL_PRCM_MUX_TIMER15_GFCLK_MUX = 76U,
PMHAL_PRCM_MUX_TIMER16_GFCLK_MUX = 77U,
PMHAL_PRCM_MUX_UART10_GFCLK_MUX = 78U,
PMHAL_PRCM_MUX_UART1_GFCLK_MUX = 79U,
PMHAL_PRCM_MUX_UART2_GFCLK_MUX = 80U,
PMHAL_PRCM_MUX_UART3_GFCLK_MUX = 81U,
PMHAL_PRCM_MUX_UART4_GFCLK_MUX = 82U,
PMHAL_PRCM_MUX_UART5_GFCLK_MUX = 83U,
PMHAL_PRCM_MUX_UART6_GFCLK_MUX = 84U,
PMHAL_PRCM_MUX_UART7_GFCLK_MUX = 85U,
PMHAL_PRCM_MUX_UART8_GFCLK_MUX = 86U,
PMHAL_PRCM_MUX_UART9_GFCLK_MUX = 87U,
PMHAL_PRCM_MUX_ABE_DPLL_BYPAS_CLK_MUX = 88U,
PMHAL_PRCM_MUX_ABE_DPLL_REF_CLK_MUX = 89U,
PMHAL_PRCM_MUX_ABE_DPLL_SYS_CLK_MUX = 90U,
PMHAL_PRCM_MUX_DCAN1_SYS_CLK_MUX = 91U,
PMHAL_PRCM_MUX_WKUPAON_ICLK_MUX = 92U,
PMHAL_PRCM_MUX_HDMI_DPLL_CLK_MUX = 93U,
PMHAL_PRCM_MUX_VIDEO1_DPLL_CLK_MUX = 94U,
PMHAL_PRCM_MUX_VIDEO2_DPLL_CLK_MUX = 95U,
PMHAL_PRCM_MUX_FUNC_32K_CLK_MUX = 96U,
PMHAL_PRCM_MUX_VPE_GCLK_MUX = 97U,
PMHAL_PRCM_MUX_MAX = PMHAL_PRCM_MUX_VPE_GCLK_MUX,
PMHAL_PRCM_MUX_COUNT = PMHAL_PRCM_MUX_MAX + 1U,
PMHAL_PRCM_DIV_ABE_24M_FCLK = 98U,
PMHAL_PRCM_DIV_MIN = PMHAL_PRCM_DIV_ABE_24M_FCLK,
PMHAL_PRCM_DIV_ABE_LP_CLK = 99U,
PMHAL_PRCM_DIV_DSP_DPLL_HS_CLK = 100U,
PMHAL_PRCM_DIV_EVE_DPLL_HS_CLK = 101U,
PMHAL_PRCM_DIV_FUNC_24M_CLK = 102U,
PMHAL_PRCM_DIV_IVA_DPLL_HS_CLK = 103U,
PMHAL_PRCM_DIV_L3_ICLK = 104U,
PMHAL_PRCM_DIV_L4_ROOT_CLK = 105U,
PMHAL_PRCM_DIV_MPU_DPLL_HS_CLK = 106U,
PMHAL_PRCM_DIV_PER_DPLL_HS_CLK = 107U,
PMHAL_PRCM_DIV_USB_DPLL_HS_CLK = 108U,
PMHAL_PRCM_DIV_ABE_CLK = 109U,
PMHAL_PRCM_DIV_ABE_GICLK = 110U,
PMHAL_PRCM_DIV_AESS_FCLK = 111U,
PMHAL_PRCM_DIV_FUNC_128M_CLK_MUX = 112U,
PMHAL_PRCM_DIV_QSPI_GFCLK = 113U,
PMHAL_PRCM_DIV_CORE_DPLL_OUT_DCLK = 114U,
PMHAL_PRCM_DIV_DSP_GCLK = 115U,
PMHAL_PRCM_DIV_EMIF_PHY_DCLK = 116U,
PMHAL_PRCM_DIV_EMU_DCLK = 117U,
PMHAL_PRCM_DIV_EVE_DCLK = 118U,
PMHAL_PRCM_DIV_FUNC_96M_AON_DCLK = 119U,
PMHAL_PRCM_DIV_GMAC_250M_DCLK = 120U,
PMHAL_PRCM_DIV_GPU_DCLK = 121U,
PMHAL_PRCM_DIV_HDMI_DCLK = 122U,
PMHAL_PRCM_DIV_IVA_DCLK = 123U,
PMHAL_PRCM_DIV_L3INIT_480M_DCLK = 124U,
PMHAL_PRCM_DIV_MPU_DCLK = 125U,
PMHAL_PRCM_DIV_PCIE2_DCLK = 126U,
PMHAL_PRCM_DIV_PCIE_DCLK = 127U,
PMHAL_PRCM_DIV_PER_ABE_X1_DCLK = 128U,
PMHAL_PRCM_DIV_SATA_DCLK = 129U,
PMHAL_PRCM_DIV_SECURE_32K_DCLK = 130U,
PMHAL_PRCM_DIV_SYS_CLK1_DCLK = 131U,
PMHAL_PRCM_DIV_SYS_CLK2_DCLK = 132U,
PMHAL_PRCM_DIV_USB_OTG_DCLK = 133U,
PMHAL_PRCM_DIV_VIDEO1_DCLK = 134U,
PMHAL_PRCM_DIV_VIDEO2_DCLK = 135U,
PMHAL_PRCM_DIV_FUNC_12M_FCLK = 136U,
PMHAL_PRCM_DIV_FUNC_48M_FCLK = 137U,
PMHAL_PRCM_DIV_FUNC_96M_FCLK = 138U,
PMHAL_PRCM_DIV_MMC1_FCLK = 139U,
PMHAL_PRCM_DIV_MMC2_FCLK = 140U,
PMHAL_PRCM_DIV_L3INIT_60M_FCLK = 141U,
PMHAL_PRCM_DIV_GMAC_GMII_REF_CLK = 142U,
PMHAL_PRCM_DIV_GMII_M_CLK = 143U,
PMHAL_PRCM_DIV_MMC3_GFCLK = 144U,
PMHAL_PRCM_DIV_MMC4_GFCLK = 145U,
PMHAL_PRCM_DIV_RGMII_5M_REF_CLK = 146U,
PMHAL_PRCM_DIV_HDMI_CLK2 = 147U,
PMHAL_PRCM_DIV_PER_ABE_X1_GFCLK2 = 148U,
PMHAL_PRCM_DIV_VIDEO1_CLK2 = 149U,
PMHAL_PRCM_DIV_VIDEO2_CLK2 = 150U,
PMHAL_PRCM_DIV_MLBP_CLK = 151U,
PMHAL_PRCM_DIV_MLB_CLK = 152U,
PMHAL_PRCM_DIV_HDMI_CLK = 153U,
PMHAL_PRCM_DIV_VIDEO1_CLK = 154U,
PMHAL_PRCM_DIV_VIDEO2_CLK = 155U,
PMHAL_PRCM_DIV_CUSTEFUSE_SYS_GFCLK = 156U,
PMHAL_PRCM_DIV_ABE_SYS_CLK = 157U,
PMHAL_PRCM_DIV_L3INSTR_TS_GCLK = 158U,
PMHAL_PRCM_DIV_TIMER_SYS_CLK = 159U,
PMHAL_PRCM_DIV_IPU1_GCLK = 160U,
PMHAL_PRCM_DIV_IPU2_GCLK = 161U,
PMHAL_PRCM_DIV_FUNC_32K_CLK = 162U,
PMHAL_PRCM_DIV_VPE_GCLK = 163U,
PMHAL_PRCM_DIV_MAX = PMHAL_PRCM_DIV_VPE_GCLK,
PMHAL_PRCM_DIV_COUNT = PMHAL_PRCM_DIV_MAX + 1U,
PMHAL_PRCM_DPLL_APLL_PCIE = 164U,
PMHAL_PRCM_DPLL_MIN = PMHAL_PRCM_DPLL_APLL_PCIE,
PMHAL_PRCM_DPLL_ABE = 165U,
PMHAL_PRCM_DPLL_CORE = 166U,
PMHAL_PRCM_DPLL_DDR = 167U,
PMHAL_PRCM_DPLL_GMAC = 168U,
PMHAL_PRCM_DPLL_GPU = 169U,
PMHAL_PRCM_DPLL_IVA = 170U,
PMHAL_PRCM_DPLL_PCIE_REF = 171U,
PMHAL_PRCM_DPLL_PER = 172U,
PMHAL_PRCM_DPLL_USB = 173U,
PMHAL_PRCM_DPLL_DSP = 174U,
PMHAL_PRCM_DPLL_EVE = 175U,
PMHAL_PRCM_DPLL_MPU = 176U,
PMHAL_PRCM_DPLL_MAX = PMHAL_PRCM_DPLL_MPU,
PMHAL_PRCM_DPLL_COUNT = PMHAL_PRCM_DPLL_MAX + 1U,
PMHAL_PRCM_VIDEOPLL_VIDEO1 = 177U,
PMHAL_PRCM_VIDEOPLL_MIN = PMHAL_PRCM_VIDEOPLL_VIDEO1,
PMHAL_PRCM_VIDEOPLL_VIDEO2 = 178U,
PMHAL_PRCM_VIDEOPLL_HDMI = 179U
, PMHAL_PRCM_VIDEOPLL_COUNT = PMHAL_PRCM_VIDEOPLL_MAX + 1U,
PMHAL_PRCM_NODE_MAX = PMHAL_PRCM_VIDEOPLL_MAX,
PMHAL_PRCM_NODE_COUNT = PMHAL_PRCM_VIDEOPLL_COUNT,
PMHAL_PRCM_ROOT_CLK_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_MUX_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DIV_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_NODE_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_VIDEOPLL_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_ROOT_CLK_MIN = 0U,
PMHAL_PRCM_ROOT_CLK_PCIESREF_ACS = PMHAL_PRCM_ROOT_CLK_MIN,
PMHAL_PRCM_NODE_MIN = PMHAL_PRCM_ROOT_CLK_MIN,
PMHAL_PRCM_ROOT_CLK_RMII = 1U,
PMHAL_PRCM_ROOT_CLK_SYS_32K = 2U,
PMHAL_PRCM_ROOT_CLK_SYS_CLKIN1 = 3U,
PMHAL_PRCM_ROOT_CLK_SYS_CLKIN2 = 4U,
PMHAL_PRCM_ROOT_CLK_BOARD_MAX = PMHAL_PRCM_ROOT_CLK_SYS_CLKIN2,
PMHAL_PRCM_ROOT_CLK_EMU_CLKIN = 5U,
PMHAL_PRCM_ROOT_CLK_REF_CLKIN0 = 6U,
PMHAL_PRCM_ROOT_CLK_REF_CLKIN1 = 7U,
PMHAL_PRCM_ROOT_CLK_REF_CLKIN2 = 8U,
PMHAL_PRCM_ROOT_CLK_REF_CLKIN3 = 9U,
PMHAL_PRCM_ROOT_CLK_SATA_CLKIN = 10U,
PMHAL_PRCM_ROOT_CLK_SDVENC_CLKIN = 11U,
PMHAL_PRCM_ROOT_CLK_USB_OTG_CLKIN = 12U,
PMHAL_PRCM_ROOT_CLK_ATLCLKIN3 = 13U,
PMHAL_PRCM_ROOT_CLK_ATL_CLKIN0 = 14U,
PMHAL_PRCM_ROOT_CLK_ATL_CLKIN1 = 15U,
PMHAL_PRCM_ROOT_CLK_ATL_CLKIN2 = 16U,
PMHAL_PRCM_ROOT_CLK_MLBP_CLKIN = 17U,
PMHAL_PRCM_ROOT_CLK_MLB_CLKIN = 18U,
PMHAL_PRCM_ROOT_CLK_SECURE_32K_CLK_SRC = 19U,
PMHAL_PRCM_ROOT_CLK_VIDEO1_CLKIN = 20U,
PMHAL_PRCM_ROOT_CLK_VIDEO1_M2_CLKIN = 21U,
PMHAL_PRCM_ROOT_CLK_HDMI_CLKIN = 22U,
PMHAL_PRCM_ROOT_CLK_MAX = PMHAL_PRCM_ROOT_CLK_HDMI_CLKIN,
PMHAL_PRCM_ROOT_CLK_COUNT = PMHAL_PRCM_ROOT_CLK_MAX + 1U,
PMHAL_PRCM_MUX_ATL_DPLL_CLK_MUX = 23U,
PMHAL_PRCM_MUX_MIN = PMHAL_PRCM_MUX_ATL_DPLL_CLK_MUX,
PMHAL_PRCM_MUX_ATL_GFCLK_MUX = 24U,
PMHAL_PRCM_MUX_IPU1_GFCLK_MUX = 25U,
PMHAL_PRCM_MUX_ADC_GFCLK_MUX = 26U,
PMHAL_PRCM_MUX_EVE_GCLK_MUX = 27U,
PMHAL_PRCM_MUX_GPU_CORE_GCLK_MUX = 28U,
PMHAL_PRCM_MUX_GPU_HYD_GCLK_MUX = 29U,
PMHAL_PRCM_MUX_QSPI_GFCLK_MUX = 30U,
PMHAL_PRCM_MUX_VIP1_GCLK_MUX = 31U,
PMHAL_PRCM_MUX_VIP2_GCLK_MUX = 32U,
PMHAL_PRCM_MUX_VIP3_GCLK_MUX = 33U,
PMHAL_PRCM_MUX_CLKOUTMUX0_CLK_MUX = 34U,
PMHAL_PRCM_MUX_CLKOUTMUX1_CLK_MUX = 35U,
PMHAL_PRCM_MUX_CLKOUTMUX2_CLK_MUX = 36U,
PMHAL_PRCM_MUX_MMC1_FCLK_MUX = 37U,
PMHAL_PRCM_MUX_MMC2_FCLK_MUX = 38U,
PMHAL_PRCM_MUX_GMAC_RFT_CLK_MUX = 39U,
PMHAL_PRCM_MUX_MMC3_GFCLK_MUX = 40U,
PMHAL_PRCM_MUX_MMC4_GFCLK_MUX = 41U,
PMHAL_PRCM_MUX_RMII_REF_CLK_MUX = 42U,
PMHAL_PRCM_MUX_MCASP1_AUX_GFCLK_MUX = 43U,
PMHAL_PRCM_MUX_MCASP2_AUX_GFCLK_MUX = 44U,
PMHAL_PRCM_MUX_MCASP3_AUX_GFCLK_MUX = 45U,
PMHAL_PRCM_MUX_MCASP4_AUX_GFCLK_MUX = 46U,
PMHAL_PRCM_MUX_MCASP5_AUX_GFCLK_MUX = 47U,
PMHAL_PRCM_MUX_MCASP6_AUX_GFCLK_MUX = 48U,
PMHAL_PRCM_MUX_MCASP7_AUX_GFCLK_MUX = 49U,
PMHAL_PRCM_MUX_MCASP8_AUX_GFCLK_MUX = 50U,
PMHAL_PRCM_MUX_MCASP1_AHCLKR_MUX = 51U,
PMHAL_PRCM_MUX_MCASP1_AHCLKX_MUX = 52U,
PMHAL_PRCM_MUX_MCASP2_AHCLKR_MUX = 53U,
PMHAL_PRCM_MUX_MCASP2_AHCLKX_MUX = 54U,
PMHAL_PRCM_MUX_MCASP3_AHCLKX_MUX = 55U,
PMHAL_PRCM_MUX_MCASP4_AHCLKX_MUX = 56U,
PMHAL_PRCM_MUX_MCASP5_AHCLKX_MUX = 57U,
PMHAL_PRCM_MUX_MCASP6_AHCLKX_MUX = 58U,
PMHAL_PRCM_MUX_MCASP7_AHCLKX_MUX = 59U,
PMHAL_PRCM_MUX_MCASP8_AHCLKX_MUX = 60U,
PMHAL_PRCM_MUX_TIMER5_GFCLK_MUX = 61U,
PMHAL_PRCM_MUX_TIMER6_GFCLK_MUX = 62U,
PMHAL_PRCM_MUX_TIMER7_GFCLK_MUX = 63U,
PMHAL_PRCM_MUX_TIMER8_GFCLK_MUX = 64U,
PMHAL_PRCM_MUX_TIMER1_GFCLK_MUX = 65U,
PMHAL_PRCM_MUX_TIMER2_GFCLK_MUX = 66U,
PMHAL_PRCM_MUX_TIMER3_GFCLK_MUX = 67U,
PMHAL_PRCM_MUX_TIMER4_GFCLK_MUX = 68U,
PMHAL_PRCM_MUX_TIMER10_GFCLK_MUX = 69U,
PMHAL_PRCM_MUX_TIMER11_GFCLK_MUX = 70U,
PMHAL_PRCM_MUX_TIMER9_GFCLK_MUX = 71U,
PMHAL_PRCM_MUX_TIMER13_GFCLK_MUX = 72U,
PMHAL_PRCM_MUX_TIMER14_GFCLK_MUX = 73U,
PMHAL_PRCM_MUX_TIMER15_GFCLK_MUX = 74U,
PMHAL_PRCM_MUX_TIMER16_GFCLK_MUX = 75U,
PMHAL_PRCM_MUX_UART10_GFCLK_MUX = 76U,
PMHAL_PRCM_MUX_UART1_GFCLK_MUX = 77U,
PMHAL_PRCM_MUX_UART2_GFCLK_MUX = 78U,
PMHAL_PRCM_MUX_UART3_GFCLK_MUX = 79U,
PMHAL_PRCM_MUX_UART4_GFCLK_MUX = 80U,
PMHAL_PRCM_MUX_UART5_GFCLK_MUX = 81U,
PMHAL_PRCM_MUX_UART6_GFCLK_MUX = 82U,
PMHAL_PRCM_MUX_UART7_GFCLK_MUX = 83U,
PMHAL_PRCM_MUX_UART8_GFCLK_MUX = 84U,
PMHAL_PRCM_MUX_UART9_GFCLK_MUX = 85U,
PMHAL_PRCM_MUX_ABE_DPLL_BYPAS_CLK_MUX = 86U,
PMHAL_PRCM_MUX_ABE_DPLL_REF_CLK_MUX = 87U,
PMHAL_PRCM_MUX_ABE_DPLL_SYS_CLK_MUX = 88U,
PMHAL_PRCM_MUX_DCAN1_SYS_CLK_MUX = 89U,
PMHAL_PRCM_MUX_WKUPAON_ICLK_MUX = 90U,
PMHAL_PRCM_MUX_HDMI_DPLL_CLK_MUX = 91U,
PMHAL_PRCM_MUX_VIDEO1_DPLL_CLK_MUX = 92U,
PMHAL_PRCM_MUX_VIDEO2_DPLL_CLK_MUX = 93U,
PMHAL_PRCM_MUX_FUNC_32K_CLK_MUX = 94U,
PMHAL_PRCM_MUX_VPE_GCLK_MUX = 95U,
PMHAL_PRCM_MUX_MAX = PMHAL_PRCM_MUX_VPE_GCLK_MUX,
PMHAL_PRCM_MUX_COUNT = PMHAL_PRCM_MUX_MAX + 1U,
PMHAL_PRCM_DIV_ABE_24M_FCLK = 96U,
PMHAL_PRCM_DIV_MIN = PMHAL_PRCM_DIV_ABE_24M_FCLK,
PMHAL_PRCM_DIV_ABE_LP_CLK = 97U,
PMHAL_PRCM_DIV_DSP_DPLL_HS_CLK = 98U,
PMHAL_PRCM_DIV_EVE_DPLL_HS_CLK = 99U,
PMHAL_PRCM_DIV_FUNC_24M_CLK = 100U,
PMHAL_PRCM_DIV_IVA_DPLL_HS_CLK = 101U,
PMHAL_PRCM_DIV_L3_ICLK = 102U,
PMHAL_PRCM_DIV_L4_ROOT_CLK = 103U,
PMHAL_PRCM_DIV_MPU_DPLL_HS_CLK = 104U,
PMHAL_PRCM_DIV_PER_DPLL_HS_CLK = 105U,
PMHAL_PRCM_DIV_USB_DPLL_HS_CLK = 106U,
PMHAL_PRCM_DIV_ABE_CLK = 107U,
PMHAL_PRCM_DIV_ABE_GICLK = 108U,
PMHAL_PRCM_DIV_AESS_FCLK = 109U,
PMHAL_PRCM_DIV_FUNC_128M_CLK_MUX = 110U,
PMHAL_PRCM_DIV_QSPI_GFCLK = 111U,
PMHAL_PRCM_DIV_CORE_DPLL_OUT_DCLK = 112U,
PMHAL_PRCM_DIV_DSP_GCLK = 113U,
PMHAL_PRCM_DIV_EMIF_PHY_DCLK = 114U,
PMHAL_PRCM_DIV_EMU_DCLK = 115U,
PMHAL_PRCM_DIV_EVE_DCLK = 116U,
PMHAL_PRCM_DIV_FUNC_96M_AON_DCLK = 117U,
PMHAL_PRCM_DIV_GMAC_250M_DCLK = 118U,
PMHAL_PRCM_DIV_GPU_DCLK = 119U,
PMHAL_PRCM_DIV_HDMI_DCLK = 120U,
PMHAL_PRCM_DIV_IVA_DCLK = 121U,
PMHAL_PRCM_DIV_L3INIT_480M_DCLK = 122U,
PMHAL_PRCM_DIV_MPU_DCLK = 123U,
PMHAL_PRCM_DIV_PCIE2_DCLK = 124U,
PMHAL_PRCM_DIV_PCIE_DCLK = 125U,
PMHAL_PRCM_DIV_PER_ABE_X1_DCLK = 126U,
PMHAL_PRCM_DIV_SATA_DCLK = 127U,
PMHAL_PRCM_DIV_SECURE_32K_DCLK = 128U,
PMHAL_PRCM_DIV_SYS_CLK1_DCLK = 129U,
PMHAL_PRCM_DIV_SYS_CLK2_DCLK = 130U,
PMHAL_PRCM_DIV_USB_OTG_DCLK = 131U,
PMHAL_PRCM_DIV_VIDEO1_DCLK = 132U,
PMHAL_PRCM_DIV_VIDEO2_DCLK = 133U,
PMHAL_PRCM_DIV_FUNC_12M_FCLK = 134U,
PMHAL_PRCM_DIV_FUNC_48M_FCLK = 135U,
PMHAL_PRCM_DIV_FUNC_96M_FCLK = 136U,
PMHAL_PRCM_DIV_MMC1_FCLK = 137U,
PMHAL_PRCM_DIV_MMC2_FCLK = 138U,
PMHAL_PRCM_DIV_L3INIT_60M_FCLK = 139U,
PMHAL_PRCM_DIV_GMAC_GMII_REF_CLK = 140U,
PMHAL_PRCM_DIV_GMII_M_CLK = 141U,
PMHAL_PRCM_DIV_MMC3_GFCLK = 142U,
PMHAL_PRCM_DIV_MMC4_GFCLK = 143U,
PMHAL_PRCM_DIV_RGMII_5M_REF_CLK = 144U,
PMHAL_PRCM_DIV_HDMI_CLK2 = 145U,
PMHAL_PRCM_DIV_PER_ABE_X1_GFCLK2 = 146U,
PMHAL_PRCM_DIV_VIDEO1_CLK2 = 147U,
PMHAL_PRCM_DIV_VIDEO2_CLK2 = 148U,
PMHAL_PRCM_DIV_MLBP_CLK = 149U,
PMHAL_PRCM_DIV_MLB_CLK = 150U,
PMHAL_PRCM_DIV_HDMI_CLK = 151U,
PMHAL_PRCM_DIV_VIDEO1_CLK = 152U,
PMHAL_PRCM_DIV_VIDEO2_CLK = 153U,
PMHAL_PRCM_DIV_CUSTEFUSE_SYS_GFCLK = 154U,
PMHAL_PRCM_DIV_ABE_SYS_CLK = 155U,
PMHAL_PRCM_DIV_L3INSTR_TS_GCLK = 156U,
PMHAL_PRCM_DIV_TIMER_SYS_CLK = 157U,
PMHAL_PRCM_DIV_IPU1_GCLK = 158U,
PMHAL_PRCM_DIV_IPU2_GCLK = 159U,
PMHAL_PRCM_DIV_FUNC_32K_CLK = 160U,
PMHAL_PRCM_DIV_VPE_GCLK = 161U,
PMHAL_PRCM_DIV_MAX = PMHAL_PRCM_DIV_VPE_GCLK,
PMHAL_PRCM_DIV_COUNT = PMHAL_PRCM_DIV_MAX + 1U,
PMHAL_PRCM_DPLL_APLL_PCIE = 162U,
PMHAL_PRCM_DPLL_MIN = PMHAL_PRCM_DPLL_APLL_PCIE,
PMHAL_PRCM_DPLL_ABE = 163U,
PMHAL_PRCM_DPLL_CORE = 164U,
PMHAL_PRCM_DPLL_DDR = 165U,
PMHAL_PRCM_DPLL_GMAC = 166U,
PMHAL_PRCM_DPLL_GPU = 167U,
PMHAL_PRCM_DPLL_IVA = 168U,
PMHAL_PRCM_DPLL_PCIE_REF = 169U,
PMHAL_PRCM_DPLL_PER = 170U,
PMHAL_PRCM_DPLL_USB = 171U,
PMHAL_PRCM_DPLL_DSP = 172U,
PMHAL_PRCM_DPLL_EVE = 173U,
PMHAL_PRCM_DPLL_MPU = 174U,
PMHAL_PRCM_DPLL_MAX = PMHAL_PRCM_DPLL_MPU,
PMHAL_PRCM_DPLL_COUNT = PMHAL_PRCM_DPLL_MAX + 1U,
PMHAL_PRCM_VIDEOPLL_VIDEO1 = 175U,
PMHAL_PRCM_VIDEOPLL_MIN = PMHAL_PRCM_VIDEOPLL_VIDEO1,
PMHAL_PRCM_VIDEOPLL_HDMI = 176U
,
PMHAL_PRCM_VIDEOPLL_COUNT = PMHAL_PRCM_VIDEOPLL_MAX + 1U,
PMHAL_PRCM_NODE_MAX = PMHAL_PRCM_VIDEOPLL_MAX,
PMHAL_PRCM_NODE_COUNT = PMHAL_PRCM_VIDEOPLL_COUNT,
PMHAL_PRCM_ROOT_CLK_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_MUX_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DIV_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_DPLL_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_NODE_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_VIDEOPLL_UNDEF = 0x7FFFFFFFU,
PMHAL_PRCM_ROOT_CLK_MIN = 0U,
PMHAL_PRCM_ROOT_CLK_SYS_CLKIN1 = PMHAL_PRCM_ROOT_CLK_MIN,
PMHAL_PRCM_NODE_MIN = PMHAL_PRCM_ROOT_CLK_MIN,
PMHAL_PRCM_ROOT_CLK_SYS_CLKIN2 = 1U,
PMHAL_PRCM_ROOT_CLK_REF_CLKIN0 = 2U,
PMHAL_PRCM_ROOT_CLK_REF_CLKIN1 = 3U,
PMHAL_PRCM_ROOT_CLK_REF_CLKIN2 = 4U,
PMHAL_PRCM_ROOT_CLK_ATL_CLKIN0 = 5U,
PMHAL_PRCM_ROOT_CLK_ATL_CLKIN1 = 6U,
PMHAL_PRCM_ROOT_CLK_ATL_CLKIN2 = 7U,
PMHAL_PRCM_ROOT_CLK_ATL_CLKIN3 = 8U,
PMHAL_PRCM_ROOT_CLK_SECURE_32K_CLK_SRC = 9U,
PMHAL_PRCM_ROOT_CLK_BOARD_MAX = PMHAL_PRCM_ROOT_CLK_SECURE_32K_CLK_SRC,
PMHAL_PRCM_ROOT_CLK_MAX = PMHAL_PRCM_ROOT_CLK_SECURE_32K_CLK_SRC,
PMHAL_PRCM_ROOT_CLK_COUNT = PMHAL_PRCM_ROOT_CLK_MAX + 1U,
PMHAL_PRCM_MUX_IPU1_GFCLK_MUX = 10U,
PMHAL_PRCM_MUX_MIN = PMHAL_PRCM_MUX_IPU1_GFCLK_MUX,
PMHAL_PRCM_MUX_ADC_MUX = 11U,
PMHAL_PRCM_MUX_EVE_GCLK_MUX = 12U,
PMHAL_PRCM_MUX_QSPI_GFCLK_MUX = 13U,
PMHAL_PRCM_MUX_VIP1_GCLK_MUX = 14U,
PMHAL_PRCM_MUX_CLKOUTMUX0_CLK_MUX = 15U,
PMHAL_PRCM_MUX_CLKOUTMUX1_CLK_MUX = 16U,
PMHAL_PRCM_MUX_CLKOUTMUX2_CLK_MUX = 17U,
PMHAL_PRCM_MUX_GMAC_RFT_CLK_MUX = 18U,
PMHAL_PRCM_MUX_MMC4_GFCLK_MUX = 19U,
PMHAL_PRCM_MUX_RMII_50M_CLK_MUX = 20U,
PMHAL_PRCM_MUX_MCASP1_AUX_GFCLK_MUX = 21U,
PMHAL_PRCM_MUX_MCASP1_AHCLKR_MUX = 22U,
PMHAL_PRCM_MUX_MCASP1_AHCLKX_MUX = 23U,
PMHAL_PRCM_MUX_MCASP2_AUX_GFCLK_MUX = 24U,
PMHAL_PRCM_MUX_MCASP2_AHCLKR_MUX = 25U,
PMHAL_PRCM_MUX_MCASP2_AHCLKX_MUX = 26U,
PMHAL_PRCM_MUX_MCASP3_AUX_GFCLK_MUX = 27U,
PMHAL_PRCM_MUX_MCASP3_AHCLKR_MUX = 28U,
PMHAL_PRCM_MUX_MCASP3_AHCLKX_MUX = 29U,
PMHAL_PRCM_MUX_TIMER5_GFCLK_MUX = 30U,
PMHAL_PRCM_MUX_TIMER6_GFCLK_MUX = 31U,
PMHAL_PRCM_MUX_TIMER7_GFCLK_MUX = 32U,
PMHAL_PRCM_MUX_TIMER8_GFCLK_MUX = 33U,
PMHAL_PRCM_MUX_TIMER1_GFCLK_MUX = 34U,
PMHAL_PRCM_MUX_TIMER2_GFCLK_MUX = 35U,
PMHAL_PRCM_MUX_TIMER3_GFCLK_MUX = 36U,
PMHAL_PRCM_MUX_TIMER4_GFCLK_MUX = 37U,
PMHAL_PRCM_MUX_UART1_GFCLK_MUX = 38U,
PMHAL_PRCM_MUX_UART2_GFCLK_MUX = 39U,
PMHAL_PRCM_MUX_UART3_GFCLK_MUX = 40U,
PMHAL_PRCM_MUX_DCAN1_SYS_CLK_MUX = 41U,
PMHAL_PRCM_MUX_WKUPAON_ICLK_MUX = 42U,
PMHAL_PRCM_MUX_EVE_CLK_MUX = 43U,
PMHAL_PRCM_MUX_DSP_GFCLK_MUX = 44U,
PMHAL_PRCM_MUX_RTI1_CLK_MUX = 45U,
PMHAL_PRCM_MUX_RTI2_CLK_MUX = 46U,
PMHAL_PRCM_MUX_RTI3_CLK_MUX = 47U,
PMHAL_PRCM_MUX_RTI4_CLK_MUX = 48U,
PMHAL_PRCM_MUX_RTI5_CLK_MUX = 49U,
PMHAL_PRCM_MUX_FUNC_32K_CLK_MUX = 50U,
PMHAL_PRCM_MUX_DPLL_CORE_CLK = 51U,
PMHAL_PRCM_MUX_MAX = PMHAL_PRCM_MUX_DPLL_CORE_CLK,
PMHAL_PRCM_MUX_COUNT = PMHAL_PRCM_MUX_MAX + 1U,
PMHAL_PRCM_DIV_ABE_24M_FCLK = 52U,
PMHAL_PRCM_DIV_MIN = PMHAL_PRCM_DIV_ABE_24M_FCLK,
PMHAL_PRCM_DIV_ABE_LP_CLK = 53U,
PMHAL_PRCM_DIV_DSP_DPLL_HS_CLK = 54U,
PMHAL_PRCM_DIV_FUNC_24M_CLK = 55U,
PMHAL_PRCM_DIV_L3_ICLK = 56U,
PMHAL_PRCM_DIV_L4_ROOT_CLK = 57U,
PMHAL_PRCM_DIV_PER_DPLL_HS_CLK = 58U,
PMHAL_PRCM_DIV_ABE_CLK = 59U,
PMHAL_PRCM_DIV_ABE_GICLK = 60U,
PMHAL_PRCM_DIV_AESS_FCLK = 61U,
PMHAL_PRCM_DIV_FUNC_128M_CLK_MUX = 62U,
PMHAL_PRCM_DIV_QSPI_GFCLK = 63U,
PMHAL_PRCM_DIV_CORE_DPLL_OUT_DCLK = 64U,
PMHAL_PRCM_DIV_DSP_GCLK = 65U,
PMHAL_PRCM_DIV_EMIF_PHY_DCLK = 66U,
PMHAL_PRCM_DIV_EMU_DCLK = 67U,
PMHAL_PRCM_DIV_EVE_DCLK = 68U,
PMHAL_PRCM_DIV_FUNC_96M_AON_DCLK = 69U,
PMHAL_PRCM_DIV_GMAC_250M_DCLK = 70U,
PMHAL_PRCM_DIV_GPU_DCLK = 71U,
PMHAL_PRCM_DIV_HDMI_DCLK = 72U,
PMHAL_PRCM_DIV_IVA_DCLK = 73U,
PMHAL_PRCM_DIV_L3INIT_480M_DCLK = 74U,
PMHAL_PRCM_DIV_MPU_DCLK = 75U,
PMHAL_PRCM_DIV_PCIE2_DCLK = 76U,
PMHAL_PRCM_DIV_PCIE_DCLK = 77U,
PMHAL_PRCM_DIV_PER_ABE_X1_DCLK = 78U,
PMHAL_PRCM_DIV_SATA_DCLK = 79U,
PMHAL_PRCM_DIV_SECURE_32K_DCLK = 80U,
PMHAL_PRCM_DIV_SYS_CLK1_DCLK = 81U,
PMHAL_PRCM_DIV_SYS_CLK2_DCLK = 82U,
PMHAL_PRCM_DIV_USB_OTG_DCLK = 83U,
PMHAL_PRCM_DIV_VIDEO1_DCLK = 84U,
PMHAL_PRCM_DIV_VIDEO2_DCLK = 85U,
PMHAL_PRCM_DIV_FUNC_48M_FCLK = 86U,
PMHAL_PRCM_DIV_FUNC_96M_FCLK = 87U,
PMHAL_PRCM_DIV_GMAC_GMII_MAIN_CLK = 88U,
PMHAL_PRCM_DIV_MMC4_GFCLK = 89U,
PMHAL_PRCM_DIV_RGMII_5M_CLK = 90U,
PMHAL_PRCM_DIV_HDMI_CLK2 = 91U,
PMHAL_PRCM_DIV_PER_ABE_X1_GFCLK2 = 92U,
PMHAL_PRCM_DIV_VIDEO1_CLK2 = 93U,
PMHAL_PRCM_DIV_VIDEO2_CLK2 = 94U,
PMHAL_PRCM_DIV_MLBP_CLK = 95U,
PMHAL_PRCM_DIV_MLB_CLK = 96U,
PMHAL_PRCM_DIV_HDMI_CLK = 97U,
PMHAL_PRCM_DIV_VIDEO1_CLK = 98U,
PMHAL_PRCM_DIV_VIDEO2_CLK = 99U,
PMHAL_PRCM_DIV_CUSTEFUSE_SYS_GFCLK = 100U,
PMHAL_PRCM_DIV_ABE_SYS_CLK = 101U,
PMHAL_PRCM_DIV_L3INSTR_TS_GCLK = 102U,
PMHAL_PRCM_DIV_TIMER_SYS_CLK = 103U,
PMHAL_PRCM_DIV_TESOC_EXT_CLK = 104U,
PMHAL_PRCM_DIV_VID_PIX_CLK = 105U,
PMHAL_PRCM_DIV_SYS_CLK1 = 106U,
PMHAL_PRCM_DIV_SYS_CLK2 = 107U,
PMHAL_PRCM_DIV_IPU1_GCLK = 108U,
PMHAL_PRCM_DIV_FUNC_32K_CLK = 109U,
PMHAL_PRCM_DIV_MAX = PMHAL_PRCM_DIV_FUNC_32K_CLK,
PMHAL_PRCM_DIV_COUNT = PMHAL_PRCM_DIV_MAX + 1U,
PMHAL_PRCM_DPLL_CORE = 110U,
PMHAL_PRCM_DPLL_MIN = PMHAL_PRCM_DPLL_CORE,
PMHAL_PRCM_DPLL_DDR = 111U,
PMHAL_PRCM_DPLL_DSP_GMAC = 112U,
PMHAL_PRCM_DPLL_PER = 113U,
PMHAL_PRCM_DPLL_EVE_VID_DSP = 114U,
PMHAL_PRCM_DPLL_MAX = PMHAL_PRCM_DPLL_EVE_VID_DSP,
PMHAL_PRCM_DPLL_COUNT = PMHAL_PRCM_DPLL_MAX + 1U,
PMHAL_PRCM_VIDEOPLL_MIN = PMHAL_PRCM_DPLL_EVE_VID_DSP,
PMHAL_PRCM_VIDEOPLL_MAX = PMHAL_PRCM_DPLL_EVE_VID_DSP,