|
Nano102_112 Series BSP
V3.03.002
The Board Support Package for Nano102_112 Series
|
#include <Nano1X2Series.h>
Data Fields | |
| union { | |
| __I uint32_t RBR | |
| __O uint32_t THR | |
| }; | |
| __IO uint32_t | CTL |
| __IO uint32_t | ALTCTL |
| __IO uint32_t | EGTR |
| __IO uint32_t | RFTMR |
| __IO uint32_t | ETUCR |
| __IO uint32_t | IER |
| __IO uint32_t | ISR |
| __IO uint32_t | TRSR |
| __IO uint32_t | PINCSR |
| __IO uint32_t | TMR0 |
| __IO uint32_t | TMR1 |
| __IO uint32_t | TMR2 |
| __IO uint32_t | UACTL |
| __I uint32_t | TDRA |
| __I uint32_t | TDRB |
@addtogroup SC Smart Card Host Interface Controller(SC) Memory Mapped Structure for SC Controller
Definition at line 7543 of file Nano1X2Series.h.
| union { ... } |
| __IO uint32_t SC_T::ALTCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TX_RST | TX Software Reset |
| When TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the TX internal state machine and pointers. | ||
| Note: This bit will be auto cleared and needs at least 3 SC engine clock cycles. | ||
| [1] | RX_RST | RX Software Reset |
| When RX_RST is set, all the bytes in the receiver buffer and RX internal state machine will be cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the RX internal state machine and pointers. | ||
| Note: This bit will be auto cleared and needs at least 3 SC engine clock cycles. | ||
| [2] | DACT_EN | Deactivation Sequence Generator Enable |
| This bit enables SC controller to initiate the card by deactivation sequence | ||
| 0 = No effect. | ||
| 1 = Deactivation sequence generator Enabled. | ||
| Note1: When the deactivation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to "1". | ||
| Note2: This field will be cleared by TX_RST and RX_RST. | ||
| So don't fill this bit, TX_RST, and RX_RST at the same time. | ||
| Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [3] | ACT_EN | Activation Sequence Generator Enable |
| This bit enables SC controller to initiate the card by activation sequence | ||
| 0 = No effect. | ||
| 1 = Activation sequence generator Enabled. | ||
| Note1: When the activation sequence completed, this bit will be cleared automatically and the SC_IS [INIT_IS] will be set to "1". | ||
| Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time. | ||
| Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [4] | WARST_EN | Warm Reset Sequence Generator Enable |
| This bit enables SC controller to initiate the card by warm reset sequence | ||
| 0 = No effect. | ||
| 1 = Warm reset sequence generator Enabled. | ||
| Note1: When the warm reset sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to "1". | ||
| Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time. | ||
| Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [5] | TMR0_SEN | Internal Timer0 Start Enable |
| This bit enables Timer0 to start counting. | ||
| Software can fill "0" to stop it and set "1" to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Starts counting. | ||
| Note1: This field is used for internal 24 bit timer when SC_CTL [TMR_SEL] = 01. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMR0 [26] = "0"), this bit will be auto-cleared by hardware. | ||
| Note3: This field will be cleared by TX_RST and RX_RST. | ||
| So don't fill this bit, TX_RST and RX_RST at the same time. | ||
| Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [6] | TMR1_SEN | Internal Timer1 Start Enable |
| This bit enables Timer "1" to start counting. | ||
| Software can fill 0 to stop it and set "1" to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Starts counting. | ||
| Note1: This field is used for internal 8-bit timer when SC_CTL [TMR_SEL] = 01 or 10. | ||
| Don't filled TMR1_SEN when SC_CTL [TMR_SEL] = 00 or 11. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMR1 [26] = "0"), this bit will be auto-cleared by hardware. | ||
| Note3: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time. | ||
| Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [7] | TMR2_SEN | Internal Timer2 Start Enable |
| This bit enables Timer2 to start counting. | ||
| Software can fill "0" to stop it and set "1" to reload and count. | ||
| 0 = Stops counting. | ||
| 1 = Starts counting. | ||
| Note1: This field is used for internal 8-bit timer when SC_CTL [TMR_SEL] == 11. | ||
| Don't filled TMR2_SEN when SC_CTL [TMR_SEL] == 00 or 01 or 10. | ||
| Note2: If the operation mode is not in auto-reload mode (SC_TMR2 [26] = "0"), this bit will be auto-cleared by hardware. | ||
| Note3: This field will be cleared by TX_RST and RX_RST. | ||
| So don't fill this bit, TX_RST, and RX_RST at the same time. | ||
| Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed. | ||
| [9:8] | INIT_SEL | Initial Timing Selection |
| This field indicates the timing of hardware initial state (activation or warm-reset or deactivation). | ||
| [12] | RX_BGT_EN | Receiver Block Guard Time Function Enable |
| 0 = Receiver block guard time function Disabled. | ||
| 1 = Receiver block guard time function Enabled. | ||
| [13] | TMR0_ATV | Internal Timer0 Active State (Read Only) |
| This bit indicates the timer counter status of timer0. | ||
| 0 = Timer0 is not active. | ||
| 1 = Timer0 is active. | ||
| [14] | TMR1_ATV | Internal Timer1 Active State (Read Only) |
| This bit indicates the timer counter status of timer1. | ||
| 0 = Timer1 is not active. | ||
| 1 = Timer1 is active. | ||
| [15] | TMR2_ATV | Internal Timer2 Active State (Read Only) |
| This bit indicates the timer counter status of timer2. | ||
| 0 = Timer2 is not active. | ||
| 1 = Timer2 is active. |
Definition at line 7748 of file Nano1X2Series.h.
| __IO uint32_t SC_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SC_CEN | SC Engine Enable |
| Set this bit to "1" to enable SC operation. | ||
| If this bit is cleared, SC will force all transition to IDLE state. | ||
| [1] | DIS_RX | RX Transition Disable |
| 0 = Receiver Enabled. | ||
| 1 = Receiver Disabled. | ||
| [2] | DIS_TX | TX Transition Disable |
| 0 = Transceiver Enabled. | ||
| 1 = Transceiver Disabled. | ||
| [3] | AUTO_CON_EN | Auto Convention Enable |
| 0 = Auto-convention Disabled. | ||
| 1 = Auto-convention Enabled. | ||
| When hardware receives TS in answer to reset state and the TS is direct convention, CON_SEL will be set to 00 automatically, otherwise if the TS is inverse convention, CON_SEL will be set to 11. | ||
| If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F. | ||
| After hardware received first data and stored it at buffer, hardware will decided the convention and change the SC_CTL[CON_SEL] register automatically. | ||
| If the first data is not 0x3B or 0x3F, hardware will generate an interrupt INT_ACON_ERR(if SC_IER [ACON_ERR_IE = "1"] to CPU. | ||
| [5:4] | CON_SEL | Convention Selection |
| 00 = Direct convention. | ||
| 01 = Reserved. | ||
| 10 = Reserved. | ||
| 11 = Inverse convention. | ||
| Note: If AUTO_CON_EN is enabled, this field must be ignored. | ||
| [7:6] | RX_FTRI_LEV | RX Buffer Trigger Level |
| When the number of bytes in the receiving buffer equals the RX_FTRI_LEV, the RDA_IF will be set (if IER [RDA_IEN] is enabled, an interrupt will be generated). | ||
| 00 = INTR_RDA Trigger Level 1 byte. | ||
| 01 = INTR_RDA Trigger Level 2 bytes. | ||
| 10 = INTR_RDA Trigger Level 3 bytes. | ||
| 11 = Reserved. | ||
| [12:8] | BGT | Block Guard Time (BGT) |
| This field indicates the counter for block guard time. | ||
| According to ISO7816-3, in T=0 mode, software must fill 15 (real block guard time = 16) to this field and in T=1 mode software must fill 21 (real block guard time = 22) to it. | ||
| In TX mode, hardware will auto hold off first character until BGT has elapsed regardless of the TX data. | ||
| In RX mode, software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing. | ||
| If the incoming data timing less than BGT, an interrupt will be generated. | ||
| Note: The real block guard time is BGT + 1. | ||
| [14:13] | TMR_SEL | Timer Selection |
| 00 = Disable all internal timer function. | ||
| 01 = Enable internal 24 bit timer. | ||
| Software can configure it by setting SC_TMR0 [23:0]. | ||
| SC_TMR1 and SC_TMR2 will be ignored in this mode. | ||
| 10 = Enable internal 24 bit timer and 8 bit internal timer. | ||
| Software can configure the 24 bit timer by setting SC_TMR0 [23:0] and configure the 8 bit timer by setting SC_TMR1 [7:0]. | ||
| SC_TMR2 will be ignored in this mode. | ||
| 11 = Enable internal 24 bit timer and two 8 bit timers. | ||
| Software can configure them by setting SC_TMR0 [23:0], SC_TMR1 [7:0] and SC_TMR2 [7:0]. | ||
| [15] | SLEN | Stop Bit Length |
| This field indicates the length of stop bit. | ||
| 0 = The stop bit length is 2 ETU. | ||
| 1 = The stop bit length is 1 ETU. | ||
| Note: The default stop bit length is 2. | ||
| [18:16] | RX_ERETRY | RX Error Retry Register |
| This field indicates the maximum number of receiver retries that are allowed when parity error has occurred. | ||
| Note1: The real maximum retry number is RX_ERETRY + 1, so 8 is the maximum retry number. | ||
| Note2: This field can not be changed when RX_ERETRY_EN enabled. | ||
| The change flow is to disable RX_ETRTRY_EN first and then fill new retry value. | ||
| [19] | RX_ERETRY_EN | RX Error Retry Enable Register |
| This bit enables receiver retry function when parity error has occurred. | ||
| 0 = RX error retry function Disabled. | ||
| 1 = RX error retry function Enabled. | ||
| Note: User must fill RX_ERETRY value before enabling this bit. | ||
| [22:20] | TX_ERETRY | TX Error Retry Register |
| This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. | ||
| Note1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number. | ||
| Note2: This field can not be changed when TX_ERETRY_EN enabled. | ||
| The change flow is to disable TX_ETRTRY_EN first and then fill new retry value. | ||
| [23] | TX_ERETRY_EN | TX Error Retry Enable Register |
| This bit enables transmitter retry function when parity error has occurred. | ||
| 0 = TX error retry function Disabled. | ||
| 1 = TX error retry function Enabled. | ||
| Note: User must fill TX_ERETRY value before enabling this bit. | ||
| [25:24] | CD_DEB_SEL | Card Detect De-Bounce Select Register |
| This field indicates the card detect de-bounce selection. | ||
| This field indicates the card detect de-bounce selection. | ||
| 00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks. | ||
| 01 = De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks. | ||
| 10 = De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks. | ||
| 11 = De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks. |
Definition at line 7658 of file Nano1X2Series.h.
| __IO uint32_t SC_T::EGTR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | EGT | Extended Guard Time |
| This field indicates the extended guard timer value. | ||
| Note: The counter is ETU based and the real extended guard time is EGT. |
Definition at line 7761 of file Nano1X2Series.h.
| __IO uint32_t SC_T::ETUCR |
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | ETU_RDIV | ETU Rate Divider |
| The field indicates the clock rate divider. | ||
| The real ETU is ETU_RDIV + 1. | ||
| Note1: Software can configure this field, but this field must be greater than 0x04. | ||
| Note2: Software can configure this field, but if the error rate is equal to 2%, this field must be greater than 0x040. | ||
| [15] | COMPEN_EN | Compensation Mode Enable |
| This bit enables clock compensation function. | ||
| When this bit enabled, hardware will alternate between n clock cycles and (n-1) clock cycles, where n is the value to be written into the ETU_RDIV register. | ||
| 0 = Compensation function Disabled. | ||
| 1 = Compensation function Enabled. |
Definition at line 7796 of file Nano1X2Series.h.
| __IO uint32_t SC_T::IER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDA_IE | Receive Data Reach Interrupt Enable |
| This field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable. | ||
| 0 = INT_RDR Disabled. | ||
| 1 = INT_RDR Enabled. | ||
| [1] | TBE_IE | Transmit Buffer Empty Interrupt Enable |
| This field is used for transmit buffer empty interrupt enable. | ||
| 0 = INT_THRE Disabled. | ||
| 1 = INT_THRE Enabled. | ||
| [2] | TERR_IE | Transfer Error Interrupt Enable |
| This field is used for transfer error interrupt enable. | ||
| The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F), receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY). | ||
| 0 = INT_TERR Disabled. | ||
| 1 = INT_TERR Enabled. | ||
| [3] | TMR0_IE | Timer0 Interrupt Enable |
| This field is used for TMR0 interrupt enable. | ||
| 0 = INT_TMR0 Disabled. | ||
| 1 = INT_TMR0 Enabled. | ||
| [4] | TMR1_IE | Timer1 Interrupt Enable |
| This field is used for TMR1 interrupt enable. | ||
| 0 = INT_TMR1 Disabled. | ||
| 1 = INT_TMR1 Enabled. | ||
| [5] | TMR2_IE | Timer2 Interrupt Enable |
| This field is used for TMR2 interrupt enable. | ||
| 0 = INT_TMR2 Disabled. | ||
| 1 = INT_TMR2 Enabled. | ||
| [6] | BGT_IE | Block Guard Time Interrupt Enable |
| This field is used for block guard time interrupt enable. | ||
| 0 = INT_BGT Disabled. | ||
| 1 = INT_BGT Enabled. | ||
| [7] | CD_IE | Card Detect Interrupt Enable |
| This field is used for card detect interrupt enable. | ||
| The card detect status register is SC_PINCSR [CD_CH] and SC_PINCSR[CD_CL]. | ||
| 0 = INT_CD Disabled. | ||
| 1 = INT_CD Enabled. | ||
| [8] | INIT_IE | Initial End Interrupt Enable |
| This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable. | ||
| 0 = INT_INIT Disabled. | ||
| 1 = INT_INIT Enabled. | ||
| [9] | RTMR_IE | Receiver Buffer Time-Out Interrupt Enable |
| This field is used for receiver buffer time-out interrupt enable. | ||
| 0 = INT_RTMR Disabled. | ||
| 1 = INT_RTMR Enabled. | ||
| [10] | ACON_ERR_IE | Auto Convention Error Interrupt Enable |
| This field is used for auto convention error interrupt enable. | ||
| 0 = INT_ACON_ERR Disabled. | ||
| 1 = INT_ACON_ERR Enabled. |
Definition at line 7852 of file Nano1X2Series.h.
| __IO uint32_t SC_T::ISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RDA_IS | Receive Data Reach Interrupt Status Flag (Read Only) |
| This field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt status flag. | ||
| Note: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV]. | ||
| If software reads data from SC_RBR and receiver pointer is less than SC_CTL [RX_FTRI_LEV], this bit will be cleared automatically. | ||
| [1] | TBE_IS | Transmit Buffer Empty Interrupt Status Flag (Read Only) |
| This field is used for transmit buffer empty interrupt status flag. | ||
| This bit is different with SC_TRSR [TX_EMPTY_F] flag and SC_TRSR [TX_ATV] flag; The TX_EMPTY_F will be set when the last byte data be read to shift register and TX_ATV flag indicates the transmitter is in active or not (the last data has been transmitted or not), but the TBE_IS may be set when the last byte data be read to shift register or the last data has been transmitted. | ||
| When this bit assert, software can write 1~4 byte data to SC_THR register. | ||
| Note: If software wants to clear this bit, software must write data to SC_THR register and then this bit will be cleared automatically. | ||
| [2] | TERR_IS | Transfer Error Interrupt Status Flag (Read Only) |
| This field is used for transfer error interrupt status flag. | ||
| The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F) and receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY). | ||
| Note: This field is the status flag of SC_TRSR [RX_EBR_F], SC_TRSR [RX_EFR_F], SC_TRSR [RX_EPA_F], SC_TRSR [RX_OVER_F], SC_TRSR [TX_OVER_F], SC_TRSR [RX_OVER_ERETRY] or SC_TRSR [TX_OVER_ERETRY]. | ||
| So if software wants to clear this bit, software must write "1" to each field. | ||
| [3] | TMR0_IS | Timer0 Interrupt Status Flag (Read Only) |
| This field is used for TMR0 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [4] | TMR1_IS | Timer1 Interrupt Status Flag (Read Only) |
| This field is used for TMR1 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [5] | TMR2_IS | Timer2 Interrupt Status Flag (Read Only) |
| This field is used for TMR2 interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [6] | BGT_IS | Block Guard Time Interrupt Status Flag (Read Only) |
| This field is used for block guard time interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [7] | CD_IS | Card Detect Interrupt Status Flag (Read Only) |
| This field is used for card detect interrupt status flag. | ||
| The card detect status register is SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F]. | ||
| Note: This field is the status flag of SC_PINCSR [CD_INS_F] or SC_PINCSR [CD_REM_F]. | ||
| So if software wants to clear this bit, software must write "1" to this field. | ||
| [8] | INIT_IS | Initial End Interrupt Status Flag (Read Only) |
| This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [9] | RTMR_IS | Receiver Buffer Time-Out Interrupt Status Flag (Read Only) |
| This field is used for receiver buffer time-out interrupt status flag. | ||
| Note: This field is the status flag of receiver buffer time-out state. | ||
| If software wants to clear this bit, software must read the receiver buffer remaining data by reading SC_RBR register,. | ||
| [10] | ACON_ERR_IS | Auto Convention Error Interrupt Status Flag (Read Only) |
| This field indicates auto convention sequence error. | ||
| If the received TS at ATR state is not 0x3B or 0x3F, this bit will be set. | ||
| Note: This bit is read only, but can be cleared by writing "1" to it. |
Definition at line 7904 of file Nano1X2Series.h.
| __IO uint32_t SC_T::PINCSR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | POW_EN | SC_POW_EN Pin Signal |
| This bit is the pin status of SC_POW_EN but user can drive SC_POW_EN pin to high or low by setting this bit. | ||
| 0 = Drive SC_POW_EN pin to low. | ||
| 1 = Drive SC_POW_EN pin to high. | ||
| Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field When operating in these modes. | ||
| [1] | SC_RST | SC_RST Pin Signal |
| This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit. | ||
| 0 = Drive SC_RST pin to low. | ||
| 1 = Drive SC_RST pin to high. | ||
| Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field When operating in these modes. | ||
| [2] | CD_REM_F | Card Detect Removal Status Of SC_CD Pin (Read Only) |
| This bit is set whenever card has been removal. | ||
| 0 = No effect. | ||
| 1 = Card Removal. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: Card detect engine will start after SC_CTL [SC_CEN] set. | ||
| [3] | CD_INS_F | Card Detect Insert Status Of SC_CD Pin (Read Only) |
| This bit is set whenever card has been inserted. | ||
| 0 = No effect. | ||
| 1 = Card insert. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: Card detect engine will start after SC_CTL [SC_CEN] set. | ||
| [4] | CD_PIN_ST | Card Detect Status Of SC_CD Pin Status (Read Only) |
| This bit is the pin status flag of SC_CD | ||
| 0 = SC_CD pin state at low. | ||
| 1 = SC_CD pin state at high. | ||
| [6] | CLK_KEEP | SC Clock Enable |
| 0 = SC clock generation Disabled. | ||
| 1 = SC clock always keeps free running. | ||
| Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field when operation in these modes. | ||
| [7] | ADAC_CD_EN | Auto Deactivation When Card Removal |
| 0 = Auto deactivation Disabled when hardware detected the card is removal. | ||
| 1 = Auto deactivation Enabled when hardware detected the card is removal. | ||
| Note1: When the card is removal, hardware will stop any process and then do deactivation sequence (if this bit be setting). | ||
| If this process completes. | ||
| Hardware will generate an interrupt INT_INIT to CPU. | ||
| [8] | SC_OEN_ST | SC Data Pin Output Enable Status (Read Only) |
| 0 = SC data output enable pin status is at low. | ||
| 1 = SC data output enable pin status is at high. | ||
| [9] | SC_DATA_O | Output Of SC Data Pin |
| This bit is the pin status of SC data output but user can drive this pin to high or low by setting this bit. | ||
| 0 = Drive SC data output pin to low. | ||
| 1 = Drive SC data output pin to high. | ||
| Note: When SC is at activation, warm re set or deactivation mode, this bit will be changed automatically. | ||
| So don't fill this field when SC is in these modes. | ||
| [10] | CD_LEV | Card Detect Level |
| 0 = When hardware detects the card detect pin from high to low, it indicates a card is detected. | ||
| 1 = When hardware detects the card detect pin from low to high, it indicates a card is detected. | ||
| Note: Software must select card detect level before Smart Card engine enable | ||
| [11] | POW_INV | SC_POW Pin Inverse |
| This bit is used for inverse the SC_POW pin. | ||
| There are four kinds of combination for SC_POW pin setting by POW_INV and | ||
| POW_EN(SC_PINCSR[0]). POW_INV is bit 1 and POW_EN is bit 0 for SC_POW_Pin as | ||
| high or low voltage selection. | ||
| POW_INV is 0 and POW_EN is 0, than SC_POW Pin output 0. | ||
| POW_INV is 0 and POW_EN is 1, than SC_POW Pin output 1. | ||
| POW_INV is 1 and POW_EN is 0, than SC_POW Pin output 1. | ||
| POW_INV is 1 and POW_EN is 1, than SC_POW Pin output 0. | ||
| Note: Software must select POW_INV before Smart Card is enabled by SC_CEN (SC_CTL[0]) | ||
| [16] | SC_DATA_I_ST | SC Data Input Pin Status (Read Only) |
| This bit is the pin status of SC_DATA_I | ||
| 0 = The SC_DATA_I pin is low. | ||
| 1 = The SC_DATA_I pin is high. |
Definition at line 8055 of file Nano1X2Series.h.
| __I uint32_t SC_T::RBR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | RBR | Receiving Buffer |
| By reading this register, the SC Controller will return an 8-bit data received from RX pin (LSB first). |
Definition at line 7559 of file Nano1X2Series.h.
| __IO uint32_t SC_T::RFTMR |
| Bits | Field | Descriptions |
|---|---|---|
| [8:0] | RFTM | SC Receiver Buffer Time-Out Register (ETU Based) |
| The time-out counter resets and starts counting whenever the RX buffer received a new data word. | ||
| Once the counter decrease to "1" and no new data is received or CPU does not read data by reading SC_RBR register, a receiver time-out interrupt INT_RTMR will be generated(if SC_IER[RTMR_IE] is high). | ||
| Note1: The counter is ETU based and the real count value is RFTM + 1 | ||
| Note2: Fill all "0" to this field to disable this function. |
Definition at line 7776 of file Nano1X2Series.h.
| __I uint32_t SC_T::TDRA |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | TDR0 | Timer0 Current Data Register (Read Only) |
| This field indicates the current count values of timer0. |
Definition at line 8139 of file Nano1X2Series.h.
| __I uint32_t SC_T::TDRB |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | TDR1 | Timer1 Current Data Register (Read Only) |
| This field indicates the current count values of timer1. | ||
| [15:8] | TDR2 | Timer2 Current Data Register (Read Only) |
| This field indicates the current count values of timer2. |
Definition at line 8153 of file Nano1X2Series.h.
| __O uint32_t SC_T::THR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | THR | Transmit Buffer |
| By writing to this register, the SC sends out an 8-bit data through the TX pin (LSB first). |
Definition at line 7570 of file Nano1X2Series.h.
| __IO uint32_t SC_T::TMR0 |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | CNT | Timer 0 Counter Value Register (ETU Base) |
| This field indicates the internal timer operation values. | ||
| [27:24] | MODE | Timer 0 Operation Mode Selection |
| This field indicates the internal 24 bit timer operation selection. |
Definition at line 8069 of file Nano1X2Series.h.
| __IO uint32_t SC_T::TMR1 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CNT | Timer 1 Counter Value Register (ETU Base) |
| This field indicates the internal timer operation values. | ||
| [27:24] | MODE | Timer 1 Operation Mode Selection |
| This field indicates the internal 8 bit timer operation selection. |
Definition at line 8083 of file Nano1X2Series.h.
| __IO uint32_t SC_T::TMR2 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CNT | Timer 2 Counter Value Register (ETU Base) |
| This field indicates the internal timer operation values. | ||
| [27:24] | MODE | Timer 2 Operation Mode Selection |
| This field indicates the internal 8 bit timer operation selection. |
Definition at line 8097 of file Nano1X2Series.h.
| __IO uint32_t SC_T::TRSR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RX_OVER_F | RX Overflow Error Status Flag (Read Only) |
| This bit is set when RX buffer overflow. | ||
| If the number of received bytes is greater than RX Buffer (SC_RBR) size, 4 bytes of SC, this bit will be set. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: The overwrite data will be ignored. | ||
| [1] | RX_EMPTY_F | Receiver Buffer Empty Status Flag(Read Only) |
| This bit indicates RX buffer empty or not. | ||
| When the last byte of RX buffer has been read by CPU, hardware sets this bit high. | ||
| It will be cleared when SC receives any new data. | ||
| [2] | RX_FULL_F | Receiver Buffer Full Status Flag (Read Only) |
| This bit indicates RX buffer full or not. | ||
| This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware. | ||
| [4] | RX_EPA_F | Receiver Parity Error Status Flag (Read Only) |
| This bit is set to logic "1" whenever the received character does not have a valid "parity bit". | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag. | ||
| [5] | RX_EFR_F | Receiver Frame Error Status Flag (Read Only) |
| This bit is set to logic "1" whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic "0"). | ||
| Note1: This bit is read only, but can be cleared by writing "1" to it. | ||
| Note2: If CPI sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag. | ||
| [6] | RX_EBR_F | Receiver Break Error Status Flag (Read Only) |
| This bit is set to a logic "1" whenever the received data input (RX) held in the "spacing state" (logic "0") is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits). | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag. | ||
| [8] | TX_OVER_F | TX Overflow Error Interrupt Status Flag (Read Only) |
| If TX buffer is full (TX_FULL_F = "1"), an additional write data to SC_THR will cause this bit to logic "1". | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: The additional write data will be ignored. | ||
| [9] | TX_EMPTY_F | Transmit Buffer Empty Status Flag (Read Only) |
| This bit indicates TX buffer empty or not. | ||
| When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. | ||
| It will be cleared when writing data into SC_THR (TX buffer not empty). | ||
| [10] | TX_FULL_F | Transmit Buffer Full Status Flag (Read Only) |
| This bit indicates TX buffer full or not. | ||
| This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware. | ||
| [18:16] | RX_POINT_F | Receiver Buffer Pointer Status Flag (Read Only) |
| This field indicates the RX buffer pointer status flag. | ||
| When SC receives one byte from external device, RX_POINT_F increases one. | ||
| When one byte of RX buffer is read by CPU, RX_POINT_F decreases one. | ||
| [21] | RX_REERR | Receiver Retry Error (Read Only) |
| This bit is set by hardware when RX has any error and retries transfer. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2 This bit is a flag and can not generate any interrupt to CPU. | ||
| Note3: If CPU enables receiver retry function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F). | ||
| [22] | RX_OVER_ERETRY | Receiver Over Retry Error (Read Only) |
| This bit is set by hardware when RX transfer error retry over retry number limit. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2: If CPU enables receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F). | ||
| [23] | RX_ATV | Receiver In Active Status Flag (Read Only) |
| This bit is set by hardware when RX transfer is in active. | ||
| This bit is cleared automatically when RX transfer is finished. | ||
| [26:24] | TX_POINT_F | Transmit Buffer Pointer Status Flag (Read Only) |
| This field indicates the TX buffer pointer status flag. | ||
| When CPU writes data into SC_THR, TX_POINT_F increases one. | ||
| When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one. | ||
| [29] | TX_REERR | Transmitter Retry Error (Read Only) |
| This bit is set by hardware when transmitter re-transmits. | ||
| Note1: This bit is read only, but it can be cleared by writing "1" to it. | ||
| Note2 This bit is a flag and can not generate any interrupt to CPU. | ||
| [30] | TX_OVER_ERETRY | Transmitter Over Retry Error (Read Only) |
| This bit is set by hardware when transmitter re-transmits over retry number limitation. | ||
| Note: This bit is read only, but it can be cleared by writing "1" to it. | ||
| [31] | TX_ATV | Transmit In Active Status Flag (Read Only) |
| This bit is set by hardware when TX transfer is in active or the last byte transmission has not completed. | ||
| This bit is cleared automatically when TX transfer is finished and the STOP bit (include guard time) has been transmitted. |
Definition at line 7979 of file Nano1X2Series.h.
| __IO uint32_t SC_T::UACTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | UA_MODE_EN | UART Mode Enable |
| 0 = Smart Card mode. | ||
| 1 = UART mode. | ||
| Note1: When operating in UART mode, user must set SCx_CTL [CON_SEL] and SCx_CTL [AUTO_CON_EN] to "0". | ||
| Note2: When operating in smart card mode, user must set SCx_UACTL [7:0] register to "0". | ||
| Note3: When UART is enabled, hardware will generate a reset to reset internal buffer and internal state machine. | ||
| [5:4] | DATA_LEN | Data Length |
| 00 = 8 bits | ||
| 01 = 7 bits | ||
| 10 = 6 bits | ||
| 11 = 5 bits | ||
| Note: In Smart Card mode, this field must be '00' | ||
| [6] | PBDIS | Parity Bit Disable |
| 0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data. | ||
| 1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. | ||
| Note: In Smart Card mode, this field must be '0' (default setting is with parity bit) | ||
| [7] | OPE | Odd Parity Enable |
| 0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
| 1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. | ||
| Note: This bit has effect only when PBDIS bit is '0'. |
Definition at line 8127 of file Nano1X2Series.h.


This kata arose from some discussions we’ve been having at the DFW Practioners meetings. The problem domain is something seemingly simple: pricing goods at supermarkets.
Some things in supermarkets have simple prices: this can of beans costs $0.65. Other things have more complex prices. For example:
- three for a dollar (so what’s the price if I buy 4, or 5?)
- $1.99/pound (so what does 4 ounces cost?)
- buy two, get one free (so does the third item have a price?)
This kata involves no coding. The exercise is to experiment with various models for representing money and prices that are flexible enough to deal with these (and other) pricing schemes, and at the same time are generally usable (at the checkout, for stock management, order entry, and so on). Spend time considering issues such as:
- does fractional money exist?
- when (if ever) does rounding take place?
- how do you keep an audit trail of pricing decisions (and do you need to)?
- are costs and prices the same class of thing?
- if a shelf of 100 cans is priced using “buy two, get one free”, how do you value the stock?
This is an ideal shower-time kata, but be careful. Some of the problems are more subtle than they first appear. I suggest that it might take a couple of weeks worth of showers to exhaust the main alternatives.
Goal
The goal of this kata is to practice a looser style of experimental modelling. Look for as many different ways of handling the issues as possible. Consider the various tradeoffs of each. What techniques use best for exploring these models? For recording them? How can you validate a model is reasonable?
What’s a Code Kata?
As a group, software developers don’t practice enough. Most of our learning takes place on the job, which means that most of our mistakes get made there as well. Other creative professions practice: artists carry a sketchpad, musicians play technical pieces, poets constantly rewrite works. In karate, where the aim is to learn to spar or fight, most of a student’s time is spent learning and refining basic moves. The more formal of these exercises are called kata.
To help developers get the same benefits from practicing, we’re putting together a series of code kata: simple, artificial exercises which let us experiment and learn without the pressure of a production environment. Our suggestions for doing the kata are:
- find a place and time where you won’t be interrupted
- focus on the essential elements of the kata
- remember to look for feedback for every major decision
- if it helps, keep a journal of your progress
- have discussion groups with other developers, but try to have completed the kata first
There are no right or wrong answers in these kata: the benefit comes from the process, not from the result.


GLDEX: Fitting Single and Mixture of Generalised Lambda Distributions
(RS and FMKL) using Various Methods
The fitting algorithms considered in this package have two major objectives. One is to provide a smoothing device to fit distributions to data using the weight and unweighted discretised approach based on the bin width of the histogram. The other is to provide a definitive fit to the data set using the maximum likelihood and quantile matching estimation. Other methods such as moment matching, starship method, L moment matching are also provided. Diagnostics on goodness of fit can be done via qqplots, KS-resample tests and comparing mean, variance, skewness and kurtosis of the data with the fitted distribution.
| Version: |
<IP_ADDRESS> |
| Depends: |
cluster, grDevices, graphics, stats |
| Published: |
2016-12-26 |
| Author: |
Steve Su, with contributions from: Diethelm Wuertz, Martin Maechler and Rmetrics core team members for low discrepancy algorithm, Juha Karvanen for L moments codes, Robert King for gld C codes and starship codes, Benjamin Dean for corrections and input in ks.gof code and R core team for histsu function. |
| Maintainer: |
Steve Su <allegro.su at gmail.com> |
| License: |
GPL (≥ 3) |
| NeedsCompilation: |
yes |
| Materials: |
README |
| In views: |
Cluster, Distributions |
| CRAN checks: |
GLDEX results |
Downloads:
Reverse dependencies:
Linking:
Please use the canonical form
https://CRAN.R-project.org/package=GLDEX
to link to this page.


About
This is a very simplistic extension developed to learn about Chrome Extensions and help me track time for tasks.
Feel free to grab the code and use it as you wish.
Credits
It was developed by me, Ricardo Godoy, and I used some resources:
Icon by Freepik from www.flaticon.com


I'm currently in Las Vegas attending RailsConf 2009. This morning I heard Heroku's Adam Wiggins give an excellent overview of Rails Metal, Rack and Sinatra.
Some time ago now, Rails adopted Rack as its middleware layer. For those not in the know (myself included before Adam's talk), according to RailsGuides Rack is:
Rack provides a minimal, modular and adaptable interface for developing web applications in Ruby. By wrapping HTTP requests and responses in the simplest way possible, it unifies and distills the API for web servers, web frameworks, and software in between (the so-called middleware) into a single method call.
Metal is essentially a thin wrapper around the Rack middleware layer of Rails. Why is this important? Well, by dropping down into Metal it's possible to completely bypass the Rails framework and squeeze the absolute maximum performance out of your stack. Specifically this can be useful for a common request to your application where the response time is crucial and you want to avoid the extra overhead of passing through the Rails routing mechanism before serving a response.
OK, so enough talk, what do the numbers look like? This is by no means meant to be a thorough test of all possible permutations of Rails, Sinatra and Metal, rather I'm interested in replacing a simple API method with a Sinatra application and a Metal endpoint. The API I'm testing is the Galaxy Zoo API layer. Within the Galaxy Zoo API we have the concept of 'Assets'. An Asset is something like a SDSS galaxy image and a frequently accessed API url looks like:
http://api_url/api/assets/:id
This API call returns a simple XML snippet that looks something like this:
<?xml version="1.0" encoding="UTF-8"?>
<asset>
<id>1</id>
<location>http://s3.aws.com/1.jpg</location>
<project_id>1</project_id>
<external_ref></external_ref>
</asset>
I used Apache benchmark to test each option. Passenger 2.2.2 / Rails 2.3.2 and my MacBook Pro (2.53 GHz) were used to serve the application. Also, to ensure a reasonably fair test I rebooted the OS for each variant and 'warmed up' Apache by running the test 4 times before taking the benchmark results from the 5th and final time I issued this command:
ab -n 1000 -c 4 http://api_url/api/assets/1
This is basically making 1000 requests with 4 concurrent connections.
OK, so first up I used a standard Rails controller action, the code for which is shown below:
def show
@asset = Asset.find(params[:id])
respond_to do |format|
format.xml { render :xml => @asset.to_xml }
end
end
This came out at a very reasonable 230 requests per second:
Requests per second: 229.64 [#/sec] (mean)
Next up I added in a Sinatra 'application' to respond to the api/assets/:id url. Because of the way that Rails uses Rack, the Sinatra/Metal endpoints are picked up before the Rails routing mechanism kicks in, no modification is therefore required to the routes.rb config to make the Sinatra application pick up the request url.
By default Sinatra/Metal endpoints are picked up if they are placed in the RAILS_ROOT/app/metal/ and have a class name that represents the filename for the Sinatra application:
RAILS_ROOT/app/metal/sinatra_asset.rb
require 'sinatra'
class SinatraAsset < Sinatra::Application
set :environment, 'production'
get '/api/assets/:id' do
Asset.find(params[:id]).to_xml
end
end
Benchmarking Sinatra produces the following results:
Requests per second: 416.61 [#/sec] (mean)
Wow! So we've gone from ~230 requests per second using a standard Rails controller action up to over 400 requests per second using Sinatra. This is obviously a pretty serious speed bump and for really not very much work.
Finally I tested a Metal endpoint to intercept the same request url. Once again, Metal endpoints need to be installed in:
RAILS_ROOT/app/metal/metal_asset.rb
class MetalAsset
def self.call(env)
url_pattern = /^\/api\/assets\/(\d+)$/
if m = env['PATH_INFO'].match(url_pattern)
asset = Asset.find(m[1])
[ 200, {"Content-Type" => "text/xml"}, asset.to_xml]
else
[ 404, {}, '']
end
end
end
So Sinatra was fast - how fast is Metal? Well it's pretty nippy:
Requests per second: 522.12 [#/sec] (mean)
As I mentioned earlier, this is by no means meant to be a through test of how Rails controller actions perform compared to their Sinatra and Metal equivalents, however the numbers are pretty spectacular: a bare Metal endpoint more than doubles the number of requests this application can handle per second. This is not to say that the Sinatra results weren't pretty damn good too - using Sintara gave an 80% speed boost for this simple API request.
It seems clear that a significant speed boost can be had by getting down to 'the metal'. Personally I prefer the clear syntax of Sinatra over the URL regex that Metal requires to achieve the same result, although the additional ~100 requests per second that Metal offers over Sinatra is hard to ignore.
David Heinemeier Hansson talked this week about the refactoring that's going on with the Rails routing mechanism for the upcoming Rails 3 release so it's possible that these numbers could significantly change when Rails 3 makes it into the wild. For now though, if you've got a Rails application with a frequently accessed url, drop in a Sinatra application or a Metal end point and watch it fly!


Somehow I Manage
Pictures worth a thousand words.
This is where I see my family everyday.
My Castle, where my dinner party went wrong.
My five minutes of fame.
The night I proposed... she said no.
I did buy this for myself but it doesn't make it any less true.
The vacation is all inclusive, you know what that means...
This shows both the friends I have and the skills I have.
MILF, also Pam's mom.


Welcome to the Tea Emporium. You can learn about the different types of tea available. You can also learn about Gong Fu Cha, which is a different way of brewing tea.
The Chinese Tea Shop has a very good website about tea. The site makes good use of the head element to prepare the metadata for the website. The website itself is split into different sections, which makes navigation much easier.


At least four dead after massive floods hit southeastern France
ROQUEBRUNE-SUR-ARGENS, France (Reuters) - Four people were found dead on Sunday after massive flooding that has hit southeastern France since Friday, causing major damage in the region, local authorities said.
One person was found dead near Muy, between the towns of Nice and Marseille, after falling off a rescue boat near Muy late on Saturday, the police prefecture of the Var department said in a statement.
Another body was found in a car in Cabasse and two people were found dead in Tanneron, it added.
A 77-year old man has been missing since Saturday morning in Saint-Antonin-du-Var.
Several rivers burst their banks in southeastern France, causing major damage as homes were flooded and cars and boats were swept along by the waters.
Interior Minister Christophe Castaner travelled to the Var on Sunday to meet victims and rescue workers as rain continued to fall in the region, although it was not as heavy as in previous days and floods started to subside.


| iss | bookingDate | classification | bookingNo | prisonerId | sentencingDate | Cmd |
|---|---|---|---|---|---|---|
| ${booking.isSelected} | ${bookingDate | dateFormat } | ${classification} | ${bookingNo} | ${prisonerId} | ${sentencingDate| dateFormat } |
| iss | Srv Provided | Srv Type | Srv DateFrom | Srv DateTo | Transport Method |
Sending Provider |
Designated Provider |
Service Reason |
Cmd |
|---|


BRASSED OFF A film review by Scott Renshaw Copyright 1997 Scott Renshaw
(Miramax) Starring: Pete Postlethwaite, Tara Fitzgerald, Ewan McGregor, Stephen Thompkinson, Jim Carter. Screenplay: Mark Herman. Producer: Steve Abbott. Director: Mark Herman. MPAA Rating: PG-13 (profanity) Running Time: 107 minutes. Reviewed by Scott Renshaw.
Writer/director Mark Herman is so concerned about sounding the trumpet to deliver a "message" in BRASSED OFF that he almost ruins a perfectly good character study. The story is set in the Yorkshire town of Grimley, where Danny (Pete Postlethwaite) prepares to lead into competition the brass band made up of workers at the local colliery (coal mine). Danny seems blissfully unaware of the issue which preoccupies every other band member, including his own son Phil (Stephen Thompkinson): the government program of coal pit closures which is threatening to make Grimley the latest target. Still the band, including a lovely new arrival named Gloria (Tara Fitzgerald), plays on, trying to make progress toward a national competition at the Albert Hall while a union vote over the fate of the colliery looms.
BRASSED OFF is at its best painting a vivid portrait of life in a northern coal town. Long days of hard labor are punctuated by pints with the boys and nearly wordless exchanges between husbands and wives. Meanwhile, the battle of wills between Danny and the other band members points out a profound gap between what the band means to each side. For the players, it is a social club which provides a rare opportunity to blow off steam, demonstrated in an amusing montage of ever-more-inebriated performances. For Danny, the band is a symbol, an enduring tradition and the one beautiful thing in a dark, dusty world.
If Herman had kept his focus on this clash between pragmatism and idealism, best exemplified by the relationship between Danny and Phil (an exceptional performance by Stephen Thompkinson), BRASSED OFF could have been a minor gem. Unfortunately, Herman is determined to make sure we leave the theater enlightened about the injustice of the pit closure program. Phil rails against Margaret Thatcher in a church; Danny uses the band competition as a soapbox for the miners' cause; statistics of job losses roll by as the film ends. Like too many directors of films about social issues, Herman doesn't trust our sympathy for the characters to create all the resonance the story needs. Add an over-dramatized but under-developed romance between Fitzgerald and Ewan McGregor (as a young miner) and you have a film which strays from its strengths. The human drama of BRASSED OFF makes for much sweeter music than strident sermonizing.
On the Renshaw scale of 0 to 10 brass bands: 6.
Visit Scott Renshaw's MoviePage http://www-leland.stanford.edu/~srenshaw Subscribe to receive reviews directly via email See details on the MoviePage
The review above was posted to the
rec.arts.movies.reviews newsgroup (de.rec.film.kritiken for German reviews).
The Internet Movie Database accepts no responsibility for the contents of the
review and has no editorial control. Unless stated otherwise, the copyright
belongs to the author.
Please direct comments/criticisms of the review to relevant newsgroups.
Broken URLs inthe reviews are the responsibility of the author.
The formatting of the review is likely to differ from the original due
to ASCII to HTML conversion.
Related links: index of all rec.arts.movies.reviews reviews


Key2MyHeart is an installation by Luis Fernandez and Douwe Schmidt where you can use your heartbeat to generate a key to send and receive encrypted mail.
To fully enjoy what we are at here, you'll need to learn a bit about PGP, how to use our service and our intentions. Luckily we've got them all covered for you in the three sections below. Enjoy and drop us a word!
We didn't invent this. PGP has been around for millions of years in Internet terms. Learn a bit on the background of the decennia old and ancient technology to send secure messages over the internet.
If you met us in real life, changes are you are actually having a bracelet now that contains the key to your heart. Learn here how to put your key to work and start sending and receiving encrypted messages.
Why, how, when? And what is wrong with us anyway? Read the answers to some of these questions here and learn more about the key2myheart project


RNA-Seq pipeline (aRNApipe)
RNA-Seq pipeline (aRNApipe)
Project: #PROJECT
#LATMENU
#PROG: ALIGNMENT QUALITY METRICS
2D
3D
#TABLE Check the definition of some of these measurements in the
Picard documentation
.


COLL 142 - Week 12
The Final Project
Salvatore "Sal" Testa /@saltesta14
Where did all the time go?
Reading from hardware (traffic light)
Writing to hardware (servos)
What do I do if I have an uncontrollable desire to make low quality music?
Where is my laser-cut music box?
Build the box, format your song, upload it to your music player.


Middle East Participants Gather In Warsaw
6 mins ago
AliSher Azimi
Afghan President Ashraf Ghani Visits Jalalabad
6 mins ago
AliSher Azimi
Coffin Of Slain Japanese Doctor Nakamura Transported To Japan
6 mins ago
AliSher Azimi


In this section you'll learn how to get started with a MEAN.JS application, install all the prerequisites, and initialize your application.
Before you begin, you should make sure you have installed all these prerequisites on your development machine.
$ npm install -g bower
$ npm install -g grunt-cli
$ npm install -g gulp
Note: Your user might not have the permissions to install package globally, so use a super user or sudo.
There are several ways you can get the MEAN.JS boilerplate:
Although the meanjs generator is released, the sub generators are still under development. See the Generator Repo for information on how to use the meanjs generator.
Note: If you want to support git mergeupdates it would be better to use git clonefor your initial project creation, don't worry you'd still be able use the generator.
You can also use Git to directly clone the MEAN.JS repository:
$ git clone https://github.com/meanjs/mean.git meanjs
This will clone the latest version of the MEAN.JS repository to a meanjs folder.
Another way to use the MEAN.JS boilerplate is to download a zip copy of the latest MEAN.JS stable version. You can also do this using wget command:
$ wget https://github.com/meanjs/mean/archive/v0.4.1.zip -O meanjs.zip; unzip meanjs.zip; rm meanjs.zip
Don't forget to rename mean-0.4.1 after your project name.
Once you've installed all the prerequisites, you're just a few steps away from starting to develop you MEAN application.
The first thing you should do is install the Node.js dependencies. The boilerplate comes pre-bundled with a package.json file that contains the list of modules you need to start your application, to learn more about the modules installed visit the NPM & Package.json section.
To install Node.js dependencies you're going to use npm again, just run this in the command-line:
$ npm install
bower install
command to install all the front-end modules needed for the application.After the install process is over, you'll be able to run your application using Grunt, just run grunt default task:
$ gruntYour application should run on the 3000 port so in your browser just go to http://localhost:3000.
After the install process is over, you'll be able to run your application using Gulp, just run gulp default task:
$ gulpYour application should run on the 3000 port so in your browser just go to http://localhost:3000.
That's it! your application should be running by now, to proceed with your development check the other sections in this documentation.
If you encounter any problem try the Troubleshooting section.


xguest_selinux
Section: xguest SELinux Policy documentation (8)Updated: xguest
Index Return to Main Contents
NAME
xguest_u - Least priviledged X user - Security Enhanced Linux PolicyDESCRIPTION
xguest_u is an SELinux User defined in the SELinux policy. SELinux users have default roles, xguest_r. The default role has a default type, xguest_t, associated with it.
The SELinux user will usually login to a system with a context that looks like:
xguest_u:xguest_r:xguest_u:s0-s0:c0.c1023
Linux users are automatically assigned an SELinux users at login. Login programs use the SELinux User to assign initial context to the user's shell.
SELinux policy uses the context to control the user's access.
By default all users are assigned to the SELinux user via the __default__ flag
On Targeted policy systems the __default__ user is assigned to the unconfined_u SELinux user.
You can list all Linux User to SELinux user mapping using:
semanage login -l
If you wanted to change the default user mapping to use the xguest_u user, you would execute:
semanage login -m -s xguest_u __default__
USER DESCRIPTION
The SELinux user xguest_u is defined in policy as a unprivileged user. SELinux prevents unprivileged users from doing administration tasks without transitioning to a different role.
SUDO
The SELinux type xguest_t is not allowed to execute sudo.
X WINDOWS LOGIN
The SELinux user xguest_u is able to X Windows login.
NETWORK
- The SELinux user xguest_u is able to connect to the following tcp ports.
-
dns_port_t: 53
ldap_port_t: 389,636,3268
soundd_port_t: 8000,9433,16001
ipp_port_t: 631,8610-8614
transproxy_port_t: 8081
all ports with out defined types
ftp_port_t: 21,990
kerberos_port_t: 88,750
speech_port_t: 8036
http_cache_port_t: 3128,8080,8118,8123,10001-10010
http_port_t: 80,443,488,8008,8009,8443
ocsp_port_t: 9080
flash_port_t: 843,1935
pulseaudio_port_t: 4713
jabber_client_port_t: 5222,5223
BOOLEANS
SELinux policy is customizable based on least access required. xguest_t policy is extremely flexible and has several booleans that allow you to manipulate the policy and run xguest_t with the tightest access possible.
If you want to allow xguest to configure Network Manager and connect to apache ports, you must turn on the xguest_connect_network boolean.
setsebool -P xguest_connect_network 1
If you want to allow users to connect to mysql, you must turn on the allow_user_mysql_connect boolean.
setsebool -P allow_user_mysql_connect 1
If you want to allow user processes to change their priority, you must turn on the user_setrlimit boolean.
setsebool -P user_setrlimit 1
If you want to control users use of ping and traceroute, you must turn on the user_ping boolean.
setsebool -P user_ping 1
If you want to allow w to display everyone, you must turn on the user_ttyfile_stat boolean.
setsebool -P user_ttyfile_stat 1
If you want to allow regular users direct dri device access, you must turn on the user_direct_dri boolean.
setsebool -P user_direct_dri 1
If you want to allow xguest to use blue tooth devices, you must turn on the xguest_use_bluetooth boolean.
setsebool -P xguest_use_bluetooth 1
If you want to allow user to r/w files on filesystems that do not have extended attributes (FAT, CDROM, FLOPPY), you must turn on the user_rw_noexattrfile boolean.
setsebool -P user_rw_noexattrfile 1
If you want to allow users to run TCP servers (bind to ports and accept connection from the same domain and outside users) disabling this forces FTP passive mode and may change other protocols, you must turn on the user_tcp_server boolean.
setsebool -P user_tcp_server 1
If you want to allow regular users direct mouse access, you must turn on the user_direct_mouse boolean.
setsebool -P user_direct_mouse 1
If you want to allow users to connect to PostgreSQL, you must turn on the allow_user_postgresql_connect boolean.
setsebool -P allow_user_postgresql_connect 1
If you want to allow xguest users to mount removable media, you must turn on the xguest_mount_media boolean.
setsebool -P xguest_mount_media 1
HOME_EXEC
The SELinux user xguest_u is able execute home content files.
TRANSITIONS
Three things can happen when xguest_t attempts to execute a program.
1. SELinux Policy can deny xguest_t from executing the program.
-
2. SELinux Policy can allow xguest_t to execute the program in the current user type.
Execute the following to see the types that the SELinux user xguest_t can execute without transitioning:
sesearch -A -s xguest_t -c file -p execute_no_trans
-
3. SELinux can allow xguest_t to execute the program and transition to a new type.
Execute the following to see the types that the SELinux user xguest_t can execute and transition:
$ sesearch -A -s xguest_t -c process -p transition
COMMANDS
semanage login can also be used to manipulate the Linux User to SELinux User mappings
semanage user can also be used to manipulate SELinux user definitions.
system-config-selinux is a GUI tool available to customize SELinux policy settings.
AUTHOR
This manual page was autogenerated by genuserman.py.SEE ALSO
selinux(8), semanage(8).
Index
- NAME
- DESCRIPTION
- USER DESCRIPTION
- SUDO
- X WINDOWS LOGIN
- NETWORK
- BOOLEANS
- HOME_EXEC
- TRANSITIONS
- COMMANDS
- AUTHOR
- SEE ALSO
This document was created by man2html, using the manual pages.
Time: 05:34:31 GMT, December 24, 2015


| LuaTables Constructor | Constructs a new table collection from the given state. |
| Global | Returns a table representing the global namespace. |
| Registry | Returns a table that can be used for internal storage. |
| Add | Pushes a new table on top of the stack |
| Equals (inherited from Object) | |
| GetHashCode (inherited from Object) | |
| GetType (inherited from Object) | |
| Insert | Inserts a new table to specified location on the stack. |
| Remove | Removes the specified table. |
| ToString (inherited from Object) |


Test polynomials systematically
With this dialog you can systematically generate quadratic polynomials of the form
and evaluate them.
The polynomials are generated by iterating through all combinations of the coefficients a, b and c, that the specification of their intervals allow.
The interval of the independent variable x can be specified in the input field "Values for x".


Profile
Bio Graph
Name : {{student.get_name}}
Year of study : {{student.get_year}}
Branch: {{student.get_branch}}
College : {{student.get_college}}
Degree Pursued : {{student.get_degree_pursued}}
Email :{{student.get_email}}
Phone : {{student.get_mobile_number}}


First, consult the help file for your device type to join the Network.
Conductor
linkThe conductor can control many parameters of the piece including total duration, the duration of each slide, and how long of a blank screen to leave at the start (so, for example, you would not project ‘Ready’ to an audience).
The conductor can also control the dimensions of the score. For an ensemble of mixed phone and tablet (or laptop) devices, Portrait (3x4)
is probably best.
There is also an opportunity to pick colours.  Be careful not to set the foreground and the background to the same colour.
Press start to start the piece. You will be redirected to view the score. Not everyone will see updates at the same time.
If you wish to stop the score once it is running, select ‘Stop’ from the menu in the top left corner.
If you wish to Restart a score that has finished or is currently running, select ‘Restart’ from the menu in the top left corner.
 From the conductor page, select, Shutdown Computer
and then click to shutdown on the next page. The following page should fail to load.
Please wait a minute before unplugging the computer.
You must shut down the computer properly before unplugging it.
Click Change Wifi Password
to set a new wifi password. Leave the password fields blank if you want to leave the wifi passwordless.
Write your new passsword down. It may be a good idea to write it down on the Immrama computer, on a sticker or a post it note.
All users on the first page have access to Show Wifi Password
and can use this to help others log on. Only the Conductor should change or set the password.
This feature not yet implemented


**WORD NOT FOUND**
Sorry, but the API didn't return any definitions. Either the word is misspelled or the word doesn't exist in the dictionary.
Click here to return to main page.


In our 'Water Utilities and Machine Learning' whitepaper, you'll learn how machine learning can help you:
- Identify and repair leaks faster than ever
- Assess the health of your assets and defer investment
- Strengthen your business intelligence through monthly reporting
- Mine data insights from SCADA and GIS databases
After filling out the form below and clicking submit, we will email you the whitepaper.


WITNESS LIST Appropriations Committee March 1, 1999-8:00A Budget On: Bailey Taylor, Sheila (State Office of Administrative Hearings) Brummett, Jay (Texas Real Estate Commission) Francis, Brian (Texas Real Estate Commission) Lanford, Lane (Public Utility Commission) Liner, Renil (Texas Appraiser Licensing Certification Board) McClellan, Suzi (Public Utility Counsel) McKeever, Robin (Public Utility Commission) McNeil, Chas (Funeral Services Commission) Miller, BJ (Funeral Service Commission) Richards, C. David (Funeral Service Commission) Spradlin, Tom (State Securities Board) Thorburn, Wayne (Texas Real Estate Commission) Yeager, Lisabeth (State Office of Administrative Hearings)


--------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------
8
Human Resources Policies
conditions of sale, output, or production (Price Fixing).
Agreeing with
competitor(s)
not to
deal with vendors or distributors,
other competitors, or customers (Group Boycott).
Agreeing with
competitor(s)
to split territories or customers (Territory
or Customer Allocation).
“Agreeing” includes stated or implied, formal or informal, oral or written
understandings, whether created directly with another party or indirectly
through a third party.
Conflict of Interest
Employees are required to disclose or avoid any activity or interest that may be
regarded as a possible conflict with DIPI interest.
Using DIPI time and/or resources and/or influence to promote personal
interests or the interests of third parties.
Holding a second job
with, or consulting for
a competitor,
vendor or
supplier with whom the Company conducts business.
Conducting Company business with related parties or dealing with businesses
in which you or related parties have significant interest.
Gifts and Entertainment
Gifts and entertainment can help build relationships, but they must never influence
decisions, nor should they be considered part of “doing business.” Employees must
always refrain from paying or receiving a bribe intended to influence business
operations or government conduct.
No gift or entertainment should ever be
offered, given, provided or accepted by any Company employee or officer, family
member of an employee or officer, or agent unless it:
is not a cash gift,
is consistent with customary business practices;
cannot be construed as a bribe or payoff; and
Does not violate any laws or DIPI policies.
IX. Relationship with Government Agencies
The DIPI will take whatever steps are necessary to undertake legally appropriate
conduct and continue to develop fair and good faith relationships with all relevant
government agencies.
You must take whatever steps are necessary to develop and maintain fair
relationships with government agencies.
You are prohibited from giving or accepting gifts, entertainment, travel, payments
and other considerations of value to an employee of any governmental agency
unless they are in accordance with the rules and policies established for your
location.
For gifts, entertainment, travel, payments and other considerations of
value that you would like to give to or accept from anyone associated with a
government or government entity, express written approval must be obtained from
the compliance department for your location prior to doing so.
You must not, directly or indirectly, offer, promise, give, or demand a bribe or other


Grand child overriding template section to have no header image and a new property: ${other}
Section introduced before child content.
Grand child overriding child introduced section.


{% extends 'layouts/layout.html' %} {% block pageTitle %} Upload a photo of your passport {% endblock %} {% block content %}
We need a clear photo of the page in your passport that has your name and face on it.
Make sure:


My Resume
Table of contents
SUMMARY
Tonny Pham
Email: its(at)thisdomain
Full-stack developer. 16 years of experience in Software Development. Comprehensive experience in the development lifecycle of many services including e-commerce system, real-time games, streaming applications. Always hunger for challenge and problem-solving. Professional at self-motivation. Familiar with working in a multi-timezone team.
COMPANIES
VELTRA
Tokyo, Japan, 2007/06 ~ Now
Senior Engineer, Lead Engineer
Responsibility
- Design the architecture of the rebuilt system to scale up/out the current complex monolith system
- Review the current system architecture and process, to move to microservice platform
- Review business requirements
- Team building, culture building
Livio (Transfer due to changing equity)
Tokyo, Japan, 2017/01 - 2017/05
Senior Engineer, Project Manager
Responsibility
- Review business requirements
- Design product features, the business flow, and the operation flow
- Review the reusability, maintainability of source codes
- Collaborate third-party influencers with help desk
- Team building, new engineer training
- Organize up promotion plans
Playnext JP Inc.
Tokyo, Japan — 2013/7 - 2016/12
Senior Engineer, Project Manager,
Responsibility
- Guide team to adopt agile development method
- Design the architecture to support a significant amount of CCU on real-time games
- Review business requirements
- Decide the technology stack for each project
- Maintain feature list and manage their priority.
- Manage product’s time to market and product lifecycle
- Collaborate with teams around the world to keep up with new technologies and best practices.
- Train new engineers
Rakuten Inc.
Tokyo, Japan — 2011/04-2013/01
Lead Engineer, Application Engineer, iOS Engineer, Researcher
Responsibility
- Pioneer in developing the product's reviews polarization algorithm, the market’s product recommendation system, data classification and visualization methodology.
- Collaborate with China team, Baidu team to design, review, implement the China E-Commerce platform.
- Design architecture for Indonesia, Taiwan’s group-buy system
- Review, design technology architecture, maintain the Global E-Commerce system
- Build the Bank’s iPad Prototype application
PROJECTS
Veltra Scaling
Tokyo, 2017-2018
Requirements
- Identify the problems of the current system.
- Collaborate with business team to assure correctness of business model in the new platform
- Support Malaysia Team, Philippine Team, and Japan Team
- Design the architecture to support large-scale system with a very high CCU rate
- Team building, culture building
Technology
- Google Cloud Platform as Infrastructure
- Big Table, Google Cloud SQL, Google Datastore, Cassandra, Mysql, Redis as database
- JSON, Protobuf as data transfer protocol
- Golang, Node.js, C, PHP
- Kubernetes, Docker, Google Container Engine
- Elastic Search
GameChanger
Tokyo, 2017
Requirements
- A new platform to connect influencers with advertisers
- Collaborate with business team in Silicon Valley and engineer team in Tokyo
- Manage the project, and time to market
- Make a clear plan for promotion strategy
Technology
- Heroku as the Infrastructure provider
- MongoDB, Redis as the data store
- IronQueue, IronWorker as asynchronous task provider
- Node.js
- Docker as container engine
- Various API and tools
ESportsPlus
Tokyo, San Jose, CA, 2016-2017
Requirements
- Design the architecture for a new real-time platform specialized in fantasy esports (Dota, LOL, etc.)
- Cross-platform service, therefore, requires web, iOS, Android client
- Build and manage the relationship with Esports Organization across the world
- Manage the iOS, Android and web lifecycle
Technology
- GCP as the Infrastructure provider
- MongoDB, Mysql, Redis as the data store
- Paypal, bitwallet as the payment gateway
- Meteor.js as the framework
- Golang
- Docker as container engine
- Various API and tools
SportsPlus
Tokyo, San Jose, CA, 2014-2015-2016
Requirements
- Design the architecture for a new real-time fantasy baseball platform
- Collaborate with US team to conform law issues
- Cross-platform service, requires web, iOS, Android client
- Manage the iOS, Android and web lifecycle
Technology
- AWS as the Infrastructure provider
- MongoDB, Mysql, Redis as the data store
- Paypal as the payment gateway
- Meteor.js as the framework
- NodeJS
- Various API and tools
天下統一スマッシュ
Tokyo, 2014-2015
Requirements
- Design the architecture for a new real-time platform for a real-time games
- Collaborate with Japanese Team and business team to refine requirements
- Cross-platform service, iOS, Android client
- Must support minimum 50k CCU (Stress tested)
Technology
- Node.js, Sails.js
- Mysql
- Redis
- HAProxy
- Twemproxy
Assassin’s Creeds: Memories
Tokyo, Santa Clara CA, 2013-2014
Requirements
- Design the architecture for a new real-time platform for a realtime games
- Collaborate with Japanese Team and business team to refine the requirement
- Cross-platform service, iOS, Android client
- Must support minimum 50k CCU (Stress tested)
Technology
- Php
- HTML5
- CSS3
- BackboneJS
- Cassandra
- Mysql
- Code Igniter
- Node.js
iPad Bank Application
San Francisco, CA — 2012
- Bank application that allows the user to see balance, transfer money.
- iOS
Global E-Commerce merchant platform
Tokyo — 2012
Requirement
- Design application stack
- Moving from the traditional server-based to Cloud Foundry- based
- Support all browsers
- Collaborate with design team to provide best practice
- Lead a team of 20 engineers
Technology
- Ruby on Rails
- Redis
- Cloudfoundry
- MySQL
- HTML5
- Coffee Script
- RSpec
- Nokogirina
Taiwan, Indonesia E-commerce Merchant Platform
Tokyo, Japan — 2011-2012
Responsiblity
- Maintain and add new features to existing system Add the Group-buy function to the existing platform.
- Collaborate with China business team to solve constant law changing issue
- Collaborate with new payment systems in China
Technology
- Oracle DB
- Java 6
- Tomcat 6
- Flare
- Memcache
- Thrift
- Rabbitmq
- Salesforce API
Big data, machine learning, data visualization, data mining, articles clustering
Tokyo, Japan — 2009, 2010, 2011
- Mining useful information from the set of user-generated content
- Create prototype demonstrates the usabilities of researched result
Technology
- PHP
- Ruby
- Java
- Erlang
- MySQL
- Mecab
- Cabocha


Try out our Premium Member services: Virtual Legal Assistant, Query Alert Service and an ad-free experience. Free for one month and pay only if you like it.
-1- IN THE HIGH COURT OF KARNATAKA AT BANGALORE DATED THIS THE 10th DAY OF SEPTEMBER 2014 PRESENT THE HON'BLE MR.D.H.WAGHELA, CHIEF JUSTICE AND THE HON'BLE MR.JUSTICE ASHOK B HINCHIGERI WP No.14520/2014(GM-MMS) BETWEEN SRI.C.V.MATHEW KUTTY S/O C.M.VARKEY AGE:65 YEARS, R/O SHIVAPURA VILLAGE, KARKALA TALUK, UDUPI DISTRICT ... PETITIONER (By Sri. R.MANJUNATH, ADV. FOR Sri. ANANDA SHETTY A, ADV.,) AND 1. THE INCHARGE MINES AND GEOLOGY DEPRTMENT, REPRESENTED BY ITS DIRECTOR SANTHEKATTE-576105 TALUK:UDUPI, DISTRICT:UDUPI 2. THE DEPUTY DIRECTOR MINES & GEOLOGY DEPARTMENT, MANGALORE-575001 3. THE DIRECTOR MINES & GEOLOGY DEPARTMENT, BANGLAORE-560001 4. THE KARNATAKA POLLUTION CONTROL BOARD, REPRESENTED BY MEMBER SECRETARY NO.36, SHIVAPURA INDUSTRIAL AREA MANIPAL-576104 -2- 5. THE KARNATAKA POLLUTION CONTROL BOARD, BY ITS MEMBER SECRETARY, PLOT NO. 1 TO 5, NO.45, CHURCH STREET, BANGALORE-560001. 6. THE DEPUTY CHIEF CONTROLLER OF EXPLOSIVES MANGALORE-575001 7. THE DEPUTY COMMISSIONER UDUPI DISTRICT UDUPI-576100 8. THE TAHSILDAR KARKALA TALUK, KARKALA-575104 9. SRI.ASHOK HEGDE S/O K.H.HEGDE AGE:50 YEARS, R/O 'ASHIRWAD' SHIVAPURA VILLAGE & POST, KARKALA TALUK-576112 UDUPI DISTRICT ... RESPONDENTS (By Sri.D.NAGARAJ, AGA FOR R.1 TO 3, 7,8 Sri.R.RAMACHANDRAN, ADV. FOR R.5 Sri.JAYAKUMAR S.PATIL, SR.ADV. FOR SRI.K.CHANDRASHEKAR, ADV. FOR R.9 R.4 AND 6 SERVED) THIS WRIT PETITION IS FILED UNDER ARTICLES 226 AND 227 OF THE CONSTITUTION OF INDIA PRAYING TO DIRECT R-1 TO CONSIDER THE REPRESENTATIONS AS WELL AS THE REMINDERS FILED BY HIM FOR TAKING ACTION AGAINST THE QUARRYING AS WELL AS THE CRUSHING OF THE JELLY IN SY.NO.216 OF SHIVAPURA VILLAGE, KARKALA TALUK, UDUPI DISTRICT PURSUANT TO THE REPRESENTATION DATED 08.06.2012 VIDE ANNEXURE-C & FOLLOWED BY REMINDERS DATED 11.09.2012 AS PER ANNEXURE-D & DATED 11.09.2012 AS PER ANNEXURE-D & DATED 14.08.2013 AS PER ANNEXURE-E AND ETC., THIS WRIT PETITION COMING ON FOR PRELIMINARY HEARING THIS DAY, CHIEF JUSTICE MADE THE FOLLOWING: -3- ORDER
D.H.WAGHELA, C.J. (Oral) :
1. The petitioner has invoked Articles 226 and 227 of the Constitution with the prayer to issue a writ of mandamus directing respondent No.1 to consider representations as well as reminders filed by him for taking action against the quarrying as well as crushing of jelly in Sy.No.216 of Shivapura Village, Karkala Taluk, Udupi District.
2. Upon notice being issued, the respondents concerned have filed their statements of objections and respondent No.9, against whom serious allegations are made, has stated on oath that the petitioner has suppressed several true facts regarding agreement of sale, dated 28.05.2011 with respondent No.9 in respect of several parcels of land including Sy.No.216/2. It is also alleged that after payment of substantial sale consideration, respondent No.9 has initiated litigation in the form of OS No.59/2012 before the Court of Senior Civil Judge and ACJM, Karkala, for specific performance, which suit is pending. It is further stated that the schedule property referred in the writ petition i.e., -4- Sy.No.216 is government land and there is no quarrying activity thereat either by respondent No.9 or any other person, as contended.
3. Thus in short, the petition raises not only questions of disputed facts but appears to be suppressing certain material facts and under such circumstances, the petition is not required to be entertained. However, in view of the allegations made about damage to trees and plantation on account of alleged industrial activity of stone crushing, etc., by respondent No.9, the petitioner is permitted to make appropriate application with all the necessary details to the local office of the Karnataka State Pollution Control Board, even as one complaint already appears to have been made as early as in August 2013. It is stated on behalf of the State Pollution Control Board, respondent No.5, that upon a proper complaint being received with all the relevant and essential facts, action will be taken in accordance with law in respect of violation, if any, of the provisions of the Air (Prevention and Control of Pollution) Act, 1981 and Water (Prevention and Control of Pollution) Act, 1974. Upon that -5- statement being made and recorded, the petition does not survive for any further consideration and accordingly it is disposed as dismissed, with no order as to cost.
Sd/-
CHIEF JUSTICE Sd/-
JUDGE mv


Where do you want to meet?
Proceed
results here
Update Locations
Share this link in the chat window so your friends can add their locations
Add/Update Location
MeetApp!
Here are our picks


| Convolution | Start Time | Stop Time | Elapsed Time |
|---|---|---|---|
| Square * Square | 8:43:18 | 8:43:36 | 18 seconds |
| Square * 2D_Gaussian | 8:43:37 | 8:43:55 | 18 seconds |
| Sobel_X * Square | 8:44:02 | 8:44:02 | 0 |
| Sobel_Y * Square | 8:44:05 | 8:44:05 | 0 |
| Square * Noisy Image | 8:44:09 | 8:45:23 | 74 seconds |
| 2D_Gaussian * Noisy Image | 8:45:24 | 8:46:39 | 75 seconds |
|
Part A - Square * Square As the kernel moves over the image we see a global averaging at each point. The outer points that have little overlap between the kernel and then original input signal thus tend to be darker especially when scaled in comparison to the other points in the image that have significantly more overlap between convolution kernel and input signal. The overall effect is a smoothing and softening effect with the corners rounding out instead of having the hard edges. The intense white is found only in the middle sections both up and down and right to left because that is where the most overlap occurs. Part B - Square * 2-D Gaussian The same kind of filtering is going on with this part as part A in that an overall smoothing and averaging of the image occurs. As the Gaussian moves over the image it is creating an average of the part of the image that it is superimposed over. The difference is that the averaging is a more weighted average with the value of the image at the center of the kernel having a greater weight than the values at the outer edge of the kernel. Because the weighting is more localized we see the image closer to it's original form than with the White_Box filter with only a slight rounding of the edges from the points on the edge that are weighted with the values outside of the image (those that register as 0). Part C - Sobel * Square The kernels obviously act like dirty filters changing the light colors to darker shades. The alteration has to do with the positive and negatives that are opposite from one another in the kernel and subtract the values and produce relative uniform output. The band on the outer edge is produced according to the orientation of the convolution kernel. Part E - 2D_Gaussian Function * Noisy Image They both removed a large portion of the noise from the image. The White_Box function removed the noise, but introduced a large amount of blur into the convolved image. The Gaussian did better at removing the noise while retaining a cleaner copy of the original image. This is due to the fact that the Gaussian produces a more weighted local average of the image. The White Box image produces a more general average of the image and thus takes into account other parts of the image that degraded the clarity and sharpness of the resulting image. Part F - The Message Give instruction to a wise man, and he will be yet the wiser |


--- layout: post status: publish published: true title: Regarding ECMA-234 author: display_name: Tomas Restrepo login: tomasr email<EMAIL_ADDRESS>url: http://winterdom.com/ author_login: tomasr author_email<EMAIL_ADDRESS>author_url: http://winterdom.com/ wordpress_id: 510 wordpress_url: http://winterdom.com/2002/03/regardingecma234 date: '2002-03-31 15:14:13 +0000' date_gmt: '2002-03-31 15:14:13 +0000' categories: - ".NET" tags: [] comments: [] ---
Regarding ECMA-234, Richard Birkby was kind enough to mention this:
"IIRC, this was an attempt by Sun and others to prevent Windows 95 (and hence
Win32) becoming popular. You see, they had created WABI (Windows Application
Binary Interface) for emulating the Windows API on Unix (think WINE). But,
it only supported Win16. So obviously, if every application became 32 bit,
Sun would have to put a lot of resources into updating WABI.
Their approach was to attempt to standardize the Win16 API hoping this would
stall Microsoft..."


Hey, my name is Alex but everybody calls me 〈binti〉 I was born in
1992 "a good year I say "
I don't have unusual hobbies, I don't belive in horoscope, I'm not superstitious, and
at the moment I have no idea what I should write in this section
I do what every other people do : eat, sleep, fooling around, hitting the gym from time to time aaaand traveling.
Yeah, i really enjoy traveling. Here you can take a sneaky peek from the 2017 summer.


South Australia Braces For Catastrophic Bushfire Danger And Record-Breaking Temperatures
It’s set to be a hot and windy day through South Australia with temperatures above 40 degrees forecast across the State.
With firefighters preparing for the extreme weather, ‘catastrophic’ fire danger warnings remain in place for the West Coast, Eastern Eyre Peninsula, Lower Eyre Peninsula, Mid North, Mount Lofty Ranges, Yorke Peninsula and Kangaroo Island districts.
Total fire bans have been declared in 16 districts and no part of South Australia has a fire risk rating lower than ‘severe’.
The CFS urges residents to action their Bushfire Survival plans and contact 000 in an emergency.
On Tuesday afternoon, the Department of Education announced more than 100 government schools would be closed Wednesday (head HERE for the full list).
A severe weather warning for damaging winds has also been issued for West Coast, Lower Eyre Peninsula, Eastern Eyre Peninsula, Yorke Peninsula, Kangaroo Island and parts of Mount Lofty Ranges, Mid North and North West Pastoral districts.


Fashion Notes: Melania Trump Touchdowns in Burberry, Celine for Football Game
First Lady Melania Trump scored a touchdown when she arrived in Alabama for a college football game, alongside President Trump, in winter crisp black cashmere and luxury sunglasses.
Melania Trump traveled to Tuscaloosa, Alabama with her husband for a college football game wearing a cashmere-wool blend peacoat by Burberry — the London-based house that former Givenchy creative director Riccardo Tisci has recently rebranded. The coat features a large lapel covered in a knit sweater.
The long-waisted black coat was paired with oversized aviator acetate shades by Celine, a departure from her usual Yves Saint Laurent sunglasses. The shades retail for about $500.
Of course, what Mrs. Trump look is complete without her favorite style of Manolo Blahniks. This pair of Manolos are black to match the look and suede for the ultimate winter vibe.
John Binder is a reporter for Breitbart News. Follow him on Twitter at @JxhnBinder.


The Geise research group seeks to develop structure/property/ processing relationships to guide polymeric materials design for membrane-based liquid separation and energy applications by understanding the influence of nano- and molecular-scale interactions and phenomena on mass transfer and system-level performance.
We are located in the Department of Chemical Engineering at the University of Virginia.
Within the next 10 years, the United Nations predicts that nearly two-thirds of the world’s population may find themselves living in a water stressed area. Today, the vast majority of desalination processes are performed using polymer-based membranes. Improved membranes are needed to meet the challenges of economically and sustainably purifying increasingly saline and contaminated water sources around the globe.
Read MoreOur research focuses on experimental studies aimed at solving fundamental and practical problems related to water and ion transport through polymers that could be used as membranes in a variety of water and energy applications. Providing sustainable and economic supplies of purified water and clean energy solutions is a critical global challenge for the future, and polymer membranes will play a key role in these efforts. We seek to rationally tailor and design polymers at the molecular level and process those polymers to engineer advanced membrane materials that will expand access to clean water and enhance the use of renewable energy sources.
Meet the Geise GroupEnergy demand around the globe is projected to increase by more than 50% over the next 35 years, and sustainable, low-carbon footprint energy resources are needed to meet this increasing energy demand. Technologies such as large-scale flow batteries, reverse electrodialysis, and capacitive mixing rely on polymer membranes to regulate ion transport. Improved membrane selectivity will enable advances in renewable energy storage and generation technologies.
Read More
Congratulations to graduate student Huan Zhang for earning his M.E. degree in chemical engineering!
Additionally, Prof. Geise gave invited talks on group research activities related to the influence of polymer backbone rigidity on water/salt selectivity and ion specific effects in charged polymer membrane materials for water and energy applications at the 14th Pacific Polymer Conference and the Pacifichem 2015 meeting, respectively.
Drew Biedermann (pictured below) presented his research at the undergraduate student poster session at the 2015 AIChE Annual Meeting in Salt Lake City. His poster was titled, "Concentration Dependence of Transport and Sorption Behavior of NaCl in Disulfonated Poly(Arylene Ether Sulfone) Membranes". Additionally, at the meeting, Professor Geise gave a presentation highlighting the group's research efforts.
Geise research group work on membrane polymers for water purification and desalination was featured in a U.Va. Today article.
[August 2015] Article accepted for publication in Environmental Science"Reducing nitrogen crossover in microbial reverse-electrodialysis cells by using adjacent anion exchange membranes and anion exchange resin" has been accepted for publication in the RSC journal Environmental Science: Water Research & Technology
Professor Geise was featured in the Spring 2015 edition of ChE News at U.Va.Read the article "Tuning Polymer Membranes for Water and Energy Applications" in the Spring 2015 edition of ChE News at U.Va.
[June 2015] Article accepted for publication in the Journal of Membrane Science"Water and salt transport properties of zwitterionic polymer films" has been accepted for publication in the Journal of Membrane Science.
[May 2015] Geise research group welcomes graduate student Huan ZhangGraduate student Huan Zhang (Tsinghua University) has joined the Geise Research Group.
[March 2015] Prof. Geise wins NAMS Young Membrane Scientist AwardThe North American Membrane Society (NAMS) awarded Prof. Geise the Young Membrane Scientist Award, which will be presented at the NAMS 2015 meeting held in Boston in early June.
[February 2015] Invited lecture: Prof. Geise at the Advances in Materials and Processes for Polymeric Membrane Mediated Water Purification meetingProf. Geise delivered an invited presentation titled Ion sorption and transport in charged polymers for membrane applications at the Advances in Materials and Processes for Polymeric Membrane Mediated Water Purification meeting in Pacific Grove, CA.
[December 2014] Invited lecture: Prof. Geise at the Macromex 2014 meetingProf. Geise delivered an invited presentation titled Structure/property relationships in polymer membranes for water and energy at the Macromex 2014 meeting in Nuevo Vallarta.
[November 2014] Geise research group welcomes new graduate students Yuanyuan Ji and Tianyi XueGraduate students Yuanyuan Ji (Tianjin University) and Tianyi Xue (Tsinghua University) have joined the Geise Research Group.
[August 2014] Article accepted for publication in Physical Chemistry Chemical Physics"Specific ion effects on membrane potential and the permselectivity of ion exchange membranes" has been accepted for publication in the RSC journal Physical Chemistry Chemical Physics.
[July 2014] Prof. Geise named an Excellence in Diversity Fellow at U.Va.Prof. Geise was awarded a 2014-2015 Excellence in Diversity Fellowship at the University of Virginia.


×
Assigned Nodes
Name
IP Address
Status
{{instance.name}}
{{instance.instanceIP}}
{{instance.instanceState}}


Summoner Brynthea:
Oh my, it seems that you have forgotten the rule about touching the opponent's creature! You lose. Now I shall have that ugly Arcana Card of yours.
Ask for another battle.


{% extends 'logged_base.html' %} {% block detail %}
Click on any of them to navigate to its url, or open it all with just a button in the Dashboard.
{% else %}Start collecting your favorite links in it with the "Add Link" button and open it all with just a button in the Dashboard.
{% endif %}


Name
M/Z
RT
0
Pending Updates
points. Progress:
unknown
MZ:
[
,
]
RT:
[
,
]
INT:
[
,
]
Help
Parameter Settings
Number of Points:
Jump to Window:
min
max
M/Z
RT
Logarithmic Height Scaling:
Scale Height
Scaling Factor:
Use Cylinders
Jump To:
Next Untraced Point
Label Precision:
M/Z
RT
Intensity
Guard Rail Size:
Colorblind Mode
Display Button Tooltips


Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) <IP_ADDRESS>.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. Fri Mar 10 23:28:29 2017 Command Line: synthesis -f SevenSegClock_SevenSegClock_lattice.synproj -gui Synthesis options: The -a option is MachXO2. The -s option is 5. The -t option is TQFP144. The -d option is LCMXO2-640UHC. Using package TQFP144. Using performance grade 5. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-640UHC ### Package : TQFP144 ### Speed : 5 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = AutoShift. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = TRUE Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p C:/Users/Justin/Dropbox/Projects/7SegClock/Lattice_FPGA (searchpath added) -p C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data (searchpath added) -p C:/Users/Justin/Dropbox/Projects/7SegClock/Lattice_FPGA/SevenSegClock (searchpath added) -p C:/Users/Justin/Dropbox/Projects/7SegClock/Lattice_FPGA (searchpath added) Verilog design file = C:/Users/Justin/Dropbox/Projects/7SegClock/Lattice_FPGA/SevenSegClock/source/AutoShift_1.v NGD file = SevenSegClock_SevenSegClock.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v. VERI-1482 Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Top module name (Verilog): AutoShift INFO - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(9): compiling module AutoShift. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH(NOM_FREQ="3.50"). VERI-1018 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(86): RedD1 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(86): Seg should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(86): GrnD1 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(86): Seg should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(86): ledA1 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(87): RedD2 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(87): Seg should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(87): GrnD2 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(87): Seg should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(87): ledA2 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(88): RedD3 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(88): Seg should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(88): GrnD3 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(88): Seg should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(88): ledA3 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(89): RedD4 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(89): Seg should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(89): GrnD4 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(89): Seg should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(89): ledA4 should be on the sensitivity list. VERI-1221 WARNING - synthesis: c:/users/justin/dropbox/projects/7segclock/lattice_fpga/sevensegclock/source/autoshift_1.v(136): expression size 32 truncated to fit in target size 12. VERI-1209 Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga. Package Status: Final Version 1.42. Top-level module name = AutoShift. GSR will not be inferred because no asynchronous signal was found in the netlist. INFO - synthesis: Register tmp_i1 of type IFS1P3DX will not be replicated. Applying 200.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in AutoShift_drc.log. Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'... All blocks are expanded and NGD expansion is successful. Writing NGD file SevenSegClock_SevenSegClock.ngd. ################### Begin Area Report (AutoShift)###################### Number of register bits => 302 of 964 (31 % ) CCU2D => 14 FD1P3AY => 1 FD1P3IX => 6 FD1S3AX => 203 FD1S3AY => 1 FD1S3IX => 6 GSR => 1 IB => 4 IFS1P3DX => 1 LUT4 => 90 OB => 85 OFS1P3IX => 84 OSCH => 1 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 4 Net : osc_clk_c_c, loads : 111 Net : clk_c, loads : 95 Net : latch_c, loads : 84 Net : pwm_c, loads : 12 Clock Enable Nets Number of Clock Enables: 1 Top 1 highest fanout Clock Enables: Net : Led_6_N_104_0, loads : 15 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : n949, loads : 84 Net : Led_6_N_104_0, loads : 15 Net : Seg_4, loads : 11 Net : Seg_3, loads : 11 Net : Seg_5, loads : 10 Net : Seg_2, loads : 10 Net : Seg_1, loads : 10 Net : Seg_0, loads : 10 Net : Seg_6, loads : 8 Net : Led_5, loads : 6 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk3 [get_nets pwm_c] | -| -| 0 | | | create_clock -period 5.000000 -name | | | clk2 [get_nets latch_c] | -| -| 0 | | | create_clock -period 5.000000 -name | | | clk1 [get_nets clk_c] | 200.000 MHz| 568.182 MHz| 1 | | | create_clock -period 5.000000 -name | | | clk0 [get_nets osc_clk_c_c] | 200.000 MHz| 149.745 MHz| 4 * | | | -------------------------------------------------------------------------------- 1 constraints not met. Peak Memory Usage: 52.418 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.577 secs --------------------------------------------------------------