import logging import sys from typing import TYPE_CHECKING, Any, FrozenSet, Iterable, Optional, Tuple, Union, cast from pip._vendor.packaging.specifiers import InvalidSpecifier, SpecifierSet from pip._vendor.packaging.utils import NormalizedName, canonicalize_name from pip._vendor.packaging.version import Version from pip._vendor.packaging.version import parse as parse_version from pip._vendor.pkg_resources import Distribution from pip._internal.exceptions import HashError, MetadataInconsistent from pip._internal.models.link import Link, links_equivalent from pip._internal.models.wheel import Wheel from pip._internal.req.constructors import ( install_req_from_editable, install_req_from_line, ) from pip._internal.req.req_install import InstallRequirement from pip._internal.utils.misc import dist_is_editable, normalize_version_info from pip._internal.utils.packaging import get_requires_python from .base import Candidate, CandidateVersion, Requirement, format_name if TYPE_CHECKING: from .factory import Factory logger = logging.getLogger(__name__) BaseCandidate = Union[ "AlreadyInstalledCandidate", "EditableCandidate", "LinkCandidate", ] def as_base_candidate(candidate: Candidate) -> Optional[BaseCandidate]: """The runtime version of BaseCandidate.""" base_candidate_classes = ( AlreadyInstalledCandidate, EditableCandidate, LinkCandidate, ) if isinstance(candidate, base_candidate_classes): return candidate return None def make_install_req_from_link(link, template): # type: (Link, InstallRequirement) -> InstallRequirement assert not template.editable, "template is editable" if template.req: line = str(template.req) else: line = link.url ireq = install_req_from_line( line, user_supplied=template.user_supplied, comes_from=template.comes_from, use_pep517=template.use_pep517, isolated=template.isolated, constraint=template.constraint, options=dict( install_options=template.install_options, global_options=template.global_options, hashes=template.hash_options, ), ) ireq.original_link = template.original_link ireq.link = link return ireq def make_install_req_from_editable(link, template): # type: (Link, InstallRequirement) -> InstallRequirement assert template.editable, "template not editable" return install_req_from_editable( link.url, user_supplied=template.user_supplied, comes_from=template.comes_from, use_pep517=template.use_pep517, isolated=template.isolated, constraint=template.constraint, options=dict( install_options=template.install_options, global_options=template.global_options, hashes=template.hash_options, ), ) def make_install_req_from_dist(dist, template): # type: (Distribution, InstallRequirement) -> InstallRequirement project_name = canonicalize_name(dist.project_name) if template.req: line = str(template.req) elif template.link: line = f"{project_name} @ {template.link.url}" else: line = f"{project_name}=={dist.parsed_version}" ireq = install_req_from_line( line, user_supplied=template.user_supplied, comes_from=template.comes_from, use_pep517=template.use_pep517, isolated=template.isolated, constraint=template.constraint, options=dict( install_options=template.install_options, global_options=template.global_options, hashes=template.hash_options, ), ) ireq.satisfied_by = dist return ireq class _InstallRequirementBackedCandidate(Candidate): """A candidate backed by an ``InstallRequirement``. This represents a package request with the target not being already in the environment, and needs to be fetched and installed. The backing ``InstallRequirement`` is responsible for most of the leg work; this class exposes appropriate information to the resolver. :param link: The link passed to the ``InstallRequirement``. The backing ``InstallRequirement`` will use this link to fetch the distribution. :param source_link: The link this candidate "originates" from. This is different from ``link`` when the link is found in the wheel cache. ``link`` would point to the wheel cache, while this points to the found remote link (e.g. from pypi.org). """ is_installed = False def __init__( self, link, # type: Link source_link, # type: Link ireq, # type: InstallRequirement factory, # type: Factory name=None, # type: Optional[NormalizedName] version=None, # type: Optional[CandidateVersion] ): # type: (...) -> None self._link = link self._source_link = source_link self._factory = factory self._ireq = ireq self._name = name self._version = version self.dist = self._prepare() def __str__(self): # type: () -> str return f"{self.name} {self.version}" def __repr__(self): # type: () -> str return "{class_name}({link!r})".format( class_name=self.__class__.__name__, link=str(self._link), ) def __hash__(self): # type: () -> int return hash((self.__class__, self._link)) def __eq__(self, other): # type: (Any) -> bool if isinstance(other, self.__class__): return links_equivalent(self._link, other._link) return False @property def source_link(self): # type: () -> Optional[Link] return self._source_link @property def project_name(self): # type: () -> NormalizedName """The normalised name of the project the candidate refers to""" if self._name is None: self._name = canonicalize_name(self.dist.project_name) return self._name @property def name(self): # type: () -> str return self.project_name @property def version(self): # type: () -> CandidateVersion if self._version is None: self._version = parse_version(self.dist.version) return self._version def format_for_error(self): # type: () -> str return "{} {} (from {})".format( self.name, self.version, self._link.file_path if self._link.is_file else self._link, ) def _prepare_distribution(self): # type: () -> Distribution raise NotImplementedError("Override in subclass") def _check_metadata_consistency(self, dist): # type: (Distribution) -> None """Check for consistency of project name and version of dist.""" canonical_name = canonicalize_name(dist.project_name) if self._name is not None and self._name != canonical_name: raise MetadataInconsistent( self._ireq, "name", self._name, dist.project_name, ) parsed_version = parse_version(dist.version) if self._version is not None and self._version != parsed_version: raise MetadataInconsistent( self._ireq, "version", str(self._version), dist.version, ) def _prepare(self): # type: () -> Distribution try: dist = self._prepare_distribution() except HashError as e: # Provide HashError the underlying ireq that caused it. This # provides context for the resulting error message to show the # offending line to the user. e.req = self._ireq raise self._check_metadata_consistency(dist) return dist def _get_requires_python_dependency(self): # type: () -> Optional[Requirement] requires_python = get_requires_python(self.dist) if requires_python is None: return None try: spec = SpecifierSet(requires_python) except InvalidSpecifier as e: message = "Package %r has an invalid Requires-Python: %s" logger.warning(message, self.name, e) return None return self._factory.make_requires_python_requirement(spec) def iter_dependencies(self, with_requires): # type: (bool) -> Iterable[Optional[Requirement]] requires = self.dist.requires() if with_requires else () for r in requires: yield self._factory.make_requirement_from_spec(str(r), self._ireq) yield self._get_requires_python_dependency() def get_install_requirement(self): # type: () -> Optional[InstallRequirement] return self._ireq class LinkCandidate(_InstallRequirementBackedCandidate): is_editable = False def __init__( self, link, # type: Link template, # type: InstallRequirement factory, # type: Factory name=None, # type: Optional[NormalizedName] version=None, # type: Optional[CandidateVersion] ): # type: (...) -> None source_link = link cache_entry = factory.get_wheel_cache_entry(link, name) if cache_entry is not None: logger.debug("Using cached wheel link: %s", cache_entry.link) link = cache_entry.link ireq = make_install_req_from_link(link, template) assert ireq.link == link if ireq.link.is_wheel and not ireq.link.is_file: wheel = Wheel(ireq.link.filename) wheel_name = canonicalize_name(wheel.name) assert name == wheel_name, f"{name!r} != {wheel_name!r} for wheel" # Version may not be present for PEP 508 direct URLs if version is not None: wheel_version = Version(wheel.version) assert version == wheel_version, "{!r} != {!r} for wheel {}".format( version, wheel_version, name ) if ( cache_entry is not None and cache_entry.persistent and template.link is template.original_link ): ireq.original_link_is_in_wheel_cache = True super().__init__( link=link, source_link=source_link, ireq=ireq, factory=factory, name=name, version=version, ) def _prepare_distribution(self): # type: () -> Distribution return self._factory.preparer.prepare_linked_requirement( self._ireq, parallel_builds=True ) class EditableCandidate(_InstallRequirementBackedCandidate): is_editable = True def __init__( self, link, # type: Link template, # type: InstallRequirement factory, # type: Factory name=None, # type: Optional[NormalizedName] version=None, # type: Optional[CandidateVersion] ): # type: (...) -> None super().__init__( link=link, source_link=link, ireq=make_install_req_from_editable(link, template), factory=factory, name=name, version=version, ) def _prepare_distribution(self): # type: () -> Distribution return self._factory.preparer.prepare_editable_requirement(self._ireq) class AlreadyInstalledCandidate(Candidate): is_installed = True source_link = None def __init__( self, dist, # type: Distribution template, # type: InstallRequirement factory, # type: Factory ): # type: (...) -> None self.dist = dist self._ireq = make_install_req_from_dist(dist, template) self._factory = factory # This is just logging some messages, so we can do it eagerly. # The returned dist would be exactly the same as self.dist because we # set satisfied_by in make_install_req_from_dist. # TODO: Supply reason based on force_reinstall and upgrade_strategy. skip_reason = "already satisfied" factory.preparer.prepare_installed_requirement(self._ireq, skip_reason) def __str__(self): # type: () -> str return str(self.dist) def __repr__(self): # type: () -> str return "{class_name}({distribution!r})".format( class_name=self.__class__.__name__, distribution=self.dist, ) def __hash__(self): # type: () -> int return hash((self.__class__, self.name, self.version)) def __eq__(self, other): # type: (Any) -> bool if isinstance(other, self.__class__): return self.name == other.name and self.version == other.version return False @property def project_name(self): # type: () -> NormalizedName return canonicalize_name(self.dist.project_name) @property def name(self): # type: () -> str return self.project_name @property def version(self): # type: () -> CandidateVersion return parse_version(self.dist.version) @property def is_editable(self): # type: () -> bool return dist_is_editable(self.dist) def format_for_error(self): # type: () -> str return f"{self.name} {self.version} (Installed)" def iter_dependencies(self, with_requires): # type: (bool) -> Iterable[Optional[Requirement]] if not with_requires: return for r in self.dist.requires(): yield self._factory.make_requirement_from_spec(str(r), self._ireq) def get_install_requirement(self): # type: () -> Optional[InstallRequirement] return None class ExtrasCandidate(Candidate): """A candidate that has 'extras', indicating additional dependencies. Requirements can be for a project with dependencies, something like foo[extra]. The extras don't affect the project/version being installed directly, but indicate that we need additional dependencies. We model that by having an artificial ExtrasCandidate that wraps the "base" candidate. The ExtrasCandidate differs from the base in the following ways: 1. It has a unique name, of the form foo[extra]. This causes the resolver to treat it as a separate node in the dependency graph. 2. When we're getting the candidate's dependencies, a) We specify that we want the extra dependencies as well. b) We add a dependency on the base candidate. See below for why this is needed. 3. We return None for the underlying InstallRequirement, as the base candidate will provide it, and we don't want to end up with duplicates. The dependency on the base candidate is needed so that the resolver can't decide that it should recommend foo[extra1] version 1.0 and foo[extra2] version 2.0. Having those candidates depend on foo=1.0 and foo=2.0 respectively forces the resolver to recognise that this is a conflict. """ def __init__( self, base, # type: BaseCandidate extras, # type: FrozenSet[str] ): # type: (...) -> None self.base = base self.extras = extras def __str__(self): # type: () -> str name, rest = str(self.base).split(" ", 1) return "{}[{}] {}".format(name, ",".join(self.extras), rest) def __repr__(self): # type: () -> str return "{class_name}(base={base!r}, extras={extras!r})".format( class_name=self.__class__.__name__, base=self.base, extras=self.extras, ) def __hash__(self): # type: () -> int return hash((self.base, self.extras)) def __eq__(self, other): # type: (Any) -> bool if isinstance(other, self.__class__): return self.base == other.base and self.extras == other.extras return False @property def project_name(self): # type: () -> NormalizedName return self.base.project_name @property def name(self): # type: () -> str """The normalised name of the project the candidate refers to""" return format_name(self.base.project_name, self.extras) @property def version(self): # type: () -> CandidateVersion return self.base.version def format_for_error(self): # type: () -> str return "{} [{}]".format( self.base.format_for_error(), ", ".join(sorted(self.extras)) ) @property def is_installed(self): # type: () -> bool return self.base.is_installed @property def is_editable(self): # type: () -> bool return self.base.is_editable @property def source_link(self): # type: () -> Optional[Link] return self.base.source_link def iter_dependencies(self, with_requires): # type: (bool) -> Iterable[Optional[Requirement]] factory = self.base._factory # Add a dependency on the exact base # (See note 2b in the class docstring) yield factory.make_requirement_from_candidate(self.base) if not with_requires: return # The user may have specified extras that the candidate doesn't # support. We ignore any unsupported extras here. valid_extras = self.extras.intersection(self.base.dist.extras) invalid_extras = self.extras.difference(self.base.dist.extras) for extra in sorted(invalid_extras): logger.warning( "%s %s does not provide the extra '%s'", self.base.name, self.version, extra, ) for r in self.base.dist.requires(valid_extras): requirement = factory.make_requirement_from_spec( str(r), self.base._ireq, valid_extras ) if requirement: yield requirement def get_install_requirement(self): # type: () -> Optional[InstallRequirement] # We don't return anything here, because we always # depend on the base candidate, and we'll get the # install requirement from that. return None class RequiresPythonCandidate(Candidate): is_installed = False source_link = None def __init__(self, py_version_info): # type: (Optional[Tuple[int, ...]]) -> None if py_version_info is not None: version_info = normalize_version_info(py_version_info) else: version_info = sys.version_info[:3] self._version = Version(".".join(str(c) for c in version_info)) # We don't need to implement __eq__() and __ne__() since there is always # only one RequiresPythonCandidate in a resolution, i.e. the host Python. # The built-in object.__eq__() and object.__ne__() do exactly what we want. def __str__(self): # type: () -> str return f"Python {self._version}" @property def project_name(self): # type: () -> NormalizedName # Avoid conflicting with the PyPI package "Python". return cast(NormalizedName, "<Python from Requires-Python>") @property def name(self): # type: () -> str return self.project_name @property def version(self): # type: () -> CandidateVersion return self._version def format_for_error(self): # type: () -> str return f"Python {self.version}" def iter_dependencies(self, with_requires): # type: (bool) -> Iterable[Optional[Requirement]] return () def get_install_requirement(self): # type: () -> Optional[InstallRequirement] return None


Ten Georgian Opposition Protesters Jailed For Disobeying Police
by RFE/RL's Georgian ServiceTBILISI -- A Georgian court has sentenced 10 opposition demonstrators to between four to 13 days in prison on charges of disobeying law enforcement officers during an anti-government protest earlier this week.
Twenty-five other protesters are awaiting verdicts later on November 21 from the Tbilisi City Court.
The activists were detained on November 18 as they were blocking the entrances of the parliament building while thousands of people protested to demand snap polls after lawmakers failed to enact promised electoral reforms.
Groups of activists on November 21 symbolically tried to lock the entrances to the court and government buildings with padlocks.
Opposition parties say Georgia's electoral system unfairly favors the ruling Georgian Dream party.
Changing it to a proportional one from 2020 was one of the demands of thousands of demonstrators who rallied for weeks in Tbilisi in June and July.
The Georgian Dream party, including its billionaire founder and leader Bidzina Ivanishvili, backed the reform, but the constitutional amendments still failed to pass in parliament on November 14.
The United States and the European Union have called on the Georgian government, political parties, and civil society to engage in a "calm and respectful dialogue."


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Figure 92: Johann van der Schijff. Artifactual Intelligence, 1993.
[ Return to: Part 1 - 4.The Future as Present ]
A range of hand weapons are embedded in a stone slab and presented on a very heavy, rusted, metal base. Similar to Advanced Guidance, it shows the affinities between ancient and modern weaponry. Discarded pieces of micro-electronic circuit boards are imbedded in the handles of a club, a knife, and a stabbing spear. A grenade, climbing rope, battle axe, and spear make up the rest of this toolkit for survival / domination. Although they lie passively in their stone slots, the weapons invite the viewer to pick them up and actively make use of them. The piece reflects on the brooding violence underlying South African society. [Figure 92]
Figure 93: René Magritte. The Reckless Sleeper, 1927.
(Whitfield 1992: 35)
The weapons comment on cultural categorisation, seen in the retention of signifiers which are wrenched from their contexts. This is shown through the random proliferation of both hand-made and high-tech components to comment on archaic notions of the fight for domination. The weapons themselves are presented without any significant use-value, almost as if they are museum-pieces. The work draws formally from paintings made by René Magritte such as The Reckless Sleeper (1927) where arbitrary objects are depicted, embedded in an amorphic shape. [Figure 93] These surrealist / dream images act as metaphors of the human unconsciousness. As analogy, Artifactual Intelligence speaks of the imprint of violence on the South African psyche.
Figure 94: Johann van der Schijff. Artifactual Intelligence, 1993.
Mild-steel; Cor-Ten steel; stainless steel;
sandstone; found handmade weapons; rope; computer components.
H: 910 mm W: 630 mm L: 1200 mm
Figure 95: Johann van der Schijff. Drawing no. 1,
Artifactual Intelligence, 1993.
Figure 96: Johann van der Schijff. Drawing no. 2,
Artifactual Intelligence, 1993.
Figure 97: Johann van der Schijff. Drawing no. 3,
Artifactual Intelligence, 1993.
Figure 98: Johann van der Schijff. Drawing no. 4,
Artifactual Intelligence, 1993.


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WITNESS LIST Veteran Affairs & Military Installations Committee February 22, 1999-11:00A SB 171 For: DIKE, JERRY (TX. DEPT. OF TRANSPORTATION, AUSTIN, TX), AUSTIN, TX SB 313 For: BERRY, JIM (BEE DEVELOPMENT AUTHORITY), BEEVILLE, TX CAMPBELL, JIM (CITY OF SAN ANTONIO), SAN ANTONIO, TX PINKLEY, CRAIG (TX. DEPT. OF ECONOMIC DEVELOPMENT), NEW BRAUNFELS WEST, MICHAEL (TX. DEPT. OF ECONOMIC DEVELOPMENT), AUSTIN, TX Registering, but not testifying: For: CAIN, RANDY (THE CITY OF LUBBOCK), AUSITN, TX SB 416 For: PALMQUIST, MICHAEL (AMERICAN LEGION/TX. COALITION OF VET. ORG.), AUSTIN, TX


Ira Water is Pune’s leading Rainwater Harvesting provider. Since 2012 Ira is on a mission to make water available by replenishing groundwater through rainwater harvesting. Today with over 130 projects completed Ira has been a catalyst in increasing groundwater table in Western Maharashtra cities Pune, Mumbai, Nasik and Goa.
Ira has transformed << sq ft>> of landscape by recharging the acquirers and conserving 7000 million litres of water.
This year we’ve launched new product, Ira’s Water Saving Aerators that fit into existing taps. The aerators reduce the flow, regulate the pressure without affecting the water usage experience and save up to 80% of water. It is a German product, it's quality and precision make it a class-apart product.
We started Ira with a single mission, to make water available. And our priority is to address it locally first in Pune.
We have four objectives for the period 2017-2020 that guide our work
To improve groundwater table by recharging 50,000 borewells in India
To save 3 TMC water which is equivalent to size of a dam.
To develop a sustainable model for rural water management.
To raise awareness by educating children and working with policy makers, city planners and developers.
Water availability is an ongoing issue, which is becoming more complex due to rising demand and depleting supply. In order to focus on making water available Ira has identified three key areas that must be addressed for sustenance
Awareness, education. Basic necessity is often overlooked and taken for granted. Attitude towards water should be changed, it is a community resource, which is meant to be judiciously used, shared and conserved.
Builders, developers, industries, new construction need to comply with the regulation so groundwater is saved from pollution and depletion.
Understand water sources and question the sustainability. We work towardsinfluencing policy makers, city planners and developers to bring about avenues for more community involvement .
Swapnil and Udyam both wanted to work on a business idea that will have a positive social impact. They had an inclination towards friend of water, water being a key element. Water as a resource is poorly mismanaged and there were not many professional water management companies. They saw the future in Rainwater Harvesting, which could be implemented on individual level in a decentralized and has massive potential.
After graduating as a Mechanical Engineer from MIT, Pune, Swapnil has gained all-round professional experience in the last 3 years.He has worked in the sectors of manufacturing, EPC project management and R&D under banners like Tata, Essar and Mahindra. He brings in his comprehensive expertise and incessant enthusiasm to Ira.
Udyam is a Production Engineering graduate from K.K. Wagh College of Engineering, Nashik. With an aptitude for innovation, entrepreneurship was always on the cards for him. He is amongst the owners of Shamala Electroplaters, his family business that specialises in Hard Chromium Plating. He lends solidarity to Ira with his studious and observant self.
We are containing the groundwater depletion before it is too late.
we provide a transformational experience and build long-term value through our solution.
we embrace and promote water use efficiency and augment RWH with water saving and other innovative technologies for better.
Expert In-House Technical Team.
we have seen people come and go in last 5 years.
Download our company profile.


| 11 = Select P1.3 as the input of ACMP0. | ||
| [30] | T0 | Timer0 Trigger PWM Function Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| When this bit is set, timer0 time-out event will update PHCHG with PHCHG_NXT register. | ||
| [31] | CE0 | ACMP0 Trigger Function Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set. |
Definition at line 3573 of file Mini51Series.h.
| PWM_T::PIER |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PWMPIE0 | PWM Channel 0 Period Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | PWMPIE1 | PWM Channel 1 Period Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2] | PWMPIE2 | PWM Channel 2 Period Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [3] | PWMPIE3 | PWM Channel 3 Period Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [4] | PWMPIE4 | PWM Channel 4 Period Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [5] | PWMPIE5 | PWM Channel 5 Period Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [8] | PWMDIE0 | PWM Channel 0 Duty Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [9] | PWMDIE1 | PWM Channel 1 Duty Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [10] | PWMDIE2 | PWM Channel 2 Duty Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [11] | PWMDIE3 | PWM Channel 3 Duty Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [12] | PWMDIE4 | PWM Channel 4 Duty Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [13] | PWMDIE5 | PWM Channel 5 Duty Interrupt Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [16] | BRKIE | Fault Brake0 And 1 Interrupt Enable Control |
| 0 = Disabling flags BKF0 and BKF1 to trigger PWM interrupt. | ||
| 1 = Enabling flags BKF0 and BKF1 can trigger PWM interrupt. | ||
| [17] | INT_TYPE | PWM Interrupt Type Selection Bit |
| 0 = PWMPIFn will be set if PWM counter underflows. | ||
| 1 = PWMPIFn will be set if PWM counter matches CNRn register. | ||
| Note: This bit is effective when PWM in central align mode only. |
Definition at line 3563 of file Mini51Series.h.
| PWM_T::PIIR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PWMPIF0 | PWM Channel 0 Period Interrupt Flag |
| Flag is set by hardware when PWM0 down counter reaches zero. | ||
| Note: Software can write 1 to clear this bit. | ||
| [1] | PWMPIF1 | PWM Channel 1 Period Interrupt Flag |
| Flag is set by hardware when PWM1 down counter reaches zero. | ||
| Note: Software can write 1 to clear this bit. | ||
| [2] | PWMPIF2 | PWM Channel 2 Period Interrupt Flag |
| Flag is set by hardware when PWM2 down counter reaches zero. | ||
| Note: Software can write 1 to clear this bit. | ||
| [3] | PWMPIF3 | PWM Channel 3 Period Interrupt Flag |
| Flag is set by hardware when PWM3 down counter reaches zero. | ||
| Note: Software can write 1 to clear this bit. | ||
| [4] | PWMPIF4 | PWM Channel 4 Period Interrupt Flag |
| Flag is set by hardware when PWM4 down counter reaches zero. | ||
| Note: Software can write 1 to clear this bit. | ||
| [5] | PWMPIF5 | PWM Channel 5 Period Interrupt Flag |
| Flag is set by hardware when PWM5 down counter reaches zero. | ||
| Note: Software can write 1 to clear this bit. | ||
| [8] | PWMDIF0 | PWM Channel 0 Duty Interrupt Flag |
| Flag is set by hardware when a channel 0 PWM counter reaches CMR0 in down-count direction. | ||
| Note: Software can write 1 to clear this bit. | ||
| [9] | PWMDIF1 | PWM Channel 1 Duty Interrupt Flag |
| Flag is set by hardware when a channel 1 PWM counter reaches CMR1 in down-count direction. | ||
| Note: Software can write 1 to clear this bit. | ||
| [10] | PWMDIF2 | PWM Channel 2 Duty Interrupt Flag |
| Flag is set by hardware when a channel 2 PWM counter reaches CMR2 in down-count direction. | ||
| Note: Software can write 1 to clear this bit. | ||
| [11] | PWMDIF3 | PWM Channel 3 Duty Interrupt Flag |
| Flag is set by hardware when a channel 3 PWM counter reaches CMR3 in down-count direction. | ||
| Note: Software can write 1 to clear this bit. | ||
| [12] | PWMDIF4 | PWM Channel 4 Duty Interrupt Flag |
| Flag is set by hardware when a channel 4 PWM counter reaches CMR4 in down-count direction. | ||
| Note: Software can write 1 to clear this bit. | ||
| [13] | PWMDIF5 | PWM Channel 5 Duty Interrupt Flag |
| Flag is set by hardware when a channel 5 PWM counter reaches CMR5 in down-count direction. | ||
| Note: Software can write 1 to clear this bit. | ||
| [16] | BKF0 | PWM Brake0 Flag |
| 0 = PWM Brake does not recognize a falling signal at BKP0. | ||
| 1 = When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high. | ||
| Note: Software can write 1 to clear this bit. | ||
| [17] | BKF1 | PWM Brake1 Flag |
| 0 = PWM Brake does not recognize a falling signal at BKP1. | ||
| 1 = When PWM Brake detects a falling signal at pin BKP1, this flag will be set to high. | ||
| Note: Software can write 1 to clear this bit. |
Definition at line 3564 of file Mini51Series.h.
| GPIO_T::PIN |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | PIN | Port 0-5 Pin [N] Pin Value |
| Each bit of the register reflects the actual status of the respective Px.n pin. | ||
| If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. | ||
| Note1: x = 0~5, n = 0~7. | ||
| Note2: | ||
| P0_PIN[3:2] are reserved. | ||
| P1_PIN[7:6], [1] are reserved. | ||
| P2_PIN[7], [1:0] are reserved. | ||
| P3_PIN[7], [3] are reserved. | ||
| P4_PIN[5:0] are reserved. | ||
| P5_PIN[7:6] are reserved. |
Definition at line 2078 of file Mini51Series.h.
| GPIO_T::PMD |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | PMD0 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: x = 0~4, n = 0~7. | ||
| Note2: | ||
| P0_PMD[7:4] are reserved. | ||
| P1_PMD[15:12], [3:2] are reserved. | ||
| P2_PMD[15:14], [3:0] are reserved. | ||
| P3_PMD[15:14], [7:6] are reserved. | ||
| P4_PMD[11:0] are reserved. | ||
| P5_PMD[15:12] are reserved. | ||
| [3:2] | PMD1 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: x = 0~4, n = 0~7. | ||
| Note2: | ||
| P0_PMD[7:4] are reserved. | ||
| P1_PMD[15:12], [3:2] are reserved. | ||
| P2_PMD[15:14], [3:0] are reserved. | ||
| P3_PMD[15:14], [7:6] are reserved. | ||
| P4_PMD[11:0] are reserved. | ||
| P5_PMD[15:12] are reserved. | ||
| [5:4] | PMD2 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: x = 0~4, n = 0~7. | ||
| Note2: | ||
| P0_PMD[7:4] are reserved. | ||
| P1_PMD[15:12], [3:2] are reserved. | ||
| P2_PMD[15:14], [3:0] are reserved. | ||
| P3_PMD[15:14], [7:6] are reserved. | ||
| P4_PMD[11:0] are reserved. | ||
| P5_PMD[15:12] are reserved. | ||
| [7:6] | PMD3 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: x = 0~4, n = 0~7. | ||
| Note2: | ||
| P0_PMD[7:4] are reserved. | ||
| P1_PMD[15:12], [3:2] are reserved. | ||
| P2_PMD[15:14], [3:0] are reserved. | ||
| P3_PMD[15:14], [7:6] are reserved. | ||
| P4_PMD[11:0] are reserved. | ||
| P5_PMD[15:12] are reserved. | ||
| [9:8] | PMD4 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: x = 0~4, n = 0~7. | ||
| Note2: | ||
| P0_PMD[7:4] are reserved. | ||
| P1_PMD[15:12], [3:2] are reserved. | ||
| P2_PMD[15:14], [3:0] are reserved. | ||
| P3_PMD[15:14], [7:6] are reserved. | ||
| P4_PMD[11:0] are reserved. | ||
| P5_PMD[15:12] are reserved. | ||
| [11:10] | PMD5 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: x = 0~4, n = 0~7. | ||
| Note2: | ||
| P0_PMD[7:4] are reserved. | ||
| P1_PMD[15:12], [3:2] are reserved. | ||
| P2_PMD[15:14], [3:0] are reserved. | ||
| P3_PMD[15:14], [7:6] are reserved. | ||
| P4_PMD[11:0] are reserved. | ||
| P5_PMD[15:12] are reserved. | ||
| [13:12] | PMD6 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: x = 0~4, n = 0~7. | ||
| Note2: | ||
| P0_PMD[7:4] are reserved. | ||
| P1_PMD[15:12], [3:2] are reserved. | ||
| P2_PMD[15:14], [3:0] are reserved. | ||
| P3_PMD[15:14], [7:6] are reserved. | ||
| P4_PMD[11:0] are reserved. | ||
| P5_PMD[15:12] are reserved. | ||
| [15:14] | PMD7 | Port 0-5 I/O Pin [N] Mode Control |
| Determine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]). | ||
| 00 = Px.n is in Input mode. | ||
| 01 = Px.n is in Push-pull Output mode. | ||
| 10 = Px.n is in Open-drain Output mode. | ||
| 11 = Px.n is in Quasi-bidirectional mode. | ||
| Note1: x = 0~4, n = 0~7. | ||
| Note2: | ||
| P0_PMD[7:4] are reserved. | ||
| P1_PMD[15:12], [3:2] are reserved. | ||
| P2_PMD[15:14], [3:0] are reserved. | ||
| P3_PMD[15:14], [7:6] are reserved. | ||
| P4_PMD[11:0] are reserved. | ||
| P5_PMD[15:12] are reserved. |
Definition at line 2074 of file Mini51Series.h.
| PWM_T::POE |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PWM0 | PWM Channel 0 Output Enable Control |
| 0 = PWM channel 0 output to pin Disabled. | ||
| 1 = PWM channel 0 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [1] | PWM1 | PWM Channel 1 Output Enable Control |
| 0 = PWM channel 1 output to pin Disabled. | ||
| 1 = PWM channel 1 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [2] | PWM2 | PWM Channel 2 Output Enable Control |
| 0 = PWM channel 2 output to pin Disabled. | ||
| 1 = PWM channel 2 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [3] | PWM3 | PWM Channel 3 Output Enable Control |
| 0 = PWM channel 3 output to pin Disabled. | ||
| 1 = PWM channel 3 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [4] | PWM4 | PWM Channel 4 Output Enable Control |
| 0 = PWM channel 4 output to pin Disabled. | ||
| 1 = PWM channel 4 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. | ||
| [5] | PWM5 | PWM Channel 5 Output Enable Control |
| 0 = PWM channel 5 output to pin Disabled. | ||
| 1 = PWM channel 5 output to pin Enabled. | ||
| Note: The corresponding GPIO pin must be switched to PWM function. |
Definition at line 3565 of file Mini51Series.h.
| PWM_T::PPR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CP01 | Clock Prescaler 0 For PWM Counter 0 And 1 |
| Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter. | ||
| If CP01 = 0, the clock prescaler 0 output clock will be stopped. | ||
| So the corresponding PWM counter will also be stopped. | ||
| [15:8] | CP23 | Clock Prescaler 2 For PWM Counter 2 And 3 |
| Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter. | ||
| If CP23 = 0, the clock prescaler 2 output clock will be stopped. | ||
| So the corresponding PWM counter will also be stopped. | ||
| [23:16] | CP45 | Clock Prescaler 4 For PWM Counter 4 And 5 |
| Clock input is divided by (CP45 + 1) before it is fed to the corresponding PWM counter. | ||
| If CP45 = 0, the clock prescaler 4 output clock will be stopped. | ||
| So the corresponding PWM counter will also be stopped. |
Definition at line 3555 of file Mini51Series.h.
| CLK_T::PWRCON |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | XTLCLK_EN | External Crystal HXT Or LXT Enable Control (Write Protect) |
| The default clock source is from HIRC. | ||
| These two bits are default set to "00" and the XTAL1 and XTAL2 pins are GPIO. | ||
| 00 = XTAL1 and XTAL2 are GPIO, disable both LXT & HXT (default). | ||
| 01 = HXT Enabled. | ||
| 10 = LXT Enabled. | ||
| 11 = XTAL1 is external clock input pin, XTAL2 is GPIO. | ||
| Note: To enable the external XTAL function, the P5_ALT[1:0] and P5_MFP[1:0] bits must also be set in P5_MFP. | ||
| [2] | OSC22M_EN | 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect) |
| 0 = 22.1184 MHz internal high speed RC oscillator (HIRC) Disabled. | ||
| 1 = 22.1184 MHz internal high speed RC oscillator (HIRC) Enabled. | ||
| Note: The default of OSC22M_EN bit is 1. | ||
| [3] | OSC10K_EN | 10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protect) |
| 0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. | ||
| 1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. | ||
| [4] | PD_WU_DLY | Wake-up Delay Counter Enable Control (Write Protect) |
| When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. | ||
| The delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal (HXT), 4096 clock cycles for 32.768 kHz external low speed crystal (LXT), and 16 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC). | ||
| 0 = Clock cycles delay Disabled. | ||
| 1 = Clock cycles delay Enabled. | ||
| [5] | PD_WU_INT_EN | Power-down Mode Wake-up Interrupt Enable Control (Write Protect) |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high. | ||
| [6] | PD_WU_STS | Power-down Mode Wake-up Interrupt Status |
| Set by "Power-down wake-up event", which indicates that resume from Power-down mode. | ||
| The flag is set if the GPIO, UART, WDT, I2C, ACMP, Timer or BOD wake-up occurred. | ||
| Note: This bit works only if PD_WU_INT_EN (PWRCON[5]) set to 1. Write 1 to clear the bit to 0. | ||
| [7] | PWR_DOWN_EN | System Power-down Enable Bit (Write Protect) |
| When chip wakes up from Power-down mode, this bit is cleared by hardware. | ||
| User needs to set this bit again for next Power-down. | ||
| In Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT), 32.768 kHz external low speed crystal oscillator (LXT), and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode. | ||
| In Power-down mode, the system clock is disabled, and ignored the clock source selection. | ||
| The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator. | ||
| 0 = Chip operating normally or chip in Idle mode because of WFI command. | ||
| 1 = Chip enters Power-down mode instantly or waits CPU sleep command WFI. | ||
| [9] | PD_32K | Enable LXT In Power-down Mode |
| This bit controls the crystal oscillator active or not in Power-down mode. | ||
| 0 = No effect to Power-down mode. | ||
| 1 = If XTLCLK_EN[1:0] = 10, LXT is still active in Power-down mode. |
Definition at line 844 of file Mini51Series.h.
| UART_T::RBR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | RBR | Receive Buffer Bits (Read Only) |
| By reading this register, the UART Controller will return an 8-bit data received from RX pin (LSB first). |
Definition at line 5321 of file Mini51Series.h.
| __I uint32_t { ... } ::RBR |
Definition at line 5321 of file Mini51Series.h.
| GCR_T::RegLockAddr |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RegUnLock | Register Write-protection Disable Index (Read Only) |
| 0 = Write-protection Enabled for writing protected registers. | ||
| Any write to the protected register is ignored. | ||
| 1 = Write-protection Disabled for writing protected registers. | ||
| The Protected registers are: | ||
| IPRSTC1 (0x5000_0008) | ||
| BODCTL (0x5000_0018) | ||
| PWRCON (0x5000_0200), bit[6] is not protected for power wake-up interrupt clear | ||
| APBCLK (0x5000_0208), bit[0] watchdog clock enable only | ||
| CLKSEL0 (0x5000_0210) | ||
| CLKSEL1 (0x5000_0214), bit[1:0] Watchdog clock source select only | ||
| NMI_SEL (0x5000_0380), bit[8] NMI interrupt enable only | ||
| ISPCON (0x5000_C000) | ||
| ISPTRG (0x5000_C010) | ||
| WTCR (0x4000_4000) | ||
| Note: The bits which are write-protected will be noted as" (Write Protect)" beside the description. | ||
| [7:0] | REGWRPROT | Register Write-protection Code (Write Only) |
| Some registers have write-protection function. | ||
| Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. | ||
| After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write. |
Definition at line 1530 of file Mini51Series.h.
| GCR_T::RSTSRC |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RSTS_POR | Power-on Reset Flag |
| The RSTS_POR flag is set by the "reset signal", which is from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]), to indicate the previous reset source. | ||
| 0 = No reset from POR or CHIP_RST. | ||
| 1 = Power-on-Reset (POR) or CHIP_RST had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to 0. | ||
| [1] | RSTS_RESET | Reset Pin Reset Flag |
| The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source. | ||
| 0 = No reset from pin /RESET pin. | ||
| 1 = The /RESET pin had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to 0. | ||
| [2] | RSTS_WDT | Watchdog Reset Flag |
| The RSTS_WDT flag is set by the "reset signal" from the Watchdog timer to indicate the previous reset source. | ||
| 0 = No reset from Watchdog timer. | ||
| 1 = The Watchdog timer had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to 0. | ||
| [4] | RSTS_BOD | Brown-out Detector Reset Flag |
| The RSTS_BOD flag is set by the "reset signal" from the Brown-out Detector to indicate the previous reset source. | ||
| 0 = No reset from BOD. | ||
| 1 = The BOD had issued the reset signal to reset the system. | ||
| Note: Software can write 1 to clear this bit to 0. | ||
| [5] | RSTS_MCU | MCU Reset Flag |
| The RSTS_MCU flag is set by the "reset signal" from the Cortex-M0 core to indicate the previous reset source. | ||
| 0 = No reset from Cortex-M0. | ||
| 1 = The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2]), Application Interrupt and Reset Control Register, address = 0xE000ED0C in system control registers of Cortex-M0 core. | ||
| Note: Software can write 1 to clear this bit to 0. | ||
| [7] | RSTS_CPU | CPU Reset Flag |
| The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC). | ||
| 0 = No reset from CPU. | ||
| 1 = Cortex-M0 core and FMC are reset by software setting CPU_RST to 1. | ||
| Note: Software can write 1 to clear this bit to 0. |
Definition at line 1505 of file Mini51Series.h.
| SPI_T::RX |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | RX | Data Receive Bits (Read Only) |
| The Data Receive Registers hold the value of received data of the last executed transfer. | ||
| Valid bits depend on the transmit bit length field in the SPI_CNTRL register. | ||
| For example, if TX_BIT_LEN is set to 0x08, bit RX [7:0] holds the received data. | ||
| The values of the other bits are unknown. |
Definition at line 4479 of file Mini51Series.h.
| INT_T::SRC0 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2680 of file Mini51Series.h.
| INT_T::SRC1 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2681 of file Mini51Series.h.
| INT_T::SRC12 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2693 of file Mini51Series.h.
| INT_T::SRC14 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2697 of file Mini51Series.h.
| INT_T::SRC16 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2701 of file Mini51Series.h.
| INT_T::SRC17 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2702 of file Mini51Series.h.
| INT_T::SRC18 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2703 of file Mini51Series.h.
| INT_T::SRC2 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2682 of file Mini51Series.h.
| INT_T::SRC25 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2707 of file Mini51Series.h.
| INT_T::SRC28 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2711 of file Mini51Series.h.
| INT_T::SRC29 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2712 of file Mini51Series.h.
| INT_T::SRC3 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2683 of file Mini51Series.h.
| INT_T::SRC4 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2684 of file Mini51Series.h.
| INT_T::SRC5 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2685 of file Mini51Series.h.
| INT_T::SRC6 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2686 of file Mini51Series.h.
| INT_T::SRC7 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2687 of file Mini51Series.h.
| INT_T::SRC8 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2688 of file Mini51Series.h.
| INT_T::SRC9 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | INT_SRC | Interrupt Source |
| Define the interrupt sources for interrupt event. |
Definition at line 2689 of file Mini51Series.h.
| SPI_T::SSR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | SSR | Slave Select Control Bit (Master Only) |
| If AUTOSS bit is 0, | ||
| 0 = Set the SPISS line to inactive state. | ||
| 1 = Set the proper SPISS line to active state. | ||
| If AUTOSS bit is 1, | ||
| 0 = Keep the SPISS line at inactive state. | ||
| 1 = Select the SPISS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. | ||
| The active state of SPISS is specified in SS_LVL bit. | ||
| [2] | SS_LVL | Slave Select Active Level (Slave Only) |
| It defines the active status of slave select signal (SPISS). | ||
| If SS_LTRIG bit is 1: | ||
| 0 = The slave select signal SPISS is active at Low-level. | ||
| 1 = The slave select signal SPISS is active at High-level. | ||
| If SS_LTRIG bit is 0: | ||
| 0 = The slave select signal SPISS is active at Falling-edge. | ||
| 1 = The slave select signal SPISS is active at Rising-edge. | ||
| [3] | AUTOSS | Automatic Slave Selection Function Enable Bit (Master Only) |
| 0 = SPISS pin signal will be asserted/de-asserted by setting /clearing SSR bit. | ||
| 1 = SPISS pin signal will be generated automatically, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished. | ||
| [4] | SS_LTRIG | Slave Select Level Trigger Enable Bit (Slave Only) |
| 0 = The input slave select signal is edge-trigger. | ||
| 1 = The input slave select signal is level-trigger. | ||
| [5] | LTRIG_FLAG | Level Trigger Flag (Read Only, Slave Only) |
| When the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not. | ||
| 0 = The transaction number or the transferred bit length of one transaction does not meet the specified requirements. | ||
| 1 = The transaction number and the transferred bit length met the specified requirements which defined in TX_BIT_LEN. |
Definition at line 4475 of file Mini51Series.h.
| SPI_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RX_INTSTS | Receive FIFO Threshold Interrupt Status (Read Only) |
| 0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD. | ||
| 1 = The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD. | ||
| Note: If RX_INTEN = 1 and RX_INTSTS = 1, the SPI controller will generate a SPI interrupt request. | ||
| [2] | RX_OVERRUN | Receive FIFO Overrun Status |
| When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. | ||
| 0 = No overrun in receive FIFO. | ||
| 1 = Overrun in receive FIFO. | ||
| Note: This bit will be cleared by writing 1 to itself. | ||
| [4] | TX_INTSTS | Transmit FIFO Threshold Interrupt Status (Read Only) |
| 0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD. | ||
| 1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD. | ||
| Note: If TX_INTEN = 1 and TX_INTSTS = 1, the SPI controller will generate a SPI interrupt request. | ||
| [11] | SLV_START_INTSTS | Slave Start Interrupt Status (Slave Only) |
| It is used to dedicate that the transfer has started in slave 3-wire mode. | ||
| 0 = Slave does not detect any SPI bus clock transfer since the SSTA_INTEN bit was set to 1. | ||
| 1 = The transfer has started in slave 3-wire mode. | ||
| Note 1: It will be cleared as transfer done or by writing one to this bit. | ||
| Note 2: It's a mutual mirror bit of SPI_CNTRL2[11]. | ||
| [15:12] | RX_FIFO_COUNT | Receive FIFO Data Count (Read Only) |
| Indicates the valid data count of receive FIFO buffer. | ||
| [16] | IF | SPI Unit-transfer Interrupt Flag |
| 0 = The transfer does not finish yet. | ||
| 1 = The SPI controller has finished one unit transfer. | ||
| Note 1: This bit will be cleared by writing 1 to itself. | ||
| Note 2: It's a mutual mirror bit of SPI_CNTRL[16]. | ||
| [20] | TIMEOUT | Time-out Interrupt Flag |
| 0 = No receive FIFO time-out event. | ||
| 1 = The receive FIFO buffer is not empty and it does not be read over 64 SPI clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. | ||
| When the received FIFO buffer is read by software, the time-out status will be cleared automatically. | ||
| Note: This bit will be cleared by writing 1 to itself. | ||
| [24] | RX_EMPTY | Receive FIFO Buffer Empty Indicator (Read Only) |
| 0 = The receive FIFO buffer is not empty. | ||
| 1 = The receive FIFO buffer is empty. | ||
| Note: It's a mutual mirror bit of SPI_CNTRL[24]. | ||
| [25] | RX_FULL | Receive FIFO Buffer Full Indicator (Read Only) |
| 0 = The receive FIFO buffer is not full. | ||
| 1 = The receive FIFO buffer is full. | ||
| Note: It's a mutual mirror bit of SPI_CNTRL[25]. | ||
| [26] | TX_EMPTY | Transmit FIFO Buffer Empty Indicator (Read Only) |
| 0 = The transmit FIFO buffer is not empty. | ||
| 1 = The transmit FIFO buffer is empty. | ||
| Note: It's a mutual mirror bit of SPI_CNTRL[26]. | ||
| [27] | TX_FULL | Transmit FIFO Buffer Full Indicator (Read Only) |
| 0 = The transmit FIFO buffer is not full. | ||
| 1 = The transmit FIFO buffer is full. | ||
| Note: It's a mutual mirror bit of SPI_CNTRL[27]. | ||
| [31:28] | TX_FIFO_COUNT | Transmit FIFO Data Count (Read Only) |
| Indicates the valid data count of transmit FIFO buffer. |
Definition at line 4489 of file Mini51Series.h.
| TIMER_T::TCAP |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | TCAP | Timer Capture Data Register |
| When TEXIF flag is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately. |
Definition at line 4823 of file Mini51Series.h.
| TIMER_T::TCMPR |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | TCMP | Timer Compared Value |
| TCMP is a 24-bit compared value register. | ||
| When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1. | ||
| Time-out period = (Period of Timer clock source) * (8-bit PRESCALE + 1) * (24-bit TCMP). | ||
| Note1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state. |
Definition at line 4820 of file Mini51Series.h.
| TIMER_T::TCSR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | PRESCALE | Prescale Counter |
| Timer input clock source is divided by (PRESCALE+1) before it is fed to the Timer up counter. | ||
| If this field is 0 (PRESCALE = 0), then there is no scaling. | ||
| [16] | TDR_EN | Data Load Enable Control |
| When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting. | ||
| 0 = Timer Data Register update Disabled. | ||
| 1 = Timer Data Register update Enabled while Timer counter is active. | ||
| [17] | PERIODIC_SEL | Periodic Mode Behavior Selection |
| 0 = In One-shot or Periodic mode, when write new TCMP, timer counter will reset. | ||
| 1 = In One-shot or Periodic mode, when write new TCMP if new TCMP > TDR(current counter) , timer counter keep counting and will not reset. | ||
| If new TCMP <= TDR(current counter) , timer counter will reset. | ||
| [18] | TOUT_PIN | Toggle Out Pin Selection |
| When Timer is set to toggle mode, | ||
| 0 = Time0/1 toggle output pin is T0/T1 pin. | ||
| 1 = Time0/1 toggle output pin is T0EX/T1EX pin. | ||
| [19] | CAP_SRC | Capture Pin Source Selection |
| 0 = Capture Function source is from TxEX pin. | ||
| 1 = Capture Function source is from ACMPx output signal. | ||
| [23] | WAKE_EN | Wake-up Enable Control |
| When WAKE_EN (UA_IER[6]) is set and the TIF or TEXIF (TEXISR[0]) is set, the timer controller will generator a wake-up trigger event to CPU. | ||
| 0 = Wake-up trigger event Disabled. | ||
| 1 = Wake-up trigger event Enabled. | ||
| [24] | CTB | Counter Mode Enable Control |
| This bit is for external counting pin function enabled. | ||
| When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. | ||
| Please refer to section <IP_ADDRESS> for detail description. | ||
| 0 = External event counter mode Disabled. | ||
| 1 = External event counter mode Enabled. | ||
| [25] | CACT | Timer Active Status (Read Only) |
| This bit indicates the 24-bit up counter status. | ||
| 0 = 24-bit up counter is not active. | ||
| 1 = 24-bit up counter is active. | ||
| [26] | CRST | Timer Reset |
| 0 = No effect. | ||
| 1 = Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1. | ||
| [28:27] | MODE | Timer Operating Mode |
| 00 = The timer is operating in the One-shot mode. | ||
| The associated interrupt signal is generated once (if IE is enabled) and CEN is automatically cleared by hardware. | ||
| 01 = The timer is operating in Periodic mode. | ||
| The associated interrupt signal is generated periodically (if IE is enabled). | ||
| 10 = The timer is operating in Toggle mode. | ||
| The interrupt signal is generated periodically (if IE is enabled). | ||
| The associated signal (tout) is changing back and forth with 50% duty cycle. | ||
| 11 = The timer is operating in Continuous Counting mode. | ||
| The associated interrupt signal is generated when TDR = TCMPR (if IE is enabled). | ||
| However, the 24-bit up-timer counts continuously. | ||
| Please refer to <IP_ADDRESS> for detailed description about Continuous Counting mode operation. | ||
| [29] | IE | Interrupt Enable Control |
| 0 = Timer Interrupt function Disabled. | ||
| 1 = Timer Interrupt function Enabled. | ||
| If this bit is enabled, when the timer interrupt flag (TIF) is set to 1, the timer interrupt signal is generated and inform to CPU. | ||
| [30] | CEN | Timer Enable Control |
| 0 = Stops/Suspends counting. | ||
| 1 = Starts counting. | ||
| Note1: In stop status, and then set CEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. | ||
| Note2: This bit is auto-cleared by hardware in one-shot mode (MODE (TCSRx[28:27]) = 00) when the timer interrupt flag (TIF) is generated. | ||
| [31] | DBGACK_TMR | ICE Debug Mode Acknowledge Disable Control (Write Protect) |
| 0 = ICE debug mode acknowledgement effects TIMER counting. | ||
| Timer counter will be held while CPU is held by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| Timer counter will keep going no matter CPU is held by ICE or not. |
Definition at line 4819 of file Mini51Series.h.
| TIMER_T::TDR |
| Bits | Field | Descriptions |
|---|---|---|
| [23:0] | TDR | Timer Data Register |
| If TDR_EN (TCSRx[16]) is set to 1, TDR register value will be updated continuously to monitor 24-bit up counter value. |
Definition at line 4822 of file Mini51Series.h.
| TIMER_T::TEXCON |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TX_PHASE | Timer External Count Pin Phase Detect Selection |
| This bit indicates the detection phase of Tx (x = 0~1) pin. | ||
| 0 = A falling edge of Tx (x = 0~1) pin will be counted. | ||
| 1 = A rising edge of Tx (x = 0~1) pin will be counted. | ||
| [2:1] | TEX_EDGE | Timer External Pin Edge Detection |
| 00 = A 1 to 0 transition on TxEX (x = 0~1) will be detected. | ||
| 01 = A 0 to 1 transition on TxEX (x = 0~1) will be detected. | ||
| 10 = Either 1 to 0 or 0 to 1 transition on TxEX (x = 0~1) will be detected. | ||
| 11 = Reserved. | ||
| [3] | TEXEN | Timer External Pin Function Enable Control |
| This bit enables the RSTCAPSEL function on the TxEX (x = 0~1) pin. | ||
| 0 = RSTCAPSEL function of TxEX (x = 0~1) pin will be ignored. | ||
| 1 = RSTCAPSEL function of TxEX (x = 0~1) pin is active. | ||
| [4] | RSTCAPSEL | Timer External Reset Counter / Timer External Capture Mode Selection |
| 0 = Transition on TxEX (x = 0~1) pin is using to save the TDR value into TCAP value if TEXIF flag is set to 1. | ||
| 1 = Transition on TxEX (x = 0~1) pin is using to reset the 24-bit up counter. | ||
| [5] | TEXIEN | Timer External Capture Interrupt Enable Control |
| 0 = TxEX (x = 0~1) pin detection Interrupt Disabled. | ||
| 1 = TxEX (x = 0~1) pin detection Interrupt Enabled. | ||
| If TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1. | ||
| [6] | TEXDB | Timer External Capture Input Pin De-bounce Enable Control |
| 0 = TxEX (x = 0~1) pin de-bounce Disabled. | ||
| 1 = TxEX (x = 0~1) pin de-bounce Enabled. | ||
| If this bit is enabled, the edge detection of TxEX (x = 0~1) pin is detected with de-bounce circuit. | ||
| [7] | TCDB | Timer External Counter Input Pin De-bounce Enable Control |
| 0 = Tx (x = 0~1) pin de-bounce Disabled. | ||
| 1 = Tx (x = 0~1) pin de-bounce Enabled. | ||
| If this bit is enabled, the edge detection of Tx (x = 0~1) pin is detected with de-bounce circuit. | ||
| [8] | CAP_MODE | Capture Mode Selection |
| 0 = Timer counter reset function or free-counting mode of timer capture function. | ||
| 1 = Trigger-counting mode of timer capture function. |
Definition at line 4824 of file Mini51Series.h.
| TIMER_T::TEXISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TEXIF | Timer External Interrupt Flag |
| This bit indicates the external capture interrupt flag status | ||
| When TEXEN enabled, TxEX (x = 0, 1) pin selected as external capture function, and a transition on TxEX (x = 0, 1) pin matched the TEX_EDGE setting, this flag will set to 1 by hardware. | ||
| 0 = TxEX (x = 0, 1) pin interrupt did not occur. | ||
| 1 = TxEX (x = 0, 1) pin interrupt occurred. | ||
| Note: This bit is cleared by writing 1 to it |
Definition at line 4825 of file Mini51Series.h.
| UART_T::THR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | THR | Transmit Holding Bits |
| By writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first). |
Definition at line 5322 of file Mini51Series.h.
| __O uint32_t { ... } ::THR |
Definition at line 5322 of file Mini51Series.h.
| TIMER_T::TISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TIF | Timer Interrupt Flag |
| This bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value. | ||
| 0 = No effect. | ||
| 1 = TDR value matches the TCMP value. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [1] | TWF | Timer Wake-up Flag |
| This bit indicates the interrupt wake-up flag status of Time. | ||
| 0 = Timer does not cause chip wake-up. | ||
| 1 = Chip wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated. | ||
| Note: This bit is cleared by writing 1 to it. |
Definition at line 4821 of file Mini51Series.h.
| UART_T::TOR |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | TOIC | Time-out Interrupt Comparator |
| The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. | ||
| Once the content of time-out counter (TOUT_CNT) is equal to that of time-out interrupt comparator (TOIC), a receiver time-out interrupt (TOUT_INT) is generated if RTO_IEN (UA_IER [4]). | ||
| A new incoming data word or RX FIFO empty clears TOUT_INT. | ||
| In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255. | ||
| So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. | ||
| [15:8] | DLY | TX Delay Time Value |
| This field is used to program the transfer delay time between the last stop bit and next start bit. |
Definition at line 5331 of file Mini51Series.h.
| PWM_T::TRGCON0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CM0TRGREN | Enable PWM Trigger ADC Function While Channel0's Counter Matching CMR0 In Up-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [1] | CNT0TRGEN | Enable PWM Trigger ADC Function While Channel0's Counter Matching CNR0 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [2] | CM0TRGFEN | Enable PWM Trigger ADC Function While Channel0's Counter Matching CMR0 In Down-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. | ||
| [3] | P0TRGEN | Enable PWM Trigger ADC Function While Channel0's Counter Matching 0 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. | ||
| [8] | CM1TRGREN | Enable PWM Trigger ADC Function While Channel1's Counter Matching CMR1 In Up-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [9] | CNT1TRGEN | Enable PWM Trigger ADC Function While Channel1's Counter Matching CNR1 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [10] | CM1TRGFEN | Enable PWM Trigger ADC Function While Channel1's Counter Matching CMR1 In Down-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. | ||
| [11] | P1TRGEN | Enable PWM Trigger ADC Function While Channel1's Counter Matching 0 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. | ||
| [16] | CM2TRGREN | Enable PWM Trigger ADC Function While Channel2's Counter Matching CMR2 In Up-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [17] | CNT2TRGEN | Enable PWM Trigger ADC Function While Channel2's Counter Matching CNR2 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [18] | CM2TRGFEN | Enable PWM Trigger ADC Function While Channel2's Counter Matching CMR2 In Down-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. | ||
| [19] | P2TRGEN | Enable PWM Trigger ADC Function While Channel2's Counter Matching 0 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. | ||
| [24] | CM3TRGREN | Enable PWM Trigger ADC Function While Channel3's Counter Matching CMR3 In Up-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [25] | CNT3TRGEN | Enable PWM Trigger ADC Function While Channel3's Counter Matching CNR3 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [26] | CM3TRGFEN | Enable PWM Trigger ADC Function While Channel3's Counter Matching CMR3 In Down-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. | ||
| [27] | P3TRGEN | Enable PWM Trigger ADC Function While Channel3's Counter Matching 0 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. |
Definition at line 3568 of file Mini51Series.h.
| PWM_T::TRGCON1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CM4TRGREN | Enable PWM Trigger ADC Function While Channel4's Counter Matching CMR4 In Up-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [1] | CNT4TRGEN | Enable PWM Trigger ADC Function While Channel4's Counter Matching CNR4 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [2] | CM4TRGFEN | Enable PWM Trigger ADC Function While Channel4's Counter Matching CMR4 In Down-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. | ||
| [3] | P4TRGEN | Enable PWM Trigger ADC Function While Channel4's Counter Matching 0 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. | ||
| [8] | CM5TRGREN | Enable PWM Trigger ADC Function While Channel5's Counter Matching CMR5 In Up-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [9] | CNT5TRGEN | Enable PWM Trigger ADC Function While Channel5's Counter Matching CNR5 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is only valid for PWM in center aligned mode. | ||
| When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect. | ||
| [10] | CM5TRGFEN | Enable PWM Trigger ADC Function While Channel5's Counter Matching CMR5 In Down-count Direction |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. | ||
| [11] | P5TRGEN | Enable PWM Trigger ADC Function While Channel5's Counter Matching 0 |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: This bit is valid for both center aligned mode and edged aligned mode. |
Definition at line 3569 of file Mini51Series.h.
| PWM_T::TRGSTS0 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CMR0FLAG_R | ADC Trigger Flag By Counting Up To CMR |
| Note: Software can write 1 to clear this bit. | ||
| [1] | CNT0FLAG | ADC Trigger Flag By Counting To CNR |
| Note: Software can write 1 to clear this bit. | ||
| [2] | CMR0FLAG_F | ADC Trigger Flag By Counting Down To CMR |
| Note: Software can write 1 to clear this bit. | ||
| [3] | PERID0FLAG | ADC Trigger Flag By Period |
| Note: Software can write 1 to clear this bit. | ||
| [8] | CMR1FLAG_R | ADC Trigger Flag By Counting Up To CMR |
| Note: Software can write 1 to clear this bit. | ||
| [9] | CNT1FLAG | ADC Trigger Flag By Counting To CNR |
| Note: Software can write 1 to clear this bit. | ||
| [10] | CMR1FLAG_F | ADC Trigger Flag By Counting Down To CMR |
| Note: Software can write 1 to clear this bit. | ||
| [11] | PERID1FLAG | ADC Trigger Flag By Period |
| Note: Software can write 1 to clear this bit. | ||
| [16] | CMR2FLAG_R | ADC Trigger Flag By Counting Up To CMR |
| Note: Software can write 1 to clear this bit. | ||
| [17] | CNT2FLAG | ADC Trigger Flag By Counting To CNR |
| Note: Software can write 1 to clear this bit. | ||
| [18] | CMR2FLAG_F | ADC Trigger Flag By Counting Down To CMR |
| Note: Software can write 1 to clear this bit. | ||
| [19] | PERID2FLAG | ADC Trigger Flag By Period |
| Note: Software can write 1 to clear this bit. | ||
| [24] | CMR3FLAG_R | When Counter Counting Up To CMR, This Bit Will Be Set For Trigger ADC |
| Note: Software can write 1 to clear this bit. | ||
| [25] | CNT3FLAG | When Counter Counting To CNR, This Bit Will Be Set For Trigger ADC |
| Note: Software can write 1 to clear this bit. | ||
| [26] | CMR3FLAG_F | When Counter Counting Down To CMR, This Bit Will Be Set For Trigger ADC |
| Note: Software can write 1 to clear this bit. | ||
| [27] | PERID3FLAG | When Counter Counting To Period, This Bit Will Be Set For Trigger ADC |
| Note: Software can write 1 to clear this bit. |
Definition at line 3570 of file Mini51Series.h.
| PWM_T::TRGSTS1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CMR4FLAG_R | ADC Trigger Flag By Counting Up To CMR |
| Note: Software can write 1 to clear this bit. | ||
| [1] | CNT4FLAG | ADC Trigger Flag By Counting To CNR |
| Note: Software can write 1 to clear this bit. | ||
| [2] | CMR4FLAG_F | ADC Trigger Flag By Counting Down To CMR |
| Note: Software can write 1 to clear this bit. | ||
| [3] | PERID4FLAG | ADC Trigger Flag By Period |
| Note: Software can write 1 to clear this bit. | ||
| [8] | CMR5FLAG_R | ADC Trigger Flag By Counting Up To CMR |
| Note: Software can write 1 to clear this bit. | ||
| [9] | CNT5FLAG | ADC Trigger Flag By Counting To CNR |
| Note: Software can write 1 to clear this bit. | ||
| [10] | CMR5FLAG_F | ADC Trigger Flag By Counting Down To CMR |
| Note: Software can write 1 to clear this bit. | ||
| [11] | PERID5FLAG | ADC Trigger Flag By Period |
| Note: Software can write 1 to clear this bit. |
Definition at line 3571 of file Mini51Series.h.
| SPI_T::TX |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | TX | Data Transmit Bits (Write Only) |
| The Data Transmit Registers hold the data to be transmitted in the next transfer. | ||
| Valid bits depend on the transmit bit length field in the CNTRL register. | ||
| For example, if TX_BIT_LEN is set to 0x08, the bit TX [7:0] will be transmitted in next transfer. |
Definition at line 4483 of file Mini51Series.h.
| WDT_T::WTCR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WTR | Reset Watchdog Timer Up Counter (Write Protect) |
| 0 = No effect. | ||
| 1 = Reset the internal 18-bit WDT up counter value. | ||
| Note: This bit will be automatically cleared by hardware. | ||
| [1] | WTRE | Watchdog Timer Time-out Reset Enable Control (Write Protect) |
| Setting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period (1024 * TWDT) expires. | ||
| 0 = WDT time-out reset function Disabled. | ||
| 1 = WDT time-out reset function Enabled. | ||
| [2] | WTRF | Watchdog Timer Time-out Reset Flag |
| This bit indicates the system has been reset by WDT time-out reset or not. | ||
| 0 = WDT time-out reset did not occur. | ||
| 1 = WDT time-out reset occurred. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [3] | WTIF | Watchdog Timer Time-out Interrupt Flag |
| This bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval. | ||
| 0 = WDT time-out interrupt did not occur. | ||
| 1 = WDT time-out interrupt occurred. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [4] | WTWKE | Watchdog Timer Time-out Wake-up Function Control (Write Protect) |
| If this bit is set to 1, while WTIF is generated to 1 and WTIE enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. | ||
| 0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. | ||
| 1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. | ||
| Note: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator. | ||
| [5] | WTWKF | Watchdog Timer Time-out Wake-up Flag |
| This bit indicates the interrupt wake-up flag status of WDT. | ||
| 0 = WDT does not cause chip wake-up. | ||
| 1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. | ||
| Note: This bit is cleared by writing 1 to it. | ||
| [6] | WTIE | Watchdog Timer Time-out Interrupt Enable Control (Write Protect) |
| If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. | ||
| 0 = WDT time-out interrupt Disabled. | ||
| 1 = WDT time-out interrupt Enabled. | ||
| [7] | WTE | Watchdog Timer Enable Control (Write Protect) |
| 0 = WDT Disabled. (This action will reset the internal up counter value.) | ||
| 1 = WDT Enabled. | ||
| [10:8] | WTIS | Watchdog Timer Interval Selection |
| These three bits select the time-out interval for the Watchdog Timer. | ||
| 000 = 24 * TWDT. | ||
| 001 = 26 * TWDT. | ||
| 010 = 28 * TWDT. | ||
| 011 = 210 * TWDT. | ||
| 100 = 212 * TWDT. | ||
| 101 = 214 * TWDT. | ||
| 110 = 216 * TWDT. | ||
| 111 = 218 * TWDT. | ||
| [31] | DBGACK_WDT | ICE Debug Mode Acknowledge Disable Control (Write Protect) |
| 0 = ICE debug mode acknowledgement effects WDT counting. | ||
| WDT up counter will be kept while CPU is hanging by ICE. | ||
| 1 = ICE debug mode acknowledgement Disabled. | ||
| WDT up counter will keep going no matter CPU is hanging by ICE or not. |
Definition at line 5625 of file Mini51Series.h.


2: /*
3: Code for managing color the X implementation of the PetscDraw routines.
5: Currently we default to using cmapping[0 to PETSC_DRAW_BASIC_COLORS-1] for the basic colors and
6: cmapping[DRAW_BASIC_COLORS to 255] for countour plots.
8: */
9: #include <../src/sys/classes/draw/impls/x/ximpl.h> 10: #include <X11/Xatom.h>
12: static const char *(colornames[PETSC_DRAW_BASIC_COLORS]) = {"white",
13: "black",
14: "red",
15: "green",
16: "cyan",
17: "blue",
18: "magenta",
19: "aquamarine",
20: "forestgreen",
21: "orange",
22: "violet",
23: "brown",
24: "pink",
25: "coral",
26: "gray",
27: "yellow",
28: "gold",
29: "lightpink",
30: "mediumturquoise",
31: "khaki",
32: "dimgray",
33: "yellowgreen",
34: "skyblue",
35: "darkgreen",
36: "navyblue",
37: "sandybrown",
38: "cadetblue",
39: "powderblue",
40: "deeppink",
41: "thistle",
42: "limegreen",
43: "lavenderblush",
44: "plum"};
46: /*
47: Sets up a color map for a display. This is shared by all the windows
48: opened on that display; this is to save time when windows are open so
49: each one does not have to create its own color map which can take 15 to 20 seconds
51: This is new code written 2/26/1999 Barry Smith,I hope it can replace
52: some older,rather confusing code.
54: The calls to XAllocNamedColor() and XAllocColor() are very slow
55: because we have to request from the X server for each
56: color. Could not figure out a way to request a large number at the
57: same time.
59: IMPORTANT: this code will fail if user opens windows on two different
60: displays: should add error checking to detect this. This is because all windows
61: share the same gColormap and gCmapping.
63: */
64: static Colormap gColormap = 0;
65: static PetscDrawXiPixVal gCmapping[256];
66: static unsigned char gCpalette[256][3];
68: PetscErrorCode PetscDrawSetUpColormap_Shared(Display *display,int screen,Visual *visual,Colormap colormap) 69: {
70: int i,k,ncolors = 256-PETSC_DRAW_BASIC_COLORS;
71: unsigned char R[256-PETSC_DRAW_BASIC_COLORS];
72: unsigned char G[256-PETSC_DRAW_BASIC_COLORS];
73: unsigned char B[256-PETSC_DRAW_BASIC_COLORS];
74: XColor colordef,ecolordef;
75: PetscBool fast = PETSC_FALSE;
79: if (colormap) gColormap = colormap;
80: else gColormap = DefaultColormap(display,screen);
83: /* set the basic colors into the color map */
84: for (i=0; i<PETSC_DRAW_BASIC_COLORS; i++) {
85: XAllocNamedColor(display,gColormap,colornames[i],&colordef,&ecolordef);
86: gCmapping[i] = colordef.pixel;
87: gCpalette[i][0] = (unsigned char)(colordef.red >> 8);
88: gCpalette[i][1] = (unsigned char)(colordef.green >> 8);
89: gCpalette[i][2] = (unsigned char)(colordef.blue >> 8);
90: }
92: /* set the contour colors into the colormap */
93: PetscOptionsGetBool(NULL,NULL,"-draw_fast",&fast,NULL);
94: PetscDrawUtilitySetCmap(NULL,ncolors,R,G,B);
95: for (i=0, k=PETSC_DRAW_BASIC_COLORS; i<ncolors; i++, k++) {
96: colordef.red = (unsigned short)(R[i] << 8);
97: colordef.green = (unsigned short)(G[i] << 8);
98: colordef.blue = (unsigned short)(B[i] << 8);
99: colordef.flags = DoRed|DoGreen|DoBlue;
100: colordef.pixel = gCmapping[PETSC_DRAW_BLACK];
101: if (!fast) XAllocColor(display,gColormap,&colordef);
102: gCmapping[k] = colordef.pixel;
103: gCpalette[k][0] = R[i];
104: gCpalette[k][1] = G[i];
105: gCpalette[k][2] = B[i];
106: }
108: PetscInfo(0,"Successfully allocated colors\n");
109: return(0);
110: }
112: /*
113: Keep a record of which pixel numbers in the cmap have been
114: used so far; this is to allow us to try to reuse as much of the current
115: colormap as possible.
116: */
117: static PetscBool cmap_pixvalues_used[256];
118: static int cmap_base = 0;
120: PetscErrorCode PetscDrawSetUpColormap_Private(Display *display,int screen,Visual *visual,Colormap colormap)121: {
122: int found,i,k,ncolors = 256-PETSC_DRAW_BASIC_COLORS;
123: unsigned char R[256-PETSC_DRAW_BASIC_COLORS];
124: unsigned char G[256-PETSC_DRAW_BASIC_COLORS];
125: unsigned char B[256-PETSC_DRAW_BASIC_COLORS];
126: Colormap defaultmap = DefaultColormap(display,screen);
127: XColor colordef;
128: PetscBool fast = PETSC_FALSE;
132: if (colormap) gColormap = colormap;
133: else gColormap = XCreateColormap(display,RootWindow(display,screen),visual,AllocAll);
135: cmap_base = 0;
137: PetscMemzero(cmap_pixvalues_used,256*sizeof(PetscBool));
139: /* set the basic colors into the color map */
140: for (i=0; i<PETSC_DRAW_BASIC_COLORS; i++) {
141: XParseColor(display,gColormap,colornames[i],&colordef);
142: /* try to allocate the color in the default-map */
143: found = XAllocColor(display,defaultmap,&colordef);
144: /* use it, if it it exists and is not already used in the new colormap */
145: if (found && colordef.pixel < 256 && !cmap_pixvalues_used[colordef.pixel]) {
146: cmap_pixvalues_used[colordef.pixel] = PETSC_TRUE;
147: /* otherwise search for the next available slot */
148: } else {
149: while (cmap_pixvalues_used[cmap_base]) cmap_base++;
150: colordef.pixel = cmap_base;
151: cmap_pixvalues_used[cmap_base++] = PETSC_TRUE;
152: }
153: XStoreColor(display,gColormap,&colordef);
154: gCmapping[i] = colordef.pixel;
155: gCpalette[i][0] = (unsigned char)(colordef.red >> 8);
156: gCpalette[i][1] = (unsigned char)(colordef.green >> 8);
157: gCpalette[i][2] = (unsigned char)(colordef.blue >> 8);
158: }
160: /* set the contour colors into the colormap */
161: PetscOptionsGetBool(NULL,NULL,"-draw_fast",&fast,NULL);
162: PetscDrawUtilitySetCmap(NULL,ncolors,R,G,B);
163: for (i=0, k=PETSC_DRAW_BASIC_COLORS; i<ncolors; i++, k++) {
164: colordef.red = (unsigned short)(R[i] << 8);
165: colordef.green = (unsigned short)(G[i] << 8);
166: colordef.blue = (unsigned short)(B[i] << 8);
167: colordef.flags = DoRed|DoGreen|DoBlue;
168: colordef.pixel = gCmapping[PETSC_DRAW_BLACK];
169: if (!fast) {
170: /* try to allocate the color in the default-map */
171: found = XAllocColor(display,defaultmap,&colordef);
172: /* use it, if it it exists and is not already used in the new colormap */
173: if (found && colordef.pixel < 256 && !cmap_pixvalues_used[colordef.pixel]) {
174: cmap_pixvalues_used[colordef.pixel] = PETSC_TRUE;
175: /* otherwise search for the next available slot */
176: } else {
177: while (cmap_pixvalues_used[cmap_base]) cmap_base++;
178: colordef.pixel = cmap_base;
179: cmap_pixvalues_used[cmap_base++] = PETSC_TRUE;
180: }
181: XStoreColor(display,gColormap,&colordef);
182: }
183: gCmapping[k] = colordef.pixel;
184: gCpalette[k][0] = R[i];
185: gCpalette[k][1] = G[i];
186: gCpalette[k][2] = B[i];
187: }
189: PetscInfo(0,"Successfully allocated colors\n");
190: return(0);
191: }
193: PetscErrorCode PetscDrawSetUpColormap_X(Display *display,int screen,Visual *visual,Colormap colormap)194: {
196: PetscBool sharedcolormap = PETSC_FALSE;
197: XVisualInfo vinfo;
200: PetscOptionsGetBool(NULL,NULL,"-draw_x_shared_colormap",&sharedcolormap,NULL);
201: /*
202: Need to determine if window supports allocating a private colormap,
203: */
204: if (XMatchVisualInfo(display,screen,24,StaticColor,&vinfo) ||
205: XMatchVisualInfo(display,screen,24,TrueColor,&vinfo) ||
206: XMatchVisualInfo(display,screen,16,StaticColor,&vinfo) ||
207: XMatchVisualInfo(display,screen,16,TrueColor,&vinfo) ||
208: XMatchVisualInfo(display,screen,15,StaticColor,&vinfo) ||
209: XMatchVisualInfo(display,screen,15,TrueColor,&vinfo)) sharedcolormap = PETSC_TRUE;
210: /*
211: Generate the X colormap object
212: */
213: if (sharedcolormap) {
214: PetscDrawSetUpColormap_Shared(display,screen,visual,colormap);
215: } else {
216: PetscDrawSetUpColormap_Private(display,screen,visual,colormap);
217: }
218: return(0);
219: }
221: PETSC_INTERN PetscErrorCode PetscDrawSetColormap_X(PetscDraw_X*,Colormap);
223: PetscErrorCode PetscDrawSetColormap_X(PetscDraw_X *XiWin,Colormap colormap)224: {
225: PetscBool fast = PETSC_FALSE;
229: PetscOptionsGetBool(NULL,NULL,"-draw_fast",&fast,NULL);
230: if (XiWin->depth < 8) SETERRQ(PETSC_COMM_SELF,PETSC_ERR_SUP_SYS,"PETSc Graphics require monitors with at least 8 bit color (256 colors)");
231: if (!gColormap) {
232: PetscDrawSetUpColormap_X(XiWin->disp,XiWin->screen,XiWin->vis,colormap);
233: }
234: XiWin->cmap = gColormap;
235: XiWin->cmapsize = fast ? PETSC_DRAW_BASIC_COLORS : 256;
236: PetscMemcpy(XiWin->cmapping,gCmapping,sizeof(XiWin->cmapping));
237: PetscMemcpy(XiWin->cpalette,gCpalette,sizeof(XiWin->cpalette));
238: XiWin->background = XiWin->cmapping[PETSC_DRAW_WHITE];
239: XiWin->foreground = XiWin->cmapping[PETSC_DRAW_BLACK];
240: return(0);
241: }
243: PetscErrorCode PetscDrawXiColormap(PetscDraw_X *XiWin)244: { return PetscDrawSetColormap_X(XiWin,(Colormap)0); }
246: /*
247: Color in X is many-layered. The first layer is the "visual",a
248: immutable attribute of a window set when the window is
249: created.
251: The next layer is the colormap. The installation of colormaps is
252: the buisness of the window manager (in some distant later release).
253: */
255: /*
256: This routine gets the visual class (PseudoColor, etc) and returns
257: it. It finds the default visual. Possible returns are
258: PseudoColor
259: StaticColor
260: DirectColor
261: TrueColor
262: GrayScale
263: StaticGray
264: */
265: PetscErrorCode PetscDrawXiSetVisualClass(PetscDraw_X *XiWin)266: {
267: XVisualInfo vinfo;
270: if (XMatchVisualInfo(XiWin->disp,XiWin->screen,24,DirectColor,&vinfo)) {
271: XiWin->vis = vinfo.visual;
272: } else if (XMatchVisualInfo(XiWin->disp,XiWin->screen,8,PseudoColor,&vinfo)) {
273: XiWin->vis = vinfo.visual;
274: } else if (XMatchVisualInfo(XiWin->disp,XiWin->screen,DefaultDepth(XiWin->disp,XiWin->screen),PseudoColor,&vinfo)) {
275: XiWin->vis = vinfo.visual;
276: } else {
277: XiWin->vis = DefaultVisual(XiWin->disp,XiWin->screen);
278: }
279: return(0);
280: }
282: PetscErrorCode PetscDrawXiSetColormap(PetscDraw_X *XiWin)283: {
285: XSetWindowColormap(XiWin->disp,XiWin->win,XiWin->cmap);
286: return(0);
287: }
289: /*
290: Get RGB color entries out of the X colormap
291: */
292: PetscErrorCode PetscDrawXiGetPalette(PetscDraw_X *XiWin,unsigned char palette[256][3])
293: {
294: int k;
295: XColor colordef[256];
298: for (k=0; k<256; k++) {
299: colordef[k].pixel = XiWin->cmapping[k];
300: colordef[k].flags = DoRed|DoGreen|DoBlue;
301: }
302: XQueryColors(XiWin->disp,XiWin->cmap,colordef,256);
303: for (k=0; k<256; k++) {
304: palette[k][0] = (unsigned char)(colordef[k].red >> 8);
305: palette[k][1] = (unsigned char)(colordef[k].green >> 8);
306: palette[k][2] = (unsigned char)(colordef[k].blue >> 8);
307: }
308: return(0);
309: }


About
[top]
=====
Whitelips is an online IDE for Whitespace.
What's New? [top]
===========
Version 0.13.1
- Links in "about" tab open in a new window.
- Memory tab is updated only when visible.
- Interpreter is way faster with fewer interruptions.
===========
Version 0.13.0:
- Memory can now hold arbitrary length values (BigInt).
- Added Malbolge interpreter and sample files.
- Added "about" tab for program descriptions.
===========
Version 0.10.1:
- Support for virtual machines. See vm/bf.ws.
- Support for compilers. See wc/bf2wsa.ws.
- New icons.
- Optional parameters for asm keywords - parameter is added using a push.
- Some bug fixes.
- EOF is interpreted as "no change".
Whitespace
[top]
==========
Whitespace is a language that does not force you to add semicolons at the end of
statements!
Assembly
[top]
========
As there is no official standard, Whitelips features it's own assembly
language. Care has been taken to make it compatible with others, but
this has never been a goal.
push $n - Push value $n onto the stack.
dup - Duplicate the topmost stack element.
copy $n - copies the $n-th element from stack, where 0 is the topmost
value.
swap - swap two topmost stack elements.
drop - discards the topmost stack value.
slide $n - keeps the topmost element, and deletes the next $n elements.
add -
sub -
mul -
div -
mod -
store -
retrieve -
label $l -
call $l -
jmp $l -
jz $l -
jn $l -
ret -
end - Terminate the program.
printc -
printi -
readc -
readi -
Where:
$n - an integer parameter.
$l - a label.
[top]
Optimizer
[top]
=========
The main philosophy behind the optimizer is that all Whitespace instructions are
equally slow. This means that all optimizations are made to reduce the number of
instructions. Optimizer guarantees that the number of instructions in the output
is less or equal to the original program.
As a secondary objective, the optimizer tries to reduce the size of the program to
speed up parsing. The optimizer does not guarantee that the output code is smaller
or equal in bytes compared to the initial program.
The optimizer works on the Whitespace instruction level, which means the assembly
programs can not be optimized directly - they have to be compiled into Whitespace.
This is a serious restriction by design.
Rules:
* Remove unreachable code.
* Inline unconditional jumps, if possible.
* Inline function calls.
* Remove unused and duplicate labels.
* Mimimize label names by usage in the program.
[top]


Library: Crypto
Package: Cipher
Header: Poco/Crypto/CipherKey.h
Description
CipherKey stores the key information for decryption/encryption of data. To create a random key, using the following code:
CipherKey key("aes-256");
Note that you won't be able to decrypt data encrypted with a random key once the Cipher is destroyed unless you persist the generated key and IV. An example usage for random keys is to encrypt data saved in a temporary file.
To create a key using a human-readable password string, use the following code. We create a AES Cipher and use a salt value to make the key more robust:
std::string password = "secret"; std::string salt("asdff8723lasdf(**923412"); CipherKey key("aes-256", password, salt);
Member Summary
Member Functions: blockSize, getIV, getKey, impl, ivSize, keySize, mode, name, setIV, setKey
Types
ByteVec
typedef CipherKeyImpl::ByteVec ByteVec;
Mode
typedef CipherKeyImpl::Mode Mode;
Enumerations
Anonymous
DEFAULT_ITERATION_COUNT = 2000
Default iteration count to use with generateKey(). RSA security recommends an iteration count of at least 1000.
Constructors
CipherKey
CipherKey(
const std::string & name
);
Creates a new CipherKeyImpl object. Autoinitializes key and initialization vector.
CipherKey
CipherKey(
const std::string & name,
const ByteVec & key,
const ByteVec & iv
);
Creates a new CipherKeyImpl object using the given cipher name, key and initialization vector.
CipherKey
CipherKey(
const std::string & name,
const std::string & passphrase,
const std::string & salt = "",
int iterationCount = DEFAULT_ITERATION_COUNT
);
Creates a new CipherKeyImpl object using the given cipher name, passphrase, salt value and iteration count.
Destructor
~CipherKey
~CipherKey();
Destroys the CipherKeyImpl.
Member Functions
blockSize
int blockSize() const;
Returns the block size of the Cipher.
getIV
const ByteVec & getIV() const;
Returns the initialization vector (IV) for the Cipher.
getKey
const ByteVec & getKey() const;
Returns the key for the Cipher.
impl
CipherKeyImpl::Ptr impl();
Returns the impl object
ivSize
int ivSize() const;
Returns the IV size of the Cipher.
keySize
int keySize() const;
Returns the key size of the Cipher.
mode
Mode mode() const;
Returns the Cipher's mode of operation.
name
const std::string & name() const;
Returns the name of the Cipher.
setIV
void setIV(
const ByteVec & iv
);
Sets the initialization vector (IV) for the Cipher.
setKey
void setKey(
const ByteVec & key
);
Sets the key for the Cipher.


| 045:017 Khan | : |
And gave them clear proofs in matters [by revealing to them the Taurat (Torah)]. And they differed not until after the knowledge came to them, through envy among themselves. Verily, Your Lord will judge between them on the Day of Resurrection about that wherein they used to differ. |
| 045:017 Maulana | : |
And we gave them clear arguments in the Affair. So they differed not until after knowledge had come to them, out of envy among themselves. Surely thy Lord will judge between them on the day of Resurrection concerning that wherein they differed. |
| 045:017 Pickthal | : |
And gave them plain commandments. And they differed not until after the knowledge came unto them, through rivalry among themselves. Lo! thy Lord will judge between them on the Day of Resurrection concerning that wherein they used to differ. |
| 045:017 Rashad | : |
We have given them herein clear commandments. Ironically, they did not dispute this until the knowledge had come to them. This is due to jealousy on their part. Surely, your Lord will judge them on the Day of Resurrection regarding everything they have disputed. |
| 045:017 Sarwar | : |
We also gave them clear evidence in support of the true religion. Only after having received knowledge did they create differences among themselves because of their rebelliousness. Your Lord will issue His decree concerning their differences on the Day of Judgment. |
| 045:017 Shakir | : |
And We gave them clear arguments in the affair, but they did not differ until after knowledge had come to them out of envy among themselves; surely your -Lord will judge between them on the day of resurrection concerning that wherein they differed. |
| 045:017 Sherali | : |
And WE gave them clear Signs regarding this Affair. And they did not differ but after true knowledge had come to them, through mutual envy. Verily, thy Lord will judge between them on the Day of Resurrection concerning that wherein they differed. |
| 045:017 Yusufali | : |
And We granted them Clear Signs in affairs (of Religion): it was only after knowledge had been granted to them that they fell into schisms, through insolent envy among themselves. Verily thy Lord will judge between them on the Day of Judgment as to those matters in which they set up differences. |
Concepts/Themes Covered: أركان الإسلام > التوحيد > توحيد الله تعالي > ربوبيته جلّ وعلا Pillars of Islam> Islamic> Oneness of Allah> His Divinity, the Great and Almighty أركان الإسلام > التوحيد > الكافرون > وجوب الاعراض عن الكفار Pillars of Islam> Islamic> The Disbelievers> The Prohibition to avoid the Atheists الإنسان والعلاقات الاجتماعية > المجتمعات > اختلاف الناس Man and The Social Relations>The Societies>Different Kinds of People الديانات > بنو إسرائيل > معاندتهم و تكذيبهم و قتلهم الأنبياء Religions>Children of Israel> Their Opposition, their Denial and their Killing the Prophets الديانات > بنو إسرائيل > نعم الله عليهم Religions>Children of Israel>Allah Gifts on them
This tool uses eight English parallel translations for the Holy Quran imported from Mr. Clay Smith. You can also visit Qurany Concepts for browsing the Quran themes or topics. If you want to search the Holy Quran for keywords, please visit Qurany Keywords.


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property of class JsNgramReader
Description
Store verbose data for test and debug.
Example
chk = jsngram.jsngram.JsNgramReader(src) chk.read_files(True) print(chk.work)
Usage
Data structure is as followings: { files: [(file name, full path of file),,,], keys: [(decoded key string, decoded character list of key),,,], data: [decoded data from a json file,,,], reverse: work space of method reverse }


adjust if things look or
another city?
color scheme: {% for c in color_scheme_dict %} {% ifequal c color_scheme %} {{ c }} {% else %} {{ c }} {% endifequal %} {% endfor %}
width and height in px: Must be a number between 0 and 640 pixels.
(re)generating map... it will periodically update itself as you check into more places, but the links won't change
deleting map...