Med Flight, two ambulances called to head-on collision in Mazomanie
by Logan RudeMAZOMANIE, Wis. - Med Flight and two ambulances were called to assist with a two-vehicle head-on crash in Mazomanie just after 10:45 a.m. Sunday, according to Dane County Dispatch.
The crash happened at 105 E. Hudson St. At least two people were injured in the crash, according to Dane County Dispatch.


--- title: Easy To Remember Secure Password Generator | Developer Tools layout: post ---
{% include common-meta %}This is a free online tool to do simple password generation that you can easily remember. Generally coming up with a secured password is not easy. Even if you create a secure password it become hard to remember. This password tool can suggest a complex password based on your choice of words or sentences.
Complex password is essential to keep your data secure online. All complex passwords may not be easy to remember. We use simple simple well known techniques to suggest relatively secure passwords. This helps you stay secure at the same time remember your password.
Since the password is based on your input it may be easy to remember. We do minor noticeable changes in your words to generate a complex looking password. Some techniques are obvious and some you can learn as you see them.
We randomly replace the alphabets with their similar looking characters. This will make it easy to remember but partly random password. For example letter lowercase s
can be replaced with any one of these S, 5, $
Since this password is based on your input its complexity mainly depends on your inputs.  It is also well known fact that no password is secure. However, as the complexity is high there is a low risk of compromise.
Please note that we are using a randomization logic to generate these passwords and sometimes you may end up with not very complex password. We recommend you to retry generation and do it until you think it is complex enough.
You can enter a word or sentence that you can remember easily. For example, you can use a street address, or favorite movie title, or anything that you can remember in future.
Note: Do not enter any sensitive informaiton on this page.


Add Job Types
When a new kind of job is required for backend processing, it has to be done properly in order to ensure it is used, set up, and processed by NCA.
- Make sure there aren’t already existing jobs that do what you want! There
are a lot of jobs in NCA already, and some are meant to be very generic, such
as
JobTypeRenameDir
.- Read and make sure you understand all structs in
src/jobs
that implementProcess
- Read and make sure you understand all structs in
- Create a new
JobType
insrc/models/job.go
.- Add the
JobType
to the const list- Make sure the string is 100% unique within that list!
- Add the new
JobType
to theValidJobTypes
list
- Add the
- Create a new struct that implements the
Process
method.- Use an existing Go file if it makes sense (e.g., another metadata or
filesystem job) or create a new one in
src/jobs/
. - Make sure you document the type! What is its purpose?
- Need an example? The metadata jobs are very simple and can be found in
src/jobs/metadata_jobs.go
.
- Use an existing Go file if it makes sense (e.g., another metadata or
filesystem job) or create a new one in
- Wire up the
JobType
to the concreteProcess
implementor- This is done in
src/jobs/jobs.go
, in theDBJobToProcessor
function
- This is done in
- Queue a job of the new type.
- See
src/jobs/queue.go
- You might need to create a new arg value in
src/models/pipeline.go
, likeJobArgSource
,JobArgWorkflowStep
, etc. - You will certainly need to create the job and push it into a queue. This
happens in a
Queue...
function (e.g.,QueueBatchForDeletion
).
- See
- Make something run jobs of the new type.
- For almost any new job, you’ll just add the type to an existing runner
function in
src/cmd/run-jobs/main.go
(runAllQueues
). This ensures a simple job runner invocation (with thewatchall
argument) will run your new job type.
- For almost any new job, you’ll just add the type to an existing runner
function in


Comments
-
Greg Hurrell
(In reply to comment #0)
Currently WinSwitch never appears in the Accounts Preferences Pane's Startup Items list, so it always loads unless it has been manually uninstalled. I'm not an experienced developer, so I'm guessing, but I'm pretty sure that Menu Extras are not managed through this Pref pane interface, only applications.
That's correct. True menu extras (NSMenuExtra) are not applications but loadable bundles. The System UI Server maintains a list of loaded menu extras and each time you log in or boot up it loads the same menu extras; no applications are involved. Menu extras are added/removed by telling the System UI Server to load/unload those bundles.
Things which aren't "true" menu extras are implemented using NSStatusItem and they are not loadable bundles. They need a separate application to host them. Such an application could be added/removed to your startup items list. Most third-party tools use this technique.
What this in effect means is that true menu extras can't be managed using startup items; only applications can be managed that way.
I have some other utilities in use that add Menu Extras, but they do this by using an application which launches and then triggers the menu extra. Whether the app launches at startup is controllable in the Prefs pane.
WinSwitch is a true menu extra because that's the only way to get it to appear all the way over to the right side, as the user expects for a fast user switching menu.
It could be changed into an application that runs at login time and loads the loadable bundle, but it would also have to remove itself on every logout otherwise it would appear automatically on the next login anyway (because as noted above, the System UI Server maintains a list of loaded menu extras and automatically reloads them on subsequent logins).
This effectively amounts to installing/uninstalling itself automatically on every single run, which is not very efficient.
This enhancement would give people (for example, people who have a need to run with an otherwise "standard" menu bar for things like making screen shots and creating training video) boot-by-boot control over WinSwitch without having to install/reinstall.
I think a better workaround for the purposes of taking screenshots is the following:
1. Before the screenshot, hold down the "Command" key and drag WinSwitch out of the menu bar.
2. After the screenshot, double-click the "Activate WinSwitch" script installed into /Users/Shared to restore it to the menu bar.
Admittedly, this is not fully-automated, but the alternatively is just too ugly from a design standpoint because it would mean using NSMenuExtra in a way that violates its intended usage pattern.
-
Greg Hurrell
For the reasons stated above, marking this one as "WONTFIX" but seeing as the source is available anyone interested in going down this path knows what to do...
-
jim
Reasonable conclusion. (Sorry for the delay in my response.) Perhaps there's a way to automate unloading the bundle through applescripts, and triggering the status of those scripts through the Winswitch UI...I'll have to think it over. But your response and thoughtful comments are appreciated.
Add a comment
Comments are now closed for this issue.


Before we talk about classes, let's talk a little bit about OOP(Object-Oriented Programming).
In general, programming is all about taking actions with information(data). Good example would be a HTML form: user enters her information into a form, a program validates it, then stores the information in the database. You can ultimately say that what the program is doing is just taking nouns(data) and using verbs to do something with the nouns. In procedural programming(without classes), its focus is on the verbs. Do this, then do that. With OOP, the focus is on the nouns, and that is made possible by using objects. But objects need a guide to tell them what to do, and taht's where classes come into the mix.
To simply put, a class is a collection of methods designed to work together to do 'something' with a particular information, and in Ruby, the information is called instance variables and instance methods are the ones that do 'something' with them.
Let's say that we want to create a class called Users. (By the way, in Ruby, the first letters of class names are usually capitalized.) The first instance method we define is #initialize which takes two parameters first_name and last_name. This method is called every time an instance of this Users class is instantiated. Inside initialize, instance variables @first_name and @last_name is created using the arguments provided. The next instance method we define is called create_username. This method takes one parameter which becomes @username inside of it. #create_password is similar to #create_username. It assigns @password to the password provided. The last four instance methods #first_name, #last_name, #username and #password are used to access each instance variable that was previously defined.
@last_name = last_name
end
user = Users.new('eiko', 'seino') # new instance of Users is created
user.create_username(username) # username called 'username' is created
user.password(password) # password called 'password' is created
user.lastname # => 'seino'
user.username # => 'username'


--- layout: post title: Setting up bridged networking on vmware for ncp2 date: 2008-08-12 06:23:02.000000000 +05:30 categories: - Nexenta - Opensolaris - tech - ubuntu tags: - networking - Nexenta status: publish type: post published: true meta: _edit_last: '1' author: login: admin email<EMAIL_ADDRESS>display_name: admin first_name: '' last_name: '' ---
I had a little trouble setting up VMware to share the host's (Ubuntu) nic interface eth0 (with static ip) with the guest ncp2.
Follow the instrucions here to setup a VMware install: http://www.nexenta.org/os/Getting_Started
When you need to pass network settings, for a static IP configuration on the host, follow the below steps.
Lets say the guest is setup as
IP:<IP_ADDRESS>, with netmask <IP_ADDRESS> and router <IP_ADDRESS>
Then host needs to be
IP: <IP_ADDRESS> (or 4 or 5..), with netmask <IP_ADDRESS> and router <IP_ADDRESS>


Synthesis Report #Build: Synplify Pro L-2016.09L-1, Build 147R, Mar 7 2017 #install: C:\lscc\diamond\3.9_x64\synpbase #OS: Windows 7 6.1 #Hostname: TINO-ALPHA1 # Wed Oct 03 00:10:13 2018 #Implementation: FleaDSO Synopsys HDL Compiler, version comp2016q3p1, Build 284R, built Mar 10 2017 @N|Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys VHDL Compiler, version comp2016q3p1, Build 284R, built Mar 10 2017 @N|Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @N: CD720 :"C:\lscc\diamond\3.9_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ps @N:"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":19:7:19:21|Top entity is set to FleaFPGA_Ohm_A5. File C:\lscc\diamond\3.9_x64\synpbase\lib\lucent\ecp5u.vhd changed - recompiling File C:\lscc\diamond\3.9_x64\examples\FleaDSO\ADC_PLL\ADC_PLL.vhd changed - recompiling File C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd changed - recompiling File C:\lscc\diamond\3.9_x64\examples\FleaDSO\ddr_out\ddr_out.vhd changed - recompiling File C:\lscc\diamond\3.9_x64\examples\FleaDSO\DVI_clkgen\DVI_clkgen.vhd changed - recompiling File C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\DVI_D.vhd changed - recompiling File C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd changed - recompiling VHDL syntax check successful! File C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd changed - recompiling @N: CD630 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":19:7:19:21|Synthesizing work.fleafpga_ohm_a5.arch. @W: CD326 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":197:17:197:32|Port rxint of entity work.simple_uart is unconnected. If a port needs to remain unconnected, use the keyword open. @W: CD326 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":197:17:197:32|Port rxdata of entity work.simple_uart is unconnected. If a port needs to remain unconnected, use the keyword open. @W: CD326 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":197:17:197:32|Port txready of entity work.simple_uart is unconnected. If a port needs to remain unconnected, use the keyword open. @W: CD638 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":119:10:119:16|Signal clk_pcs is undriven. Either assign the signal a value or remove the signal declaration. @N: CD630 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":8:7:8:17|Synthesizing work.simple_uart.rtl. @N: CD231 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":44:14:44:15|Using onehot encoding for type rxstates. For example, enumeration idle is mapped to "10000". @N: CD231 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":51:14:51:15|Using onehot encoding for type txstates. For example, enumeration idle is mapped to "10". @W: CD434 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":102:13:102:17|Signal reset in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process. @N: CD604 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":172:4:172:17|OTHERS clause is not synthesized. @W: CD434 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":128:28:128:36|Signal rxcounter in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process. @N: CD604 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":212:4:212:17|OTHERS clause is not synthesized. @W: CD434 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":183:19:183:22|Signal txgo in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process. @W: CD434 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":183:24:183:32|Signal txcounter in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process. Post processing for work.simple_uart.rtl @A: CL282 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":130:2:130:3|Feedback mux created for signal rxbuffer[8:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A: CL282 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":130:2:130:3|Feedback mux created for signal rxdata[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A: CL282 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":185:2:185:3|Feedback mux created for signal txbuffer[18:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @N: CL189 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":185:2:185:3|Register bit txbuffer(18) is always 0. @W: CL260 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":185:2:185:3|Pruning register bit 18 of txbuffer(18 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N: CD630 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\DVI_D.vhd":15:7:15:10|Synthesizing work.dvid.behavioral. @W: CD638 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\DVI_D.vhd":49:8:49:14|Signal dummy20 is undriven. Either assign the signal a value or remove the signal declaration. @W: CD638 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\DVI_D.vhd":51:8:51:14|Signal dummy21 is undriven. Either assign the signal a value or remove the signal declaration. @W: CD638 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\DVI_D.vhd":53:8:53:14|Signal dummy22 is undriven. Either assign the signal a value or remove the signal declaration. @W: CD638 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\DVI_D.vhd":55:8:55:14|Signal dummy23 is undriven. Either assign the signal a value or remove the signal declaration. @N: CD630 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\ddr_out\ddr_out.vhd":12:7:12:13|Synthesizing work.ddr_out.structure. @N: CD630 :"C:\lscc\diamond\3.9_x64\cae_library\synthesis\vhdl\ecp5u.vhd":2007:10:2007:16|Synthesizing work.oddrx1f.syn_black_box. Post processing for work.oddrx1f.syn_black_box @N: CD630 :"C:\lscc\diamond\3.9_x64\cae_library\synthesis\vhdl\ecp5u.vhd":1022:10:1022:11|Synthesizing work.ob.syn_black_box. Post processing for work.ob.syn_black_box @N: CD630 :"C:\lscc\diamond\3.9_x64\cae_library\synthesis\vhdl\ecp5u.vhd":823:10:823:12|Synthesizing work.vhi.syn_black_box. Post processing for work.vhi.syn_black_box @N: CD630 :"C:\lscc\diamond\3.9_x64\cae_library\synthesis\vhdl\ecp5u.vhd":830:10:830:12|Synthesizing work.vlo.syn_black_box. Post processing for work.vlo.syn_black_box Post processing for work.ddr_out.structure @N: CD630 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\TDMS_encoder.vhd":14:7:14:18|Synthesizing work.tdms_encoder.behavioral. Post processing for work.tdms_encoder.behavioral Post processing for work.dvid.behavioral @N: CD630 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\DVI_clkgen\DVI_clkgen.vhd":12:7:12:16|Synthesizing work.dvi_clkgen.structure. @N: CD630 :"C:\lscc\diamond\3.9_x64\cae_library\synthesis\vhdl\ecp5u.vhd":2081:10:2081:16|Synthesizing work.ehxplll.syn_black_box. Post processing for work.ehxplll.syn_black_box Post processing for work.dvi_clkgen.structure @W: CL168 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\DVI_clkgen\DVI_clkgen.vhd":53:4:53:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N: CD630 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":26:7:26:18|Synthesizing work.fleafpga_dso.behavior. @W: CD638 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":59:9:59:19|Signal sampler_raw is undriven. Either assign the signal a value or remove the signal declaration. @W: CD638 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":61:9:61:22|Signal adc_currentraw is undriven. Either assign the signal a value or remove the signal declaration. @N: CD630 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\DSO_RAMBUFFER_CH1\DSO_RAMBUFFER_CH1.vhd":12:7:12:23|Synthesizing work.dso_rambuffer_ch1.structure. @N: CD630 :"C:\lscc\diamond\3.9_x64\cae_library\synthesis\vhdl\ecp5u.vhd":1128:10:1128:15|Synthesizing work.dp16kd.syn_black_box. Post processing for work.dp16kd.syn_black_box Post processing for work.dso_rambuffer_ch1.structure @N: CD630 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\Simple_VGA_CRTC.vhd":40:7:40:20|Synthesizing work.vga_controller.behavior. Post processing for work.vga_controller.behavior @A: CL282 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\Simple_VGA_CRTC.vhd":80:4:80:5|Feedback mux created for signal row[9:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A: CL282 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\Simple_VGA_CRTC.vhd":80:4:80:5|Feedback mux created for signal column[9:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @N: CD630 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\ADC_PLL\ADC_PLL.vhd":12:7:12:13|Synthesizing work.adc_pll.structure. Post processing for work.adc_pll.structure @W: CL168 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\ADC_PLL\ADC_PLL.vhd":45:4:45:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. Post processing for work.fleafpga_dso.behavior @W: CL271 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Pruning unused bits 17 to 9 of vga_trigger_scaled_3(17 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W: CL271 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Pruning unused bits 17 to 9 of vga_bufout_scaled_3(17 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @A: CL282 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":163:3:163:4|Feedback mux created for signal ADC_lowspeed_raw[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @N: CL189 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Register bit Blue_out(3) is always 0. @W: CL260 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Pruning register bit 3 of Blue_out(3 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. Post processing for work.fleafpga_ohm_a5.arch @W: CL240 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":100:1:100:8|Signal mmc_mosi is floating; a simulation mismatch is possible. @W: CL240 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":99:1:99:7|Signal mmc_clk is floating; a simulation mismatch is possible. @W: CL240 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":52:1:52:9|Signal Dram_DQML is floating; a simulation mismatch is possible. @W: CL240 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":51:1:51:9|Signal Dram_DQMH is floating; a simulation mismatch is possible. @W: CL240 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":47:1:47:9|Signal Dram_Addr is floating; a simulation mismatch is possible. @W: CL240 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":46:1:46:7|Signal Dram_BA is floating; a simulation mismatch is possible. @W: CL240 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":45:1:45:9|Signal Dram_n_We is floating; a simulation mismatch is possible. @W: CL240 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":44:1:44:10|Signal Dram_n_Cas is floating; a simulation mismatch is possible. @W: CL240 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":43:1:43:10|Signal Dram_n_Ras is floating; a simulation mismatch is possible. @W: CL240 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":41:1:41:8|Signal Dram_Clk is floating; a simulation mismatch is possible. @W: CL167 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":197:17:197:32|Input txgo of instance myuart is floating @N: CL189 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\Simple_VGA_CRTC.vhd":80:4:80:5|Register bit row(9) is always 0. @W: CL260 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\Simple_VGA_CRTC.vhd":80:4:80:5|Pruning register bit 9 of row(9 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N: CL189 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Register bit gridrow(0) is always 0. @N: CL189 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Register bit gridrow(1) is always 0. @N: CL189 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Register bit gridrow(2) is always 0. @N: CL189 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Register bit gridrow(3) is always 0. @N: CL189 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Register bit gridrow(4) is always 1. @N: CL189 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Register bit gridrow(5) is always 1. @W: CL190 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":163:3:163:4|Optimizing register bit adc_rawout(13) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL260 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":163:3:163:4|Pruning register bit 13 of adc_rawout(13 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W: CL279 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Pruning register bits 5 to 0 of gridrow(8 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W: CL190 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":163:3:163:4|Optimizing register bit adc_rawout(12) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL260 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":163:3:163:4|Pruning register bit 12 of adc_rawout(12 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W: CL190 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":163:3:163:4|Optimizing register bit adc_rawout(11) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: CL260 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":163:3:163:4|Pruning register bit 11 of adc_rawout(11 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N: CL189 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":163:3:163:4|Register bit ADC_lowspeed_raw(7) is always 0. @W: CL279 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Pruning register bits 2 to 1 of Green_out(3 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W: CL279 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Pruning register bits 2 to 1 of Red_out(3 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W: CL279 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":263:2:263:3|Pruning register bits 2 to 1 of Blue_out(2 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W: CL260 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_DSO.vhd":163:3:163:4|Pruning register bit 7 of ADC_lowspeed_raw(7 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N: CL159 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\simple_uart.vhd":16:2:16:5|Input txgo is unused. @N: CL159 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":38:1:38:11|Input slave_cts_i is unused. @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":48:1:48:9|Inout Dram_Data is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":55:1:55:6|Inout GPIO_2 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":56:1:56:6|Inout GPIO_3 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":57:1:57:6|Inout GPIO_4 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":59:1:59:6|Inout GPIO_6 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":60:1:60:6|Inout GPIO_7 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":61:1:61:6|Inout GPIO_8 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":62:1:62:6|Inout GPIO_9 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":63:1:63:7|Inout GPIO_10 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":64:1:64:7|Inout GPIO_11 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":65:1:65:7|Inout GPIO_12 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":66:1:66:7|Inout GPIO_13 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":67:1:67:7|Inout GPIO_14 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":68:1:68:7|Inout GPIO_15 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":69:1:69:7|Inout GPIO_16 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":70:1:70:7|Inout GPIO_17 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":71:1:71:7|Inout GPIO_18 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":72:1:72:7|Inout GPIO_19 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":75:1:75:7|Inout GPIO_22 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":76:1:76:7|Inout GPIO_23 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":77:1:77:7|Inout GPIO_24 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":78:1:78:7|Inout GPIO_25 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":79:1:79:7|Inout GPIO_26 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":80:1:80:7|Inout GPIO_27 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":81:1:81:9|Inout GPIO_IDSD is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":82:1:82:9|Inout GPIO_IDSC is unused @N: CL159 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":96:1:96:8|Input mmc_dat1 is unused. @N: CL159 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":97:1:97:8|Input mmc_dat2 is unused. @N: CL159 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":101:1:101:8|Input mmc_miso is unused. @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":105:1:105:8|Inout PS2_clk1 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":106:1:106:9|Inout PS2_data1 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":108:1:108:8|Inout PS2_clk2 is unused @W: CL158 :"C:\lscc\diamond\3.9_x64\examples\FleaDSO\source\FleaFPGA_2v5_DSO_toplevel.vhd":109:1:109:9|Inout PS2_data2 is unused At c_vhdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 85MB peak: 97MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Oct 03 00:10:15 2018 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 279R, built Mar 8 2017 @N|Running in 64-bit mode File C:\lscc\diamond\3.9_x64\examples\FleaDSO\FleaDSO\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Oct 03 00:10:15 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Oct 03 00:10:15 2018 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 279R, built Mar 8 2017 @N|Running in 64-bit mode File C:\lscc\diamond\3.9_x64\examples\FleaDSO\FleaDSO\synwork\FleaDSO_FleaDSO_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Oct 03 00:10:17 2018 ###########################################################] Pre-mapping Report # Wed Oct 03 00:10:17 2018 Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1682R, Built Mar 10 2017 10:47:08 Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09L-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @A: MF827 |No constraint file specified. @L: C:\lscc\diamond\3.9_x64\examples\FleaDSO\FleaDSO\FleaDSO_FleaDSO_scck.rpt Printing clock summary report in "C:\lscc\diamond\3.9_x64\examples\FleaDSO\FleaDSO\FleaDSO_FleaDSO_scck.rpt" file @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @W: BN287 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":130:2:130:3|Register rxstate[0:4] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Register txstate[0:1] with reset has an initial value of 1. Ignoring initial value. @W: BN132 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":263:2:263:3|Removing sequential instance user_module1.addpixel2[8:0] because it is equivalent to instance user_module1.addpixel1[8:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Removing sequential instance txready (in view: work.simple_uart(rtl)) of type view:PrimLib.dffse(prim) because it does not drive other instances. @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":130:2:130:3|Removing sequential instance rxdata[7:0] (in view: work.simple_uart(rtl)) of type view:PrimLib.dffe(prim) because it does not drive other instances. @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":130:2:130:3|Removing sequential instance rxint (in view: work.simple_uart(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Removing sequential instance txint (in view: work.simple_uart(rtl)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":104:2:104:3|Removing sequential instance rxcounter[15:0] (in view: work.simple_uart(rtl)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":130:2:130:3|Removing sequential instance rxstate[0:4] (in view: work.simple_uart(rtl)) of type view:PrimLib.dffpatre(prim) because it does not drive other instances. @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":130:2:130:3|Removing sequential instance rxbuffer[8:0] (in view: work.simple_uart(rtl)) of type view:PrimLib.dffe(prim) because it does not drive other instances. @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":104:2:104:3|Removing sequential instance rxclock (in view: work.simple_uart(rtl)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":64:2:64:3|Removing sequential instance rxd_sync2 (in view: work.simple_uart(rtl)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":64:2:64:3|Removing sequential instance rxd_sync (in view: work.simple_uart(rtl)) of type view:PrimLib.dff(prim) because it does not drive other instances. @W: BN114 :"c:\lscc\diamond\3.9_x64\examples\fleadso\ddr_out\ddr_out.vhd":52:4:52:16|Removing instance Inst3_ODDRX1F (in view: work.ddr_out_0(structure)) of black box view:work.ODDRX1F(syn_black_box) because it does not drive other instances. @W: BN114 :"c:\lscc\diamond\3.9_x64\examples\fleadso\ddr_out\ddr_out.vhd":52:4:52:16|Removing instance Inst3_ODDRX1F (in view: work.ddr_out_1(structure)) of black box view:work.ODDRX1F(syn_black_box) because it does not drive other instances. @W: BN114 :"c:\lscc\diamond\3.9_x64\examples\fleadso\ddr_out\ddr_out.vhd":52:4:52:16|Removing instance Inst3_ODDRX1F (in view: work.ddr_out_2(structure)) of black box view:work.ODDRX1F(syn_black_box) because it does not drive other instances. @W: BN114 :"c:\lscc\diamond\3.9_x64\examples\fleadso\ddr_out\ddr_out.vhd":52:4:52:16|Removing instance Inst3_ODDRX1F (in view: work.ddr_out_3(structure)) of black box view:work.ODDRX1F(syn_black_box) because it does not drive other instances. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 syn_allowed_resources : blockrams=56 set on top level netlist FleaFPGA_Ohm_A5 Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------------------------------------------------------------- ADC_PLL|CLKOP_inferred_clock 491.6 MHz 2.034 inferred Autoconstr_clkgroup_3 45 ADC_PLL|CLKOS_inferred_clock 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_4 102 DVI_clkgen|CLKOP_inferred_clock 657.5 MHz 1.521 inferred Autoconstr_clkgroup_2 40 DVI_clkgen|CLKOS2_inferred_clock 334.6 MHz 2.989 inferred Autoconstr_clkgroup_1 72 DVI_clkgen|CLKOS3_inferred_clock 593.1 MHz 1.686 inferred Autoconstr_clkgroup_0 38 System 1.0 MHz 1000.000 system system_clkgroup 0 vga_controller|v_sync_derived_clock 1.0 MHz 1000.000 derived (from ADC_PLL|CLKOS_inferred_clock) Autoconstr_clkgroup_4 50 =================================================================================================================================================== @W: MT529 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":82:2:82:3|Found inferred clock DVI_clkgen|CLKOS3_inferred_clock which controls 38 sequential elements including myuart.txcounter[15:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W: MT529 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\tdms_encoder.vhd":76:6:76:7|Found inferred clock DVI_clkgen|CLKOS2_inferred_clock which controls 72 sequential elements including u100.u21.dc_bias[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W: MT529 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\dvi_d.vhd":110:6:110:7|Found inferred clock DVI_clkgen|CLKOP_inferred_clock which controls 40 sequential elements including u100.shift_red[0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W: MT529 :"c:\lscc\diamond\3.9_x64\examples\fleadso\dso_rambuffer_ch1\dso_rambuffer_ch1.vhd":51:4:51:26|Found inferred clock ADC_PLL|CLKOP_inferred_clock which controls 45 sequential elements including user_module1.U3.DSO_RAMBUFFER_CH1_0_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W: MT529 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_vga_crtc.vhd":80:4:80:5|Found inferred clock ADC_PLL|CLKOS_inferred_clock which controls 102 sequential elements including user_module1.U2.row_1[8:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. Finished Pre Mapping Phase. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) None None Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Oct 03 00:10:18 2018 ###########################################################] Map & Optimize Report # Wed Oct 03 00:10:18 2018 Synopsys Lattice Technology Mapper, Version maplat, Build 1682R, Built Mar 10 2017 10:47:08 Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09L-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB) Available hyper_sources - for debug and ip models None Found @N: MT206 |Auto Constrain mode is enabled @N: MF236 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":271:29:271:57|Generating a type div divider @N: MF236 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":268:28:268:58|Generating a type div divider @W: BN132 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":263:2:263:3|Removing sequential instance user_module1.set_pixel2 because it is equivalent to instance user_module1.set_pixel1. To keep the instance, apply constraint syn_preserve=1 on the instance. @N: FX493 |Applying initial value "10000000000000" on instance user_module1.sample_rate[13:0]. @N: FX493 |Applying initial value "0000000000" on instance u100.shift_red[9:0]. @N: FX493 |Applying initial value "0000000000" on instance u100.shift_green[9:0]. @N: FX493 |Applying initial value "0000000000" on instance u100.shift_blue[9:0]. @N: FX493 |Applying initial value "0000011111" on instance u100.shift_clock[9:0]. @N: FX493 |Applying initial value "0000000000" on instance u100.latched_red[9:0]. @N: FX493 |Applying initial value "0000000000" on instance u100.latched_green[9:0]. @N: FX493 |Applying initial value "0000000000" on instance u100.latched_blue[9:0]. Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB) @N: MO231 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":163:3:163:4|Found counter in view:work.FleaFPGA_DSO(behavior) instance ADC_buffer_addr[9:0] @N: MO231 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":163:3:163:4|Found counter in view:work.FleaFPGA_DSO(behavior) instance ADC_sample_divider[13:0] @N: MF179 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":306:9:306:52|Found 9 by 9 bit equality operator ('==') un33_vga_disp_en (in view: work.FleaFPGA_DSO(behavior)) @N: MF179 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":316:8:316:49|Found 9 by 9 bit equality operator ('==') un37_vga_disp_en (in view: work.FleaFPGA_DSO(behavior)) @N: MF179 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":184:9:184:53|Found 9 by 9 bit equality operator ('==') un1_adc_rawout (in view: work.FleaFPGA_DSO(behavior)) @N: MF179 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":285:8:285:47|Found 9 by 9 bit equality operator ('==') un11_vga_disp_en (in view: work.FleaFPGA_DSO(behavior)) @N: MF179 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":178:8:178:39|Found 14 by 14 bit equality operator ('==') un6_adc_sample_divider (in view: work.FleaFPGA_DSO(behavior)) @N: MF179 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":295:9:295:42|Found 10 by 10 bit equality operator ('==') un19_vga_disp_en (in view: work.FleaFPGA_DSO(behavior)) @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":263:2:263:3|Removing sequential instance grid_column[0] (in view: work.FleaFPGA_DSO(behavior)) because it does not drive other instances. @W: BN132 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\tdms_encoder.vhd":76:6:76:7|Removing instance u100.u22.encoded[3] because it is equivalent to instance u100.u22.encoded[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\tdms_encoder.vhd":76:6:76:7|Removing instance u100.u22.encoded[9] because it is equivalent to instance u100.u22.encoded[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\tdms_encoder.vhd":76:6:76:7|Removing instance u100.u23.encoded[3] because it is equivalent to instance u100.u23.encoded[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\tdms_encoder.vhd":76:6:76:7|Removing instance u100.u23.encoded[1] because it is equivalent to instance u100.u23.encoded[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 144MB peak: 146MB) @W: BN132 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\dvi_d.vhd":101:6:101:7|Removing instance u100.latched_red[3] because it is equivalent to instance u100.latched_red[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\dvi_d.vhd":101:6:101:7|Removing instance u100.latched_red[9] because it is equivalent to instance u100.latched_red[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\dvi_d.vhd":43:101:43:101|Removing instance u100.latched_green[3] because it is equivalent to instance u100.latched_green[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\dvi_d.vhd":43:101:43:101|Removing instance u100.latched_green[9] because it is equivalent to instance u100.latched_green[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W: BN132 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\dvi_d.vhd":43:101:43:101|Removing instance u100.latched_blue[3] because it is equivalent to instance u100.latched_blue[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 149MB) @N: MF578 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":222:2:222:3|Incompatible asynchronous control logic preventing generated clock conversion of user_module1.sample_button_count[3] (in view: work.FleaFPGA_Ohm_A5(arch)). Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 149MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 149MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 153MB peak: 156MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 162MB peak: 163MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 162MB peak: 163MB) @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":263:2:263:3|Removing sequential instance user_module1.vga_trigger_scaled[0] (in view: work.FleaFPGA_Ohm_A5(arch)) because it does not drive other instances. @N: BN362 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":263:2:263:3|Removing sequential instance user_module1.vga_bufout_scaled[0] (in view: work.FleaFPGA_Ohm_A5(arch)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 158MB peak: 163MB) Finished technology mapping (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 158MB peak: 163MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:07s -1.57ns 385 / 321 2 0h:00m:07s -1.57ns 368 / 322 3 0h:00m:07s -1.57ns 368 / 322 4 0h:00m:07s -1.57ns 368 / 322 5 0h:00m:07s -1.57ns 368 / 322 6 0h:00m:07s -1.57ns 368 / 322 7 0h:00m:09s -2.24ns 393 / 368 8 0h:00m:09s -2.24ns 409 / 368 9 0h:00m:09s -2.24ns 416 / 368 10 0h:00m:09s -2.24ns 420 / 368 11 0h:00m:09s -2.24ns 421 / 368 12 0h:00m:10s -2.24ns 410 / 368 13 0h:00m:10s -2.24ns 410 / 368 14 0h:00m:10s -2.24ns 409 / 368 15 0h:00m:10s -2.24ns 409 / 368 16 0h:00m:10s -2.24ns 409 / 368 @N: MF322 |Retiming summary: 18 registers retimed to 67 ##### BEGIN RETIMING REPORT ##### Retiming summary : 18 registers retimed to 67 Original and Pipelined registers replaced by retiming : myuart.txcounter[0] myuart.txcounter[1] myuart.txcounter[2] myuart.txcounter[3] myuart.txcounter[4] myuart.txcounter[5] myuart.txcounter[6] myuart.txcounter[7] myuart.txcounter[8] myuart.txcounter[9] myuart.txcounter[10] myuart.txcounter[11] myuart.txcounter[12] myuart.txcounter[13] myuart.txcounter[14] myuart.txcounter[15] myuart.txstate[0] myuart.txstate[1] New registers created by retiming : myuart.txcounter_ret myuart.txcounter_ret[0] myuart.txcounter_ret_0 myuart.txcounter_ret_1 myuart.txcounter_ret_2 myuart.txcounter_ret_3 myuart.txcounter_ret_4 myuart.txcounter_ret_5 myuart.txcounter_ret_6 myuart.txcounter_ret_7 myuart.txcounter_ret_8 myuart.txcounter_ret_9 myuart.txcounter_ret_10 myuart.txcounter_ret_11 myuart.txcounter_ret_12 myuart.txcounter_ret_13 myuart.txcounter_ret_14 myuart.txcounter_ret_15 myuart.txcounter_ret_16 myuart.txcounter_ret_17 myuart.txcounter_ret_18 myuart.txcounter_ret_19 myuart.txcounter_ret_20 myuart.txcounter_ret_21 myuart.txcounter_ret_22 myuart.txcounter_ret_23 myuart.txcounter_ret_24 myuart.txcounter_ret_25 myuart.txcounter_ret_26 myuart.txcounter_ret_27 myuart.txcounter_ret_28 myuart.txcounter_ret_30 myuart.txcounter_ret_31 myuart.txcounter_ret_32 myuart.txcounter_ret_33 myuart.txcounter_ret_34 myuart.txcounter_ret_35 myuart.txcounter_ret_36 myuart.txcounter_ret_37 myuart.txcounter_ret_38 myuart.txcounter_ret_39 myuart.txcounter_ret_40 myuart.txcounter_ret_41 myuart.txcounter_ret_42 myuart.txcounter_ret_43 myuart.txcounter_ret_44 myuart.txcounter_ret_45 myuart.txcounter_ret_46 myuart.txcounter_ret_47 myuart.txcounter_ret_48 myuart.txcounter_ret_49 myuart.txcounter_ret_50 myuart.txcounter_ret_51 myuart.txcounter_ret_52 myuart.txcounter_ret_53 myuart.txcounter_ret_54 myuart.txcounter_ret_55 myuart.txcounter_ret_56 myuart.txcounter_ret_57 myuart.txcounter_ret_58 myuart.txcounter_ret_59 myuart.txcounter_ret_60 myuart.txcounter_ret_61 myuart.txstate_ret myuart.txstate_ret_0 myuart.txstate_ret_1 myuart.txstate_ret_2 ##### END RETIMING REPORT ##### Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 166MB peak: 167MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Boundary register myuart.txbuffer_16_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Boundary register myuart.txbuffer_15_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Boundary register myuart.txbuffer_14_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Boundary register myuart.txbuffer_13_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Boundary register myuart.txbuffer_12_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Boundary register myuart.txbuffer_11_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Boundary register myuart.txbuffer_10_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Boundary register myuart.txbuffer_9_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Boundary register myuart.txbuffer_8_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\simple_uart.vhd":185:2:185:3|Boundary register myuart.txbuffer_7_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":74:45:74:50|Boundary register user_module1.trig_row_8_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":74:45:74:50|Boundary register user_module1.trig_row_7_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":74:45:74:50|Boundary register user_module1.trig_row_6_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":74:45:74:50|Boundary register user_module1.trig_row_5_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":74:45:74:50|Boundary register user_module1.trig_row_4_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":74:45:74:50|Boundary register user_module1.trig_row_3_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":74:45:74:50|Boundary register user_module1.trig_row_2_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"c:\lscc\diamond\3.9_x64\examples\fleadso\source\fleafpga_dso.vhd":74:45:74:50|Boundary register user_module1.trig_row_1_.fb (in view: work.FleaFPGA_Ohm_A5(arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. Finished restoring hierarchy (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 167MB peak: 168MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 6 gated/generated clock tree(s) driving 370 clock pin(s) of sequential element(s) 0 instances converted, 370 sequential instances remain driven by gated/generated clocks =============================================================================================================== Gated/Generated Clocks ================================================================================================================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- @K:CKID0001 user_module1.U1.PLLInst_0 EHXPLLL 100 user_module1.Green_out_1[0] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements @K:CKID0002 u0.PLLInst_0 EHXPLLL 87 myuart.txbuffer[17] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements @K:CKID0003 u0.PLLInst_0 EHXPLLL 48 u100.latched_blue[9] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements @K:CKID0004 user_module1.U1.PLLInst_0 EHXPLLL 45 user_module1.ADC_lowspeed_raw_1[6] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements @K:CKID0005 u0.PLLInst_0 EHXPLLL 40 u100.shift_blue[9] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements @K:CKID0006 user_module1.U2.v_sync FD1S3BX 50 user_module1.ADC_filter_shift Need declared clock or clock from port to derive clock from ff ======================================================================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 131MB peak: 168MB) Writing Analyst data base C:\lscc\diamond\3.9_x64\examples\FleaDSO\FleaDSO\synwork\FleaDSO_FleaDSO_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 163MB peak: 168MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: C:\lscc\diamond\3.9_x64\examples\FleaDSO\FleaDSO\FleaDSO_FleaDSO.edi L-2016.09L-1 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 167MB peak: 169MB) Start final timing analysis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 165MB peak: 169MB) @W: MT246 :"c:\lscc\diamond\3.9_x64\examples\fleadso\ddr_out\ddr_out.vhd":42:4:42:17|Blackbox ODDRX1F is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\lscc\diamond\3.9_x64\examples\fleadso\dvi_clkgen\dvi_clkgen.vhd":59:4:59:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT420 |Found inferred clock DVI_clkgen|CLKOP_inferred_clock with period 2.22ns. Please declare a user-defined clock on object "n:u0.CLKOP" @W: MT420 |Found inferred clock DVI_clkgen|CLKOS2_inferred_clock with period 3.35ns. Please declare a user-defined clock on object "n:u0.CLKOS2" @W: MT420 |Found inferred clock DVI_clkgen|CLKOS3_inferred_clock with period 3.33ns. Please declare a user-defined clock on object "n:u0.CLKOS3" @N: MT615 |Found clock vga_controller|v_sync_derived_clock with period 1000.00ns @W: MT420 |Found inferred clock ADC_PLL|CLKOS_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:user_module1.U1.CLKOS" @W: MT420 |Found inferred clock ADC_PLL|CLKOP_inferred_clock with period 4.53ns. Please declare a user-defined clock on object "n:user_module1.U1.CLKOP" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Oct 03 00:10:31 2018 # Top view: FleaFPGA_Ohm_A5 Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.800 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ADC_PLL|CLKOP_inferred_clock 220.6 MHz 187.5 MHz 4.532 5.332 -0.800 inferred Autoconstr_clkgroup_3 ADC_PLL|CLKOS_inferred_clock 1.0 MHz 42.8 MHz 1000.000 23.340 976.660 inferred Autoconstr_clkgroup_4 DVI_clkgen|CLKOP_inferred_clock 450.6 MHz 383.0 MHz 2.219 2.611 -0.392 inferred Autoconstr_clkgroup_2 DVI_clkgen|CLKOS2_inferred_clock 298.4 MHz 253.6 MHz 3.352 3.943 -0.591 inferred Autoconstr_clkgroup_1 DVI_clkgen|CLKOS3_inferred_clock 300.0 MHz 255.0 MHz 3.333 3.921 -0.588 inferred Autoconstr_clkgroup_0 vga_controller|v_sync_derived_clock 1.0 MHz 45.8 MHz 1000.000 21.817 978.183 derived (from ADC_PLL|CLKOS_inferred_clock) Autoconstr_clkgroup_4 System 1.0 MHz NA 1000.000 NA NA system system_clkgroup ================================================================================================================================================================================= @N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------- DVI_clkgen|CLKOS3_inferred_clock DVI_clkgen|CLKOS3_inferred_clock | 3.333 -0.588 | No paths - | No paths - | No paths - DVI_clkgen|CLKOS2_inferred_clock DVI_clkgen|CLKOS2_inferred_clock | 3.352 -0.591 | No paths - | No paths - | No paths - DVI_clkgen|CLKOS2_inferred_clock DVI_clkgen|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | No paths - DVI_clkgen|CLKOP_inferred_clock System | 2.219 1.111 | No paths - | No paths - | No paths - DVI_clkgen|CLKOP_inferred_clock DVI_clkgen|CLKOP_inferred_clock | 2.219 -0.392 | No paths - | No paths - | No paths - ADC_PLL|CLKOP_inferred_clock DVI_clkgen|CLKOS3_inferred_clock | Diff grp - | No paths - | No paths - | No paths - ADC_PLL|CLKOP_inferred_clock ADC_PLL|CLKOP_inferred_clock | 4.532 -0.800 | No paths - | No paths - | No paths - ADC_PLL|CLKOS_inferred_clock DVI_clkgen|CLKOS2_inferred_clock | Diff grp - | No paths - | No paths - | No paths - ADC_PLL|CLKOS_inferred_clock ADC_PLL|CLKOS_inferred_clock | 1000.000 976.661 | No paths - | No paths - | No paths - vga_controller|v_sync_derived_clock ADC_PLL|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | No paths - vga_controller|v_sync_derived_clock ADC_PLL|CLKOS_inferred_clock | 1000.000 978.183 | No paths - | No paths - | No paths - vga_controller|v_sync_derived_clock vga_controller|v_sync_derived_clock | 1000.000 1996.729 | No paths - | No paths - | No paths - =================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.  At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 37MB peak: 169MB) Process took 0h:00m:13s realtime, 0h:00m:12s cputime # Wed Oct 03 00:10:31 2018 ###########################################################]


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Every month we'll discuss AI, Machine Learning, Deep Learning, Data Science, and any other topics in the realm of AI that seems interesting.
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@@include('../start.html') Work ONESHOP A men's online fashion accessory shop specializing in modern urban wear Roles Customized theme layout Customized cart plugins Added lightbox for products Simplified checkout process Built custom landing pages Integrated analytics tools Tools @@include('../end.html')
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This tool ease the installation and the use of ROS middleware. First of all, we need to install PhaROS-Tool, then we can use it to ease the configuration of our own nodes.
You can download PhaROS-Tool with:
Once downloaded just execute the following lines to install it and update it.
Executing the following line validate the correct installation and will give you an help.
The result is:
Each of these commands will be explained in this document.
The following example line will install the desktop-full of the hydro version of ROS:
You can install the version of ROS you want. This process works only on Ubuntu. The possible options are available executing this line:
They are:
-version : you define the version of ROS (fuerte | groovy | hydro). By default it is groovy.
-type-installation : you can define the type of ros installation (desktop | desktop-full | ros-base). By default, it is desktop.
-configure : It indicates if the installation should be configured. It modifies the .bashrc file. The value can be true or false. By default, it is true.
-create-workspace : it indicates if a workspace should be created. It will create a workspace at ~/ros/worskpace. The value can be true or false. By default, it is true.
The repositories listed are the places where your projects are saved. By default there are two repositories: the first one is the main repository of PhaROS, the second is the material for peripherics we already plugged on PhaROS. For example, there is a package for the turtlebot in this repository.
You can list repositories with the folowing command:
By default, it will give you the two following repositories, and attached information.
This command allows one to add one new repository. To use the ev3 ROS package, you have to register the following repository:
The package EV3ROSDirectory contains all the metadata needed to build a ROS package. It is explained after in the chapter.
Tip: If your repository requires user/password for reading add user=User password=Password to the example.
Pay attention that the User/Password will be stored in a text file without any security.
After adding the new repository, you can verify it is included it is available in the list of repository:
Yes, it is !
Adding a repository would need some options. Here are the available options to register a repository:
After having added the ev3 repository, as explained in the previous section, you can install the package Ev3 for ROS. This package is named ev3. The command should be run in the ros workspace. By default, the ROS workspace is in emph{{textasciitilde}/ros/workspace/}.
The previous line search the ev3 package in the available repositories. When it found it, it install it in a new pharo image. Here, we are using the version 3.0 of Pharo. It is configured for ROS Hydro, the version of ROS that I previously installed. I also configure the user name in the Pharo image. All the source code that I produce with this image will have as author the name JLaval. Finally, I force a new installation. It means that if the package already exists, it will be replaced and all the changes will be lost.
The usage of this command can be completed with the following options:
-location : You can give the absolute path to a valid catkin workspace (not the source folder). The default value is the current directory.
-silent : The values can be true or false. If silent is false you will be able to see the installation of the output image. The default value is true.
-version : It indicates the version of Pharo to download. The default value is 2.0. It can be 1.4, 2.0 or 3.0.
-ros-distro : It indicates the distribution of ROS that you want to use. By default it is groovy, but you can configure it with groovy, hydro or fuerte.
-package : It indicates the name of the package to install (If you use <<pharos install aPackage package=otherPackage>> the one to be installed is otherPackage).
-package-version : It indicates the package version. By default it takes the latest one.
-pharo-user : It indicates the user name for the result image.
-force-new : It DELETES the package if it exists in the pointed location.
!!Run PhaROS software
To edit the source code, just run the following line. It will open the Pharo image used for your package.
For example, you can browse the method EV3ROSPackage>>scriptPublishColour in PhaROS. It is the script to run a ROS node that publishes the color sensor data.
Each scripts in PhaROS has the signature format like emph{scriptWord1Word2}. It begins with emph{script} followed by the words of the method.
Each script when compiled generates a .sh script. Like that, when you need to execute your script without touching the source code, you don't need to open PhaROS. You can access to the scripts generated by executing the following lines:
The first line change the directory to the package ev3. The second line lists the available scripts. When writting these lines, there are 3 available scripts:
The first script make the robot move meanwhile it detects an obstacle. The second provide a publisher for the color sensor. The third script publish the sonar data.
As expected we find the script that publish the color sensor data. The name given to the script is related to the format of the name given inside PhaROS. A method signature like emph{scriptWord1Word2} become emph{word1_word2.st}.
Now, you can run the scripts without seeing PhaROS environment as following:
or run the script with the environment:
!!Create your ROS package
There are three steps to create your packages: first, you will create your PhaROS package, that contains your source code. Then, you will create a configuration that gives PhaROS the possibility to load your source code. Finally, you will create a method that contains the ROS Package information.
!!!Create your package : pharos create
To create a Pharo image for developing your own software, you would use the command ¿?. In the following line, I am creating a phaROS configuration for the package ¿?.
[[[language=bash
$ cd ~/ros/workspace/
$ pharos create my_super_ros_package version=3.0 ros-distro=hydro author=JLaval<EMAIL_ADDRESS>]]]
Pay attention that your package name follows the naming conventions. It should start with a lower case letter and only contain lower case letters, digits and underscores.
The usage of this command can be completed with the following options:
-help : It shows this text
-location : You can give the absolute path to a valid catkin workspace (not the source folder). The default value is the current directory.
-silent : The values can be true or false. If silent is false you will be able to see the installation of the output image. The default value is true.
-version : It indicates the version of Pharo to download. The default value is 2.0. It can be 1.4, 2.0 or 3.0.
-ros-distro : It indicates the distribution of ROS that you want to use. By default it is groovy, but you can configure it with groovy, hydro or fuerte.
-archetype : It indicates the name of the archetype to use for creating things. By default, it is basic-archetype.
-author : It indicates the name of the author.
-maintainer : It indicates the name of the maintainer. The default value is the one indicated in author.
-author-email : It indicates the email of the author.
-maintainer-email : It indicates the email of the maintainer. The default value is the one indicated in author-email.
-description : It indicates the description of the package.
-pharo-user : It indicates the user name for the result image.
-force-new : It DELETES the package if it exists in the pointed location.
Inside PhaROS environment, one package, emph{My_super_ros_packagePackage} was created with 2 classes inside: emph{My_super_ros_packagePackage} and emph{My_super_ros_packageNodelets}. Inside the class emph{My_super_ros_packagePackage}, you will find some example methods.
Create the ConfigurationOf inside PhaROS, in a package ConfigurationOfMySuperRosPackage. To create a configuration in PhaROS, yo can find more documentation in the free book ``Deep into Pharo'' available on url{http://www.deepintopharo.com/}. For example, for the ev3 package, I created this class: [[[language=Smalltalk Object subclass: #ConfigurationOfEv3ROS instanceVariableNames: 'project' classVariableNames: 'LastVersionLoad' category: 'ConfigurationOfEv3ROS' ]]] This class contains the method emph{baseline10:}, which load my source code. [[[language=Smalltalk ConfigurationOfEv3ROS>>baseline10: spec <version:'1.0-baseline'> spec for: #common do: [ spec blessing: #baseline. spec repository: 'http://smalltalkhub.com/mc/JLaval/Ev3ROS/main'. spec project: 'JetStorm' with: [ spec className: 'ConfigurationOfJetStorm'; file: 'ConfigurationOfJetStorm' ; version: #bleedingEdge; repository: 'http://smalltalkhub.com/mc/JLaval/JetStorm/main'. ]. spec project: 'PhaROS' with: [ spec className: 'ConfigurationOfPhaROS'; file: 'ConfigurationOfPhaROS' ; version: #bleedingEdge; repository: 'http://car.mines-douai.fr/squeaksource/PhaROS'. ]. spec package: 'EV3ROSPackage' with: [ spec requires: #('JetStorm' 'PhaROS') ]. ]. ]]] !!!Create the ROS metadata: pharos create-repository Creating a directory for your own project repository needs a st file. Then, you have to load it in a pharo image and personalize it. For example, I used the following command line to create my file for Ev3. [[[language=bash $ pharos create-repository EV3ROS --user=JLaval > eve.st ]]] Then, I just file in the file.st in PhaROS. It will create a package EV3ROSDirectory that contains the meta data. You can do it for My_super_ros_package: [[[language=bash $ pharos create-repository My_super_ros_package --user=JLaval > myROS.st ]]] It will create a package My_super_ros_packageDirectory that contains the meta data. This command can have two options: ---user : gives the name of the user for generation by default is 'Generated' ---output path to where the script will be dumped. By default is the standar output. When the file is integrated in PhaROS, you can see the methods emph{EV3ROSDirectory class>>archetypeEv3} and emph{EV3ROSDirectory class>>ev3RosPackage}, respectively emph{My_super_ros_packageDirectory class>>archetypeExample} and emph{My_super_ros_packageDirectory class>>exampleMetacelloPackage} for My_super_ros_package. There are other files that are not necessary here. You can browse and discover them. [[[language=Smalltalk EV3ROSDirectory class>>archetypeEv3 ^ { #archetype -> 'EV3ROS-archetype' . #description -> 'Minimum dependancies for using EV3+ROS' . #license -> 'MIT' . #version -> '0.1.0' . #maintainer -> ({ #name-> 'JLaval' . #email -><EMAIL_ADDRESS>} asDictionary) . #author -> ({ #name-> 'JLaval' . #email -><EMAIL_ADDRESS>} asDictionary) . #metacello -> ({ #url -> 'http://smalltalkhub.com/mc/JLaval/ev3ros/main' . #configurationOf -> 'ConfigurationOfEv3ROS' . #package -> 'EV3ROSArchetype' } asDictionary) } asDictionary ]]] [[[language=Smalltalk EV3ROSDirectory class>>ev3RosPackage ^ { #name -> 'ev3' . #description -> 'ROS package for managing Ev3' . #license -> 'MIT' . #version -> '0.1.0' . #maintainer -> ({ #name-> 'JLaval' . #email -><EMAIL_ADDRESS>} asDictionary) . #author -> ({ #name-> 'JLaval' . #email -><EMAIL_ADDRESS>} asDictionary) . #metacello -> ({ #url -> 'http://smalltalkhub.com/mc/JLaval/Ev3ROS/main' . #configurationOf -> 'ConfigurationOfEv3ROS' . #package -> 'EV3ROSPackage' } asDictionary) } asDictionary ]]] As you can see, each method represents the metadata used for the publication in ROS. You can use and complete your data for your own PhaROS package. Finally, do not forget to change the method emph{EV3ROSDirectory class>>deployUnitsMetadata} to call the correct configuration method. [[[language=Smalltalk EV3ROSDirectory class>>deployUnitsMetadata ^ { self archetypeEv3 . self ev3RosPackage. } ]]] !!Create your ROS node source code Last but not least, we can create the behavior in the PhaROS environment. In this section, I present the source code used by the three nodes: the first node publish the sonar sensor data, the second publish the colour sensor data, the third one subscribe to the sonar publisher and move until the data is lower than 10 centimeters. First, I initialise the node with a connection to the robot. [[[language=Smalltalk EV3ROSPackage>>initialize super initialize. ev3 := Ev3Vehicle newIp: '<IP_ADDRESS>' daisyChain: #EV3. ]]] Then, following there are the two scripts used to publish sensor data. [[[language=Smalltalk EV3ROSPackage>>scriptPublishColour | colourSensor colourPublisher | colourSensor := ev3 sensor3. colourPublisher := self node topicPublisher: '/ev3/colour' typedAs: 'std_msgs/Int32'. self paralellize looping publish: colourSensor at: colourPublisher. ]]] [[[language=Smalltalk EV3ROSPackage>>scriptPublishSonar | sonarSensor sonarPublisher | sonarSensor := ev3 sensor4. sonarPublisher := self node topicPublisher: '/ev3/sonar' typedAs: 'std_msgs/Float32'. self paralellize looping publish: sonarSensor at: sonarPublisher . ]]] The usefull method used in the two previous method: [[[language=Smalltalk EV3ROSPackage>>publish: aSensor at: aPublisher. aPublisher send: [ : m | m data: aSensor read. ]. 0.5 hz wait. ]]] The following methods allow the robot to move and to stop. [[[language=Smalltalk EV3ROSPackage>>letEv3Move ev3 motorB isRunning ifFalse: [ ev3 motorB startAtSpeed: 30 ]. ev3 motorC isRunning ifFalse: [ ev3 motorC startAtSpeed: 30 ]. ]]] [[[language=Smalltalk EV3ROSPackage>>stopEv3 ev3 motorB stop. ev3 motorC stop. ]]] Then this is the script that allows the robot to subscribe to the sonar sensor and move. [[[language=Smalltalk EV3ROSPackage>>scriptMoveMeanwhileYouCan (self node buildConnectionFor: '/ev3/sonar') typedAs: 'std_msgs/Float32'; for: [ : m | (m data < 10) ifTrue: [ self stopEv3. ] ifFalse: [ self letEv3Move ]]; connect. ]]] Here is the end of this tutorial.


Package com.jme.util.mikktspace
Interface MikkTSpaceContext
-
- All Known Implementing Classes:
MikkTSpaceImpl
public interface MikkTSpaceContext
- Author:
- Nehon
-
-
Method Summary
All Methods Instance Methods Abstract Methods Modifier and Type Method Description void
getNormal(float[] normOut, int face, int vert)
int
getNumFaces()
Returns the number of faces (triangles/quads) on the mesh to be processed.int
getNumVerticesOfFace(int face)
Returns the number of vertices on face number iFace iFace is a number in the range {0, 1, ..., getNumFaces()-1}void
getPosition(float[] posOut, int face, int vert)
returns the position/normal/texcoord of the referenced face of vertex number iVert.void
getTexCoord(float[] texOut, int face, int vert)
void
setTSpace(float[] tangent, float[] biTangent, float magS, float magT, boolean isOrientationPreserving, int face, int vert)
This function is used to return tangent space results to the application.void
setTSpaceBasic(float[] tangent, float sign, int face, int vert)
The call-backsetTSpaceBasic() is sufficient for basic normal mapping.
-
-
-
Method Detail
-
getNumFaces
int getNumFaces()
Returns the number of faces (triangles/quads) on the mesh to be processed.- Returns:
- the count (≥0)
-
getNumVerticesOfFace
int getNumVerticesOfFace(int face)
Returns the number of vertices on face number iFace iFace is a number in the range {0, 1, ..., getNumFaces()-1}- Parameters:
face
-- Returns:
- the count (≥0)
-
getPosition
void getPosition(float[] posOut, int face, int vert)
returns the position/normal/texcoord of the referenced face of vertex number iVert. iVert is in the range {0,1,2} for triangles and {0,1,2,3} for quads.- Parameters:
posOut
-face
-vert
-
-
getNormal
void getNormal(float[] normOut, int face, int vert)
-
getTexCoord
void getTexCoord(float[] texOut, int face, int vert)
-
setTSpaceBasic
void setTSpaceBasic(float[] tangent, float sign, int face, int vert)
The call-backsetTSpaceBasic() is sufficient for basic normal mapping. This function is used to return the tangent and sign to the application. tangent is a unit length vector. For normal maps it is sufficient to use the following simplified version of the bitangent which is generated at pixel/vertex level. bitangent = fSign * cross(vN, tangent); Note that the results are returned unindexed. It is possible to generate a new index list But averaging/overwriting tangent spaces by using an already existing index list WILL produce INCRORRECT results. DO NOT! use an already existing index list.- Parameters:
tangent
-sign
-face
-vert
-
-
setTSpace
void setTSpace(float[] tangent, float[] biTangent, float magS, float magT, boolean isOrientationPreserving, int face, int vert)
This function is used to return tangent space results to the application. tangent and biTangent are unit length vectors and fMagS and fMagT are their true magnitudes which can be used for relief mapping effects. biTangent is the "real" bitangent and thus may not be perpendicular to tangent. However, both are perpendicular to the vertex normal. For normal maps it is sufficient to use the following simplified version of the bitangent which is generated at pixel/vertex level.fSign = bIsOrientationPreserving ? 1.0f : (-1.0f); bitangent = fSign * cross(vN, tangent);
Note that the results are returned unindexed. It is possible to generate a new index list. But averaging/overwriting tangent spaces by using an already existing index list WILL produce INCRORRECT results. DO NOT! use an already existing index list.- Parameters:
tangent
-biTangent
-magS
-magT
-isOrientationPreserving
-face
-vert
-
-
-


Hello. My name is Joe. I am a Colorado based jr. designer, web developer, life long learner, and ready for new opportunities. A bit about me. I love coffee, peanut butter, welding, and spending time with my family.
I believe in user centered design and delevering the best possible experiences to people. I have experience with HTML, CSS, Bootstrap, Flexbox, Javascript, jQuery, Ruby and Rails, Git, Github, Figma, and Photoshop.
I have great communication skills, worked on many teams of different sizes, willing to learn, can teach, train and overall bring a diverse skill set to the table. Currently, I am looking to join a new team of like minded folks. So feel free to reach out and let’s connect.
Let's Talk


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[gecode-users] Using GecodeJ with Eclipse
Guido Tack
tack at ps.uni-sb.de
Thu Apr 5 17:37:24 CEST 2007
Luis Quesada wrote:
> In order to set java.library.path, I did the following:
>
> I went to Run-> Run...-> Java Applicaton-> New ->Arguments -> VM
> Arguments. I pasted "-Djava.library.path=/usr/local/lib/" to the
> VM Arguments field.
That seems to be the way to do it.
> However, I am now getting the following problem:
>
> Gecode native code library failed to load.
> java.lang.UnsatisfiedLinkError: /usr/local/lib/libgecodej.so.1.0:
> libgecodeint.so.8: cannot open shared object file: No such file or
> directory
It means that the Gecode libraries are not on the LD_LIBRARY_PATH.
Check where they are installed, and that that path is either in /etc/
ld.so.conf (like /usr/lib) or in the LD_LIBRARY_PATH environment
variable.
Cheers,
Guido
--
Guido Tack
Programming Systems Lab, Saarland University, Germany
http://www.ps.uni-sb.de/~tack
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I am a Web Developer eager to learn something new every day and particularly enjoy coding challenges.
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The rugby evening headlines as Wales' 60-cap rule debated again while another Rugby World Cup winner bows out
Some wanted a 75-cap rule
by Mark OrdersHere are your evening headlines for Thursday, November 14.
Gatland says Wales rule on exiles should be cut to 30 caps
Warren Gatland believes exiled Wales players who have 30 or more caps should be allowed to play for their country.
Such a move would make Toulon's Rhys Webb, who has 31 caps, available for national duties once again.
In 2017, the Welsh Rugby Union scrapped the old ‘Gatland’s Law’ selection policy and introduced a new rule affecting players taking contracts outside Wales. The big change was that exiled players needed to have 60 or more caps to be eligible to pull on the red jersey.
But former Wales coach Gatland says he always felt the limit was set too high, and that it should have been cut back to 30 caps.
"I still felt desperately that Rhys Webb, every inch a scrum-half of international calibre, has fallen victim to our 60-cap rule which states that for people playing their rugby outside Wales, only those with that number of Test appearances or more can be picked for their country", the 56-year-old writes in his new autobiography, Pride and Passion.
"Rhys had already agreed to join Toulon when the rule was introduced in 2017. He could have pulled out of the deal and remained available to Wales but to his credit he felt he had made a commitment to the French club and should honour it.
"I can't pretend I agree with the situation and I've made my feelings known, but as some influential figures in Welsh rugby originally wanted a 75-cap cut-off, it was never going to be an easy argument to win."
WRU chief executive Martyn Phillips reckons the existing policy has worked but indicated to WalesOnline in the summer that the union did intend to review the rule .
Sonny Bill is in the money
He has starred in NRL, Super Rugby, Japan and the Top 14 over the past decade and a half, so Sonny Bill Williams could have been forgiven for quietly playing out the remainder of his career.
But the All Black is up for one final challenge, for he has joined Toronto Wolfpack RLF to complete in Super League.
He will earn a reputed £2.6 million a year over two seasons to become the highest-paid player in either rugby code.
“As a man of faith, I just really believe this is meant to be. My wife is probably a bit upset that she is going to have to move all four kids over here but after talking with her I am really excited. It all came to fruition really quickly,” said Williams.
“I am a sportsman but I need to have a purpose and something I believe in. After speaking to Brian [McDermott, Toronto coach] his philosophy on how he wants to play the game – I can be really suited to his style.
“It’s a journey — there’s a bit of pressure there but it’s so exciting. What they are trying to achieve on and off the field is special. What if we succeed and what if I am a part of that?”
Goodbye, Schalk
South Africa hooker Schalk Brits has announced his retirement from rugby — again.
The talented No. 2 first declared his intention to bow out in May 2018 after departing Saracens, only to be coaxed back by Springboks coach Rassie Erasmus.
But this time the 38-year-old can see the finish line.
"To say Schalk is a team player would be underestimating the massive role he played in our success, and for that I can only thank him," said Erasmus, who guided South Africa to World Cup final success over England.
It’s isn’t quite the end, mind.
He is set to figure for the Barbarians Brazil and against Wales this month and will try to appear for Cambridge in the 2020 varsity match against Oxford.
Departing Fiji boss predicts bright future for the islanders
Fiji general manager Geoff Webster is departing the role with high hopes that the islanders can go from strength to strength.
Despite producing some spectacular rugby, Semi Radradra, Leone Nakarawa and Co exited the World Cup at the pool stage yet again.

“The foundations for sustained performance are now in place,” he insisted.
“I expect a good number of young prospects to kick on and make their mark.
“A vibrant, professional Fiji can only enhance the code globally.”

Young regional player earns big praise
Ospreys youngster Morgan Morris has wasted no time making a mark in senior rugby, with plaudits coming in for his efforts this season.
Both Dan Lydiate and the region’s head coach Allen Clarke named-checked the 21-year-old at the media’s press conference this week and his former director of rugby at Swansea, Richard Lancaster, added his name to the list of endorsements.
“I don’t think it’s in doubt he’ll prove a very good player for the Ospreys,” said Lancaster.
“It’s then a question of how far he can go from there.
“That’s up to him, then.
“But in terms of attitude, he’s first class.”


Objective
In this challenge, we practice calculating standard deviation.
Task
Find the largest possible value of $N$ where the standard deviation of the values in the set {$1,2,3,N$} is equal to the standard deviation of the values in the set {$1,2,3$}.
Output the value of $N$, correct to two decimal places.
Output Format
Your output must be a floating point/decimal number, correct to a scale of $2$ decimal places. You can submit solutions in either of the $2$ following ways:
Solve the problem manually and submit your result as Plain Text.
Submit an R or Python program, which uses the above parameters (hard-coded), and computes the answer.
Your answer format should resemble something like:
4.23
(This is NOT the answer, just a demonstration of the answering format.)


The Department of Technology Promotion and Coordination
University of Computer Studies
Second Year (B.C.Teach)
Final Examination
SE+ SAD(CST-206)
September, 2016
Zone III
- Create an html page with following by using the DOM.
- Place the following CSS rules.
.r1{width:200px;
height:50px;
background-color:#bb88ff;
}
.r2{widht:20px;
height:50px;
background-color:#bbff88;}
- Creae a heading "Free to Air TV Channels" with heading style 3 and append to the document body.
- Write JavaScript statement for following table by using DOM. All odd rows apply the first CSS rule and all even rows apply the second CSS rules.


@* * Copyright 2023 HM Revenue & Customs * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. *@ @import config.ApplicationConfig @import views.html.view_application.helpers._ @import views.view_application.ViewApplicationHelper._ @import views.view_application.helpers.ViewApplicationType @(supplier: models.Supplier, id: Int)(implicit viewApplicationType: ViewApplicationType, messages: Messages, applicationConfig: ApplicationConfig) @editUrl(id: Int) = @{controllers.routes.SupplierAddressesController.showSupplierAddressesPage(id, isLinearMode = false, isNewRecord = false).url} @deleteUrl(id: Int) = @{controllers.routes.SupplierAddressesController.showDelete(id).url} @tableRowTitle = @{supplier.supplierName.fold("")(x => x)} @content = {