-------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) <IP_ADDRESS> Sun Jan 4 07:39:14 2015 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: AutoShift Device,speed: LCMXO2-7000HE,5 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Derating parameters ------------------- Temperature: 85 C Voltage: 1.200 V ================================================================================ Preference: FREQUENCY NET "osc_clk_c_c" 2.080000 MHz ; 55 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 478.066ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 2.569ns (79.8% logic, 20.2% route), 7 logic levels. Constraint Details: 2.569ns physical path delay SLICE_0 to SLICE_2 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.066ns Physical Path Details: Data path SLICE_0 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.518 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.703 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.130 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.130 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.462 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 2.569 (79.8% logic, 20.2% route), 7 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.090ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 2.545ns (79.6% logic, 20.4% route), 6 logic levels. Constraint Details: 2.545ns physical path delay SLICE_3 to SLICE_2 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.090ns Physical Path Details: Data path SLICE_3 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.809 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.130 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.462 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 2.545 (79.6% logic, 20.4% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.149ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 2.486ns (79.2% logic, 20.8% route), 6 logic levels. Constraint Details: 2.486ns physical path delay SLICE_0 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.149ns Physical Path Details: Data path SLICE_0 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.518 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.703 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.130 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.509 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 2.486 (79.2% logic, 20.8% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.173ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 2.462ns (79.0% logic, 21.0% route), 5 logic levels. Constraint Details: 2.462ns physical path delay SLICE_3 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.173ns Physical Path Details: Data path SLICE_3 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.809 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.509 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 2.462 (79.0% logic, 21.0% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.196ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 2.439ns (78.8% logic, 21.2% route), 6 logic levels. Constraint Details: 2.439ns physical path delay SLICE_0 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.196ns Physical Path Details: Data path SLICE_0 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.518 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.703 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.130 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.462 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 2.439 (78.8% logic, 21.2% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.196ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 2.439ns (78.8% logic, 21.2% route), 6 logic levels. Constraint Details: 2.439ns physical path delay SLICE_3 to SLICE_2 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.196ns Physical Path Details: Data path SLICE_3 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.703 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.130 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.462 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 2.439 (78.8% logic, 21.2% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.220ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 2.415ns (78.6% logic, 21.4% route), 5 logic levels. Constraint Details: 2.415ns physical path delay SLICE_1 to SLICE_2 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.220ns Physical Path Details: Data path SLICE_1 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q0 to R4C9C.A0 n7 C0TOFCO_DE --- 0.809 R4C9C.A0 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.130 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.462 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 2.415 (78.6% logic, 21.4% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.220ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 2.415ns (78.6% logic, 21.4% route), 5 logic levels. Constraint Details: 2.415ns physical path delay SLICE_3 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.220ns Physical Path Details: Data path SLICE_3 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.809 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.462 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 2.415 (78.6% logic, 21.4% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.279ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 2.356ns (78.0% logic, 22.0% route), 5 logic levels. Constraint Details: 2.356ns physical path delay SLICE_0 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.279ns Physical Path Details: Data path SLICE_0 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.518 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.703 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.130 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF1_DE --- 0.509 R4C9D.FCI to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 2.356 (78.0% logic, 22.0% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.279ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 2.356ns (78.0% logic, 22.0% route), 5 logic levels. Constraint Details: 2.356ns physical path delay SLICE_3 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.279ns Physical Path Details: Data path SLICE_3 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.703 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.509 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 2.356 (78.0% logic, 22.0% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.303ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 2.332ns (77.8% logic, 22.2% route), 4 logic levels. Constraint Details: 2.332ns physical path delay SLICE_1 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.303ns Physical Path Details: Data path SLICE_1 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q0 to R4C9C.A0 n7 C0TOFCO_DE --- 0.809 R4C9C.A0 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.509 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 2.332 (77.8% logic, 22.2% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.303ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 2.332ns (77.8% logic, 22.2% route), 4 logic levels. Constraint Details: 2.332ns physical path delay SLICE_3 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.303ns Physical Path Details: Data path SLICE_3 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.809 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF1_DE --- 0.509 R4C9D.FCI to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 2.332 (77.8% logic, 22.2% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.326ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 2.309ns (77.6% logic, 22.4% route), 5 logic levels. Constraint Details: 2.309ns physical path delay SLICE_0 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.326ns Physical Path Details: Data path SLICE_0 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.518 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.703 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.130 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF0_DE --- 0.462 R4C9D.FCI to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 2.309 (77.6% logic, 22.4% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.326ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 2.309ns (77.6% logic, 22.4% route), 5 logic levels. Constraint Details: 2.309ns physical path delay SLICE_1 to SLICE_2 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.326ns Physical Path Details: Data path SLICE_1 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q1 to R4C9C.A1 n6 C1TOFCO_DE --- 0.703 R4C9C.A1 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.130 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.462 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 2.309 (77.6% logic, 22.4% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.326ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 2.309ns (77.6% logic, 22.4% route), 5 logic levels. Constraint Details: 2.309ns physical path delay SLICE_3 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.326ns Physical Path Details: Data path SLICE_3 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.703 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.462 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 2.309 (77.6% logic, 22.4% route), 5 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.350ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 2.285ns (77.3% logic, 22.7% route), 4 logic levels. Constraint Details: 2.285ns physical path delay SLICE_1 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.350ns Physical Path Details: Data path SLICE_1 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q0 to R4C9C.A0 n7 C0TOFCO_DE --- 0.809 R4C9C.A0 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.462 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 2.285 (77.3% logic, 22.7% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.350ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 2.285ns (77.3% logic, 22.7% route), 4 logic levels. Constraint Details: 2.285ns physical path delay SLICE_3 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.350ns Physical Path Details: Data path SLICE_3 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.809 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF0_DE --- 0.462 R4C9D.FCI to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 2.285 (77.3% logic, 22.7% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.350ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i5 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 2.285ns (77.3% logic, 22.7% route), 4 logic levels. Constraint Details: 2.285ns physical path delay SLICE_5 to SLICE_2 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.350ns Physical Path Details: Data path SLICE_5 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9D.CLK to R4C9D.Q0 SLICE_5 (from osc_clk_c_c) ROUTE 1 0.518 R4C9D.Q0 to R4C9D.A0 n5 C0TOFCO_DE --- 0.809 R4C9D.A0 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.130 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.462 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 2.285 (77.3% logic, 22.7% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.409ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i4 (to osc_clk_c_c +) Delay: 2.226ns (76.7% logic, 23.3% route), 4 logic levels. Constraint Details: 2.226ns physical path delay SLICE_0 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.409ns Physical Path Details: Data path SLICE_0 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.518 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.703 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.130 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF1_DE --- 0.509 R4C9C.FCI to R4C9C.F1 SLICE_1 ROUTE 1 0.000 R4C9C.F1 to R4C9C.DI1 n52 (to osc_clk_c_c) -------- 2.226 (76.7% logic, 23.3% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.409ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 2.226ns (76.7% logic, 23.3% route), 4 logic levels. Constraint Details: 2.226ns physical path delay SLICE_1 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.409ns Physical Path Details: Data path SLICE_1 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q1 to R4C9C.A1 n6 C1TOFCO_DE --- 0.703 R4C9C.A1 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.509 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 2.226 (76.7% logic, 23.3% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.409ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 2.226ns (76.7% logic, 23.3% route), 4 logic levels. Constraint Details: 2.226ns physical path delay SLICE_3 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.409ns Physical Path Details: Data path SLICE_3 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.703 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF1_DE --- 0.509 R4C9D.FCI to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 2.226 (76.7% logic, 23.3% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.433ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 2.202ns (76.5% logic, 23.5% route), 3 logic levels. Constraint Details: 2.202ns physical path delay SLICE_1 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.433ns Physical Path Details: Data path SLICE_1 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q0 to R4C9C.A0 n7 C0TOFCO_DE --- 0.809 R4C9C.A0 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF1_DE --- 0.509 R4C9D.FCI to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 2.202 (76.5% logic, 23.5% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.433ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i4 (to osc_clk_c_c +) Delay: 2.202ns (76.5% logic, 23.5% route), 3 logic levels. Constraint Details: 2.202ns physical path delay SLICE_3 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.433ns Physical Path Details: Data path SLICE_3 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.809 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF1_DE --- 0.509 R4C9C.FCI to R4C9C.F1 SLICE_1 ROUTE 1 0.000 R4C9C.F1 to R4C9C.DI1 n52 (to osc_clk_c_c) -------- 2.202 (76.5% logic, 23.5% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.433ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i5 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 2.202ns (76.5% logic, 23.5% route), 3 logic levels. Constraint Details: 2.202ns physical path delay SLICE_5 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.433ns Physical Path Details: Data path SLICE_5 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9D.CLK to R4C9D.Q0 SLICE_5 (from osc_clk_c_c) ROUTE 1 0.518 R4C9D.Q0 to R4C9D.A0 n5 C0TOFCO_DE --- 0.809 R4C9D.A0 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.509 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 2.202 (76.5% logic, 23.5% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.444ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i6 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 2.191ns (75.8% logic, 24.2% route), 4 logic levels. Constraint Details: 2.191ns physical path delay SLICE_5 to SLICE_2 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.444ns Physical Path Details: Data path SLICE_5 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9D.CLK to R4C9D.Q1 SLICE_5 (from osc_clk_c_c) ROUTE 13 0.530 R4C9D.Q1 to R4C9D.A1 cnt_6 C1TOFCO_DE --- 0.703 R4C9D.A1 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOFCO_D --- 0.130 R4C10A.FCI to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.462 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 2.191 (75.8% logic, 24.2% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.456ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i3 (to osc_clk_c_c +) Delay: 2.179ns (76.2% logic, 23.8% route), 4 logic levels. Constraint Details: 2.179ns physical path delay SLICE_0 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.456ns Physical Path Details: Data path SLICE_0 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.518 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.703 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOFCO_D --- 0.130 R4C9B.FCI to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF0_DE --- 0.462 R4C9C.FCI to R4C9C.F0 SLICE_1 ROUTE 1 0.000 R4C9C.F0 to R4C9C.DI0 n53 (to osc_clk_c_c) -------- 2.179 (76.2% logic, 23.8% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.456ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 2.179ns (76.2% logic, 23.8% route), 4 logic levels. Constraint Details: 2.179ns physical path delay SLICE_1 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.456ns Physical Path Details: Data path SLICE_1 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q1 to R4C9C.A1 n6 C1TOFCO_DE --- 0.703 R4C9C.A1 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOFCO_D --- 0.130 R4C9D.FCI to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.462 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 2.179 (76.2% logic, 23.8% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.456ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 2.179ns (76.2% logic, 23.8% route), 4 logic levels. Constraint Details: 2.179ns physical path delay SLICE_3 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.456ns Physical Path Details: Data path SLICE_3 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.703 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOFCO_D --- 0.130 R4C9C.FCI to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF0_DE --- 0.462 R4C9D.FCI to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 2.179 (76.2% logic, 23.8% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.468ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i7 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 2.167ns (75.5% logic, 24.5% route), 3 logic levels. Constraint Details: 2.167ns physical path delay SLICE_4 to SLICE_2 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.468ns Physical Path Details: Data path SLICE_4 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C10A.CLK to R4C10A.Q0 SLICE_4 (from osc_clk_c_c) ROUTE 13 0.530 R4C10A.Q0 to R4C10A.A0 cnt_7 C0TOFCO_DE --- 0.809 R4C10A.A0 to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.462 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 2.167 (75.5% logic, 24.5% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.480ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 2.155ns (76.0% logic, 24.0% route), 3 logic levels. Constraint Details: 2.155ns physical path delay SLICE_1 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.480ns Physical Path Details: Data path SLICE_1 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q0 to R4C9C.A0 n7 C0TOFCO_DE --- 0.809 R4C9C.A0 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF0_DE --- 0.462 R4C9D.FCI to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 2.155 (76.0% logic, 24.0% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.480ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i3 (to osc_clk_c_c +) Delay: 2.155ns (76.0% logic, 24.0% route), 3 logic levels. Constraint Details: 2.155ns physical path delay SLICE_3 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.480ns Physical Path Details: Data path SLICE_3 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q0 to R4C9B.A0 n9 C0TOFCO_DE --- 0.809 R4C9B.A0 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF0_DE --- 0.462 R4C9C.FCI to R4C9C.F0 SLICE_1 ROUTE 1 0.000 R4C9C.F0 to R4C9C.DI0 n53 (to osc_clk_c_c) -------- 2.155 (76.0% logic, 24.0% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.480ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i5 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 2.155ns (76.0% logic, 24.0% route), 3 logic levels. Constraint Details: 2.155ns physical path delay SLICE_5 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.480ns Physical Path Details: Data path SLICE_5 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9D.CLK to R4C9D.Q0 SLICE_5 (from osc_clk_c_c) ROUTE 1 0.518 R4C9D.Q0 to R4C9D.A0 n5 C0TOFCO_DE --- 0.809 R4C9D.A0 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.462 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 2.155 (76.0% logic, 24.0% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.527ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i6 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 2.108ns (74.9% logic, 25.1% route), 3 logic levels. Constraint Details: 2.108ns physical path delay SLICE_5 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.527ns Physical Path Details: Data path SLICE_5 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9D.CLK to R4C9D.Q1 SLICE_5 (from osc_clk_c_c) ROUTE 13 0.530 R4C9D.Q1 to R4C9D.A1 cnt_6 C1TOFCO_DE --- 0.703 R4C9D.A1 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF1_DE --- 0.509 R4C10A.FCI to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 2.108 (74.9% logic, 25.1% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.539ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i2 (to osc_clk_c_c +) Delay: 2.096ns (75.3% logic, 24.7% route), 3 logic levels. Constraint Details: 2.096ns physical path delay SLICE_0 to SLICE_3 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.539ns Physical Path Details: Data path SLICE_0 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.518 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.703 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOF1_DE --- 0.509 R4C9B.FCI to R4C9B.F1 SLICE_3 ROUTE 1 0.000 R4C9B.F1 to R4C9B.DI1 n54 (to osc_clk_c_c) -------- 2.096 (75.3% logic, 24.7% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.539ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 2.096ns (75.3% logic, 24.7% route), 3 logic levels. Constraint Details: 2.096ns physical path delay SLICE_1 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.539ns Physical Path Details: Data path SLICE_1 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q1 to R4C9C.A1 n6 C1TOFCO_DE --- 0.703 R4C9C.A1 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF1_DE --- 0.509 R4C9D.FCI to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 2.096 (75.3% logic, 24.7% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.539ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i4 (to osc_clk_c_c +) Delay: 2.096ns (75.3% logic, 24.7% route), 3 logic levels. Constraint Details: 2.096ns physical path delay SLICE_3 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.539ns Physical Path Details: Data path SLICE_3 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.703 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF1_DE --- 0.509 R4C9C.FCI to R4C9C.F1 SLICE_1 ROUTE 1 0.000 R4C9C.F1 to R4C9C.DI1 n52 (to osc_clk_c_c) -------- 2.096 (75.3% logic, 24.7% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.574ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i8 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 2.061ns (74.3% logic, 25.7% route), 3 logic levels. Constraint Details: 2.061ns physical path delay SLICE_4 to SLICE_2 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.574ns Physical Path Details: Data path SLICE_4 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C10A.CLK to R4C10A.Q1 SLICE_4 (from osc_clk_c_c) ROUTE 13 0.530 R4C10A.Q1 to R4C10A.A1 cnt_8 C1TOFCO_DE --- 0.703 R4C10A.A1 to R4C10A.FCO SLICE_4 ROUTE 1 0.000 R4C10A.FCO to R4C10B.FCI n1305 FCITOF0_DE --- 0.462 R4C10B.FCI to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 2.061 (74.3% logic, 25.7% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.574ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i6 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 2.061ns (74.3% logic, 25.7% route), 3 logic levels. Constraint Details: 2.061ns physical path delay SLICE_5 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.574ns Physical Path Details: Data path SLICE_5 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9D.CLK to R4C9D.Q1 SLICE_5 (from osc_clk_c_c) ROUTE 13 0.530 R4C9D.Q1 to R4C9D.A1 cnt_6 C1TOFCO_DE --- 0.703 R4C9D.A1 to R4C9D.FCO SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI n1304 FCITOF0_DE --- 0.462 R4C10A.FCI to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 2.061 (74.3% logic, 25.7% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.586ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i1 (to osc_clk_c_c +) Delay: 2.049ns (74.7% logic, 25.3% route), 3 logic levels. Constraint Details: 2.049ns physical path delay SLICE_0 to SLICE_3 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.586ns Physical Path Details: Data path SLICE_0 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.518 R4C9A.Q1 to R4C9A.A1 n10 C1TOFCO_DE --- 0.703 R4C9A.A1 to R4C9A.FCO SLICE_0 ROUTE 1 0.000 R4C9A.FCO to R4C9B.FCI n1301 FCITOF0_DE --- 0.462 R4C9B.FCI to R4C9B.F0 SLICE_3 ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 n55 (to osc_clk_c_c) -------- 2.049 (74.7% logic, 25.3% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.586ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 2.049ns (74.7% logic, 25.3% route), 3 logic levels. Constraint Details: 2.049ns physical path delay SLICE_1 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.586ns Physical Path Details: Data path SLICE_1 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q1 to R4C9C.A1 n6 C1TOFCO_DE --- 0.703 R4C9C.A1 to R4C9C.FCO SLICE_1 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI n1303 FCITOF0_DE --- 0.462 R4C9D.FCI to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 2.049 (74.7% logic, 25.3% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 478.586ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i3 (to osc_clk_c_c +) Delay: 2.049ns (74.7% logic, 25.3% route), 3 logic levels. Constraint Details: 2.049ns physical path delay SLICE_3 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 478.586ns Physical Path Details: Data path SLICE_3 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q1 to R4C9B.A1 n8 C1TOFCO_DE --- 0.703 R4C9B.A1 to R4C9B.FCO SLICE_3 ROUTE 1 0.000 R4C9B.FCO to R4C9C.FCI n1302 FCITOF0_DE --- 0.462 R4C9C.FCI to R4C9C.F0 SLICE_1 ROUTE 1 0.000 R4C9C.F0 to R4C9C.DI0 n53 (to osc_clk_c_c) -------- 2.049 (74.7% logic, 25.3% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.036ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i7 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 1.599ns (66.9% logic, 33.1% route), 2 logic levels. Constraint Details: 1.599ns physical path delay SLICE_4 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.036ns Physical Path Details: Data path SLICE_4 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C10A.CLK to R4C10A.Q0 SLICE_4 (from osc_clk_c_c) ROUTE 13 0.530 R4C10A.Q0 to R4C10A.A0 cnt_7 CTOF1_DEL --- 0.703 R4C10A.A0 to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 1.599 (66.9% logic, 33.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.048ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i4 (to osc_clk_c_c +) Delay: 1.587ns (67.4% logic, 32.6% route), 2 logic levels. Constraint Details: 1.587ns physical path delay SLICE_1 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.048ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q0 to R4C9C.A0 n7 CTOF1_DEL --- 0.703 R4C9C.A0 to R4C9C.F1 SLICE_1 ROUTE 1 0.000 R4C9C.F1 to R4C9C.DI1 n52 (to osc_clk_c_c) -------- 1.587 (67.4% logic, 32.6% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.048ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i2 (to osc_clk_c_c +) Delay: 1.587ns (67.4% logic, 32.6% route), 2 logic levels. Constraint Details: 1.587ns physical path delay SLICE_3 to SLICE_3 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.048ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q0 to R4C9B.A0 n9 CTOF1_DEL --- 0.703 R4C9B.A0 to R4C9B.F1 SLICE_3 ROUTE 1 0.000 R4C9B.F1 to R4C9B.DI1 n54 (to osc_clk_c_c) -------- 1.587 (67.4% logic, 32.6% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.048ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i5 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 1.587ns (67.4% logic, 32.6% route), 2 logic levels. Constraint Details: 1.587ns physical path delay SLICE_5 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.048ns Physical Path Details: Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9D.CLK to R4C9D.Q0 SLICE_5 (from osc_clk_c_c) ROUTE 1 0.518 R4C9D.Q0 to R4C9D.A0 n5 CTOF1_DEL --- 0.703 R4C9D.A0 to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 1.587 (67.4% logic, 32.6% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.335ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i9 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i9 (to osc_clk_c_c +) Delay: 1.300ns (59.2% logic, 40.8% route), 2 logic levels. Constraint Details: 1.300ns physical path delay SLICE_2 to SLICE_2 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.335ns Physical Path Details: Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C10B.CLK to R4C10B.Q0 SLICE_2 (from osc_clk_c_c) ROUTE 13 0.530 R4C10B.Q0 to R4C10B.A0 cnt_9 CTOF_DEL --- 0.404 R4C10B.A0 to R4C10B.F0 SLICE_2 ROUTE 1 0.000 R4C10B.F0 to R4C10B.DI0 n47 (to osc_clk_c_c) -------- 1.300 (59.2% logic, 40.8% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.335ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i7 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i7 (to osc_clk_c_c +) Delay: 1.300ns (59.2% logic, 40.8% route), 2 logic levels. Constraint Details: 1.300ns physical path delay SLICE_4 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.335ns Physical Path Details: Data path SLICE_4 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C10A.CLK to R4C10A.Q0 SLICE_4 (from osc_clk_c_c) ROUTE 13 0.530 R4C10A.Q0 to R4C10A.A0 cnt_7 CTOF_DEL --- 0.404 R4C10A.A0 to R4C10A.F0 SLICE_4 ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 n49 (to osc_clk_c_c) -------- 1.300 (59.2% logic, 40.8% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.335ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i8 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i8 (to osc_clk_c_c +) Delay: 1.300ns (59.2% logic, 40.8% route), 2 logic levels. Constraint Details: 1.300ns physical path delay SLICE_4 to SLICE_4 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.335ns Physical Path Details: Data path SLICE_4 to SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C10A.CLK to R4C10A.Q1 SLICE_4 (from osc_clk_c_c) ROUTE 13 0.530 R4C10A.Q1 to R4C10A.A1 cnt_8 CTOF_DEL --- 0.404 R4C10A.A1 to R4C10A.F1 SLICE_4 ROUTE 1 0.000 R4C10A.F1 to R4C10A.DI1 n48 (to osc_clk_c_c) -------- 1.300 (59.2% logic, 40.8% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C10A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.335ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i6 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i6 (to osc_clk_c_c +) Delay: 1.300ns (59.2% logic, 40.8% route), 2 logic levels. Constraint Details: 1.300ns physical path delay SLICE_5 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.335ns Physical Path Details: Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9D.CLK to R4C9D.Q1 SLICE_5 (from osc_clk_c_c) ROUTE 13 0.530 R4C9D.Q1 to R4C9D.A1 cnt_6 CTOF_DEL --- 0.404 R4C9D.A1 to R4C9D.F1 SLICE_5 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 n50 (to osc_clk_c_c) -------- 1.300 (59.2% logic, 40.8% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.347ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i0 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i0 (to osc_clk_c_c +) Delay: 1.288ns (59.8% logic, 40.2% route), 2 logic levels. Constraint Details: 1.288ns physical path delay SLICE_0 to SLICE_0 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.347ns Physical Path Details: Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9A.CLK to R4C9A.Q1 SLICE_0 (from osc_clk_c_c) ROUTE 1 0.518 R4C9A.Q1 to R4C9A.A1 n10 CTOF_DEL --- 0.404 R4C9A.A1 to R4C9A.F1 SLICE_0 ROUTE 1 0.000 R4C9A.F1 to R4C9A.DI1 n56 (to osc_clk_c_c) -------- 1.288 (59.8% logic, 40.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9A.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.347ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i4 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i4 (to osc_clk_c_c +) Delay: 1.288ns (59.8% logic, 40.2% route), 2 logic levels. Constraint Details: 1.288ns physical path delay SLICE_1 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.347ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q1 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q1 to R4C9C.A1 n6 CTOF_DEL --- 0.404 R4C9C.A1 to R4C9C.F1 SLICE_1 ROUTE 1 0.000 R4C9C.F1 to R4C9C.DI1 n52 (to osc_clk_c_c) -------- 1.288 (59.8% logic, 40.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.347ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i3 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i3 (to osc_clk_c_c +) Delay: 1.288ns (59.8% logic, 40.2% route), 2 logic levels. Constraint Details: 1.288ns physical path delay SLICE_1 to SLICE_1 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.347ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9C.CLK to R4C9C.Q0 SLICE_1 (from osc_clk_c_c) ROUTE 1 0.518 R4C9C.Q0 to R4C9C.A0 n7 CTOF_DEL --- 0.404 R4C9C.A0 to R4C9C.F0 SLICE_1 ROUTE 1 0.000 R4C9C.F0 to R4C9C.DI0 n53 (to osc_clk_c_c) -------- 1.288 (59.8% logic, 40.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9C.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.347ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i2 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i2 (to osc_clk_c_c +) Delay: 1.288ns (59.8% logic, 40.2% route), 2 logic levels. Constraint Details: 1.288ns physical path delay SLICE_3 to SLICE_3 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.347ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q1 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q1 to R4C9B.A1 n8 CTOF_DEL --- 0.404 R4C9B.A1 to R4C9B.F1 SLICE_3 ROUTE 1 0.000 R4C9B.F1 to R4C9B.DI1 n54 (to osc_clk_c_c) -------- 1.288 (59.8% logic, 40.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.347ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i1 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i1 (to osc_clk_c_c +) Delay: 1.288ns (59.8% logic, 40.2% route), 2 logic levels. Constraint Details: 1.288ns physical path delay SLICE_3 to SLICE_3 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.347ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9B.CLK to R4C9B.Q0 SLICE_3 (from osc_clk_c_c) ROUTE 1 0.518 R4C9B.Q0 to R4C9B.A0 n9 CTOF_DEL --- 0.404 R4C9B.A0 to R4C9B.F0 SLICE_3 ROUTE 1 0.000 R4C9B.F0 to R4C9B.DI0 n55 (to osc_clk_c_c) -------- 1.288 (59.8% logic, 40.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9B.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 479.347ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q cnt_237__i5 (from osc_clk_c_c +) Destination: FF Data in cnt_237__i5 (to osc_clk_c_c +) Delay: 1.288ns (59.8% logic, 40.2% route), 2 logic levels. Constraint Details: 1.288ns physical path delay SLICE_5 to SLICE_5 meets 480.769ns delay constraint less 0.000ns skew and 0.134ns DIN_SET requirement (totaling 480.635ns) by 479.347ns Physical Path Details: Data path SLICE_5 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.366 R4C9D.CLK to R4C9D.Q0 SLICE_5 (from osc_clk_c_c) ROUTE 1 0.518 R4C9D.Q0 to R4C9D.A0 n5 CTOF_DEL --- 0.404 R4C9D.A0 to R4C9D.F0 SLICE_5 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 n51 (to osc_clk_c_c) -------- 1.288 (59.8% logic, 40.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 6 3.080 OSC.OSC to R4C9D.CLK osc_clk_c_c -------- 3.080 (0.0% logic, 100.0% route), 0 logic levels. Report: 369.959MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "osc_clk_c_c" 2.080000 | | | MHz ; | 2.080 MHz| 369.959 MHz| 7 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 5 clocks: Clock Domain: n1378 Source: SLICE_25.F1 Loads: 2 No transfer within this clock domain is found Clock Domain: osc_clk_c_c Source: OSCH_inst.OSC Loads: 6 Covered under: FREQUENCY NET "osc_clk_c_c" 2.080000 MHz ; Clock Domain: latch_c Source: latch.PAD Loads: 11 No transfer within this clock domain is found Clock Domain: n1377 Source: SLICE_26.F1 Loads: 15 No transfer within this clock domain is found Clock Domain: clk_c Source: clk.PAD Loads: 12 No transfer within this clock domain is found Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 55 paths, 1 nets, and 191 connections (65.19% coverage)


This section outlines the production process of the IPAX. Though not necessarily needed to be done in this particular order, we recommend users to build an IPAX in the step as shown in the diagram below. This page provides steps for assembly process, but the detail of each step can be found in the respective page.
The entire bill of materials for the IPAX is provided in the BOM folder. The BOM also indicates recommended vendors, though users can procure their components through any vendors.
There are 3 printed circuit boards in the IPAX that need to be fabricated. The KiCAD files for all three boards are available in the PCBs folder. In each folder for each PCB, there is a folder called "Gerber" that contains gerber files that are ready to be sent to a PCB house for fabrication.
The control board and the power regulator boards can be fabricated with regular FR-4 substrate, but we strongly recommend that the LED array board should be fabricated with aluminum substrate to help with heat sink.
*There is an optional 4th board called "optics holder" that is not required, but we recommend if users plan to use the IPAX for an application that requires the LED to be on for an extended period of time. This board mainly helps attach the LED array board to the aluminum flange of the housing. It will help dissipate heat from the LEDs out very quickly. However, if heating is not a problem, it can be replaced with a simple 3D printed part.
**Another optinal PCB is an SD card add-on, which will be deprecated and added directly to the control board in future revisions. However, for now, it provides the control board with an access to an SD card without the need to turn the Pi on. The SD card can be used to store environmental data and also to store configuration files.
There are 3 components that need to be printed out using an FDM 3D printer. The STEP files of all three components are provided in Mechanical folder, along with the STEP file for the entire assembly. Note that we use Fusion 360 as the CAD software, so there might be some issues if the files are opened with other software.
There are no special requirements for all these 3D printed parts. We use PLA material to print all of them. Note that the two battery holders shown in the picture below are identical.
*Optics holder can be replaced with an aluminum PCB for better heat dissipation.
The LED board and the Arducam camera board can be attached to the optics holder PCB (or 3D printed part) using a set of M3 screws and standoffs as shown in the image below. The assembly can then be attached to the aluminum flange using a set screw and a screw.
Note that depending on the M12 lens, the position of the camera might need to be adjusted. The provided files are suitable for M12 lens with focal length no longer than 16mm; otherwise, the lens would be too long to fit inside the housing. The lens should be almost flat on top of the acrylic viewport to prevent the LED light from reflecting back into the camera lens.
The Pi Zero W can be attached to the 3D printed PCB tray with a set of M2.5 standoffs (M3 does not fit through the holes on the Pi zero board). Note that this is the only place where M2.5 screws are used; the rest of the system uses M3 only.
The control board is attached directly on top of the Pi with the 40-pin GPIO headers. The power regulator board is attached to the other side of the PCB tray. Then, the entire tray is attached to the flange. Note that the bottom of the tray (the power regulator side) can be reinforced with 87mm M3 standoff (combination of multiple standoffs).
The battery used in this tutorial is Tenergy 31019. Other batteries will work as well, but users need to modify the 3D file for the battery holder.
The endcap requires at least two switches: one for main power and the other for shutdown signal. The environmental sensors are optional and can be replaced with blank screws. All wire-to-wire connections are done with Molex Minifit connectors.
Note that we do not recommend Blueorobotics vent plug, and its function can be done through a switch instead. See mechanical section for more information.
Here is the fully assembled internal parts of the IPAX.
Programming on the control board is done with Arduino platform and on the Pi Zero W is done with Python. The detail can be found on programming section.


My three favorite websites are reddit.com, lumosity.com, and techcrunch.com and I'll explain why!
I love reddit because it is really easy to get lost in the links and enjoy the content. From a user experience perspective, it is rather easy to use and navigate through because the layout and organization is very simple. However, it is quite plain and uninteresting, and sometimes it feels like it could use a bit more visual styling just to spice things up. The content itself is entertaining most of the time but sometimes it can get really innappropriate just because most people are anonymous on the site, and can say whatever they want. While it is very difficult to find a specific article or post, it is easy to find interesting posts in any category on the site. After being on the site for a while it can often feel like you've wasted alot of time, but I can guarantee that it is never boring and I find it very entertaining.
I love lumosity because I genuinely enjoy playing the games on the site and feel like it actually has made a difference in my memory, attention, and problem solving ability. The site is very visually appealing and is organized very well, but because of the way the games are designed, the site is primarily optimized for desktop use with a keyboard and mouse. I like the way it presents your scores and training history on the home page and makes navigating between pages very simple. Generally each session of lumosity only takes about 15 minutes, so I never really feel tired or bored after doing my daily training, but I'm sure that if played for too long I would start to lose interest. I started lumosity as a trial version but eventually ended up paying for it because I liked the way the site was set up and the content was very appealing. Plus, nobody can complain about having a faster, more efficient brain!
techcrunch is one of my favorite websites because it always keeps me up-to-date with interesting advancements in technology and provides at least some explanation of how they work. When I first look at the site I am immediately drawn to the "latest" news feed which shows articles on technology and its applications. Overall the site is visually appealing and I like the neutral color scheme because it is less distracting. Yet, the advertisements are often very ostentatious and annoying, but I can't really complain too much because the content is my main focus. It is very simple to navigate between pages and categories, and the site itself is responsive and always works on any of my devices.


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µEvLoop
A fast and lightweight event loop aimed at embedded platforms in C99.
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Go to the documentation of this file.
7 #ifndef UEL_CONDITIONAL_H
8 #define UEL_CONDITIONAL_H
36 uel_closure_t if_true, uel_closure_t if_false);
Conditionals are constructs that provide functional flow control.
Definition: conditional.h:19
uel_closure_t if_true
The closure that will be invoked if the test closure returns true
Definition: conditional.h:23
uel_closure_t if_false
The closure that will be invoked if the test closure returns false
Definition: conditional.h:25
Defines closures, objects that bind functions to creating and calling contexts.
uel_closure_t test
A closure that, based on its input, should return true or false.
Definition: conditional.h:21
void * uel_conditional_apply(uel_conditional_t *conditional, void *params)
Applies a conditional do some input.
void uel_conditional_init(uel_conditional_t *conditional, uel_closure_t test, uel_closure_t if_true, uel_closure_t if_false)
Initialises a conditional structure.


Logan Paul admits to breaking self-imposed sex ban ahead of KSI rematch
Paul takes on YouTube rival KSI in their rematch in Los Angeles on Saturday after the pair turned professional
by Martin Domin, https://www.facebook.com/mirrorfightingLogan Paul has admitted he broke his own sex ban in the build up to his rematch with KSI.
The American YouTube star will settle his feud with his fellow social media sensation when the pair clash in Los Angeles on Saturday.
Paul has been training with former heavyweight world champion Shannon Briggs after turning professional for the sequel which will be held 14 months after the first fight ended in a draw.
Paul had previously claimed that he was abstaining from sex for the duration of this training camp and that he had banned girls from his 'Maverick Mansion'.
But he has now conceded: "There were no girlfriends, just tunnel vision, no sex all camp but just one issue a month ago... so we did four weeks.
"In this camp I have never been more calm focused and confident. I truly feel like the best version of myself and better than I have ever felt and boxing is the vehicle for that."
Briggs was brought on board earlier this year when promoter Eddie Hearn demanded Paul and KSI turn professional in order for him to stage the show.
And the 47-year-old former boxer insists his man has the mentality to win.
"He's mean right now, he's ready to fight," he said. "Everybody had to move people out of the house, we're not playing.
"I called him the first week and told him he had to change as a person, that boxing will change you.
"You've got to dig deep into your soul because you have to confront fighting another man. I don't care what you say, it's not easy; you can lose, get knocked out, be embarrassed.
"The man's already famous so he's got a lot to lose.


Index of all elements
[ d ]
[ g ]
[ i ]
[ l ]
[ m ]
[ p ]
[ u ]
[ w ]
[ _ ]
top
top
i
- instance
- in file DataGraph.php, method DataGraph::instance()
Creates an instance of this class if none exists. Returns instance otherwise.
top
l
- Logger
- in file Logger.php, class Logger
Logger class.
- Logger.php
- procedural page Logger.php
top
m
- mapData
- in file WrapperFlickr.php, method WrapperFlickr::mapData()
Maps data from data source response in dataobject extending datagraph.
- mapData
- in file Wrapper.php, method Wrapper::mapData()
Method for deriving class to map data from data source response to dataobject extending datagraph.
- Mediator
- in file Mediator.php, class Mediator
Mediator class.
- Mediator.php
- procedural page Mediator.php
top
p
- push
- in file DataGraph.php, method DataGraph::push()
Adds dataobjects (entities/attributes) to the datagraph (DomDocument) by calling itself recursively depending on the depth of the given dataobject array.
top
top
w
- Wrapper
- in file Wrapper.php, class Wrapper
Wrapper class.
- WrapperFlickr.php
- procedural page WrapperFlickr.php
- Wrapper.php
- procedural page Wrapper.php
- WrapperFlickr
- in file WrapperFlickr.php, class WrapperFlickr
Wrapper class for Flickr API.
top
_
- __autoload
- in file DataIntegrator.php, function __autoload()
Autoloader for classes depending on filename.
- __construct
- in file WrapperFlickr.php, method WrapperFlickr::__construct()
Stores given config from calling class in member variable.
- __construct
- in file Wrapper.php, method Wrapper::__construct()
Loads datagraph instance.
- __construct
- in file Mediator.php, method Mediator::__construct()
Returns false when config could not be loaded. Initiates logger and wrapper functionality. Overwrites current error reporting level.
- __construct
- in file Logger.php, method Logger::__construct()
Sets log file destination when given. Overwrites PHP error handler.
- __destruct
- in file Mediator.php, method Mediator::__destruct()
Resets to original error reporting level.
top
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1. What are the differences between processes and threads
| Process | Thread | |
| Definition | A program in progress | A segment of a process |
| Lightweight | Not Lightweight | Lightweight |
| Creation/Termination/Communication Time | More | Less |
| Resources | More | Less |
| By OS | Treated separately by OS | Treated as a single task |
| Memory | Do not share memory | share memory |


sada(1) Qualcomm Atheros Open Powerline Toolkit sada(1) NAME sada - slave authorization/deauthorization SYNOPSIS sada [options] [...] DESCRIPTION OPTIONS -e Redirects stderr messages to stdout. By convention status and error messages are printed on stderr while primary program output is printed on stdout. This option prints all output on stdout in cases where this is desired. -q Suppresses status messages on stderr. -v Print additional information on stdout. In particular, this option dumps incoming and outgoing packets which can be saved as text files for reference. -?,--help Print program help summary on stdout. This option takes precedence over other options on the command line. -!,--version Print program version information on stdout. This option takes precedence over other options on the command line. Use this option when sending screen dumps to Atheros Technical Support so that they know exactly which version of the Linux Toolkit you are using. ARGUMENTS EXAMPLES None. REFERENCES See the Qualcomm Atheros Powerline Firmware Technical Reference Manual for more information about MDU powerline configu‐ ration. DISCLAIMER None. SEE ALSO plc(1), mdustats(1) CREDITS Charles Maier<EMAIL_ADDRESS>open-plc-utils-0.0.3 November 2013 sada(1)


This fishing port is a popular summer tourist resort, especially for families who enjoy its great beaches. It also has many cycle and walking trails in the surrounding wooded countryside.
Position 54° 46'12"N, 17° 33'07"E (harbour entrance)
Customs and Immigration office is at the harbour entrance. Call VHF channel 12.
Warning - the entrance (161m wide) becomes difficult in winds from W through N to NE above Force 5.
There is an outbound current at the entrance, and the port itself of up to 2kn an influence from Lake Lebsko. The most frequent cross current is NE 2-3kn during strong westerly winds.
Approaches - although the approach to Leba is easy during the day as well as at night, during a sunny summers day, locating the actual entrance can be difficult (the sun's reflection on the water, the white sands, and the trees screening the port, cause the problem.) Locate the castle-like structure on the Hotel Neptune then look for the mole heads.
From the west - Lighthouse Czolpino Fl W 8s Mo(n) 75m 12M, round and built from red brick. Unfortunately it is obscured by trees leaving mainly the top black dome, housing the light visible. Before the lighthouse you will see the sand dunes, 40-50m high, glistening in the sun.
From the East - Lighthouse Stilo (Fl(3)W 12s 75m 23M, red tower, black and white bands, mounted high up on the top of the dunes and clearly visible. Hotel Neptune (known as Georing's Palace) has the appearance of a castle with a single tower. Three grey, steel chimneys in town can be seen. The middle one is 40m tall. 4.5M east of Leba, close to shore, masts of a wreck Nord Star stick out of the water. A signal mast is situated 320m south of eastern head.


About Us
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{% extends "main.html" %} {% block content %}
Time series forecasting is the process of analyzing time series data using, statistics and modeling to make predictions and inform strategic decision-making. In some industries, forecasting might refer to data at a specific future point in time, while prediction refers to future data in general. Time series allows you to analyze major patterns such as trends, seasonality, cyclicity, and irregularity. Time series analysis is used for various applications such as stock market analysis, pattern recognition, earthquake prediction, economic forecasting, census analysis and so on.
Time series analysis comprises methods for analyzing time series data in order to extract meaningful statistics and other characteristics of the data. Time series forecasting is the use of a model to predict future values based on previously observed values.


Goldbach’s Conjecture
问题描述 :
Goldbach’s Conjecture: For any even number n greater than or equal to 4, there exists at least one pair of prime numbers p1 and p2 such that n = p1 + p2.
This conjecture has not been proved nor refused yet. No one is sure whether this conjecture actually holds. However, one can find such a pair of prime numbers, if any, for a given even number. The problem here is to write a program that reports the number of all the pairs of prime numbers satisfying the condition in the conjecture for a given even number.
This conjecture has not been proved nor refused yet. No one is sure whether this conjecture actually holds. However, one can find such a pair of prime numbers, if any, for a given even number. The problem here is to write a program that reports the number of all the pairs of prime numbers satisfying the condition in the conjecture for a given even number.
A sequence of even numbers is given as input. Corresponding to each number, the program should output the number of pairs mentioned above. Notice that we are interested in the number of essentially different pairs and therefore you should not count (p1, p2) and (p2, p1) separately as two different pairs.
输入:
An integer is given in each input line. You may assume that each integer is even, and is greater than or equal to 4 and less than 2^15. The end of the input is indicated by a number 0.
输出:
Each output line should contain an integer number. No other characters should appear in the output.
样例输入:
6 10 12 0
样例输出:
1 2 1
#include "stdio.h" #include <math.h> #define MAXINT 65536 int main() { bool prime[MAXINT]; int i, l, j, n; //构造素数表 for (i = 0; i < MAXINT; i++) prime[i] = 1; l = sqrt((double)MAXINT); for(i = 2; i <= l; i++) if(prime[i]) for(j = 2; j*i < MAXINT; j++) prime[j*i] = 0; //构造素数表 while(~scanf("%d",&n)) { if(n == 0) break; l = n/2, j = 0; for (i = 2; i <= l; i++) if (prime[i] && prime[n-i]) j++; printf("%d\n", j); } return 0; }
解题报告转自：http://blog.csdn.net/ysc504/article/details/8251210
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请问printAllCombination的时间复杂度怎么分析呢？
6题应该就是算概率的吧
我觉得是D哎……
bottes vernies blanches
I appreciate the efforts you men and women place in to share blogs on such sort of matters, it was certainly useful. Keep Posting!
Excellent Web-site! I required to ask if I might webpages and use a component of the net web website and use a number of factors for just about any faculty process. Please notify me through email regardless of whether that would be excellent. 此时的数据量还是很小的，耗时却不短。这种方法确实可以，当然或许还有其他的优化方案，但是优化只能针对某些数据，不太可能在所有情况下都能在可接受的时间内求解出答案。


The socket package provides interface ala {@link java.net.Socket}
over JXTA pipes. Since the PipeService provides uni-directional, and
unreliable communication channels, the JxtaSocket employs it's own
protocol over pipes to establish bi-directional connections for every
request. In addition the JxtaSocket also employs the reliability
library to ensure reliable delivery of data. Another feature of
JxtaSockets is chunking, which relieves applications from having to
worry about mtu size, just remember to invoke flush at the end of data
transmission
JxtaSocket defines the following message elements employed during
the life cycle of a JxtaSocket :
The socket package also provides interface ala {@link
java.net.MulticastSocket} over propagated pipes. Keep in mind
JxtaMulticastSocket does not provide chunking nor reliability at this
time, therefore one must consider configuration parameters such as the
multicast datagram size defined for the TCP Message Transport :
As well as any other mtu size imposed by the JXTA Platform, or the
operating system.
For examples on how to utilize the net.jxta.socket see the online
tutorials on JxtaSocket,
and JxtaMulticastSocket
available at http://www.jxta.org/Tutorials.html


すべてのクラス
BigPentagonEnemy
BigPentagonEnemyDrawer
BigSquareEnemy
BigSquareEnemyDrawer
BigTriangleEnemy
BigTriangleEnemyDrawer
Configuration
Direction
Enemy
ExpeditionLine
ExpeditionLineDrawer
Field
GameContext
GameContext.State
GameScreen
Level
Levels
Main
Player
PlayerDrawer
Point
Region
ResultScreen
Screen
Sprite
SpriteDrawer
SquareEnemy
SquareEnemyDrawer
Territory
Territory.State
TerritoryDrawer
TitleScreen
TriangleEnemy
TriangleEnemyDrawer