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The Abstract Factory Pattern¶
A “Creational Pattern” from the Gang of Four book
Verdict
The Abstract Factory is an awkward workaround for the lack of first-class functions and classes in less powerful programming languages. It is a poor fit for Python, where we can instead simply pass a class or a factory function when a library needs to create objects on our behalf.
The Python Standard Library’s json
module
is a good example of a library
that needs to instantiate objects on behalf of its caller.
Consider a JSON string like this one:
text = '{"total": 9.61, "items": ["Americano", "Omelet"]}'
By default, the json
module’s loads()
function
will create unicode
objects
for the strings "Americano"
and "Omelet"
,
a list
to hold them,
a Python float
for 9.61
,
and a dict
with unicode
keys for the top-level JSON object.
But some users will not be content with these defaults.
For example, an accountant would probably be unhappy
with the choice of a float
to represent an exact amount like “9 dollars 61 cents”
and would prefer an exact Decimal
instead.
The need to control what kind of numeric object the json
module creates
is a specific instance of a general problem:
- In the course of performing its duties, a routine is going to need to create a number of objects on behalf of the caller.
- But the class that the routine would instantiate by default does not cover all possible cases.
- So instead of hard-coding that default class and making customization impossible, the routine wants to let the caller specify which classes it will instantiate.
First, we’ll look at the Pythonic approach to this problem. Then we’ll start placing a series of restrictions on our Python code to more closely model legacy object oriented languages, until the Abstract Factory pattern emerges as the best solution within those limitations.
The Pythonic approach: callable factories¶
In Python, a “callable” —
any object f
that executes code
when invoked using the syntax f(a, b, c)
—
is a first-class object.
To be “first class” means that a callable can be passed as a parameter,
returned as a return value,
and can even be stored in a data structure
like a list or dictionary.
First-class callables offer a powerful mechanism for implementing object “factories”, a fancy term for “routines that build and return new objects.”
A beginning Python programmer might expect that each time they need to supply a factory, they will be responsible for writing a function:
import json
from decimal import Decimal
def build_decimal(string):
return Decimal(string)
print(json.loads(text, parse_float=build_decimal))
{'total': Decimal('9.61'), 'items': ['Americano', 'Omelet']}
This simple factory ran successfully! The number returned is a decimal instead of a float.
(Note my choice of a verb build_decimal()
as the name of this function,
instead of a noun like decimal_factory()
—
I find a function name easier to read when it tells me what the function does
instead of telling me what kind of function it is.)
While the above function will certainly work,
there is an elision we can perform
thanks to the fact that Python types are themselves callables.
Because Decimal
is a callable taking a string argument
and returning a decimal object instance,
we can dispense with our own factory
and pass the Decimal
type directly to the JSON loader!
Unless we need to edit the string first,
like by removing a leading currency symbol,
Decimal
can completely replace our little factory:
print(json.loads(text, parse_float=Decimal))
{'total': Decimal('9.61'), 'items': ['Americano', 'Omelet']}
There is one implementation detail that deserves mention.
If you study the json
module
you will discover that load()
is simply a wrapper
around the JSONDecoder
class.
How does the decoder instance itself support an alternative factory?
Its initialization method stores the parse_float
argument
as an instance attribute,
defaulting to Python’s built-in float
type if no override was specified:
self.parse_float = parse_float or float
It can then invoke it later as self.parse_float(…)
.
If you are interested in variations on this pattern — where a class uses its instance attributes to remember how it’s supposed to create a specific kind of object — then try reading about the Factory Method which explores several variations on this maneuver.
But to arrive at the Abstract Factory pattern,
we need to head in a different direction.
Here we’ll pursue what happens to an object factory itself —
whether Decimal()
or our hand-written build_decimal()
—
if we begin restricting the set of Python features we let ourselves use.
Restriction: outlaw passing callables¶
What if Python didn’t let you pass callables as parameters?
That restriction would remove an entire dimension from Python’s flexibility. Instead of supporting both “nouns” and “verbs” as arguments — both class instances and callable functions — some legacy languages only support passing class instances. Under that restriction, every simple factory would need to pivot from a function to a method:
# In Python: a factory function.
def build_decimal(string):
return Decimal(string.lstrip('$'))
# In some legacy languages: the code must
# move inside a class method instead.
class DecimalFactory(object):
@staticmethod
def build(string):
return Decimal(string.lstrip('$'))
In traditional Object Oriented programming,
the word “factory” is the name of this kind of class —
a class that offers a method that builds an object.
In naming the equivalent Python function build_decimal()
,
therefore,
I’m not only indulging in my own preference
for giving functions verb-names rather than noun-names,
but being as precise as possible in naming:
the “factory” is not the callable,
but the class that holds it.
Instead of continuing our earlier example of JSON parsing, let’s switch to a simpler task that can fit in a couple of lines of code: parsing a comma-separated list of numbers. Here’s how the parser would invoke the builder method on our factory class.
class Loader(object):
@staticmethod
def load(string, factory):
string = string.rstrip(',') # allow trailing comma
return [factory.build(item) for item in string.split(',')]
result = Loader.load('464.80, 993.68', DecimalFactory)
print(result)
[Decimal('464.80'), Decimal('993.68')]
Note that, thanks to the fact that Python classes offer static and class methods that can be invoked without an instance, we have not yet been reduced to needing to instantiate the factory class — we are simply passing the Python class in as a first-class object.
Restriction: outlaw passing classes¶
Next, let’s also pretend that a Python class cannot be passed as a value, but that only object instances can be assigned to names and passed as parameters.
This restriction is going to prevent us
from passing the DecimalFactory
class
as an argument to the load()
method.
Instead, we’re going to have to uselessly instantiate DecimalFactory
and pass the resulting object:
f = DecimalFactory()
result = Loader.load('464.80, 993.68', f)
print(result)
[Decimal('464.80'), Decimal('993.68')]
Note the difference
between this pattern
and the Factory Method.
Here, we are neither asked nor required to subclass Loader
itself
in order to customize the objects it creates.
Instead, object creation is entirely parametrized
by the separate factory object we choose to pass in.
Note also the clear warning sign in the factory’s own code
that build()
should, in Python, not really be the method of an object.
Scroll back up and read the method’s code.
Where does it accept as an argument, or use in its result,
the object self
on which it is being invoked?
It makes no use of it at all!
The method never mentions self
in its code.
As Jack Diederich propounded in his famous talk
Stop Writing Classes,
a method that never uses self
should not actually be a method in Python.
But such are the depths
to which we’ve been driven by these artificial restrictions.
Generalizing: the complete Abstract Factory¶
Two final moves will illustrate the full design pattern.
First, let’s expand our factory to create every kind of object that the loader needs to create — in this case, not just the numbers that are being parsed, but even the container that will hold them. Now that we have switched to instantiating the factory, we can write these as plain methods instead of static methods:
class Factory(object):
def build_sequence(self):
return []
def build_number(self, string):
return Decimal(string)
And here is an updated loader that uses this factory:
class Loader(object):
def load(string, factory):
sequence = factory.build_sequence()
for substring in string.split(','):
item = factory.build_number(substring)
sequence.append(item)
return sequence
f = Factory()
result = Loader.load('1.23, 4.56', f)
print(result)
[Decimal('1.23'), Decimal('4.56')]
Every choice it needs to make about object instantiation is deferred to the factory instead of taking place in the parser itself.
Second, consider the behavior of languages that force you
to declare ahead of time the type of each method parameter.
You would overly restrict your future choices
if your code insisted that the factory
parameter
could only ever be an instance of this particular class Factory
because then you could never pass in anything
that didn’t inherit from it.
Instead, to more happily separate specification from implementation,
you would create an abstract class.
It’s this final step that merits the word “abstract”
in the pattern’s name “Abstract Factory”.
Your abstract class would merely promise
that the factory
argument to load()
would be a class adhering to the required interface:
from abc import ABCMeta, abstractmethod
class AbstractFactory(metaclass=ABCMeta):
@abstractmethod
def build_sequence(self):
pass
@abstractmethod
def build_number(self, string):
pass
Once the abstract class is in place and Factory
inherits from it,
though, the operations that take place at runtime
are exactly the same as they were before.
The factory’s methods are called with various arguments,
which direct them to create various kinds of object,
which they construct and return
without the caller needing to know the details.
It’s like something you might do in Python, but made overly complicated. So avoid the Abstract Factory and use callables as factories instead.


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[gecode-users] compilation question
Alejandro Arbelaez
alejandro.arbelaez at gmail.com
Tue Mar 11 18:07:41 CET 2008
Hi all,
I'm trying to compile gecode with gcc 4.2 and I'm getting the following
error:
g++-4.2 -I. -DNDEBUG -fvisibility=hidden -fPIC -Wextra -Wall -pipe -ggdb -O3
-fno-strict-aliasing -finline-limit=3000 -ffast-math \
-c -o gecode/support/buddy/bddio.o gecode/support/buddy/bddio.c
./gecode/support/buddy/bdd.h: In function 'int bdd_loaddata(FILE*)':
./gecode/support/buddy/bdd.h:508: error: 'bdd::bdd(BDD)' is private
gecode/support/buddy/bddio.c:558: error: within this context
./gecode/support/buddy/bdd.h:508: error: 'bdd::bdd(BDD)' is private
gecode/support/buddy/bddio.c:558: error: within this context
gecode/support/buddy/bddio.c:558: error: cannot convert 'bdd' to 'BDD' for
argument '1' to 'BDD bdd_addref(BDD)'
I think I've a problem installing gcc 4.2 but I'm not sure about that, any
clue?
BTW: my default compiler is i686-apple-darwin9-gcc-4.0.1 and I installed
i686-apple-darwin9-gcc-4.2.1. Finally I configured gecode with the following
characteristics
./configure --prefix=..... CC=g++-4.2 CXX=g++-4.2
Thanks in advance,
Alejandro
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-------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) <IP_ADDRESS>6 Mon Apr 06 13:43:07 2020 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: top Device,speed: LCMXO2-7000HE,M Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "osc_clk" 88.670000 MHz ; 10 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Sin/d_tmp_i0_i53 (from osc_clk +) Destination: FF Data in CIC1Sin/d_d_tmp_i0_i53 (to osc_clk +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay CIC1Sin/SLICE_2167 to CIC1Sin/SLICE_2130 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path CIC1Sin/SLICE_2167 to CIC1Sin/SLICE_2130: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R12C38B.CLK to R12C38B.Q1 CIC1Sin/SLICE_2167 (from osc_clk) ROUTE 3 0.154 R12C38B.Q1 to R12C38D.M1 CIC1Sin/d_tmp_53 (to osc_clk) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CIC1Sin/SLICE_2167: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R12C38B.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CIC1Sin/SLICE_2130: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R12C38D.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Cos/d_tmp_i0_i13 (from osc_clk +) Destination: FF Data in CIC1Cos/d_d_tmp_i0_i13 (to osc_clk +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay CIC1Cos/SLICE_1898 to CIC1Cos/SLICE_1861 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path CIC1Cos/SLICE_1898 to CIC1Cos/SLICE_1861: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R23C19B.CLK to R23C19B.Q1 CIC1Cos/SLICE_1898 (from osc_clk) ROUTE 2 0.154 R23C19B.Q1 to R23C19D.M1 CIC1Cos/d_tmp_13 (to osc_clk) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CIC1Cos/SLICE_1898: Name Fanout Delay (ns) Site Resource ROUTE 999 1.425 OSC.OSC to R23C19B.CLK osc_clk -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1861: Name Fanout Delay (ns) Site Resource ROUTE 999 1.425 OSC.OSC to R23C19D.CLK osc_clk -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Cos/d_tmp_i0_i3 (from osc_clk +) Destination: FF Data in CIC1Cos/d_d_tmp_i0_i3 (to osc_clk +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R22C17A.CLK to R22C17A.Q1 CIC1Cos/SLICE_1893 (from osc_clk) ROUTE 2 0.154 R22C17A.Q1 to R22C17C.M1 CIC1Cos/d_tmp_3 (to osc_clk) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CIC1Cos/SLICE_1893: Name Fanout Delay (ns) Site Resource ROUTE 999 1.425 OSC.OSC to R22C17A.CLK osc_clk -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1856: Name Fanout Delay (ns) Site Resource ROUTE 999 1.425 OSC.OSC to R22C17C.CLK osc_clk -------- 1.425 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Sin/d_tmp_i0_i47 (from osc_clk +) Destination: FF Data in CIC1Sin/d_d_tmp_i0_i47 (to osc_clk +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay CIC1Sin/SLICE_2164 to CIC1Sin/SLICE_2127 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path CIC1Sin/SLICE_2164 to CIC1Sin/SLICE_2127: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C37B.CLK to R7C37B.Q1 CIC1Sin/SLICE_2164 (from osc_clk) ROUTE 3 0.154 R7C37B.Q1 to R7C37A.M1 CIC1Sin/d_tmp_47 (to osc_clk) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CIC1Sin/SLICE_2164: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R7C37B.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CIC1Sin/SLICE_2127: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R7C37A.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Cos/d_tmp_i0_i58 (from osc_clk +) Destination: FF Data in CIC1Cos/d_d_tmp_i0_i58 (to osc_clk +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay CIC1Cos/SLICE_1921 to CIC1Cos/SLICE_1884 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path CIC1Cos/SLICE_1921 to CIC1Cos/SLICE_1884: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C23D.CLK to R14C23D.Q0 CIC1Cos/SLICE_1921 (from osc_clk) ROUTE 3 0.154 R14C23D.Q0 to R14C23C.M1 CIC1Cos/d_tmp_58 (to osc_clk) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CIC1Cos/SLICE_1921: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R14C23D.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1884: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R14C23C.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Cos/d_tmp_i0_i53 (from osc_clk +) Destination: FF Data in CIC1Cos/d_d_tmp_i0_i53 (to osc_clk +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay CIC1Cos/SLICE_1918 to CIC1Cos/SLICE_1882 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path CIC1Cos/SLICE_1918 to CIC1Cos/SLICE_1882: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R16C23C.CLK to R16C23C.Q1 CIC1Cos/SLICE_1918 (from osc_clk) ROUTE 3 0.154 R16C23C.Q1 to R16C23B.M0 CIC1Cos/d_tmp_53 (to osc_clk) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CIC1Cos/SLICE_1918: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R16C23C.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1882: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R16C23B.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Cos/d_tmp_i0_i49 (from osc_clk +) Destination: FF Data in CIC1Cos/d_d_tmp_i0_i49 (to osc_clk +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay CIC1Cos/SLICE_1916 to CIC1Cos/SLICE_1880 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path CIC1Cos/SLICE_1916 to CIC1Cos/SLICE_1880: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R14C22D.CLK to R14C22D.Q1 CIC1Cos/SLICE_1916 (from osc_clk) ROUTE 3 0.154 R14C22D.Q1 to R14C22A.M0 CIC1Cos/d_tmp_49 (to osc_clk) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CIC1Cos/SLICE_1916: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R14C22D.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CIC1Cos/SLICE_1880: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R14C22A.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Sin/d_tmp_i0_i57 (from osc_clk +) Destination: FF Data in CIC1Sin/d_d_tmp_i0_i57 (to osc_clk +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay CIC1Sin/SLICE_2169 to CIC1Sin/SLICE_2132 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path CIC1Sin/SLICE_2169 to CIC1Sin/SLICE_2132: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C38B.CLK to R7C38B.Q1 CIC1Sin/SLICE_2169 (from osc_clk) ROUTE 3 0.154 R7C38B.Q1 to R7C38C.M1 CIC1Sin/d_tmp_57 (to osc_clk) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CIC1Sin/SLICE_2169: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R7C38B.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CIC1Sin/SLICE_2132: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R7C38C.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Sin/d_tmp_i0_i8 (from osc_clk +) Destination: FF Data in CIC1Sin/d_d_tmp_i0_i8 (to osc_clk +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay CIC1Sin/SLICE_2144 to CIC1Sin/SLICE_2107 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path CIC1Sin/SLICE_2144 to CIC1Sin/SLICE_2107: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R11C27B.CLK to R11C27B.Q1 CIC1Sin/SLICE_2144 (from osc_clk) ROUTE 2 0.154 R11C27B.Q1 to R11C27A.M1 CIC1Sin/d_tmp_8 (to osc_clk) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CIC1Sin/SLICE_2144: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R11C27B.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CIC1Sin/SLICE_2107: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R11C27A.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Sin/d_tmp_i0_i0 (from osc_clk +) Destination: FF Data in CIC1Sin/d_d_tmp_i0_i0 (to osc_clk +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay CIC1Sin/SLICE_2140 to CIC1Sin/SLICE_2103 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path CIC1Sin/SLICE_2140 to CIC1Sin/SLICE_2103: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R12C24A.CLK to R12C24A.Q0 CIC1Sin/SLICE_2140 (from osc_clk) ROUTE 2 0.154 R12C24A.Q0 to R12C24C.M0 CIC1Sin/d_tmp_0 (to osc_clk) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CIC1Sin/SLICE_2140: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R12C24A.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CIC1Sin/SLICE_2103: Name Fanout Delay (ns) Site Resource ROUTE 999 1.443 OSC.OSC to R12C24C.CLK osc_clk -------- 1.443 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET "osc_clk" ; 10 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 2.722ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Mixer1/RFInR1_13 (from osc_clk +) Destination: Port Pad DiffOut Data Path Delay: 1.531ns (79.5% logic, 20.5% route), 2 logic levels. Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels. Constraint Details: 1.191ns delay OSCH_inst to Mixer1/SLICE_2223 and 1.531ns delay Mixer1/SLICE_2223 to DiffOut (totaling 2.722ns) meets 0.000ns hold offset OSCH_inst to DiffOut by 2.722ns Physical Path Details: Clock path OSCH_inst to Mixer1/SLICE_2223: Name Fanout Delay (ns) Site Resource ROUTE 999 1.191 OSC.OSC to R2C24A.CLK osc_clk -------- 1.191 (0.0% logic, 100.0% route), 0 logic levels. Data path Mixer1/SLICE_2223 to DiffOut: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R2C24A.CLK to R2C24A.Q1 Mixer1/SLICE_2223 (from osc_clk) ROUTE 2 0.314 R2C24A.Q1 to 122.PADDO DiffOut_c DOPAD_DEL --- 1.084 122.PADDO to 122.PAD DiffOut -------- 1.531 (79.5% logic, 20.5% route), 2 logic levels. Passed: The following path meets requirements by 2.840ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Sin/d_out_i0_i6 (from osc_clk +) Destination: Port Pad MYLED[0] Data Path Delay: 1.649ns (65.9% logic, 34.1% route), 2 logic levels. Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels. Constraint Details: 1.191ns delay OSCH_inst to CIC1Sin/SLICE_2218 and 1.649ns delay CIC1Sin/SLICE_2218 to MYLED[0] (totaling 2.840ns) meets 0.000ns hold offset OSCH_inst to MYLED[0] by 2.840ns Physical Path Details: Clock path OSCH_inst to CIC1Sin/SLICE_2218: Name Fanout Delay (ns) Site Resource ROUTE 999 1.191 OSC.OSC to R8C28D.CLK osc_clk -------- 1.191 (0.0% logic, 100.0% route), 0 logic levels. Data path CIC1Sin/SLICE_2218 to MYLED[0]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C28D.CLK to R8C28D.Q0 CIC1Sin/SLICE_2218 (from osc_clk) ROUTE 2 0.563 R8C28D.Q0 to 97.PADDO MYLED_c_0 DOPAD_DEL --- 0.953 97.PADDO to 97.PAD MYLED[0] -------- 1.649 (65.9% logic, 34.1% route), 2 logic levels. Passed: The following path meets requirements by 2.875ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Sin/d_out_i0_i8 (from osc_clk +) Destination: Port Pad MYLED[2] Data Path Delay: 1.684ns (64.5% logic, 35.5% route), 2 logic levels. Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels. Constraint Details: 1.191ns delay OSCH_inst to CIC1Sin/SLICE_2219 and 1.684ns delay CIC1Sin/SLICE_2219 to MYLED[2] (totaling 2.875ns) meets 0.000ns hold offset OSCH_inst to MYLED[2] by 2.875ns Physical Path Details: Clock path OSCH_inst to CIC1Sin/SLICE_2219: Name Fanout Delay (ns) Site Resource ROUTE 999 1.191 OSC.OSC to R8C29D.CLK osc_clk -------- 1.191 (0.0% logic, 100.0% route), 0 logic levels. Data path CIC1Sin/SLICE_2219 to MYLED[2]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C29D.CLK to R8C29D.Q0 CIC1Sin/SLICE_2219 (from osc_clk) ROUTE 2 0.598 R8C29D.Q0 to 99.PADDO MYLED_c_2 DOPAD_DEL --- 0.953 99.PADDO to 99.PAD MYLED[2] -------- 1.684 (64.5% logic, 35.5% route), 2 logic levels. Passed: The following path meets requirements by 2.940ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Sin/d_out_i0_i7 (from osc_clk +) Destination: Port Pad MYLED[1] Data Path Delay: 1.749ns (62.1% logic, 37.9% route), 2 logic levels. Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels. Constraint Details: 1.191ns delay OSCH_inst to CIC1Sin/SLICE_2218 and 1.749ns delay CIC1Sin/SLICE_2218 to MYLED[1] (totaling 2.940ns) meets 0.000ns hold offset OSCH_inst to MYLED[1] by 2.940ns Physical Path Details: Clock path OSCH_inst to CIC1Sin/SLICE_2218: Name Fanout Delay (ns) Site Resource ROUTE 999 1.191 OSC.OSC to R8C28D.CLK osc_clk -------- 1.191 (0.0% logic, 100.0% route), 0 logic levels. Data path CIC1Sin/SLICE_2218 to MYLED[1]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C28D.CLK to R8C28D.Q1 CIC1Sin/SLICE_2218 (from osc_clk) ROUTE 2 0.663 R8C28D.Q1 to 98.PADDO MYLED_c_1 DOPAD_DEL --- 0.953 98.PADDO to 98.PAD MYLED[1] -------- 1.749 (62.1% logic, 37.9% route), 2 logic levels. Passed: The following path meets requirements by 2.956ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Sin/d_out_i0_i9 (from osc_clk +) Destination: Port Pad MYLED[3] Data Path Delay: 1.765ns (61.5% logic, 38.5% route), 2 logic levels. Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels. Constraint Details: 1.191ns delay OSCH_inst to CIC1Sin/SLICE_2219 and 1.765ns delay CIC1Sin/SLICE_2219 to MYLED[3] (totaling 2.956ns) meets 0.000ns hold offset OSCH_inst to MYLED[3] by 2.956ns Physical Path Details: Clock path OSCH_inst to CIC1Sin/SLICE_2219: Name Fanout Delay (ns) Site Resource ROUTE 999 1.191 OSC.OSC to R8C29D.CLK osc_clk -------- 1.191 (0.0% logic, 100.0% route), 0 logic levels. Data path CIC1Sin/SLICE_2219 to MYLED[3]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C29D.CLK to R8C29D.Q1 CIC1Sin/SLICE_2219 (from osc_clk) ROUTE 2 0.679 R8C29D.Q1 to 100.PADDO MYLED_c_3 DOPAD_DEL --- 0.953 100.PADDO to 100.PAD MYLED[3] -------- 1.765 (61.5% logic, 38.5% route), 2 logic levels. Passed: The following path meets requirements by 2.986ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Sin/d_out_i0_i10 (from osc_clk +) Destination: Port Pad MYLED[4] Data Path Delay: 1.795ns (60.5% logic, 39.5% route), 2 logic levels. Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels. Constraint Details: 1.191ns delay OSCH_inst to CIC1Sin/SLICE_2220 and 1.795ns delay CIC1Sin/SLICE_2220 to MYLED[4] (totaling 2.986ns) meets 0.000ns hold offset OSCH_inst to MYLED[4] by 2.986ns Physical Path Details: Clock path OSCH_inst to CIC1Sin/SLICE_2220: Name Fanout Delay (ns) Site Resource ROUTE 999 1.191 OSC.OSC to R8C29B.CLK osc_clk -------- 1.191 (0.0% logic, 100.0% route), 0 logic levels. Data path CIC1Sin/SLICE_2220 to MYLED[4]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C29B.CLK to R8C29B.Q0 CIC1Sin/SLICE_2220 (from osc_clk) ROUTE 2 0.709 R8C29B.Q0 to 104.PADDO MYLED_c_4 DOPAD_DEL --- 0.953 104.PADDO to 104.PAD MYLED[4] -------- 1.795 (60.5% logic, 39.5% route), 2 logic levels. Passed: The following path meets requirements by 2.986ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CIC1Sin/d_out_i0_i11 (from osc_clk +) Destination: Port Pad MYLED[5] Data Path Delay: 1.795ns (60.5% logic, 39.5% route), 2 logic levels. Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels. Constraint Details: 1.191ns delay OSCH_inst to CIC1Sin/SLICE_2221 and 1.795ns delay CIC1Sin/SLICE_2221 to MYLED[5] (totaling 2.986ns) meets 0.000ns hold offset OSCH_inst to MYLED[5] by 2.986ns Physical Path Details: Clock path OSCH_inst to CIC1Sin/SLICE_2221: Name Fanout Delay (ns) Site Resource ROUTE 999 1.191 OSC.OSC to R8C29A.CLK osc_clk -------- 1.191 (0.0% logic, 100.0% route), 0 logic levels. Data path CIC1Sin/SLICE_2221 to MYLED[5]: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C29A.CLK to R8C29A.Q0 CIC1Sin/SLICE_2221 (from osc_clk) ROUTE 2 0.709 R8C29A.Q0 to 105.PADDO MYLED_c_5 DOPAD_DEL --- 0.953 105.PADDO to 105.PAD MYLED[5] -------- 1.795 (60.5% logic, 39.5% route), 2 logic levels. Passed: The following path meets requirements by 3.273ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ncoGen/phase_accum_i63 (from osc_clk +) Destination: Port Pad sinGen Data Path Delay: 2.082ns (63.3% logic, 36.7% route), 3 logic levels. Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels. Constraint Details: 1.191ns delay OSCH_inst to ncoGen/SLICE_725 and 2.082ns delay ncoGen/SLICE_725 to sinGen (totaling 3.273ns) meets 0.000ns hold offset OSCH_inst to sinGen by 3.273ns Physical Path Details: Clock path OSCH_inst to ncoGen/SLICE_725: Name Fanout Delay (ns) Site Resource ROUTE 999 1.191 OSC.OSC to R12C10D.CLK osc_clk -------- 1.191 (0.0% logic, 100.0% route), 0 logic levels. Data path ncoGen/SLICE_725 to sinGen: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R12C10D.CLK to R12C10D.Q1 ncoGen/SLICE_725 (from osc_clk) ROUTE 3 0.452 R12C10D.Q1 to R2C10B.A0 phase_accum_63 CTOF_DEL --- 0.101 R2C10B.A0 to R2C10B.F0 ncoGen/SLICE_2510 ROUTE 1 0.312 R2C10B.F0 to 142.PADDO sinGen_c DOPAD_DEL --- 1.084 142.PADDO to 142.PAD sinGen -------- 2.082 (63.3% logic, 36.7% route), 3 logic levels. Passed: The following path meets requirements by 3.415ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q PWM1/PWMOut_15 (from osc_clk +) Destination: Port Pad PWMOut Data Path Delay: 2.224ns (54.7% logic, 45.3% route), 2 logic levels. Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels. Constraint Details: 1.191ns delay OSCH_inst to PWM1/SLICE_6 and 2.224ns delay PWM1/SLICE_6 to PWMOut (totaling 3.415ns) meets 0.000ns hold offset OSCH_inst to PWMOut by 3.415ns Physical Path Details: Clock path OSCH_inst to PWM1/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 999 1.191 OSC.OSC to R3C14B.CLK osc_clk -------- 1.191 (0.0% logic, 100.0% route), 0 logic levels. Data path PWM1/SLICE_6 to PWMOut: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk) ROUTE 6 1.007 R3C14B.Q1 to 43.PADDO PWMOutP4_c DOPAD_DEL --- 1.084 43.PADDO to 43.PAD PWMOut -------- 2.224 (54.7% logic, 45.3% route), 2 logic levels. Passed: The following path meets requirements by 3.706ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q PWM1/PWMOut_15 (from osc_clk +) Destination: Port Pad PWMOutP1 Data Path Delay: 2.515ns (48.4% logic, 51.6% route), 2 logic levels. Clock Path Delay: 1.191ns (0.0% logic, 100.0% route), 0 logic levels. Constraint Details: 1.191ns delay OSCH_inst to PWM1/SLICE_6 and 2.515ns delay PWM1/SLICE_6 to PWMOutP1 (totaling 3.706ns) meets 0.000ns hold offset OSCH_inst to PWMOutP1 by 3.706ns Physical Path Details: Clock path OSCH_inst to PWM1/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 999 1.191 OSC.OSC to R3C14B.CLK osc_clk -------- 1.191 (0.0% logic, 100.0% route), 0 logic levels. Data path PWM1/SLICE_6 to PWMOutP1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R3C14B.CLK to R3C14B.Q1 PWM1/SLICE_6 (from osc_clk) ROUTE 6 1.298 R3C14B.Q1 to 61.PADDO PWMOutP4_c DOPAD_DEL --- 1.084 61.PADDO to 61.PAD PWMOutP1 -------- 2.515 (48.4% logic, 51.6% route), 2 logic levels. Report: 2.722ns is the maximum offset for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "osc_clk" 88.670000 MHz ; | 0.000 ns| 0.306 ns| 1 | | | CLOCK_TO_OUT ALLPORTS 20.000000 ns | | | CLKNET "osc_clk" ; | 0.000 ns| 2.722 ns| 2 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 3 clocks: Clock Domain: uart_rx1/UartClk[2] Source: uart_rx1/SLICE_12.Q1 Loads: 29 No transfer within this clock domain is found Clock Domain: osc_clk Source: OSCH_inst.OSC Loads: 1367 Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ; Data transfers from: Clock Domain: uart_rx1/UartClk[2] Source: uart_rx1/SLICE_12.Q1 Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ; Transfers: 9 Clock Domain: CIC1_out_clkSin Source: CIC1Sin/SLICE_2197.Q0 Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ; Transfers: 10 Clock Domain: CIC1_out_clkSin Source: CIC1Sin/SLICE_2197.Q0 Loads: 153 No transfer within this clock domain is found Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1466977 paths, 1 nets, and 16496 connections (99.99% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 10 (setup), 0 (hold) Score: 30054 (setup), 0 (hold) Cumulative negative slack: 30054 (30054+0)