You may see D FF symbols with two additional inputs ¾ CLR (clear) and PR (preset). These inputs are used to set the start condition of the FF ¾ CLR sets Q to 0; PR sets Q to 1. Figure 3-17 shows the standard symbol with the CLR and PR inputs. Since these inputs are preceded by inverters (part of the FF), a LOW-going signal is necessary to activate the FF. These signals (CLR and PR) override any existing condition of the output.
3-17
You may also see an inverter at the clock input. In this case, the output will change on the negative- going transition of the clock pulse.
Q24. What are the inputs to a D FF? Q25. How long is data delayed by a D FF? Q26. What condition must occur to have a change in the output of a D FF?
The J-K FF is the most widely used FF because of its versatility. When properly used it may perform the function of an R-S, T, or D FF. The standard symbol for the J-K FF is shown in view A of figure 3-18.
3-18
The J-K is a five-input device. The J and K inputs are for data. The CLK input is for the clock; and the PS and CLR inputs are the preset and clear inputs, respectively. The outputs Q and Q are the normal complementary outputs.
Observe the Truth Table and timing diagram in figure 3-18, views B and C, as the circuit is explained.
3-19
Line 1 of the Truth Table corresponds to T0 in the timing diagram. The PS and CLR inputs are both LOW. The CLK, J, and K inputs are irrelevant. At this point the FF is jammed, and both Q and Q are HIGH. As with the R-S FF, this state cannot be used.
At T1, PS remains LOW while CLR goes HIGH. The Q output remains HIGH and Q goes LOW. The FF is in the PRESET condition (line 2 of the Truth Table).
At T2, PS goes HIGH, CLR goes LOW, Q goes LOW, and Q goes HIGH. At this point the FF is CLEARED (line 3 of the Truth Table). The condition of the CLK, J, and K inputs have no effect on the PS and CLR actions since these inputs override the other inputs. Starting at T3, PS and CLR will be held at HIGHs so as not to override the other actions of the FF. Using the PS and CLR inputs only, the circuit will function as an R-S FF.
Between T2 and T3, the CLK input is applied to the device. Since the CLK input has an inverter, all actions will take place on the negative-going transition of the clock pulse.
Line 4 of the Truth Table shows both PS and CLR HIGH, a negative-going CLK, and J and K at 0, or LOW. This corresponds to T3 on the timing diagram. In this condition the FF holds the previous condition of the output. In this case the FF is reset. If the circuit were set when these inputs occurred, it would remain set.
At time T5, we have a negative-going clock pulse and a HIGH on the J input. This causes the circuit to set, Q to go HIGH, and Q to go LOW. See line 5 of the Truth Table.
At T6, J goes LOW, K goes HIGH, and the clock is in a positive-going transition. There is no change in the output because all actions take place on the negative clock transition.
At T7, when J is LOW, K is HIGH; the clock is going negative, the FF resets, Q goes LOW, and Q goes HIGH (line 6).
With both J and K HIGH and a negative-going clock (as at T9 and line 7), the FF will toggle or change state with each clock pulse. It will continue to toggle as long as J and K both remain HIGH.
Line 8 of the Truth Table indicates that as long as the clock is in any condition other than a negative- going transition, there will be no change in the output regardless of the state of J or K.
As mentioned at the beginning of this section, J-K FFs may be used as R-S, T, or D FFs.
Figure 3-19 shows how a J-K can be made to perform the other functions.
3-20
In view A, using just the PS and CLR inputs of the J-K will cause it to react like an R-S FF. In view B, data is applied to the J input. This same data is applied to the K input through an inverter
to ensure that the K input is in the opposite state. In this configuration, the J-K performs the same function as a D FF.
View C shows both the J and K inputs held at 1, or HIGH. The FF will change state or toggle with each negative-going transition of the clock just as a T FF will.
Now you can see the versatility of the J-K FF.
Q27. What type of FF can be used as an R-S, a T, or a D FF? Q28. What will be the output of Q if J is HIGH, PS and CLR are HIGH, and the clock is going
negative?
Q29. Assume that K goes HIGH and J goes LOW; when will the FF reset? Q30. What logic levels must exist for the FF to be toggled by the clock? Q31. What two inputs to a J-K FF will override the other inputs? Q32. How is the J-K FF affected if PS and CLR are both LOW?
3-21
Clocks and counters are found in all types of digital equipment. Although they provide different functions, they are all constructed of circuits with which you are familiar. By changing the way the circuits are interconnected, we can build timing circuits, multipliers and dividers, and storage units. In this section we will discuss the purpose, construction, and operation of these important digital circuits.
Clocks have been mentioned in the preceding section with regard to their action with FFs. You will recall that the clock is a timing signal generated by the equipment to control operations. This control feature is demonstrated in both the D and J-K FFs. Remember that the clock output had to be in a certain condition for the FFs to perform their functions.
The simplest form of a clock is the astable or free-running multivibrator. A schematic diagram of a typical free-running multivibrator is shown in figure 3-20 along with its output waveforms. This multivibrator circuit is called free running because it alternates between two different output voltages during the time it is active. Outputs 1 and 2 will be equal and opposite since Q1 and Q2 conduct alternately. The frequency of the outputs may be altered within certain limits by varying the values of R2C1 and R3C2. You may want to review the operation of the astable multivibrator in NEETS, Module 9, Introduction to Wave-Generation and Wave-Shaping Circuits. Although the astable multivibrator circuit seems to produce a good, balanced square wave, it lacks the frequency stability necessary for some types of equipment.
The frequency stability of the astable multivibrator can be increased by applying a trigger pulse to the circuit. The frequency of the trigger must be higher than the free-running frequency of the multivibrator. The output frequency will match the trigger frequency and produce a more stable output.
3-22
Another method of producing a stable clock pulse is to use a triggered monostable or one-shot multivibrator. You will recall from NEETS, Module 9, that a one-shot multivibrator has one stable state and will only change states when acted on by an outside source (the trigger). A block diagram of a monostable multivibrator with input and output signals is shown in figure 3-21. The duration of the output pulse is dependent on the charge time of an RC network in the multivibrator. Each trigger input results in a complete cycle in the output, as shown in figure 3-21. Trigger pulses are supplied by an oscillator.
The circuits described previously are very simple clocks. However, as the complexity of the system increases, so do the timing requirements. Complex systems have multiphase clocks to control a variety of operations. Multiphase clocks allow functions involving more than one operation to be completed during a single clock cycle. They also permit an operation to extend over more than one clock cycle.
A block diagram of a two-phase clock system is shown in figure 3-22, view A. The astable multivibrator provides the basic timing for the circuit, while the one-shot multivibrators are used to shape the pulses. Outputs Q and Q are input to one-shot multivibrators 1 and 2, respectively. The resulting outputs are in phase with the inputs, but the duration of the pulse is greatly reduced as shown in view B.
3-23
Clocks are designed to provide the most efficient operation of the equipment. During the design phase, the frequency, pulse width, and the number of phases required is determined; and the clock circuit is built to meet those requirements.
Most modern high-speed equipment uses crystal-controlled oscillators as the basis for their timing networks. Crystals are stable even at extremely high frequencies.
Q33. What is a clock with regard to digital equipment? Q34. What is the simplest type of clock circuit? Q35. What is needed to use a monostable or one-shot multivibrator for a clock circuit? Q36. What type of clock is used when more than one operation is to be completed during one clock
cycle?
A counter is simply a device that counts. Counters may be used to count operations, quantities, or periods of time. They may also be used for dividing frequencies, for addressing information in storage, or for temporary storage.
Counters are a series of FFs wired together to perform the type of counting desired. They will count up or down by ones, twos, or more.
The total number of counts or stable states a counter can indicate is called MODULUS. For instance, the modulus of a four-stage counter would be 1610, since it is capable of indicating 00002 to 11112. The term modulo is used to describe the count capability of counters; that is, modulo-16 for a four-stage binary counter, modulo-11 for a decade counter, modulo-8 for a three-stage binary counter, and so forth.
Ripple counters are so named because the count is like a chain reaction that ripples through the counter because of the time involved. This effect will become more evident with the explanation of the following circuit.
Figure 3-23, view A, shows a basic four-stage, or modulo-16, ripple counter. The inputs and outputs are shown in view B. The four J-K FFs are connected to perform a toggle function; which, you will recall, divides the input by 2. The HIGHs on the J and K inputs enable the FFs to toggle. The inverters on the clock inputs indicate that the FFs change state on the negative-going pulse.
3-24
Assume that A, B, C, and D are lamps and that all the FFs are reset. The lamps will all be out, and the count indicated will be 00002. The negative-going pulse of clock pulse 1 causes FF1 to set. This lights lamp A, and we have a count of 00012. The negative-going pulse of clock pulse 2 toggles FF1, causing it to reset. This negative-going input to FF2 causes it to set and causes B to light. The count after two clock pulses is 00102, or 210. Clock pulse 3 causes FF1 to set and lights lamp A. The setting of FF1 does not affect FF2, and lamp B stays lit. After three clock pulses, the indicated count is 00112.
Clock pulse 4 causes FF1 to reset, which causes FF2 to reset, which causes FF3 to set, giving us a count of 01002. This step shows the ripple effect.
This setting and resetting of the FFs will continue until all the FFs are set and all the lamps are lit. At that time the count will be 11112 or 1510. Clock pulse 16 will cause FF1 to reset and lamp A to go out. This will cause FF2 through FF4 to reset, in order, and will extinguish lamps B, C, and D. The counter would then start at 00012 on clock pulse 17. To display a count of 1610 or 100002, we would need to add another FF.
The ripple counter is also called an ASYNCHRONOUS counter. Asynchronous means that the events (setting and resetting of FFs) occur one after the other rather than all at once. Because the ripple count is asynchronous, it can produce erroneous indications when the clock speed is high. A high-speed clock can cause the lower stage FFs to change state before the upper stages have reacted to the previous clock pulse. The errors are produced by the FFs’ inability to keep up with the clock.
3-25
High-frequency operations require that all the FFs of a counter be triggered at the same time to prevent errors. We use a SYNCHRONOUS counter for this type of operation.
The synchronous counter is similar to a ripple counter with two exceptions: The clock pulses are applied to each FF, and additional gates are added to ensure that the FFs toggle in the proper sequence.
A logic diagram of a three-state (modulo-8) synchronous counter is shown in figure 3-24, view A. The clock input is wired to each of the FFs to prevent possible errors in the count. A HIGH is wired to the J and K inputs of FF1 to make the FF toggle. The output of FF1 is wired to the J and K inputs of FF2, one input of the AND gate, and indicator A. The output of FF2 is wired to the other input of the AND gate and indicator B. The AND output is connected to the J and K inputs of FF3. The C indicator is the only output of FF3.
During the explanation of this circuit, you should follow the logic diagram, view A, and the pulse sequences, view B.
Assume the following initial conditions: The outputs of all FFs, the clock, and the AND gate are 0; the J and K inputs to FF1 are HIGH. The negative-going portion of the clock pulse will be used throughout the explanation.
Clock pulse 1 causes FF1 to set. This HIGH lights lamp A, indicating a binary count of 001. The HIGH is also applied to the J and K inputs of FF2 and one input of the AND gate. Notice that FF2 and
3-26
FF3 are unaffected by the first clock pulse because the J and K inputs were LOW when the clock pulse was applied.
As clock pulse 2 goes LOW, FF1 resets, turning off lamp A. In turn, FF2 will set, lighting lamp B and showing a count of 0102. The HIGH from FF2 is also felt by the AND gate. The AND gate is not activated at this time because the signal from FF1 is now a LOW. A LOW is present on the J and K inputs of FF3, so it is not toggled by the clock.
Clock pulse 3 toggles FF1 again and lights lamp A. Since the J and K inputs to FF2 were LOW when pulse 3 occurred, FF2 does not toggle but remains set. Lamps A and B are lit, indicating a count of 0112. With both FF1 and FF2 set, HIGHs are input to both inputs of the AND gate, resulting in HIGHs to J and K of FF3. No change occurred in the output of FF3 on clock pulse 3 because the J and K inputs were LOW at the time.
Just before clock pulse 4 occurs, we have the following conditions: FF1 and FF2 are set, and the AND gate is outputting a HIGH to the J and K inputs of FF3. With these conditions all of the FFs will toggle with the next clock pulse.
At clock pulse 4, FF1 and FF2 are reset, and FF3 sets. The output of the AND gate goes to 0, and we have a count of 1002.
It appears that the clock pulse and the AND output both go to 0 at the same time, but the clock pulse arrives at FF3 before the AND gate goes LOW because of the transit time of the signal through FF1, FF2, and the AND gate.
Between pulses 4 and 8, FF3 remains set because the J and K inputs are LOW. FF1 and FF2 toggle in the same sequence as they did on clock pulses 1, 2, and 3.
Clock pulse 7 results in all of the FFs being set and the AND gate output being HIGH. Clock pulse 8 causes all the FFs to reset and all the lamps to turn off, indicating a count of 0002 . The next clock pulse (9) will restart the count sequence.
Q37. What is the modulus of a five-stage binary counter? Q38. An asynchronous counter is also called a ___________ counter. Q39. J-K FFs used in counters are wired to perform what function? Q40. What type of counter has clock pulses applied to all FFs? Q41. In figure 3-24, view A, what logic element enables FF3 to toggle with the clock? Q42. What is the largest count that can be indicated by a four-stage counter?
A decade counter is a binary counter that is designed to count to 1010, or 10102. An ordinary four- stage counter can be easily modified to a decade counter by adding a NAND gate as shown in figure 3-25. Notice that FF2 and FF4 provide the inputs to the NAND gate. The NAND gate outputs are connected to the CLR input of each of the FFs.
3-27
The counter operates as a normal counter until it reaches a count of 10102, or 1010. At that time, both inputs to the NAND gate are HIGH, and the output goes LOW. This LOW applied to the CLR input of the FFs causes them to reset to 0. Remember from the discussion of J-K FFs that CLR and PS or PR override any existing condition of the FF. Once the FFs are reset, the count may begin again. The following table shows the binary count and the inputs and outputs of the NAND gate for each count of the decade counter:
Changing the inputs to the NAND gate can cause the maximum count to be changed. For instance, if FF4 and FF3 were wired to the NAND gate, the counter would count to 11002 (1210), and then reset.
Q43. How many stages are required for a decade counter? Q44. In figure 3-25, which two FFs must be HIGH to reset the counter?
A ring counter is defined as a loop of bistable devices (flip-flops) interconnected in such a manner that only one of the devices may be in a specified state at one time. If the specified condition is HIGH,
3-28
then only one device may be HIGH at one time. As the clock, or input, signal is received, the specified state will shift to the next device at a rate of 1 shift per clock, or input, pulse.
Figure 3-26, view A, shows a typical four-stage ring counter. This particular counter is composed of R-S FFs. J-K FFs may be used as well. Notice that the output of each AND gate is input to the R, or reset side, of the nearest FF and to the S, or set side, of the next FF. The Q output of each FF is applied to the B input of the AND gate that is connected to its own R input.
The circuit input may be normal CLK pulses or pulses from elsewhere in the equipment that would indicate some operation has been completed.
Now, let’s look at the circuit operation and observe the signal flow as shown in figure 3-26, view B.
For an initial condition, let’s assume that the output of FF1 is HIGH and that the input and FF2, FF3, and FF4 are LOW. Under these conditions, lamp A will be lit; and lamps B, C, and D will be extinguished. The HIGH from FF1 is also applied to the B input of AND gate 1.
The first input pulse is applied to the A input of each of the AND gates. The B inputs to AND gates 2, 3, and 4 are LOW since the outputs of FF2, FF3, and FF4 are LOW. AND gate 1 now has HIGHs on both inputs and produces a HIGH output. This HIGH simultaneously resets FF1 and sets FF2. Lamp A then goes out, and lamp B goes on. We now have a HIGH on AND gate 2 at the B input. We also have a LOW on AND gate 1 at input B.
3-29
Input pulse 2 will produce a HIGH output from AND gate 2 since AND gate 2 is the only one with HIGHs on both inputs. The HIGH from AND gate 2 causes FF2 to reset and FF3 to set. Indicator B goes out and C goes on.
Pulse 3 will cause AND gate 3 to go HIGH. This results in FF3 being reset and FF4 being set. Pulse 4 causes FF4 to reset and FF1 to set, bringing the counter full circle to the initial conditions. As long as the counter is operational, it will continue to light the lamps in sequence ¾ 1, 2, 3, 4; 1, 2, 3, 4, etc.
As we stated at the beginning of this section, only one FF may be in the specified condition at one time. The specified condition shifts one position with each input pulse.
Q45. In figure 3-26, view A, which AND gate causes FF3 to set? Q46. Which AND gate causes FF3 to reset? Q47. What causes the specified condition to shift position? Q48. If the specified state is OFF, how many FFs may be off at one time?
Up to this point the counters that you have learned about have been up counters (with the exception of the ring counter). An up counter starts at 0 and counts to a given number. This section will discuss DOWN counters, which start at a given number and count down to 0.
Up counters are sometimes called INCREMENT counters. Increment means to increase. Down counters are called DECREMENT counters. Decrement means to decrease.
A three-stage, ripple down counter is shown in figure 3-27, view A. Notice that the PS (preset) input of the J-K FFs is used in this circuit. HIGHs are applied to all the J and K inputs. This enables the FFs to toggle on the input pulses.
3-30
A negative-going pulse is applied to all PS terminals to start the countdown. This causes all the FFs to set and also lights indicators A, B, and C. The beginning count is 1112 (710). At the same time, LOWs are applied to the CLK inputs of FF2 and FF3, but they do not toggle because the PS overrides any change. All actions in the counter will take place on the negative-going portion of the input pulse. Let’s go through the pulse sequences in figure 3-27, view B.
CP1 causes FF1 to toggle and output Q to go LOW.  Notice that Q goes HIGH but no change occurs in FF2 or FF3. Lamps B and C are now on, A is off, and the indicated count is 1102 (610).
CP2 toggles FF1 again and lights lamp A. When Q goes HIGH, Q goes LOW. This negative-going signal causes FF2 to toggle and reset. Lamp B is turned off, and a HIGH is felt at the CLK input of FF3. The indicated count is 1012 (510); lamps A and C are on, and B is off.
At CP3, FF1 toggles and resets.  A positive-going signal is applied to the CLK input of FF2. Lamp B remains off and C remains on. The count at this point is 1002 (410).
CP4 toggles FF1 and causes it to set, lighting lamp A. Now FF1, output Q , goes LOW causing FF2 to toggle. This causes FF2 to set and lights lamp B. Output of FF2, Q , then goes LOW, which causes FF3 to reset and turn off lamp C. The indicated count is now 0112 (310).
The next pulse, CP5, turns off lamp A but leaves B on. The count is now 0102. CP6 turns on lamp A and turns off lamp B, for a count of 0012. CP7 turns off lamp A. Now all the lamps are off, and the counter indicates 000.
3-31
On the negative-going signal of CP8, all FFs are set, and all the lamps are lighted. The CLK pulse toggles FF1, making output Q go HIGH. As output Q goes LOW, the negative-going signal causes FF2 to toggle. As FF2, output Q, goes HIGH, output Q goes LOW, causing FF3 to toggle and set. As each FF sets, its indicator lamp lights. The counter is now ready to again start counting down from 1112 with the next CLK pulse.
Q49. How many FFs are required to count down from 1510? Q50. What signal causes FF2 to toggle?
A register is a temporary storage device. Registers are used to store data, memory addresses, and operation codes. Registers are normally referred to by the number of stages they contain or by the number of bits they will store. For instance, an eight-stage register would be called an 8-bit register. The contents of the register is also called a WORD. The contents of an 8-bit register is an 8-bit word. The contents of a 4-bit register is a 4-bit word and so forth.
Registers are also used in the transfer of data to and from input and output devices such as teletypes, printers, and cathode-ray tubes.
Most registers are constructed of FFs and associated circuitry. They permit us to load or store data and to transfer the data at the proper time.
Parallel registers are designed to receive or transfer all bits of data or information simultaneously.
A 4-bit parallel register is shown in figure 3-28. The data inputs are A, B, C, and D. The FFs store the data until it is needed. AND gates 5, 6, 7, and 8 are the transfer gates.
3-32
Before we go through the operation of the register, let’s set some initial conditions. Assume that inputs A, B, and D are HIGH and that FF2 and FF4 are set from a previous operation. The READ IN, READ OUT, and RESET inputs are all LOW.
To begin the operation, we apply a reset pulse to the RESET input of all the FFs, clearing the Q outputs to LOWs. This step ensures against any erroneous data transfer that would occur because of the states of FF2 and FF4.
Inputs A, B, C, and D are input to gates 1, 2, 3, and 4, respectively. When the READ IN input goes HIGH, AND gates 1, 2, and 4 go HIGH, causing FF1, FF2, and FF4 to set. The output of AND gate 3 does not change since the C input is LOW. The 4-bit word, 1101, is now stored in the register. The outputs of FFs 1, 2, 3, and 4 are applied to AND gates 5, 6, 7, and 8, respectively.
When the data is required for some other operation, a positive-going pulse is applied to the READ OUT inputs of the AND gates. This HIGH, along with the HIGHs from the FFs, causes the outputs of AND gates 5, 6, and 8 to go HIGH. Since the Q output of FF3 is LOW, the output of gate 7 will be LOW. The 4-bit word, 1101, is transferred to where it is needed.
Q51. How many stages are required to store a 16-bit word? Q52. Simultaneous transfer of data may be accomplished with what type of register? Q53. How are erroneous transfers of data prevented?
A shift register is a register in which the contents may be shifted one or more places to the left or right. This type of register is capable of performing a variety of functions. It may be used for serial-to- parallel conversion and for scaling binary numbers.
Before we get into the operation of the shift register, let’s discuss serial-to-parallel conversion, parallel-to-serial conversion, and scaling.
Serial and parallel are terms used to describe the method in which data or information is moved from one place to another. SERIAL TRANSFER means that the data is moved along a single line one bit at a time. A control pulse is required to move each bit. PARALLEL TRANSFER means that each bit of data is moved on its own line and that all bits transfer simultaneously as they did in the parallel register. A single control pulse is required to move all bits.
Figure 3-29 shows how both of these transfers occur. In each case, the four-bit word 1101 is being transferred to a storage device. In view A, the data moves along a single line. Each bit of the data will be stored by an individual control pulse. In view B, each bit has a separate input line. One control pulse will cause the entire word to be stored.
3-33
Serial-to-parallel conversion or parallel-to-serial conversion describes the manner in which data is stored in a storage device and the manner in which that data is removed from the storage device.
Serial-to-parallel conversion means that data is transferred into the storage device or register in serial fashion and removed in parallel fashion, as in figure 3-30, view A. Parallel-to-serial conversion means the data is transferred into the storage device in parallel and removed as serial data, as shown in view B.
Serial transfer takes time. The longer the word length, the longer the transfer will take. Although parallel transfer is much faster, it requires more circuitry to transfer the data.
3-34
SCALING means to change the magnitude of a number. Shifting binary numbers to the left increases their value, and shifting to the right decreases their value. The increase or decrease in value is based on powers of 2.
A shift of one place to the left increases the value by a power of 2, which in effect is multiplying the number by 2. To demonstrate this, let’s assume that the following block diagram is a 5-bit shift register containing the binary number 01100.
Shifting the entire number one place to the left will put the register in the following condition:
The binary number 01100 has a decimal equivalent of 12. If we convert 110002 to decimal, we find it has a value of 2410. By shifting the number one place to the left, we have multiplied it by 2. A shift of two places to the left would be the equivalent of multiplying the number by 22, or 4; three places by 23, or 8; and so forth.
Shifting a binary number to the right decreases the value of the number by a power of 2 for each place. Let’s look at the same 5-bit register containing 011002 and shift the number to the right.
A shift of one place to the right will result in the register being in the following condition:
By comparing decimal equivalents you can see that we have decreased the value from 1210 to 610. We have effectively divided the number by 2. A shift of two places to the right is the equivalent of dividing the number by 22, or 4; three places by 23; or 8; and so forth.
3-35
Figure 3-31shows a typical 4-bit shift register. This particular register is capable of left shifts only. There are provisions for serial and parallel input and serial and parallel output. Additional circuitry would be required to make right shifts possible.
Before any operation takes place, a CLEAR pulse is applied to the RESET terminal of each FF to ensure that the Q output is LOW.
The simplest modes of operation for this register are the parallel inputs and outputs. Parallel data is applied to the SET inputs of the FFs and results in either a 1 or 0 output, depending on the input. The outputs of the FFs may be sampled for parallel output. In this mode, the register functions just like the parallel register covered earlier in this section.
Now let’s look at parallel-to-serial conversion. We will use the 4-bit shift register in figure 3-31 and the timing sequence in figure 3-32 to aid you in understanding the operations.
3-36
At CP1, a CLEAR pulse is applied to all the FFs, resetting the register to a count of 0. The number 01012 is applied to the parallel inputs at CP2, causing FF1 and FF3 to set. At this point, the J inputs of FF2 and FF4 are HIGH. AND gate 2 has a LOW output since the FF4 output is LOW. This LOW output represents the first digit of the number 01012 to be output in serial form. At the same time we have HIGHs on the K inputs of FF1 and FF3. (Notice the NOT symbol on FF1 at input K. With no serial input to AND gate 1, the output is LOW; therefore, the K input to FF1 is held HIGH). With these conditions CP3 causes FF1 and FF3 to reset and FF2 and FF4 to set. The HIGH output of FF4, along with CP3, causes AND gate 2 to output a HIGH. This represents the second digit of the number 01012.
At CP4, FF2 and FF4 reset, and FF3 sets. FF1 remains reset because of the HIGH at the K input. The output of AND gate 2 goes LOW because the output of FF4 is LOW and the third digit of the number is output on the serial line. CP5 causes FF4 to set and FF3 to reset. CP5 and the HIGH from FF4 cause AND gate 2 to output the last digit of the number on the serial line. It took a total of four CLK pulses to input the number in parallel and output it in serial.
CP6 causes FF4 to reset and effectively clears the register for the next parallel input.
Between CP7 and CP10, the number 11102 is input as parallel data and output as serial data.
Serial input is accomplished much in the same manner as serial output. Instead of shifting the data out one bit at a time, we shift the data in one bit at a time.
To understand this conversion, you should again use figure 3-31and also the timing diagram shown in figure 3-33. In this example we will convert the number 10112 from serial data to parallel data.
3-37
A CLEAR pulse resets all the FFs at CP1. At CP2, the most significant bit of the data is input to AND gate 1. This HIGH along with the clock pulse causes AND gate 1 to output a HIGH. The HIGH from the AND gate and the clock pulse applied to FF1 cause the FF to set. FFs 2, 3, and 4 are held reset. At this point, the MSD of the data has been shifted into the register.
The next bit of data is a 0. The output of AND gate 1 is LOW. Because of the inverter on the K input of FF1, the FF senses a HIGH at that input and resets. At the same time this is occurring, the HIGH on the J input of FF2 (from FF1) and the CLK cause FF2 to set. The two MSDs, 1 and 0, are now in the register.
CP4 causes FF3 to set and FF2 to reset. FF1 is set by the CLK pulse and the third bit of the number. The register now contains 01012, as a result of shifting the first three bits of data.
The remaining bit is shifted into the register by CP5. FF1 remains set, FF2 sets, FF3 resets, and FF4 sets. At this point, the serial transfer is complete. The binary word can be sampled on the parallel output lines. Once the parallel data is transferred, a CLEAR pulse resets the FFs (CP6), and the register is ready to input the next word.
Using the shift register shown in figure 3-31 for scaling a number is quite simple. The number to be scaled is loaded into the register either in serial or parallel form. Once the data is in the register, the scaling takes place in the same manner as that for shifting the data for serial output. A single clock pulse will cause each bit of data to shift one place to the left. Remember that each shift is the equivalent of increasing the value by a power of 2. The scaled data is read from the parallel outputs. Care must be taken not to over shift the data to the point that the MSDs are shifted out of the register.
Q54. Serial-to-parallel and parallel-to-serial conversions are accomplished by what type of circuit? Q55. What type of data transfer requires the most time? Q56. What is the main disadvantage of parallel transfer? Q57. How many FFs would be required for an 8-bit shift register?
3-38
Q58. How many clock pulses are required to output a 4-bit number in serial form? Q59. Two shifts to the left are equal to increasing the magnitude of a number by how much? Q60. To increase the magnitude of a number by 23, you must shift the number how many times and in
what direction?
Logic families are groups of logic circuits that are based on particular types of elements (resistors, transistors, and so forth). Families are identified by the manner in which the elements are connected, and, in some cases, by the types of elements used.
Logic circuits of a particular family can be interconnected without having to use additional circuitry. In other words, the output of one logic circuit can be used as the input to another logic circuit. This feature is known as compatibility. All circuits within a logic family will be compatible with the other circuits within that family.
As a technician, your responsibility will be to identify defective parts and repair or replace them as required. It will be beneficial for you to have a basic knowledge of the types of logic that are used in digital equipment.
Logic circuits are usually manufactured as integrated circuits and packaged in dual-inline packages (DIP), modified transistor outlines (TO), or flat packs. These packaging techniques are described in NEETS, Module 7, Introduction to Solid-State Devices and Power Supplies.
Circuitry in a package is normally shown using standard logic symbols instead of individual components such as transistors, diodes, and so forth. Figure 3-34 shows four examples of this type of packaging. The numbered blocks (1-14 and 1-16) are the pins on the package. Circuit packages are also identified by a manufacturer’s part number. Similar circuits produced by different manufacturers will not carry the same identification numbers in all cases.
3-39
As mentioned before, logic families are identified by the elements used and the manner in which the elements are used. A brief description of some of the more common logic families follows.
RTL (RESISTOR-TRANSISTOR LOGIC) In this type of logic, inputs are applied to resistors, and the output is produced by a transistor. RTL is
normally constructed from discrete components (individual resistors and transistors). Some circuits are manufactured as integrated circuits and packaged in modified transistor outline (TO) packages, as shown in figure 3-35. An in-depth coverage of circuit packaging can be found in NEETS, Module 14, Introduction to Microelectronics.
3-40
DTL (DIODE TRANSISTOR LOGIC) Input signals are applied to diodes in this logic family. The diodes either conduct or cut off and
produce the desired output from the transistor. DTL is normally found in dual-inline packages (DIP) as well as older discrete component logic.
TTL (TRANSISTOR-TRANSISTOR LOGIC) In TTL, transistors with multiple emitters are used for the logic inputs. Additional transistors are
used to produce the desired output. TTL is normally packed in DIPs and is quite common in military equipment.
CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTORS) The CMOS logic circuits use metal oxide semiconductors similar to field-effect transistors (FETs).
The logic family used in a piece of equipment is determined by the design engineers. The type of logic used will be based on the requirements of the equipment and on what family best fulfills the requirements.
The use of integrated circuits enables designers to produce equipment that is very small and highly efficient when compared to other methods of construction. The block diagram shown in figure 3-36, view A, represents an 8-bit, serial-input and parallel-output shift register. This circuit is contained in a standard 14-pin DIP measuring about 0.75 inch long and 0.25 inch wide. View B shows this circuit package.
3-41
Q61. What are RTL, DTL, and TTL examples of? Q62. What type of logic family uses diodes in the input? Q63. What is the most common type of integrated circuit packaging found in military equipment? Q64. Circuits that can be interconnected without additional circuitry are known as ____________
circuits.
Now that you have completed this chapter, you should have a basic understanding of the more common special logic circuits. The following is a summary of the emphasized terms and points found in the "Special Logic Circuits" chapter.
SPECIAL LOGIC CIRCUITS perform arithmetic and logic operations; input, output, store and transfer information; and provide proper timing for these operations.
EXCLUSIVE OR (X-OR) circuits produce a 1 output when ONLY one input is HIGH. Can be used as a quarter adder.
3-42
EXCLUSIVE NOR (X-NOR) circuits produce a 1 output when all inputs are 0 and when more than 1 input is 1.
QUARTER ADDER circuits produce the sum of two numbers but do not generate a carry. HALF ADDER circuits produce the sum of two numbers and generate a carry.
FULL ADDER circuits add a carry to obtain the correct sum.
PARALLEL ADDER circuits use full adders connected in parallel to accommodate the addition of multiple-digit numbers.
STANDARD SYMBOLS depict logic circuitry with blocks, showing only inputs and outputs. One block may contain many types of gates and circuits.
SUBTRACTION in binary is accomplished by complementing and adding.
FLIP-FLOP are bistable multivibrators used for storage, timing, arithmetic operations, and transfer of information.
R-S FFs have the Q output of the FF HIGH in the set mode and LOW in the reset mode.
3-43
T (TOGGLE) FFS change state with each pulse applied to the input. Each T FF will divide the input by 2.
D FF is used to store data at a predetermined time.
J-K FF is the most versatile FF. J-Ks can perform the same functions as all the other FFs.
CLOCKS are circuits that generate the timing and control signals for other operations.
COUNTERS are used to count operations, quantities, or periods of time. They can be used to divide frequencies, to address information in storage, or as temporary storage.
MODULUS of a counter is the total number of counts or stable states a counter may indicate.
UP COUNTERS count from 0 to a predetermined number.
DOWN COUNTERS count from a predetermined number to 0.
RING COUNTERS are loop counters that may be used for timing operations.
REGISTERS are used as temporary storage devices as well as for transfer of information.
PARALLEL REGISTERS receive or transfer all bits of data simultaneously.
SHIFT REGISTERS are used to perform serial-to-parallel and parallel-to-serial conversion and for scaling binary numbers.
3-44
SERIAL TRANSFER causes all bits of data to be transferred on a single line.
PARALLEL TRANSFER has each data bit on its own line.
SCALING of binary numbers means to increase or decrease the magnitude of a number by a power of 2.
LOGIC FAMILIES are composed of logic circuits based on particular types of elements.
ANSWERS TO QUESTIONS Q1. THROUGH Q64. A1. ¯ .
A2. Low (0). A3. One or the other of the inputs must be HIGH, but not both at the same time. A4. Exclusive NOR (X-NOR). A5. HIGH.
A6. The half adder generates a carry. A7. Quarter adder. A8. Sum equals 0 with a carry of 1. A9. Full adder.
A10. Four.
A11. S1 = 1, S2 = 0 and C2 = 1.
A12. C1 = 0.
A13. X-OR gates.
A14. Four.
A15. MSD of the sum. A16. Add 1 portion.
A17. Subtrahend.
A18. Storing information. A19. Six.
A20. 1 and 0, or opposite states.
A21. By cross-coupling NAND or OR gates.
A22. One.
3-45
A23. To divide the input by 2.
A24. Clock and data.
A25. Up to one clock pulse.
A26. A positive-going clock pulse.
A27. J-K flip-flop. A28. Set, or HIGH (1). A29. When the clock pulse goes LOW.
A30. Both J and K must be HIGH.
A31. Clear (CLR) and preset (PS or PR). A32. The flip-flop is jammed. A33. A timing signal.
A34. An astable or free-running multivibrator. A35. Triggers.
A36. A multiphase clock.
A37. 32.
A38. Ripple.
A39. Toggle.
A40. Synchronous.
A41. The AND gate.
A42. 11112, or 1510.
A43. Four.
A44. FFs 2 and 4.
A45. Two.
A46. Three.
A47. The input, or clock pulse.
A48. One.
A49. Four.
A50. Q output of FF 1 going LOW.
3-46
A51. 16.
A52. Parallel.
A53. By clearing the register.
A54. Shift register. A55. Serial.
A56. Requires more circuitry.
A57. Eight.
A58. Four.
A59. 22, or four times. A60. Three to the left. A61. Logic families. A62. DTL (diode transistor logic). A63. DIPs (dual inline packages). A64. Compatible.
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ADDEND ¾ A number to be added to an augend.
ADDITION ¾ A form of counting where on quantity is added to another.
AND GATE ¾ A logic circuit in which all inputs must be HIGH to produce a HIGH output.
ASSOCIATIVE LAW ¾ A simple equality statement A(BC) = ABC or A+(B+C) = A+B+C.
AUGEND ¾ A number to which another number is to be added.
BASE ¾ The number of symbols used in the particular number system.
BCD (BINARY CODED DECIMAL) ¾ A method of using binary digits to represent the decimal digits 0 through 9.
BINARY SYSTEM ¾ The base 2 number system using 0 and 1 as the symbols.
BOOLEAN ALGEBRA ¾ A mathematical concept based on the assumption that most quantities have two possible conditions ¾ TRUE and FALSE.
BOOLEAN EXPRESSION ¾ A description of the input or output conditions of a logic gate.
BORROW ¾ To transfer a digit (equal to the base of the number system) from the next higher order column for the purpose of subtraction.
CARRY ¾ A carry is produced when the sum of two or more numbers in a vertical column equals or exceeds the base of the number system in use.
CLOCK ¾ A circuit that generates timing control signals in a computer or other type of digital equipment.
COMMUTATIVE LAW ¾ The order in which terms are written does not affect their value; AB = BA, A+B = B+A.
COMPATIBILITY ¾ The feature of logic families that allows interconnection of circuits without the need for additional circuitry.
COMPLEMENT ¾ Something used to complete something else.
COMPLEMENTARY LAW ¾ A term ANDed with its complement is 0, and a term ORed with its complement is 1; A A = 0, A + A = 1.
CONVERSION ¾ To change a number in one base to its equivalent in another base.
COUNTER ¾ A device that counts.
D FLIP-FLOP ¾ Stores the data bit (D) in conjunction with the clock input. DECADE COUNTER ¾ Counter from 0 to 1010 in base 2, then resets.
DECIMAL POINT ¾ The radix point for the decimal system.
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DECIMAL SYSTEM ¾ A number system with a base or radix of 10.
DEMORGAN’S THEOREM ¾ This theorem has two parts: the first states that AB = A + B ; the second states that BA + = A B .
DIFFERENCE ¾ That which is left after subtraction.

DIVIDEND ¾ A number to be divided.
DIVISOR ¾ A number by which a dividend is divided.
DOUBLE NEGATIVE LAW ¾ A term that is inverted twice is equal to the term; A = A.
DOWN COUNTER¾ A circuit that counts from a predetermined number down to 0.
EXCLUSIVE-NOR (X-NOR) ¾ A logic circuit that produces a HIGH output when all inputs are LOW or all inputs are HIGH.
EXCLUSIVE-OR (X-OR) GATE ¾ A logic circuit that produces a HIGH output when one and only one input is HIGH.
EXPONENT ¾ A number above and to the right of a base indicating the number of time the base is multiplied by itself; 24 = 2 · 2 · 2 · 2.
FLIP-FLOP ¾ A bistable multivibrator.
FRACTIONAL NUMBER ¾ A symbol to the right of the radix point that represents a portion of a complete object.
HEXADECIMAL (HEX) SYSTEM ¾ The base 16 number system using 0 through 9 and A, B, C, D, E, and F as symbols.
IDEMPOTENT LAW ¾ States that a term ANDed with itself or ORed with itself is equal to the term; AA = A, A+A = A.
INVERTER ¾ A logic gate that outputs the complement of its input.
J-K FLIP-FLOP ¾ Can perform the functions of the RS, T, and D flip-flops.
LAW OF ABSORPTION ¾ This law is the result of the application of several other laws. It states that A(A+B) = A or A+(AB) = A.
LAW OF COMMON IDENTITIES ¾ The two statements A( A +B) = AB and A+ A B = A+B are based on the complementary law.
LAW OF IDENTITY ¾ States that a term TRUE in one part of an expression will be TRUE in all parts of the expression; A = A, A = A .
LAW OF INTERSECTION ¾ A term ANDed with 1 equals that term, and a term ANDed with 0 equals 0; A·1 = A, A· 0 = 0.
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LAW OF UNION ¾ A term ORed with 1 equals 1; a term ORed with 0 equals that term; A+1 = 1, A + 0 = 0.
LEAST SIGNIFICANT (LSD) ¾ The digit which has the least effect on the value of a number.
LOGIC ¾ The science of reasoning; the development of a reasonable or logical conclusion based on known information.
LOGIC FAMILY ¾ A group of logic circuits based on specific types of circuit elements (DTL, TTL, CMOS, and so forth).
LOGIC GATES ¾ Decision-making circuits in computers and other types of equipment.
LOGIC POLARITY ¾ The polarity of a voltage used to represent the logic 1 state.
LOGIC SYMBOL ¾ Standard symbol used to indicate a particular logic function.
MINUEND ¾ The number from which another number is subtracted.
MIXED NUMBER ¾ Represents one or more complete units and a portion of a single unit.
MODULUS ¾ The number of different values that a counter can contain or display.
MOST SIGNIFICANT DIGIT (MSD) ¾ The digit which if changed will have the greatest effect on the value of a number.
NAND GATE ¾ An AND gate with an inverted output. The output is LOW when all inputs are HIGH, and HIGH when any or all inputs are LOW.
NEGATIVE LOGIC ¾ The voltage representing logic state 1 is more negative that the voltage representing a logic state 0.
NEGATOR ¾ See inverter.
NOR GATE ¾ An OR gate with an inverted output. The output is LOW when any or all inputs are HIGH, and HIGH when all inputs are LOW.
NOT CIRCUIT ¾ See inverter.
NUMBER ¾ A symbol used to represent a unit or a quantity.
OCTAL SYSTEM ¾ The base 8 number system using 0 through 7 as the symbols.
OR GATE ¾ A logic circuit which produces a HIGH output when one or more inputs is/are HIGH.
PARALLEL DATA ¾ Each bit of data has a separate line and all bits are moved simultaneously.
PARALLEL REGISTER ¾ A register that receives, stores, and transfers data in a parallel mode.
POSITIONAL NOTATION ¾ A method where the value of the number is defined by the symbol and the symbol’s position.
POSITIVE LOGIC ¾ The voltage representing logic state 1 is more positive than the voltage representing a logic state 0.
POWER OF A NUMBER ¾ The number of times a base is multiplied by itself. The power of a base is indicated by the exponent; that is, 103 = 10 · 10 · 10.
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QUOTIENT ¾ The result in division.
RADIX POINT ¾ The symbol that separates whole numbers and fractional numbers.
RADIX ¾ The total number of symbols used in a particular number system.
REGISTER ¾ A circuit of flip-flops designed to receive, store, and transfer data.
REMAINDER ¾ The final undivided part that is less than the divisor.
RING COUNTER ¾ A loop in which only one flip-flop will be set at any given time; used in timing.
RIPPLE (ASYNCHRONOUS) COUNTER ¾ A circuit that counts from 0 to a specified value. Subject to error at high frequency.
R’s (RADIX) COMPLEMENT ¾ The difference between a given number and the next higher power of the number system (10008 minus 2548 equals 5248).
R’s-1 (RADIX-1) COMPLEMENT ¾ The difference between a given number and the highest value symbol in the number system (7778 minus 2548 equals 5248).
R-S FLIP-FLOP ¾ A flip-flop with two inputs ¾ S (set) and R (reset). The Q output is HIGH in the set mode and LOW in the reset mode.
SERIAL DATA ¾ All data bits are transferred one bit at a time along a single conductor.
SHIFT REGISTER ¾ A register capable of serial-to-parallel and parallel-to-serial conversion and scaling.
SHIFTING ¾ Moving the contents of a register right or left to scale the number or to input or output serial data.
SUBSCRIPT ¾ A number written below and to the right of a value indicating the base or radix of the number system in use (358).
SUBTRACTION ¾ Taking away one number from another.
SUBTRAHEND ¾ The quantity to be subtracted from the minuend.
SUM ¾ The result in addition.
SYNCHRONOUS COUNTER ¾ Performs the same function as a ripple counter but error free at high frequency.
T FLIP-FLOP ¾ A single input flip-flop that changes state with each positive pulse or each negative pulse. Divides input frequency by two.
TRUTH TABLE ¾ A chart showing all possible input combinations and the resultant outputs.
UNIT ¾ A single object. UP/DOWN COUNTER ¾ A counter circuit that can count up or down on command.
VINCULUM ¾ A bar over a logic statement indicating the FALSE condition of the statement.
WHOLE NUMBER ¾ A symbol that represents one or more complete objects. ZERO ¾ A symbol that indicates no numerical value for a position in positional notation.
INDEX-1
INDEX-2
INDEX-3
Information: The text pages that you are to study are provided at the beginning of the assignment questions.
1
Textbook Assignment: "Number Systems," chapter 1, pages 1-1 through 1-69. _________________________________________________________________________________
1-1. Modern number systems are built around which of the following components?
1. Unit, number, and radix 2. Number, base, and radix 3. Position, power, and unit 4. Digit, power, and position
1-2. What term describes a single object in a modern number system?
1. Unit 2. Base 3. Digit 4. Number
1-3. What is a number?
1. A quantity of objects 2. A counting system based on symbols 3. The decimal system 4. A symbol representing a unit or a
1-4. Which of the following symbols is NOT an Arabic figure?
1. C 2. 2 3. 7 4. 9
1-5. What term describes the number of symbols used in a number system?
1. Power 2. Radix 3. Exponent 4. Subscript
1-6. What is the base of a number system using all the letters of the alphabet ¾ A=0, B=1, C=2, and so forth?
1. 29 2. 25 3. 28 4. 26
1-7. A number system uses the symbols 0 through 4. What is its base?
1. 6 2. 5 3. 3 4. 4
1-8. Using positional notation, what two factors determine the value of a number?
1. Symbol and position 2. Position and base 3. Radix and symbol 4. Unit and symbol
1-9. How many decimal units are represented by the 5 in the number 157210?
1. 100 2. 50 3. 500 4. 5000
1-10. The 1 in 157210 is equal to what power of ten?
1. 101 2. 102 3. 103 4. 104
2
1-11. The power of a number is indicated by the
1. subscript 2. exponent 3. radical 4. radix
1-12. What is the value of 5 times 100?
1. 1 2. 0.5 3. 5 4. 50
1-13. Which of the following numbers is a mixed number?
1. 14.03 2. 156 3. 1,257 4. .0004
1-14. What term describes the symbol that separates the whole and fractional numbers in any number system?
1. Exponent 2. Radix point 3. Decimal point 4. Position point
1-15. What is the MSD of (a) 0.4201, (b) 13, and (c) 32.06?
1. (a) 4 (b) 1 (c) 3 2. (a) 1 (b) 3 (c) 2 3. (a) 2 (b) 1 (c) 2 4. (a) 4 (b) 3 (c) 3
1-16. What term is defined as a number to be added to a preceding number?
1. Addend 2. Augend 3. Carry 4. Sum
1-17. Identify A through D in the following example.
1. Addend, sum, carry, augend 2. Carry, augend, addend, sum 3. Augend, carry, sum, addend 4. Carry, augend, sum, addend
IN ANSWERING QUESTION 1-18, PERFORM THE INDICATED OPERATION.
1-18. Add:
1. 418 2. 508 3. 528 4. 518
1-19. In subtraction, the (a) is subtracted from the (b).
1. (a) Minuend (b) subtrahend 2. (a) Remainder (b) subtrahend 3. (a) Subtrahend (b) difference 4. (a) Subtrahend (b) minuend
1-20. A borrow is required in which of the following examples?
1.
2.
3.
4.
3
1-21. The result of subtraction is known as the
1. addend 2. quotient 3. difference 4. subtrahend
1-22. What are the (a) radix and (b) the symbols used in the binary number system?
1. (a) 1 (b) 0, 1 2. (a) 2 (b) 1, 0 3. (a) 3 (b) 0, 1, 2 4. (a) 0 (b) 1, 2
1-23. Positional notation for the binary system is based on powers of
1. 1 2. 2 3. 3 4. 0
1-24. What is the decimal equivalent of 23?
1. 6 2. 2 3. 8 4. 10
1-25. The decimal number 1 is equal to what power of two?
1. 21 2. 22 3. 23 4. 20
1-26. Which of the following powers of two indicates a fraction?
1. 21 2. 20 3. 2 - 2 4. 22
1-27. Which digit is the MSD in the binary number 1011001?
1. The 0 farthest to the left 2. The 1 farthest to the left 3. The 0 farthest to the right 4. The 1 farthest to the right
1-28. Which of the following combinations of binary addition is INCORRECT?
1. 1 + 1 = 1 with a carry 2. 1 + 0 = 1 3. 0 + 0 = 0 4. 0 + 1 = 1
IN ANSWERING QUESTIONS 1-29 THROUGH 1-33, PERFORM THE INDICATED OPERATION.
1-29. Add:
100102
1. 100002 2. 111002 3. 101012 4. 110102
1-30. Add:
111012
1. 111112 2. 1001102 3. 1110102 4. 1000002
4
1-31. Add:
1. 1002 2. 10102 3. 10012 4. 10002
1-32. Add:
1. 10002 2. 10012 3. 1012 4. 1112
1-33. Add:
1. 0111102 2. 1010102 3. 100101 4. 1110012
1-34. Which of the following rules of binary subtraction is correct?
1. 0 - 0 = 0 with a borrow 2. 1 - 0 = 0 3. 2 - 1 = 1 4. 1 - 0 = 1
1-35. In the following example, which number is the minuend?
1. 101102 2. 11002 3. 10102 4. 101012
1-36. Which of the following rules of binary subtraction requires the use of a borrow?
1. 0 - 0 2. 1 - 0 3. 1 - 1 4. 0 - 1
1-37. In binary subtraction, what is the value of a borrow when it is moved to the next lower order column?
1. 12 2. 22 3. 102 4. 1010
IN ANSWERING QUESTIONS 1-38 THROUGH 1-40, PERFORM THE INDICATED OPERATION.
1-38. Subtract:
1. 101002 2. 110102 3. 001012 4. 010102
1-39. Subtract:
1. 001102 2. 010012 3. 011002 4. 000102
5
1-40. Subtract:
1. 10102 2. 10112 3. 11102 4. 10012
1-41. Subtraction is accomplished by which of the following methods in a computer that can only add?
1. Binary subtraction 2. Decimal complement 3. Complementary subtraction 4. Minuend complement
1-42. What is the R's-1 complement of 63310?
1. 47710 2. 46610 3. 36610 4. 37710
1-43. What is the R's-1 complement of 10111012?
1. 01000102 2. 10111102 3. 898889810 4. 898889910
1-44. What is the R's complement of 39510?
1. 60410 2. 60510 3. 71510 4. 71410
1-45. Which of the following parts of a subtraction problem must be complemented to perform complementary subtraction?
1. Subtrahend 2. Difference 3. Remainder 4. Minuend
1-46. Which of the following examples is the correct step when using the R's complement to subtract 12310 from 26410?
1. 735 + 123
2. 264 + 876
3. 264 + 321
4. 264 + 877
1-47. Which of the following solutions is correct when using the R's complement method of subtracting 51610 from 84510?
1. 845 + 483 328
2. 845 + 484 329
3. 845 + 615 460
4. 155 + 516 671
1-48. Which of the following numbers is the R's-1 complement of the binary number 10101?
1. 101002 2. 010112 3. 011002 4. 010102
6
1-49. Perform the R’s-1 complement of the following binary numbers.
1. (a) 01112 (b) 00102 (c) 10112 2. (a) 01102 (b) 00112 (c) 10102 3. (a) 01112 (b) 00112 (c) 10112 4. (a) 01102 (b) 00102 (c) 10102
1-50. Which of the following statements regarding the forming of the R’s complement of a binary number is correct?
1. Retain the MSD and complement all other digits
2. Complement all digits and subtract 1 3. Complement all digits 4. Retain the least significant 1 and
1-51. Which of the following numbers is the R’s complement of 1001012?
1. 1010102 2. 0110112 3. 1101102 4. 1010012
IN ANSWERING QUESTIONS 1-52 AND 1-53, USE THE R’S COMPLEMENT METHOD TO SOLVE THE PROBLEMS.
1-52. Subtract:
1. 1102 2. 0102 3. 1002 4. 11002
1-53. Subtract:
1. 00012 2. 01002 3. 01102 4. 00112
1-54. In the previous problems, what is indicated by the carry that expands the difference by one place?
1. The answer is incorrect 2. The answer is a positive number 3. The answer is correct 4. The answer is a negative number
IN ANSWERING QUESTIONS 1-55 THROUGH 1-57, SOLVE THE SUBTRACTION PROBLEMS AND INDICATE THE SIGN OF THE DIFFERENCE.
1-55. Subtract:
1. 000012 positive 2. 011112 negative 3. 011002 positive 4. 000012 negative
1-56. Subtract:
1. 00102 negative 2. 01112 positive 3. 11102 negative 4. 11112 positive
7
1-57. Subtract:
1. 111112 negative 2. 000012 negative 3. 011112 positive 4. 100002 positive
1-58. What is the radix of the octal number system?
1. 1010 2. 0 to 7 3. 8 4. 78
1-59. Which of the following is NOT a valid octal number?
1. 6048 2. 5918 3. 7438 4. 4778
1-60. Which of the following equations is correct?
1. 80 = 8 2. 81 = 1 3. 84 = 8 · 8 · 8 4. 82 = 8 · 8
1-61. One octal digit is represented by how many binary digits?
1. One 2. Two 3. Three 4. Four
1-62. What is the decimal value of 83?
1. 6410 2. 12810 3. 25610 4. 51210
1-63. Which of the following symbols is the least significant digit of the octal number 1622.374?
1. 1 2. 2 3. 6 4. 4
1-64. What is the sum of 48 and 48?
1. 1010 2. 108 3. 78 4. 168
1-65. What is the sum of 778 and 38?
1. 1278 2. 808 3. 1008 4. 1028
IN ANSWERING QUESTION 1-66, PERFORM THE INDICATED OPERATION.
1-66. Add:
1. 4658 2. 5618 3. 4378 4. 5318
1-67. Find the sum of 77418 and 678.
1. 100008 2. 100308 3. 70308 4. 107308
1-68. What is the sum of 78, 68, 58, and 48?
1. 228 2. 178 3. 268 4. 248
8
IN ANSWERING QUESTIONS 1-69 AND 1-70, PERFORM THE INDICATED OPERATION.
1-69. Add:
1. 76368 2. 76408 3. 106368 4. 107008
1-70. Add:
1. 101108 2. 107418 3. 105718 4. 122218
1-71. Which, if any, of the following is a difference between subtracting octal numbers and subtracting decimal numbers?
1. The amount of the borrow 2. The octal minuend is converted to
decimal 3. The octal subtrahend is converted to
decimal 4. None; there is no difference
IN ANSWERING QUESTIONS 1-72 THROUGH 1-74, PERFORM THE INDICATED OPERATION.
1-72. Subtract:
1. 1258 2. 2658 3. 2258 4. 22510
1-73. Subtract:
1. 1448 2. 2328 3. 1328 4. 1428
1-74. Subtract:
1. 20018 2. 20118 3. 21118 4. 20008
9
ASSIGNMENT 2 Textbook assignment: Chapter 2, “Number Systems,” pages 2-1 through 2-36.
2-1. Which of the following numbers does NOT represent a hexadecimal value?
1. 2DF4 2. A32B 3. 47CE 4. 9FGF
2-2. What is the decimal value of the highest symbol in the hex system?
1. 1510 2. 1610 3. F16 4. 1016
2-3. The decimal number 256 is equal to what power of 16?
1. 163 2. 162 3. 164 4. 161
2-4. List the MSD and LSD of the hex number F24.ECB.
1. MSD = 4, LSD = E 2. MSD = 4, LSD = B 3. MSD = F, LSD = 4 4. MSD = F, LSD = B
IN ANSWERING QUESTIONS 2-5 THROUGH 2-7, PERFORM THE INDICATED OPERATION.
2-5. Find the sum.
1. C16 2. D16 3. E16 4. F16
2-6. Add:
1. 3316 2. 3116 3. 3716 4. 4716
2-7. Add:
1. C1116 2. C0A16 3. B0016 4. BFA16
2-8. When a borrow is taken from a hex number, that number is reduced by how much?
1. 1 2. 1016 3. 1610 4. 1010
10
IN ANSWERING QUESTION 2-9, FIND THE DIFFERENCE.
2-9. Subtract:
1. A16 2. 716 3. 816 4. 916
2-10. To begin conversion of a decimal number to a different base, divide the (a) by (b).
1. (a) new base (b) 10
2. (a) decimal number (b) 2
3. (a) decimal number (b) the new base
4. (a) new base (b) the decimal equivalent
2-11. Which of the following terms describes the first remainder when converting decimal numbers to other bases?
1. MSD 2. LSD 3. Radix of the new base 4. Exponent of the new base
IN ANSWERING QUESTIONS 2-12 THROUGH 2-14, USE THE DIVISION METHOD TO CONVERT DECIMAL NUMBERS TO BINARY.
2-12. 4310
1. 1010112 2. 1101012 3. 1000112 4. 1011012
2-13. 6310
1. 1010112 2. 1100112 3. 1011012 4. 1111112
2-14. 13010
1. 11110002 2. 11110102 3. 100000102 4. 100010102
2-15. To convert fractional decimal numbers to binary, multiply the number by (a) and extract the portion of the product to the (b) of the radix point.
1. (a) 2 (b) left 2. (a) 2 (b) right 3. (a) 10 (b) left 4. (a) 10 (b) right
IN ANSWERING QUESTIONS 2-16 THROUGH 2-19, PERFORM THE INDICATED OPERATION.
2-16. Convert 0.7510 to binary.
1. 0.102 2. 0.012 3. 0.112 4. 1.002
2-17. Convert 0.62510 to binary.
1. 0.0112 2. 0.1012 3. 0.1102 4. 0.1002
2-18. Convert 12.510 to base 2.
1. 1100.102 2. 1010.012 3. 1001.102 4. 1101.012
11
2-19. Convert 33.3410 to base 2 (four places).
1. 11110.10102 2.<PHONE_NUMBER>2 3.<PHONE_NUMBER>2 4.<PHONE_NUMBER>2
IN ANSWERING QUESTIONS 2-20 THROUGH 2-22, USE THE DIVISION METHOD TO CONVERT DECIMAL NUMBERS TO OCTAL.
2-20. 19310
1. 628 2. 1428 3. 3018 4. 4038
2-21. 74610
1. 13528 2. 25318 3. 14768 4. 23128
2-22. 300710
1. 50008 2. 56778 3. 47718 4. 41158
IN ANSWERING QUESTIONS 2-23 THROUGH 2-25, PERFORM THE INDICATED OPERATION.
2-23. Convert 0.30510 to octal (four places).
1. 0.57658 2. 0.14718 3. 0.30508 4. 0.23418
2-24. Convert 78.910 to octal (three places).
1. 100.4178 2. 103.7148 3. 116.7148 4. 116.1478
2-25. Convert 506.6610 to octal (four places).
1. 677.50638 2. 521.44018 3. 653.37748 4. 772.52178
2-26. What is the hex equivalent of 4510?
1. 1F16 2. 2416 3. 2A16 4. 2D16
2-27. What is the hex equivalent of 25510?
1. AE16 2. BC16 3. CG16 4. FF16
IN ANSWERING QUESTIONS 2-28 THROUGH 2-30, PERFORM THE INDICATED OPERATION.
2-28. Convert 160910 to hex.
1. 5A516 2. 64916 3. C4116 4. A9516
2-29. Convert 0.84 to hex (three places).
1. 0.D7016 2. 0.1F316 3. 0.AAC16 4. 0.C3E16
2-30. Convert 0.10910 to hex (four places).
1. 0.111416 2. 0.101F16 3. 0.1BE716 4. 0.09D416
12
2-31. What is the hex equivalent of 174.9510? Carry out two places.
1. 9F.C416 2. AE.F316 3. AE.9C16 4. BA.EC16
2-32. What is the hex equivalent of 7023.86910? Carry out to four places.
1. 1C5E.A9F616 2. 1B6F.DE7616 3. 1D7C.EC8716 4. 1AA9.DB1A16
IN ANSWERING QUESTIONS 2-33 THROUGH 2-38, CONVERT THE BINARY NUMBERS TO THEIR OCTAL EQUIVALENT.
2-33. 00110102
1. 1508 2. 0328 3. 0428 4. 0628
2-34.<PHONE_NUMBER>002
1. 5168 2. 1478 3. 6678 4. 12348
2-35.<PHONE_NUMBER>1111012
1. 533758 2. 1557768 3. 2557718 4. 1267718
2-36. 0.11101010002
1. 0.15608 2. 0.16508 3. 0.7508 4. 0.7248
2-37. 1001000.000111102
1. 110.0748 2. 440.0368 3. 410.0708 4. 220.0748
2-38.<PHONE_NUMBER>.111100112
1. 1773.7468 2. 7751.3638 3. 1773.6338 4. 7751.4738
IN ANSWERING QUESTIONS 2-39 THROUGH 2-42, CONVERT THE BINARY NUMBERS TO THEIR HEXADECIMAL EQUIVALENTS.
2-39. 1011012
1. B116 2. 5516 3. 1B16 4. 2D16
2-40.<PHONE_NUMBER>102
1. EB216 2. EC416 3. 7B216 4. 726216
2-41. 0.01001111002
1. 0.4 F16 2. 0.9 E16 3. 0.13C16 4. 0.23616
2-42. 11011100.1100101010112
1. 670.625316 2. 9A.BAC16 3. DC.CAB16 4. AB.CDE16
13
IN ANSWERING QUESTIONS 2-43 THROUGH 2-45, CONVERT THE OCTAL NUMBERS TO THEIR BINARY EQUIVALENTS.
2-43. 5718
1.<PHONE_NUMBER> 2. 10111112 3.<PHONE_NUMBER> 4.<PHONE_NUMBER>
2-44. 13128
1.<PHONE_NUMBER>2 2.<PHONE_NUMBER>2 3.<PHONE_NUMBER>12 4.<PHONE_NUMBER>02
2-45. 136.528
1. 1110110.1011002 2. 11011111.1010102 3. 01011011.0101012 4. 01011110.1010102
IN ANSWERING QUESTIONS 2-46 AND 2-47, PERFORM THE INDICATED OPERATIONS.
2-46. Convert 24.738 to hex.
1. 11.7616 2. 14.EC16 3. 24.7D16 4. 20.A616
2-47. Convert 657.138 to hex.
1. 328.06516 2. D37.2616 3. 1AF.2C16 4. 20A.B116
IN ANSWERING QUESTIONS 2-48 THROUGH 2-50, CONVERT THE HEX NUMBERS TO BINARY.
2-48. 2A16
1. 010010102 2. 001010102 3. 010011002 4. 000111002
2-49. E4716
1.<PHONE_NUMBER>112 2.<PHONE_NUMBER>112 3.<PHONE_NUMBER>102 4.<PHONE_NUMBER>112
2-50. 8C.1F16
1.<PHONE_NUMBER>11102 2. 10001100.000111112 3. 1001100.000111102 4. 10011101.000111112
IN ANSWERING QUESTIONS 2-51 AND 2-52, CONVERT THE HEX NUMBERS TO OCTAL.
2-51. 74E16
1. 74168 2. 72178 3. 35168 4. 46368
2-52. F1.C816
1. 741.6208 2. 661.3048 3. 331.648 4. 361.628
2-53. What is the decimal equivalent of 10112
1. 1310 2. 1110 3. 910 4. 1010
14
IN ANSWERING QUESTIONS 2-54 AND 2-55, PERFORM THE INDICATED OPERATION.
2-54. Convert 1011012 to decimal.
1. 5510 2. 2910 3. 3610 4. 4510
2-55. Convert<PHONE_NUMBER>2 to decimal.
1.  C3.616
1. 46.510 2. 84.410 3. 150.50510 4. 195.37510
2-64. 4DD.E16
1. 1245.750510 2. 1245.875010 3. 733.750510 4. 733.937510
2-65. What term describes the use of four binary digits to represent one decimal digit?
1. Decimal-coded binary 2. Octal-coded binary 3. Binary-coded decimal 4. Hexadecimal notation
15
2-66. How many binary digits are required to represent the decimal number 243 in BCD?
1. 12 2. 8 3. 3 4. 4
IN ANSWERING QUESTIONS 2-67 AND 2-68, PERFORM THE INDICATED OPERATION.
2-67. Convert 38910 to BCD.
1. 0000 1110 0101BCD 2. 0011 0001 1101BCD 3. 0011 1000 1001BCD 4. 0011 0100 0101BCD
2-68. Convert<PHONE_NUMBER>11BCD to decimal.
1. 89710 2. 85710 3. 49710 4. 45710
2-69. Which of the following numbers has the highest decimal value?
1. 100110012 2. 111000012 3. 1001 1001BCD 4. 1000 0110BCD
2-70. Which of the following numbers is NOT a valid BCD number?
1. 0110 2. 1001 3. 1000 4. 1010
IN ANSWERING QUESTIONS 2-71 THROUGH 2-75, PERFORM THE INDICATED OPERATION.
2-71. Add:
1. 0111BCD 2. 1001BCD 3. 1010BCD 4. 1000BCD
2-72. Add:
1. 0001 0000BCD 2. 0001 0110BCD 3. 0111 0110BCD 4. 0001 1111BCD
2-73. Add:
1. 1101BCD 2. 0011BCD 3. 0001 0011BCD 4. 0001 0110BCD
2-74. Add:
1. 0011 1011BCD 2. 0011 0001BCD 3. 0100 1011BCD 4. 0100 0001BCD
16
2-75. Add:
1. 0000 1111 0110BCD 2. 0001 0101 1100BCD 3. 0001 0101 0110BCD 4. 0001 0111 0100BCD
17
Logic Circuits," Chapter 3, pages 3-1 through 3-3. _____________________________________________________________________________________
NOTE: UNLESS OTHERWISE INDICATED, ALL QUESTIONS AND ANSWERS REFER TO POSITIVE LOGIC.
3-1. Logic is the development of a reasonable conclusion based on known information.
1. T 2. F
3-2. Which of the following methods is used to represent the FALSE condition of the logic symbol, F?
1. (F) 2. [F] 3. F 4. F
3-3. Which of the following statements describes logic polarity?
1. Negative logic is indicated by a vinculum
2. Positive logic is always represented by a positive voltage
3. A logic 1 is a positive voltage; a logic 0 is a negative voltage
4. The change in voltage polarity to represent a logic 1
3-4. Which of the following examples represents positive logic?
1. - 5v equals 0, - 10v equals 1 2. +5v equals 0, +10v equals 1 3. +5v equals 1, +10v equals 0 4. - 5v equals 1, +5v equals 0
3-5. Of the following examples, choose the one that represents negative logic.
1. - 15v equals 0, - 10v equals 1 2. - 10v equals 1, - 15v equals 0 3. 0v equals 0, - 10v equals 1 4. - 5v equals 0, 0v equals 1
3-6. If the letter X represents an input to a logic device, what logic state of X must exist to activate the device or contribute to the activation of the device?
1. 0 2. 1 3. Positive logic 4. Negative logic
3-7. A chart that lists all possible input combinations and resultant output is called a
1. Truth Table 2. Decision Table 3. logic symbol listing 4. polarity magnitude listing
3-8. What is a logic gate?
1. A block diagram 2. An astable multivibrator 3. A bistable multivibrator 4. A decision-making circuit
18
3-9. Which of the following logic gates requires all inputs to be TRUE at the same time to produce a TRUE output?
1. OR 2. NOT 3. AND 4. NAND
3-10. Which of the following output Boolean expressions is/are correct for an AND gate?
1. f = AB 2. f = A·B 3. Both 1 and 2 above 4. A=B
3-11. Which of the following symbols represents the output Boolean expression RZ?
Figure 3A. ¾ AND gate timing diagram.
IN ANSWERING QUESTIONS 3-12 THROUGH 3-14, REFER TO FIGURE 3A.
3-12. At which of the following times will the output of a two input AND gate go HIGH?
1. T2, T5, and T8 2. T4 only 3. T2, T6, and T10 4. T4 and T9
3-13. At which of the following times will the output of the AND gate be LOW?
1. T1 to T4 and T5 to T8 2. T1 to T4 and T6 to T9 3. T4 to T6 and T8 to T10 4. T1 to T3 and T6 to T10
19
3-14. If input B were used instead of input B, how would the output be affected, if at all?
1. It would be HIGH from T2 to T 4 2. It would be LOW from T4 to T 6 3. It would be HIGH from T2 to T 3and
T8 to T9 4. It would not be affected
3-15. What is the output Boolean expression for an AND gate having F, G K, , and L as inputs?
1.
Figure 3B. ¾ Logic symbol diagram.
IN ANSWERING QUESTIONS 3-16 THROUGH 3-18, REFER TO FIGURE 3B.
3-16. Which of the following gates is represented by the symbol in the figure?
1. AND 2. OR 3. NOR 4. X-OR
3-17. What is the output Boolean expression for the gate?
1. X, Y+Z 2. X+Y ¯ X 3. X+Y+Z 4. X ¯ Y¯ Z
THIS SPACE LEFT BLANK INTENTIONALLY.
20
3-18. Which of the following Truth Tables correspond to the gate in the figure?
1.
2.
3.
4.
21
Figure 3C. ¾ OR gate timing diagram.
IN ANSWERING QUESTIONS 3-19 THROUGH 3-21, REFER TO FIGURE 3C.
3-19. The gate will have a HIGH output at which of the following times?
1. T0 to T3, T4 to T7, and T8 to T9 2. T1 to T2 and T4 to T9 3. T3 to T4 and T7 to T8 4. T1 to T2 only
3-20. What are the input logic states between T5 and T6?
1. X = 1, Y = 0, Z = 0 2. X = 1, Y = 0, Z = 1 3. X = 0, Y = 1, Z = 0 4. X = 0, Y = 1, Z = 1
3-21. Between T0 and T6, at what times will the output of the gate be LOW?
1. T3 to T4 2. T2 to T5 3. T3 to T6 4. T0 to T1
3-22. What is the Boolean expression for an OR gate having the following inputs?
1. T R P 2. T R P 3. T + R + P 4. T + R + P
3-23. What is the purpose of an inverter?
1. To change logic polarity 2. To change voltage levels 3. To amplify the input 4. To complement the input
3-24. Which of the following symbols represents an inverter?
22
3-25. Which of the following is the standard logic symbol for a NAND gate?
3-26. What is the output expression for an inverter with the following input?
1. ( QR ) + (S T ) 2. R Q S T 3. RQST 4. T)S()Q(R +
3-27. Which of the following gates produces a HIGH output when any or all of the inputs are LOW?
1. AND 2. OR 3. NAND 4. NOR
Figure 3D. ¾ Incomplete NAND gate Truth Table.
IN ANSWERING QUESTION 3-28, REFER TO FIGURE 3D.
3-28. Which of the following NAND gate input combinations and output function is missing?
1. X = 0, Y = 1, f = 0 2. X = 0, Y = 1, f = 1 3. X = 0, Y = 0, f = 0 4. X = 1, Y = 1, f = 1
3-29. What is the output Boolean expression for a NAND gate with inputs G, K, and P ?
1. GK P 2. GKP 3. PGK 4. G K P
23
3-30. The output of a NOR gate will be HIGH under which of the following conditions?
1. When all inputs are HIGH 2. When all inputs are LOW 3. When one input is HIGH 4. When one input is LOW
3-31. What is the output Boolean expression for a NOR gate with P , Q, and R as inputs?
1. RQP ++ 2. RQP ++ 3. RQP ++ 4. RQP ++
Figure 3E. ¾ Input signal timing diagram.
IN ANSWERING QUESTIONS 3-32 THROUGH 3-34, REFER TO FIGURE 3E.
3-32. Figure 3E represents the input signals to a NOR gate. What is the output expression?
1. M + N 2. NM + 3. NM + 4. NM +
3-33. At which of the following times will the output be HIGH?
1. T3 to T4 2. T8 to T9 3. T4 to T6 and T7 to T8 4. T3 to T4 and T8 to T9
3-34. What should the output be between times T3 and T4?
1. LOW 2. HIGH
Figure 3F. ¾ Logic gates.
IN ANSWERING QUESTIONS 3-35 THROUGH 3-37, REFER TO FIGURE 3F.
3-35. What is the output expression for gate D?
1. ZX + 2. XZ 3. ZX + 4. ZX +
24
3-36. The Truth Tables are identical for which two gates?
1. C and D 2. A and D 3. B and C 4. A and B
3-37. Which gate represents the output
expression ZX ?
1. A 2. B 3. C 4. D
Figure 3G. ¾ Logic circuit.
IN ANSWERING QUESTION 3-38, REFER TO FIGURE 3G.
3-38. Which of the following output expressions represents the output of gate 3?
1. (RS) (TV) 2. RS + TV 3. (RS) + ( TV ) 4. ( RS ) +(TV)
Figure 3H. ¾ Logic circuit.
IN ANSWERING QUESTIONS 3-39 AND 3-40, REFER TO FIGURE 3H.
3-39. The output expression JK represents the output of which, if any, of the following gates?
1. 1 2. 2 3. 3 4. None of the above
3-40. What is the output expression for gate 3?
1. ML(KJ + ) 2. )ML()KJ( ++ 3. )ML()KJ( +++ 4. )ML)(1J(K +
25
Figure 3I. ¾ Logic circuit.
IN ANSWERING QUESTIONS 3-41 THROUGH 3-45, REFER TO FIGURE 3I.
3-41. What is the output expression for gate 105?
1. ( )VT()RS ++ 2. RSTV
3. )VT)(RS( + 4. )VT()RS( ++
3-42. Which of the following gates provides a common output to two other gates?
1. 101 2. 102 3. 104 4. 106
3-43. Which of the following expressions represents the output of gate 106?
1. TVXW 2. VTXW +++ 3. )XW()TV( + 4. )XW(V)(T ++
3-44. Which of the following conditions will cause gate 107 output to be HIGH?
1. Gate 106 is LOW; Y and Z are HIGH
2. Gate 106 is LOW; Y is HIGH, Z is LOW
3. Gate 106 is HIGH; Y and Z are LOW
4. Gate 106 is HIGH; Y is LOW, Z is HIGH
3-45. What is the output expression for gate 107?
1. )ZY)(XWTV( ++ 2. ( XWVT +++ )(YZ) 3. ((T+V)+( W +X))( YZ ) 4. )ZY)(XW)(VT( ++
3-46. Boolean algebra is used primarily by which of the following groups?
1. Fabricators 2. Technicians 3. Design engineers 4. Repair personnel
26
3-47. Which of the following Boolean laws states, "a term that is TRUE in one part of an expression will be TRUE in all parts of the expression"?
1. Identity 2. Commutative 3. Complementary 4. Double negative
3-48. The examples AB = BA and A+B = B+A represent which of the following Boolean laws?
1. Associative 2. Commutative 3. Intersection 4. Union
3-49. What type of logic gate is modified to produce an exclusive OR gate?
1. AND 2. NAND 3. OR 4. NOR
3-50. Which of the following symbols represents the operation function of an exclusive OR gate?
1. Q 2. ¯ 3. O 4. ˜
Figure 3J. ¾ Logic gate.
IN ANSWERING QUESTIONS 3-51 AND 3-52, REFER TO FIGURE 3J.
3-51. What will be the output of the gate when (a) X is HIGH and Z is LOW, and (b) X and Z are both HIGH?
1. (a) LOW (b) LOW 2. (a) LOW (b) HIGH 3. (a) HIGH (b) LOW 4. (a) HIGH (b) HIGH
3-52. What will be the output of the gate when (a) X and Z are both LOW and (b) X is LOW and Z is HIGH?
1. (a) LOW (b) LOW 2. (a) LOW (b) HIGH 3. (a) HIGH (b) LOW 4. (a) HIGH (b) HIGH
27
3-53. Which of the following symbols represents an exclusive NOR gate?
3-54. What is the output of an exclusive NOR gate when (a) all inputs are LOW and (b) all inputs are HIGH?
1. HIGH (b) HIGH 2. LOW (b) HIGH 3. HIGH (b) LOW 4. LOW (b) LOW
3-55. What is the output expression for an exclusive NOR gate with R and T as inputs?
1. TR ¯ 2. TR + 3. TR + 4. TR ¯
28
ASSIGNMENT 4 Textbook assignment: Chapter 4, “Special Logic Circuits,” pages 3-3 through 3-67.
4-1. Which of the following circuits will add two binary digits but not produce a carry?
1. AND gate 2. Half adder 3. Quarter adder 4. Summation amplifier
Figure 4A.—Logic circuit.
IN ANSWERING QUESTIONS 4-2 THROUGH 4-5, REFER TO FIGURE 4A.
4-2. What type of circuit is depicted in the
figure?
1. Inverter amplifier 2. Half subtracter 3. Half adder 4. Quarter adder
4-3. Which of the following gates will have
HIGH outputs when K is HIGH and L is LOW?
1. 1 only 2. 3 only 3. 1 and 2 4. 1 and 3
4-4. What will be the output of gate 3 when
K and L are both HIGH?
1. LOW 2. HIGH
4-5. Assume that K and L are both HIGH.
Which of the following statements represents the output of gate 3?
1. 1 plus 1 = 0 (No carry) 2. 1 plus 0 = 1 3. 0 plus 1 = 1 4. 0 plus 0 = 0
4-6. Which of the following gates performs
the same function as a quarter adder?
1. Half adder 2. Exclusive OR 3. NOR 4. Exclusive NOR
THIS SPACE LEFT BLANK INTENTIONALLY.
29
Figure 4B.—Logic circuit.
IN ANSWERING QUESTIONS 4-7 THROUGH 4-9, REFER TO FIGURE 4B.
4-7. Which of the following circuits is shown
in the figure?
1. Quarter adder 2. Half adder 3. Full adder 4. Subtracter
4-8. Which of the following gate
combinations may be replaced with an exclusive OR gate?
1. 1, 2, and 3 2. 1, 2, and 4 3. 1, 3, and 4 4. 2, 3, and 4
4-9. The output of gate 3 is the (a) and the
output of gate 4 is the (b).
1. (a) Carry (b) sum 2. (a) Sum (b) difference 3. (a) Sum (b) carry 4. (a) Carry (b) difference
4-10. What is the largest sum that can be obtained from a half adder?
1. 012 2. 102 3. 112 4. 1002
4-11. Which of the following statements describes the difference between a half adder and a full adder?
1. A half adder produces a carry 2. A full adder produces a carry 3. A half adder will add a carry from
another circuit 4. A full adder will add a carry from
THIS SPACE LEFT BLANK INTENTIONALLY.
30
Figure 4C.—Logic circuit.
IN ANSWERING QUESTIONS 4-12 THROUGH 4-14, REFER TO FIGURE 4C.
4-12. What type of circuit is shown in the
figure?
1. Full adder 2. Subtracter adder 3. Double half adder 4. Double exclusive OR
4-13. If A and B are 0 and C is 1, what will be
the outputs at D and E?
1. D = 0, E = 0 2. D = 0, E = 1 3. D = 1, E = 0 4. D = 1, E = 1
4-14. Under which of the following conditions will outputs D and E both be HIGH?
1. A, B, and C are HIGH 2. A and B are HIGH, C is LOW 3. A and B are LOW, C is HIGH 4. A, B, and C are LOW
4-15. What is the largest sum that can be
obtained from a full adder?
1. 102 2. 112 3. 1002 4. 1112
4-16. How many full adders are required to
form a parallel adder capable of adding 100012 and 10002?
1. Five 2. Six 3. Three 4. Four
31
4-17. Which of the following statements describes the method used in computers to subtract binary numbers?
1. R's complement the minuend and
add to the subtrahend 2. Add the minuend and subtrahend
and complement the sum 3. R's complement the subtrahend and
add to the minuend 4. Subtract the subtrahend from the
Figure 4D.—Adder/subtracter circuit.
IN ANSWERING QUESTIONS 4-18 THROUGH 4-20, REFER TO FIGURE 4D.
4-18. What type of complement is performed
by X-OR gates 1 and 2?
1. R's complement 2. Minuend complement 3. R's + 1 complement 4. Difference complement
4-19. Which of the following inputs is used for the least significant digit of the minuend?
1. A1 2. A2 3. B1 4. B2
4-20. What will be the output of (a) X-OR 2
and (b) X-OR 1 in the subtract mode with a subtrahend of 102?
1. (a) 0 (b) 0 2. (a) 0 (b) 1 3. (a) 1 (b) 0 4. (a) 1 (b) 1
4-21. Flip-flops are what type of
multivibrators?
1. Astable 2. Monostable 3. Free running 4. Bistable
4-22. Flip-flops may NOT be used for which
of the following operations?
1. Temporary storage 2. Subtraction 3. Division 4. Transfer of information
4-23. When, if ever, will the outputs Q and Q of an R-S flip-flop be the same?
1. When R and S are both LOW 2. When R is LOW and S is HIGH 3. When R is HIGH and S is LOW 4. Never
32
Figure 4E.—R-S flip-flop with timing diagram.
WHEN ANSWERING QUESTIONS 4-24 AND 4-25, REFER TO FIGURE 4E.
4-24. Assume the flip-flop is set at T0. At
which of the following times will the flip-flop be reset?
1. T1 to T3, T5 to T6, and T9 to T10 2. T0 to T1, T3 to T5, and T6 to T9 3. T1 to T3, T5 to T7, and T9 to T10 4. T1 to T4, T5 to T7, and T9 to T10
4-25. What happens to the flip-flop at T6?
1. It sets 2. It resets 3. It sets and immediately resets 4. It remains reset
4-26. Which of the following statements
describes a toggle flip-flop?
1. A monostable device 2. An astable device that changes state
only on a set pulse 3. A two input bistable device 4. A bistable device with a single input
4-27. A T flip-flop is used primarily for which of the following functions?
1. To divide the input frequency by
two 2. To double the input frequency 3. To amplify the input frequency 4. To invert the input frequency
4-28. What are the inputs to a D flip-flop?
1. Set and reset 2. Set and clock 3. Data and clock 4. Reset and data
4-29. What is the purpose of a D flip-flop?
1. To eliminate the output of the
equipment 2. To divide the data input by the clock
frequency 3. To store data until it is needed 4. To toggle the data input
4-30. An inverter on the clock input has which
of the following effects on the D flip- flop?
1. The output will change on the
2. The output will change on the positive-going transition of the clock pulse
3. The data input will change at the clock frequency
4. The output will change at the clock frequency
4-31. Which of the following statements is
true concerning CLR and PR pulses to the D flip-flop?
1. CLR causes Q to go high, PR causes
Q to go low 2. CLR and PR override any existing
output condition 3. Other inputs override CLR and PR 4. CLR and PR have no effect on the
33
4-32. Which of the following statements is correct concerning D flip-flops?
1. The output is delayed up to one
clock pulse 2. Input data is delayed until it
coincides with the clock 3. The clock is delayed until it
coincides with the input data 4. The output is always a square wave
Figure 4F.—Standard symbol for a J-K flip-flop.
WHEN ANSWERING QUESTIONS 4-33 THROUGH 4-36, REFER TO FIGURE 4F.
4-33. The flip-flop shown in the figure may be
used in place of which of following flip- flops?
1. R-S 2. T 3. D 4. Each of the above
4-34. With the clock applied and J and K inputs held HIGH, what is the output at Q?
1. Constant HIGH 2. Constant LOW 3. Toggle at one half the clock
frequency 4. Toggle at twice the clock frequency
4-35. What will be the Q output if K is HIGH and CLK goes HIGH?
1. HIGH 2. LOW
4-36. A pulse on which of the following
inputs will cause the flip-flop to set regardless of the other inputs?
1. CLK 2. CLR 3. J or K 4. PR or PS
4-37. The circuit which generates a timing
1. clock 2. counter 3. oscillator 4. bistable multivibrator
4-38. Which of the following statements is
true regarding astable multivibrators used as clocks?
1. As multivibrator frequency
increases, stability decreases 2. Output 2 will have a higher voltage
than output 1 3. The frequency stability may be
4. A trigger of lower frequency will stabilize the output frequency
4-39. Which of the following types of circuits
will produce a stable clock when triggered by an outside source?
1. R-S flip-flop 2. Bistable multivibrator 3. One-shot multivibrator 4. D flip-flop
34
4-40. Which of the following types of clocks would probably be used in a complex piece of equipment with a variety of timing requirements?
1. Single triggered-monostable 2. Single free-running 3. Triggered-astable for each section of
the equipment 4. Multiphase
4-41. What is the modulus of a 3-stage binary
counter?
1. 7 2. 8 3. 3 4. 4
4-42. Counters may be used for which of the following purposes?
1. Counting operations, quantities and
time 2. Dividing frequency 3. Addressing information in storage 4. Each of the above
35
WHEN ANSWERING QUESTIONS 4-43 THROUGH 4-46, REFER TO FIGURE 4G.  What type of circuit is shown?
1. J-K flip-flops 2. Clock 3. Shift register 4. Ripple counter
4-44. Assume all lights are out. After 6 input
pulses, which two lamps will be lit?
1. A and B 2. A and C 3. B and C 4. B and D
4-45. Assume all lamps are out. After 16 input pulses, which lamps, if any, will be lit?
1. A, B, C, and D 2. B, C, and D 3. A, B, and D 4. None
4-46. What is the main disadvantage of using
this circuit with a high frequency input?
1. The circuit will burn up 2. Possible errors in the output 3. The flip-flops will act as T flip-flops 4. Above a certain frequency the
36
WHEN ANSWERING QUESTIONS 4-47 THROUGH 4-50, REFER TO FIGURE 4H.
4-47. What is the maximum count that this
counter is capable of holding?
1. 58 2. 78 3. 38 4. 48
4-48. What type of counter is shown?
1. Ring 2. Asynchronous 3. Synchronous 4. Decade
4-49. Under which of the following conditions will the output of the AND gate be HIGH?
1. FF 1 and FF 2 are set 2. FF 1 and FF 2 are reset 3. FF 2 and FF 3 are set 4. FF 1 and FF 3 are reset
4-50. With all the FFs initially reset, the AND
gate output will be HIGH after how many input pulses?
1. 3 only 2. 4 only 3. 7 only 4. 3 and 7
37
WHEN ANSWERING QUESTIONS 4-51 AND 4-52, REFER TO FIGURE 4I.
4-51. What is the maximum binary count that
will be shown before all the flip-flops reset?
1. 1112 2. 10102 3. 11112 4. 10002
4-52. To change the maximum count from 1010 to 910, which two flip-flops would be wired as NAND gate inputs?
1. FF 1 and FF 2 2. FF 2 and FF 3 3. FF 1 and FF 4 4. FF 1 and FF 3
THIS SPACE LEFT BLANK INTENTIONALLY.
38
WHEN ANSWERING QUESTIONS 4-53 THROUGH 4-55, REFER TO FIGURE 4J.
4-53. Which of the following types of
counters is shown in the figure?
1. Ring 2. Asynchronous 3. Synchronous 4. Decade
4-54. At any given time, how many flip-flops
may be set?
1. Only one 2. Any two 3. Any three 4. All
4-55. Which of the following conditions must exist to set FF 3?
1. AND gate 1 output HIGH 2. AND gate 2 output HIGH 3. AND gate 3 output LOW 4. Clock input to AND gate 3 LOW
39
WHEN ANSWERING QUESTIONS 4-56 AND 4-57, REFER TO FIGURE 4K.
4-56. Assume only FF 1 and FF 3 are set.
Which, if any, of the flip-flops will be set after the next clock pulse?
1. FF 2 only 2. FF 3 only 3. FF 2 and FF 3 4. None
4-57. Assume that all FFs are set, which of the
following actions will take place at clock pulse 4?
1. FF 1, FF 2 and FF 3 will set 2. FF 1 will set, FF 2 and FF 3 will
reset 3. FF 1, FF 2, and FF 3 will reset 4. FF 1 and FF 2 will set, FF 3 will
4-58. What term identifies a series of FFs designed to temporarily store information?
1. Data word 2. Counter 3. Register 4. DIP package
4-59. Which of the following statements
describes parallel transfer?
1. Data is transferred one bit at a time 2. All data bits are transferred
simultaneously 3. Data is received in serial form and
transferred in parallel form 4. Data is transferred on a single line
40
WHEN ANSWERING QUESTIONS 4-60 AND 4-61, REFER TO FIGURE 4L.
4-60. Which of the following methods will
clear the register of old information no longer needed?
1. A HIGH applied to the READ IN
line 2. A HIGH applied to the RESET line 3. A LOW applied on the RESET and
a HIGH on the READ OUT lines 4. HIGHs are applied on the A, B, C,
4-61. Under which of the following conditions will the output of gate 7 be HIGH?
1. When FF 3 and RESET are HIGH 2. When gate 3 and FF 3 are HIGH 3. When FF 3 and READ OUT are
HIGH 4. When the output of gate 3 is HIGH
41
WHEN ANSWERING QUESTIONS 4-62 THROUGH 4-67, REFER TO FIGURE 4M.
4-62. Which of the following operations is the
circuit capable of performing?
1. Serial-to-parallel conversion 2. Parallel-to-serial conversion 3. Left shifts 4. Each of the above
4-63. What is the maximum word length the
register is capable of handling?
1. 6 bit 2. 5 bit 3. 3 bit 4. 4 bit
4-64. How many clock/shift pulses are required to serially input a word into the register?
1. 1 2. 5 3. 3 4. 4
4-65. To output a word in parallel form, how
many output lines are required?
1. 1 2. 2 3. 4 4. 8
42
4-66. To increase the value of a word by one power of 2, how many shifts are required?
1. 1 2. 2 3. 3 4. 0
4-67. Which of the following operations takes
the longest time?
1. Serial in, parallel out 2. Serial in, serial out 3. Parallel in, serial out 4. Parallel in, parallel out
4-68. Shifting a word in a shift register 3
places to the left is equal to multiplying the number by how much?
1. 1010 2. 210 3. 810 4. 410
4-69. Logic families are identified by which of the following means?
1. Logic polarity required 2. The types of elements used 3. Size and cost of manufacture 4. Packaging (DIP, TO, flat packs)
4-70. A TTL logic circuit would use which of
the following types of elements?
1. Diode-transistor 2. Resistor-transistor 3. Transistor-transistor 4. Complementary metal oxide


I'm A Celebrity's fake chores exposed as bosses ban campfire and eating bugs
The line-up of this year's I'm A Celebrity certainly don't have their work cut out for them - half the chores they're meant to do are already sorted by producers
by Irishmirror.ieThe cast of I'm A Celebrity... Get Me Out Of Here! 2019 are all in the camp now - but unlike in previous years, they're set to have a relatively easy time of things.
Because this year's camp comes with a shakeup amid problems in Australia and an outcry over previous series of the ITV show.
Mirror Online can reveal that not only will the campmates be given an easy ride with their Bushtucker trials - there's now a ban on the eating of live animals, meaning the days of having to crunch down on twitching witchetty grubs are gone - but there aren't even that many chores to do.
There's also a ban on the lighting of a campfire for the first time in the history of the show, given that vast areas of the state of New South Wales are on fire thanks to unprecedented wildfires.
Instead, the celebs will have to cook their food on a gas stove to limit the risk of another blaze.
"In light of the current situation in Australia, I'm A Celebrity will not feature an open camp fire," an ITV spokesman said this week.
"Instead, campmates will cook their food and boil their water on a specially made gas stove."
However, there won't even be much boiling of water, as there's a special tank installed in the camp where they can draw their drinking water without having to faff around with heating up the stove.
And while this year there's no need for them to use firewood, in previous series the chopping has already been done for them by staff, who leave handy piles of the fuel lying around so the stars can just pick it up pre-chopped and haul it back to camp.
The worst part of the camp has to be the dunny, where the celebs do their business.
But while much has been made of the poor star who gets the raw end of the deal, the toilet is actually emptied for them by production runners, who take the bucket to another location where it is picked up, cleaned and returned.
One thing that is just as true in real life as is shown on TV is the tiny amount of food the celebs receive daily.
Unless they win stars in their challenges, each of the campmates are on basic rations of rice and beans - which can lead to exhaustion.
Sometimes they get given electrolyte drinks and glucose to keep them going, but most of the time they'll lay around the camp to conserve their energy.
Medic Bob told the Mirror in previous years that he's had to administer emergency supplements to some of the celebs.
"I mean there's been a couple, I can't mention it medically, but there's been a couple that have had a few dizzy spells and we've given them some electrolyte drinks and some glucose," he said in 2017.
"They're very hungry, really hungry. They're very hungry at the moment, they haven't done quite so well at the trials lately.
"If you could see how much rice and beans they get per person, per day, I think you'd be quite shocked.
*I'm A Celebrity 2019 launches Sunday November 17 at 9pm on ITV


CodeSpec 1.0
Base Test
In order to check ability of vedio capturing I want to google for some stuffs and record them
Google for Cats
Start time : 10/21/2016 6:56:37 PM
End time : 10/21/2016 6:56:51 PM
Google for Dogs
Start time : 10/21/2016 6:56:51 PM
End time : 10/21/2016 6:56:56 PM


TABLE OF INTERACTIONS WITH
ZONISAMIDE
See also: metabolized anticonvulsants
From the French ANSM drug interactions document of September 2016, p. 234
ZONISAMIDE RxNorm:39998 ATC:N03AX15 |
VALPROIC (ACID) AND, BY EXTRAPOLATION, VALPROMIDE CLASS CODE: N03AG0 |
Increase of the hyperammonemia, with increased risk of encephalopathy |
Precaution for use Regular clinical and biological monitoring. |


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