#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010 #install: C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A #OS: Windows XP 5.1 #Hostname: MATTHEWTANC0DD1 #Implementation: synthesis #Mon Feb 14 22:59:43 2011 $ Start of Compile #Mon Feb 14 22:59:43 2011 Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\igloo.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\io_controller.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\smartgen\clocks\clocks.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\clock_manager.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\jtag_shift.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\jtag_pc_poll.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\smartgen\program_table_mem\program_table_mem.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\function_search.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\program_table_loader.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\mem_manager.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\output_buffer.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\jtag_controller.v" @I::"C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\main.v" Verilog syntax check successful! File C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\smartgen\clocks\clocks.v changed - recompiling File C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\clock_manager.v changed - recompiling File C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\io_controller.v changed - recompiling File C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\program_table_loader.v changed - recompiling File C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\function_search.v changed - recompiling File C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\output_buffer.v changed - recompiling File C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\hdl\jtag_controller.v changed - recompiling Selecting top level module main @N:CG364 : igloo.v(1864) | Synthesizing module VCC @N:CG364 : igloo.v(1163) | Synthesizing module GND @N:CG364 : igloo.v(2447) | Synthesizing module PLL @N:CG364 : igloo.v(276) | Synthesizing module PLLINT @N:CG364 : clocks.v(5) | Synthesizing module clocks @N:CG364 : clock_manager.v(3) | Synthesizing module clock_manager @N:CG364 : io_controller.v(2) | Synthesizing module io_controller @N:CG364 : jtag_shift.v(59) | Synthesizing module jtag_shift @N:CG179 : jtag_shift.v(178) | Removing redundant assignment @N:CG179 : jtag_shift.v(217) | Removing redundant assignment @N:CG179 : jtag_shift.v(258) | Removing redundant assignment @A:CL106 : jtag_shift.v(99) | Register data_in_reg with async load is being synthesized in compatability mode. A Synthesis/Simulation mismatch is possible. @A: : jtag_shift.v(99) | Feedback mux created for signal bit_count[4:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @N:CG364 : jtag_pc_poll.v(1) | Synthesizing module jtag_pc_poll @A: : jtag_pc_poll.v(47) | Feedback mux created for signal data[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @N:CG364 : igloo.v(1996) | Synthesizing module RAM4K9 @N:CG364 : igloo.v(1283) | Synthesizing module INV @N:CG364 : program_table_mem.v(5) | Synthesizing module program_table_mem @N:CG364 : program_table_loader.v(2) | Synthesizing module program_table_loader @N:CG364 : function_search.v(27) | Synthesizing module function_search @W:CG133 : function_search.v(53) | No assignment to next_state @W:CG133 : function_search.v(54) | No assignment to min @W:CG133 : function_search.v(55) | No assignment to mid @W:CG133 : function_search.v(56) | No assignment to max @W:CL113 : function_search.v(61) | Feedback mux created for signal counting. @W:CL251 : function_search.v(61) | All reachable assignments to counting assign 1, register removed by optimization @N:CG364 : mem_manager.v(2) | Synthesizing module mem_manager @N:CG364 : output_buffer.v(2) | Synthesizing module output_buffer @N:CG364 : jtag_controller.v(2) | Synthesizing module jtag_controller @N:CG364 : main.v(2) | Synthesizing module main @W:CL159 : jtag_controller.v(25) | Input search_clk is unused @W:CL159 : output_buffer.v(18) | Input load_next is unused @W:CL159 : output_buffer.v(19) | Input cts is unused @W:CL159 : mem_manager.v(22) | Input search_reset is unused @A:CL153 : function_search.v(55) | *Unassigned bits of mid[9:0] have been referenced and are being tied to 0 - simulation mismatch possible @W:CL159 : function_search.v(45) | Input read_data is unused @N:CL201 : jtag_pc_poll.v(47) | Trying to extract state machine for register next_state Extracted state machine for register next_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : jtag_shift.v(99) | Trying to extract state machine for register next_state Extracted state machine for register next_state State machine has 13 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 @N:CL201 : io_controller.v(53) | Trying to extract state machine for register next_state Extracted state machine for register next_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL260 : clock_manager.v(81) | Pruning Register bit 7 of init[7:0] @W:CL260 : clock_manager.v(81) | Pruning Register bit 6 of init[7:0] @W:CL260 : clock_manager.v(81) | Pruning Register bit 5 of init[7:0] @W:CL260 : clock_manager.v(81) | Pruning Register bit 4 of init[7:0] @W:CL260 : clock_manager.v(81) | Pruning Register bit 3 of init[7:0] @W:CL260 : clock_manager.v(81) | Pruning Register bit 2 of init[7:0] @W:CL260 : clock_manager.v(81) | Pruning Register bit 1 of init[7:0] @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 14 22:59:44 2011 ###########################################################] Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version D-2009.12A @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO129 : clock_manager.v(81) | Sequential instance init[0] has been reduced to a combinational gate by constant propagation Automatic dissolve at startup in view:work.clock_manager(verilog) of u0(clocks) Automatic dissolve at startup in view:work.mem_manager(verilog) of u0(program_table_mem) Automatic dissolve at startup in view:work.main(verilog) of u0(clock_manager) @N:BN116 : clock_manager.v(59) | Removing sequential instance u0.osc12m of view:PrimLib.dff(prim) because there are no references to its outputs @N:BN116 : clock_manager.v(49) | Removing sequential instance u0.osc24m of view:PrimLib.dff(prim) because there are no references to its outputs @N:BN116 : clock_manager.v(39) | Removing sequential instance u0.osc48m_out of view:PrimLib.dff(prim) because there are no references to its outputs @W:BN132 : jtag_controller.v(109) | Removing sequential instance u3.output_buffer_enable, because it is equivalent to instance u3.search_enable Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Encoding state machine work.io_controller(verilog)-next_state[3:0] original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine work.jtag_pc_poll(verilog)-next_state[3:0] original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[15] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[14] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[13] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[12] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[11] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[10] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[9] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[8] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[6] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[5] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[4] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[3] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[1] is always 0, optimizing ... @W:MO161 : jtag_pc_poll.v(47) | Register bit shift_data_in[0] is always 0, optimizing ... @N: : jtag_shift.v(99) | Found counter in view:work.jtag_shift(verilog) inst bit_count[4:0] Encoding state machine work.jtag_shift(verilog)-next_state[12:0] original code -> new code 00000 -><PHONE_NUMBER>001 00001 -><PHONE_NUMBER>010 00010 -><PHONE_NUMBER>100 00011 -><PHONE_NUMBER>000 00100 -><PHONE_NUMBER>000 00101 -><PHONE_NUMBER>000 00110 -><PHONE_NUMBER>000 00111 -><PHONE_NUMBER>000 01000 -><PHONE_NUMBER>000 01001 -><PHONE_NUMBER>000 01010 -><PHONE_NUMBER>000 01011 -><PHONE_NUMBER>000 01100 -><PHONE_NUMBER>000 @N: : program_table_loader.v(22) | Found counter in view:work.program_table_loader(verilog) inst write_addr[9:0] @N: : function_search.v(61) | Found counter in view:work.function_search(verilog) inst result[15:0] Automatic dissolve during optimization of view:work.jtag_controller(verilog) of u0(jtag_pc_poll) Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 56MB) @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[15] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[15] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[14] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[14] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[13] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[13] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[12] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[12] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[11] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[11] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[10] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[10] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[9] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[9] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[8] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[8] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[7] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[7] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[6] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[6] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[5] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[5] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[4] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[4] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[3] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[2] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[1] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.last_result[0] of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.last_result[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : jtag_controller.v(84) | Removing sequential instance u3.new_result of view:PrimLib.dff(prim) because there are no references to its outputs @A:BN291 : jtag_controller.v(84) | Boundary register u3.new_result has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : program_table_loader.v(22) | Removing sequential instance u3.u1.u1.write_addr[9] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : program_table_loader.v(22) | Removing sequential instance u3.u1.u1.write_addr[8] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : program_table_loader.v(22) | Removing sequential instance u3.u1.u1.write_addr[7] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : program_table_loader.v(22) | Removing sequential instance u3.u1.u1.write_addr[6] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : program_table_loader.v(22) | Removing sequential instance u3.u1.u1.write_addr[5] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : program_table_loader.v(22) | Removing sequential instance u3.u1.u1.write_addr[4] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : program_table_loader.v(22) | Removing sequential instance u3.u1.u1.write_addr[3] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : program_table_loader.v(22) | Removing sequential instance u3.u1.u1.write_addr[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : program_table_loader.v(22) | Removing sequential instance u3.u1.u1.write_addr[1] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : program_table_loader.v(22) | Removing sequential instance u3.u1.u1.write_addr[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : program_table_mem.v(83) | Removing sequential instance u3.u1.u0.program_table_mem_R0C2 of view:IGLOO.RAM4K9(prim) because there are no references to its outputs @N:BN116 : program_table_mem.v(59) | Removing sequential instance u3.u1.u0.program_table_mem_R0C3 of view:IGLOO.RAM4K9(prim) because there are no references to its outputs @N:BN116 : program_table_mem.v(38) | Removing sequential instance u3.u1.u0.program_table_mem_R0C1 of view:IGLOO.RAM4K9(prim) because there are no references to its outputs @N:BN116 : program_table_mem.v(17) | Removing sequential instance u3.u1.u0.program_table_mem_R0C0 of view:IGLOO.RAM4K9(prim) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 56MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 56MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 56MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes -------------------------------------------------------------------------- u2.mode_reset / Q 47 : 26 asynchronous set/reset u3.pc_poll_enable / Q 28 u3.u0.shift_reset / Q 52 : 47 asynchronous set/reset u3.u0.u0.data_in_reg_6_sn_m2_0_0_o4 / Y 32 ========================================================================== @N:FP130 : | Promoting Net u3.u0.shift_reset on CLKINT I_2 @N:FP130 : | Promoting Net u3.pc_poll_done on CLKINT u3.u0.poll_done_inferred_clock @N:FP130 : | Promoting Net pld_ctr4_c on CLKBUF pld_ctr4_pad Replicating Combinational Instance u3.u0.u0.data_in_reg_6_sn_m2_0_0_o4, fanout 32 segments 2 Replicating Sequential Instance u3.pc_poll_enable, fanout 29 segments 2 Replicating Sequential Instance u2.mode_reset, fanout 48 segments 2 Replicating Sequential Instance u3.u0.u0.next_state[8], fanout 25 segments 2 Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Added 0 Buffers Added 4 Cells via replication Added 3 Sequential Cells via replication Added 1 Combinational Cells via replication @N:BN115 : mem_manager.v(49) | Removing instance u1 of view:work.program_table_loader(netlist) because there are no references to its outputs Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Writing Analyst data base C:\Documents and Settings\Administrator\My Documents\actel\TDB_FPGA\synthesis\main.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Writing EDIF Netlist and constraint files D-2009.12A Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) @W:MT420 : | Found inferred clock main|pld_ctr4 with period 10.42ns. A user-defined clock should be declared on object "p:pld_ctr4" @W:MT420 : | Found inferred clock main|u0.u0.osc6m_inferred_clock with period 10.42ns. A user-defined clock should be declared on object "n:osc6m" @W:MT420 : | Found inferred clock main|u0.u0.osc96m_inferred_clock with period 10.42ns. A user-defined clock should be declared on object "n:osc96m" @W:MT420 : | Found inferred clock function_search|done_inferred_clock with period 10.42ns. A user-defined clock should be declared on object "n:u3.u1.u2.done" @W:MT420 : | Found inferred clock jtag_pc_poll|poll_done_inferred_clock with period 10.42ns. A user-defined clock should be declared on object "n:u3.u0.poll_done" @W:MT420 : | Found inferred clock main|u0.u0.mcu_osc_inferred_clock with period 10.42ns. A user-defined clock should be declared on object "n:mcu_osc" ##### START OF TIMING REPORT #####[ # Timing Report written on Mon Feb 14 22:59:47 2011 # Top view: main Library name: IGLOO Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.85, tree_type = balanced_tree ) Requested Frequency: 96.0 MHz Wire load mode: top Wire load model: IGLOO Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -2.135 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------- jtag_pc_poll|poll_done_inferred_clock 96.0 MHz 97.3 MHz 10.417 10.276 0.141 inferred Inferred_clkgroup_2 main|u0.u0.mcu_osc_inferred_clock 96.0 MHz 334.2 MHz 10.417 2.992 7.425 inferred Inferred_clkgroup_4 main|u0.u0.osc6m_inferred_clock 96.0 MHz 79.7 MHz 10.417 12.552 -2.135 inferred Inferred_clkgroup_6 main|u0.u0.osc96m_inferred_clock 96.0 MHz 88.3 MHz 10.417 11.330 -0.913 inferred Inferred_clkgroup_5 ============================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------------------------------------------- jtag_pc_poll|poll_done_inferred_clock jtag_pc_poll|poll_done_inferred_clock | 10.417 0.141 | No paths - | No paths - | No paths - jtag_pc_poll|poll_done_inferred_clock main|u0.u0.osc6m_inferred_clock | Diff grp - | No paths - | No paths - | No paths - main|u0.u0.mcu_osc_inferred_clock main|u0.u0.mcu_osc_inferred_clock | 10.417 7.425 | No paths - | No paths - | No paths - main|u0.u0.osc96m_inferred_clock jtag_pc_poll|poll_done_inferred_clock | Diff grp - | No paths - | No paths - | No paths - main|u0.u0.osc96m_inferred_clock main|u0.u0.osc96m_inferred_clock | 10.417 -0.914 | No paths - | No paths - | No paths - main|u0.u0.osc96m_inferred_clock main|u0.u0.osc6m_inferred_clock | Diff grp - | No paths - | No paths - | No paths - main|u0.u0.osc6m_inferred_clock main|u0.u0.osc6m_inferred_clock | 10.417 -2.135 | No paths - | No paths - | No paths - ===================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: jtag_pc_poll|poll_done_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ u3.u1.u2.result[0] jtag_pc_poll|poll_done_inferred_clock DFN1C1 Q search_result[0] 0.885 0.141 u3.u1.u2.result[3] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 Q search_result[3] 0.885 0.168 u3.u1.u2.result[7] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 Q search_result[7] 0.885 0.206 u3.u1.u2.result[2] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 Q search_result[2] 0.885 0.304 u3.u1.u2.result[4] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 Q search_result[4] 0.885 0.342 u3.u1.u2.result[1] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 Q search_result[1] 0.885 0.392 u3.u1.u2.result[6] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 Q search_result[6] 0.885 1.390 u3.u1.u2.result[8] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 Q search_result[8] 0.885 1.640 u3.u1.u2.result[10] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 Q search_result[10] 0.885 1.724 u3.u1.u2.result[11] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 Q search_result[11] 0.885 1.974 ============================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------ u3.u1.u2.result[14] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 D result_n14 9.769 0.141 u3.u1.u2.result[11] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 D result_n11 9.769 0.158 u3.u1.u2.result[15] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 D result_n15 9.769 0.172 u3.u1.u2.result[12] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 D result_n12 9.769 0.189 u3.u1.u2.result[13] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 D result_n13 9.769 0.720 u3.u1.u2.result[10] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 D result_n10 9.769 0.736 u3.u1.u2.result[6] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 D result_n6 9.769 1.444 u3.u1.u2.result[7] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 D result_n7 9.769 1.476 u3.u1.u2.result[8] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 D result_n8 9.769 1.476 u3.u1.u2.result[9] jtag_pc_poll|poll_done_inferred_clock DFN1E1C1 D result_n9 9.769 1.881 ======================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.417 - Setup time: 0.647 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.769 - Propagation time: 9.628 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.141 Number of logic level(s): 4 Starting point: u3.u1.u2.result[0] / Q Ending point: u3.u1.u2.result[14] / D The start point is clocked by jtag_pc_poll|poll_done_inferred_clock [rising] on pin CLK The end point is clocked by jtag_pc_poll|poll_done_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------- u3.u1.u2.result[0] DFN1C1 Q Out 0.885 0.885 - search_result[0] Net - - 1.537 - 5 u3.u1.u2.result_RNIDDH1[1] NOR2B B In - 2.422 - u3.u1.u2.result_RNIDDH1[1] NOR2B Y Out 0.754 3.176 - result_c1 Net - - 1.422 - 4 u3.u1.u2.result_RNI2OT3[5] NOR3C C In - 4.598 - u3.u1.u2.result_RNI2OT3[5] NOR3C Y Out 0.770 5.369 - result_c8_m4_0_a2_5 Net - - 0.969 - 3 u3.u1.u2.result_RNI54CE[12] NOR3C C In - 6.337 - u3.u1.u2.result_RNI54CE[12] NOR3C Y Out 0.770 7.108 - result_c12 Net - - 0.969 - 3 u3.u1.u2.result_RNO[14] AX1C B In - 8.077 - u3.u1.u2.result_RNO[14] AX1C Y Out 1.165 9.242 - result_n14 Net - - 0.386 - 1 u3.u1.u2.result[14] DFN1E1C1 D In - 9.628 - ============================================================================================== Total path delay (propagation time + setup) of 10.276 is 4.993(48.6%) logic and 5.283(51.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: main|u0.u0.mcu_osc_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------- u0.osc4m_1 main|u0.u0.mcu_osc_inferred_clock DFN1 Q osc32k_c 0.885 7.425 ==================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------- u0.osc4m_1 main|u0.u0.mcu_osc_inferred_clock DFN1 D osc32k_c_i 9.769 7.425 ======================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.417 - Setup time: 0.647 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.769 - Propagation time: 2.345 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.424 Number of logic level(s): 1 Starting point: u0.osc4m_1 / Q Ending point: u0.osc4m_1 / D The start point is clocked by main|u0.u0.mcu_osc_inferred_clock [rising] on pin CLK The end point is clocked by main|u0.u0.mcu_osc_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------- u0.osc4m_1 DFN1 Q Out 0.885 0.885 - osc32k_c Net - - 0.464 - 2 u0.osc4m_1_RNO INV A In - 1.349 - u0.osc4m_1_RNO INV Y Out 0.610 1.959 - osc32k_c_i Net - - 0.386 - 1 u0.osc4m_1 DFN1 D In - 2.345 - ============================================================================= Total path delay (propagation time + setup) of 2.992 is 2.142(71.6%) logic and 0.850(28.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: main|u0.u0.osc6m_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------- u3.u2.output_data[14] main|u0.u0.osc6m_inferred_clock DFN1 Q func_data[14] 0.885 -2.135 u3.u2.output_data[6] main|u0.u0.osc6m_inferred_clock DFN1 Q func_data[6] 0.885 -2.022 u3.u2.output_data[13] main|u0.u0.osc6m_inferred_clock DFN1 Q func_data[13] 0.885 -1.335 u3.u2.output_data[5] main|u0.u0.osc6m_inferred_clock DFN1 Q func_data[5] 0.885 -1.222 u3.u2.output_data[15] main|u0.u0.osc6m_inferred_clock DFN1 Q func_data[15] 0.885 -1.199 u3.u2.output_data[7] main|u0.u0.osc6m_inferred_clock DFN1 Q func_data[7] 0.885 -1.087 u3.u2.output_data[12] main|u0.u0.osc6m_inferred_clock DFN1 Q func_data[12] 0.885 -0.997 u3.u2.output_data[10] main|u0.u0.osc6m_inferred_clock DFN1 Q func_data[10] 0.885 -0.936 u3.u2.output_data[4] main|u0.u0.osc6m_inferred_clock DFN1 Q func_data[4] 0.885 -0.884 u3.u2.output_data[2] main|u0.u0.osc6m_inferred_clock DFN1 Q func_data[2] 0.885 -0.823 =================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------ u3.u2.output_data[0] main|u0.u0.osc6m_inferred_clock DFN1 D output_data_RNO[0] 9.728 -2.135 u3.u2.output_data[1] main|u0.u0.osc6m_inferred_clock DFN1 D output_data_RNO[1] 9.728 -2.135 u3.u2.output_data[2] main|u0.u0.osc6m_inferred_clock DFN1 D output_data_RNO[2] 9.728 -2.135 u3.u2.output_data[3] main|u0.u0.osc6m_inferred_clock DFN1 D output_data_RNO[3] 9.728 -2.135 u3.u2.output_data[4] main|u0.u0.osc6m_inferred_clock DFN1 D output_data_RNO[4] 9.728 -2.135 u3.u2.output_data[5] main|u0.u0.osc6m_inferred_clock DFN1 D output_data_RNO[5] 9.728 -2.135 u3.u2.output_data[6] main|u0.u0.osc6m_inferred_clock DFN1 D output_data_RNO[6] 9.728 -2.135 u3.u2.output_data[7] main|u0.u0.osc6m_inferred_clock DFN1 D output_data_RNO[7] 9.728 -2.135 u3.u2.output_data[8] main|u0.u0.osc6m_inferred_clock DFN1 D output_data_RNO[8] 9.728 -2.135 u3.u2.output_data[9] main|u0.u0.osc6m_inferred_clock DFN1 D output_data_RNO[9] 9.728 -2.135 ======================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.417 - Setup time: 0.689 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.728 - Propagation time: 11.863 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -2.135 Number of logic level(s): 7 Starting point: u3.u2.output_data[14] / Q Ending point: u3.u2.output_data[0] / D The start point is clocked by main|u0.u0.osc6m_inferred_clock [rising] on pin CLK The end point is clocked by main|u0.u0.osc6m_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- u3.u2.output_data[14] DFN1 Q Out 0.885 0.885 - func_data[14] Net - - 0.969 - 3 u3.u2.output_data_RNIHLQ7[14] XOR2 B In - 1.854 - u3.u2.output_data_RNIHLQ7[14] XOR2 Y Out 1.125 2.980 - N_1_33 Net - - 0.386 - 1 u3.u2.output_data_RNI4BLF[15] XA1C C In - 3.366 - u3.u2.output_data_RNI4BLF[15] XA1C Y Out 0.413 3.779 - G_1_3 Net - - 0.386 - 1 u3.u2.output_data_RNI0MAV[12] NOR3A A In - 4.166 - u3.u2.output_data_RNI0MAV[12] NOR3A Y Out 0.770 4.936 - G_1_9 Net - - 0.386 - 1 u3.u2.output_data_RNIO3OH1[9] NOR3C C In - 5.322 - u3.u2.output_data_RNIO3OH1[9] NOR3C Y Out 0.770 6.093 - G_1_12 Net - - 0.386 - 1 u3.u2.output_data_RNI0EN22[1] AO1B B In - 6.479 - u3.u2.output_data_RNI0EN22[1] AO1B Y Out 0.716 7.196 - N_2_0 Net - - 2.664 - 17 u3.u2.output_data_RNO_0[0] MX2 S In - 9.860 - u3.u2.output_data_RNO_0[0] MX2 Y Out 0.476 10.336 - N_2_1 Net - - 0.386 - 1 u3.u2.output_data_RNO[0] NOR2A A In - 10.722 - u3.u2.output_data_RNO[0] NOR2A Y Out 0.754 11.476 - output_data_RNO[0] Net - - 0.386 - 1 u3.u2.output_data[0] DFN1 D In - 11.863 - ============================================================================================= Total path delay (propagation time + setup) of 12.552 is 6.600(52.6%) logic and 5.951(47.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.417 - Setup time: 0.689 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.728 - Propagation time: 11.863 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -2.135 Number of logic level(s): 7 Starting point: u3.u2.output_data[14] / Q Ending point: u3.u2.output_data[15] / D The start point is clocked by main|u0.u0.osc6m_inferred_clock [rising] on pin CLK The end point is clocked by main|u0.u0.osc6m_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- u3.u2.output_data[14] DFN1 Q Out 0.885 0.885 - func_data[14] Net - - 0.969 - 3 u3.u2.output_data_RNIHLQ7[14] XOR2 B In - 1.854 - u3.u2.output_data_RNIHLQ7[14] XOR2 Y Out 1.125 2.980 - N_1_33 Net - - 0.386 - 1 u3.u2.output_data_RNI4BLF[15] XA1C C In - 3.366 - u3.u2.output_data_RNI4BLF[15] XA1C Y Out 0.413 3.779 - G_1_3 Net - - 0.386 - 1 u3.u2.output_data_RNI0MAV[12] NOR3A A In - 4.166 - u3.u2.output_data_RNI0MAV[12] NOR3A Y Out 0.770 4.936 - G_1_9 Net - - 0.386 - 1 u3.u2.output_data_RNIO3OH1[9] NOR3C C In - 5.322 - u3.u2.output_data_RNIO3OH1[9] NOR3C Y Out 0.770 6.093 - G_1_12 Net - - 0.386 - 1 u3.u2.output_data_RNI0EN22[1] AO1B B In - 6.479 - u3.u2.output_data_RNI0EN22[1] AO1B Y Out 0.716 7.196 - N_2_0 Net - - 2.664 - 17 u3.u2.output_data_RNO_0[15] MX2 S In - 9.860 - u3.u2.output_data_RNO_0[15] MX2 Y Out 0.476 10.336 - N_17_0 Net - - 0.386 - 1 u3.u2.output_data_RNO[15] NOR2A A In - 10.722 - u3.u2.output_data_RNO[15] NOR2A Y Out 0.754 11.476 - output_data_RNO[15] Net - - 0.386 - 1 u3.u2.output_data[15] DFN1 D In - 11.863 - ============================================================================================= Total path delay (propagation time + setup) of 12.552 is 6.600(52.6%) logic and 5.951(47.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.417 - Setup time: 0.689 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.728 - Propagation time: 11.863 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -2.135 Number of logic level(s): 7 Starting point: u3.u2.output_data[14] / Q Ending point: u3.u2.output_data[14] / D The start point is clocked by main|u0.u0.osc6m_inferred_clock [rising] on pin CLK The end point is clocked by main|u0.u0.osc6m_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- u3.u2.output_data[14] DFN1 Q Out 0.885 0.885 - func_data[14] Net - - 0.969 - 3 u3.u2.output_data_RNIHLQ7[14] XOR2 B In - 1.854 - u3.u2.output_data_RNIHLQ7[14] XOR2 Y Out 1.125 2.980 - N_1_33 Net - - 0.386 - 1 u3.u2.output_data_RNI4BLF[15] XA1C C In - 3.366 - u3.u2.output_data_RNI4BLF[15] XA1C Y Out 0.413 3.779 - G_1_3 Net - - 0.386 - 1 u3.u2.output_data_RNI0MAV[12] NOR3A A In - 4.166 - u3.u2.output_data_RNI0MAV[12] NOR3A Y Out 0.770 4.936 - G_1_9 Net - - 0.386 - 1 u3.u2.output_data_RNIO3OH1[9] NOR3C C In - 5.322 - u3.u2.output_data_RNIO3OH1[9] NOR3C Y Out 0.770 6.093 - G_1_12 Net - - 0.386 - 1 u3.u2.output_data_RNI0EN22[1] AO1B B In - 6.479 - u3.u2.output_data_RNI0EN22[1] AO1B Y Out 0.716 7.196 - N_2_0 Net - - 2.664 - 17 u3.u2.output_data_RNO_0[14] MX2 S In - 9.860 - u3.u2.output_data_RNO_0[14] MX2 Y Out 0.476 10.336 - N_16_0 Net - - 0.386 - 1 u3.u2.output_data_RNO[14] NOR2A A In - 10.722 - u3.u2.output_data_RNO[14] NOR2A Y Out 0.754 11.476 - output_data_RNO[14] Net - - 0.386 - 1 u3.u2.output_data[14] DFN1 D In - 11.863 - ============================================================================================= Total path delay (propagation time + setup) of 12.552 is 6.600(52.6%) logic and 5.951(47.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.417 - Setup time: 0.689 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.728 - Propagation time: 11.863 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -2.135 Number of logic level(s): 7 Starting point: u3.u2.output_data[14] / Q Ending point: u3.u2.output_data[13] / D The start point is clocked by main|u0.u0.osc6m_inferred_clock [rising] on pin CLK The end point is clocked by main|u0.u0.osc6m_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- u3.u2.output_data[14] DFN1 Q Out 0.885 0.885 - func_data[14] Net - - 0.969 - 3 u3.u2.output_data_RNIHLQ7[14] XOR2 B In - 1.854 - u3.u2.output_data_RNIHLQ7[14] XOR2 Y Out 1.125 2.980 - N_1_33 Net - - 0.386 - 1 u3.u2.output_data_RNI4BLF[15] XA1C C In - 3.366 - u3.u2.output_data_RNI4BLF[15] XA1C Y Out 0.413 3.779 - G_1_3 Net - - 0.386 - 1 u3.u2.output_data_RNI0MAV[12] NOR3A A In - 4.166 - u3.u2.output_data_RNI0MAV[12] NOR3A Y Out 0.770 4.936 - G_1_9 Net - - 0.386 - 1 u3.u2.output_data_RNIO3OH1[9] NOR3C C In - 5.322 - u3.u2.output_data_RNIO3OH1[9] NOR3C Y Out 0.770 6.093 - G_1_12 Net - - 0.386 - 1 u3.u2.output_data_RNI0EN22[1] AO1B B In - 6.479 - u3.u2.output_data_RNI0EN22[1] AO1B Y Out 0.716 7.196 - N_2_0 Net - - 2.664 - 17 u3.u2.output_data_RNO_0[13] MX2 S In - 9.860 - u3.u2.output_data_RNO_0[13] MX2 Y Out 0.476 10.336 - N_15_0 Net - - 0.386 - 1 u3.u2.output_data_RNO[13] NOR2A A In - 10.722 - u3.u2.output_data_RNO[13] NOR2A Y Out 0.754 11.476 - output_data_RNO[13] Net - - 0.386 - 1 u3.u2.output_data[13] DFN1 D In - 11.863 - ============================================================================================= Total path delay (propagation time + setup) of 12.552 is 6.600(52.6%) logic and 5.951(47.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.417 - Setup time: 0.689 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.728 - Propagation time: 11.863 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -2.135 Number of logic level(s): 7 Starting point: u3.u2.output_data[14] / Q Ending point: u3.u2.output_data[12] / D The start point is clocked by main|u0.u0.osc6m_inferred_clock [rising] on pin CLK The end point is clocked by main|u0.u0.osc6m_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- u3.u2.output_data[14] DFN1 Q Out 0.885 0.885 - func_data[14] Net - - 0.969 - 3 u3.u2.output_data_RNIHLQ7[14] XOR2 B In - 1.854 - u3.u2.output_data_RNIHLQ7[14] XOR2 Y Out 1.125 2.980 - N_1_33 Net - - 0.386 - 1 u3.u2.output_data_RNI4BLF[15] XA1C C In - 3.366 - u3.u2.output_data_RNI4BLF[15] XA1C Y Out 0.413 3.779 - G_1_3 Net - - 0.386 - 1 u3.u2.output_data_RNI0MAV[12] NOR3A A In - 4.166 - u3.u2.output_data_RNI0MAV[12] NOR3A Y Out 0.770 4.936 - G_1_9 Net - - 0.386 - 1 u3.u2.output_data_RNIO3OH1[9] NOR3C C In - 5.322 - u3.u2.output_data_RNIO3OH1[9] NOR3C Y Out 0.770 6.093 - G_1_12 Net - - 0.386 - 1 u3.u2.output_data_RNI0EN22[1] AO1B B In - 6.479 - u3.u2.output_data_RNI0EN22[1] AO1B Y Out 0.716 7.196 - N_2_0 Net - - 2.664 - 17 u3.u2.output_data_RNO_0[12] MX2 S In - 9.860 - u3.u2.output_data_RNO_0[12] MX2 Y Out 0.476 10.336 - N_14_0 Net - - 0.386 - 1 u3.u2.output_data_RNO[12] NOR2A A In - 10.722 - u3.u2.output_data_RNO[12] NOR2A Y Out 0.754 11.476 - output_data_RNO[12] Net - - 0.386 - 1 u3.u2.output_data[12] DFN1 D In - 11.863 - ============================================================================================= Total path delay (propagation time + setup) of 12.552 is 6.600(52.6%) logic and 5.951(47.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: main|u0.u0.osc96m_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ u3.u0.u0.next_state[10] main|u0.u0.osc96m_inferred_clock DFN1C1 Q next_state[10] 0.885 -0.913 u3.pc_poll_enable_0 main|u0.u0.osc96m_inferred_clock DFN1E1 Q pc_poll_enable_0 0.885 -0.600 u3.u0.u0.next_state_0[8] main|u0.u0.osc96m_inferred_clock DFN1C1 Q next_state_0[8] 0.885 -0.195 u3.u0.u0.bit_count[0] main|u0.u0.osc96m_inferred_clock DFN1E1 Q bit_count_c0 0.885 0.816 u3.u0.next_state[0] main|u0.u0.osc96m_inferred_clock DFN1E1C1 Q next_state[0] 0.697 1.208 u3.u0.u0.bit_count[1] main|u0.u0.osc96m_inferred_clock DFN1E1 Q bit_count[1] 0.885 1.405 u3.u0.u0.bit_count[2] main|u0.u0.osc96m_inferred_clock DFN1E1 Q bit_count[2] 0.885 1.553 u3.u0.u0.done main|u0.u0.osc96m_inferred_clock DFN1C1 Q shift_done 0.885 1.688 u3.u0.u0.bit_count[4] main|u0.u0.osc96m_inferred_clock DFN1E1 Q bit_count[4] 0.885 1.739 u2.mode0 main|u0.u0.osc96m_inferred_clock DFN1E0 Q mode0 0.697 1.983 ============================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ u3.u0.u0.data_in_reg[2] main|u0.u0.osc96m_inferred_clock DFN1P1C1 D data_in_reg_6[2] 7.174 -0.913 u3.u0.u0.data_in_reg[7] main|u0.u0.osc96m_inferred_clock DFN1P1C1 D data_in_reg_6[7] 7.174 -0.913 u3.u0.u0.tms main|u0.u0.osc96m_inferred_clock DFN1E1C1 D tms_6 9.811 0.816 u3.u0.data[0] main|u0.u0.osc96m_inferred_clock DFN1E1 E data_0_sqmuxa 9.686 1.183 u3.u0.data[1] main|u0.u0.osc96m_inferred_clock DFN1E1 E data_0_sqmuxa 9.686 1.183 u3.u0.data[2] main|u0.u0.osc96m_inferred_clock DFN1E1 E data_0_sqmuxa 9.686 1.183 u3.u0.data[3] main|u0.u0.osc96m_inferred_clock DFN1E1 E data_0_sqmuxa 9.686 1.183 u3.u0.data[4] main|u0.u0.osc96m_inferred_clock DFN1E1 E data_0_sqmuxa 9.686 1.183 u3.u0.data[5] main|u0.u0.osc96m_inferred_clock DFN1E1 E data_0_sqmuxa 9.686 1.183 u3.u0.data[6] main|u0.u0.osc96m_inferred_clock DFN1E1 E data_0_sqmuxa 9.686 1.183 ============================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.417 - Setup time: 3.243 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.174 - Propagation time: 8.087 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.914 Number of logic level(s): 2 Starting point: u3.u0.u0.next_state[10] / Q Ending point: u3.u0.u0.data_in_reg[2] / D The start point is clocked by main|u0.u0.osc96m_inferred_clock [rising] on pin CLK The end point is clocked by main|u0.u0.osc96m_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- u3.u0.u0.next_state[10] DFN1C1 Q Out 0.885 0.885 - next_state[10] Net - - 2.963 - 24 u3.u0.u0.next_state_0_RNIQTF6[8] OAI1 B In - 3.848 - u3.u0.u0.next_state_0_RNIQTF6[8] OAI1 Y Out 0.666 4.515 - N_235_0 Net - - 2.610 - 16 u3.u0.u0.data_in_reg_RNO_0[2] MX2 S In - 7.125 - u3.u0.u0.data_in_reg_RNO_0[2] MX2 Y Out 0.576 7.701 - data_in_reg_6[2] Net - - 0.386 - 1 u3.u0.u0.data_in_reg[2] DFN1P1C1 D In - 8.087 - =================================================================================================== Total path delay (propagation time + setup) of 11.330 is 5.371(47.4%) logic and 5.960(52.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.417 - Setup time: 3.243 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.174 - Propagation time: 8.087 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.914 Number of logic level(s): 2 Starting point: u3.u0.u0.next_state[10] / Q Ending point: u3.u0.u0.data_in_reg[7] / D The start point is clocked by main|u0.u0.osc96m_inferred_clock [rising] on pin CLK The end point is clocked by main|u0.u0.osc96m_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- u3.u0.u0.next_state[10] DFN1C1 Q Out 0.885 0.885 - next_state[10] Net - - 2.963 - 24 u3.u0.u0.next_state_0_RNIQTF6[8] OAI1 B In - 3.848 - u3.u0.u0.next_state_0_RNIQTF6[8] OAI1 Y Out 0.666 4.515 - N_235_0 Net - - 2.610 - 16 u3.u0.u0.data_in_reg_RNO_0[7] MX2 S In - 7.125 - u3.u0.u0.data_in_reg_RNO_0[7] MX2 Y Out 0.576 7.701 - data_in_reg_6[7] Net - - 0.386 - 1 u3.u0.u0.data_in_reg[7] DFN1P1C1 D In - 8.087 - =================================================================================================== Total path delay (propagation time + setup) of 11.330 is 5.371(47.4%) logic and 5.960(52.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.417 - Setup time: 3.243 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.174 - Propagation time: 7.774 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.600 Number of logic level(s): 2 Starting point: u3.pc_poll_enable_0 / Q Ending point: u3.u0.u0.data_in_reg[2] / D The start point is clocked by main|u0.u0.osc96m_inferred_clock [rising] on pin CLK The end point is clocked by main|u0.u0.osc96m_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- u3.pc_poll_enable_0 DFN1E1 Q Out 0.885 0.885 - pc_poll_enable_0 Net - - 2.556 - 15 u3.u0.u0.next_state_0_RNIQTF6[8] OAI1 C In - 3.441 - u3.u0.u0.next_state_0_RNIQTF6[8] OAI1 Y Out 0.760 4.201 - N_235_0 Net - - 2.610 - 16 u3.u0.u0.data_in_reg_RNO_0[2] MX2 S In - 6.811 - u3.u0.u0.data_in_reg_RNO_0[2] MX2 Y Out 0.576 7.388 - data_in_reg_6[2] Net - - 0.386 - 1 u3.u0.u0.data_in_reg[2] DFN1P1C1 D In - 7.774 - =================================================================================================== Total path delay (propagation time + setup) of 11.017 is 5.465(49.6%) logic and 5.552(50.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.417 - Setup time: 3.243 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.174 - Propagation time: 7.774 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.600 Number of logic level(s): 2 Starting point: u3.pc_poll_enable_0 / Q Ending point: u3.u0.u0.data_in_reg[7] / D The start point is clocked by main|u0.u0.osc96m_inferred_clock [rising] on pin CLK The end point is clocked by main|u0.u0.osc96m_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- u3.pc_poll_enable_0 DFN1E1 Q Out 0.885 0.885 - pc_poll_enable_0 Net - - 2.556 - 15 u3.u0.u0.next_state_0_RNIQTF6[8] OAI1 C In - 3.441 - u3.u0.u0.next_state_0_RNIQTF6[8] OAI1 Y Out 0.760 4.201 - N_235_0 Net - - 2.610 - 16 u3.u0.u0.data_in_reg_RNO_0[7] MX2 S In - 6.811 - u3.u0.u0.data_in_reg_RNO_0[7] MX2 Y Out 0.576 7.388 - data_in_reg_6[7] Net - - 0.386 - 1 u3.u0.u0.data_in_reg[7] DFN1P1C1 D In - 7.774 - =================================================================================================== Total path delay (propagation time + setup) of 11.017 is 5.465(49.6%) logic and 5.552(50.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.417 - Setup time: 3.243 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.174 - Propagation time: 7.369 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.195 Number of logic level(s): 2 Starting point: u3.u0.u0.next_state_0[8] / Q Ending point: u3.u0.u0.data_in_reg[2] / D The start point is clocked by main|u0.u0.osc96m_inferred_clock [rising] on pin CLK The end point is clocked by main|u0.u0.osc96m_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- u3.u0.u0.next_state_0[8] DFN1C1 Q Out 0.885 0.885 - next_state_0[8] Net - - 2.447 - 13 u3.u0.u0.next_state_0_RNIQTF6[8] OAI1 A In - 3.333 - u3.u0.u0.next_state_0_RNIQTF6[8] OAI1 Y Out 0.464 3.796 - N_235_0 Net - - 2.610 - 16 u3.u0.u0.data_in_reg_RNO_0[2] MX2 S In - 6.406 - u3.u0.u0.data_in_reg_RNO_0[2] MX2 Y Out 0.576 6.983 - data_in_reg_6[2] Net - - 0.386 - 1 u3.u0.u0.data_in_reg[2] DFN1P1C1 D In - 7.369 - =================================================================================================== Total path delay (propagation time + setup) of 10.612 is 5.168(48.7%) logic and 5.444(51.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: AGLN125V5Z_VQFP100_Std Report for cell main.verilog Core Cell usage: cell count area count*area AO1 4 1.0 4.0 AO1A 1 1.0 1.0 AO1B 3 1.0 3.0 AO1D 4 1.0 4.0 AOI1 1 1.0 1.0 AOI1B 1 1.0 1.0 AX1C 9 1.0 9.0 AX1D 1 1.0 1.0 CLKINT 2 0.0 0.0 GND 10 0.0 0.0 INV 1 1.0 1.0 MAJ3 1 1.0 1.0 MX2 48 1.0 48.0 MX2A 1 1.0 1.0 MX2B 1 1.0 1.0 MX2C 3 1.0 3.0 NOR2 10 1.0 10.0 NOR2A 32 1.0 32.0 NOR2B 25 1.0 25.0 NOR3 4 1.0 4.0 NOR3A 7 1.0 7.0 NOR3B 2 1.0 2.0 NOR3C 8 1.0 8.0 OA1 1 1.0 1.0 OA1A 2 1.0 2.0 OA1B 4 1.0 4.0 OA1C 5 1.0 5.0 OAI1 3 1.0 3.0 OR2 4 1.0 4.0 OR2A 10 1.0 10.0 OR2B 2 1.0 2.0 OR3 2 1.0 2.0 OR3A 1 1.0 1.0 OR3B 2 1.0 2.0 OR3C 1 1.0 1.0 PLL 1 0.0 0.0 PLLINT 1 0.0 0.0 VCC 10 0.0 0.0 XA1B 2 1.0 2.0 XA1C 7 1.0 7.0 XOR2 18 1.0 18.0 DFN1 20 1.0 20.0 DFN1C1 9 1.0 9.0 DFN1E0 7 1.0 7.0 DFN1E0C1 30 1.0 30.0 DFN1E1 30 1.0 30.0 DFN1E1C1 27 1.0 27.0 DFN1E1P1 5 1.0 5.0 DFN1P1 1 1.0 1.0 DFN1P1C1 2 1.0 2.0 ----- ---------- TOTAL 386 362.0 IO Cell usage: cell count BIBUF 3 CLKBUF 1 INBUF 6 OUTBUF 7 TRIBUFF 13 ----- TOTAL 30 Core Cells : 362 of 3072 (12%) IO Cells : 30 of 133 (23%) RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Mon Feb 14 22:59:47 2011 ###########################################################]


{% extends "layout.html" %} {% block body %}
This is demo application that shows Flask-Mongoengine features and integrations.
Feel free to open Flask debug toolbar after any action to check executed database requests.
If you use this application for first time, it is good idea to generate some fake data.
Data will be generated inside docker container database. Two databases will be used to show Flask Debug Panel integration capabilities.
You can also delete all data, to test forms only.
{% if message %}{{ message }}
{% endif %} {% endblock %}


BXDatabaseObject conforms to NSKeyValueObserving and uses self-updating collections for storing related objects; changes in them may thus be tracked with KVO.
BXSynchronizedArrayController's contents will be updated automatically. BXDatabaseContext's fetch methods also have the option to return a self-updating array instead of an ordinary one. In this case, the collection's owner has to be specified for KVO notifications to be posted. See the collection classes' documentation for details.
Another, a more low-level means of tracking changes is observing NSNotifications. Notifications on entity changes will be posted to the relevant context's notification center. The notification object will be a BXEntityDescription which corresponds to the table where the change happened. The names of the notifications are:
At the time the notifications are posted, database objects and self-updating collections will already have been updated.
When inserting, updating or deleting rows, BaseTen notices (and posts notifications of) changes that occur as a result of database triggers or rules firing. The only requirement is that said changes are to entities other than the one being changed by BaseTen; changes to the same entity will be ignored.


Public Member Functions | |
| SModelNodeInfo () | |
| SModelNodeInfo (const SModelNodeInfo &info) | |
| ~SModelNodeInfo () | |
| SModelNodeInfo & | operator= (const SModelNodeInfo &info) |
Public Attributes | |
| tstring | nodeName |
| node name. | |
| MMat4x4 * | xform |
| std::vector< SModelNodeMeshInfo > | modelNodeMeshInfoVec |
Definition at line 80 of file GrParse.cpp.
| SModelNodeInfo::SModelNodeInfo | ( | ) | [inline] |
Definition at line 82 of file GrParse.cpp.
| SModelNodeInfo::SModelNodeInfo | ( | const SModelNodeInfo & | info | ) | [inline] |
Definition at line 84 of file GrParse.cpp.
| SModelNodeInfo::~SModelNodeInfo | ( | ) | [inline] |
Definition at line 92 of file GrParse.cpp.
| SModelNodeInfo& SModelNodeInfo::operator= | ( | const SModelNodeInfo & | info | ) | [inline] |
Definition at line 94 of file GrParse.cpp.
| std::vector< SModelNodeMeshInfo > SModelNodeInfo::modelNodeMeshInfoVec |
Definition at line 111 of file GrParse.cpp.
Definition at line 110 of file GrParse.cpp.


|
TrackracerAR
0.9.2
|
Public Attributes | |
| BuildLoadUI.Settings | LoadingSettings |
| DialogBuilder.Settings | DialogSettings |
| DialogFactory.Settings | DialogFactorySettings |
| DialogFactory.Settings GameSettings.UISettings.DialogFactorySettings |
| DialogBuilder.Settings GameSettings.UISettings.DialogSettings |
| BuildLoadUI.Settings GameSettings.UISettings.LoadingSettings |


City Support
☰
Users
Warehouses
Sponsors
Select Sponsor Types
Donation Id
Item Name
Description
Quantity
Claim
Claim Item
×
Donation Id:
Quantity:
Claim Item
×
Donation Id:
Quantity:


BACK-END SPECIFICATION
LIST OF api/routes. See code comments for more info
The buttons don't work and it's not intended to be part of
the deployed project. DOES NOT include home routes or dashboard routes
Color Code:
FINISHED and IMPLEMENTED
FINISHED but UN-IMPLEMENTED
FINISHED but UNNECESSARY
FUTURE FUNCTION
The "(MR1), (PR2), etc. values are an index into the corresponding
route source file - for example MR1 == meeting-routes MR1.
API ROUTES: FINISHED and IMPLEMENTED
(MR2) FIND ALL MEETINGS by a specified ORGANIZER
dashboard-routes (logged in user)
(MR4) CREATE NEW MEETING
FIND ALL MEETINGS for SELECTED PARTICIPANT
dashboard-routes (logged in user)
(UR3) LOGIN
(UR4) LOGOUT
(UR5) SIGNUP
API ROUTES: FINISHED but UNIMPLEMENTED
GET/SET the Accepted flag for a PARTICIPANT
DELETE a MEETING from a USER
DELETE a USER from a MEETING
(MR3) FIND ONE MEETING by its meeting id
(MR5) UPDATE MEETING by its meeting id
(MR6) DELETE MEETING by its ID
FIND ALL PARTICIPANTS for SELECTED MEETING
ADD PARTICIPANTS TO SELECTED MEETING
(UR7) DELETE USER
GET PARTICIPANTS based on meeting ID
(UR1) FIND ALL USERS (so we can add to meeting)
ADD ONE USER as PARTICIPANT in selected MEETING
FINISHED but probably UNNECESSARY
(MR1) FIND ALL MEEETINGS for ALL USERS
(UR2) FIND USER by USER id
(UR6) UPDATE USER INFO by user id
to cahnge user name or password
FUTURE FUNCTION - no current API Route
Find meeting by date or time
ADD MULTIPLE USERS as PARTICIPANTS in selected MEETING


(~2-5X Extract followed by some Valerian root)
On my 6th time smoking Salvia divinorum, I did it alone, finishing the extract that I had tried the day before with C__. I was sitting on my couch with earphones playing music (an ambient track I composed) and I inhaled a bowl of extract in 2 hits. The head-spin effects came very very quickly and I could REALLY tell that this was a 5X extract.
When everything was unfolding before my eyes, I decided to close them to concentrate on the vortex. Behind closed eyelids, there was a lot going on as I felt my consciousness leave the back of my head very quickly. This is the moment that I never remember what happens, the moment that I don't know what is going on. With music very close to my ears, it was easy to concentrate on what was going on, especially because I composed the music myself, so the feelings were already all mine.
At this moment, I somewhat 'forgot' who I was. I didn't know who I was and why I existed. I was alienated of my own self, it was almost scary considering I was alone. I completely forgot the meaning of my immediate past and my immediate future as they became very vivid and apparent to me. At this point, I was thinking to myself: 'Oh no, I forgot who I am and how to live!', in astonishment.
A few minutes later when the effects began to decrease, my thoughts calmed down. I strongly think that music, if created with the right intention, can induce the thoughts of a Salvia trip. With my eyes still closed, I wondered how long I had been sitting there, I had absolutely no idea. I thought that the song playing wasn't over yet so it had not been 10 minutes yet. About 8 minutes later, I stood up finally.
Basically, what happened is that I stopped thinking in a linear way of past, present, future and was conscious of all three at a different point of view. After T+30 minutes I felt completely normal again, only more relaxed and with enhanced hearing, smelling and tasting senses. I consumed a teaspoon of Valerian root in cold water which chases the insomnia I often get after Salvia experiences and set me in a very relaxed state, I think I recall my astral body wanting to exit my physical body twice, which is what the effects of the roots create.
For the first time, I really think the Salvia being introduced herself to me... (finally) I think she said her name is Marie or Maria, that's what I remember. I have learned not to smoke extract without a sitter, who knows what I could have done with any higher dose!
Experience Reports are the writings and opinions of the individual authors who submit them.
Some of the activities described are dangerous and/or illegal and none are recommended by Erowid.


ARM Tech Conference 2016 - Santa Clara Conention Center
by Wenwei Weng
The biggest ARM event ARM techcon took place Oct 25-27 2016 in Santa Clara convention center. I took half day to attend the exibition on Oct 27th. It is very good learning expereince.
In this post, I will share my thoughts and waht are learned.
Overall summary
- There are more vendors in exibition than last year. However the scale is smaller than Intel IDF.
- There are three types of vendors: hardware, software, tools, system integrator.
- Most hardware vendors are for embedded systems targeting IOT, networking, automotive. Surprisingly vendors like Qualcomm, Samsung, MediaTek are absent, let alone Apple, Huawei. Marvell is absent as well.
- In the processor market, main players are Intel and ARM. The vendors are giving up powerpc, mips architecture.
- Nearly every hardware vendor play games by licensing ARM licence or reference implementation, plus its own strength, i.e. FPGA, memory, peripheral controllers etc.
Vendors
applied micro (apm) - ARM chip vendor , http://www.apm.com
apm is showing its flagship ARM chip X-Gene 2, 64-bit ARMv8-A architecture. It is targeting at server market, which is still pretty tough with limited success so far. Even AMD is exiting this market.
APM is showing ARM based blade vs Intel based blade server above. With Intel dominating the server market, and richness of applications of x86, it is tough for ARM to gain market share. Peopel are not willing to take the risk to migrate. Howerver there is area like in DC, providing IO/not computing, which could fit ARM.
NXP - ARM chip vendor, http://www.nxp.com
NXP ARM chip mainly comes from freescale aquization, plus its own ARM MCU.  With acquization, Qualcomm will have ARM product line for mobile phone (from its own), for networking/embedded (from freescale), and for automotive/consumer electronics (from NXP itsself).
The competitive advantage from NXP/freeacale is periperals like ethernet controller, SD controller, USB controller, crypto, these are widely used in the industry. E.g. Cisco IOS code has mature driver for ethernet, this makes a natrual choice for Cisco to choose NXP.
Analog Device - ARM chip vendor, http://www.analog.com
Analog Device is the leading analog to digital convert chip provider. It takes its advantge and integrate its chip with ARM processor, providing a SOC for that, which makes perfect sense.
It shows a prototype of using its ARM SoC to monitor the enviroment for tomato farming.
Renesas - ARM chip vendor, http://www.renasas.com, http://www.ittia.com
Renesas has been doing well in DDR memory. It takes its advantage to integrate memory with ARM processor, providing SoC with borth prcoessor and memory, which makes sense too.
Xilinx - ARM chip vendor, http://www.xilinx.com
Xilinx has been doing well in FPGA. It takes its advantage to integrate FPGA with ARM processor, providing SoC with borth prcoessor and FPGA, which makes sense too.
Renesas also provides in memory Database software, which is interesting too. Sasan Montaseri showed me the product with great passion.
Segger - embedded software vendor, http://www.segger.com
Segger is a German company, which provides a smakk foot print embedded OS, which allows the applications to host in secure/trusted zone and no-trusted zone.
Skkynet - application software, http://www.skkynet.com
This is a small Candaian company based in Ontario, which provides software running in redline box, and can stream data to cloud, which has service hosted. The service can be accessed from mobile phone.
I suggest the vendor to integrate with cisco IR800, which is a perfect platform for them to be in.
OEM production – system integrator , http://www.oemproduction.com
It provides very cute ARM based boxes with very low price and many interfaces, including 3G/4G, Wifi, USB, HDMI. The brand name is minix.
e.g. $49 for A2, $99 for X9-LX. It provides Linux or Android OS.
Mentor Graphics – Software vendor, http://www.mentorgraphics.com
Mentor Graphics has been in software business for long time with focus in automotive, embedded system. It acquired MontaVista (except the networking software CGE, which is still with Cavium Networks). I was given the demo of their fast boot system, which is deployed in automotive industry. The box can boot with almost a blink of eye. They customize u-boot, and also trim down OS as minimum as possible.
Mentor Graphics also provides embedded hypervisor like the one from Lynx software. However its dom0 is implemented using its properiety OS, which is could be a disadvantage.
AdaCore – software, http://www.adacore.com
This is a company providing Ada software development tool kits. It is widely used in embedded system like aircraft, fightjet, which needs high reliability. Its langauage syntax is much like Pascal.
Imperas – software, http://www.imperas.com
This is a company providing hareware/platform simulation for ARM based system. It can be used to debug some really hard software problem, or do software development before hardware is available. It is like simcs from WindRiver.
Aldec – ASIC design tool, http://www.aldec.com
This is a company providing ASIC design tool.
Allegro – IP vendor http://www.allegrodvt.com
This is a company provide ASIC IP, which does video encoder/decoder H.264/AVC H.265/HEVC up to 4K resolution. This is required fro video game, AI application, which requires large amount packets, idealy to be trasmitted in raw form, but too much bandwidth required. With their solution, it can be encoded/decoded and introduced delay will be less than 20ms over 802.11ad.
Below are collected business card during conference:
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Here you will find a very high level roadmap for the Apicurio Studio project. The details are subject to change,
but this page can provide a basic sense of the project's priorities and releases. Additional information can typically
be found on GitHub.
The intention is to release new versions of the Apicurio Studio very frequently. This roadmap represents a high
level set of features that make up a given release series (for example, Beta. The list of tasks
for each release series is an indication of the work to be done in that series, but not an implication of the order
in which that work will be done. Finally, we will not wait until all of the tasks are complete,
but will instead release iteratively as soon as useful functionality is completed.
{%- for section in site.data.roadmap -%}
{%- for category in section.categories -%}
-
{{ category.name }}
{%- for task in category.tasks -%}
-
{{ task.name }}
{%- if task.released -%}
{{ task.released }}
{%- endif -%}
{%- endfor -%}
{%- endfor -%}
Release Notes
{%- for rname in sortedreleases -%}
{%- assign release = site.data.releases[rname] -%}
{%- if release.tag_name contains section.version -%}
{%- endif -%}
{%- endfor -%}
{%- endfor -%}


Freecell Solver is an open source library and some command line applications, for automatically solving several variants of card Solitaire / Patience games, including Freecell.
There is a new release of the solver, version 6.0.1 with more details available in NEWS file. Note that this version does not break compatibility with the older releases, and we just felt like incrementing the primary digit.
Among the highlights are some code cleanups, some fixes, and some new features. Special thanks go to Antonio Rojas for reporting a build issue in v6.0.0, which prompted a fix.
Share and enjoy!


---
title: authnZ
layout: protoc-gen-docs
generator: protoc-gen-docs
number_of_entries: 6
---
Template authnZ defines an authorization and authentication adapter template
The Headers models the core HTTP headers needed for the JWT/OIDC flows
OutputTemplate
The Authn/Z template produces an authorization header of the format
Bearer <access> <id>
which should be replaced on the ongoing request.
as well as optional cookies to be set on the outgoing response
| Field |
Type |
Description |
authorization |
string |
The authorization header
|
sessionCookie |
string |
The session-cookie to append to the response
|
QueryParams
The QueryParams are the code HTTP request query parameters used in an OAuth 2.0 / OIDC flow
| Field |
Type |
Description |
error |
string |
The error matches an OAuth 2.0 callback error response
|
code |
string |
The code matches an OAuth 2.0 callback authorization code grant
|
state |
string |
The state matches an OAuth 2.0 callback authorization state parameter
|
properties |
map<string, istio.policy.v1beta1.Value> |
Additional data about the query parameters for use in policy.
|
Request
The Request captures information about the incoming HTTP request
| Field |
Type |
Description |
scheme |
string |
The HTTP scheme
|
host |
string |
The HTTP host
|
path |
string |
The HTTP path
|
params |
QueryParams |
THE HTTP query params
|
properties |
map<string, istio.policy.v1beta1.Value> |
Additional data about the Request for use in policy.
|
Target
A Target contains the Action destination.
| Field |
Type |
Description |
namespace |
string |
The namespace the target service is in
|
service |
string |
The service the action is being taken on.
|
method |
string |
The HTTP method of the request
|
path |
string |
The HTTP REST path within the service
|
properties |
map<string, istio.policy.v1beta1.Value> |
Additional data about the target for use in policy.
|
Template
The Authn/Z template contains the information necessary to
control authorization and authentication using OAuth 2.0 / OIDC
defined protocols. It captures information about the request source, destination
and code request telemetry that allows comprehensive JWT policy definitions.
| Field |
Type |
Description |
request |
Request |
The request contains the core information about the request being made
|
target |
Target |
The target contains aggregated Kube information about the destination
|


D3 Graph Theory is a project aimed at anyone who wants to learn graph theory. It provides quick and interactive introduction to the subject. The visuals used in the project makes it an effective learning tool.
And yes, it is an open-source project. Check the code at GitHub.


Nmap Web UI
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--- title: "Maintenance of variation for ongoing eco-evo dynamics" description: "" date: 2017-05-09T17:00:28-05:00 weight: 997 image: "/img/aphids_parasitoid.jpg" caption: "source: alexanderwild.com" ---
Feedbacks between evolutionary and ecological processes that occur because they operate on similar timescales is called eco-evo dynamics. For eco-evo dynamics to persist, the variation underlying both processes must be maintained, yet this fundamental component of eco-evo dynamics has received little attention. Pea aphids can evolve resistance to parasitoid wasps rapidly enough to affect the host–parasitoid dynamics. Through long-term lab experiments and simulations, we show that aphids dispersing among patches that vary in parasitoid abundance can produce both the ecological stability and balancing selection necessary for ongoing eco-evo dynamics.


Thai massage may soon get UNESCO recognition
by Express Web DeskBy: Express Web Desk | New Delhi | Published: December 9, 2019 9:15:59 pm
The practice employs thousands in Thailand, where it cost nearly around 0 to the customers. (Source: Wikimedia Commons)
Thai massage, a skill perfected for over 2,000 years in Thailand, might find place in UNESCO’s prestigious heritage list this week, news agency AFP reported.
The “nuad Thai” or Thai massage is said to have been originated in India and brought to Thailand some 2,500 years ago by doctors and monks, who passed its secrets to generations. It is believed that under Thailand’s King Rama III in the nineteenth century, scholars engraved their knowledge of the field onto the stones of Wat Pho(a Buddhist temple complex).
Now, Thai massage is available across the Kingdom — from Bangkok spas, to street-side shop houses to Phuket beaches. It may be added to the list of “Intangible Cultural Heritage” when the UN body meets in the Colombian capital of Bogota for a week starting Monday.
The massage technique really took off after a school was formed in a temple complex, which has now trained over 2,00,000 massage therapists so far.
“For many people who are disabled or in debt, this job is an opportunity because it requires no material — only their hands and knowledge,” the school’s director Preeda Tangtrongchitr told AFP.
The practice employs thousands in Thailand, where it costs nearly around $100 to the customers. The price is two or three-fold in London, New York or Hong Kong where the technique is booming.
(Inputs from AFP)
For all the latest World News, download Indian Express App
- Tags:
- Thailand
0 Comment(s) *
* The moderation of comments is automated and not cleared manually by indianexpress.com.


Back to Function index. Up to Contents. List of versions in reverse chronological order together with a brief list of changes. (Note: Old versions of the library use a year-month style of numbering. Now, the library uses a major and minor version number.)
- 1.2 (released 2011-12-20)
- Change license to MIT/X11.
- Add RandomLib::ExactNormal class. This enables you to sample exactly from a normal distribution with zero mean and unit variance (assuming that the underlying generator is perfect).
- Document function arguments and return values.
- Include OpenMP header in RandomThread.cpp.
- 1.0 (released 2011-08-12)
- cmake changes:
- include FindRandom.cmake in distribution;
- building with cmake creates and installs randomlib-config.cmake;
- better support for building a shared library under Windows.
- 2011-05 (released 2011-05-17)
- INCOMPATIBLE CHANGE: the default constructor Random r; sets the seed to []. Use r.Reseed(); to reset the seed to Random::SeedVector();
- Make sure Global generators are exported to the dll.
- 2011-04 (released 2011-04-12)
- Use cmake for configuration.
- Improve documentation on installation process.
- Improve documentation of parallelization.
- Remove examples RandomPermutation and shuffle and add RandomCoverage, RandomExact, RandomLambda, RandomSave, and RandomThread.
- Add specialized swap.
- Ensure the code works with compilers with no long double type.
- Add new and delete operators for SFMT19937 under Visual Studio.
- 2009-02
- RandomPermutation and shuffle accept -r option to undo a permutation or shuffle.
- Minor documentation fixes.
- 2008-11
- Changes to suppress warnings with g++ 4.3.
- Optional support for C++0x's static_assert.
- Document RandomPermutation and shuffle.
- Minor documentation fixes.
- 2008-04
- Reorganized so random algorithm and mixer can be selected independently. This eliminated a lot of duplicate code.
- This requires a new, incompatible, output format. Format is now independent of the current base of the stream.
- Name() now returns more informative name.
- SFMT19937 init_by_array mixer adopted for MT19937 generators. This is an incompatible change for the MT19937 generators. However it is possible to hook the MT19937 engine with the MixerMT1 mixers to recover the previous functionality using
- RandomEngine<MT19937<Random_u32>, MixerMT1<Random_u32> >
- RandomEngine<MT19937<Random_u64>, MixerMT1<Random_u64> >
- The way 32-bit results are glued together for to provide the Ran64() result is now LSB ordered. Previously the 32-bit version of MT19937 used MSB ordering here. This means that certain large integer results will be different for RandomEngine<MT19937<Random_u32>, MixerMT1<Random_u32> >
- Support AltiVec instructions on PowerPC for SFTM19937. Also use longer long double on PowerPC.
- Add -s seed option to shuffle and RandomPermutation.
- Use strtoull (where available) instead of strtoul in convert a string seed to numeric form.
- Switch project files to MS Visual Studio 2005.
- Use SeedVector() instead of SeedWord() for the default constructor for Random.
- Make 32-bit version of SFMT19937 the default generator.
- 2008-01
- This is a maintenance release in anticipation of a forthcoming major restructuring of the code.
- Use table of powers of two for g++ 4.1.
- Minor documentation fixes.
- 2007-05
- Add SFMT19937 generators.
- Introduce RandomGenerator::Name() to identify generator.
- Change define used to make 64-bit generator the default.
- Add RandomSelect::Weight.
- Ensure portability to systems where uint32_t is longer than 32 bits.
- 2007-04
- Add utilities RandomPermutation and shuffle.
- Implement MSB ordering on binary I/O in a portable way.
- 2006-12
- Add leapfrogging. The output format needed to be changed to accommodate an extra word of data. However, I/O routines can still read the 2006-11 version.
- 2006-11
- Introduce RandomCanonical class which accepts the random generator as a template argument.
- This allows the inclusion of 32-bit and 64-bit versions of mt19937.
- Include checksum in I/O.
- Include boost serialization.
- 2006-10
- Make 64-bit ready so a 64-bit version of mt19937 can be dropped in.
- Fix a bug in the seeding. (This bug was triggered by seed length of 624 or greater; so it was unlikely to have been encountered in practice.)
- Stop the special case treatment for Random::IntegerC<T>(numeric_limits<T>::max()). In some cases (e.g., T = int) this now gives different (but equivalent) results.
- 2006-09
- Add ExponentialProb, ExactExponential, ExactPower, and RandomNumber.
- Fix weakness in the seeding algorithm. A given seed now gives a random sequence different from previous version; so this is an incompatible change.
- Restructure the documentation.
- Allow constructors to accept vectors of any integral type and constructors with a pair of iterators.
- 2006-08
- Improve efficiency of Integer(n) where n is a power of two.
Back to Function index. Up to Contents.


You can create versioned documentation to go with your versioned assets. Just nest the examples directory with v{$n}
examples
v{$n}
For example, this example is located at /plugins/example-plugin/v{$n}/examples/01-doc-about.html
/plugins/example-plugin/v{$n}/examples/01-doc-about.html


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Speech
Minister of State for School Reform Nick Gibb outlines the government’s support for music education in schools.
Good morning. It is a great pleasure to be here today [12 March 2015] at the Music Education Expo in the Barbican, home to world-class music, theatre, art, dance and film.
And it is a fitting venue in which to be speaking about the importance of music education. As music teachers and others involved in music education, your work helps to build a love of music among pupils.
Building this love of music in schools is crucial. Because music shouldn’t be the preserve of those who can afford it, whose parents play instruments themselves or listen to music at home. This government’s plan for education has focused on raising standards for all and narrowing the gap between disadvantaged students and their peers. In the same way that high-quality schools are essential to meet this goal, so too is high-quality music education in schools.
Music is an important subject in its own right, combining intellectual rigour with creativity. The academic opportunities offered by music are clear - in 2009, 18.6% of pupils who achieved an A grade for music A level went to Oxbridge. Only 5 subjects had a higher progression rate.
The wider educational and social benefits of music are also clear. ‘The Power of Music’, recently published by Professor Susan Hallam, points to the positive effects of different aspects of music teaching and training on verbal instruction, reading and comprehension, motivation, communication and behaviour.
Senior teachers and heads in schools often speak of these benefits. As the assistant headteacher of Hackney New School, which offers all children music lessons, recently said:
Music has undoubtedly had a huge impact. Not only are pupils enjoying school more, but almost without realising it they are gaining confidence, resilience and team working skills which they then bring into other subject areas.
The ABRSM Making Music survey in 2014 found that there are particular disparities in music: children from less well-off backgrounds are less likely to play a musical instrument and less likely to have had music lessons. 40% of children from lower socio-economic groups who have never played an instrument said they had no opportunity to learn at school.
That is why when we came into government in 2010 we set out high aspirations. In the remit of the ‘Review of Music Education in England’ by Darren Henley, we stated that “every child should receive a strong, knowledge-based cultural education and should have the opportunity to learn and play a musical instrument and to sing”. Music education was patchy across the country and we wanted to change that so every pupil could benefit. The Henley Review and the subsequent National Plan for Music Education were the starting point for our approach, and set out the direction of our reforms.
Through our curriculum review, music remained a statutory subject in the national curriculum, so every child in maintained schools must study it from age 5 to 14. The new national curriculum, introduced in September, is particularly important to tackle disadvantage as the focus is on setting high expectations for everyone and ensuring that children have access to all of the national curriculum.
Alongside the new national curriculum, we have also reformed GCSEs, A levels and vocational qualifications. The greater rigour and focus on knowledge and skills in the study of music throughout key stages 1 to 3, including exposure to a wide range of music and composers, and teaching children how to read and write music using standard staff notation, will mean that music is an option for more pupils at GCSE . And the new more rigorous GCSE will in turn better prepare students for progression to A level and beyond.
Across all subjects, the importance of high-quality teaching is known to be the crucial factor in delivering better outcomes for pupils. We are fortunate to have some excellent music teachers working in our schools and I was lucky enough to present Classic FM’s primary school music teacher of the year award to Katie Crozier last year. Katie teaches at 2 schools in Huntingdonshire and has delivered significant improvement for pupils there. At her school, where she has taught since 2008, she has transformed the approach to music: the school has gone from having no orchestra and a choir of 8 members to a 50-member orchestra and a choir of 100 singers.
While there is already a great deal of good practice, we also want to make sure there is support available for teachers who may need it - in particular, practical help for non-specialist primary school teachers. I am delighted that Classic FM and the ISM are going to compile, and give schools access to, a new list of 100 pieces of classical music that every child should be familiar with by the time they leave primary school.
Being familiar with the best known classical works is as important as reading the canon. Music has been important to me personally and my suggestions for pieces to include would range from Beethoven’s Fifth Symphony to Parry’s setting of ‘I was glad’ and Allegri’s ‘Miserere’, which I still remember singing as a choirboy. I very much hope there will be strong engagement from those within music teaching with ISM and Classic FM as they develop the list.
These initiatives highlight that our ambitions cannot be achieved by acting alone. That is one of the key reasons behind the music hubs which we established in 2012 as part of the national plan. The hubs are helping to ensure that every child has the opportunity to learn instruments through whole class teaching, that there are clear progression routes available and affordable to all young people, opportunities to play in ensembles and to sing regularly, including in choirs or vocal ensembles.
In their first year, the hubs gave nearly half a million children the opportunity to learn an instrument for the first time, as well as working with almost 15,000 school choirs, orchestras and bands. 80,000 disadvantaged pupils took part in instrumental ensembles and choirs. Last year, the hubs were working with more than 60% of primary schools and more than 50% of secondary schools on their singing strategy, and 50,000 more children were receiving whole-class ensemble music teaching as a result of the hubs’ work.
On a recent school visit to Redbridge Primary School, I was able to see first-hand their whole-class ensemble teaching programme, which they offer to pupils for 3 years, first hand.
The positive impact the hubs are having is clear. That’s why in July last year we announced further funding for music hubs - an extra £18 million for music programmes, bringing the government’s investment in music education to more than £270 million since 2012.
Government support also continues for the Music and Dance Scheme, that supports the exceptionally talented at 21 music and dance centres of advanced training and 8 specialist schools, including the Royal Ballet School, which I visited recently, the Purcell School and the Yehudi Menuhin School. Programmes such as the National Youth Music Organisations, Music for Youth and In Harmony, a national scheme which focuses on offering children in 6 deprived communities an intensive orchestra experience, also give important opportunities to children up and down the country.
I was fortunate enough to attend the schools prom series, run by Music for Youth, at the Royal Albert Hall back in November, and enjoyed listening to performances by a wide range of ensembles, from the Glantaf Duo from South Glamorgan to the Wessex Youth Orchestra from Dorset.
In addition to government-funded schemes, I am pleased to see other organisations working in this area to increase opportunities in music for young people - such as the National Orchestra for All. NOFA was founded by a Teach First participant in 2011 and takes 150 musicians each year from schools in London and the west Midlands to form a full orchestra, which rehearses and performs in venues such as the Southbank Centre and the Royal Academy of Music.
The government’s free school programme has also unleashed innovation in music teaching, with a number of schools offering a specialism or focus in music such as West London Free School, East London Academy of Music and Hackney New School.
There is a great deal to celebrate and to be proud of in our performance in music - from the great classical composers of past and present, to the string of UK artists who top the charts worldwide. And in 2 years’ time, Sir Simon Rattle will return to England to the London Symphony Orchestra here at the Barbican.
A strong and rigorous music education is as important a part of being well educated as learning about science, history and literature. I hope our commitment to music education in schools is clear. We want to ensure this success in music continues and I am confident that our reforms have set us off in the right direction.
Published: 12 March 2015


Highly modular
Framework design
Laravel Zero is a lightweight and modular micro-framework for developing fast and powerful console applications. Built on top of the Laravel components.
Laravel Zero is a lightweight and modular micro-framework for developing fast and powerful console applications. Built on top of the Laravel components.


Watch: Jhené Aiko + T-Pain Hit The Kitchen W/ Their Moms + Whip Up Delicious Grub
by Team SOHHR&B singers Jhené Aiko and T-Pain are nice with the cooking skills. The duo appear in FUSE’s “Made From Scratch” series with their moms to dish on family dining traditions and discuss their lives. Watch and comment below!


|
SideCar
|
#include "Algorithms/Algorithm.h"
#include "Messages/Complex.h"
#include "Messages/Video.h"
#include "Parameter/Parameter.h"
Go to the source code of this file.
Data Structures | |
| class | SideCar::Algorithms::IQFilter |
| Conversion filter from I/Q (complex) messages into Video message format. More... | |
Namespaces | |
| SideCar | |
| Namespace for all entities specific to the 331 SideCar project. | |
| SideCar::Algorithms | |
| Namespace for entities related to SideCar algorithms. | |


Username must meet the following requirements:
Password must meet the following requirements:
- At least one letter
- At least one capital letter
- At least one number
- At least one special character
- Be at least 8 characters
Password must meet the following requirements:


A little mountain town tucked away in the Adirondacks
History of Windham
A legacy of Excellence
"The town of Windham, Ulster County, New York, was formed in March of 1798. History books disagree as to whether it was the 23rd or 27th of that month. Windham became the western half of Greene County upon the latter’s creation on March 25, 1800. The seven towns of Ashland, Halcott, Hunter, Jewett, Lexington, Prattsville and Windham were created from what we might call "Old Windham." The towns of New Goshen (Lexington) and Greenland (Hunter) were taken from the southern part of Windham in 1813." ( Windhamny.com )


Jetty Demos
The Jetty distribution includes a number of examples and
demos. These are available from both the Jetty web
site and from an installed Jetty distribution running on your system:
Example Servlets
The Servlet API and container, with context support.
Example Web Applications
The J2EE standard deployment packaging for web applications.
The links to the following demos will only be active when these
pages are accessed from your local Jetty installation (ie they
will not work from the main Jetty web site for security reasons):
Admin Servlet
A Servlet to provide basic administration of a running Jetty server.
Username=admin Password=admin


This driver reads files describing Special Use Airspaces in the OpenAir format
Airspace are returned as features of a single layer called 'airspaces', with a geometry of type Polygon and the following fields: CLASS, NAME, FLOOR, CEILING.
Airspace geometries made of arcs will be tessellated. Styling information when present is returned at the feature level.
An extra layer called 'labels' will contain a feature for each label (AT element). There can be multiple AT records for a single airspace segment. The fields are the same as the 'airspaces' layer.


Fuzzy Demo
Run Fuzzy Car demo
GADemo
Population Size
Initial Population Size
Probability of Mutation
Probability of Performing Crossover
Max Iteration
selection:
Roulette Wheel
Tournament
Run GA demo
GA Log
Iteration
Fitness
NN-GA Demo
Run NN demo


Loops can execute a block of code a number of times. They are amazing if you want to runt he same code over and over again, each time witha different value. The for loop is used to create a loop. The for loop has the following syntax:
for (statement 1; statement 2; statement 3) { code block to be executed }
Try out a for loop!
Here is how it works. Our variable "insults" contains an array of three strings. Each string is a really good insult. We used a 'for loop' to start from the 0 index and move through the entire length of the array one at a time. Each value was plugged into an alert that would kindly insult you.
Our Javascript looks like: $(document).ready(function() { $("button#example").click(function() { var insults = ['a baby', 'not an adult', 'still a baby']; for (var index = 0; index < insults.length; index += 1) { alert('You are ' + insults[index] + '!'); } }); });