Verilog
(File Menu)The conversion of the schematic diagram into a VERILOG description is usefull for compiling the schematic diagram into layout using Microwind. The verilog description is a text with a predefined syntax. Basically, the text includes a description of the module (name, input, output), the internal wires, and the list of primitives. An example of veriolog file generated by DSCH is given below.
// DSCH 2.2a
// 24/06/01 18:38:13
// C:\Dsch 2.0\Manual uw2\Base.sch
module Base( A,B,INV,NAND,XOR,NOR);
input A,B;
output INV,NAND,XOR,NOR;
not1 not12(B,INV)
nand2 nand24(B,A,NAND)
xor2 xor27(A,B,XOR)
nor2 nor28(A,B,NOR)
endmodule
// Simulation parameters
// A CLK 10 10
// B CLK 20 20
COMMENTS: //
MODULE DECLARATION: "module", name, and list of I/Os.
MODULE CONTENTS: list of inputs, of outputs, of internal wires, and the declaration of primitives, always with the primitive keyword first, the name second, and the list of parameters. For example: NOT1 is the primitive for the inverter, "not12" is the cell name, "B" is the input and "INV" the output.
MODULE END: "endmodule".
[Back]


@(session: models.Session, request: play.mvc.Http.Request) @base(session, request, "Internal Server Error", "error") {
It seems as though an internal server error has occurred. Please try your operation again in a few minutes, and if this error continues please contact the system administrator.
}


Every penny goes to help children in need.
Isaiah 117 House–Carter/Johnson/Unicoi, Inc. Project (hereinafter referred to as “the organization) is a non-profit public benefit group organized to develop and implement strategies to meet the needs of children, specifically from the time of removal until the time of foster placement, served by the Tennessee Department of Children's Services ("DCS-) in Carter, Johnson and Unicoi Counties of East Tennessee. Concerns may include, but are not limited to: food, shelter, clothing, and personal hygiene. The Project will also assist in other projects to address the needs of children served by DCS in Carter, Johnson and Unicoi Counties, as those needs are identified by DCS.
Three years ago, my husband Corey and I went through Path Training in order to become foster parents. As part of our training, we attended a class at the Washington County DCS office. During that class, we were informed that when children are removed from their homes they often have to come to the DCS office and wait for placement. As I looked around the cubicle filled space, I couldn't imagine a scared child sitting in such a sterile, cold environment waiting to learn their fate. That is when I believe God put on my heart the Isaiah 117 House.
Fast-forward one year, on November 5, 2015, at 3:45pm, I received a call from the Carter County DCS office. Within an hour, Corey, Sophie, Mac and I were picking up a 9-month-old boy named Isaiah. We were asked to come to the back door of the office. Isaiah was dirty, in clothes that were too small, and literally had nothing in the world. This was the second time I believe the Lord put on my heart the Isaiah 117 House.
What if there was a home where children could go when they are removed? What if there was a safe place with friendly, loving volunteers? What if there was an environment with clean clothes, bath toys, healthy snacks, comfy beds and toys? What if instead of cubicles, the traumatized child could see smiles, books, and snuggly blankets?
This is my dream for the Isaiah 117 House. Isaiah 1:17 says, "defend the cause of the fatherless." I believe that is what God is calling me to do. I see a home with a girl’s bedroom, a boy’s bedroom, fully stocked bathroom, playroom, nursery, etc. I see a team of volunteers, 2 at a time, on call to greet "the least of these" when they need love most. I see a place always ready to take in the children of this region in their time of need and help with what is inevitably a traumatic transition. I believe this home has the potential to positively affect the children who are coming into custody in ways far beyond what we could ever imagine as well as support the DCS staff of this region.


Edit the following two files:
/usr/include/sys/socket.h
/usr/src/sys/sys/socket.h
In each file, look for the following:
/* * Maximum queue length specifiable by listen. */ #define SOMAXCONN 5Just change the "5" to whatever appears to work. I bumped the two machines I was having problems with up to 32 and haven't noticed the problem since.
After the edit, recompile the kernel and recompile the Apache server then reboot.
FreeBSD 2.1 seems to be perfectly happy, with SOMAXCONN set to 32 already.
Addendum for very heavily loaded BSD servers
from Chuck Murcko<EMAIL_ADDRESS>If you're running a really busy BSD Apache server, the following are useful things to do if the system is acting sluggish:
maxusers 256Maxusers drives a lot of other kernel parameters:
# Network options. NMBCLUSTERS defines the number of mbuf clusters and # defaults to 256. This machine is a server that handles lots of traffic, # so we crank that value. options NMBCLUSTERS=4096 # mbuf clusters at 4096 # # Misc. options # options CHILD_MAX=512 # maximum number of child processes options OPEN_MAX=512 # maximum fds (breaks RPC svcs)
In many cases, NMBCLUSTERS must be set much larger than would appear necessary at first glance. The reason for this is that if the browser disconnects in mid-transfer, the socket fd associated with that particular connection ends up in the TIME_WAIT state for several minutes, during which time its mbufs are not yet freed. Another reason is that, on server timeouts, some connections end up in FIN_WAIT_2 state forever, because this state doesn't time out on the server, and the browser never sent a final FIN. For more details see the FIN_WAIT_2 page.
Some more info on mbuf clusters (from sys/mbuf.h):
/* * Mbufs are of a single size, MSIZE (machine/machparam.h), which * includes overhead. An mbuf may add a single "mbuf cluster" of size * MCLBYTES (also in machine/machparam.h), which has no additional overhead * and is used instead of the internal data area; this is done when * at least MINCLSIZE of data must be stored. */
CHILD_MAX and OPEN_MAX are set to allow up to 512 child processes (different than the maximum value for processes per user ID) and file descriptors. These values may change for your particular configuration (a higher OPEN_MAX value if you've got modules or CGI scripts opening lots of connections or files). If you've got a lot of other activity besides httpd on the same machine, you'll have to set NPROC higher still. In this example, the NPROC value derived from maxusers proved sufficient for our load.
To increase the size of the listen()
queue, you need to
adjust the value of SOMAXCONN. SOMAXCONN is not derived from maxusers,
so you'll always need to increase that yourself. We use a value guaranteed
to be larger than Apache's default for the listen() of 128, currently.
The actual value for SOMAXCONN is set in sys/socket.h
.
The best way to adjust this parameter is run-time, rather than changing
it in this header file and thus hardcoding a value in the kernel and
elsewhere. To do this, edit /etc/rc.local
and add the
following line:
/usr/sbin/sysctl -w kern.somaxconn=256
We used 256
but you can tune it for your own setup. In
many cases, however, even the default value of 128
(for
later versions of FreeBSD) is OK.
Caveats
Be aware that your system may not boot with a kernel that is configured to use more resources than you have available system RAM. ALWAYS have a known bootable kernel available when tuning your system this way, and use the system tools beforehand to learn if you need to buy more memory before tuning.
RPC services will fail when the value of OPEN_MAX is larger than 256. This is a function of the original implementations of the RPC library, which used a byte value for holding file descriptors. BSDI has partially addressed this limit in its 2.1 release, but a real fix may well await the redesign of RPC itself.
Finally, there's the hard limit of child processes configured in Apache.
For versions of Apache later than 1.0.5 you'll need to change the definition for HARD_SERVER_LIMIT in httpd.h and recompile if you need to run more than the default 150 instances of httpd.
From conf/httpd.conf-dist:
# Limit on total number of servers running, i.e., limit on the number # of clients who can simultaneously connect --- if this limit is ever # reached, clients will be LOCKED OUT, so it should NOT BE SET TOO LOW. # It is intended mainly as a brake to keep a runaway server from taking # Unix with it as it spirals down... MaxClients 150Know what you're doing if you bump this value up, and make sure you've done your system monitoring, RAM expansion, and kernel tuning beforehand. Then you're ready to service some serious hits!
Thanks to Tony Sanders and Chris Torek at BSDI for their helpful suggestions and information.
"M. Teterin"<EMAIL_ADDRESS>writes:
It really does help if your kernel and frequently used utilities are fully optimized. Rebuilding the FreeBSD kernel on an AMD-133 (486-class CPU) web-server with
-m486 -fexpensive-optimizations -fomit-frame-pointer -O2
helped reduce the number of "unable" errors, because the CPU was often maxed out.


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Requirements
- Prototype prototype.js
- Script.aculo.us effects.js
- Droplicious droplicious.js
- A bit of html/css/js knowhow
Install
git clone git://github.com/darrenterhune/droplicious.git
- View the project at github
Tested
- Mozilla Firefox 3.0+
- Google Chrome <IP_ADDRESS> (35163) beta
- Safari 3.2+
- IE 6+
Change Log
You can view commit changes at github.
Contributors
Jan Sovak http://canada-jack.com
Mason Meyer http://www.masonmeyer.com/
Bugs
Submit issues on the github issues page.
Connect with me
Follow me on Twitter™ @darrenterhune
License
The MIT License
Copyright © 2009 Head First Productions - Darren Terhune
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
- The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
- The author's name shall be included in all copies or substaintial portions of the Software.
 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Droplicous by Darren Terhune is licensed under a Creative Commons Attribution 2.5 Canada License.
Based on a work at headfirstproductions.ca.
Food for thought
One evening an old Cherokee told his grandson about a battle that goes on inside people. He said, "My son, the battle is between two "wolves" inside us all.
One is Evil. It is anger, envy, jealousy, sorrow, regret, greed, arrogance, self-pity, guilt, resentment, inferiority, lies, false pride, superiority, and ego.
The other is Good. It is joy, peace, love, hope, serenity, humility, kindness, benevolence,empathy, generosity, truth, compassion and faith."
The grandson thought about it for a minute and then asked his grandfather: "Which wolf wins?"
The old Cherokee simply replied, "The one you feed."


This is a quick font rendering demo for debugging purposes. The upper line shows a horizontal spritemap, the lower one uses a quadratic spritemap.


Cruise ship docks in Singapore after hundreds of passengers and crew members fall ill
SINGAPORE: A cruise ship on the way to Vietnam from Thailand docked in Singapore this week after 229 of its passengers and crew members fell ill, according to a joint statement issued on Friday (Nov 15).
The affected people suffered a gastrointestinal illness, with symptoms like vomiting and diarrhoea, said the Maritime and Port Authority of Singapore, Ministry of Health and Singapore Food Agency in response to CNA's queries.
The MV Sun Princess was travelling from Phuket to Ho Chi Minh City when it made the stop in Singapore on Wednesday at around 5.30am. The MPA had been informed of the outbreak on Monday morning.
Out of the passengers and crew members affected, 189 recovered, according to the Friday statement. Sixteen of the remaining affected disembarked and terminated their cruise in Singapore.
"There was no mass evacuation of the MV Sun Princess in Singapore and most of the passengers had disembarked for a short day tour in Singapore," the statement added.
Responding to CNA's queries, MOH said on Saturday that the outbreak was caused by norovirus. "It can be prevented from spreading with good personal hygiene. In general, there is no need to impose strict isolation or quarantine measures on persons with norovirus infection in the general population," the ministry said.
There were no Singaporeans among those affected.
The MPA, MOH and SFA conducted a joint inspection of the cruise on Wednesday. MOH also worked with the cruise operator to ensure that proper infection prevention and control were implemented.
Additionally, it provided all passengers with a health advisory with information on how to look out for symptoms of the disease as well as protection and prevention measures.
MV Sun Princess left Singapore for Ho Chi Minh City at 5.30pm on Wednesday.
On Saturday, MOH said that the 16 passengers who disembarked were managed in "outpatient settings" and assessed by a doctor to be fit for onward travel. Eight passengers have left Singapore as of Friday.
This story has been updated to include a recent response from the Ministry of Health.


Terminology
The following terminology is used in the documentation of the SBLIM CIM
Client for Java. As a DMTF Glossary document evolves, this terminology will be drawn
from there, over time.
CIM object related terms
- CIM namespace
- Run-time container within
a CIM server that can contain CIM classes, instances and qualifier
declarations. For details, refer to the CIM Infrastructure Specification
[DSP0004].
- CIM class
- A CIM class, as defined in
the CIM Infrastructure Specification [DSP0004]. The term is used for all three
kinds of CIM classes (normal, association and indication). The term is used
both for the CIM class object in the CIM server/provider and for its client
side copy.
Terms denoting specific kinds of CIM
classes:
- Normal CIM class
- A CIM class that is
neither an association class nor an indication class.
- CIM association class
- A CIM class that
has its Association qualifier effectively being true. Note that the
Association qualifier is inherited into subclasses. Also note that the Aggregation
and Composition qualifiers may refine the semantics of an association class,
but such classes still remain association classes.
- CIM indication class
- A CIM class that
has its Indication qualifier effectively being true. Note that the Indication
qualifier is inherited into subclasses.
- CIM instance
- An instance of a CIM
class. The term is used both for the CIM instance object in the CIM
server/provider and for its client side copy.
- CIM object
- A general term for either a
CIM class or CIM instance. Sometimes also includes CIM namespace in
addition. Sometimes also includes the name (path) of the object.
Phrases denoting whether the objects
are the objects in the CIM server or their local copies:
Note: These phrases can be used with all
the object related terms above.
- Local copy of a CIM object
- When a CIM
object is returned to the CIM client, the data being returned is called a
local copy of the CIM object.
- CIM object in the CIM server
- Refers to
the "live" CIM object in the CIM server (or better in the provider). In the
case of CIM instances, the live object represents an aspect of a real world
resource, and manipulation of the CIM instance manipulates the real world
resource.
CIM object naming related terms
- CIM object path
- General term for a
reference to a CIM namespace, class or instance object in a CIM server. These
object paths allow accessing the referenced CIM objects in the CIM server. The
term does not imply any particular scope at which the object path is unique.
An alternative phrase used in DMTF documents is "CIM object name".
Terms for specific kinds of CIM object
paths:
- CIM namespace path
- CIM object path
referencing a CIM namespace object in a CIM server.
- CIM class path
- CIM object path
referencing a CIM class object within a CIM namespace in a CIM server.
- CIM instance path
- CIM object path
referencing a CIM instance object within a CIM namespace in a CIM server.
Phrases describing the uniqueness scope of
object paths:
Note: These phrases can be used with all
the path related terms above.
- Global CIM object path
- CIM object path
using a reference that is globally unique (that is, across CIM servers). The
object path identifies the host and port of the CIM server, the CIM namespace
within the server, and the name of the object within the namespace.
- Intra-Server CIM object path
- CIM object
path using a reference that is unique within a single CIM server. The object
path does not identify the CIM server. It identifies the CIM namespace within
a CIM server, and the name of the object within the namespace. An alternative
phrase used in DMTF documents is "local object path".
- Intra-Namespace CIM object path
- CIM
object path using a reference that is unique within a single CIM namespace.
The object path does not identify the CIM server or namespace. It identifies
the name of the object within the namespace. An alternative phrase used in
DMTF documents is "model path", or "class name" for class objects and "instance
name" for instance objects.
CIM class/instance member related terms
Phrases defining the set of elements in a class
or instance:
Note: These phrases are stated for properties
but are equally valid for references and methods.
- Properties defined in a class
- The set
of properties introduced in the class, or overridden in the class. This does
not include any properties inherited from superclasses, or properties
introduced or overridden in subclasses of the class.
- Properties defined in the class of an
instance
- The set of properties defined in the class an instance has
been created of.
- Properties of a class
- The set of
properties effectively visible in the class, including any inherited
properties. Overridden properties are contained in that set only once.
Non-overridden properties with the same name are contained in that separately
(This should be avoided, but it can happen in different classes, for instance
when a superclass in a DMTF common schema adds a property that is already
defined in a subclass that is a vendor extension class).
- Properties of an instance
- The set of
properties effectively present in the instance.
Other terms
- CIM element
- General term for CIM class
(all kinds: normal, association, indication), property, reference, method,
method parameter, qualifier, qualifier flavor or schema.
- CIM client protocol
- General term for a
remote communications protocol between CIM client and CIM server. Note that
this includes for instance any upcoming Web services protocol and the new
SM-CLP, and is not restricted to CIM Operations over HTTP.
- CIM Operations over HTTP
- Name of the
dominant CIM client protocol, specified in DMTF DSP0200 and DSP0201.
- CIM client
- General term for a component
(usually a class library) used to communicate with a CIM server. Handlers for
indication delivery or asynchronous operation responses are also considered
part of a CIM client. Usually, a CIM client is used by a management
application.
- SBLIM CIM Client for Java
- Name of this specific
CIM client.
- CIM server
- General term for a component
(usually a demon) providing a service accessible through a CIM client protocol.
A single CIM server instance may be used by multiple CIM client instances. In
the course of handling the requests resulting from interactions with CIM
clients, a CIM server interfaces with CIM providers for getting certain
requests handled.
- CIM provider
- General term for a
component implementing all behavior that is specific to a particular CIM
class. This means, CIM providers are the link between the CIM server and any
interfaces specific to the real world resources. It is left open whether a
single CIM provider can implement one or more CIM classes. A particular CIM
provider API is not implied.


Feathers 3.1 Migration Guide
This guide explains how to migrate an application created with Feathers 3.0 to Feathers 3.1. Be aware that, as a minor update, the new features in this version are not considered "breaking" changes. You are not required to make any modifications to your projects to update to this version. However, you will see benefits from switching to some of the newer, simplified APIs. The focus of this release is to improve the developer experience, especially when dealing with font styles and skinning.
Font styles with starling.text.TextFormat
Starling 2 introduced a new starling.text.TextFormat
class that defines common font styles used by all types of text, including bitmap fonts and TTF/OTF fonts. Previously, to customize font styles on Feathers text renderers, you needed to use different classes and set different properties, depending on which text renderer you were using. For instance, TextBlockTextRenderer
has an elementFormat
property of type flash.text.engine.ElementFormat
while TextFieldTextRenderer
has a textFormat
property of type flash.text.TextFormat
. Now, all text renderers have a unified way to support the starling.text.TextFormat
class.
In fact, the font styles don't need to be set directly on the text renderer anymore. Instead, you can set them on the component that uses the text renderer, such as a Label
or Button
. They parent component will automatically pass them down to the text renderer.
Let's customize the font styles on a Label
component to see how it works:
var label:Label = new Label();
label.text = "Hello World";
label.fontStyles = new TextFormat( "_sans", 20, 0xff0000 );
this.addChild( label );
That's it! In the vast majority of cases, you won't need to deal with the text renderer factories at all.
If we wanted the Label
to use different font styles when disabled, we can do that easily too:
label.disabledFontStyles = new TextFormat( "_sans", 20, 0x999999 );
Most components that contain a text renderer will now have fontStyles
and disabledFontStyles
properties. If a component can be toggled or selected, it may also have a selectedFontStyles
property.
Finally, if a component supports a more complex set of mutiple states, such as the touch states in a Button
, it will have a setFontStylesForState()
method. This method accepts the name of the state along with a TextFormat
object to use when the component is in that state. In the following example, we set separate font styles for the "down" and "hover" states of a Button
:
var button:Button = new Button();
button.setFontStylesForState( ButtonState.DOWN, new TextFormat( "_sans", 20, 0xffffff ) );
button.setFontStylesForState( ButtonState.HOVER, new TextFormat( "_sans", 20, 0xff9999 ) );
Style properties and themes
In previous versions of Feathers, it was easy to run into conflicts with the theme when attempting to skin components. To avoid this issue, you could use the AddOnFunctionStyleProvider
class, set the styleProvider
property to null
, wait until a component initialized, or extend the theme. However, each of these options could be somewhat cumbersome for minor tweaks to a single component's appearance.
Starting with Feathers 3.1, certain properties are now considered "styles". If you set a "style property" outside of the theme, you don't need to worry about the theme replacing it later. However, any other styles from the theme won't be affected. As an example, if you wanted to customize a button's font styles outside the theme, but keep the background skin from the theme, it's easy.
var button:Button = new Button();
button.label = "Click Me";
//this can't be replaced by the theme
button.fontStyles = new TextFormat( "_sans", 20, 0xff0000 );
this.addChild( button );
To see how style are now separated from other properties in the API reference, see the Button
component styles as an example.
Minimum dimensions in the theme
Be aware that if you set a regular property in a theme, it may still conflict with code outside of the them. For example, you should not set the minWidth
and minHeight
properties directly on a component in a theme. These properties are not considered styles, and you may run into conflicts if you also try to set them outside of the theme.
//inside the theme
private function setButtonStyles( button:Button ):void
{
button.defaultSkin = new ImageSkin( texture );
button.minWidth = 40; //don't do this!
}
Instead, set minWidth
and minHeight
on the component's skin:
//inside the theme
private function setButtonStyles( button:Button ):void
{
var skin:ImageSkin = new ImageSkin( texture );
skin.minWidth = 40;
skin.minHeight = 20;
button.defaultSkin = backgroundSkin;
}
If a component doesn't have explicit dimensions, it will always use the skin's dimensions for measurement. With that mind, setting dimensions on the button's skin in the code above is virtually the same as setting dimensions directly on the button.
What if a component doesn't need to display a background skin? Consider using a transparent background skin, in that case. You might simply pass in a starling.display.Quad
with its alpha
property set to 0
:
var backgroundSkin:Quad = new Quad( 40, 20 );
backgroundSkin.alpha = 0;
component.backgroundSkin = backgroundSkin;
Starling will not ask the GPU to render a fully transparent display object, so this background cannot affect draw calls or performance. However, the dimensions of the Quad
will be treated as minimum dimensions for the component.


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Page 2 of 2
Posted:
Tue Jan 02, 2007 6:33 pm
by Serenity
I do have to say Nice work didnt think anyone was going to make it =D.. Looks very nice. Kudos
Posted:
Wed Jan 03, 2007 5:52 pm
by secretrk1313
you made my day, its always good to hear from the orriginal artist. I dont think ill be planning on making a low polly version
I wouldnt want to see what it looks like as 70 faces
EDIT: I got currious and found a easy polly reducer, with this program and a little rework a low poly version may be possible
Tell me the max amount of faces i could use and we will see what i can do
Posted:
Thu Jan 04, 2007 12:32 am
by Serenity
my only real critique is the flambouyantly pink hilt crystal
Posted:
Thu Jan 04, 2007 5:29 am
by secretrk1313
what color do you think would look good? because i thought it was a little out of place too.
Posted:
Thu Jan 04, 2007 12:21 pm
by Serenity
an opacued silver so its see through but still notice it?
Posted:
Thu Jan 04, 2007 1:54 pm
by secretrk1313
like this??
this is still the higher poly model at this point
Posted:
Thu Jan 04, 2007 3:12 pm
by Serenity
perfect, looks a lot like an impure quartz which is good kinda what I was shooting for. (quartz was said to provide protection in the mythological ages)
Posted:
Thu Jan 04, 2007 6:00 pm
by secretrk1313
ok here is the low polly one at 418 pollys, i exported every part, edited the polly count, and remerged and retextured them. This is the lowest i could go i think without losing any shape of the orriginal model. I think it looks good for going from about 2400pollys to 400. Also in this one is the new silver crystal.
please give me an exact number of triangles i am allowed to have at max because even though this one cant go any lower i would like to know
Posted:
Thu Jan 04, 2007 9:13 pm
by Serenity
No too shabby, cant complain becuase most of the High detailed stuff really wont be seen so IMO you rawk and you took my sketch and kicked its bum. Really nice
Posted:
Thu Jan 04, 2007 10:50 pm
by Joe M.
looks really good. One question: is the blade actually textured? it looks like the standard grey...
Posted:
Fri Jan 05, 2007 5:28 am
by secretrk1313
I know what you mean but it is actually textured, only to the point where its shinyer and a little bit of diffrent color though.
Posted:
Sat Jan 06, 2007 4:33 pm
by secretrk1313
Retextured into one tga file, final low poly model, tell me where to send it
Posted:
Sat Jan 06, 2007 5:01 pm
by thadiusofx3
Upload it into the awaiting approval folder in the 3d models folder of the official file storage (its a sticky in the forum)
Posted:
Sat Jan 06, 2007 5:11 pm
by secretrk1313
Done, .X file and the texture .tga file
Posted:
Sat Jan 06, 2007 5:22 pm
by Serenity
Looks awesome. Great work. hehe I look forward to seeing more models
Posted:
Sat Jan 06, 2007 6:15 pm
by Joe M.
hm, still think the blade's a little dull. Other than that, though, it looks great.
Posted:
Sat Jan 06, 2007 10:06 pm
by Karl G.
I don't know what's up, but it won't load on my computer.
Posted:
Sun Jan 07, 2007 12:31 am
by secretrk1313
tell me what program your using, and if you want it in a diffrent format
Posted:
Sun Jan 07, 2007 12:35 am
by Karl G.
I'm just using the regular old .X viewer by Microsoft. Try 3DS, I've got a converter for that. Or blender, I can export the model...
Posted:
Sun Jan 07, 2007 12:37 am
by secretrk1313
k im uploading as we speak its in awaiting aproval and called DragonSword-3DS


Before Change
// These invariants ensure that we can restore the source chroot to its original state
// during post-test cleanup, and that even if that cleanup fails for some reason, the
// next test run will be able to restore the correct state.
conftest = os.path.join(
self.context.products.get_data(GatherSources.PYTHON_SOURCES).path(), "conftest.py")
conftest_orig = None
// Note that on the first test run since the source chroot was created both invariants hold
// here: 1 holds because haven"t ever created conftest_orig, and 2 holds trivially.
// See below for why both invariants hold here on subsequent runs that complete normally.
// Note that even if invariant 2 is violated here (say because the previous run crashed before
// executing the cleanup that restores it) it will be restored in this run"s cleanup.
if os.path.exists(conftest):
conftest_orig = "{}.orig".format(conftest)
if not os.path.exists(conftest_orig):
// Note that this preserves both invariants.
After Change
// Note that it"s important to put the tmpdir under the workdir, because pytest
// uses all arguments that look like paths to compute its rootdir, and we want
// it to pick the buildroot.
with temporary_dir(root_dir=self.workdir) as conftest_dir:
conftest = os.path.join(conftest_dir, "conftest.py")
with open(conftest, "w") as fp:
fp.write(conftest_content)
yield conftest
@contextmanager
def _test_runner(self, targets, sources_map):
pex_info = PexInfo.default()
pex_info.entry_point = "pytest"


| Opcode | Instruction | Op/En | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|---|
| 9D | POPF | ZO | Valid | Valid | Pop top of stack into lower 16 bits of EFLAGS. |
| 9D | POPFD | ZO | N.E. | Valid | Pop top of stack into EFLAGS. |
| 9D | POPFQ | ZO | Valid | N.E. | Pop top of stack and zero-extend into RFLAGS. |
| Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| ZO | NA | NA | NA | NA |
Pops a doubleword (POPFD) from the top of the stack (if the current operand-size attribute is 32) and stores the value in the EFLAGS register, or pops a word from the top of the stack (if the operand-size attribute is 16) and stores it in the lower 16 bits of the EFLAGS register (that is, the FLAGS register). These instructions reverse the operation of the PUSHF/PUSHFD/PUSHFQ instructions.
The POPF (pop flags) and POPFD (pop flags double) mnemonics reference the same opcode. The POPF instruction is intended for use when the operand-size attribute is 16; the POPFD instruction is intended for use when the operand-size attribute is 32. Some assemblers may force the operand size to 16 for POPF and to 32 for POPFD. Others may treat the mnemonics as synonyms (POPF/POPFD) and use the setting of the operand-size attribute to determine the size of values to pop from the stack.
The effect of POPF/POPFD on the EFLAGS register changes, depending on the mode of operation. See Table 4-15 and the key below for details.
When operating in protected, compatibility, or 64-bit mode at privilege level 0 (or in real-address mode, the equivalent to privilege level 0), all non-reserved flags in the EFLAGS register except RF1, VIP, VIF, and VM may be modified. VIP, VIF and VM remain unaffected.
1. RF is always zero after the execution of POPF. This is because POPF, like all instructions, clears RF as it begins to execute.
When operating in protected, compatibility, or 64-bit mode with a privilege level greater than 0, but less than or equal to IOPL, all flags can be modified except the IOPL field and RF, IF, VIP, VIF, and VM; these remain unaffected. The AC and ID flags can only be modified if the operand-size attribute is 32. The interrupt flag (IF) is altered only when executing at a level at least as privileged as the IOPL. If a POPF/POPFD instruction is executed with insufficient privilege, an exception does not occur but privileged bits do not change.
When operating in virtual-8086 mode (EFLAGS.VM = 1) without the virtual-8086 mode extensions (CR4.VME = 0), the POPF/POPFD instructions can be used only if IOPL = 3; otherwise, a general-protection exception (#GP) occurs. If the virtual-8086 mode extensions are enabled (CR4.VME = 1), POPF (but not POPFD) can be executed in virtual-8086 mode with IOPL < 3.
(The protected-mode virtual-interrupt feature — enabled by setting CR4.PVI — affects the CLI and STI instructions in the same manner as the virtual-8086 mode extensions. POPF, however, is not affected by CR4.PVI.)
In 64-bit mode, the mnemonic assigned is POPFQ (note that the 32-bit operand is not encodable). POPFQ pops 64 bits from the stack. Reserved bits of RFLAGS (including the upper 32 bits of RFLAGS) are not affected.
See Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more information about the EFLAGS registers.
| Mode | Operand Size | CPL | IOPL | Flags | Notes | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 21 | 20 | 19 | 18 | 17 | 16 | 14 | 13:12 | 11 | 10 | 9 | 8 | 7 | 6 | 4 | 2 | 0 | |||||
| ID | VIP | VIF | AC | VM | RF | NT | IOPL | OF | DF | IF | TF | SF | ZF | AF | PF | CF | |||||
| Real-Address Mode (CR0.PE = 0) | 16 | 0 | 0-3 | N | N | N | N | N | 0 | S | S | S | S | S | S | S | S | S | S | S | |
| 32 | 0 | 0-3 | S | N | N | S | N | 0 | S | S | S | S | S | S | S | S | S | S | S | ||
| Protected, Compatibility, and 64-Bit Modes (CR0.PE = 1 EFLAGS.VM = 0) | 16 | 0 | 0-3 | N | N | N | N | N | 0 | S | S | S | S | S | S | S | S | S | S | S | |
| 16 | 1-3 | <CPL | N | N | N | N | N | 0 | S | N | S | S | N | S | S | S | S | S | S | ||
| 16 | 1-3 | ≥CPL | N | N | N | N | N | 0 | S | N | S | S | S | S | S | S | S | S | S | ||
| 32, 64 | 0 | 0-3 | S | N | N | S | N | 0 | S | S | S | S | S | S | S | S | S | S | S | ||
| 32, 64 | 1-3 | <CPL | S | N | N | S | N | 0 | S | N | S | S | N | S | S | S | S | S | S | ||
| 32, 64 | 1-3 | ≥CPL | S | N | N | S | N | 0 | S | N | S | S | S | S | S | S | S | S | S | ||
| Virtual-8086 (CR0.PE = 1 EFLAGS.VM = 1 CR4.VME = 0) | 16 | 3 | 0-2 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | 1 |
| 16 | 3 | 3 | N | N | N | N | N | 0 | S | N | S | S | S | S | S | S | S | S | S | ||
| 32 | 3 | 0-2 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | 1 | |
| 32 | 3 | 3 | S | N | N | S | N | 0 | S | N | S | S | S | S | S | S | S | S | S | ||
| VME (CR0.PE = 1 EFLAGS.VM = 1 CR4.VME = 1) | 16 | 3 | 0-2 | N/X | N/X | SV/X | N/X | N/X | 0/X | S/X | N/X | S/X | S/X | N/X | S/X | S/X | S/X | S/X | S/X | S/X | 2,3 |
| 16 | 3 | 3 | N | N | N | N | N | 0 | S | N | S | S | S | S | S | S | S | S | S | ||
| 32 | 3 | 0-2 | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | 1 | |
| 32 | 3 | 3 | S | N | N | S | N | 0 | S | N | S | S | S | S | S | S | S | S | S |
1. #GP fault - no flag update
2. #GP fault with no flag update if VIP=1 in EFLAGS register and IF=1 in FLAGS value on stack
3. #GP fault with no flag update if TF=1 in FLAGS value on stack
| Key | |
|---|---|
| S | Updated from stack |
| SV | Updated from IF (bit 9) in FLAGS value on stack |
| N | No change in value |
| X | No EFLAGS update |
| 0 | Value is cleared |
IF EFLAGS.VM = 0 (* Not in Virtual-8086 Mode *) THEN IF CPL = 0 OR CR0.PE = 0 THEN IF OperandSize = 32; THEN EFLAGS ← Pop(); (* 32-bit pop *) (* All non-reserved flags except RF, VIP, VIF, and VM can be modified; VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *) ELSE IF (Operandsize = 64) RFLAGS = Pop(); (* 64-bit pop *) (* All non-reserved flags except RF, VIP, VIF, and VM can be modified; VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *) ELSE (* OperandSize = 16 *) EFLAGS[15:0] ← Pop(); (* 16-bit pop *) (* All non-reserved flags can be modified. *) FI; ELSE (* CPL > 0 *) IF OperandSize = 32 THEN IF CPL > IOPL THEN EFLAGS ← Pop(); (* 32-bit pop *) (* All non-reserved bits except IF, IOPL, VIP, VIF, VM and RF can be modified; IF, IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *) ELSE EFLAGS ← Pop(); (* 32-bit pop *) (* All non-reserved bits except IOPL, VIP, VIF, VM and RF can be modified; IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *) FI; ELSE IF (Operandsize = 64) IF CPL > IOPL THEN RFLAGS ← Pop(); (* 64-bit pop *) (* All non-reserved bits except IF, IOPL, VIP, VIF, VM and RF can be modified; IF, IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *) ELSE RFLAGS ← Pop(); (* 64-bit pop *) (* All non-reserved bits except IOPL, VIP, VIF, VM and RF can be modified; IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *) FI; ELSE (* OperandSize = 16 *) EFLAGS[15:0] ← Pop(); (* 16-bit pop *) (* All non-reserved bits except IOPL can be modified; IOPL and all reserved bits are unaffected. *) FI; FI; ELSE (* In virtual-8086 mode *) IF IOPL = 3 THEN IF OperandSize = 32 THEN EFLAGS ← Pop(); (* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified; VIP, VIF, VM, IOPL and all reserved bits are unaffected. RF is cleared. *) ELSE EFLAGS[15:0] ← Pop(); FI; (* All non-reserved bits except IOPL can be modified; IOPL and all reserved bits are unaffected. *) FI; ELSE (* IOPL < 3 *) IF (Operandsize = 32) OR (CR4.VME = 0) THEN #GP(0); (* Trap to virtual-8086 monitor. *) ELSE (* Operandsize = 16 and CR4.VME = 1 *) tempFLAGS ← Pop(); IF (EFLAGS.VIP = 1 AND tempFLAGS[9] = 1) OR tempFLAGS[8] = 1 THEN #GP(0); ELSE EFLAGS.VIF ← tempFLAGS[9]; EFLAGS[15:0] ← tempFLAGS; (* All non-reserved bits except IOPL and IF can be modified; IOPL, IF, and all reserved bits are unaffected. *) FI; FI; FI; FI;
All flags may be affected; see the Operation section for details.
| #SS(0) | If the top of stack is not within the stack segment. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If an unaligned memory reference is made while CPL = 3 and alignment checking is enabled. |
| #UD | If the LOCK prefix is used. |
| #SS | If the top of stack is not within the stack segment. |
| #UD | If the LOCK prefix is used. |
| #GP(0) | If IOPL < 3 and VME is not enabled. |
| If IOPL < 3 and the 32-bit operand size is used. | |
| If IOPL < 3, EFLAGS.VIP = 1, and bit 9 (IF) is set in the FLAGS value on the stack. | |
| If IOPL < 3 and bit 8 (TF) is set in the FLAGS value on the stack. | |
| If an attempt is made to execute the POPF/POPFD instruction with an operand-size override prefix. | |
| #SS(0) | If the top of stack is not within the stack segment. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If an unaligned memory reference is made while alignment checking is enabled. |
| #UD | If the LOCK prefix is used. |
Same as for protected mode exceptions.
| #GP(0) | If the memory address is in a non-canonical form. |
| #SS(0) | If the stack address is in a non-canonical form. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |


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|
M480 BSP V3.05.005
The Board Support Package for M480 Series
|
#include <sc_reg.h>
Data Fields | |
| __IO uint32_t | DAT |
| __IO uint32_t | CTL |
| __IO uint32_t | ALTCTL |
| __IO uint32_t | EGT |
| __IO uint32_t | RXTOUT |
| __IO uint32_t | ETUCTL |
| __IO uint32_t | INTEN |
| __IO uint32_t | INTSTS |
| __IO uint32_t | STATUS |
| __IO uint32_t | PINCTL |
| __IO uint32_t | TMRCTL0 |
| __IO uint32_t | TMRCTL1 |
| __IO uint32_t | TMRCTL2 |
| __IO uint32_t | UARTCTL |
| __IO uint32_t | ACTCTL |
@addtogroup SC Smart Card Host Interface Controller(SC) Memory Mapped Structure for SC Controller
| SC_T::ACTCTL |
[0x004c] SC Activation Control Register
| Bits | Field | Descriptions |
| [4:0] | T1EXT | T1 Extend Time of Hardware Activation
This field provide the configurable cycles to extend the activation time T1 period. The cycle scaling factor is 2048. Extend cycles = (filled value * 2048) cycles. Refer to SC activation sequence in Figure 7.17-4. For example, SCLK = 4MHz, each cycle = 0.25us,. Filled 20 to this field Extend time = 20 * 2048 * 0.25us = 10.24 ms. Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 |
| SC_T::ALTCTL |
[0x0008] SC Alternate Control Register
| Bits | Field | Descriptions |
| [0] | TXRST | TX Software Reset
When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. 0 = No effect. 1 = Reset the TX internal state machine and pointers. Note: This bit will be auto cleared after reset is complete. |
| [1] | RXRST | Rx Software Reset
When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared. 0 = No effect. 1 = Reset the Rx internal state machine and pointers. Note: This bit will be auto cleared after reset is complete. |
| [2] | DACTEN | Deactivation Sequence Generator Enable Bit
This bit enables SC controller to initiate the card by deactivation sequence. 0 = No effect. 1 = Deactivation sequence generator Enabled. Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time. Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. |
| [3] | ACTEN | Activation Sequence Generator Enable Bit
This bit enables SC controller to initiate the card by activation sequence. 0 = No effect. 1 = Activation sequence generator Enabled. Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time. Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. Note4: During the activation sequence, RX is disabled automatically and can not receive data After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. |
| [4] | WARSTEN | Warm Reset Sequence Generator Enable Bit
This bit enables SC controller to initiate the card by warm reset sequence. 0 = No effect. 1 = Warm reset sequence generator Enabled. Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time. Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. Note4: During the warm reset sequence, RX is disabled automatically and can not receive data After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence. |
| [5] | CNTEN0 | Internal Timer0 Start Enable Bit
This bit enables Timer 0 to start counting User can fill 0 to stop it and set 1 to reload and count The counter unit is ETU base. 0 = Stops counting. 1 = Start counting. Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only. Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware. Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. |
| [6] | CNTEN1 | Internal Timer1 Start Enable Bit
This bit enables Timer 1 to start counting User can fill 0 to stop it and set 1 to reload and count The counter unit is ETU base. 0 = Stops counting. 1 = Start counting. Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware. Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. |
| [7] | CNTEN2 | Internal Timer2 Start Enable Bit
This bit enables Timer 2 to start counting User can fill 0 to stop it and set 1 to reload and count The counter unit is ETU base. 0 = Stops counting. 1 = Start counting. Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware. Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. |
| [9:8] | INITSEL | Initial Timing Selection
This fields indicates the initial timing of hardware activation, warm-reset or deactivation. The unit of initial timing is SC module clock. Activation: refer to SC Activation Sequence in Figure 7.17-54. Warm-reset: refer to Warm-Reset Sequence in Figure 7.17-5. Deactivation: refer to Deactivation Sequence in Figure 7.17-56. Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles. |
| [11] | ADACEN | Auto Deactivation When Card Removal
This bit is used for enable hardware auto deactivation when smart card is removed. 0 = Auto deactivation Disabled. 1 = Auto deactivation Enabled. Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. |
| [12] | RXBGTEN | Receiver Block Guard Time Function Enable Bit
This bit enables the receiver block guard time function. 0 = Receiver block guard time function Disabled. 1 = Receiver block guard time function Enabled. |
| [13] | ACTSTS0 | Internal Timer0 Active Status (Read Only)
This bit indicates the timer counter status of timer0. 0 = Timer0 is not active. 1 = Timer0 is active. Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). |
| [14] | ACTSTS1 | Internal Timer1 Active Status (Read Only)
This bit indicates the timer counter status of timer1. 0 = Timer1 is not active. 1 = Timer1 is active. Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). |
| [15] | ACTSTS2 | Internal Timer2 Active Status (Read Only)
This bit indicates the timer counter status of timer2. 0 = Timer2 is not active. 1 = Timer2 is active. Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). |
| [31] | SYNC | SYNC Flag Indicator (Read Only)
Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. 0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register. 1 = Last value is synchronizing. |
| SC_T::CTL |
[0x0004] SC Control Register
| Bits | Field | Descriptions |
| [0] | SCEN | SC Controller Enable Bit
Set this bit to 1 to enable SC operation. If this bit is cleared, 0 = SC will force all transition to IDLE state. 1 = SC controller is enabled and all function can work correctly. Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. |
| [1] | RXOFF | RX Transition Disable Control Bit
This bit is used for disable Rx transition function. 0 = The receiver Enabled. 1 = The receiver Disabled. Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. |
| [2] | TXOFF | TX Transition Disable Control Bit
This bit is used for disable Tx transition function. 0 = The transceiver Enabled. 1 = The transceiver Disabled. |
| [3] | AUTOCEN | Auto Convention Enable Bit
This bit is used for enable auto convention function. 0 = Auto-convention Disabled. 1 = Auto-convention Enabled. If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11. If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. |
| [5:4] | CONSEL | Convention Selection
00 = Direct convention. 01 = Reserved. 10 = Reserved. 11 = Inverse convention. Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. |
| [7:6] | RXTRGLV | Rx Buffer Trigger Level
When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. 00 = Rx Buffer Trigger Level with 01 bytes. 01 = Rx Buffer Trigger Level with 02 bytes. 10 = Rx Buffer Trigger Level with 03 bytes. 11 = Reserved. |
| [12:8] | BGT | Block Guard Time (BGT)
Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions This field indicates the counter for the bit length of block guard time According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it. Note: The real block guard time is BGT + 1. |
| [14:13] | TMRSEL | Timer Channel Selection
00 = All internal timer function Disabled. 11 = Internal 24 bit timer and two 8 bit timers Enabled User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]. Other configurations are reserved |
| [15] | NSB | Stop Bit Length
This field indicates the length of stop bit. 0 = The stop bit length is 2 ETU. 1= The stop bit length is 1 ETU. Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. |
| [18:16] | RXRTY | RX Error Retry Count Number
This field indicates the maximum number of receiver retries that are allowed when parity error has occurred. Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. Note2: This field cannot be changed when RXRTYEN enabled The change flow is to disable RXRTYEN first and then fill in new retry value. |
| [19] | RXRTYEN | RX Error Retry Enable Bit
This bit enables receiver retry function when parity error has occurred. 0 = RX error retry function Disabled. 1 = RX error retry function Enabled. Note: User must fill in the RXRTY value before enabling this bit. |
| [22:20] | TXRTY | TX Error Retry Count Number
This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. Note2: This field cannot be changed when TXRTYEN enabled The change flow is to disable TXRTYEN first and then fill in new retry value. |
| [23] | TXRTYEN | TX Error Retry Enable Bit
This bit enables transmitter retry function when parity error has occurred. 0 = TX error retry function Disabled. 1 = TX error retry function Enabled. |
| [25:24] | CDDBSEL | Card Detect De-bounce Selection
This field indicates the card detect de-bounce selection. 00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks. Other configurations are reserved. |
| [26] | CDLV | Card Detect Level Selection
0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected. 1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected. Note: User must select card detect level before Smart Card controller enabled. |
| [30] | SYNC | SYNC Flag Indicator (Read Only)
Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. 0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. 1 = Last value is synchronizing. |
| SC_T::DAT |
[0x0000] SC Receive/Transmit Holding Buffer Register
| Bits | Field | Descriptions |
| [7:0] | DAT | Receive/Transmit Holding Buffer
Write Operation: By writing data to DAT, the SC will send out an 8-bit data. Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed. Read Operation: By reading DAT, the SC will return an 8-bit received data. |
| SC_T::EGT |
| SC_T::ETUCTL |
[0x0014] SC Element Time Unit Control Register
| Bits | Field | Descriptions |
| [11:0] | ETURDIV | ETU Rate Divider
The field is used for ETU clock rate divider. The real ETU is ETURDIV + 1. Note: User can configure this field, but this field must be greater than 0x04. |
| SC_T::INTEN |
[0x0018] SC Interrupt Enable Control Register
| Bits | Field | Descriptions |
| [0] | RDAIEN | Receive Data Reach Interrupt Enable Bit
This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. 0 = Receive data reach trigger level interrupt Disabled. 1 = Receive data reach trigger level interrupt Enabled. |
| [1] | TBEIEN | Transmit Buffer Empty Interrupt Enable Bit
This field is used to enable transmit buffer empty interrupt. 0 = Transmit buffer empty interrupt Disabled. 1 = Transmit buffer empty interrupt Enabled. |
| [2] | TERRIEN | Transfer Error Interrupt Enable Bit
This field is used to enable transfer error interrupt The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]). 0 = Transfer error interrupt Disabled. 1 = Transfer error interrupt Enabled. |
| [3] | TMR0IEN | Timer0 Interrupt Enable Bit
This field is used to enable Timer0 interrupt function. 0 = Timer0 interrupt Disabled. 1 = Timer0 interrupt Enabled. |
| [4] | TMR1IEN | Timer1 Interrupt Enable Bit
This field is used to enable the Timer1 interrupt function. 0 = Timer1 interrupt Disabled. 1 = Timer1 interrupt Enabled. |
| [5] | TMR2IEN | Timer2 Interrupt Enable Bit
This field is used to enable Timer2 interrupt function. 0 = Timer2 interrupt Disabled. 1 = Timer2 interrupt Enabled. |
| [6] | BGTIEN | Block Guard Time Interrupt Enable Bit
This field is used to enable block guard time interrupt in receive direction. 0 = Block guard time interrupt Disabled. 1 = Block guard time interrupt Enabled. Note: This bit is valid only for receive direction block guard time. |
| [7] | CDIEN | Card Detect Interrupt Enable Bit
This field is used to enable card detect interrupt The card detect status is CDPINSTS (SCn_STATUS[13]). 0 = Card detect interrupt Disabled. 1 = Card detect interrupt Enabled. |
| [8] | INITIEN | Initial End Interrupt Enable Bit
This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt. 0 = Initial end interrupt Disabled. 1 = Initial end interrupt Enabled. |
| [9] | RXTOIEN | Receiver Buffer Time-out Interrupt Enable Bit
This field is used to enable receiver buffer time-out interrupt. 0 = Receiver buffer time-out interrupt Disabled. 1 = Receiver buffer time-out interrupt Enabled. |
| [10] | ACERRIEN | Auto Convention Error Interrupt Enable Bit
This field is used to enable auto-convention error interrupt. 0 = Auto-convention error interrupt Disabled. 1 = Auto-convention error interrupt Enabled. |
| SC_T::INTSTS |
[0x001c] SC Interrupt Status Register
| Bits | Field | Descriptions |
| [0] | RDAIF | Receive Data Reach Interrupt Status Flag (Read Only)
This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag. 0 = Number of receive buffer is less than RXTRGLV setting. 1 = Number of receive buffer data equals the RXTRGLV setting. Note: This bit is read only If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically. |
| [1] | TBEIF | Transmit Buffer Empty Interrupt Status Flag (Read Only)
This field is used for transmit buffer empty interrupt status flag. 0 = Transmit buffer is not empty. 1 = Transmit buffer is empty. Note: This bit is read only If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically. |
| [2] | TERRIF | Transfer Error Interrupt Status Flag
This field is used for transfer error interrupt status flag The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]). 0 = Transfer error interrupt did not occur. 1 = Transfer error interrupt occurred. Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR. Note2: This bit can be cleared by writing 1 to it. |
| [3] | TMR0IF | Timer0 Interrupt Status Flag
This field is used for Timer0 interrupt status flag. 0 = Timer0 interrupt did not occur. 1 = Timer0 interrupt occurred. Note: This bit can be cleared by writing 1 to it. |
| [4] | TMR1IF | Timer1 Interrupt Status Flag
This field is used for Timer1 interrupt status flag. 0 = Timer1 interrupt did not occur. 1 = Timer1 interrupt occurred. Note: This bit can be cleared by writing 1 to it. |
| [5] | TMR2IF | Timer2 Interrupt Status Flag
This field is used for Timer2 interrupt status flag. 0 = Timer2 interrupt did not occur. 1 = Timer2 interrupt occurred. Note: This bit can be cleared by writing 1 to it. |
| [6] | BGTIF | Block Guard Time Interrupt Status Flag
This field is used for indicate block guard time interrupt status flag in receive direction. 0 = Block guard time interrupt did not occur. 1 = Block guard time interrupt occurred. Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled. Note2: This bit can be cleared by writing 1 to it. |
| [7] | CDIF | Card Detect Interrupt Status Flag (Read Only)
This field is used for card detect interrupt status flag The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]). 0 = Card detect event did not occur. 1 = Card detect event occurred. Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. |
| [8] | INITIF | Initial End Interrupt Status Flag
This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag. 0 = Initial sequence is not complete. 1 = Initial sequence is completed. Note: This bit can be cleared by writing 1 to it. |
| [9] | RXTOIF | Receive Buffer Time-out Interrupt Status Flag (Read Only)
This field is used for indicate receive buffer time-out interrupt status flag. 0 = Receive buffer time-out interrupt did not occur. 1 = Receive buffer time-out interrupt occurred. Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it. |
| [10] | ACERRIF | Auto Convention Error Interrupt Status Flag
This field indicates auto convention sequence error. 0 = Received TS at ATR state is 0x3B or 0x3F. 1 = Received TS at ATR state is neither 0x3B nor 0x3F. Note: This bit can be cleared by writing 1 to it. |
| SC_T::PINCTL |
[0x0024] SC Pin Control State Register
| Bits | Field | Descriptions |
| [0] | PWREN | SCn_PWR Pin Signal
User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level. Write this field to drive SCn_PWR pin Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. Read this field to get SCn_PWR signal status. 0 = SCn_PWR signal status is low. 1 = SCn_PWR signal status is high. Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. |
| [1] | RSTEN | SCn_RST Pin Signal
User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level. Write this field to drive SCn_RST pin. 0 = Drive SCn_RST pin to low. 1 = Drive SCn_RST pin to high. Read this field to get SCn_RST signal status. 0 = SCn_RST signal status is low. 1 = SCn_RST signal status is high. Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. |
| [6] | CLKKEEP | SC Clock Enable Bit
0 = SC clock generation Disabled. 1 = SC clock always keeps free running. Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. |
| [9] | SCDATA | SCn_DATA Pin Signal
This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit. 0 = Drive SCn_DATA pin to low. 1 = Drive SCn_DATA pin to high. Read this field to get SCn_DATA signal status. 0 = SCn_DATA signal status is low. 1 = SCn_DATA signal status is high. Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when SC is in these modes. |
| [11] | PWRINV | SCn_PWR Pin Inverse
This bit is used for inverse the SCn_PWR pin. There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). PWRINV is 0 and PWREN is 0, SCn_PWR pin is 0. PWRINV is 0 and PWREN is 1, SCn_PWR pin is 1. PWRINV is 1 and PWREN is 0, SCn_PWR pin is 1. PWRINV is 1 and PWREN is 1, SCn_PWR pin is 0. Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). |
| [16] | DATASTS | SCn_DATA Pin Status (Read Only)
This bit is the pin status of SCn_DATA. 0 = The SCn_DATA pin status is low. 1 = The SCn_DATA pin status is high. |
| [17] | PWRSTS | SCn_PWR Pin Status (Read Only)
This bit is the pin status of SCn_PWR. 0 = SCn_PWR pin to low. 1 = SCn_PWR pin to high. |
| [18] | RSTSTS | SCn_RST Pin Status (Read Only)
This bit is the pin status of SCn_RST. 0 = SCn_RST pin is low. 1 = SCn_RST pin is high. |
| [30] | SYNC | SYNC Flag Indicator (Read Only)
Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. 0 = Synchronizing is completion, user can write new data to SCn_PINCTL register. 1 = Last value is synchronizing. |
| SC_T::RXTOUT |
[0x0010] SC Receive Buffer Time-out Counter Register
| Bits | Field | Descriptions |
| [8:0] | RFTM | SC Receiver FIFO Time-out Counter
The time-out down counter resets and starts counting whenever the RX buffer received a new data Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RBTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RBTOIEN (SCn_INTEN[9]) is enabled. Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5. Note2: Filling in all 0 to this field indicates to disable this function. |
| SC_T::STATUS |
[0x0020] SC Transfer Status Register
| Bits | Field | Descriptions |
| [0] | RXOV | Receive Overflow Error Status Flag
This bit is set when Rx buffer overflow. 0 = Rx buffer is not overflow. 1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes). Note: This bit can be cleared by writing 1 to it. |
| [1] | RXEMPTY | Receive Buffer Empty Status Flag (Read Only)
This bit indicates Rx buffer empty or not. 0 = Rx buffer is not empty. 1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU. |
| [2] | RXFULL | Receive Buffer Full Status Flag (Read Only)
This bit indicates Rx buffer full or not. 0 = Rx buffer count is less than 4. 1 = Rx buffer count equals to 4. |
| [4] | PEF | Receiver Parity Error Status Flag
This bit is set to logic 1 whenever the received character does not have a valid parity bit. 0 = Receiver parity error flag did not occur. 1 = Receiver parity error flag occurred. Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. |
| [5] | FEF | Receiver Frame Error Status Flag
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). 0 = Receiver frame error flag did not occur. 1 = Receiver frame error flag occurred. Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. |
| [6] | BEF | Receiver Break Error Status Flag
This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bit). 0 = Receiver break error flag did not occur. 1 = Receiver break error flag occurred. Note1: This bit can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. |
| [8] | TXOV | Transmit Overflow Error Interrupt Status Flag
This bit is set when Tx buffer overflow. 0 = Tx buffer is not overflow. 1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]). Note: This bit can be cleared by writing 1 to it. |
| [9] | TXEMPTY | Transmit Buffer Empty Status Flag (Read Only)
This bit indicates TX buffer empty or not. 0 = Tx buffer is not empty. 1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register. Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). |
| [10] | TXFULL | Transmit Buffer Full Status Flag (Read Only)
This bit indicates Tx buffer full or not. 0 = Tx buffer count is less than 4. 1 = Tx buffer count equals to 4. |
| [11] | CREMOVE | Card Removal Status of SCn_CD Pin
This bit is set whenever card has been removal. 0 = No effect. 1 = Card removed. Note1: This bit can be cleared by writing 1 to it. Note2: Card detect function will start after SCEN (SCn_CTL[0]) set. |
| [12] | CINSERT | Card Insert Status of SCn_CD Pin
This bit is set whenever card has been inserted. 0 = No effect. 1 = Card insert. Note1: This bit can be cleared by writing 1 to it. Note2: The card detect function will start after SCEN (SCn_CTL[0]) set. |
| [13] | CDPINSTS | Card Detect Pin Status (Read Only)
This bit is the pin status of SCn_CD. 0 = The SCn_CD pin state at low. 1 = The SCn_CD pin state at high. |
| [18:16] | RXPOINT | Receive Buffer Pointer Status (Read Only)
This field indicates the Rx buffer pointer status When SC controller receives one byte from external device, RXPOINT increases one When one byte of Rx buffer is read by CPU, RXPOINT decreases one. |
| [21] | RXRERR | Receiver Retry Error
This bit is used for receiver error retry and set by hardware. 0 = No Rx retry transfer. 1 = Rx has any error and retries transfer. Note1: This bit can be cleared by writing 1 to it. Note2 This bit is a flag and cannot generate any interrupt to CPU. Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. |
| [22] | RXOVERR | Receiver over Retry Error
This bit is used for receiver retry counts over than retry number limitation. 0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1. 1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1. Note1: This bit can be cleared by writing 1 to it. Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. |
| [23] | RXACT | Receiver in Active Status Flag (Read Only)
This bit indicates Rx transfer status. 0 = This bit is cleared automatically when Rx transfer is finished. 1 = This bit is set by hardware when Rx transfer is in active. Note: This bit is read only. |
| [26:24] | TXPOINT | Transmit Buffer Pointer Status (Read Only)
This field indicates the Tx buffer pointer status When CPU writes data into SCn_DAT, TXPOINT increases one When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. |
| [29] | TXRERR | Transmitter Retry Error
This bit is used for indicate transmitter error retry and set by hardware. 0 = No Tx retry transfer. 1 = Tx has any error and retries transfer. Note1: This bit can be cleared by writing 1 to it. Note2: This bit is a flag and cannot generate any interrupt to CPU. |
| [30] | TXOVERR | Transmitter over Retry Error
This bit is used for transmitter retry counts over than retry number limitation. 0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1. 1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1. Note: This bit can be cleared by writing 1 to it. |
| [31] | TXACT | Transmit in Active Status Flag (Read Only)
This bit indicates Tx transmit status. 0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed. 1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted. Note: This bit is read only. |
| SC_T::TMRCTL0 |
[0x0028] SC Internal Timer0 Control Register
| Bits | Field | Descriptions |
| [23:0] | CNT | Timer0 Counter Value
This field indicates the internal Timer0 counter values. Note: Unit of Timer0 counter is ETU base. |
| [27:24] | OPMODE | Timer0 Operation Mode Selection
This field indicates the internal 24-bit Timer0 operation selection. Refer to Table 7.17-3 for programming Timer0. |
| [31] | SYNC | SYNC Flag Indicator (Read Only)
Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. 0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register. 1 = Last value is synchronizing. |
| SC_T::TMRCTL1 |
[0x002c] SC Internal Timer1 Control Register
| Bits | Field | Descriptions |
| [7:0] | CNT | Timer 1 Counter Value
This field indicates the internal Timer1 counter values. Note: Unit of Timer1 counter is ETU base. |
| [27:24] | OPMODE | Timer 1 Operation Mode Selection
This field indicates the internal 8-bit Timer1 operation selection. Refer to Table 7.17-3 for programming Timer1. |
| [31] | SYNC | SYNC Flag Indicator (Read Only)
Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. 0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register. 1 = Last value is synchronizing. |
| SC_T::TMRCTL2 |
[0x0030] SC Internal Timer2 Control Register
| Bits | Field | Descriptions |
| [7:0] | CNT | Timer 2 Counter Value
This field indicates the internal Timer2 counter values. Note: Unit of Timer2 counter is ETU base. |
| [27:24] | OPMODE | Timer 2 Operation Mode Selection
This field indicates the internal 8-bit Timer2 operation selection Refer to Table 7.17-3 for programming Timer2. |
| [31] | SYNC | SYNC Flag Indicator (Read Only)
Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. 0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register. 1 = Last value is synchronizing. |
| SC_T::UARTCTL |
[0x0034] SC UART Mode Control Register
| Bits | Field | Descriptions |
| [0] | UARTEN | UART Mode Enable Bit
Sets this bit to enable UART mode function. 0 = Smart Card mode. 1 = UART mode. Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0. Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0. Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. |
| [5:4] | WLS | Word Length Selection
This field is used for select UART data length. 00 = Word length is 8 bits. 01 = Word length is 7 bits. 10 = Word length is 6 bits. 11 = Word length is 5 bits. Note: In smart card mode, this WLS must be '00'. |
| [6] | PBOFF | Parity Bit Disable Control
Sets this bit is used for disable parity check function. 0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. 1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. Note: In smart card mode, this field must be '0' (default setting is with parity bit). |
| [7] | OPE | Odd Parity Enable Bit
This is used for odd/even parity selection. 0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. 1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. Note: This bit has effect only when PBOFF bit is '0'. |


Using Gambit as a standalone package#
This file contains some information and tests for the use of Gambit as a stand alone package.
To install gambit as an optional package run (from root of Sage):
$ sage -i gambit
The python API documentation for gambit shows various examples that can be run easily in IPython. To run the IPython packaged with Sage run (from root of Sage):
$ ./sage --ipython
Here is an example that constructs the Prisoner’s Dilemma:
In [1]: import gambit
In [2]: g = gambit.Game.new_table([2,2])
In [3]: g.title = "A prisoner's dilemma game"
In [4]: g.players[0].label = "Alphonse"
In [5]: g.players[1].label = "Gaston"
In [6]: g
Out[6]:
NFG 1 R "A prisoner's dilemma game" { "Alphonse" "Gaston" }
{ { "1" "2" }
{ "1" "2" }
}
""
{
{ "" 0, 0 }
{ "" 0, 0 }
{ "" 0, 0 }
{ "" 0, 0 }
}
1 2 3 4
In [7]: g.players[0].strategies
Out[7]: [<Strategy [0] '1' for player 'Alphonse' in game 'A
prisoner's dilemma game'>,
<Strategy [1] '2' for player 'Alphonse' in game 'A prisoner's dilemma game'>]
In [8]: len(g.players[0].strategies)
Out[8]: 2
In [9]: g.players[0].strategies[0].label = "Cooperate"
In [10]: g.players[0].strategies[1].label = "Defect"
In [11]: g.players[0].strategies
Out[11]: [<Strategy [0] 'Cooperate' for player 'Alphonse' in game 'A
prisoner's dilemma game'>,
<Strategy [1] 'Defect' for player 'Alphonse' in game 'A prisoner's dilemma game'>]
In [12]: g[0,0][0] = 8
In [13]: g[0,0][1] = 8
In [14]: g[0,1][0] = 2
In [15]: g[0,1][1] = 10
In [16]: g[1,0][0] = 10
In [17]: g[1,1][1] = 2
In [18]: g[1,0][1] = 2
In [19]: g[1,1][0] = 5
In [20]: g[1,1][1] = 5
Here is a list of the various solvers available in gambit:
ExternalEnumPureSolver
ExternalEnumMixedSolver
ExternalLPSolver
ExternalLCPSolver
ExternalSimpdivSolver
ExternalGlobalNewtonSolver
ExternalEnumPolySolver
ExternalLyapunovSolver
ExternalIteratedPolymatrixSolver
ExternalLogitSolver
Here is how to use the ExternalEnumPureSolver
:
In [21]: solver = gambit.nash.ExternalEnumPureSolver()
In [22]: solver.solve(g)
Out[22]: [<NashProfile for 'A prisoner's dilemma game': [Fraction(0, 1), Fraction(1, 1), Fraction(0, 1), Fraction(1, 1)]>]
Note that the above finds the equilibria by investigating all potential pure pure strategy pairs. This will fail to find all Nash equilibria in certain games. For example here is an implementation of Matching Pennies:
In [1]: import gambit
In [2]: g = gambit.Game.new_table([2,2])
In [3]: g[0, 0][0] = 1
In [4]: g[0, 0][1] = -1
In [5]: g[0, 1][0] = -1
In [6]: g[0, 1][1] = 1
In [7]: g[1, 0][0] = -1
In [8]: g[1, 0][1] = 1
In [9]: g[1, 1][0] = 1
In [10]: g[1, 1][1] = -1
In [11]: solver = gambit.nash.ExternalEnumPureSolver()
In [12]: solver.solve(g)
Out[12]: []
If we solve this with the LCP
solver we get the expected Nash equilibrium:
In [13]: solver = gambit.nash.ExternalLCPSolver()
In [14]: solver.solve(g)
Out[14]: [<NashProfile for '': [0.5, 0.5, 0.5, 0.5]>]
Note that the above examples only show how to build and find equilibria for two player strategic form games. Gambit supports multiple player games as well as extensive form games: for more details see http://www.gambit-project.org/.
If one really wants to use gambit directly in Sage (without using the
NormalFormGame
class as a wrapper) then integers must first be
converted to Python integers (due to the preparser). Here is an example
showing the Battle of the Sexes:
sage: import gambit # optional - gambit
sage: g = gambit.Game.new_table([2,2]) # optional - gambit
sage: g[int(0), int(0)][int(0)] = int(2) # optional - gambit
sage: g[int(0), int(0)][int(1)] = int(1) # optional - gambit
sage: g[int(0), int(1)][int(0)] = int(0) # optional - gambit
sage: g[int(0), int(1)][int(1)] = int(0) # optional - gambit
sage: g[int(1), int(0)][int(0)] = int(0) # optional - gambit
sage: g[int(1), int(0)][int(1)] = int(0) # optional - gambit
sage: g[int(1), int(1)][int(0)] = int(1) # optional - gambit
sage: g[int(1), int(1)][int(1)] = int(2) # optional - gambit
sage: solver = gambit.nash.ExternalLCPSolver() # optional - gambit
sage: solver.solve(g) # optional - gambit
[<NashProfile for '': [[1.0, 0.0], [1.0, 0.0]]>,
<NashProfile for '': [[0.6666666667, 0.3333333333], [0.3333333333, 0.6666666667]]>,
<NashProfile for '': [[0.0, 1.0], [0.0, 1.0]]>]
AUTHOR:
Vince Knight (11-2014): Original version


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|
TrackracerAR
0.9.2
|
Interface for CalibrateState More...
Public Member Functions | |
| void | DoStart () |
| Transitions to BuildStateMachine More... | |
| void | Restart () |
| Restarts the AR Session and resets the calibration progress More... | |
Interface for CalibrateState
| void ICalibrateState.DoStart | ( | ) |
Transitions to BuildStateMachine
Implemented in CalibrateState.
| void ICalibrateState.Restart | ( | ) |
Restarts the AR Session and resets the calibration progress
Implemented in CalibrateState.


{% extends 'base.html' %} {% block title %}{{title}}{% endblock %} {% block head %} {% include '_components/_social.html' %} {% endblock %} {% block hearst_title %}Economics{% endblock %} {% block hearst_class %}article{% endblock %} {% block content %} {% include '_components/_header.html' %} Is Airbnb to blame for high housing prices in SF? By Carolyn Said July 22, 2016 Brian and Sarah Grzybowski had to find a new apartment in Potrero Hill after their landlord evicted them last year. James Tensuan, Special to The Chronicle {% include '_text/economics.html' %} Next story How The Chronicle crunched the Airbnb data {% endblock %} {% block javascript %} {% endblock %}
By Carolyn Said
July 22, 2016
Brian and Sarah Grzybowski had to find a new apartment in Potrero Hill after their landlord evicted them last year. James Tensuan, Special to The Chronicle
How The Chronicle crunched the Airbnb data


Object
the Ultimate Super ClassObject
classObject
class. Object
class includes several inherited methods that we will look at closer in this lesson.
1 public class Parent{
2 // implementation not shown
3 }
4
5 public class Child extends Parent{
6 // implementation not shown
7 }
String toString()
: Returns a String representation of an object.boolean equals(Object obj)
: Returns a boolean representing whether two objects are equal or not.
Card
classCard.java
: Review the starter code. (Posted to Classroom). CardTest.java
: Create with main()
method for testing. toString()
methodDiscuss benefits of using @Override annotation.
1 @Override
2 public String toString(){
3 return rank + suit;
4 }
toString()
1 // creates the Ace of Spades
2 Card c1 = new Card(12, 0);
3 // creates a random card
4 Card c2 = new Card();
5 System.out.println(c1);
6 System.out.println(c2);
Can't see the card suits?
Go to Project > Settings
and change encoding to UTF-8
.equals()
methodidentity vs. equality
equals
method is to determine whether two objects are equivalent to each other.==
operator is to determine whether two objects share the same identity..equals()
method from the Object
class only checks for identity. In other words,
it is no different than the ==
operator..equals()
methodsimplified overload (not a proper override)
Think about this. Why?
1 public boolean equals(Card other){
2 return this.rank.equals(other.rank) && this.suit == other.suit;
3 }
.equals()
overload1 Card c1 = new Card(12, 0);
2 Card c2 = new Card(12, 0);
3 // should print false (different references)
4 System.out.println(c1 == c2);
5 // should print true (both ace of spades)
6 System.out.println(c1.equals(c2));
Object
class takes an Object
instance as a parameter. Object
class will be called.c2 referenced polymorphically
1 Card c1 = new Card(12, 0);
2 Object c2 = new Card(12, 0);
3 System.out.println(c1.equals(c2));
.equals()
We will start by changing the method signature to:
1 @Override
2 public boolean equals(Object other)
Notice that this will not compile. Java knows that not all Object
instances are Card
instances and therefore may
not have a rank or suit. To get around this, we have to cast the object as Card.
1 @Override
2 public boolean equals(Object other){
3 Card otherCard = (Card) other;
NOTE: Casting doesn't do anything. It just is our way of telling the Java compiler that we know what we are doing, and we will ensure that other
is a valid Card
object.
We have now opened ourselves up to a potential issue by doing this. Since all references are related to the Object
class, it is now possible to pass practically anything we want to this method. If other
isn't actually a Card
instance a ClassCastException
will be generated at runtime.
1 Card c1 = new Card();
2 String c2 = "Ace of Spades";
3
4 // Will crash at runtime
5 System.out.println(c1.equals(c2));
Why doesn't the compiler catch this?
instanceof
operatorinstanceof
operator can be used to check for an is-a relationship. true
as long as the type is above it in the class hierarchy. demo instanceof
1 Card c1 = new Card();
2 String c2 = "Ace of Spades";
3 System.out.println(c1 instanceOf Card) // true c1 is a Card
4 System.out.println(c1 instanceOf String) // false c1 is NOT a String
5 System.out.println(c1 instanceOf Object) // true c1 is an Object
6 System.out.println(c2 instanceOf Card) // false c2 is NOT a Card
7 System.out.println(c2 instanceOf String) // true c2 is a String
8 System.out.println(c2 instanceOf Object) // true c2 is an Object
.equals()
method completeTo prevent this we can use the instanceOf
operator to check if the object actually is a Card
before trying to cast it as one. If it's not a Card, we will simply return false
and avoid the runtime error.
1 public boolean equals(Object other){
2 if(!(other instanceOf Card)){
3 return false;
4 }
5
6 Card otherCard = (Card) other;
7 return this.rank.equals(otherCard.rank) && this.suit == otherCard.suit;
8 }
Write a class BlackjackHand
class with the following design.
BlackjackHand()
: The constructor must initialize card1
and card2
using the random Card()
constructor. The value of the hand will be set by adding the values of the cards except when the sum is 22
(both cards are Aces). In this case the value of the hand must be set to 12
.
toString()
: A string representation of the hand must show both cards and the value of the hand in an arrangement of your choice.
equals()
: Must return true
if and only if the value of the hands are equal. This must be a proper override similar to the Card
class.
Submit this file to Classroom.
Use this BlackjackHand Class to run the following simulations. Simulation results will be entered into a Google Form. Do not submit your simulation code.
.equals()
method to determine how many times the dealer and player were dealt hands with equal values. (Enter in Google Form)| Table of Contents | t |
|---|---|
| Exposé | ESC |
| Full screen slides | e |
| Presenter View | p |
| Source Files | s |
| Slide Numbers | n |
| Toggle screen blanking | b |
| Show/hide slide context | c |
| Notes | 2 |
| Help | h |


Confirm changes
You have made the following changes, which have been highlighted in the table below:
-
{% for key_change, display_change in g.session.edited_fields.items() | sort() %}
- {{ display_change }} {% endfor %}
Update light obstruction notice
{% if not charge_item.end_date %} {% endif %} {% endif %} {% if charge_item.end_date %}This charge was cancelled on {{ charge_item.end_date.strftime('%d %B %Y').lstrip("0") }}


FuzzyClock ÒÓFuzzyClock dock É
The format of "Localizable.strings" has changed and is now more flexible to place the hourString on different positions.
All standard languages are available through the system control panel "Languages". Other localizations are available through FuzzyClock Preferences.
You can use this software for free whenever and whereever you want. Nevertheless I will be happy about your suggestions via mail to<EMAIL_ADDRESS>or better with a postcard of your home town to:
Guido Neitzer
Humperdinckstr. 8
53121 Bonn
Germany
You can find new versions at the Objectpark homepage. They will be announced at Stepwise and forthcoming also at Versiontracker .
Copyright (c) 2001 Guido Neitzer, Bonn, Germany
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files.
The above copyright notice and this permission notice shall be included in all copies of the Software.
 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.


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Presbyterian hopes to end skid vs Albany
by Associated PressAlbany (3-3) vs. Presbyterian (1-5)
People’s United Center, Hamden, Connecticut; Sunday, 1 p.m. EST
BOTTOM LINE: Presbyterian looks to end its four-game losing streak as it battles Albany. Albany took care of Sacred Heart by seven in its last outing. Presbyterian lost 73-64 on the road to Quinnipiac in its most recent game.
LEADING THE CHARGE: Cory Hightower has averaged 12.7 points and 5.8 rebounds to lead the charge for the Blue Hose. Complementing Hightower is Chris Martin, who is putting up 7.3 points, 5.8 rebounds and four assists per game. The Great Danes have been led by Cameron Healy, who is averaging 17.3 points and 4.5 rebounds.
SPARKING THE OFFENSE: Hightower has directly created 46 percent of all Presbyterian field goals over the last three games. The freshman forward has 18 field goals and 15 assists in those games.
ASSIST RATIOS: The Great Danes have recently converted baskets via assists more often than the Blue Hose. Presbyterian has 48 assists on 72 field goals (66.7 percent) across its past three contests while Albany has assists on 59 of 86 field goals (68.6 percent) during its past three games.
DID YOU KNOW: Albany has committed a turnover on just 17.8 percent of its possessions this season, which is the top rate among all America East teams. The Great Danes have turned the ball over only 12.7 times per game this season.
___
For more AP college basketball coverage: https://apnews.com/Collegebasketball and http://twitter.com/AP_Top25
___
This was generated by Automated Insights, http://www.automatedinsights.com/ap, using data from STATS LLC, https://www.stats.com


Honzi/Personal Bests/Hearthstone/The Grand Tournament
| Arcane Blast
| 1
| Epic
| Mage
| 1
|
|
| Brave Archer
| 1
| Common
| Hunter
| 2
|
|
| Buccaneer
| 1
| Common
| Rogue
| 2
|
|
| Competitive Spirit
| 1
| Rare
| Paladin
| 2
|
|
| Flash Heal
| 1
| Common
| Priest
| 2
|
|
| Gadgetzan Jouster
| 1
| Common
| Neutral
| 2
|
|
| Injured Kvaldir
| 1
| Rare
| Neutral
| 2
|
|
| Living Roots
| 1
| Common
| Druid
| 2
|
|
| Lowly Squire
| 1
| Common
| Neutral
| 2
|
|
| Power Word: Glory
| 1
| Common
| Priest
| 2
|
|
| Tournament Attendee
| 1
| Common
| Neutral
| 2
|
|
| Alexstrasza's Champion
| 2
| Rare
| Warrior
| 2
|
|
| Ancestral Knowledge
| 2
| Common
| Shaman
| 2
|
|
| Argent Lance
| 2
| Rare
| Paladin
| 2
|
|
| Argent Watchman
| 2
| Rare
| Neutral
| 2
| 1
|
| Bear Trap
| 2
| Common
| Hunter
| 2
|
|
| Bolster
| 2
| Common
| Warrior
| 2
|
|
| Boneguard Lieutenant
| 2
| Common
| Neutral
| 2
|
|
| Confuse
| 2
| Epic
| Priest
| 2
|
|
| Convert
| 2
| Rare
| Priest
| 2
|
|
| Cutpurse
| 2
| Rare
| Rogue
| 2
|
|
| Darnassus Aspirant
| 2
| Rare
| Druid
| 2
|
|
| Demonfuse
| 2
| Common
| Warlock
| 2
|
|
| Druid of the Saber
| 2
| Common
| Druid
| 2
|
|
| Fallen Hero
| 2
| Rare
| Mage
| 2
|
|
| Flame Juggler
| 2
| Common
| Neutral
| 2
|
|
| Garrison Commander
| 2
| Epic
| Neutral
| 1
|
|
| King's Elekk
| 2
| Common
| Hunter
| 2
| 2
|
| Lance Carrier
| 2
| Common
| Neutral
| 2
|
|
| Lock and Load
| 2
| Epic
| Hunter
| 1
|
|
| Sparring Partner
| 2
| Rare
| Warrior
| 2
|
|
| Tiny Knight of Evil
| 2
| Rare
| Warlock
| 2
|
|
| Totem Golem
| 2
| Common
| Shaman
| 2
|
|
| Undercity Valiant
| 2
| Common
| Rogue
| 2
|
|
| Wrathguard
| 2
| Common
| Warlock
| 2
|
|
| Wyrmrest Agent
| 2
| Rare
| Priest
| 2
|
|
| Argent Horserider
| 3
| Common
| Neutral
| 2
|
|
| Bash
| 3
| Common
| Warrior
| 2
|
|
| Beneath the Grounds
| 3
| Epic
| Rogue
| 1
|
|
| Burgle
| 3
| Rare
| Rogue
| 2
|
|
| Coliseum Manager
| 3
| Rare
| Neutral
| 2
|
|
| Dragonhawk Rider
| 3
| Common
| Neutral
| 2
|
|
| Dreadscale
| 3
| Legendary
| Hunter
| 1
|
|
| Effigy
| 3
| Rare
| Mage
| 2
|
|
| Elemental Destruction
| 3
| Epic
| Shaman
| 1
|
|
| Fencing Coach
| 3
| Rare
| Neutral
| 2
| 1
|
| Healing Wave
| 3
| Rare
| Shaman
| 2
| 1
|
| Ice Rager
| 3
| Common
| Neutral
| 2
|
|
| King's Defender
| 3
| Rare
| Warrior
| 2
|
|
| Light's Champion
| 3
| Rare
| Neutral
| 2
|
|
| Orgrimmar Aspirant
| 3
| Common
| Warrior
| 2
|
|
| Polymorph: Boar
| 3
| Rare
| Mage
| 2
|
|
| Powershot
| 3
| Rare
| Hunter
| 2
|
|
| Saboteur
| 3
| Rare
| Neutral
| 2
|
|
| Seal of Champions
| 3
| Common
| Paladin
| 2
| 1
|
| Shadowfiend
| 3
| Epic
| Priest
| 1
|
|
| Shady Dealer
| 3
| Rare
| Rogue
| 2
|
|
| Silent Knight
| 3
| Common
| Neutral
| 2
|
|
| Silver Hand Regent
| 3
| Common
| Neutral
| 2
|
|
| Spellslinger
| 3
| Common
| Mage
| 2
| 2
|
| Tuskarr Totemic
| 3
| Common
| Shaman
| 2
|
|
| Warhorse Trainer
| 3
| Common
| Paladin
| 2
|
|
| Armored Warhorse
| 4
| Rare
| Neutral
| 2
|
|
| Astral Communion
| 4
| Epic
| Druid
| 2
|
|
| Dalaran Aspirant
| 4
| Common
| Mage
| 2
|
|
| Draenei Totemcarver
| 4
| Rare
| Shaman
| 2
|
|
| Dreadsteed
| 4
| Epic
| Warlock
| 2
|
|
| Evil Heckler
| 4
| Common
| Neutral
| 2
|
|
| Fist of Jaraxxus
| 4
| Rare
| Warlock
| 2
|
|
| Frigid Snobold
| 4
| Common
| Neutral
| 2
|
|
| Holy Champion
| 4
| Common
| Priest
| 2
|
|
| Magnataur Alpha
| 4
| Rare
| Warrior
| 1
|
|
| Maiden of the Lake
| 4
| Common
| Neutral
| 2
|
|
| Murloc Knight
| 4
| Common
| Paladin
| 2
| 1
|
| Poisoned Blade
| 4
| Epic
| Rogue
| 1
|
|
| Refreshment Vendor
| 4
| Common
| Neutral
| 2
| 1
|
| Savage Combatant
| 4
| Rare
| Druid
| 2
|
|
| Spawn of Shadows
| 4
| Rare
| Priest
| 2
|
|
| Tournament Medic
| 4
| Common
| Neutral
| 2
|
|
| Twilight Guardian
| 4
| Epic
| Neutral
| 2
|
|
| Wildwalker
| 4
| Common
| Druid
| 2
|
|
| Clockwork Knight
| 5
| Common
| Neutral
| 2
|
|
| Flame Lance
| 5
| Common
| Mage
| 2
|
|
| Kvaldir Raider
| 5
| Common
| Neutral
| 2
|
|
| Mukla's Champion
| 5
| Common
| Neutral
| 2
|
|
| Ram Wrangler
| 5
| Rare
| Hunter
| 2
|
|
| Recruiter
| 5
| Epic
| Neutral
|
| 1
|
| Shado-Pan Rider
| 5
| Common
| Rogue
| 2
|
|
| Thunder Bluff Valiant
| 5
| Rare
| Shaman
| 2
|
|
| Tuskarr Jouster
| 5
| Rare
| Paladin
| 2
|
|
| Ball of Spiders
| 6
| Rare
| Hunter
| 2
| 1
|
| Bolf Ramshield
| 6
| Legendary
| Neutral
| 1
|
|
| Enter the Coliseum
| 6
| Epic
| Paladin
| 2
|
|
| Grand Crusader
| 6
| Epic
| Neutral
| 2
|
|
| Kodorider
| 6
| Epic
| Neutral
| 1
|
|
| Master Jouster
| 6
| Rare
| Neutral
| 2
|
|
| Mogor's Champion
| 6
| Rare
| Neutral
| 2
|
|
| Mysterious Challenger
| 6
| Rare
| Paladin
| 1
|
|
| Sideshow Spelleater
| 6
| Epic
| Neutral
| 2
|
|
| Void Crusher
| 6
| Rare
| Warlock
| 2
|
|
| Captured Jormungar
| 7
| Common
| Neutral
| 2
|
|
| Confessor Paletress
| 7
| Legendary
| Priest
| 1
|
|
| Fearsome Doomguard
| 7
| Common
| Warlock
| 2
|
|
| Knight of the Wild
| 7
| Rare
| Druid
| 2
|
|
| North Sea Kraken
| 9
| Common
| Neutral
| 2
| 1
|
| Frost Giant
| 10
| Epic
| Neutral
| 1
|
|