af: /root/apps/altasvc/../altagate//Supra-2019.10.b0/lib/libao.so.4: no version information available (required by af) Total IO : 84 Total Pin : 40/7 Top array is built. Loading architect libraries... ## CPU time: 0:0:0, REAL time: 0:0:0 ## Memory Usage: 0MB (0MB) Warn: Can not find SDC file ./app.sdc, create a empty one. Info: Can not find ASF file ./app.pre.asf, create a empty one. Info: Can not find ASF file ./app.post.asf, create a empty one. Setup done... Next, compile with quartus using one of following 2 approaches: 1) Command line base, run 'quartus_sh -t af_quartus.tcl' 2) GUI base, start quartus GUI, open project app, select Tools->Tcl Scripts..., load af_quartus.tcl and run Then, run 'af_run' to generate app bit-stream files Total 0 fatals, 0 errors, 1 warnings, 2 infos.
svc: af exit code 0 svc: quartus_map --read_settings_files=on, --write_settings_files=off, app, -c, app[0;32mInfo: ******************************************************************* [0m[0;32mInfo: Running Quartus II 32-bit Analysis & Synthesis [0m[0;32m Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version [0m[0;32m Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. [0m[0;32m Info: Your use of Altera Corporation's design tools, logic functions [0m[0;32m Info: and other software and tools, and its AMPP partner logic [0m[0;32m Info: functions, and any output files from any of the foregoing [0m[0;32m Info: (including device programming or simulation files), and any [0m[0;32m Info: associated documentation or information are expressly subject [0m[0;32m Info: to the terms and conditions of the Altera Program License [0m[0;32m Info: Subscription Agreement, Altera MegaCore Function License [0m[0;32m Info: Agreement, or other applicable license agreement, including, [0m[0;32m Info: without limitation, that your use is for the sole purpose of [0m[0;32m Info: programming logic devices manufactured by Altera and sold by [0m[0;32m Info: Altera or its authorized distributors. Please refer to the [0m[0;32m Info: applicable agreement for further details. [0m[0;32m Info: Processing started: Sun Jan 29 07:40:56 2023 [0m[0;32mInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off app -c app [0m[0;32mInfo (125068): Revision "app" was previously opened in Quartus II software version 11.1. Created Quartus II Default Settings File /root/apps/altasvc/temp/app_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 11.1. [0m[0;32mInfo (125069): Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file /root/apps/altasvc/../altagate/Quartus-13.1/linux/assignment_defaults.qdf [0m[0;36mWarning (125096): Overriding device family setting Cyclone IV GX -- part EP4CE75F23C8 belongs to device family Cyclone IV E [0m[0;32m Info (125063): set_global_assignment -name DEVICE EP4CE75F23C8 [0m[0;32mInfo (20029): Only one processor detected - disabling parallel compilation [0m[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file app.v [0m[0;32m Info (12023): Found entity 1: app [0m[0;32m[0m[0;32m[0m[0;36m[0m[0;32m[0m[0;32mInfo (12021): Found 49 design units, including 49 entities, in source file /root/apps/altagate/Supra-2019.10.b0/etc/arch/rodinia/alta_sim.v [0m[0;32m Info (12023): Found entity 1: alta_slice [0m[0;32m Info (12023): Found entity 2: alta_clkenctrl_rst [0m[0;32m Info (12023): Found entity 3: alta_clkenctrl [0m[0;32m Info (12023): Found entity 4: alta_asyncctrl [0m[0;32m Info (12023): Found entity 5: alta_syncctrl [0m[0;32m Info (12023): Found entity 6: alta_io_gclk [0m[0;32m Info (12023): Found entity 7: alta_gclksel [0m[0;32m Info (12023): Found entity 8: alta_gclkgen [0m[0;32m Info (12023): Found entity 9: alta_gclkgen0 [0m[0;32m Info (12023): Found entity 10: alta_gclkgen2 [0m[0;32m Info (12023): Found entity 11: alta_io [0m[0;32m Info (12023): Found entity 12: alta_rio [0m[0;32m Info (12023): Found entity 13: alta_srff [0m[0;32m Info (12023): Found entity 14: alta_dff [0m[0;32m Info (12023): Found entity 15: alta_ufm_gddd [0m[0;32m Info (12023): Found entity 16: alta_dff_stall [0m[0;32m Info (12023): Found entity 17: alta_srlat [0m[0;32m Info (12023): Found entity 18: alta_dio [0m[0;32m Info (12023): Found entity 19: alta_ufms [0m[0;32m Info (12023): Found entity 20: alta_ufms_sim [0m[0;32m Info (12023): Found entity 21: alta_pll [0m[0;32m Info (12023): Found entity 22: alta_pllx [0m[0;32m Info (12023): Found entity 23: pll_clk_trim [0m[0;32m Info (12023): Found entity 24: alta_pllv [0m[0;32m Info (12023): Found entity 25: alta_pllve [0m[0;32m Info (12023): Found entity 26: alta_sram [0m[0;32m Info (12023): Found entity 27: alta_dpram16x4 [0m[0;32m Info (12023): Found entity 28: alta_spram16x4 [0m[0;32m Info (12023): Found entity 29: alta_wram [0m[0;32m Info (12023): Found entity 30: alta_bram_pulse_generator [0m[0;32m Info (12023): Found entity 31: alta_bram [0m[0;32m Info (12023): Found entity 32: alta_ram4k [0m[0;32m Info (12023): Found entity 33: alta_boot [0m[0;32m Info (12023): Found entity 34: alta_osc [0m[0;32m Info (12023): Found entity 35: alta_ufml [0m[0;32m Info (12023): Found entity 36: alta_jtag [0m[0;32m Info (12023): Found entity 37: alta_mult [0m[0;32m Info (12023): Found entity 38: alta_dff_en [0m[0;32m Info (12023): Found entity 39: alta_multm_add [0m[0;32m Info (12023): Found entity 40: alta_multm [0m[0;32m Info (12023): Found entity 41: alta_i2c [0m[0;32m Info (12023): Found entity 42: alta_spi [0m[0;32m Info (12023): Found entity 43: alta_irda [0m[0;32m Info (12023): Found entity 44: alta_bram9k [0m[0;32m Info (12023): Found entity 45: alta_ram9k [0m[0;32m Info (12023): Found entity 46: alta_mcu [0m[0;32m Info (12023): Found entity 47: alta_mcu_m3 [0m[0;32m Info (12023): Found entity 48: alta_remote [0m[0;32m Info (12023): Found entity 49: alta_saradc [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(161): created implicit net for "ena_reg" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(185): created implicit net for "ena_int" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(186): created implicit net for "ena_reg" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(450): created implicit net for "outreg_h" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(451): created implicit net for "outreg_l" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(459): created implicit net for "oe_reg_h" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(460): created implicit net for "oe_reg_l" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(2881): created implicit net for "dffOut" [0m[0;36mWarning (10222): Verilog HDL Parameter Declaration warning at alta_sim.v(2374): Parameter Declaration in module "alta_bram_pulse_generator" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List [0m[0;32mInfo (12127): Elaborating entity "app" for the top level hierarchy [0m[0;36mWarning (10036): Verilog HDL or VHDL warning at cnt4bit.v(18): object "Rx_Data" assigned a value but never read [0m[0;32mInfo (270000): Limiting DSP block usage to 0 DSP block(s) for the partition Top [0m[0;32mInfo (270017): Limiting M4K/M9K RAM block usage to 0 M4K/M9K RAM block(s) for the Top [0m[0;32mInfo (270017): Limiting M4K/M9K RAM block usage to 0 M4K/M9K RAM block(s) for the Top [0m[0;32mInfo (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched [0m[0;32mInfo (286030): Timing-Driven Synthesis is running [0m[0;32mInfo (128000): Starting physical synthesis optimizations for speed [0m[0;32mInfo (332104): Reading SDC File: 'app.sdc' [0m[0;32mInfo (332104): Reading SDC File: 'app_derate.sdc' [0m[0;36mWarning (332190): Using the -early option with a derate factor of 2.0, i.e., greater than 1.0, causes less conservative delays which might lead to optimistic results from timing analysis. [0m[0;32mInfo (332144): No user constrained base clocks found in the design [0m[0;32mInfo (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" [0m[0;32mInfo (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. [0m[0;32mInfo (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements [0m[0;32m Info (332127): Assuming a default timing requirement [0m[0;32mInfo (332111): Found 1 clocks [0m[0;32m Info (332111): Period Clock Name [0m[0;32m Info (332111): ======== ============ [0m[0;32m Info (332111): 1.000 clk [0m[0;32mInfo (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division [0m[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps [0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01 [0m[0;32mInfo (144001): Generated suppressed messages file /root/apps/altasvc/temp/quartus_logs/app.map.smsg [0m[0;32mInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst" [0m[0;32m Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL [0m[0;36mWarning (21074): Design contains 2 input pin(s) that do not drive logic [0m[0;36m Warning (15610): No output dependent on input pin "MOSI" [0m[0;36m Warning (15610): No output dependent on input pin "SCK" [0m[0;32mInfo (21057): Implemented 28 device resources after synthesis - the final resource count might be different [0m[0;32m Info (21058): Implemented 4 input pins [0m[0;32m Info (21059): Implemented 0 output pins [0m[0;32m Info (21060): Implemented 1 bidirectional pins [0m[0;32m Info (21061): Implemented 23 logic cells [0m[0;32mInfo: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 15 warnings [0m[0;32m Info: Peak virtual memory: 438 megabytes [0m[0;32m Info: Processing ended: Sun Jan 29 07:41:00 2023 [0m[0;32m Info: Elapsed time: 00:00:04 [0m[0;32m Info: Total CPU time (on all processors): 00:00:04 [0m
svc: quartus_map exit code 0 svc: quartus_map --read_settings_files=on, --write_settings_files=off, app, -c, app[0;32mInfo: ******************************************************************* [0m[0;32mInfo: Running Quartus II 32-bit Analysis & Synthesis [0m[0;32m Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version [0m[0;32m Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. [0m[0;32m Info: Your use of Altera Corporation's design tools, logic functions [0m[0;32m Info: and other software and tools, and its AMPP partner logic [0m[0;32m Info: functions, and any output files from any of the foregoing [0m[0;32m Info: (including device programming or simulation files), and any [0m[0;32m Info: associated documentation or information are expressly subject [0m[0;32m Info: to the terms and conditions of the Altera Program License [0m[0;32m Info: Subscription Agreement, Altera MegaCore Function License [0m[0;32m Info: Agreement, or other applicable license agreement, including, [0m[0;32m Info: without limitation, that your use is for the sole purpose of [0m[0;32m Info: programming logic devices manufactured by Altera and sold by [0m[0;32m Info: Altera or its authorized distributors. Please refer to the [0m[0;32m Info: applicable agreement for further details. [0m[0;32m Info: Processing started: Sun Jan 29 07:41:05 2023 [0m[0;32mInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off app -c app [0m[0;32mInfo (125069): Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file /root/apps/altasvc/../altagate/Quartus-13.1/linux/assignment_defaults.qdf [0m[0;36mWarning (125096): Overriding device family setting Cyclone IV GX -- part EP4CE75F23C8 belongs to device family Cyclone IV E [0m[0;32m Info (125063): set_global_assignment -name DEVICE EP4CE75F23C8 [0m[0;32mInfo (20029): Only one processor detected - disabling parallel compilation [0m[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file app.v [0m[0;32m Info (12023): Found entity 1: app [0m[0;32m[0m[0;32m[0m[0;36m[0m[0;32m[0m[0;32mInfo (12021): Found 49 design units, including 49 entities, in source file /root/apps/altagate/Supra-2019.10.b0/etc/arch/rodinia/alta_sim.v [0m[0;32m Info (12023): Found entity 1: alta_slice [0m[0;32m Info (12023): Found entity 2: alta_clkenctrl_rst [0m[0;32m Info (12023): Found entity 3: alta_clkenctrl [0m[0;32m Info (12023): Found entity 4: alta_asyncctrl [0m[0;32m Info (12023): Found entity 5: alta_syncctrl [0m[0;32m Info (12023): Found entity 6: alta_io_gclk [0m[0;32m Info (12023): Found entity 7: alta_gclksel [0m[0;32m Info (12023): Found entity 8: alta_gclkgen [0m[0;32m Info (12023): Found entity 9: alta_gclkgen0 [0m[0;32m Info (12023): Found entity 10: alta_gclkgen2 [0m[0;32m Info (12023): Found entity 11: alta_io [0m[0;32m Info (12023): Found entity 12: alta_rio [0m[0;32m Info (12023): Found entity 13: alta_srff [0m[0;32m Info (12023): Found entity 14: alta_dff [0m[0;32m Info (12023): Found entity 15: alta_ufm_gddd [0m[0;32m Info (12023): Found entity 16: alta_dff_stall [0m[0;32m Info (12023): Found entity 17: alta_srlat [0m[0;32m Info (12023): Found entity 18: alta_dio [0m[0;32m Info (12023): Found entity 19: alta_ufms [0m[0;32m Info (12023): Found entity 20: alta_ufms_sim [0m[0;32m Info (12023): Found entity 21: alta_pll [0m[0;32m Info (12023): Found entity 22: alta_pllx [0m[0;32m Info (12023): Found entity 23: pll_clk_trim [0m[0;32m Info (12023): Found entity 24: alta_pllv [0m[0;32m Info (12023): Found entity 25: alta_pllve [0m[0;32m Info (12023): Found entity 26: alta_sram [0m[0;32m Info (12023): Found entity 27: alta_dpram16x4 [0m[0;32m Info (12023): Found entity 28: alta_spram16x4 [0m[0;32m Info (12023): Found entity 29: alta_wram [0m[0;32m Info (12023): Found entity 30: alta_bram_pulse_generator [0m[0;32m Info (12023): Found entity 31: alta_bram [0m[0;32m Info (12023): Found entity 32: alta_ram4k [0m[0;32m Info (12023): Found entity 33: alta_boot [0m[0;32m Info (12023): Found entity 34: alta_osc [0m[0;32m Info (12023): Found entity 35: alta_ufml [0m[0;32m Info (12023): Found entity 36: alta_jtag [0m[0;32m Info (12023): Found entity 37: alta_mult [0m[0;32m Info (12023): Found entity 38: alta_dff_en [0m[0;32m Info (12023): Found entity 39: alta_multm_add [0m[0;32m Info (12023): Found entity 40: alta_multm [0m[0;32m Info (12023): Found entity 41: alta_i2c [0m[0;32m Info (12023): Found entity 42: alta_spi [0m[0;32m Info (12023): Found entity 43: alta_irda [0m[0;32m Info (12023): Found entity 44: alta_bram9k [0m[0;32m Info (12023): Found entity 45: alta_ram9k [0m[0;32m Info (12023): Found entity 46: alta_mcu [0m[0;32m Info (12023): Found entity 47: alta_mcu_m3 [0m[0;32m Info (12023): Found entity 48: alta_remote [0m[0;32m Info (12023): Found entity 49: alta_saradc [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(161): created implicit net for "ena_reg" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(185): created implicit net for "ena_int" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(186): created implicit net for "ena_reg" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(450): created implicit net for "outreg_h" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(451): created implicit net for "outreg_l" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(459): created implicit net for "oe_reg_h" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(460): created implicit net for "oe_reg_l" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(2881): created implicit net for "dffOut" [0m[0;36mWarning (10222): Verilog HDL Parameter Declaration warning at alta_sim.v(2374): Parameter Declaration in module "alta_bram_pulse_generator" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List [0m[0;32mInfo (12127): Elaborating entity "app" for the top level hierarchy [0m[0;36mWarning (10036): Verilog HDL or VHDL warning at cnt4bit.v(18): object "Rx_Data" assigned a value but never read [0m[0;32mInfo (270000): Limiting DSP block usage to 0 DSP block(s) for the partition Top [0m[0;32mInfo (270017): Limiting M4K/M9K RAM block usage to 0 M4K/M9K RAM block(s) for the Top [0m[0;32mInfo (270017): Limiting M4K/M9K RAM block usage to 0 M4K/M9K RAM block(s) for the Top [0m[0;32mInfo (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched [0m[0;32mInfo (286030): Timing-Driven Synthesis is running [0m[0;32mInfo (128000): Starting physical synthesis optimizations for speed [0m[0;32mInfo (332104): Reading SDC File: 'app.sdc' [0m[0;32mInfo (332104): Reading SDC File: 'app_derate.sdc' [0m[0;36mWarning (332190): Using the -early option with a derate factor of 2.0, i.e., greater than 1.0, causes less conservative delays which might lead to optimistic results from timing analysis. [0m[0;32mInfo (332144): No user constrained base clocks found in the design [0m[0;32mInfo (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" [0m[0;32mInfo (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. [0m[0;32mInfo (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements [0m[0;32m Info (332127): Assuming a default timing requirement [0m[0;32mInfo (332111): Found 1 clocks [0m[0;32m Info (332111): Period Clock Name [0m[0;32m Info (332111): ======== ============ [0m[0;32m Info (332111): 1.000 clk [0m[0;32mInfo (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division [0m[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps [0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01 [0m[0;32mInfo (144001): Generated suppressed messages file /root/apps/altasvc/temp/quartus_logs/app.map.smsg [0m[0;32mInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst" [0m[0;32m Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL [0m[0;36mWarning (21074): Design contains 2 input pin(s) that do not drive logic [0m[0;36m Warning (15610): No output dependent on input pin "MOSI" [0m[0;36m Warning (15610): No output dependent on input pin "SCK" [0m[0;32mInfo (21057): Implemented 28 device resources after synthesis - the final resource count might be different [0m[0;32m Info (21058): Implemented 4 input pins [0m[0;32m Info (21059): Implemented 0 output pins [0m[0;32m Info (21060): Implemented 1 bidirectional pins [0m[0;32m Info (21061): Implemented 23 logic cells [0m[0;32mInfo: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 15 warnings [0m[0;32m Info: Peak virtual memory: 443 megabytes [0m[0;32m Info: Processing ended: Sun Jan 29 07:41:09 2023 [0m[0;32m Info: Elapsed time: 00:00:04 [0m[0;32m Info: Total CPU time (on all processors): 00:00:04 [0m
svc: quartus_map exit code 0 svc: quartus_sh -t, af_quartus.tcl[0;32mInfo: ******************************************************************* [0m[0;32mInfo: Running Quartus II 32-bit Shell [0m[0;32m Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version [0m[0;32m Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. [0m[0;32m Info: Your use of Altera Corporation's design tools, logic functions [0m[0;32m Info: and other software and tools, and its AMPP partner logic [0m[0;32m Info: functions, and any output files from any of the foregoing [0m[0;32m Info: (including device programming or simulation files), and any [0m[0;32m Info: associated documentation or information are expressly subject [0m[0;32m Info: to the terms and conditions of the Altera Program License [0m[0;32m Info: Subscription Agreement, Altera MegaCore Function License [0m[0;32m Info: Agreement, or other applicable license agreement, including, [0m[0;32m Info: without limitation, that your use is for the sole purpose of [0m[0;32m Info: programming logic devices manufactured by Altera and sold by [0m[0;32m Info: Altera or its authorized distributors. Please refer to the [0m[0;32m Info: applicable agreement for further details. [0m[0;32m Info: Processing started: Sun Jan 29 07:41:10 2023 [0m[0;32mInfo: Command: quartus_sh -t af_quartus.tcl [0;32mInfo: ******************************************************************* [0m[0;32mInfo: Running Quartus II 32-bit Shell [0m[0;32m Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version [0m[0;32m Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. [0m[0;32m Info: Your use of Altera Corporation's design tools, logic functions [0m[0;32m Info: and other software and tools, and its AMPP partner logic [0m[0;32m Info: functions, and any output files from any of the foregoing [0m[0;32m Info: (including device programming or simulation files), and any [0m[0;32m Info: associated documentation or information are expressly subject [0m[0;32m Info: to the terms and conditions of the Altera Program License [0m[0;32m Info: Subscription Agreement, Altera MegaCore Function License [0m[0;32m Info: Agreement, or other applicable license agreement, including, [0m[0;32m Info: without limitation, that your use is for the sole purpose of [0m[0;32m Info: programming logic devices manufactured by Altera and sold by [0m[0;32m Info: Altera or its authorized distributors. Please refer to the [0m[0;32m Info: applicable agreement for further details. [0m[0;32m Info: Processing started: Sun Jan 29 07:41:12 2023 [0m[0;32mInfo: Command: quartus_sh -t af_ip.tcl [0m[0;32mInfo (125069): Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file /root/apps/altagate/Quartus-13.1/linux/assignment_defaults.qdf [0m[0;36mWarning (125096): Overriding device family setting Cyclone IV GX -- part EP4CE75F23C8 belongs to device family Cyclone IV E [0m[0;32m Info (125063): set_global_assignment -name DEVICE EP4CE75F23C8 [0m[0;32mInfo: ******************************************************************* [0m[0;32mInfo: Running Quartus II 32-bit Analysis & Synthesis [0m[0;32m Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version [0m[0;32m Info: Processing started: Sun Jan 29 07:41:17 2023 [0m[0;32mInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off app -c app [0m[0;36mWarning (125096): Overriding device family setting Cyclone IV -- part EP4CE75F23C8 belongs to device family Cyclone IV E [0m[0;32m Info (125063): set_global_assignment -name FAMILY "Cyclone IV" [0m[0;32mInfo (20029): Only one processor detected - disabling parallel compilation [0m[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file app.v [0m[0;32m Info (12023): Found entity 1: app [0m[0;32m[0m[0;32m[0m[0;36m[0m[0;32m[0m[0;32mInfo (12021): Found 49 design units, including 49 entities, in source file /root/apps/altagate/Supra-2019.10.b0/etc/arch/rodinia/alta_sim.v [0m[0;32m Info (12023): Found entity 1: alta_slice [0m[0;32m Info (12023): Found entity 2: alta_clkenctrl_rst [0m[0;32m Info (12023): Found entity 3: alta_clkenctrl [0m[0;32m Info (12023): Found entity 4: alta_asyncctrl [0m[0;32m Info (12023): Found entity 5: alta_syncctrl [0m[0;32m Info (12023): Found entity 6: alta_io_gclk [0m[0;32m Info (12023): Found entity 7: alta_gclksel [0m[0;32m Info (12023): Found entity 8: alta_gclkgen [0m[0;32m Info (12023): Found entity 9: alta_gclkgen0 [0m[0;32m Info (12023): Found entity 10: alta_gclkgen2 [0m[0;32m Info (12023): Found entity 11: alta_io [0m[0;32m Info (12023): Found entity 12: alta_rio [0m[0;32m Info (12023): Found entity 13: alta_srff [0m[0;32m Info (12023): Found entity 14: alta_dff [0m[0;32m Info (12023): Found entity 15: alta_ufm_gddd [0m[0;32m Info (12023): Found entity 16: alta_dff_stall [0m[0;32m Info (12023): Found entity 17: alta_srlat [0m[0;32m Info (12023): Found entity 18: alta_dio [0m[0;32m Info (12023): Found entity 19: alta_ufms [0m[0;32m Info (12023): Found entity 20: alta_ufms_sim [0m[0;32m Info (12023): Found entity 21: alta_pll [0m[0;32m Info (12023): Found entity 22: alta_pllx [0m[0;32m Info (12023): Found entity 23: pll_clk_trim [0m[0;32m Info (12023): Found entity 24: alta_pllv [0m[0;32m Info (12023): Found entity 25: alta_pllve [0m[0;32m Info (12023): Found entity 26: alta_sram [0m[0;32m Info (12023): Found entity 27: alta_dpram16x4 [0m[0;32m Info (12023): Found entity 28: alta_spram16x4 [0m[0;32m Info (12023): Found entity 29: alta_wram [0m[0;32m Info (12023): Found entity 30: alta_bram_pulse_generator [0m[0;32m Info (12023): Found entity 31: alta_bram [0m[0;32m Info (12023): Found entity 32: alta_ram4k [0m[0;32m Info (12023): Found entity 33: alta_boot [0m[0;32m Info (12023): Found entity 34: alta_osc [0m[0;32m Info (12023): Found entity 35: alta_ufml [0m[0;32m Info (12023): Found entity 36: alta_jtag [0m[0;32m Info (12023): Found entity 37: alta_mult [0m[0;32m Info (12023): Found entity 38: alta_dff_en [0m[0;32m Info (12023): Found entity 39: alta_multm_add [0m[0;32m Info (12023): Found entity 40: alta_multm [0m[0;32m Info (12023): Found entity 41: alta_i2c [0m[0;32m Info (12023): Found entity 42: alta_spi [0m[0;32m Info (12023): Found entity 43: alta_irda [0m[0;32m Info (12023): Found entity 44: alta_bram9k [0m[0;32m Info (12023): Found entity 45: alta_ram9k [0m[0;32m Info (12023): Found entity 46: alta_mcu [0m[0;32m Info (12023): Found entity 47: alta_mcu_m3 [0m[0;32m Info (12023): Found entity 48: alta_remote [0m[0;32m Info (12023): Found entity 49: alta_saradc [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(161): created implicit net for "ena_reg" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(185): created implicit net for "ena_int" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(186): created implicit net for "ena_reg" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(450): created implicit net for "outreg_h" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(451): created implicit net for "outreg_l" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(459): created implicit net for "oe_reg_h" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(460): created implicit net for "oe_reg_l" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(2881): created implicit net for "dffOut" [0m[0;36mWarning (10222): Verilog HDL Parameter Declaration warning at alta_sim.v(2374): Parameter Declaration in module "alta_bram_pulse_generator" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List [0m[0;32mInfo (12127): Elaborating entity "app" for the top level hierarchy [0m[0;36mWarning (10036): Verilog HDL or VHDL warning at cnt4bit.v(18): object "Rx_Data" assigned a value but never read [0m[0;32mInfo (270000): Limiting DSP block usage to 0 DSP block(s) for the partition Top [0m[0;32mInfo (270017): Limiting M4K/M9K RAM block usage to 0 M4K/M9K RAM block(s) for the Top [0m[0;32mInfo (270017): Limiting M4K/M9K RAM block usage to 0 M4K/M9K RAM block(s) for the Top [0m[0;32mInfo (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched [0m[0;32mInfo (286030): Timing-Driven Synthesis is running [0m[0;32mInfo (128000): Starting physical synthesis optimizations for speed [0m[0;32mInfo (332104): Reading SDC File: 'app.sdc' [0m[0;32mInfo (332104): Reading SDC File: 'app_derate.sdc' [0m[0;36mWarning (332190): Using the -early option with a derate factor of 2.0, i.e., greater than 1.0, causes less conservative delays which might lead to optimistic results from timing analysis. [0m[0;32mInfo (332144): No user constrained base clocks found in the design [0m[0;32mInfo (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" [0m[0;32mInfo (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. [0m[0;32mInfo (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements [0m[0;32m Info (332127): Assuming a default timing requirement [0m[0;32mInfo (332111): Found 1 clocks [0m[0;32m Info (332111): Period Clock Name [0m[0;32m Info (332111): ======== ============ [0m[0;32m Info (332111): 1.000 clk [0m[0;32mInfo (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division [0m[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps [0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01 [0m[0;32mInfo (144001): Generated suppressed messages file /root/apps/altasvc/temp/quartus_logs/app.map.smsg [0m[0;32mInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst" [0m[0;32m Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL [0m[0;36mWarning (21074): Design contains 2 input pin(s) that do not drive logic [0m[0;36m Warning (15610): No output dependent on input pin "MOSI" [0m[0;36m Warning (15610): No output dependent on input pin "SCK" [0m[0;32mInfo (21057): Implemented 28 device resources after synthesis - the final resource count might be different [0m[0;32m Info (21058): Implemented 4 input pins [0m[0;32m Info (21059): Implemented 0 output pins [0m[0;32m Info (21060): Implemented 1 bidirectional pins [0m[0;32m Info (21061): Implemented 23 logic cells [0m[0;32mInfo: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 15 warnings [0m[0;32m Info: Peak virtual memory: 438 megabytes [0m[0;32m Info: Processing ended: Sun Jan 29 07:41:21 2023 [0m[0;32m Info: Elapsed time: 00:00:04 [0m[0;32m Info: Total CPU time (on all processors): 00:00:04 [0m[0m[0;36mWarning (125096): Overriding device family setting Cyclone IV -- part EP4CE75F23C8 belongs to device family Cyclone IV E [0m[0;32m Info (125063): set_global_assignment -name FAMILY "Cyclone IV" [0m[0;32mInfo: ******************************************************************* [0m[0;32mInfo: Running Quartus II 32-bit Analysis & Synthesis [0m[0;32m Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version [0m[0;32m Info: Processing started: Sun Jan 29 07:41:27 2023 [0m[0;32mInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off app -c app [0m[0;36mWarning (125096): Overriding device family setting Cyclone IV -- part EP4CE75F23C8 belongs to device family Cyclone IV E [0m[0;32m Info (125063): set_global_assignment -name FAMILY "Cyclone IV" [0m[0;32mInfo (20029): Only one processor detected - disabling parallel compilation [0m[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file app.v [0m[0;32m Info (12023): Found entity 1: app [0m[0;32m[0m[0;32m[0m[0;36m[0m[0;32m[0m[0;32mInfo (12021): Found 49 design units, including 49 entities, in source file /root/apps/altagate/Supra-2019.10.b0/etc/arch/rodinia/alta_sim.v [0m[0;32m Info (12023): Found entity 1: alta_slice [0m[0;32m Info (12023): Found entity 2: alta_clkenctrl_rst [0m[0;32m Info (12023): Found entity 3: alta_clkenctrl [0m[0;32m Info (12023): Found entity 4: alta_asyncctrl [0m[0;32m Info (12023): Found entity 5: alta_syncctrl [0m[0;32m Info (12023): Found entity 6: alta_io_gclk [0m[0;32m Info (12023): Found entity 7: alta_gclksel [0m[0;32m Info (12023): Found entity 8: alta_gclkgen [0m[0;32m Info (12023): Found entity 9: alta_gclkgen0 [0m[0;32m Info (12023): Found entity 10: alta_gclkgen2 [0m[0;32m Info (12023): Found entity 11: alta_io [0m[0;32m Info (12023): Found entity 12: alta_rio [0m[0;32m Info (12023): Found entity 13: alta_srff [0m[0;32m Info (12023): Found entity 14: alta_dff [0m[0;32m Info (12023): Found entity 15: alta_ufm_gddd [0m[0;32m Info (12023): Found entity 16: alta_dff_stall [0m[0;32m Info (12023): Found entity 17: alta_srlat [0m[0;32m Info (12023): Found entity 18: alta_dio [0m[0;32m Info (12023): Found entity 19: alta_ufms [0m[0;32m Info (12023): Found entity 20: alta_ufms_sim [0m[0;32m Info (12023): Found entity 21: alta_pll [0m[0;32m Info (12023): Found entity 22: alta_pllx [0m[0;32m Info (12023): Found entity 23: pll_clk_trim [0m[0;32m Info (12023): Found entity 24: alta_pllv [0m[0;32m Info (12023): Found entity 25: alta_pllve [0m[0;32m Info (12023): Found entity 26: alta_sram [0m[0;32m Info (12023): Found entity 27: alta_dpram16x4 [0m[0;32m Info (12023): Found entity 28: alta_spram16x4 [0m[0;32m Info (12023): Found entity 29: alta_wram [0m[0;32m Info (12023): Found entity 30: alta_bram_pulse_generator [0m[0;32m Info (12023): Found entity 31: alta_bram [0m[0;32m Info (12023): Found entity 32: alta_ram4k [0m[0;32m Info (12023): Found entity 33: alta_boot [0m[0;32m Info (12023): Found entity 34: alta_osc [0m[0;32m Info (12023): Found entity 35: alta_ufml [0m[0;32m Info (12023): Found entity 36: alta_jtag [0m[0;32m Info (12023): Found entity 37: alta_mult [0m[0;32m Info (12023): Found entity 38: alta_dff_en [0m[0;32m Info (12023): Found entity 39: alta_multm_add [0m[0;32m Info (12023): Found entity 40: alta_multm [0m[0;32m Info (12023): Found entity 41: alta_i2c [0m[0;32m Info (12023): Found entity 42: alta_spi [0m[0;32m Info (12023): Found entity 43: alta_irda [0m[0;32m Info (12023): Found entity 44: alta_bram9k [0m[0;32m Info (12023): Found entity 45: alta_ram9k [0m[0;32m Info (12023): Found entity 46: alta_mcu [0m[0;32m Info (12023): Found entity 47: alta_mcu_m3 [0m[0;32m Info (12023): Found entity 48: alta_remote [0m[0;32m Info (12023): Found entity 49: alta_saradc [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(161): created implicit net for "ena_reg" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(185): created implicit net for "ena_int" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(186): created implicit net for "ena_reg" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(450): created implicit net for "outreg_h" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(451): created implicit net for "outreg_l" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(459): created implicit net for "oe_reg_h" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(460): created implicit net for "oe_reg_l" [0m[0;36mWarning (10236): Verilog HDL Implicit Net warning at alta_sim.v(2881): created implicit net for "dffOut" [0m[0;36mWarning (10222): Verilog HDL Parameter Declaration warning at alta_sim.v(2374): Parameter Declaration in module "alta_bram_pulse_generator" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List [0m[0;32mInfo (12127): Elaborating entity "app" for the top level hierarchy [0m[0;36mWarning (10036): Verilog HDL or VHDL warning at cnt4bit.v(18): object "Rx_Data" assigned a value but never read [0m[0;32mInfo (270000): Limiting DSP block usage to 0 DSP block(s) for the partition Top [0m[0;32mInfo (270017): Limiting M4K/M9K RAM block usage to 0 M4K/M9K RAM block(s) for the Top [0m[0;32mInfo (270017): Limiting M4K/M9K RAM block usage to 0 M4K/M9K RAM block(s) for the Top [0m[0;32mInfo (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched [0m[0;32mInfo (286030): Timing-Driven Synthesis is running [0m[0;32mInfo (128000): Starting physical synthesis optimizations for speed [0m[0;32mInfo (332104): Reading SDC File: 'app.sdc' [0m[0;32mInfo (332104): Reading SDC File: 'app_derate.sdc' [0m[0;36mWarning (332190): Using the -early option with a derate factor of 2.0, i.e., greater than 1.0, causes less conservative delays which might lead to optimistic results from timing analysis. [0m[0;32mInfo (332144): No user constrained base clocks found in the design [0m[0;32mInfo (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" [0m[0;32mInfo (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. [0m[0;32mInfo (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements [0m[0;32m Info (332127): Assuming a default timing requirement [0m[0;32mInfo (332111): Found 1 clocks [0m[0;32m Info (332111): Period Clock Name [0m[0;32m Info (332111): ======== ============ [0m[0;32m Info (332111): 1.000 clk [0m[0;32mInfo (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division [0m[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps [0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01 [0m[0;32mInfo (144001): Generated suppressed messages file /root/apps/altasvc/temp/quartus_logs/app.map.smsg [0m[0;32mInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst" [0m[0;32m Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL [0m[0;36mWarning (21074): Design contains 2 input pin(s) that do not drive logic [0m[0;36m Warning (15610): No output dependent on input pin "MOSI" [0m[0;36m Warning (15610): No output dependent on input pin "SCK" [0m[0;32mInfo (21057): Implemented 28 device resources after synthesis - the final resource count might be different [0m[0;32m Info (21058): Implemented 4 input pins [0m[0;32m Info (21059): Implemented 0 output pins [0m[0;32m Info (21060): Implemented 1 bidirectional pins [0m[0;32m Info (21061): Implemented 23 logic cells [0m[0;32mInfo: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 15 warnings [0m[0;32m Info: Peak virtual memory: 438 megabytes [0m[0;32m Info: Processing ended: Sun Jan 29 07:41:31 2023 [0m[0;32m Info: Elapsed time: 00:00:04 [0m[0;32m Info: Total CPU time (on all processors): 00:00:04 [0m[0;36mWarning (125096): Overriding device family setting Cyclone IV -- part EP4CE75F23C8 belongs to device family Cyclone IV E [0m[0;32m Info (125063): set_global_assignment -name FAMILY "Cyclone IV" [0m[0;32mInfo: ******************************************************************* [0m[0;32mInfo: Running Quartus II 32-bit Fitter [0m[0;32m Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version [0m[0;32m Info: Processing started: Sun Jan 29 07:41:34 2023 [0m[0;32mInfo: Command: quartus_fit --read_settings_files=off --write_settings_files=off app -c app --check_ios [0m[0;32mInfo: qfit2_default_script.tcl version: #1 [0m[0;32mInfo: Project = app [0m[0;32mInfo: Revision = app [0m[0;32mInfo (20029): Only one processor detected - disabling parallel compilation [0m[0;32mInfo (119006): Selected device EP4CE75F23C8 for design "app" [0m[0;32mInfo (21077): Low junction temperature is 0 degrees C [0m[0;32mInfo (21077): High junction temperature is 85 degrees C [0m[0;36mWarning (171002): Current optimization assignments may cause the Fitter to introduce hold timing violations on connections clocked by global signals [0m[0;32mInfo (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices [0m[0;32m Info (176445): Device EP4CE15F23C8 is compatible [0m[0;32m Info (176445): Device EP4CE40F23C8 is compatible [0m[0;32m Info (176445): Device EP4CE30F23C8 is compatible [0m[0;32m Info (176445): Device EP4CE55F23C8 is compatible [0m[0;32m Info (176445): Device EP4CE115F23C8 is compatible [0m[0;32mInfo (169124): Fitter converted 5 user pins into dedicated programming pins [0m[0;32m Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 [0m[0;32m Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 [0m[0;32m Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2 [0m[0;32m Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1 [0m[0;32m Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22 [0m[0;36mWarning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details [0m[0;36mCritical Warning (169085): No exact pin location assignment(s) for 5 pins of 5 total pins [0m[0;32m Info (169086): Pin MOSI not assigned to an exact location on the device [0m[0;32m Info (169086): Pin SCK not assigned to an exact location on the device [0m[0;32m Info (169086): Pin MISO not assigned to an exact location on the device [0m[0;32m Info (169086): Pin clk not assigned to an exact location on the device [0m[0;32m Info (169086): Pin SSEL not assigned to an exact location on the device [0m[0;32mInfo (176353): Automatically promoted node clk~input (placed in PIN G1 (CLK1, DIFFCLK_0n)) [0m[0;32m Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 [0m[0;32mInfo (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement [0m[0;32m Info (176211): Number of I/O pins in group: 4 (unused VREF, 3.3V VCCIO, 3 input, 0 output, 1 bidirectional) [0m[0;32m Info (176212): I/O standards used: 3.3-V LVTTL. [0m[0;32mInfo (176215): I/O bank details before I/O pin placement [0m[0;32m Info (176214): Statistics of I/O banks [0m[0;32m Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 26 pins available [0m[0;32m Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 37 pins available [0m[0;32m Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available [0m[0;32m Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available [0m[0;32m Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 38 pins available [0m[0;32m Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available [0m[0;32m Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 38 pins available [0m[0;32m Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 38 pins available [0m[0;32mInfo (171121): Fitter preparation operations ending: elapsed time is 00:00:04 [0m[0;36mWarning (169177): 5 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. [0m[0;32m Info (169178): Pin MOSI uses I/O standard 3.3-V LVTTL at G4 [0m[0;32m Info (169178): Pin SCK uses I/O standard 3.3-V LVTTL at G3 [0m[0;32m Info (169178): Pin MISO uses I/O standard 3.3-V LVTTL at B1 [0m[0;32m Info (169178): Pin clk uses I/O standard 3.3-V LVTTL at G1 [0m[0;32m Info (169178): Pin SSEL uses I/O standard 3.3-V LVTTL at B2 [0m[0;32mInfo (11763): Results from the I/O assignment analysis compilation cannot be preserved because I/O assignment analysis was run with Incremental Compilation enabled [0m[0;32mInfo: Quartus II 32-bit I/O Assignment Analysis was successful. 0 errors, 5 warnings [0m[0;32m Info: Peak virtual memory: 419 megabytes [0m[0;32m Info: Processing ended: Sun Jan 29 07:41:40 2023 [0m[0;32m Info: Elapsed time: 00:00:06 [0m[0;32m Info: Total CPU time (on all processors): 00:00:06 [0m[0;36mWarning (125096): Overriding device family setting Cyclone IV -- part EP4CE75F23C8 belongs to device family Cyclone IV E [0m[0;32m Info (125063): set_global_assignment -name FAMILY "Cyclone IV" [0m[0;32mInfo: ******************************************************************* [0m[0;32mInfo: Running Quartus II 32-bit Fitter [0m[0;32m Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version [0m[0;32m Info: Processing started: Sun Jan 29 07:41:43 2023 [0m[0;32mInfo: Command: quartus_fit --read_settings_files=off --write_settings_files=off app -c app [0m[0;32mInfo: qfit2_default_script.tcl version: #1 [0m[0;32mInfo: Project = app [0m[0;32mInfo: Revision = app [0m[0;32mInfo (20029): Only one processor detected - disabling parallel compilation [0m[0;32mInfo (119006): Selected device EP4CE75F23C8 for design "app" [0m[0;32mInfo (21077): Low junction temperature is 0 degrees C [0m[0;32mInfo (21077): High junction temperature is 85 degrees C [0m[0;32mInfo (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance [0m[0;36mWarning (171002): Current optimization assignments may cause the Fitter to introduce hold timing violations on connections clocked by global signals [0m[0;32mInfo (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices [0m[0;32m Info (176445): Device EP4CE15F23C8 is compatible [0m[0;32m Info (176445): Device EP4CE40F23C8 is compatible [0m[0;32m Info (176445): Device EP4CE30F23C8 is compatible [0m[0;32m Info (176445): Device EP4CE55F23C8 is compatible [0m[0;32m Info (176445): Device EP4CE115F23C8 is compatible [0m[0;32mInfo (169124): Fitter converted 5 user pins into dedicated programming pins [0m[0;32m Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 [0m[0;32m Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 [0m[0;32m Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2 [0m[0;32m Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1 [0m[0;32m Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22 [0m[0;36mWarning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details [0m[0;36mCritical Warning (169085): No exact pin location assignment(s) for 5 pins of 5 total pins [0m[0;32m Info (169086): Pin MOSI not assigned to an exact location on the device [0m[0;32m Info (169086): Pin SCK not assigned to an exact location on the device [0m[0;32m Info (169086): Pin MISO not assigned to an exact location on the device [0m[0;32m Info (169086): Pin clk not assigned to an exact location on the device [0m[0;32m Info (169086): Pin SSEL not assigned to an exact location on the device [0m[0;32mInfo (332104): Reading SDC File: 'app.sdc' [0m[0;32mInfo (332104): Reading SDC File: 'app_derate.sdc' [0m[0;36mWarning (332190): Using the -early option with a derate factor of 2.0, i.e., greater than 1.0, causes less conservative delays which might lead to optimistic results from timing analysis. [0m[0;32mInfo (332144): No user constrained base clocks found in the design [0m[0;32mInfo (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" [0m[0;32mInfo (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. [0m[0;32mInfo (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements [0m[0;32m Info (332127): Assuming a default timing requirement [0m[0;32mInfo (332111): Found 1 clocks [0m[0;32m Info (332111): Period Clock Name [0m[0;32m Info (332111): ======== ============ [0m[0;32m Info (332111): 1.000 clk [0m[0;32mInfo (176353): Automatically promoted node clk~input (placed in PIN G1 (CLK1, DIFFCLK_0n)) [0m[0;32m Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 [0m[0;32mInfo (176233): Starting register packing [0m[0;32m[0m[0;32m[0m[0;32m[0m[0;32m[0m[0;32m[0m[0;32m[0m[0;32m[0m[0;32m[0m[0;32mInfo (176235): Finished register packing [0m[0;32m Extra Info (176219): No registers were packed into other blocks [0m[0;32mInfo (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement [0m[0;32m Info (176211): Number of I/O pins in group: 4 (unused VREF, 3.3V VCCIO, 3 input, 0 output, 1 bidirectional) [0m[0;32m Info (176212): I/O standards used: 3.3-V LVTTL. [0m[0;32mInfo (176215): I/O bank details before I/O pin placement [0m[0;32m Info (176214): Statistics of I/O banks [0m[0;32m Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 26 pins available [0m[0;32m Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 37 pins available [0m[0;32m Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available [0m[0;32m Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available [0m[0;32m Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 38 pins available [0m[0;32m Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available [0m[0;32m Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 38 pins available [0m[0;32m Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 38 pins available [0m[0;32mInfo (128000): Starting physical synthesis optimizations for speed [0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01 [0m[0;32mInfo (171121): Fitter preparation operations ending: elapsed time is 00:00:04 [0m[0;32mInfo (170189): Fitter placement preparation operations beginning [0m[0;32mInfo (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 [0m[0;32mInfo (170191): Fitter placement operations beginning [0m[0;32mInfo (170137): Fitter placement was successful [0m[0;32mInfo (170192): Fitter placement operations ending: elapsed time is 00:00:05 [0m[0;32mInfo (128000): Starting physical synthesis optimizations for speed [0m[0;32mInfo (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division [0m[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps [0m[0;32mInfo (128002): Starting physical synthesis algorithm logic replication [0m[0;32mInfo (128003): Physical synthesis algorithm logic replication complete: estimated slack improvement of 0 ps [0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01 [0m[0;32mInfo (170193): Fitter routing operations beginning [0m[0;32mInfo (170195): Router estimated average interconnect usage is 0% of the available device resources [0m[0;32m Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11 [0m[0;32mInfo (170194): Fitter routing operations ending: elapsed time is 00:00:04 [0m[0;32mInfo (11888): Total time spent on timing analysis during the Fitter is 0.40 seconds. [0m[0;32mInfo (334003): Started post-fitting delay annotation [0m[0;32mInfo (334004): Delay annotation completed successfully [0m[0;32mInfo (334003): Started post-fitting delay annotation [0m[0;32mInfo (334004): Delay annotation completed successfully [0m[0;32mInfo (11218): Fitter post-fit operations ending: elapsed time is 00:00:02 [0m[0;36mWarning (169177): 5 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. [0m[0;32m Info (169178): Pin MOSI uses I/O standard 3.3-V LVTTL at U16 [0m[0;32m Info (169178): Pin SCK uses I/O standard 3.3-V LVTTL at B16 [0m[0;32m Info (169178): Pin MISO uses I/O standard 3.3-V LVTTL at W8 [0m[0;32m Info (169178): Pin clk uses I/O standard 3.3-V LVTTL at G1 [0m[0;32m Info (169178): Pin SSEL uses I/O standard 3.3-V LVTTL at AB6 [0m[0;32mInfo (144001): Generated suppressed messages file /root/apps/altasvc/temp/quartus_logs/app.fit.smsg [0m[0;32mInfo: Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings [0m[0;32m Info: Peak virtual memory: 665 megabytes [0m[0;32m Info: Processing ended: Sun Jan 29 07:42:13 2023 [0m[0;32m Info: Elapsed time: 00:00:30 [0m[0;32m Info: Total CPU time (on all processors): 00:00:30 [0m[0;32mInfo (293026): Skipped module Assembler due to the assignment FLOW_DISABLE_ASSEMBLER [0m[0;32mInfo (293026): Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER [0m[0;36mWarning (125096): Overriding device family setting Cyclone IV -- part EP4CE75F23C8 belongs to device family Cyclone IV E [0m[0;32m Info (125063): set_global_assignment -name FAMILY "Cyclone IV" [0m[0;32mInfo: ******************************************************************* [0m[0;32mInfo: Running Quartus II 32-bit TimeQuest Timing Analyzer [0m[0;32m Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version [0m[0;32m Info: Processing started: Sun Jan 29 07:42:17 2023 [0m[0;32mInfo: Command: quartus_sta app -c app [0m[0;32mInfo: qsta_default_script.tcl version: #1 [0m[0;32mInfo (20029): Only one processor detected - disabling parallel compilation [0m[0;32mInfo (21077): Low junction temperature is 0 degrees C [0m[0;32mInfo (21077): High junction temperature is 85 degrees C [0m[0;32mInfo (332104): Reading SDC File: 'app.sdc' [0m[0;32mInfo (332104): Reading SDC File: 'app_derate.sdc' [0m[0;36mWarning (332190): Using the -early option with a derate factor of 2.0, i.e., greater than 1.0, causes less conservative delays which might lead to optimistic results from timing analysis. [0m[0;32mInfo (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" [0m[0;32mInfo (332105): Deriving Clocks [0m[0;32m Info (332105): create_clock -period 1.000 -name clk clk [0m[0;32mInfo (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" [0m[0;32mInfo (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. [0m[0;32mInfo: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON [0m[0;32mInfo: Analyzing Slow 1200mV 85C Model [0m[0;36mCritical Warning (332148): Timing requirements not met [0m[0;32m Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. [0m[0;32mInfo (332146): Worst-case setup slack is -4.527 [0m[0;32m Info (332119): Slack End Point TNS Clock [0m[0;32m Info (332119): ========= =================== ===================== [0m[0;32m Info (332119): -4.527 -49.451 clk [0m[0;32mInfo (332146): Worst-case hold slack is 0.869 [0m[0;32m Info (332119): Slack End Point TNS Clock [0m[0;32m Info (332119): ========= =================== ===================== [0m[0;32m Info (332119): 0.869 0.000 clk [0m[0;32mInfo (332140): No Recovery paths to report [0m[0;32mInfo (332140): No Removal paths to report [0m[0;32mInfo (332146): Worst-case minimum pulse width slack is -3.974 [0m[0;32m Info (332119): Slack End Point TNS Clock [0m[0;32m Info (332119): ========= =================== ===================== [0m[0;32m Info (332119): -3.974 -58.636 clk [0m[0;32mInfo: Analyzing Slow 1200mV 0C Model [0m[0;32mInfo (334003): Started post-fitting delay annotation [0m[0;32mInfo (334004): Delay annotation completed successfully [0m[0;32mInfo (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. [0m[0;36mCritical Warning (332148): Timing requirements not met [0m[0;32m Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. [0m[0;32mInfo (332146): Worst-case setup slack is -4.119 [0m[0;32m Info (332119): Slack End Point TNS Clock [0m[0;32m Info (332119): ========= =================== ===================== [0m[0;32m Info (332119): -4.119 -44.563 clk [0m[0;32mInfo (332146): Worst-case hold slack is 0.769 [0m[0;32m Info (332119): Slack End Point TNS Clock [0m[0;32m Info (332119): ========= =================== ===================== [0m[0;32m Info (332119): 0.769 0.000 clk [0m[0;32mInfo (332140): No Recovery paths to report [0m[0;32mInfo (332140): No Removal paths to report [0m[0;32mInfo (332146): Worst-case minimum pulse width slack is -3.974 [0m[0;32m Info (332119): Slack End Point TNS Clock [0m[0;32m Info (332119): ========= =================== ===================== [0m[0;32m Info (332119): -3.974 -58.636 clk [0m[0;32mInfo: Analyzing Fast 1200mV 0C Model [0m[0;32mInfo (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. [0m[0;36mCritical Warning (332148): Timing requirements not met [0m[0;32m Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. [0m[0;32mInfo (332146): Worst-case setup slack is -1.286 [0m[0;32m Info (332119): Slack End Point TNS Clock [0m[0;32m Info (332119): ========= =================== ===================== [0m[0;32m Info (332119): -1.286 -13.488 clk [0m[0;32mInfo (332146): Worst-case hold slack is 0.352 [0m[0;32m Info (332119): Slack End Point TNS Clock [0m[0;32m Info (332119): ========= =================== ===================== [0m[0;32m Info (332119): 0.352 0.000 clk [0m[0;32mInfo (332140): No Recovery paths to report [0m[0;32mInfo (332140): No Removal paths to report [0m[0;32mInfo (332146): Worst-case minimum pulse width slack is -3.000 [0m[0;32m Info (332119): Slack End Point TNS Clock [0m[0;32m Info (332119): ========= =================== ===================== [0m[0;32m Info (332119): -3.000 -68.476 clk [0m[0;32mInfo (332102): Design is not fully constrained for setup requirements [0m[0;32mInfo (332102): Design is not fully constrained for hold requirements [0m[0;32mInfo: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings [0m[0;32m Info: Peak virtual memory: 428 megabytes [0m[0;32m Info: Processing ended: Sun Jan 29 07:42:21 2023 [0m[0;32m Info: Elapsed time: 00:00:04 [0m[0;32m Info: Total CPU time (on all processors): 00:00:04 [0m[0;32mInfo: ******************************************************************* [0m[0;32mInfo: Running Quartus II 32-bit EDA Netlist Writer [0m[0;32m Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version [0m[0;32m Info: Processing started: Sun Jan 29 07:42:25 2023 [0m[0;32mInfo: Command: quartus_eda --read_settings_files=off --write_settings_files=off app -c app [0m[0;32mInfo (204019): Generated file app_8_1200mv_85c_slow.vo in folder "/root/apps/altasvc/temp/simulation/modelsim/" for EDA simulation tool [0m[0;32mInfo (204019): Generated file app_8_1200mv_0c_slow.vo in folder "/root/apps/altasvc/temp/simulation/modelsim/" for EDA simulation tool [0m[0;32mInfo (204019): Generated file app_min_1200mv_0c_fast.vo in folder "/root/apps/altasvc/temp/simulation/modelsim/" for EDA simulation tool [0m[0;32mInfo (204019): Generated file app.vo in folder "/root/apps/altasvc/temp/simulation/modelsim/" for EDA simulation tool [0m[0;32mInfo (204019): Generated file app_8_1200mv_85c_v_slow.sdo in folder "/root/apps/altasvc/temp/simulation/modelsim/" for EDA simulation tool [0m[0;32mInfo (204019): Generated file app_8_1200mv_0c_v_slow.sdo in folder "/root/apps/altasvc/temp/simulation/modelsim/" for EDA simulation tool [0m[0;32mInfo (204019): Generated file app_min_1200mv_0c_v_fast.sdo in folder "/root/apps/altasvc/temp/simulation/modelsim/" for EDA simulation tool [0m[0;32mInfo (204019): Generated file app_v.sdo in folder "/root/apps/altasvc/temp/simulation/modelsim/" for EDA simulation tool [0m[0;32mInfo: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings [0m[0;32m Info: Peak virtual memory: 343 megabytes [0m[0;32m Info: Processing ended: Sun Jan 29 07:42:27 2023 [0m[0;32m Info: Elapsed time: 00:00:02 [0m[0;32m Info: Total CPU time (on all processors): 00:00:01 [0m[0;32mInfo (293000): Quartus II Full Compilation was successful. 0 errors, 31 warnings [0m[0;32mInfo (23030): Evaluation of Tcl script af_quartus.tcl was successful [0m[0;32mInfo: Quartus II 32-bit Shell was successful. 0 errors, 32 warnings [0m[0;32m Info: Peak virtual memory: 139 megabytes [0m[0;32m Info: Processing ended: Sun Jan 29 07:42:27 2023 [0m[0;32m Info: Elapsed time: 00:01:17 [0m[0;32m Info: Total CPU time (on all processors): 00:01:13 [0m
svc: quartus_sh exit code 0 svc: af -B, --batch, --mode, QUARTUS, -X, set QUARTUS_SDC true, -X, set FITTING timing_more, -X, set FITTER full, -X, set EFFORT highest, -X, set HOLDX default, -X, set SKEW basicaf: /root/apps/altasvc/../altagate//Supra-2019.10.b0/lib/libao.so.4: no version information available (required by af) Sun Jan 29 07:42:28 2023 Using pre-ASF file app.pre.asf. Total IO : 84 Total Pin : 40/7 Top array is built. Loading architect libraries... ## CPU time: 0:0:0, REAL time: 0:0:0 ## Memory Usage: 0MB (0MB) Loading route table... ## CPU time: 0:0:1, REAL time: 0:0:1 ## Memory Usage: 63MB (63MB) Using design verilog file ./simulation/modelsim/app.vo. Preparing design... ## CPU time: 0:0:0, REAL time: 0:0:0 ## Memory Usage: 63MB (63MB) Pseudo pack design... Packing Statistics Total Logics : 23/1280 ( 1%) Total LUTs : 22/1280 ( 1%) Total Registers : 14/1280 ( 1%) Total Block Rams : 0/ 15 ( 0%) Total Slice Rams : 0/ 160 ( 0%) Total PLLs : 0/ 1 ( 0%) Total Pins : 5/ 40 ( 12%) Global Signals : 1/ 8 ( 12%) clk~inputclkctrl_outclk (from: clk~input_o) Total Lonely Datain : 0 Total Lonely Register : 1 Total LUT-FF Pairs : 13 Total Register Packings : 0 Registers with synchronous reset : 0 Registers with asynchronous reset : 0 Registers with sync and async reset : 0 ## CPU time: 0:0:0, REAL time: 0:0:0 ## Memory Usage: 63MB (63MB) Filter verilog... ## CPU time: 0:0:0, REAL time: 0:0:0 ## Memory Usage: 63MB (63MB) Read DB design... ## CPU time: 0:0:0, REAL time: 0:0:0 ## Memory Usage: 80MB (80MB) Process design... Info: Found GCLK net clk~inputclkctrl_outclk (4). ## CPU time: 0:0:0, REAL time: 0:0:0 ## Memory Usage: 81MB (81MB) Using design SDC file ./app.sdc. Using ASF file app.asf. Info: Auto constraint: create_clock -name Internal_generated_clock_app|clk -period 1000.000 clk. Placement Statistics Total Logic Tiles : 2/80 (2.5%) Total Valid Nets : 34 (16+18) Total Valid Fanouts : 143 (82+61) Total Tile Fanouts : 30 Tile Zip Fanins : 7 (3:11) Tile Zip Fanouts : 14 (7:21) Total Ignored Nets : 16 Total Valid Blocks : 5 (2/3) Total Ignored Blocks : 1 Total Zip Complexities : 4/30 1.58/6.30 Avg Zip Bottleneck : 1.00 1.00 Avg Net Bottleneck : 13.00 218.00 Iter #1/1 ... Pass 1 #1/2 ... Partitioning... step = 0, partition : 13,8 step = 1, partition : 6,5 .................... step = 2, partition : 3,2 .................... step = 3, partition : 2,2 .................... step = 4, partition : 2,2 .................... ## CPU time: 0:0:0, REAL time: 0:0:0 Pass 1 #2/2 ... Partitioning... step = 0, partition : 13,8 step = 1, partition : 6,5 .................... step = 2, partition : 3,2 .................... step = 3, partition : 2,2 .................... step = 4, partition : 2,2 .................... ## CPU time: 0:0:0, REAL time: 0:0:1 Pass 2 #1/1 ... Legalization and Swapping... .......... ## CPU time: 0:0:0, REAL time: 0:0:0 Pass 3 #1/1 ... Touchup... ## CPU time: 0:0:0, REAL time: 0:0:0 Pass 4 #1/1 ... Optimization... ............................................................ Finishing... ## CPU time: 0:0:0, REAL time: 0:0:0 Total wire cost after placement: 0:0:0(0:0) 40.898(19.571)+55(0)+10 20.2277(2.31606)+-37.5 *** Post Placement Timing Report *** === User constraints === === Auto constraints === Fmax report User constraint: 1.000MHz, Fmax: 326.043MHz, Clock: Internal_generated_clock_app|clk Clock transfer report: Worst setup: 996.933, with clock Internal_generated_clock_app|clk Worst hold: 1.052, with clock Internal_generated_clock_app|clk Coverage report User constraints covered 0 connections out of 99 total, coverage: 0.0% Auto constraints covered 95 connections out of 99 total, coverage: 96.0% Hold from enabled to enabled, clock Internal_generated_clock_app|clk, constraint 0.000 Slack: 1.052 Arrival Time: 3.092 Required Time: 2.040 *** End Timing Report *** route_design -dump ./alta_db/route.tx -replace ./alta_db/replace.tx Route Design Statistics Total Routing Nets : 34 Fanout Average : 3.21 (1..8) Max Fanout Net : AsyncReset_X12_Y1_GND Logic Slices : 23/1280 (1.8%) Routing... Budget Useful Skew... === User constraints === === Auto constraints === Fmax report User constraint: 1.000MHz, Fmax: 326.043MHz, Clock: Internal_generated_clock_app|clk ## CPU time: 0:0:0, REAL time: 0:0:0 iter = 1/1, route#: 34, violation# : 8, overflow# : 8, conflict# : 8, node#: 175 ## CPU time: 0:0:0, REAL time: 0:0:0 iter = 2/2, route#: 34, violation# : 6, overflow# : 6, conflict# : 7, node#: 179 ## CPU time: 0:0:0, REAL time: 0:0:0 iter = 3/3, route#: 34, violation# : 0, overflow# : 0, conflict# : 0, node#: 190 ## CPU time: 0:0:0, REAL time: 0:0:0 iter = 4/2, route#: 2, violation# : 0, overflow# : 0, conflict# : 0, node#: 190 ## CPU time: 0:0:0, REAL time: 0:0:0 iter = 5/2, route#: 2, violation# : 0, overflow# : 0, conflict# : 0, node#: 190 ## CPU time: 0:0:0, REAL time: 0:0:0 iter = 6/1, route#: 2, violation# : 0, overflow# : 0, conflict# : 0, node#: 190 ## CPU time: 0:0:0, REAL time: 0:0:0 iter = 7/2, route#: 2, violation# : 0, overflow# : 0, conflict# : 0, node#: 190 ## CPU time: 0:0:0, REAL time: 0:0:0 iter = 8/1, route#: 2, violation# : 0, overflow# : 0, conflict# : 0, node#: 190 ## CPU time: 0:0:0, REAL time: 0:0:0 iter = 9/1, route#: 2, violation# : 0, overflow# : 0, conflict# : 0, node#: 190 Optimizing... ... Done *** Post Routing Timing Report *** === User constraints === === Auto constraints === Fmax report User constraint: 1.000MHz, Fmax: 150.082MHz, Clock: Internal_generated_clock_app|clk Clock transfer report: Worst setup: 993.337, with clock Internal_generated_clock_app|clk Worst hold: 1.052, with clock Internal_generated_clock_app|clk Coverage report User constraints covered 0 connections out of 99 total, coverage: 0.0% Auto constraints covered 95 connections out of 99 total, coverage: 96.0% Hold from enabled to enabled, clock Internal_generated_clock_app|clk, constraint 0.000 Slack: 1.052 Arrival Time: 4.110 Required Time: 3.058 *** End Timing Report *** Sun Jan 29 07:42:33 2023 Warn: User constraints coverage is too low at 0.0%. Info: Using config file ./app.bin to generate download file ./app_download.svf. Using post-ASF file app.post.asf. Sun Jan 29 07:42:34 2023 Total 0 fatals, 0 errors, 1 warnings, 3 infos.
svc: af exit code 0 Done: 0.009, 0.290, 9.273, 9.131, 79.036, 5.735


PixInvent, I fount you...
I would be good.Family
Thanks, Let's do it.
Can we connect today...
You have new comment...
Hi Pixinvent...Work
Project ABC Status...
Andy, Lte's...Private
Your New UI.
Everything looks good.
Thanks, Let's do it.
Can we connect today...
I paid it, Thanks.
Check once...Work
Where are you John?
Party tonight ?Friends
Okay, I will call you.
Here they are work.
Your New UI.
Everything looks good.
Thanks, Let's do it.
Can we connect today...
I paid it, Thanks.
Check once...Work
Where are you John?
Party tonight ?Friends
Okay, I will call you.
Here they are work.


I Alone Level-up: Chapter 47
Was it because of the restrictions?
The drop rate was good . He had only taken down three knights, but two of them dropped an item . It was a drop rate of 66 . 6% . He had not seen a rate like this anywhere else before . On top of that, most of the items dropped in Instant Dungeons were trash that were sold to the shop . This was not the case here .
| You’ve found a “High-level Knight’s Breastplate” [1]. |
| Would you like to acquire it?. |
‘Of course I would . ’
The breastplate of the first knight Jinwoo took out slowly disappeared then reappeared in front of his feet .
thud
The equipment’s information popped up .
| High-level Knight’s Breastplate. |
| Rarity: B. Type: Armor. Physical Damage Reduction +7%. (If your strength is below 80, your movements will be slowed . ) |
7% physical damage reduction! Combined with his natural buff, he could increase his damage reduction to a total of 27% .
‘If I reach a 100%, do I just become immune to physical damage?’
He dismissed the thought after realizing that a B-rank equipment only gave 7% . If the pattern stuck, an A-rank equipment would probably not give 30% or 40% reduction, so reaching 100% would be impossible .
‘Still, every little bit counts . ’
Gathering the boosts bit by bit would have a great impact down the line . He remembered the effectiveness of good equipment the first time he saw Yoo Jinho .
‘So I just do this, right?’
He held up the breastplate . As expected, the System asked him with a message,
| Would you like to equip the “High-level Knight’s Breastplate”?. |
Just looking at the armor, it was not something he wanted to be seen walking around in . If it wasn’t for his experiences with “Gatekeeper’s Necklace”, he would’ve been a lot more hesitant .
‘Yes . ’
ring~
| The “High-level Knight’s Breastplate” has been equipped . . |
The breastplate was invisible to the eye . Jinwoo opened up his status screen to confirm the benefits .
| Physical Damage Reduction: 27%. |
‘The reduction increased . ’
He felt his chest; he did not feel anything there . He twisted and stretched his body but did not feel the armor hinder him . It was almost as if it wasn’t there . It was the same as the time he equipped the Gatekeeper’s Necklace .
‘Good . ’
Jinwoo turned his gaze to the other knight, crumpled up in a corner . Its crushed form sparked with the light of a drop .
| You’ve found a “Leather Pouch”. |
| Would you like to acquire it?. |
Although it was his handiwork, he felt a little bad at its mangled body . It seemed that he could not control his strength when using his bare hands in a fight .
“ . ”
With a solemn expression, he stretched a hand to the light,
‘Acquire . ’
| You’ve opened the leather pouch . . |
| There was 30,000 gold inside . . |
| You’ve acquired 30,000 gold . . |
‘Huh?’
Without even appearing in his hands, the leather pouch was just opened . It appeared that this was a little different than the other items . He opened his inventory and confirmed that he had received the 30,000 gold .
| Current Gold: 863,400. |
‘Thirty thousand in one go, eh?’
Was it because knights normally carried that much? He remembered that in video games, humanoid monsters often dropped more items than others . Well, it made sense that humans carried more things than beasts or bugs . Not that it was certain the System was copying all of that . Still, this was good news . There were still many things he wanted to buy with gold, and it would be good if gold kept dropping this way .
‘Anything else I could take?’
They say there was no end to man’s greed . Jinwoo looked around with greedy eyes . The knights’ armors were all crushed by his hands and did not look usable… His gaze fell upon their swords .
‘That looks usable . ’
A clean longsword that looked new . Since it was not a dagger, he didn’t plan on using it, but he could probably sell in the shop or to other Hunters . Jinwoo picked up the sword . However, the moment he raised the weapon, it rapidly rusted then turned to dust in his hands .
“Shit…”
It happened in a blink of an eye .
‘It won’t let me obtain anything if it’s not a drop?’
Regrettable, but there was nothing he could do . He clapped his hands and picked up the torch he had dropped earlier .
Turning around the corner to where the knights had come from, he saw yet another deep, dark tunnel .
“ . ”
It seemed that there was still a long way to go .
It was funny, but it almost seemed like he had to study the encounters like a test . After 2 hours of wandering the Dungeon, he had come across 4 types of monsters:
Knights, Mages, Assassins and Archers .
“Is it ‘Stealth’ this time?”
The assassin had disappeared before his eyes . Without panicking, Jinwoo immediately focused his senses and detected the enemy approaching from his back .
clang!
Jinwoo parried the assassin’s dagger with Casaka’s Poisoned Fang, then quickly counterattacked after it fell off his balance . His dagger found its way straight into the enemy’s chest .
stab!
| You’ve defeated the Assassin . . |
| You’ve leveled up!. |
After receiving a fatal blow, the assassin turned into black smoke without so much as a scream .
thud
All that was left in its place was the leather armor it was wearing .
‘I wonder why they’re all humanoid . ’
Jinwoo thought this every time he defeated one of them . Thankfully, he did not get to see their faces when they fought . The knights had their helmets, the assassins and archers their leather hoods, and the mages covered their heads with the hood of their robes .
Jinwoo turned to continue on his path .
Suddenly, a flash blinded his vision . A mage that hid its presence had completed casting its light-element spell .
Bang!
It was an explosion that pierced the ears!
But Jinwoo had already moved behind the mage .
“ . !”
The mage detected a presence behind it and quickly began to cast a spell, but Jinwoo had already brought down his dagger down upon it . The mage disappeared with a black smoke .
thud
Jinwoo stared at the robe that lost its owner and put away his dagger .
‘I was hit by an attack like that before, you see . ’
In fact, he was already preparing to move when he felt the collection of mana from a distance . Jo Gyuhwan’s light-element magic . Jinwoo was not as naive as to be struck by an attack he was hit with before . This was the meaning of studying the encounters .
‘Not only that . ’
Each of the monsters needed a specific stat to deal with .
Knights with strength, assassins with sense, archers with agility and mages with constitution .
If the appropriate stat was not above a certain level, dealing with the corresponding enemy would’ve been very difficult . With a low strength, he wouldn’t have been able to damage the armor of the knight; with a low sense, he wouldn’t have been able to detect the assassin .
‘Looks like distributing my stats evenly was helpful for situations like this’
Well, his intelligence was a bit low, but that could be dealt with by managing his mana carefully .
| You’ve opened the leather pouch . . |
| There was 20,000 gold and a “canteen with warm water” inside . . |
| You’ve acquired 20,000 gold and a “canteen with warm water” . . |
Jinwoo opened his inventory and took out the canteen and drank from it .
“Whew-”
Fatigue was piling up .
‘How much longer do I have to go?’
No, was there even an end?
Jinwoo dropped the empty canteen and stood with his hands on his hip . It’s been 3 hours since he had started the quest . Both his body and mind were becoming tired .
‘ . Should I rest for a bit?’
He sat down with his back against the cave wall .
‘Status screen . ’
ring~
| Fatigue: 66. |
His fatigue had almost reached a dangerous point . Above 70, it would have a noticeable debuff on his body and mind . Even for a moment, he had to rest his eyes and recover his stamina . Jinwoo rested his head against the wall and quickly began to doze off . Even in this environment, he was so tired that he would fall asleep in a moment . Unfortunately…
thwip-!
A sharp sound flew across the air! With his agility stat slowing down the world, Jinwoo was able to grab the arrow that was flying towards him .
grab!
The Hunter’s eyes shot open . At a distance, the archer was preparing its next shot .
‘Won’t let me even sleep, huh . ’
Jinwoo summoned Casaka’s Poisoned Fang as he got up .
crack!
The breastplate caved in at Jinwoo’s punch, and the knight struck the wall . Its body slid down the wall, sprawled out on the ground and stopped moving .
ring~
| You’ve defeated the Knight . . |
| You’ve leveled up!. |
It was unfortunate that it was not accompanied by a status recovery, but Jinwoo was still steadily leveling up through the battles . It was a small consolation amidst the piling up fatigue . The man stared at his slightly scratched knuckles and clicked his tongue . It would be nice if he could just rest for a little bit, but the monsters did not give him any room to breathe . Thankfully, they did drop a lot of items .
| Equipment [2]. Gatekeeper’s Necklace (A) High-level Knight’s Breastplate (B) Mid-level Assassin’s Shoes (B) Low-level Archer’s Gloves (C) High-level Mage’s Ring (B) |
Other than what he had equipped, there were several items that he put away in his inventory as well .
‘Wish they dropped a usable weapon . ’
Unfortunately, the daggers dropped by the assassins, while having a similar attack power as Casaka’s Poisoned Fang, did not have any special effects so could not be considered an upgrade .
‘Alright, what’ve you got?’
Jinwoo stretched a hand toward the light from the fallen knight .
ring~
| High-level Knight’s Gauntlet. |
| Rarity: B. Type: Armor. Physical Damage Reduction +3%. Additional effect: Protects the hands from injury. (If your strength is below 80, your movement will be slowed . ) |
‘Oooh . ’
Jinwoo obtained the gauntlets with a happy expression and equipped them . Just like the other equipment, the gauntlets did not show their form and did not impede his fingers .
‘Good . ’
After moving his fingers around, Jinwoo raised his head .
Ahead of the tunnel, the torches that lined the wall finally ended . At their end was a giant door . Jinwoo remembered the entrance of the underground temple from back then . His party was not prepared and met a tragic fate through the doors .
It would be different this time .
Jinwoo looked back on the path that he had walked so far .
‘It’s been six hours since I came in here…’
His level had reached 45, and he had picked up a lot of new equipment .
He was prepared .
He wanted to rest for a bit and recover his stamina, but he knew that it would just summon more monsters that would interrupt his sleep . He could not afford to increase his fatigue any more through such encounters .
| HP: 4,511 / 8,330. MP: 660 / 790 Fatigue: 43 |
‘I have to win with just this . ’
After performing a final check on his status, Jinwoo grabbed the handles of the door .
guoooooooo-!
As if moved by some unknown mechanism, the doors opened apart easily .
.
Translator’s Notes:
[1]: “High-level Knight’s Breastplate” (상급 기사의 흉갑): “advanced/high level” 상급 + “knight” 기사 + “breastplate” 흉갑
[2]: All pretty literal and straight forward . The equipment are divided into 3 tiers, high-level, mid-level and low-level (상급, 중급, 하급) .


?BOTANICAL
NeČ.York
Botanical
Garden
lb545b?
E.
C.
LEONARD,
Collector
April
4-12,
1920
jT
t
ang
Vicinity
or
MUiiuvlUuiČEtang
Saumatre
SMITHSONIAN
INSTITUTION
From
THE
UNITED
STATES
NATIONAL
HERBARIUM
PLANTS
OF
HAITI
BIOLOGICAL
EXPLORATION
CONDUCTED
BY
DR.
W.
L.
ABBOTT
Eustoma
exaltatum
(L.)
Salisb.
ex
G.
Don
Det.-rev.
M.
Thiv
(B)
2001
1624567
Legend -
Level of confidence that token is an accurately-transcribed word
extremely low
very low
low
undetermined
medium
high
very high


--- layout: page-services title: Montage Studio | HTML5 Authoring - HTML5 Framework explore: true ---


The whole screenshot is created with JavaScript. The only server interaction that is happening on this page is the proxy for loading the external pages/images into JSONP/CORS enabled page and onwards onto the JavaScript renderer script. There are a lot of problemii s of loading external pages, even with a proxy, and as such many pages will not render at all. If you wish to try the script properly, I recommend you get a copy of the source from here instead.


Fruit Project
My still life project focused on fruits, and how the intensity of their colours can be manipulated to create brighter and bolder paintings. I had researched the work of Amy Whitehouse and Kaiti Papadimitriou to inspire my two outcomes. My final pieces show a pomegranate, painted from a photo I took and digitally edited myself as a reference. The first outcome was made with acrylic paint and my second mixed media.
Modelling and Observational Sketching
I wanted to develop my modelling skills as well as my observational drawing, so I created models out of card to investigate the effects of light and shadows. It was interesting to see the shadows change form as the light source moved. Following that, I tried making sketches of the models from life using a ball-point pen and cross-hatching technique.
Digital Art
In my free time, I enjoy making digital art of fictional characters. Using a tablet and stylus, I like to create characters based on colour schemes, and also illustrate existing characters from fictional worlds. Sometimes I share my digital art on social media for others to see.
Architecture Modelling
I had completed the Bronze Arts Award where the aim was to create our own architectural models of follies using card, accompanied by orthographic drawings of our designs. I started making initial models to explore the capabilities of card, then I chose two of my models to combine and develop into a final design.


AWS::ApiGateway::Deployment
The AWS::ApiGateway::Deployment
resource deploys an Amazon API Gateway (API Gateway) RestApi
resource to a stage so that clients can call the API over the Internet. The stage
acts as an environment.
Syntax
To declare this entity in your AWS CloudFormation template, use the following syntax:
JSON
{ "Type" : "AWS::ApiGateway::Deployment", "Properties" : { "DeploymentCanarySettings" :
DeploymentCanarySettings
, "Description" :String
, "RestApiId" :String
, "StageDescription" :StageDescription
, "StageName" :String
} }
YAML
Type: AWS::ApiGateway::Deployment Properties: DeploymentCanarySettings:
DeploymentCanarySettings
Description:String
RestApiId:String
StageDescription:StageDescription
StageName:String
Properties
DeploymentCanarySettings
-
Specifies settings for the canary deployment.
Required: No
Type: DeploymentCanarySettings
Update requires: Replacement
Description
-
A description of the purpose of the API Gateway deployment.
Required: No
Type: String
Update requires: No interruption
RestApiId
-
The ID of the RestApi resource to deploy.
Required: Yes
Type: String
Update requires: Replacement
StageDescription
-
Configures the stage that API Gateway creates with this deployment.
Required: No
Type: Amazon API Gateway Deployment StageDescription
Update requires: No interruption
StageName
-
A name for the stage that API Gateway creates with this deployment. Use only alphanumeric characters.
Required: No
Type: String
Update requires: No interruption
Return Value
Ref
When the logical ID of this resource is provided to the Ref
intrinsic function, Ref
returns the deployment ID, such as 123abc
.
For more information about using the Ref
function, see Ref.
Examples
The following sections provide examples for declaring API Gateway deployments.
Deployment with an Empty Embedded Stage
The following example deploys the MyApi
API to a stage named DummyStage
.
JSON
"Deployment": { "Type": "AWS::ApiGateway::Deployment", "Properties": { "RestApiId": { "Ref": "MyApi" }, "Description": "My deployment", "StageName": "DummyStage" } }
YAML
Deployment: Type: AWS::ApiGateway::Deployment Properties: RestApiId: Ref: "MyApi" Description: "My deployment" StageName: "DummyStage"
AWS::ApiGateway::Method
Dependency
If you create a AWS::ApiGateway::RestApi
resource and its methods (using AWS::ApiGateway::Method
) in the same template as your deployment, the deployment must depend on the RestApi
's methods. To create a dependency, add a DependsOn
attribute to the deployment. If you don't, AWS CloudFormation creates the deployment
right after it creates the RestApi
resource that doesn't contain any methods, and AWS CloudFormation encounters the
following error:
The REST API doesn't contain any methods
.
JSON
"Deployment": { "DependsOn": "MyMethod", "Type": "AWS::ApiGateway::Deployment", "Properties": { "RestApiId": { "Ref": "MyApi" }, "Description": "My deployment", "StageName": "DummyStage" } }
YAML
Deployment: DependsOn: "MyMethod" Type: AWS::ApiGateway::Deployment Properties: RestApiId: Ref: "MyApi" Description: "My deployment" StageName: "DummyStage"


Reports properties in .fxml files (both attributes and tags) that have the default values and therefore are redundant.


|
||||||||||
| PREV NEXT | FRAMES NO FRAMES |
| Packages that use com.brightcove.commons.catalog.objects.enumerations | |
|---|---|
| com.brightcove.commons.catalog.objects | |
| com.brightcove.commons.catalog.objects.enumerations |
| Classes in com.brightcove.commons.catalog.objects.enumerations used by com.brightcove.commons.catalog.objects | |
|---|---|
| ControllerTypeEnum
The controller type for a rendition on a video. |
|
| CuePointTypeEnum
The type for a Cue Point on a video. |
|
| EconomicsEnum
The economic model for a video. |
|
| GeoFilterCodeEnum
The geography name/code pair to be used in filtering videos. |
|
| ImageTypeEnum
The type for an Image. |
|
| InclusionRuleEnum
The Inclusion Rule for a playlist. |
|
| ItemStateEnum
The state a video is in. |
|
| PlaylistTypeEnum
The type for a playlist. |
|
| VideoCodecEnum
The codec used for encoding a video. |
|
| VideoFieldEnum
Defines the allowable fields on a Video object. |
| Classes in com.brightcove.commons.catalog.objects.enumerations used by com.brightcove.commons.catalog.objects.enumerations | |
|---|---|
| ControllerTypeEnum
The controller type for a rendition on a video. |
|
| CuePointTypeEnum
The type for a Cue Point on a video. |
|
| EconomicsEnum
The economic model for a video. |
|
| EncodeToEnum
The encoding to transcode a new video to after initial creation. |
|
| GeoFilterCodeEnum
The geography name/code pair to be used in filtering videos. |
|
| ImageTypeEnum
The type for an Image. |
|
| InclusionRuleEnum
The Inclusion Rule for a playlist. |
|
| ItemStateEnum
The state a video is in. |
|
| MediaDeliveryEnum
Format to deliver media URLs in. |
|
| PlaylistFieldEnum
Defines the allowable fields on a Playlist object. |
|
| PlaylistTypeEnum
The type for a playlist. |
|
| SortByTypeEnum
The field to sort a video list on. |
|
| SortOrderTypeEnum
The order (direction) to sort a video list in. |
|
| UploadStatusEnum
The status for an uploaded video. |
|
| VideoCodecEnum
The codec used for encoding a video. |
|
| VideoFieldEnum
Defines the allowable fields on a Video object. |
|
| VideoStateFilterEnum
States a video can be in, to be used for filtering find_x Media API calls. |
|
||||||||||
| PREV NEXT | FRAMES NO FRAMES |


Backstroke is the first stroke in a medley relay.
Breaststroke is the second stroke in a medley relay.
Butterfly is the third stroke in a medley relay.
Freestyle is the last stroke in a medley relay.


Lions BloodBank |
| Contact No:080 22266807 | Email: NA |
Address:Bhagwan Mahaveer Jain Hospital,Vasantha Nagar | Pincode:560052 |
| City: Bangalore |
| Website:NA |
|
KIMS Hospital |
| Contact No:080 26613225 | Email: NA |
Address:K.R.Road, Visveswarapuram | Pincode:560004 |
| City: Bangalore | | Website:https://kimsblood.bank/ |
|
Indian Medical Association |
| Contact No:NA | Email: NA |
Address:358,Old Government Hospital, BeronQuilla,ShantiNagar | Pincode:560079 |
| City: Bangalore | | Website:NA |
|
Bangalore Baptist Hospital |
| Contact No:080 22024700 | Email: NA |
Address:Bellary Road, Hebbal | Pincode:560024 |
| City: Bangalore |
| Website:Https://www.bbh.og.in/ |
|
Victoria Hospital |
| Contact No:NA | Email: NA |
Address:Fort Road, K.R.Market | Pincode:560002 |
| City: Bangalore |
| Website:NA |
|
KLE.Societys Hosptial |
| Contact No:NA | Email: NA |
Address:Nehru Nagar, Bengaluru | Pincode:560010 |
| City: Bangalore | | Website:NA |
|


#Build: Synplify Pro (R) N-2018.03G-Beta6, Build 118R, May 15 2018 #install: C:\Gowin\1.8\SynplifyPro #OS: Windows 8 6.2 #Hostname: BEACONDEV3 # Mon Oct 8 02:53:50 2018 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03G-Beta6 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.2 Hostname: BEACONDEV3 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11 @N: : | Running in 64-bit mode Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03G-Beta6 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.2 Hostname: BEACONDEV3 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11 @N: : | Running in 64-bit mode @N: : | : Running Verilog Compiler in System Verilog mode @N: : | : Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Gowin\oled_ssd1306\impl\temp\gao\ao_0\gw_ao_parameter.v" (library work) @I::"C:\Gowin\oled_ssd1306\impl\temp\gao\ao_0\gw_ao_top_define.v" (library work) @I::"C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_define.v" (library work) @I::"C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_mem_ctrl.v" (library work) @W:CG1337 : gw_ao_mem_ctrl.v(104) | Net capture_length_zero is not declared. @I::"C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_top.v" (library work) Verilog syntax check successful! @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_C:\Gowin\oled_ssd1306\impl\temp\gao\ao_0\gw_ao_parameter.v_unit in library work. Selecting top level module ao_top Extracted state machine for register module_state State machine has 6 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 75MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Oct 8 02:53:51 2018 ###########################################################] Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: N-2018.03G-Beta6 Install: C:\Gowin\1.8\SynplifyPro OS: Windows 6.2 Hostname: BEACONDEV3 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Oct 8 02:53:51 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Oct 8 02:53:51 2018 ###########################################################]


--- layout: page title: Corpus page: Tasks permalink: tasks/corpus ---
Corpus building is the task of creating corpus suitable for various natural language processing tasks. The corpus are often sanitized and labeled and are available in a ready to use format.
{% include table.html %}


Even the all-powerful Pointing has no control about the blind texts it is an almost unorthographic life One day however a small line of blind text by the name of Lorem Ipsum decided to leave for the far World of Grammar.
The Big Oxmox advised her not to do so, because there were thousands of bad Commas, wild Question Marks and devious Semikoli, but the Little Blind Text didn’t listen.
For dynamic shadows works accurately enough, I only calculate the shadow inside frustum of camera. On other iterations, I create one fake frustum independent to the camera to have the precision at the cost to distance.
Because the size of the map will not influence the performance of the game, I implement baked shadows.
When we calculated the baked shadows, We looked that they were are inaccurate due to the amount of information stored in a single texture. To solve this, I choose to create a version of a cascade method where I divide the information stored in three different textures.
At the last days of this project, the team ask for a new water shader more simplest than we already had. For this shader, I create one where the uvs gave the visual effect of movement.
When we go to present this shader, I realized that the textures imported in GL_CLAMP_TO_EDGE for default and I can’t change these. For solve this and I can pass the water shader to the team, I edit the resource system of textures to save the new variables that I need. The bad things are that the implementation of this system arrives in the polish phase and we can’t implement into the game.


Transforming an UML model into a RDBMS model
(Demonstrates 'default_values' and 'opposite' feature)
------------------------------------------------------------------------------------------------------------------------------------
This example demonstrates the use of 'default_values' and
'opposite' constructs in qvt specification file.
'default_values' feature : This
feature is used to specify a default value for a target domain variable when it
does not get a binding from the evaluation of other relation expressions. This
feature is relevant only for enforcement.
'opposite' feature : 'opposite' is used to
specify the non-navigable end of an association. e.g. UML Meta model has an
association "attribute" from Class to Attribute, which is
non-navigable in Class direction. In this case, opposite can be used as
"opposite(umlmm::Class.attribute)" to navigate in Class direction.
Syntax :
"opposite" "("
<fully-qualified-class-pathname> "." <navigable-end>
")"
Folder ‘spec’ contains :
UmlToRel.qvt :
QVT specification file for UmlToRel transformation.
Folder ‘spec/Example1’ contains :
UmlMM.xml : UML
Meta Model
RelMM.xml :
RDBMS Meta Model
UmlUM1.xml : A
sample UML model
Folder ‘spec/Example2’ contains :
UmlMM.xml : UML
Meta Model
RelMM.xml :
RDBMS Meta Model
RelUM2.xml : A
sample RDBMS model
UML metamodel:
See figure 'Simple UML Meta Model for example UmlToRel' in
file UmlToRel.pdf file.
RDBMS metamodel:
See figure 'Simple RDBMS Meta Model for example UmlToRel'
in file UmlToRel.pdf file.
This example maps classes of a simple UML model to tables
of a simple RDBMS model & vice versa.
----------
The sample UML model is given in file UmlUM1.xml file
contains:
Example QVT file (UmlToRel.qvt) is run in enforce mode in
rdbms direction. It enforces RDBMS model & exports it in RelUM1.xml file.
To run this example execute the batch file ‘run1.bat’ for
windows or the shell script ‘run1.sh’
for unix.
----------
The sample RDBMS model is given in file RelUM2.xml file
contains:
Example QVT file (UmlToRel.qvt) is run in enforce mode in
uml direction. It enforces UML model & exports it in UmlUM2.xml file.
To run this example execute the batch file ‘run2.bat’ for
windows or the shell script ‘run2.sh’
for unix.


The site
This site allows a user to create and delete posts as well as accounts. Each post has the date of posting, a title and an author.
Posts are editable however, only the posts' author can edit its content and title
The making of the site
This site was made using the Python programming language and the Flask extension
Why was this site made
The main reason was to provide a basic training of the skills required to build a next, more advanced project