Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA | Source operand is an SNaN value or unsupported format. |
| #D | Source is a denormal value. |
| #U | Result is too small for destination format. |
| #P | Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
| Same exceptions as in protected mode. |
| 3-309 |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| F2XM1—Compute 2x–1 |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 E1 | FABS | Valid | Valid | Replace ST with its absolute value. |
Description
| Clears the sign bit of ST(0) to create the absolute value of the operand. The following table shows the results |
| obtained when creating the absolute value of various classes of numbers. |
Table 3-17. Results Obtained from FABS
| ST(0) SRC | ST(0) DEST |
|---|---|
| − ∞ | + ∞ |
| − F | + F |
| − 0 | + 0 |
| + 0 | + 0 |
| + F | + F |
| + ∞ | + ∞ |
| NaN | NaN |
NOTES:
| F Means finite floating-point value. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
ST(0) ← |ST(0)|;
FPU Flags Affected
| C1 | Set to 0. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| 3-311 |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D8 /0 | FADD m32fp | Valid | Valid | Add m32fp to ST(0) and store result in ST(0). |
| DC /0 | FADD m64fp | Valid | Valid | Add m64fp to ST(0) and store result in ST(0). |
| D8 C0+i | FADD ST(0), ST(i) | Valid | Valid | Add ST(0) to ST(i) and store result in ST(0). |
| DC C0+i | FADD ST(i), ST(0) | Valid | Valid | Add ST(i) to ST(0) and store result in ST(i). |
| DE C0+i | FADDP ST(i), ST(0) | Valid | Valid |
Add ST(0) to ST(i), store result in ST(i), and pop the register stack. |
| DE C1 | FADDP | Valid | Valid |
Add ST(0) to ST(1), store result in ST(1), and pop the register stack. |
| DA /0 | FIADD m32int | Valid | Valid | Add m32int to ST(0) and store result in ST(0). |
| DE /0 | FIADD m16int | Valid | Valid | Add m16int to ST(0) and store result in ST(0). |
Description
| Adds the destination and source operands and stores the sum in the destination location. The destination operand |
| is always an FPU register; the source operand can be a register or a memory location. Source operands in memory |
| can be in single-precision or double-precision floating-point format or in word or doubleword integer format. |
| The no-operand version of the instruction adds the contents of the ST(0) register to the ST(1) register. The one- |
| operand version adds the contents of a memory location (either a floating-point or an integer value) to the contents |
| of the ST(0) register. The two-operand version, adds the contents of the ST(0) register to the ST(i) register or vice |
| versa. The value in ST(0) can be doubled by coding: |
| FADD ST(0), ST(0); |
| The FADDP instructions perform the additional operation of popping the FPU register stack after storing the result. |
| To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) |
| by 1. (The no-operand version of the floating-point add instructions always results in the register stack being |
| popped. In some assemblers, the mnemonic for this instruction is FADD rather than FADDP.) |
| The FIADD instructions convert an integer source operand to double extended-precision floating-point format |
| before performing the addition. |
| The table on the following page shows the results obtained when adding various classes of numbers, assuming that |
| neither overflow nor underflow occurs. |
| When the sum of two operands with opposite signs is 0, the result is +0, except for the round toward −∞ mode, in |
| which case the result is −0. When the source operand is an integer 0, it is treated as a +0. |
| When both operand are infinities of the same sign, the result is ∞ of the expected sign. If both operands are infini- |
| ties of opposite signs, an invalid-operation exception is generated. See Table 3-18. |
| FADD/FADDP/FIADD—Add |
Table 3-18. FADD/FADDP/FIADD Results
DEST
| NaN | − ∞ | − F | − 0 | + 0 | + F | + ∞ |
| − ∞ | − ∞ | − ∞ | − ∞ | − ∞ | − ∞ | * |
| − F or − I | − ∞ | − F | SRC | SRC | ± F or ± 0 | + ∞ |
SRC
| DEST | DEST | NaN | −0 | − ∞ | − 0 | ± 0 | + ∞ |
| DEST | DEST | NaN | + 0 | − ∞ | ± 0 | + 0 | + ∞ |
| ± F or ± 0 | + F | NaN | + F or + I | − ∞ | SRC | SRC | + ∞ |
| + ∞ | + ∞ | NaN | + ∞ | * | + ∞ | + ∞ | + ∞ |
| NaN | NaN | NaN | NaN | NaN | NaN | NaN | NaN |
NOTES:
| F Means finite floating-point value. |
| Means integer. |
| Indicates floating-point invalid-arithmetic-operand (#IA) exception. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| IF Instruction = FIADD |
| THEN |
| DEST ← DEST + ConvertToDoubleExtendedPrecisionFP(SRC); |
| ELSE (* Source operand is floating-point value *) |
| DEST ← DEST + SRC; |
| FI; |
| IF Instruction = FADDP |
| THEN |
| PopRegisterStack; |
| FI; |
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA |
Operand is an SNaN value or unsupported format. Operands are infinities of unlike sign. |
| #D | Source operand is a denormal value. |
| #U | Result is too small for destination format. |
| #O | Result is too large for destination format. |
|
#P 3-313 |
Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD FADD/FADDP/FIADD—Add |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| DF /4 | FBLD m80dec | Valid | Valid |
Convert BCD value to floating-point and push onto the FPU stack. |
Description
| Converts the BCD source operand into double extended-precision floating-point format and pushes the value onto |
| the FPU stack. The source operand is loaded without rounding errors. The sign of the source operand is preserved, |
| including that of −0. |
| The packed BCD digits are assumed to be in the range 0 through 9; the instruction does not check for invalid digits |
| (AH through FH). Attempting to load an invalid encoding produces an undefined result. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| TOP ← TOP − 1; |
| ST(0) ← ConvertToDoubleExtendedPrecisionFP(SRC); |
FPU Flags Affected
| C1 | Set to 1 if stack overflow occurred; otherwise, set to 0. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack overflow occurred. |
Protected Mode Exceptions
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
|
#UD 3-315 |
If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD FBLD—Load Binary Coded Decimal |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| DF /6 | FBSTP m80bcd | Valid | Valid | Store ST(0) in m80bcd and pop ST(0). |
Description
| Converts the value in the ST(0) register to an 18-digit packed BCD integer, stores the result in the destination |
| operand, and pops the register stack. If the source value is a non-integral value, it is rounded to an integer value, |
| according to rounding mode specified by the RC field of the FPU control word. To pop the register stack, the |
| processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. |
| The destination operand specifies the address where the first byte destination value is to be stored. The BCD value |
| (including its sign bit) requires 10 bytes of space in memory. |
| The following table shows the results obtained when storing various classes of numbers in packed BCD format. |
Table 3-19. FBSTP Results
| ST(0) | DEST |
|---|---|
| − ∞ or Value Too Large for DEST Format | * |
| F ≤ − 1 | − D |
| −1 < F < -0 | ** |
| − 0 | − 0 |
| + 0 | + 0 |
| + 0 < F < +1 | ** |
| F ≥ +1 | + D |
| + ∞ or Value Too Large for DEST Format | * |
| NaN | * |
NOTES:
| F Means finite floating-point value. |
| D Means packed-BCD number. |
| Indicates floating-point invalid-operation (#IA) exception. |
| ** ±0 or ±1, depending on the rounding mode. |
| If the converted value is too large for the destination format, or if the source operand is an ∞, SNaN, QNAN, or is in |
| an unsupported format, an invalid-arithmetic-operand condition is signaled. If the invalid-operation exception is |
| not masked, an invalid-arithmetic-operand exception (#IA) is generated and no value is stored in the destination |
| operand. If the invalid-operation exception is masked, the packed BCD indefinite value is stored in memory. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| DEST ← BCD(ST(0)); |
| PopRegisterStack; |
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. |
|
C0, C2, C3 3-317 |
Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA |
Converted value that exceeds 18 BCD digits in length. Source operand is an SNaN, QNaN, ±∞, or in an unsupported format. |
| #P | Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #GP(0) |
If a segment register is being loaded with a segment selector that points to a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD FBSTP—Store BCD Integer and Pop |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 E0 | FCHS | Valid | Valid | Complements sign of ST(0). |
Description
| Complements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magni- |
| tude or vice versa. The following table shows the results obtained when changing the sign of various classes of |
| numbers. |
Table 3-20. FCHS Results
| ST(0) SRC | ST(0) DEST |
|---|---|
| − ∞ | + ∞ |
| − F | + F |
| − 0 | + 0 |
| + 0 | − 0 |
| + F | − F |
| + ∞ | − ∞ |
| NaN | NaN |
NOTES:
| * |
F means finite floating-point value. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
SignBit(ST(0)) ← NOT (SignBit(ST(0)));
FPU Flags Affected
| C1 | Set to 0. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
| Same exceptions as in protected mode. |
| 3-319 |
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FCHS—Change Sign |
| Opcode* | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| 9B DB E2 | FCLEX | Valid | Valid |
Clear floating-point exception flags after checking for pending unmasked floating-point exceptions. |
| DB E2 | FNCLEX* | Valid | Valid |
Clear floating-point exception flags without checking for pending unmasked floating-point exceptions. |
NOTES:
| * | See IA-32 Architecture Compatibility section below. |
Description
| Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), the exception summary status flag (ES), the |
| stack fault flag (SF), and the busy flag (B) in the FPU status word. The FCLEX instruction checks for and handles |
| any pending unmasked floating-point exceptions before clearing the exception flags; the FNCLEX instruction does |
| not. |
| The assembler issues two instructions for the FCLEX instruction (an FWAIT instruction followed by an FNCLEX |
| instruction), and the processor executes each of these instructions separately. If an exception is generated for |
| either of these instructions, the save EIP points to the instruction that caused the exception. |
IA-32 Architecture Compatibility
| When operating a Pentium or Intel486 processor in MS-DOS* compatibility mode, it is possible (under unusual |
| circumstances) for an FNCLEX instruction to be interrupted prior to being executed to handle a pending FPU excep- |
| tion. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel® |
| 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances. An |
| FNCLEX instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000 |
| processor. |
| This instruction affects only the x87 FPU floating-point exception flags. It does not affect the SIMD floating-point |
| exception flags in the MXCRS register. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| FPUStatusWord[0:7] ← 0; |
| FPUStatusWord[15] ← 0; |
FPU Flags Affected
| The PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared. The C0, C1, C2, and C3 flags are |
| undefined. |
Floating-Point Exceptions
None
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| Same exceptions as in protected mode. |
| 3-321 |
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FCLEX/FNCLEX—Clear Exceptions |
| Opcode* | Instruction | 64-Bit Mode | Compat/Leg Mode* | Description |
|---|---|---|---|---|
| DA C0+i | FCMOVB ST(0), ST(i) | Valid | Valid | Move if below (CF=1). |
| DA C8+i | FCMOVE ST(0), ST(i) | Valid | Valid | Move if equal (ZF=1). |
| DA D0+i | FCMOVBE ST(0), ST(i) | Valid | Valid | Move if below or equal (CF=1 or ZF=1). |
| DA D8+i | FCMOVU ST(0), ST(i) | Valid | Valid | Move if unordered (PF=1). |
| DB C0+i | FCMOVNB ST(0), ST(i) | Valid | Valid | Move if not below (CF=0). |
| DB C8+i | FCMOVNE ST(0), ST(i) | Valid | Valid | Move if not equal (ZF=0). |
| DB D0+i | FCMOVNBE ST(0), ST(i) | Valid | Valid | Move if not below or equal (CF=0 and ZF=0). |
| DB D8+i | FCMOVNU ST(0), ST(i) | Valid | Valid | Move if not unordered (PF=0). |
NOTES:
| * | See IA-32 Architecture Compatibility section below. |
Description
| Tests the status flags in the EFLAGS register and moves the source operand (second operand) to the destination |
| operand (first operand) if the given test condition is true. The condition for each mnemonic os given in the Descrip- |
| tion column above and in Chapter 8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume |
| 1. The source operand is always in the ST(i) register and the destination operand is always ST(0). |
| The FCMOVcc instructions are useful for optimizing small IF constructions. They also help eliminate branching |
| overhead for IF operations and the possibility of branch mispredictions by the processor. |
| A processor may not support the FCMOVcc instructions. Software can check if the FCMOVcc instructions are |
| supported by checking the processor’s feature information with the CPUID instruction (see “COMISS—Compare |
| Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS” in this chapter). If both the CMOV and FPU |
| feature bits are set, the FCMOVcc instructions are supported. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
IA-32 Architecture Compatibility
| The FCMOVcc instructions were introduced to the IA-32 Architecture in the P6 family processors and are not avail- |
| able in earlier IA-32 processors. |
Operation
| IF condition TRUE |
| THEN ST(0) ← ST(i); |
| FI; |
FPU Flags Affected
| C1 | Set to 0 if stack underflow occurred. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
Integer Flags Affected
| None. |
| 3-323 |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FCMOVcc—Floating-Point Conditional Move |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D8 /2 | FCOM m32fp | Valid | Valid | Compare ST(0) with m32fp. |
| DC /2 | FCOM m64fp | Valid | Valid | Compare ST(0) with m64fp. |
| D8 D0+i | FCOM ST(i) | Valid | Valid | Compare ST(0) with ST(i). |
| D8 D1 | FCOM | Valid | Valid | Compare ST(0) with ST(1). |
| D8 /3 | FCOMP m32fp | Valid | Valid | Compare ST(0) with m32fp and pop register stack. |
| DC /3 | FCOMP m64fp | Valid | Valid | Compare ST(0) with m64fp and pop register stack. |
| D8 D8+i | FCOMP ST(i) | Valid | Valid | Compare ST(0) with ST(i) and pop register stack. |
| D8 D9 | FCOMP | Valid | Valid | Compare ST(0) with ST(1) and pop register stack. |
| DE D9 | FCOMPP | Valid | Valid |
Compare ST(0) with ST(1) and pop register stack twice. |
Description
| Compares the contents of register ST(0) and source value and sets condition code flags C0, C2, and C3 in the FPU |
| status word according to the results (see the table below). The source operand can be a data register or a memory |
| location. If no source operand is given, the value in ST(0) is compared with the value in ST(1). The sign of zero is |
| ignored, so that –0.0 is equal to +0.0. |
Table 3-21. FCOM/FCOMP/FCOMPP Results
| Condition | C3 | C2 | C0 |
|---|---|---|---|
| ST(0) > SRC | 0 | 0 | 0 |
| ST(0) < SRC | 0 | 0 | 1 |
| ST(0) = SRC | 1 | 0 | 0 |
| Unordered* | 1 | 1 | 1 |
NOTES:
| * |
Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated. This instruction checks the class of the numbers being compared (see “FXAM—Examine Floating-Point” in this chapter). If either operand is a NaN or is in an unsupported format, an invalid-arithmetic-operand exception (#IA) is raised and, if the exception is masked, the condition flags are set to “unordered.” If the invalid-arithmetic- operand exception is unmasked, the condition code flags are not set. The FCOMP instruction pops the register stack following the comparison operation and the FCOMPP instruction pops the register stack twice following the comparison operation. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The FCOM instructions perform the same operation as the FUCOM instructions. The only difference is how they handle QNaN operands. The FCOM instructions raise an invalid-arithmetic-operand exception (#IA) when either or both of the operands is a NaN value or is in an unsupported format. The FUCOM instructions perform the same operation as the FCOM instructions, except that they do not generate an invalid-arithmetic-operand exception for QNaNs. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. 3-325 |
Operation
| CASE (relation of operands) OF |
| C3, C2, C0 ← 000; |
| C3, C2, C0 ← 001; |
| C3, C2, C0 ← 100; |
| ESAC; |
| IF ST(0) or SRC = NaN or unsupported format |
| THEN |
| #IA |
| IF FPUControlWord.IM = 1 |
| THEN |
| C3, C2, C0 ← 111; |
| FI; |
| FI; |
| IF Instruction = FCOMP |
| THEN |
| PopRegisterStack; |
| FI; |
| IF Instruction = FCOMPP |
| THEN |
| PopRegisterStack; |
| PopRegisterStack; |
| FI; |
FPU Flags Affected
| C1 | Set to 0. |
| C0, C2, C3 | See table on previous page. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA |
One or both operands are NaN values or have unsupported formats. Register is marked empty. |
| #D | One or both operands are denormal values. |
Protected Mode Exceptions
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
|
#UD FCOM/FCOMP/FCOMPP—Compare Floating Point Values |
If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD 3-327 |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| DB F0+i | FCOMI ST, ST(i) | Valid | Valid | Compare ST(0) with ST(i) and set status flags accordingly. |
| DF F0+i | FCOMIP ST, ST(i) | Valid | Valid |
Compare ST(0) with ST(i), set status flags accordingly, and pop register stack. |
| DB E8+i | FUCOMI ST, ST(i) | Valid | Valid |
Compare ST(0) with ST(i), check for ordered values, and set status flags accordingly. |
| DF E8+i | FUCOMIP ST, ST(i) | Valid | Valid |
Compare ST(0) with ST(i), check for ordered values, set status flags accordingly, and pop register stack. |
Description
| Performs an unordered comparison of the contents of registers ST(0) and ST(i) and sets the status flags ZF, PF, and |
| CF in the EFLAGS register according to the results (see the table below). The sign of zero is ignored for compari- |
| sons, so that –0.0 is equal to +0.0. |
Table 3-22. FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results
| Comparison Results* | ZF | PF | CF |
|---|---|---|---|
| ST0 > ST(i) | 0 | 0 | 0 |
| ST0 < ST(i) | 0 | 0 | 1 |
| ST0 = ST(i) | 1 | 0 | 0 |
| Unordered** | 1 | 1 | 1 |
NOTES:
|
* ** Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated. An unordered comparison checks the class of the numbers being compared (see “FXAM—Examine Floating-Point” in this chapter). The FUCOMI/FUCOMIP instructions perform the same operations as the FCOMI/FCOMIP instruc- tions. The only difference is that the FUCOMI/FUCOMIP instructions raise the invalid-arithmetic-operand exception (#IA) only when either or both operands are an SNaN or are in an unsupported format; QNaNs cause the condition code flags to be set to unordered, but do not cause an exception to be generated. The FCOMI/FCOMIP instructions raise an invalid-operation exception when either or both of the operands are a NaN value of any kind or are in an unsupported format. If the operation results in an invalid-arithmetic-operand exception being raised, the status flags in the EFLAGS register are set only if the exception is masked. The FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions set the OF, SF and AF flags to zero in the EFLAGS register (regardless of whether an invalid-operation exception is detected). The FCOMIP and FUCOMIP instructions also pop the register stack following the comparison operation. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
See the IA-32 Architecture Compatibility section below. |
IA-32 Architecture Compatibility
| The FCOMI/FCOMIP/FUCOMI/FUCOMIP instructions were introduced to the IA-32 Architecture in the P6 family |
| processors and are not available in earlier IA-32 processors. |
| FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS |
Operation
| CASE (relation of operands) OF |
| ZF, PF, CF ← 000; |
| ZF, PF, CF ← 001; |
| ZF, PF, CF ← 100; |
| ESAC; |
| IF Instruction is FCOMI or FCOMIP |
| THEN |
| IF ST(0) or ST(i) = NaN or unsupported format |
| THEN |
| #IA |
| IF FPUControlWord.IM = 1 |
| THEN |
| ZF, PF, CF ← 111; |
| FI; |
| FI; |
| FI; |
| IF Instruction is FUCOMI or FUCOMIP |
| THEN |
| IF ST(0) or ST(i) = QNaN, but not SNaN or unsupported format |
| THEN |
| ZF, PF, CF ← 111; |
| ELSE (* ST(0) or ST(i) is SNaN or unsupported format *) |
| #IA; |
| IF FPUControlWord.IM = 1 |
| THEN |
| ZF, PF, CF ← 111; |
| FI; |
| FI; |
| FI; |
| IF Instruction is FCOMIP or FUCOMIP |
| THEN |
| PopRegisterStack; |
| FI; |
FPU Flags Affected
| C1 | Set to 0. |
| C0, C2, C3 | Not affected. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
|
#IA 3-329 |
(FCOMI or FCOMIP instruction) One or both operands are NaN values or have unsupported formats. (FUCOMI or FUCOMIP instruction) One or both operands are SNaN values (but not QNaNs) or have undefined formats. Detection of a QNaN value does not raise an invalid-operand excep- tion. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 FF | FCOS | Valid | Valid | Replace ST(0) with its approximate cosine. |
Description
| Computes the approximate cosine of the source operand in register ST(0) and stores the result in ST(0). The |
| source operand must be given in radians and must be within the range −263 to +263. The following table shows the |
| results obtained when taking the cosine of various classes of numbers. |
Table 3-23. FCOS Results
| ST(0) SRC | ST(0) DEST |
|---|---|
| − ∞ | * |
| − F | −1 to +1 |
| − 0 | + 1 |
| + 0 | + 1 |
| + F | − 1 to + 1 |
| + ∞ | * |
| NaN | NaN |
NOTES:
| F Means finite floating-point value. |
| Indicates floating-point invalid-arithmetic-operand (#IA) exception. |
| If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in |
| register ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of |
| range. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range − |
| 263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2π. |
| However, even within the range -263 to +263, inaccurate results can occur because the finite approximation of π |
| used internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply |
| FCOS only to arguments reduced accurately in software, to a value smaller in absolute value than 3π/8. See the |
| sections titled “Approximation of Pi” and “Transcendental Instruction Accuracy” in Chapter 8 of the Intel® 64 and |
| IA-32 Architectures Software Developer’s Manual, Volume 1, for a discussion of the proper value to use for π in |
| performing such reductions. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| IF |ST(0)| < 263 |
| THEN |
| C2 ← 0; |
| ST(0) ← FCOS(ST(0)); // approximation of cosine |
| ELSE (* Source operand is out-of-range *) |
| C2 ← 1; |
| FI; |
| 3-331 |
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. Undefined if C2 is 1. |
| C2 | Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0. |
| C0, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA | Source operand is an SNaN value, ∞, or unsupported format. |
| #D | Source is a denormal value. |
| #P | Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FCOS— Cosine |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 F6 | FDECSTP | Valid | Valid | Decrement TOP field in FPU status word. |
Description
| Subtracts one from the TOP field of the FPU status word (decrements the top-of-stack pointer). If the TOP field |
| contains a 0, it is set to 7. The effect of this instruction is to rotate the stack by one position. The contents of the |
| FPU data registers and tag register are not affected. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| IF TOP = 0 |
| THEN TOP ← 7; |
| ELSE TOP ← TOP – 1; |
| FI; |
FPU Flags Affected
The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.
Floating-Point Exceptions
None.
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| 3-333 |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D8 /6 | FDIV m32fp | Valid | Valid | Divide ST(0) by m32fp and store result in ST(0). |
| DC /6 | FDIV m64fp | Valid | Valid | Divide ST(0) by m64fp and store result in ST(0). |
| D8 F0+i | FDIV ST(0), ST(i) | Valid | Valid | Divide ST(0) by ST(i) and store result in ST(0). |
| DC F8+i | FDIV ST(i), ST(0) | Valid | Valid | Divide ST(i) by ST(0) and store result in ST(i). |
| DE F8+i | FDIVP ST(i), ST(0) | Valid | Valid |
Divide ST(i) by ST(0), store result in ST(i), and pop the register stack. |
| DE F9 | FDIVP | Valid | Valid |
Divide ST(1) by ST(0), store result in ST(1), and pop the register stack. |
| DA /6 | FIDIV m32int | Valid | Valid | Divide ST(0) by m32int and store result in ST(0). |
| DE /6 | FIDIV m16int | Valid | Valid | Divide ST(0) by m16int and store result in ST(0). |
Description
| Divides the destination operand by the source operand and stores the result in the destination location. The desti- |
| nation operand (dividend) is always in an FPU register; the source operand (divisor) can be a register or a memory |
| location. Source operands in memory can be in single-precision or double-precision floating-point format, word or |
| doubleword integer format. |
| The no-operand version of the instruction divides the contents of the ST(1) register by the contents of the ST(0) |
| register. The one-operand version divides the contents of the ST(0) register by the contents of a memory location |
| (either a floating-point or an integer value). The two-operand version, divides the contents of the ST(0) register by |
| the contents of the ST(i) register or vice versa. |
| The FDIVP instructions perform the additional operation of popping the FPU register stack after storing the result. |
| To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) |
| by 1. The no-operand version of the floating-point divide instructions always results in the register stack being |
| popped. In some assemblers, the mnemonic for this instruction is FDIV rather than FDIVP. |
| The FIDIV instructions convert an integer source operand to double extended-precision floating-point format |
| before performing the division. When the source operand is an integer 0, it is treated as a +0. |
| If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of |
| the appropriate sign is stored in the destination operand. |
| The following table shows the results obtained when dividing various classes of numbers, assuming that neither |
| overflow nor underflow occurs. |
| FDIV/FDIVP/FIDIV—Divide |
Table 3-24. FDIV/FDIVP/FIDIV Results
DEST
| NaN | − ∞ | − F | − 0 | + 0 | + F | + ∞ |
| − ∞ | * | + 0 | + 0 | − 0 | − 0 | * |
| − F | + ∞ | + F | + 0 | − 0 | − F | − ∞ |
| − I | + ∞ | + F | + 0 | − 0 | − F | − ∞ |
SRC
| ** | * | * | ** | NaN | − 0 | + ∞ | − ∞ |
| ** | * | * | ** | NaN | + 0 | − ∞ | + ∞ |
| − F | − 0 | + 0 | + F | NaN | + I | − ∞ | + ∞ |
| − F | − 0 | + 0 | + F | NaN | + F | − ∞ | + ∞ |
| − 0 | − 0 | + 0 | + 0 | NaN | + ∞ | * | * |
| NaN | NaN | NaN | NaN | NaN | NaN | NaN | NaN |
NOTES:
| F Means finite floating-point value. |
| Means integer. |
| Indicates floating-point invalid-arithmetic-operand (#IA) exception. |
| ** Indicates floating-point zero-divide (#Z) exception. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| IF SRC = 0 |
| THEN |
| #Z; |
| ELSE |
| IF Instruction is FIDIV |
| THEN |
| DEST ← DEST / ConvertToDoubleExtendedPrecisionFP(SRC); |
| ELSE (* Source operand is floating-point value *) |
| DEST ← DEST / SRC; |
| FI; |
| FI; |
| IF Instruction = FDIVP |
| THEN |
| PopRegisterStack; |
| FI; |
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. |
|
C0, C2, C3 3-335 |
Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA |
Operand is an SNaN value or unsupported format. ±∞ / ±∞; ±0 / ±0 |
| #D | Source is a denormal value. |
| #Z | DEST / ±0, where DEST is not equal to ±0. |
| #U | Result is too small for destination format. |
| #O | Result is too large for destination format. |
| #P | Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD FDIV/FDIVP/FIDIV—Divide |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D8 /7 | FDIVR m32fp | Valid | Valid | Divide m32fp by ST(0) and store result in ST(0). |
| DC /7 | FDIVR m64fp | Valid | Valid | Divide m64fp by ST(0) and store result in ST(0). |
| D8 F8+i | FDIVR ST(0), ST(i) | Valid | Valid | Divide ST(i) by ST(0) and store result in ST(0). |
| DC F0+i | FDIVR ST(i), ST(0) | Valid | Valid | Divide ST(0) by ST(i) and store result in ST(i). |
| DE F0+i | FDIVRP ST(i), ST(0) | Valid | Valid |
Divide ST(0) by ST(i), store result in ST(i), and pop the register stack. |
| DE F1 | FDIVRP | Valid | Valid |
Divide ST(0) by ST(1), store result in ST(1), and pop the register stack. |
| DA /7 | FIDIVR m32int | Valid | Valid | Divide m32int by ST(0) and store result in ST(0). |
| DE /7 | FIDIVR m16int | Valid | Valid | Divide m16int by ST(0) and store result in ST(0). |
Description
| Divides the source operand by the destination operand and stores the result in the destination location. The desti- |
| nation operand (divisor) is always in an FPU register; the source operand (dividend) can be a register or a memory |
| location. Source operands in memory can be in single-precision or double-precision floating-point format, word or |
| doubleword integer format. |
| These instructions perform the reverse operations of the FDIV, FDIVP, and FIDIV instructions. They are provided to |
| support more efficient coding. |
| The no-operand version of the instruction divides the contents of the ST(0) register by the contents of the ST(1) |
| register. The one-operand version divides the contents of a memory location (either a floating-point or an integer |
| value) by the contents of the ST(0) register. The two-operand version, divides the contents of the ST(i) register by |
| the contents of the ST(0) register or vice versa. |
| The FDIVRP instructions perform the additional operation of popping the FPU register stack after storing the result. |
| To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) |
| by 1. The no-operand version of the floating-point divide instructions always results in the register stack being |
| popped. In some assemblers, the mnemonic for this instruction is FDIVR rather than FDIVRP. |
| The FIDIVR instructions convert an integer source operand to double extended-precision floating-point format |
| before performing the division. |
| If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of |
| the appropriate sign is stored in the destination operand. |
| The following table shows the results obtained when dividing various classes of numbers, assuming that neither |
| overflow nor underflow occurs. |
| 3-337 |
Table 3-25. FDIVR/FDIVRP/FIDIVR Results
DEST
|
NaN − ∞ NaN |
− ∞ |
− F + ∞ |
− 0 + ∞ |
+ 0 − ∞ |
+ F − ∞ ** |
+ ∞ * |
SRC
| − F | + 0 | + F | − F | − 0 |
| − I | + 0 | + F | − F | − 0 |
| − 0 | + 0 | + 0 | − 0 | − 0 |
| + 0 | − 0 | − 0 | + 0 | + 0 |
| + I | − 0 | − F | + F | + 0 |
|
+ F + ∞ |
− 0 |
− F + ∞ |
+ F + ∞ NaN |
+ 0 NaN |
NOTES:
| F Means finite floating-point value. |
| Means integer. |
| Indicates floating-point invalid-arithmetic-operand (#IA) exception. |
| ** Indicates floating-point zero-divide (#Z) exception. |
| When the source operand is an integer 0, it is treated as a +0. This instruction’s operation is the same in non-64-bit |
| modes and 64-bit mode. |
Operation
| IF DEST = 0 |
| THEN |
| #Z; |
| ELSE |
| IF Instruction = FIDIVR |
| THEN |
| DEST ← ConvertToDoubleExtendedPrecisionFP(SRC) / DEST; |
| ELSE (* Source operand is floating-point value *) |
| DEST ← SRC / DEST; |
| FI; |
| FI; |
| IF Instruction = FDIVRP |
| THEN |
| PopRegisterStack; |
| FI; |
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. |
|
C0, C2, C3 FDIVR/FDIVRP/FIDIVR—Reverse Divide |
Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA |
Operand is an SNaN value or unsupported format. ±∞ / ±∞; ±0 / ±0 |
| #D | Source is a denormal value. |
| #Z | SRC / ±0, where SRC is not equal to ±0. |
| #U | Result is too small for destination format. |
| #O | Result is too large for destination format. |
| #P | Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD 3-339 |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| DD C0+i | FFREE ST(i) | Valid | Valid | Sets tag for ST(i) to empty. |
Description
| Sets the tag in the FPU tag register associated with register ST(i) to empty (11B). The contents of ST(i) and the FPU |
| stack-top pointer (TOP) are not affected. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
TAG(i) ← 11B;
FPU Flags Affected
C0, C1, C2, C3 undefined.
Floating-Point Exceptions
None
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FFREE—Free Floating-Point Register |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| DE /2 | FICOM m16int | Valid | Valid | Compare ST(0) with m16int. |
| DA /2 | FICOM m32int | Valid | Valid | Compare ST(0) with m32int. |
| DE /3 | FICOMP m16int | Valid | Valid | Compare ST(0) with m16int and pop stack register. |
| DA /3 | FICOMP m32int | Valid | Valid | Compare ST(0) with m32int and pop stack register. |
Description
| Compares the value in ST(0) with an integer source operand and sets the condition code flags C0, C2, and C3 in |
| the FPU status word according to the results (see table below). The integer value is converted to double extended- |
| precision floating-point format before the comparison is made. |
Table 3-26. FICOM/FICOMP Results
| Condition | C3 | C2 | C0 |
|---|---|---|---|
| ST(0) > SRC | 0 | 0 | 0 |
| ST(0) < SRC | 0 | 0 | 1 |
| ST(0) = SRC | 1 | 0 | 0 |
| Unordered | 1 | 1 | 1 |
| These instructions perform an “unordered comparison.” An unordered comparison also checks the class of the |
| numbers being compared (see “FXAM—Examine Floating-Point” in this chapter). If either operand is a NaN or is in |
| an undefined format, the condition flags are set to “unordered.” |
| The sign of zero is ignored, so that –0.0 ← +0.0. |
| The FICOMP instructions pop the register stack following the comparison. To pop the register stack, the processor |
| marks the ST(0) register empty and increments the stack pointer (TOP) by 1. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| CASE (relation of operands) OF |
| C3, C2, C0 ← 000; |
| C3, C2, C0 ← 001; |
| C3, C2, C0 ← 100; |
| C3, C2, C0 ← 111; |
| ESAC; |
| IF Instruction = FICOMP |
| THEN |
| PopRegisterStack; |
| FI; |
FPU Flags Affected
| C1 | Set to 0. |
| C0, C2, C3 | See table on previous page. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA | One or both operands are NaN values or have unsupported formats. |
|
#D 3-341 |
One or both operands are denormal values. |
Protected Mode Exceptions
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD FICOM/FICOMP—Compare Integer |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| DF /0 | FILD m16int | Valid | Valid | Push m16int onto the FPU register stack. |
| DB /0 | FILD m32int | Valid | Valid | Push m32int onto the FPU register stack. |
| DF /5 | FILD m64int | Valid | Valid | Push m64int onto the FPU register stack. |
Description
| Converts the signed-integer source operand into double extended-precision floating-point format and pushes the |
| value onto the FPU register stack. The source operand can be a word, doubleword, or quadword integer. It is loaded |
| without rounding errors. The sign of the source operand is preserved. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| TOP ← TOP − 1; |
| ST(0) ← ConvertToDoubleExtendedPrecisionFP(SRC); |
FPU Flags Affected
| C1 | Set to 1 if stack overflow occurred; set to 0 otherwise. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack overflow occurred. |
Protected Mode Exceptions
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
|
#UD 3-343 |
If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD FILD—Load Integer |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 F7 | FINCSTP | Valid | Valid | Increment the TOP field in the FPU status register. |
Description
| Adds one to the TOP field of the FPU status word (increments the top-of-stack pointer). If the TOP field contains a |
| 7, it is set to 0. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data |
| registers and tag register are not affected. This operation is not equivalent to popping the stack, because the tag |
| for the previous top-of-stack register is not marked empty. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| IF TOP = 7 |
| THEN TOP ← 0; |
| ELSE TOP ← TOP + 1; |
| FI; |
FPU Flags Affected
The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.
Floating-Point Exceptions
None
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| 3-345 |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| 9B DB E3 | FINIT | Valid | Valid |
Initialize FPU after checking for pending unmasked floating-point exceptions. |
| DB E3 | FNINIT* | Valid | Valid |
Initialize FPU without checking for pending unmasked floating-point exceptions. |
NOTES:
| * | See IA-32 Architecture Compatibility section below. |
Description
| Sets the FPU control, status, tag, instruction pointer, and data pointer registers to their default states. The FPU |
| control word is set to 037FH (round to nearest, all exceptions masked, 64-bit precision). The status word is cleared |
| (no exception flags set, TOP is set to 0). The data registers in the register stack are left unchanged, but they are all |
| tagged as empty (11B). Both the instruction and data pointers are cleared. |
| The FINIT instruction checks for and handles any pending unmasked floating-point exceptions before performing |
| the initialization; the FNINIT instruction does not. |
| The assembler issues two instructions for the FINIT instruction (an FWAIT instruction followed by an FNINIT |
| instruction), and the processor executes each of these instructions in separately. If an exception is generated for |
| either of these instructions, the save EIP points to the instruction that caused the exception. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
IA-32 Architecture Compatibility
| When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual |
| circumstances) for an FNINIT instruction to be interrupted prior to being executed to handle a pending FPU excep- |
| tion. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel® |
| 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances. An |
| FNINIT instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000 |
| processor. |
| In the Intel387 math coprocessor, the FINIT/FNINIT instruction does not clear the instruction and data pointers. |
| This instruction affects only the x87 FPU. It does not affect the XMM and MXCSR registers. |
Operation
| FPUControlWord ← 037FH; |
| FPUStatusWord ← 0; |
| FPUTagWord ← FFFFH; |
| FPUDataPointer ← 0; |
| FPUInstructionPointer ← 0; |
| FPULastInstructionOpcode ← 0; |
FPU Flags Affected
C0, C1, C2, C3 set to 0.
Floating-Point Exceptions
| None |
| FINIT/FNINIT—Initialize Floating-Point Unit |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| 3-347 |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| DF /2 | FIST m16int | Valid | Valid | Store ST(0) in m16int. |
| DB /2 | FIST m32int | Valid | Valid | Store ST(0) in m32int. |
| DF /3 | FISTP m16int | Valid | Valid | Store ST(0) in m16int and pop register stack. |
| DB /3 | FISTP m32int | Valid | Valid | Store ST(0) in m32int and pop register stack. |
| DF /7 | FISTP m64int | Valid | Valid | Store ST(0) in m64int and pop register stack. |
Description
| The FIST instruction converts the value in the ST(0) register to a signed integer and stores the result in the desti- |
| nation operand. Values can be stored in word or doubleword integer format. The destination operand specifies the |
| address where the first byte of the destination value is to be stored. |
| The FISTP instruction performs the same operation as the FIST instruction and then pops the register stack. To pop |
| the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. |
| The FISTP instruction also stores values in quadword integer format. |
| The following table shows the results obtained when storing various classes of numbers in integer format. |
Table 3-27. FIST/FISTP Results
| ST(0) | DEST |
|---|---|
| − ∞ or Value Too Large for DEST Format | * |
| F ≤ −1 | − I |
| −1 < F < −0 | ** |
| − 0 | 0 |
| + 0 | 0 |
| + 0 < F < + 1 | ** |
| F ≥ + 1 | + I |
| + ∞ or Value Too Large for DEST Format | * |
| NaN | * |
NOTES:
| F Means finite floating-point value. |
| Means integer. |
| Indicates floating-point invalid-operation (#IA) exception. |
| ** 0 or ±1, depending on the rounding mode. |
| If the source value is a non-integral value, it is rounded to an integer value, according to the rounding mode spec- |
| ified by the RC field of the FPU control word. |
| If the converted value is too large for the destination format, or if the source operand is an ∞, SNaN, QNAN, or is in |
| an unsupported format, an invalid-arithmetic-operand condition is signaled. If the invalid-operation exception is |
| not masked, an invalid-arithmetic-operand exception (#IA) is generated and no value is stored in the destination |
| operand. If the invalid-operation exception is masked, the integer indefinite value is stored in memory. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
| FIST/FISTP—Store Integer |
Operation
| DEST ← Integer(ST(0)); |
| IF Instruction = FISTP |
| THEN |
| PopRegisterStack; |
| FI; |
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Indicates rounding direction of if the inexact exception (#P) is generated: 0 ← not roundup; 1 ← roundup. Set to 0 otherwise. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA |
Converted value is too large for the destination format. Source operand is an SNaN, QNaN, ±∞, or unsupported format. |
| #P | Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #GP(0) |
If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
| Same exceptions as in protected mode. |
| 3-349 |
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD FIST/FISTP—Store Integer |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| DF /1 | FISTTP m16int | Valid | Valid | Store ST(0) in m16int with truncation. |
| DB /1 | FISTTP m32int | Valid | Valid | Store ST(0) in m32int with truncation. |
| DD /1 | FISTTP m64int | Valid | Valid | Store ST(0) in m64int with truncation. |
Description
| FISTTP converts the value in ST into a signed integer using truncation (chop) as rounding mode, transfers the |
| result to the destination, and pop ST. FISTTP accepts word, short integer, and long integer destinations. |
| The following table shows the results obtained when storing various classes of numbers in integer format. |
Table 3-28. FISTTP Results
| ST(0) | DEST |
|---|---|
| − ∞ or Value Too Large for DEST Format | * |
| F ≤ − 1 | − I |
| − 1 < F < + 1 | 0 |
| F Š + 1 | + I |
| + ∞ or Value Too Large for DEST Format | * |
| NaN | * |
NOTES:
| F Means finite floating-point value. |
| Ι |
| ∗ Indicates floating-point invalid-operation (#IA) exception. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| DEST ← ST; |
| pop ST; |
Flags Affected
C1 is cleared; C0, C2, C3 undefined.
Numeric Exceptions
Invalid, Stack Invalid (stack underflow), Precision.
Protected Mode Exceptions
| #GP(0) |
If the destination is in a nonwritable segment. For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. |
| #SS(0) | For an illegal address in the SS segment. |
| #PF(fault-code) | For a page fault. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #NM |
If CR0.EM[bit 2] = 1. If CR0.TS[bit 3] = 1. |
|
#UD 3-351 |
If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. |
Real Address Mode Exceptions
| GP(0) | If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. |
| #NM |
If CR0.EM[bit 2] = 1. If CR0.TS[bit 3] = 1. |
| #UD |
If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. |
Virtual 8086 Mode Exceptions
| GP(0) | If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. |
| #NM |
If CR0.EM[bit 2] = 1. If CR0.TS[bit 3] = 1. |
| #UD |
If CPUID.01H:ECX.SSE3[bit 0] = 0. If the LOCK prefix is used. |
| #PF(fault-code) | For a page fault. |
| #AC(0) | For unaligned memory reference if the current privilege is 3. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
|
#AC(0) FISTTP—Store Integer with Truncation |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 /0 | FLD m32fp | Valid | Valid | Push m32fp onto the FPU register stack. |
| DD /0 | FLD m64fp | Valid | Valid | Push m64fp onto the FPU register stack. |
| DB /5 | FLD m80fp | Valid | Valid | Push m80fp onto the FPU register stack. |
| D9 C0+i | FLD ST(i) | Valid | Valid | Push ST(i) onto the FPU register stack. |
Description
| Pushes the source operand onto the FPU register stack. The source operand can be in single-precision, double- |
| precision, or double extended-precision floating-point format. If the source operand is in single-precision or |
| double-precision floating-point format, it is automatically converted to the double extended-precision floating- |
| point format before being pushed on the stack. |
| The FLD instruction can also push the value in a selected FPU register [ST(i)] onto the stack. Here, pushing register |
| ST(0) duplicates the stack top. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| IF SRC is ST(i) |
| THEN |
| temp ← ST(i); |
| FI; |
| TOP ← TOP − 1; |
| IF SRC is memory-operand |
| THEN |
| ST(0) ← ConvertToDoubleExtendedPrecisionFP(SRC); |
| ELSE (* SRC is ST(i) *) |
| ST(0) ← temp; |
| FI; |
FPU Flags Affected
| C1 | Set to 1 if stack overflow occurred; otherwise, set to 0. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow or overflow occurred. |
| #IA |
Source operand is an SNaN. Does not occur if the source operand is in double extended-preci- sion floating-point format (FLD m80fp or FLD ST(i)). |
|
#D 3-353 |
Source operand is a denormal value. Does not occur if the source operand is in double extended-precision floating-point format. |
Protected Mode Exceptions
| #GP(0) |
If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD FLD—Load Floating Point Value |
If the LOCK prefix is used. |
| Opcode* | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 E8 | FLD1 | Valid | Valid | Push +1.0 onto the FPU register stack. |
| D9 E9 | FLDL2T | Valid | Valid | Push log210 onto the FPU register stack. |
| D9 EA | FLDL2E | Valid | Valid | Push log2e onto the FPU register stack. |
| D9 EB | FLDPI | Valid | Valid | Push π onto the FPU register stack. |
| D9 EC | FLDLG2 | Valid | Valid | Push log102 onto the FPU register stack. |
| D9 ED | FLDLN2 | Valid | Valid | Push loge2 onto the FPU register stack. |
| D9 EE | FLDZ | Valid | Valid | Push +0.0 onto the FPU register stack. |
NOTES:
| * | See IA-32 Architecture Compatibility section below. |
Description
| Push one of seven commonly used constants (in double extended-precision floating-point format) onto the FPU |
| register stack. The constants that can be loaded with these instructions include +1.0, +0.0, log210, log2e, π, log102, |
| and loge2. For each constant, an internal 66-bit constant is rounded (as specified by the RC field in the FPU control |
| word) to double extended-precision floating-point format. The inexact-result exception (#P) is not generated as a |
| result of the rounding, nor is the C1 flag set in the x87 FPU status word if the value is rounded up. |
| See the section titled “Approximation of Pi” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Devel- |
| oper’s Manual, Volume 1, for a description of the π constant. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
IA-32 Architecture Compatibility
| When the RC field is set to round-to-nearest, the FPU produces the same constants that is produced by the Intel |
| 8087 and Intel 287 math coprocessors. |
Operation
| TOP ← TOP − 1; |
| ST(0) ← CONSTANT; |
FPU Flags Affected
| C1 | Set to 1 if stack overflow occurred; otherwise, set to 0. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack overflow occurred. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
| Same exceptions as in protected mode. |
| 3-355 |
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 /5 | FLDCW m2byte | Valid | Valid | Load FPU control word from m2byte. |
Description
| Loads the 16-bit source operand into the FPU control word. The source operand is a memory location. This instruc- |
| tion is typically used to establish or change the FPU’s mode of operation. |
| If one or more exception flags are set in the FPU status word prior to loading a new FPU control word and the new |
| control word unmasks one or more of those exceptions, a floating-point exception will be generated upon execution |
| of the next floating-point instruction (except for the no-wait floating-point instructions, see the section titled “Soft- |
| ware Exception Handling” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, |
| Volume 1). To avoid raising exceptions when changing FPU operating modes, clear any pending exceptions (using |
| the FCLEX or FNCLEX instruction) before loading the new control word. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
FPUControlWord ← SRC;
FPU Flags Affected
C0, C1, C2, C3 undefined.
Floating-Point Exceptions
| None; however, this operation might unmask a pending exception in the FPU status word. That exception is then |
| generated upon execution of the next “waiting” floating-point instruction. |
Protected Mode Exceptions
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
|
#UD 3-357 |
If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD FLDCW—Load x87 FPU Control Word |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 /4 | FLDENV m14/28byte | Valid | Valid | Load FPU environment from m14byte or m28byte. |
Description
| Loads the complete x87 FPU operating environment from memory into the FPU registers. The source operand spec- |
| ifies the first byte of the operating-environment data in memory. This data is typically written to the specified |
| memory location by a FSTENV or FNSTENV instruction. |
| The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data |
| pointer, and last opcode. Figures 8-9 through 8-12 in the Intel® 64 and IA-32 Architectures Software Developer’s |
| Manual, Volume 1, show the layout in memory of the loaded environment, depending on the operating mode of the |
| processor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the |
| real mode layouts are used. |
| The FLDENV instruction should be executed in the same operating mode as the corresponding FSTENV/FNSTENV |
| instruction. |
| If one or more unmasked exception flags are set in the new FPU status word, a floating-point exception will be |
| generated upon execution of the next floating-point instruction (except for the no-wait floating-point instructions, |
| see the section titled “Software Exception Handling” in Chapter 8 of the Intel® 64 and IA-32 Architectures Soft- |
| ware Developer’s Manual, Volume 1). To avoid generating exceptions when loading a new environment, clear all |
| the exception flags in the FPU status word that is being loaded. |
| If a page or limit fault occurs during the execution of this instruction, the state of the x87 FPU registers as seen by |
| the fault handler may be different than the state being loaded from memory. In such situations, the fault handler |
| should ignore the status of the x87 FPU registers, handle the fault, and return. The FLDENV instruction will then |
| complete the loading of the x87 FPU registers with no resulting context inconsistency. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| FPUControlWord ← SRC[FPUControlWord]; |
| FPUStatusWord ← SRC[FPUStatusWord]; |
| FPUTagWord ← SRC[FPUTagWord]; |
| FPUDataPointer ← SRC[FPUDataPointer]; |
| FPUInstructionPointer ← SRC[FPUInstructionPointer]; |
| FPULastInstructionOpcode ← SRC[FPULastInstructionOpcode]; |
FPU Flags Affected
The C0, C1, C2, C3 flags are loaded.
Floating-Point Exceptions
| None; however, if an unmasked exception is loaded in the status word, it is generated upon execution of the next |
| “waiting” floating-point instruction. |
| 3-359 |
Protected Mode Exceptions
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD FLDENV—Load x87 FPU Environment |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D8 /1 | FMUL m32fp | Valid | Valid | Multiply ST(0) by m32fp and store result in ST(0). |
| DC /1 | FMUL m64fp | Valid | Valid | Multiply ST(0) by m64fp and store result in ST(0). |
| D8 C8+i | FMUL ST(0), ST(i) | Valid | Valid | Multiply ST(0) by ST(i) and store result in ST(0). |
| DC C8+i | FMUL ST(i), ST(0) | Valid | Valid | Multiply ST(i) by ST(0) and store result in ST(i). |
| DE C8+i | FMULP ST(i), ST(0) | Valid | Valid |
Multiply ST(i) by ST(0), store result in ST(i), and pop the register stack. |
| DE C9 | FMULP | Valid | Valid |
Multiply ST(1) by ST(0), store result in ST(1), and pop the register stack. |
| DA /1 | FIMUL m32int | Valid | Valid | Multiply ST(0) by m32int and store result in ST(0). |
| DE /1 | FIMUL m16int | Valid | Valid | Multiply ST(0) by m16int and store result in ST(0). |
Description
| Multiplies the destination and source operands and stores the product in the destination location. The destination |
| operand is always an FPU data register; the source operand can be an FPU data register or a memory location. |
| Source operands in memory can be in single-precision or double-precision floating-point format or in word or |
| doubleword integer format. |
| The no-operand version of the instruction multiplies the contents of the ST(1) register by the contents of the ST(0) |
| register and stores the product in the ST(1) register. The one-operand version multiplies the contents of the ST(0) |
| register by the contents of a memory location (either a floating point or an integer value) and stores the product in |
| the ST(0) register. The two-operand version, multiplies the contents of the ST(0) register by the contents of the |
| ST(i) register, or vice versa, with the result being stored in the register specified with the first operand (the desti- |
| nation operand). |
| The FMULP instructions perform the additional operation of popping the FPU register stack after storing the |
| product. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack |
| pointer (TOP) by 1. The no-operand version of the floating-point multiply instructions always results in the register |
| stack being popped. In some assemblers, the mnemonic for this instruction is FMUL rather than FMULP. |
| The FIMUL instructions convert an integer source operand to double extended- |
| precision floating-point format before performing the multiplication. |
| The sign of the result is always the exclusive-OR of the source signs, even if one or more of the values being multi- |
| plied is 0 or ∞. When the source operand is an integer 0, it is treated as a +0. |
| The following table shows the results obtained when multiplying various classes of numbers, assuming that neither |
| overflow nor underflow occurs. |
| 3-361 |
Table 3-29. FMUL/FMULP/FIMUL Results
| DEST | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| − ∞ | − F | − 0 | + 0 | + F | + ∞ | NaN | |||||||||||
| − ∞ | + ∞ | + ∞ | * | * | − ∞ | − ∞ | NaN | ||||||||||
| − F | + ∞ | + F | + 0 | − 0 | − F | − ∞ | NaN | ||||||||||
| − I | + ∞ | + F | + 0 | − 0 | − F | − ∞ | NaN | ||||||||||
| SRC | − 0 | * | + 0 | + 0 | − 0 | − 0 | * | NaN | |||||||||
| + 0 | * | − 0 | − 0 | + 0 | + 0 | * | NaN | ||||||||||
| + I | − ∞ | − F | − 0 | + 0 | + F | + ∞ | NaN | ||||||||||
| + F | − ∞ | − F | − 0 | + 0 | + F | + ∞ | NaN | ||||||||||
| + ∞ | − ∞ | − ∞ | * | * | + ∞ | + ∞ | NaN | ||||||||||
| NaN | NaN | NaN | NaN | NaN | NaN | NaN | NaN |
NOTES:
| F Means finite floating-point value. |
| Means Integer. |
| Indicates invalid-arithmetic-operand (#IA) exception. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| IF Instruction = FIMUL |
| THEN |
| DEST ← DEST ∗ ConvertToDoubleExtendedPrecisionFP(SRC); |
| ELSE (* Source operand is floating-point value *) |
| DEST ← DEST ∗ SRC; |
| FI; |
| IF Instruction = FMULP |
| THEN |
| PopRegisterStack; |
| FI; |
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA |
Operand is an SNaN value or unsupported format. One operand is ±0 and the other is ±∞. |
| #D | Source operand is a denormal value. |
| #U | Result is too small for destination format. |
| #O | Result is too large for destination format. |
|
#P FMUL/FMULP/FIMUL—Multiply |
Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD 3-363 |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 D0 | FNOP | Valid | Valid | No operation is performed. |
Description
| Performs no FPU operation. This instruction takes up space in the instruction stream but does not affect the FPU or |
| machine context, except the EIP register and the FPU Instruction Pointer. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
FPU Flags Affected
C0, C1, C2, C3 undefined.
Floating-Point Exceptions
None
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FNOP—No Operation |
| Opcode* | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 F3 | FPATAN | Valid | Valid | Replace ST(1) with arctan(ST(1)/ST(0)) and pop the register stack. |
| NOTES: |
| See IA-32 Architecture Compatibility section below. |
Description
| Computes the arctangent of the source operand in register ST(1) divided by the source operand in register ST(0), |
| stores the result in ST(1), and pops the FPU register stack. The result in register ST(0) has the same sign as the |
| source operand ST(1) and a magnitude less than +π. |
| The FPATAN instruction returns the angle between the X axis and the line from the origin to the point (X,Y), where |
| Y (the ordinate) is ST(1) and X (the abscissa) is ST(0). The angle depends on the sign of X and Y independently, |
| not just on the sign of the ratio Y/X. This is because a point (−X,Y) is in the second quadrant, resulting in an angle |
| between π/2 and π, while a point (X,−Y) is in the fourth quadrant, resulting in an angle between 0 and −π/2. A point |
| (−X,−Y) is in the third quadrant, giving an angle between −π/2 and −π. |
| The following table shows the results obtained when computing the arctangent of various classes of numbers, |
| assuming that underflow does not occur. |
Table 3-30. FPATAN Results
| ST(0) | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| − ∞ | − F | − 0 | + 0 | + F | + ∞ | NaN | |||||||||||
| − ∞ | − 3π/4* | − π/2 | − π/2 | − π/2 | − π/2 | − π/4* | NaN | ||||||||||
| ST(1) | − F | -p | −π to −π/2 | −π/2 | −π/2 | −π/2 to −0 | - 0 | NaN | |||||||||
| − 0 | -p | -p | -p* | − 0* | − 0 | − 0 | NaN | ||||||||||
| + 0 | +p | + p | + π* | + 0* | + 0 | + 0 | NaN | ||||||||||
| + F | +p | +π to +π/2 | + π/2 | +π/2 | +π/2 to +0 | + 0 | NaN | ||||||||||
| + ∞ | +3π/4* | +π/2 | +π/2 | +π/2 | + π/2 | + π/4* | NaN | ||||||||||
| NaN | NaN | NaN | NaN | NaN | NaN | NaN | NaN |
NOTES:
| F Means finite floating-point value. |
| Table 8-10 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, specifies that the ratios 0/0 and ∞/∞ |
| generate the floating-point invalid arithmetic-operation exception and, if this exception is masked, the floating-point QNaN indefi- |
| nite value is returned. With the FPATAN instruction, the 0/0 or ∞/∞ value is actually not calculated using division. Instead, the arc- |
| tangent of the two variables is derived from a standard mathematical formulation that is generalized to allow complex numbers as |
| arguments. In this complex variable formulation, arctangent(0,0) etc. has well defined values. These values are needed to develop |
| a library to compute transcendental functions with complex arguments, based on the FPU functions that only allow floating-point |
| values as arguments. |
| There is no restriction on the range of source operands that FPATAN can accept. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
IA-32 Architecture Compatibility
| The source operands for this instruction are restricted for the 80287 math coprocessor to the following range: |
| 0 ≤ |ST(1)| < |ST(0)| < +∞ |
| 3-365 |
Operation
| ST(1) ← arctan(ST(1) / ST(0)); |
| PopRegisterStack; |
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA | Source operand is an SNaN value or unsupported format. |
| #D | Source operand is a denormal value. |
| #U | Result is too small for destination format. |
| #P | Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FPATAN—Partial Arctangent |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 F8 | FPREM | Valid | Valid |
Replace ST(0) with the remainder obtained from dividing ST(0) by ST(1). |
Description
| Computes the remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the |
| ST(1) register (the divisor or modulus), and stores the result in ST(0). The remainder represents the following |
| value: |
| Remainder ← ST(0) − (Q ∗ ST(1)) |
| Here, Q is an integer value that is obtained by truncating the floating-point number quotient of [ST(0) / ST(1)] |
| toward zero. The sign of the remainder is the same as the sign of the dividend. The magnitude of the remainder is |
| less than that of the modulus, unless a partial remainder was computed (as described below). |
| This instruction produces an exact result; the inexact-result exception does not occur and the rounding control has |
| no effect. The following table shows the results obtained when computing the remainder of various classes of |
| numbers, assuming that underflow does not occur. |
Table 3-31. FPREM Results
| ST(1) | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| -∞ | -F | -0 | +0 | +F | +∞ | NaN | |||||||||||
| -∞ | * | * | * | * | * | * | NaN | ||||||||||
| ST(0) | -F | ST(0) | -F or -0 | ** | ** | -F or -0 | ST(0) | NaN | |||||||||
| -0 | -0 | -0 | * | * | -0 | -0 | NaN | ||||||||||
| +0 | +0 | +0 | * | * | +0 | +0 | NaN | ||||||||||
| +F | ST(0) | +F or +0 | ** | ** | +F or +0 | ST(0) | NaN | ||||||||||
| +∞ | * | * | * | * | * | * | NaN | ||||||||||
| NaN | NaN | NaN | NaN | NaN | NaN | NaN | NaN |
NOTES:
Operation
| D ← exponent(ST(0)) – exponent(ST(1)); |
| IF D < 64 |
| THEN |
| Q ← Integer(TruncateTowardZero(ST(0) / ST(1))); |
| ST(0) ← ST(0) – (ST(1) ∗ Q); |
| C2 ← 0; |
| C0, C3, C1 ← LeastSignificantBits(Q); (* Q2, Q1, Q0 *) |
| ELSE |
| C2 ← 1; |
| N ← An implementation-dependent number between 32 and 63; |
| QQ ← Integer(TruncateTowardZero((ST(0) / ST(1)) / 2(D − N))); |
| ST(0) ← ST(0) – (ST(1) ∗ QQ ∗ 2(D − N)); |
| FI; |
FPU Flags Affected
| C0 | Set to bit 2 (Q2) of the quotient. |
| C1 | Set to 0 if stack underflow occurred; otherwise, set to least significant bit of quotient (Q0). |
| C2 | Set to 0 if reduction complete; set to 1 if incomplete. |
| C3 | Set to bit 1 (Q1) of the quotient. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA | Source operand is an SNaN value, modulus is 0, dividend is ∞, or unsupported format. |
| #D | Source operand is a denormal value. |
| #U | Result is too small for destination format. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FPREM—Partial Remainder |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 F5 | FPREM1 | Valid | Valid |
Replace ST(0) with the IEEE remainder obtained from dividing ST(0) by ST(1). |
Description
| Computes the IEEE remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in |
| the ST(1) register (the divisor or modulus), and stores the result in ST(0). The remainder represents the following |
| value: |
| Remainder ← ST(0) − (Q ∗ ST(1)) |
| Here, Q is an integer value that is obtained by rounding the floating-point number quotient of [ST(0) / ST(1)] |
| toward the nearest integer value. The magnitude of the remainder is less than or equal to half the magnitude of the |
| modulus, unless a partial remainder was computed (as described below). |
| This instruction produces an exact result; the precision (inexact) exception does not occur and the rounding control |
| has no effect. The following table shows the results obtained when computing the remainder of various classes of |
| numbers, assuming that underflow does not occur. |
Table 3-32. FPREM1 Results
| ST(1) | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| − ∞ | − F | − 0 | + 0 | + F | + ∞ | NaN | |||||||||||
| − ∞ | * | * | * | * | * | * | NaN | ||||||||||
| ST(0) | − F | ST(0) | ±F or −0 | ** | ** | ± F or − 0 | ST(0) | NaN | |||||||||
| − 0 | − 0 | − 0 | * | * | − 0 | -0 | NaN | ||||||||||
| + 0 | + 0 | + 0 | * | * | + 0 | +0 | NaN | ||||||||||
| + F | ST(0) | ± F or + 0 | ** | ** | ± F or + 0 | ST(0) | NaN | ||||||||||
| + ∞ | * | * | * | * | * | * | NaN | ||||||||||
| NaN | NaN | NaN | NaN | NaN | NaN | NaN | NaN |
NOTES:
Operation
| D ← exponent(ST(0)) – exponent(ST(1)); |
| IF D < 64 |
| THEN |
| Q ← Integer(RoundTowardNearestInteger(ST(0) / ST(1))); |
| ST(0) ← ST(0) – (ST(1) ∗ Q); |
| C2 ← 0; |
| C0, C3, C1 ← LeastSignificantBits(Q); (* Q2, Q1, Q0 *) |
| ELSE |
| C2 ← 1; |
| N ← An implementation-dependent number between 32 and 63; |
| QQ ← Integer(TruncateTowardZero((ST(0) / ST(1)) / 2(D − N))); |
| ST(0) ← ST(0) – (ST(1) ∗ QQ ∗ 2(D − N)); |
| FI; |
FPU Flags Affected
| C0 | Set to bit 2 (Q2) of the quotient. |
| C1 | Set to 0 if stack underflow occurred; otherwise, set to least significant bit of quotient (Q0). |
| C2 | Set to 0 if reduction complete; set to 1 if incomplete. |
| C3 | Set to bit 1 (Q1) of the quotient. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA |
Source operand is an SNaN value, modulus (divisor) is 0, dividend is ∞, or unsupported format. |
| #D | Source operand is a denormal value. |
| #U | Result is too small for destination format. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FPREM1—Partial Remainder |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 F2 | FPTAN | Valid | Valid |
Replace ST(0) with its approximate tangent and push 1 onto the FPU stack. |
Description
| Computes the approximate tangent of the source operand in register ST(0), stores the result in ST(0), and pushes |
| a 1.0 onto the FPU register stack. The source operand must be given in radians and must be less than ±263. The |
| following table shows the unmasked results obtained when computing the partial tangent of various classes of |
| numbers, assuming that underflow does not occur. |
Table 3-33. FPTAN Results
| ST(0) SRC | ST(0) DEST |
|---|---|
| − ∞ | * |
| − F | − F to + F |
| − 0 | - 0 |
| + 0 | + 0 |
| + F | − F to + F |
| + ∞ | * |
| NaN | NaN |
NOTES:
| F Means finite floating-point value. |
| Indicates floating-point invalid-arithmetic-operand (#IA) exception. |
| If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in |
| register ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of |
| range. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range − |
| 263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2π. |
| However, even within the range -263 to +263, inaccurate results can occur because the finite approximation of π |
| used internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply |
| FPTAN only to arguments reduced accurately in software, to a value smaller in absolute value than 3π/8. See the |
| sections titled “Approximation of Pi” and “Transcendental Instruction Accuracy” in Chapter 8 of the Intel® 64 and |
| IA-32 Architectures Software Developer’s Manual, Volume 1, for a discussion of the proper value to use for π in |
| performing such reductions. |
| The value 1.0 is pushed onto the register stack after the tangent has been computed to maintain compatibility with |
| the Intel 8087 and Intel287 math coprocessors. This operation also simplifies the calculation of other trigonometric |
| functions. For instance, the cotangent (which is the reciprocal of the tangent) can be computed by executing a |
| FDIVR instruction after the FPTAN instruction. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
| 3-371 |
Operation
| IF ST(0) < 263 |
| THEN |
| C2 ← 0; |
| ST(0) ← fptan(ST(0)); // approximation of tan |
| TOP ← TOP − 1; |
| ST(0) ← 1.0; |
| ELSE (* Source operand is out-of-range *) |
| C2 ← 1; |
| FI; |
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred. Set if result was rounded up; cleared otherwise. |
| C2 | Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0. |
| C0, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow or overflow occurred. |
| #IA | Source operand is an SNaN value, ∞, or unsupported format. |
| #D | Source operand is a denormal value. |
| #U | Result is too small for destination format. |
| #P | Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FPTAN—Partial Tangent |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 FC | FRNDINT | Valid | Valid | Round ST(0) to an integer. |
Description
| Rounds the source value in the ST(0) register to the nearest integral value, depending on the current rounding |
| mode (setting of the RC field of the FPU control word), and stores the result in ST(0). |
| If the source value is ∞, the value is not changed. If the source value is not an integral value, the floating-point |
| inexact-result exception (#P) is generated. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
ST(0) ← RoundToIntegralValue(ST(0));
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA | Source operand is an SNaN value or unsupported format. |
| #D | Source operand is a denormal value. |
| #P | Source operand is not an integral value. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| 3-373 |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| DD /4 | FRSTOR m94/108byte | Valid | Valid | Load FPU state from m94byte or m108byte. |
Description
| Loads the FPU state (operating environment and register stack) from the memory area specified with the source |
| operand. This state data is typically written to the specified memory location by a previous FSAVE/FNSAVE instruc- |
| tion. |
| The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data |
| pointer, and last opcode. Figures 8-9 through 8-12 in the Intel® 64 and IA-32 Architectures Software Developer’s |
| Manual, Volume 1, show the layout in memory of the stored environment, depending on the operating mode of the |
| processor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the |
| real mode layouts are used. The contents of the FPU register stack are stored in the 80 bytes immediately following |
| the operating environment image. |
| The FRSTOR instruction should be executed in the same operating mode as the corresponding FSAVE/FNSAVE |
| instruction. |
| If one or more unmasked exception bits are set in the new FPU status word, a floating-point exception will be |
| generated. To avoid raising exceptions when loading a new operating environment, clear all the exception flags in |
| the FPU status word that is being loaded. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| FPUControlWord ← SRC[FPUControlWord]; |
| FPUStatusWord ← SRC[FPUStatusWord]; |
| FPUTagWord ← SRC[FPUTagWord]; |
| FPUDataPointer ← SRC[FPUDataPointer]; |
| FPUInstructionPointer ← SRC[FPUInstructionPointer]; |
| FPULastInstructionOpcode ← SRC[FPULastInstructionOpcode]; |
| ST(0) ← SRC[ST(0)]; |
| ST(1) ← SRC[ST(1)]; |
| ST(2) ← SRC[ST(2)]; |
| ST(3) ← SRC[ST(3)]; |
| ST(4) ← SRC[ST(4)]; |
| ST(5) ← SRC[ST(5)]; |
| ST(6) ← SRC[ST(6)]; |
| ST(7) ← SRC[ST(7)]; |
FPU Flags Affected
The C0, C1, C2, C3 flags are loaded.
Floating-Point Exceptions
| None; however, this operation might unmask an existing exception that has been detected but not generated, |
| because it was masked. Here, the exception is generated at the completion of the instruction. |
| FRSTOR—Restore x87 FPU State |
Protected Mode Exceptions
| #GP(0) |
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #UD | If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
|
#UD 3-375 |
If the LOCK prefix is used. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| 9B DD /6 | FSAVE m94/108byte | Valid | Valid |
Store FPU state to m94byte or m108byte after checking for pending unmasked floating-point exceptions. Then re-initialize the FPU. |
| DD /6 | FNSAVE* m94/108byte | Valid | Valid |
Store FPU environment to m94byte or m108byte without checking for pending unmasked floating- point exceptions. Then re-initialize the FPU. |
NOTES:
| * | See IA-32 Architecture Compatibility section below. |
Description
| Stores the current FPU state (operating environment and register stack) at the specified destination in memory, |
| and then re-initializes the FPU. The FSAVE instruction checks for and handles pending unmasked floating-point |
| exceptions before storing the FPU state; the FNSAVE instruction does not. |
| The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data |
| pointer, and last opcode. Figures 8-9 through 8-12 in the Intel® 64 and IA-32 Architectures Software Developer’s |
| Manual, Volume 1, show the layout in memory of the stored environment, depending on the operating mode of the |
| processor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the |
| real mode layouts are used. The contents of the FPU register stack are stored in the 80 bytes immediately follow |
| the operating environment image. |
| The saved image reflects the state of the FPU after all floating-point instructions preceding the FSAVE/FNSAVE |
| instruction in the instruction stream have been executed. |
| After the FPU state has been saved, the FPU is reset to the same default values it is set to with the FINIT/FNINIT |
| instructions (see “FINIT/FNINIT—Initialize Floating-Point Unit” in this chapter). |
| The FSAVE/FNSAVE instructions are typically used when the operating system needs to perform a context switch, |
| an exception handler needs to use the FPU, or an application program needs to pass a “clean” FPU to a procedure. |
| The assembler issues two instructions for the FSAVE instruction (an FWAIT instruction followed by an FNSAVE |
| instruction), and the processor executes each of these instructions separately. If an exception is generated for |
| either of these instructions, the save EIP points to the instruction that caused the exception. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
IA-32 Architecture Compatibility
| For Intel math coprocessors and FPUs prior to the Intel Pentium processor, an FWAIT instruction should be |
| executed before attempting to read from the memory image stored with a prior FSAVE/FNSAVE instruction. This |
| FWAIT instruction helps ensure that the storage operation has been completed. |
| When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual |
| circumstances) for an FNSAVE instruction to be interrupted prior to being executed to handle a pending FPU excep- |
| tion. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel® |
| 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances. An |
| FNSAVE instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000 |
| processor. |
| FSAVE/FNSAVE—Store x87 FPU State |
Operation
| (* Save FPU State and Registers *) |
| DEST[FPUControlWord] ← FPUControlWord; |
| DEST[FPUStatusWord] ← FPUStatusWord; |
| DEST[FPUTagWord] ← FPUTagWord; |
| DEST[FPUDataPointer] ← FPUDataPointer; |
| DEST[FPUInstructionPointer] ← FPUInstructionPointer; |
| DEST[FPULastInstructionOpcode] ← FPULastInstructionOpcode; |
| DEST[ST(0)] ← ST(0); |
| DEST[ST(1)] ← ST(1); |
| DEST[ST(2)] ← ST(2); |
| DEST[ST(3)] ← ST(3); |
| DEST[ST(4)]← ST(4); |
| DEST[ST(5)] ← ST(5); |
| DEST[ST(6)] ← ST(6); |
| DEST[ST(7)] ← ST(7); |
| (* Initialize FPU *) |
| FPUControlWord ← 037FH; |
| FPUStatusWord ← 0; |
| FPUTagWord ← FFFFH; |
| FPUDataPointer ← 0; |
| FPUInstructionPointer ← 0; |
| FPULastInstructionOpcode ← 0; |
FPU Flags Affected
The C0, C1, C2, and C3 flags are saved and then cleared.
Floating-Point Exceptions
None.
Protected Mode Exceptions
| #GP(0) |
If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
|
#UD 3-377 |
If the LOCK prefix is used. |
Virtual-8086 Mode Exceptions
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used. |
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #PF(fault-code) | If a page fault occurs. |
|
#AC(0) FSAVE/FNSAVE—Store x87 FPU State |
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 FD | FSCALE | Valid | Valid | Scale ST(0) by ST(1). |
Description
| Truncates the value in the source operand (toward 0) to an integral value and adds that value to the exponent of |
| the destination operand. The destination and source operands are floating-point values located in registers ST(0) |
| and ST(1), respectively. This instruction provides rapid multiplication or division by integral powers of 2. The |
| following table shows the results obtained when scaling various classes of numbers, assuming that neither over- |
| flow nor underflow occurs. |
Table 3-34. FSCALE Results
| ST(1) | ST(1) | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| − ∞ | − F | − 0 | + 0 | + F | + ∞ | NaN | |||||||||||
| − ∞ | NaN | − ∞ | − ∞ | − ∞ | − ∞ | − ∞ | NaN | ||||||||||
| ST(0) | − F | − 0 | − F | − F | − F | − F | − ∞ | NaN | |||||||||
| − 0 | − 0 | − 0 | − 0 | − 0 | − 0 | NaN | NaN | ||||||||||
| + 0 | + 0 | + 0 | + 0 | + 0 | + 0 | NaN | NaN | ||||||||||
| + F | + 0 | + F | + F | + F | + F | + ∞ | NaN | ||||||||||
| + ∞ | NaN | + ∞ | + ∞ | + ∞ | + ∞ | + ∞ | NaN | ||||||||||
| NaN | NaN | NaN | NaN | NaN | NaN | NaN | NaN |
NOTES:
| F Means finite floating-point value. |
| In most cases, only the exponent is changed and the mantissa (significand) remains unchanged. However, when |
| the value being scaled in ST(0) is a denormal value, the mantissa is also changed and the result may turn out to be |
| a normalized number. Similarly, if overflow or underflow results from a scale operation, the resulting mantissa will |
| differ from the source’s mantissa. |
| The FSCALE instruction can also be used to reverse the action of the FXTRACT instruction, as shown in the following |
| example: |
| FXTRACT; |
| FSCALE; |
| FSTP ST(1); |
| In this example, the FXTRACT instruction extracts the significand and exponent from the value in ST(0) and stores |
| them in ST(0) and ST(1) respectively. The FSCALE then scales the significand in ST(0) by the exponent in ST(1), |
| recreating the original value before the FXTRACT operation was performed. The FSTP ST(1) instruction overwrites |
| the exponent (extracted by the FXTRACT instruction) with the recreated value, which returns the stack to its orig- |
| inal state with only one register [ST(0)] occupied. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
ST(0) ← ST(0) ∗ 2RoundTowardZero(ST(1));
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. |
|
C0, C2, C3 3-379 |
Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA | Source operand is an SNaN value or unsupported format. |
| #D | Source operand is a denormal value. |
| #U | Result is too small for destination format. |
| #O | Result is too large for destination format. |
| #P | Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FSCALE—Scale |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 FE | FSIN | Valid | Valid | Replace ST(0) with the approximate of its sine. |
Description
| Computes an approximation of the sine of the source operand in register ST(0) and stores the result in ST(0). The |
| source operand must be given in radians and must be within the range −263 to +263. The following table shows the |
| results obtained when taking the sine of various classes of numbers, assuming that underflow does not occur. |
Table 3-35. FSIN Results
| SRC (ST(0)) | DEST (ST(0)) |
|---|---|
| − ∞ | * |
| − F | − 1 to + 1 |
| − 0 | −0 |
| + 0 | + 0 |
| + F | − 1 to +1 |
| + ∞ | * |
| NaN | NaN |
NOTES:
| F Means finite floating-point value. |
| Indicates floating-point invalid-arithmetic-operand (#IA) exception. |
| If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in |
| register ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of |
| range. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range − |
| 263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2π. |
| However, even within the range -263 to +263, inaccurate results can occur because the finite approximation of π |
| used internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply |
| FSIN only to arguments reduced accurately in software, to a value smaller in absolute value than 3π/4. See the |
| sections titled “Approximation of Pi” and “Transcendental Instruction Accuracy” in Chapter 8 of the Intel® 64 and |
| IA-32 Architectures Software Developer’s Manual, Volume 1, for a discussion of the proper value to use for π in |
| performing such reductions. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
| IF -263 < ST(0) < 263 |
| THEN |
| C2 ← 0; |
| ST(0) ← fsin(ST(0)); // approximation of the mathematical sin function |
| ELSE (* Source operand out of range *) |
| C2 ← 1; |
| FI; |
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. |
| C2 | Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0. |
|
C0, C3 3-381 |
Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA | Source operand is an SNaN value, ∞, or unsupported format. |
| #D | Source operand is a denormal value. |
| #P | Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FSIN—Sine |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 FB | FSINCOS | Valid | Valid |
Compute the sine and cosine of ST(0); replace ST(0) with the approximate sine, and push the approximate cosine onto the register stack. |
Description
| Computes both the approximate sine and the cosine of the source operand in register ST(0), stores the sine in |
| ST(0), and pushes the cosine onto the top of the FPU register stack. (This instruction is faster than executing the |
| FSIN and FCOS instructions in succession.) |
| The source operand must be given in radians and must be within the range −263 to +263. The following table shows |
| the results obtained when taking the sine and cosine of various classes of numbers, assuming that underflow does |
| not occur. |
Table 3-36. FSINCOS Results
| SRC | DEST | |
|---|---|---|
| ST(0) | ST(1) Cosine | ST(0) Sine |
| − ∞ | * | * |
| − F | − 1 to + 1 | − 1 to + 1 |
| − 0 | + 1 | − 0 |
| + 0 | + 1 | + 0 |
| + F | − 1 to + 1 | − 1 to + 1 |
| + ∞ | * | * |
| NaN | NaN | NaN |
NOTES:
| F Means finite floating-point value. |
| Indicates floating-point invalid-arithmetic-operand (#IA) exception. |
| If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in |
| register ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of |
| range. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range − |
| 263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2π. |
| However, even within the range -263 to +263, inaccurate results can occur because the finite approximation of π |
| used internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply |
| FSINCOS only to arguments reduced accurately in software, to a value smaller in absolute value than 3π/8. See the |
| sections titled “Approximation of Pi” and “Transcendental Instruction Accuracy” in Chapter 8 of the Intel® 64 and |
| IA-32 Architectures Software Developer’s Manual, Volume 1, for a discussion of the proper value to use for π in |
| performing such reductions. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
| 3-383 |
Operation
| IF ST(0) < 263 |
| THEN |
| C2 ← 0; |
| TEMP ← fcos(ST(0)); // approximation of cosine |
| ST(0) ← fsin(ST(0)); // approximation of sine |
| TOP ← TOP − 1; |
| ST(0) ← TEMP; |
| ELSE (* Source operand out of range *) |
| C2 ← 1; |
| FI; |
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred; set to 1 of stack overflow occurs. Set if result was rounded up; cleared otherwise. |
| C2 | Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0. |
| C0, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow or overflow occurred. |
| #IA | Source operand is an SNaN value, ∞, or unsupported format. |
| #D | Source operand is a denormal value. |
| #U | Result is too small for destination format. |
| #P | Value cannot be represented exactly in destination format. |
Protected Mode Exceptions
| #NM | CR0.EM[bit 2] or CR0.TS[bit 3] = 1. |
| #MF | If there is a pending x87 FPU exception. |
| #UD | If the LOCK prefix is used. |
Real-Address Mode Exceptions
Same exceptions as in protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
| Same exceptions as in protected mode. |
| FSINCOS—Sine and Cosine |
| Opcode | Instruction | 64-Bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|
| D9 FA | FSQRT | Valid | Valid | Computes square root of ST(0) and stores the result in ST(0). |
Description
| Computes the square root of the source value in the ST(0) register and stores the result in ST(0). |
| The following table shows the results obtained when taking the square root of various classes of numbers, |
| assuming that neither overflow nor underflow occurs. |
Table 3-37. FSQRT Results
| SRC (ST(0)) | DEST (ST(0)) |
|---|---|
| − ∞ | * |
| − F | * |
| − 0 | − 0 |
| + 0 | + 0 |
| + F | + F |
| + ∞ | + ∞ |
| NaN | NaN |
NOTES:
| F Means finite floating-point value. |
| Indicates floating-point invalid-arithmetic-operand (#IA) exception. |
| This instruction’s operation is the same in non-64-bit modes and 64-bit mode. |
Operation
ST(0) ← SquareRoot(ST(0));
FPU Flags Affected
| C1 |
Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. |
| C0, C2, C3 | Undefined. |
Floating-Point Exceptions
| #IS | Stack underflow occurred. |
| #IA |
Source operand is an SNaN value or unsupported format. Source operand is a negative value (except for −0). |
| #D | Source operand is a denormal value. |