SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller. More...
Classes | |
| struct | PwmCh_num |
| PwmCh_num hardware registers. More... | |
| struct | PwmCmp |
| PwmCmp hardware registers. More... | |
| struct | Pwm |
Macros | |
| #define | PWMCMP_NUMBER 8 |
| Pwm hardware registers. More... | |
| #define | PWMCH_NUM_NUMBER 4 |
| #define | PWM_CLK_DIVA_Pos 0 |
| #define | PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) |
| (PWM_CLK) CLKA Divide Factor More... | |
| #define | PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) |
| #define | PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) |
| (PWM_CLK) CLKA clock is turned off More... | |
| #define | PWM_CLK_DIVA_PREA (0x1u << 0) |
| (PWM_CLK) CLKA clock is clock selected by PREA More... | |
| #define | PWM_CLK_PREA_Pos 8 |
| #define | PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) |
| (PWM_CLK) CLKA Source Clock Selection More... | |
| #define | PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) |
| #define | PWM_CLK_PREA_CLK (0x0u << 8) |
| (PWM_CLK) Peripheral clock More... | |
| #define | PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) |
| (PWM_CLK) Peripheral clock/2 More... | |
| #define | PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) |
| (PWM_CLK) Peripheral clock/4 More... | |
| #define | PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) |
| (PWM_CLK) Peripheral clock/8 More... | |
| #define | PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) |
| (PWM_CLK) Peripheral clock/16 More... | |
| #define | PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) |
| (PWM_CLK) Peripheral clock/32 More... | |
| #define | PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) |
| (PWM_CLK) Peripheral clock/64 More... | |
| #define | PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) |
| (PWM_CLK) Peripheral clock/128 More... | |
| #define | PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) |
| (PWM_CLK) Peripheral clock/256 More... | |
| #define | PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) |
| (PWM_CLK) Peripheral clock/512 More... | |
| #define | PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) |
| (PWM_CLK) Peripheral clock/1024 More... | |
| #define | PWM_CLK_DIVB_Pos 16 |
| #define | PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) |
| (PWM_CLK) CLKB Divide Factor More... | |
| #define | PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) |
| #define | PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) |
| (PWM_CLK) CLKB clock is turned off More... | |
| #define | PWM_CLK_DIVB_PREB (0x1u << 16) |
| (PWM_CLK) CLKB clock is clock selected by PREB More... | |
| #define | PWM_CLK_PREB_Pos 24 |
| #define | PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) |
| (PWM_CLK) CLKB Source Clock Selection More... | |
| #define | PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) |
| #define | PWM_CLK_PREB_CLK (0x0u << 24) |
| (PWM_CLK) Peripheral clock More... | |
| #define | PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) |
| (PWM_CLK) Peripheral clock/2 More... | |
| #define | PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) |
| (PWM_CLK) Peripheral clock/4 More... | |
| #define | PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) |
| (PWM_CLK) Peripheral clock/8 More... | |
| #define | PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) |
| (PWM_CLK) Peripheral clock/16 More... | |
| #define | PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) |
| (PWM_CLK) Peripheral clock/32 More... | |
| #define | PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) |
| (PWM_CLK) Peripheral clock/64 More... | |
| #define | PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) |
| (PWM_CLK) Peripheral clock/128 More... | |
| #define | PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) |
| (PWM_CLK) Peripheral clock/256 More... | |
| #define | PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) |
| (PWM_CLK) Peripheral clock/512 More... | |
| #define | PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) |
| (PWM_CLK) Peripheral clock/1024 More... | |
| #define | PWM_ENA_CHID0 (0x1u << 0) |
| (PWM_ENA) Channel ID More... | |
| #define | PWM_ENA_CHID1 (0x1u << 1) |
| (PWM_ENA) Channel ID More... | |
| #define | PWM_ENA_CHID2 (0x1u << 2) |
| (PWM_ENA) Channel ID More... | |
| #define | PWM_ENA_CHID3 (0x1u << 3) |
| (PWM_ENA) Channel ID More... | |
| #define | PWM_DIS_CHID0 (0x1u << 0) |
| (PWM_DIS) Channel ID More... | |
| #define | PWM_DIS_CHID1 (0x1u << 1) |
| (PWM_DIS) Channel ID More... | |
| #define | PWM_DIS_CHID2 (0x1u << 2) |
| (PWM_DIS) Channel ID More... | |
| #define | PWM_DIS_CHID3 (0x1u << 3) |
| (PWM_DIS) Channel ID More... | |
| #define | PWM_SR_CHID0 (0x1u << 0) |
| (PWM_SR) Channel ID More... | |
| #define | PWM_SR_CHID1 (0x1u << 1) |
| (PWM_SR) Channel ID More... | |
| #define | PWM_SR_CHID2 (0x1u << 2) |
| (PWM_SR) Channel ID More... | |
| #define | PWM_SR_CHID3 (0x1u << 3) |
| (PWM_SR) Channel ID More... | |
| #define | PWM_IER1_CHID0 (0x1u << 0) |
| (PWM_IER1) Counter Event on Channel 0 Interrupt Enable More... | |
| #define | PWM_IER1_CHID1 (0x1u << 1) |
| (PWM_IER1) Counter Event on Channel 1 Interrupt Enable More... | |
| #define | PWM_IER1_CHID2 (0x1u << 2) |
| (PWM_IER1) Counter Event on Channel 2 Interrupt Enable More... | |
| #define | PWM_IER1_CHID3 (0x1u << 3) |
| (PWM_IER1) Counter Event on Channel 3 Interrupt Enable More... | |
| #define | PWM_IER1_FCHID0 (0x1u << 16) |
| (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable More... | |
| #define | PWM_IER1_FCHID1 (0x1u << 17) |
| (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable More... | |
| #define | PWM_IER1_FCHID2 (0x1u << 18) |
| (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable More... | |
| #define | PWM_IER1_FCHID3 (0x1u << 19) |
| (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable More... | |
| #define | PWM_IDR1_CHID0 (0x1u << 0) |
| (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable More... | |
| #define | PWM_IDR1_CHID1 (0x1u << 1) |
| (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable More... | |
| #define | PWM_IDR1_CHID2 (0x1u << 2) |
| (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable More... | |
| #define | PWM_IDR1_CHID3 (0x1u << 3) |
| (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable More... | |
| #define | PWM_IDR1_FCHID0 (0x1u << 16) |
| (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable More... | |
| #define | PWM_IDR1_FCHID1 (0x1u << 17) |
| (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable More... | |
| #define | PWM_IDR1_FCHID2 (0x1u << 18) |
| (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable More... | |
| #define | PWM_IDR1_FCHID3 (0x1u << 19) |
| (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable More... | |
| #define | PWM_IMR1_CHID0 (0x1u << 0) |
| (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask More... | |
| #define | PWM_IMR1_CHID1 (0x1u << 1) |
| (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask More... | |
| #define | PWM_IMR1_CHID2 (0x1u << 2) |
| (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask More... | |
| #define | PWM_IMR1_CHID3 (0x1u << 3) |
| (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask More... | |
| #define | PWM_IMR1_FCHID0 (0x1u << 16) |
| (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask More... | |
| #define | PWM_IMR1_FCHID1 (0x1u << 17) |
| (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask More... | |
| #define | PWM_IMR1_FCHID2 (0x1u << 18) |
| (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask More... | |
| #define | PWM_IMR1_FCHID3 (0x1u << 19) |
| (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask More... | |
| #define | PWM_ISR1_CHID0 (0x1u << 0) |
| (PWM_ISR1) Counter Event on Channel 0 More... | |
| #define | PWM_ISR1_CHID1 (0x1u << 1) |
| (PWM_ISR1) Counter Event on Channel 1 More... | |
| #define | PWM_ISR1_CHID2 (0x1u << 2) |
| (PWM_ISR1) Counter Event on Channel 2 More... | |
| #define | PWM_ISR1_CHID3 (0x1u << 3) |
| (PWM_ISR1) Counter Event on Channel 3 More... | |
| #define | PWM_ISR1_FCHID0 (0x1u << 16) |
| (PWM_ISR1) Fault Protection Trigger on Channel 0 More... | |
| #define | PWM_ISR1_FCHID1 (0x1u << 17) |
| (PWM_ISR1) Fault Protection Trigger on Channel 1 More... | |
| #define | PWM_ISR1_FCHID2 (0x1u << 18) |
| (PWM_ISR1) Fault Protection Trigger on Channel 2 More... | |
| #define | PWM_ISR1_FCHID3 (0x1u << 19) |
| (PWM_ISR1) Fault Protection Trigger on Channel 3 More... | |
| #define | PWM_SCM_SYNC0 (0x1u << 0) |
| (PWM_SCM) Synchronous Channel 0 More... | |
| #define | PWM_SCM_SYNC1 (0x1u << 1) |
| (PWM_SCM) Synchronous Channel 1 More... | |
| #define | PWM_SCM_SYNC2 (0x1u << 2) |
| (PWM_SCM) Synchronous Channel 2 More... | |
| #define | PWM_SCM_SYNC3 (0x1u << 3) |
| (PWM_SCM) Synchronous Channel 3 More... | |
| #define | PWM_SCM_UPDM_Pos 16 |
| #define | PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) |
| (PWM_SCM) Synchronous Channels Update Mode More... | |
| #define | PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) |
| #define | PWM_SCM_UPDM_MODE0 (0x0u << 16) |
| (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels More... | |
| #define | PWM_SCM_UPDM_MODE1 (0x1u << 16) |
| (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels More... | |
| #define | PWM_SCM_UPDM_MODE2 (0x2u << 16) |
| (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels More... | |
| #define | PWM_SCM_PTRM (0x1u << 20) |
| (PWM_SCM) DMA Controller Transfer Request Mode More... | |
| #define | PWM_SCM_PTRCS_Pos 21 |
| #define | PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) |
| (PWM_SCM) DMA Controller Transfer Request Comparison Selection More... | |
| #define | PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) |
| #define | PWM_DMAR_DMADUTY_Pos 0 |
| #define | PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) |
| (PWM_DMAR) Duty-Cycle Holding Register for DMA Access More... | |
| #define | PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) |
| #define | PWM_SCUC_UPDULOCK (0x1u << 0) |
| (PWM_SCUC) Synchronous Channels Update Unlock More... | |
| #define | PWM_SCUP_UPR_Pos 0 |
| #define | PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) |
| (PWM_SCUP) Update Period More... | |
| #define | PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) |
| #define | PWM_SCUP_UPRCNT_Pos 4 |
| #define | PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) |
| (PWM_SCUP) Update Period Counter More... | |
| #define | PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) |
| #define | PWM_SCUPUPD_UPRUPD_Pos 0 |
| #define | PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) |
| (PWM_SCUPUPD) Update Period Update More... | |
| #define | PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) |
| #define | PWM_IER2_WRDY (0x1u << 0) |
| (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable More... | |
| #define | PWM_IER2_UNRE (0x1u << 3) |
| (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable More... | |
| #define | PWM_IER2_CMPM0 (0x1u << 8) |
| (PWM_IER2) Comparison 0 Match Interrupt Enable More... | |
| #define | PWM_IER2_CMPM1 (0x1u << 9) |
| (PWM_IER2) Comparison 1 Match Interrupt Enable More... | |
| #define | PWM_IER2_CMPM2 (0x1u << 10) |
| (PWM_IER2) Comparison 2 Match Interrupt Enable More... | |
| #define | PWM_IER2_CMPM3 (0x1u << 11) |
| (PWM_IER2) Comparison 3 Match Interrupt Enable More... | |
| #define | PWM_IER2_CMPM4 (0x1u << 12) |
| (PWM_IER2) Comparison 4 Match Interrupt Enable More... | |
| #define | PWM_IER2_CMPM5 (0x1u << 13) |
| (PWM_IER2) Comparison 5 Match Interrupt Enable More... | |
| #define | PWM_IER2_CMPM6 (0x1u << 14) |
| (PWM_IER2) Comparison 6 Match Interrupt Enable More... | |
| #define | PWM_IER2_CMPM7 (0x1u << 15) |
| (PWM_IER2) Comparison 7 Match Interrupt Enable More... | |
| #define | PWM_IER2_CMPU0 (0x1u << 16) |
| (PWM_IER2) Comparison 0 Update Interrupt Enable More... | |
| #define | PWM_IER2_CMPU1 (0x1u << 17) |
| (PWM_IER2) Comparison 1 Update Interrupt Enable More... | |
| #define | PWM_IER2_CMPU2 (0x1u << 18) |
| (PWM_IER2) Comparison 2 Update Interrupt Enable More... | |
| #define | PWM_IER2_CMPU3 (0x1u << 19) |
| (PWM_IER2) Comparison 3 Update Interrupt Enable More... | |
| #define | PWM_IER2_CMPU4 (0x1u << 20) |
| (PWM_IER2) Comparison 4 Update Interrupt Enable More... | |
| #define | PWM_IER2_CMPU5 (0x1u << 21) |
| (PWM_IER2) Comparison 5 Update Interrupt Enable More... | |
| #define | PWM_IER2_CMPU6 (0x1u << 22) |
| (PWM_IER2) Comparison 6 Update Interrupt Enable More... | |
| #define | PWM_IER2_CMPU7 (0x1u << 23) |
| (PWM_IER2) Comparison 7 Update Interrupt Enable More... | |
| #define | PWM_IDR2_WRDY (0x1u << 0) |
| (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable More... | |
| #define | PWM_IDR2_UNRE (0x1u << 3) |
| (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable More... | |
| #define | PWM_IDR2_CMPM0 (0x1u << 8) |
| (PWM_IDR2) Comparison 0 Match Interrupt Disable More... | |
| #define | PWM_IDR2_CMPM1 (0x1u << 9) |
| (PWM_IDR2) Comparison 1 Match Interrupt Disable More... | |
| #define | PWM_IDR2_CMPM2 (0x1u << 10) |
| (PWM_IDR2) Comparison 2 Match Interrupt Disable More... | |
| #define | PWM_IDR2_CMPM3 (0x1u << 11) |
| (PWM_IDR2) Comparison 3 Match Interrupt Disable More... | |
| #define | PWM_IDR2_CMPM4 (0x1u << 12) |
| (PWM_IDR2) Comparison 4 Match Interrupt Disable More... | |
| #define | PWM_IDR2_CMPM5 (0x1u << 13) |
| (PWM_IDR2) Comparison 5 Match Interrupt Disable More... | |
| #define | PWM_IDR2_CMPM6 (0x1u << 14) |
| (PWM_IDR2) Comparison 6 Match Interrupt Disable More... | |
| #define | PWM_IDR2_CMPM7 (0x1u << 15) |
| (PWM_IDR2) Comparison 7 Match Interrupt Disable More... | |
| #define | PWM_IDR2_CMPU0 (0x1u << 16) |
| (PWM_IDR2) Comparison 0 Update Interrupt Disable More... | |
| #define | PWM_IDR2_CMPU1 (0x1u << 17) |
| (PWM_IDR2) Comparison 1 Update Interrupt Disable More... | |
| #define | PWM_IDR2_CMPU2 (0x1u << 18) |
| (PWM_IDR2) Comparison 2 Update Interrupt Disable More... | |
| #define | PWM_IDR2_CMPU3 (0x1u << 19) |
| (PWM_IDR2) Comparison 3 Update Interrupt Disable More... | |
| #define | PWM_IDR2_CMPU4 (0x1u << 20) |
| (PWM_IDR2) Comparison 4 Update Interrupt Disable More... | |
| #define | PWM_IDR2_CMPU5 (0x1u << 21) |
| (PWM_IDR2) Comparison 5 Update Interrupt Disable More... | |
| #define | PWM_IDR2_CMPU6 (0x1u << 22) |
| (PWM_IDR2) Comparison 6 Update Interrupt Disable More... | |
| #define | PWM_IDR2_CMPU7 (0x1u << 23) |
| (PWM_IDR2) Comparison 7 Update Interrupt Disable More... | |
| #define | PWM_IMR2_WRDY (0x1u << 0) |
| (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask More... | |
| #define | PWM_IMR2_UNRE (0x1u << 3) |
| (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask More... | |
| #define | PWM_IMR2_CMPM0 (0x1u << 8) |
| (PWM_IMR2) Comparison 0 Match Interrupt Mask More... | |
| #define | PWM_IMR2_CMPM1 (0x1u << 9) |
| (PWM_IMR2) Comparison 1 Match Interrupt Mask More... | |
| #define | PWM_IMR2_CMPM2 (0x1u << 10) |
| (PWM_IMR2) Comparison 2 Match Interrupt Mask More... | |
| #define | PWM_IMR2_CMPM3 (0x1u << 11) |
| (PWM_IMR2) Comparison 3 Match Interrupt Mask More... | |
| #define | PWM_IMR2_CMPM4 (0x1u << 12) |
| (PWM_IMR2) Comparison 4 Match Interrupt Mask More... | |
| #define | PWM_IMR2_CMPM5 (0x1u << 13) |
| (PWM_IMR2) Comparison 5 Match Interrupt Mask More... | |
| #define | PWM_IMR2_CMPM6 (0x1u << 14) |
| (PWM_IMR2) Comparison 6 Match Interrupt Mask More... | |
| #define | PWM_IMR2_CMPM7 (0x1u << 15) |
| (PWM_IMR2) Comparison 7 Match Interrupt Mask More... | |
| #define | PWM_IMR2_CMPU0 (0x1u << 16) |
| (PWM_IMR2) Comparison 0 Update Interrupt Mask More... | |
| #define | PWM_IMR2_CMPU1 (0x1u << 17) |
| (PWM_IMR2) Comparison 1 Update Interrupt Mask More... | |
| #define | PWM_IMR2_CMPU2 (0x1u << 18) |
| (PWM_IMR2) Comparison 2 Update Interrupt Mask More... | |
| #define | PWM_IMR2_CMPU3 (0x1u << 19) |
| (PWM_IMR2) Comparison 3 Update Interrupt Mask More... | |
| #define | PWM_IMR2_CMPU4 (0x1u << 20) |
| (PWM_IMR2) Comparison 4 Update Interrupt Mask More... | |
| #define | PWM_IMR2_CMPU5 (0x1u << 21) |
| (PWM_IMR2) Comparison 5 Update Interrupt Mask More... | |
| #define | PWM_IMR2_CMPU6 (0x1u << 22) |
| (PWM_IMR2) Comparison 6 Update Interrupt Mask More... | |
| #define | PWM_IMR2_CMPU7 (0x1u << 23) |
| (PWM_IMR2) Comparison 7 Update Interrupt Mask More... | |
| #define | PWM_ISR2_WRDY (0x1u << 0) |
| (PWM_ISR2) Write Ready for Synchronous Channels Update More... | |
| #define | PWM_ISR2_UNRE (0x1u << 3) |
| (PWM_ISR2) Synchronous Channels Update Underrun Error More... | |
| #define | PWM_ISR2_CMPM0 (0x1u << 8) |
| (PWM_ISR2) Comparison 0 Match More... | |
| #define | PWM_ISR2_CMPM1 (0x1u << 9) |
| (PWM_ISR2) Comparison 1 Match More... | |
| #define | PWM_ISR2_CMPM2 (0x1u << 10) |
| (PWM_ISR2) Comparison 2 Match More... | |
| #define | PWM_ISR2_CMPM3 (0x1u << 11) |
| (PWM_ISR2) Comparison 3 Match More... | |
| #define | PWM_ISR2_CMPM4 (0x1u << 12) |
| (PWM_ISR2) Comparison 4 Match More... | |
| #define | PWM_ISR2_CMPM5 (0x1u << 13) |
| (PWM_ISR2) Comparison 5 Match More... | |
| #define | PWM_ISR2_CMPM6 (0x1u << 14) |
| (PWM_ISR2) Comparison 6 Match More... | |
| #define | PWM_ISR2_CMPM7 (0x1u << 15) |
| (PWM_ISR2) Comparison 7 Match More... | |
| #define | PWM_ISR2_CMPU0 (0x1u << 16) |
| (PWM_ISR2) Comparison 0 Update More... | |
| #define | PWM_ISR2_CMPU1 (0x1u << 17) |
| (PWM_ISR2) Comparison 1 Update More... | |
| #define | PWM_ISR2_CMPU2 (0x1u << 18) |
| (PWM_ISR2) Comparison 2 Update More... | |
| #define | PWM_ISR2_CMPU3 (0x1u << 19) |
| (PWM_ISR2) Comparison 3 Update More... | |
| #define | PWM_ISR2_CMPU4 (0x1u << 20) |
| (PWM_ISR2) Comparison 4 Update More... | |
| #define | PWM_ISR2_CMPU5 (0x1u << 21) |
| (PWM_ISR2) Comparison 5 Update More... | |
| #define | PWM_ISR2_CMPU6 (0x1u << 22) |
| (PWM_ISR2) Comparison 6 Update More... | |
| #define | PWM_ISR2_CMPU7 (0x1u << 23) |
| (PWM_ISR2) Comparison 7 Update More... | |
| #define | PWM_OOV_OOVH0 (0x1u << 0) |
| (PWM_OOV) Output Override Value for PWMH output of the channel 0 More... | |
| #define | PWM_OOV_OOVH1 (0x1u << 1) |
| (PWM_OOV) Output Override Value for PWMH output of the channel 1 More... | |
| #define | PWM_OOV_OOVH2 (0x1u << 2) |
| (PWM_OOV) Output Override Value for PWMH output of the channel 2 More... | |
| #define | PWM_OOV_OOVH3 (0x1u << 3) |
| (PWM_OOV) Output Override Value for PWMH output of the channel 3 More... | |
| #define | PWM_OOV_OOVL0 (0x1u << 16) |
| (PWM_OOV) Output Override Value for PWML output of the channel 0 More... | |
| #define | PWM_OOV_OOVL1 (0x1u << 17) |
| (PWM_OOV) Output Override Value for PWML output of the channel 1 More... | |
| #define | PWM_OOV_OOVL2 (0x1u << 18) |
| (PWM_OOV) Output Override Value for PWML output of the channel 2 More... | |
| #define | PWM_OOV_OOVL3 (0x1u << 19) |
| (PWM_OOV) Output Override Value for PWML output of the channel 3 More... | |
| #define | PWM_OS_OSH0 (0x1u << 0) |
| (PWM_OS) Output Selection for PWMH output of the channel 0 More... | |
| #define | PWM_OS_OSH1 (0x1u << 1) |
| (PWM_OS) Output Selection for PWMH output of the channel 1 More... | |
| #define | PWM_OS_OSH2 (0x1u << 2) |
| (PWM_OS) Output Selection for PWMH output of the channel 2 More... | |
| #define | PWM_OS_OSH3 (0x1u << 3) |
| (PWM_OS) Output Selection for PWMH output of the channel 3 More... | |
| #define | PWM_OS_OSL0 (0x1u << 16) |
| (PWM_OS) Output Selection for PWML output of the channel 0 More... | |
| #define | PWM_OS_OSL1 (0x1u << 17) |
| (PWM_OS) Output Selection for PWML output of the channel 1 More... | |
| #define | PWM_OS_OSL2 (0x1u << 18) |
| (PWM_OS) Output Selection for PWML output of the channel 2 More... | |
| #define | PWM_OS_OSL3 (0x1u << 19) |
| (PWM_OS) Output Selection for PWML output of the channel 3 More... | |
| #define | PWM_OSS_OSSH0 (0x1u << 0) |
| (PWM_OSS) Output Selection Set for PWMH output of the channel 0 More... | |
| #define | PWM_OSS_OSSH1 (0x1u << 1) |
| (PWM_OSS) Output Selection Set for PWMH output of the channel 1 More... | |
| #define | PWM_OSS_OSSH2 (0x1u << 2) |
| (PWM_OSS) Output Selection Set for PWMH output of the channel 2 More... | |
| #define | PWM_OSS_OSSH3 (0x1u << 3) |
| (PWM_OSS) Output Selection Set for PWMH output of the channel 3 More... | |
| #define | PWM_OSS_OSSL0 (0x1u << 16) |
| (PWM_OSS) Output Selection Set for PWML output of the channel 0 More... | |
| #define | PWM_OSS_OSSL1 (0x1u << 17) |
| (PWM_OSS) Output Selection Set for PWML output of the channel 1 More... | |
| #define | PWM_OSS_OSSL2 (0x1u << 18) |
| (PWM_OSS) Output Selection Set for PWML output of the channel 2 More... | |
| #define | PWM_OSS_OSSL3 (0x1u << 19) |
| (PWM_OSS) Output Selection Set for PWML output of the channel 3 More... | |
| #define | PWM_OSC_OSCH0 (0x1u << 0) |
| (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 More... | |
| #define | PWM_OSC_OSCH1 (0x1u << 1) |
| (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 More... | |
| #define | PWM_OSC_OSCH2 (0x1u << 2) |
| (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 More... | |
| #define | PWM_OSC_OSCH3 (0x1u << 3) |
| (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 More... | |
| #define | PWM_OSC_OSCL0 (0x1u << 16) |
| (PWM_OSC) Output Selection Clear for PWML output of the channel 0 More... | |
| #define | PWM_OSC_OSCL1 (0x1u << 17) |
| (PWM_OSC) Output Selection Clear for PWML output of the channel 1 More... | |
| #define | PWM_OSC_OSCL2 (0x1u << 18) |
| (PWM_OSC) Output Selection Clear for PWML output of the channel 2 More... | |
| #define | PWM_OSC_OSCL3 (0x1u << 19) |
| (PWM_OSC) Output Selection Clear for PWML output of the channel 3 More... | |
| #define | PWM_OSSUPD_OSSUPH0 (0x1u << 0) |
| (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 More... | |
| #define | PWM_OSSUPD_OSSUPH1 (0x1u << 1) |
| (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 More... | |
| #define | PWM_OSSUPD_OSSUPH2 (0x1u << 2) |
| (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 More... | |
| #define | PWM_OSSUPD_OSSUPH3 (0x1u << 3) |
| (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 More... | |
| #define | PWM_OSSUPD_OSSUPL0 (0x1u << 16) |
| (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 More... | |
| #define | PWM_OSSUPD_OSSUPL1 (0x1u << 17) |
| (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 More... | |
| #define | PWM_OSSUPD_OSSUPL2 (0x1u << 18) |
| (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 More... | |
| #define | PWM_OSSUPD_OSSUPL3 (0x1u << 19) |
| (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 More... | |
| #define | PWM_OSCUPD_OSCUPH0 (0x1u << 0) |
| (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 More... | |
| #define | PWM_OSCUPD_OSCUPH1 (0x1u << 1) |
| (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 More... | |
| #define | PWM_OSCUPD_OSCUPH2 (0x1u << 2) |
| (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 More... | |
| #define | PWM_OSCUPD_OSCUPH3 (0x1u << 3) |
| (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 More... | |
| #define | PWM_OSCUPD_OSCUPL0 (0x1u << 16) |
| (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 More... | |
| #define | PWM_OSCUPD_OSCUPL1 (0x1u << 17) |
| (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 More... | |
| #define | PWM_OSCUPD_OSCUPL2 (0x1u << 18) |
| (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 More... | |
| #define | PWM_OSCUPD_OSCUPL3 (0x1u << 19) |
| (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 More... | |
| #define | PWM_FMR_FPOL_Pos 0 |
| #define | PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) |
| (PWM_FMR) Fault Polarity More... | |
| #define | PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) |
| #define | PWM_FMR_FMOD_Pos 8 |
| #define | PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) |
| (PWM_FMR) Fault Activation Mode More... | |
| #define | PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) |
| #define | PWM_FMR_FFIL_Pos 16 |
| #define | PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) |
| (PWM_FMR) Fault Filtering More... | |
| #define | PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) |
| #define | PWM_FSR_FIV_Pos 0 |
| #define | PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) |
| (PWM_FSR) Fault Input Value More... | |
| #define | PWM_FSR_FS_Pos 8 |
| #define | PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) |
| (PWM_FSR) Fault Status More... | |
| #define | PWM_FCR_FCLR_Pos 0 |
| #define | PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) |
| (PWM_FCR) Fault Clear More... | |
| #define | PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) |
| #define | PWM_FPV1_FPVH0 (0x1u << 0) |
| (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 More... | |
| #define | PWM_FPV1_FPVH1 (0x1u << 1) |
| (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 More... | |
| #define | PWM_FPV1_FPVH2 (0x1u << 2) |
| (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 More... | |
| #define | PWM_FPV1_FPVH3 (0x1u << 3) |
| (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 More... | |
| #define | PWM_FPV1_FPVL0 (0x1u << 16) |
| (PWM_FPV1) Fault Protection Value for PWML output on channel 0 More... | |
| #define | PWM_FPV1_FPVL1 (0x1u << 17) |
| (PWM_FPV1) Fault Protection Value for PWML output on channel 1 More... | |
| #define | PWM_FPV1_FPVL2 (0x1u << 18) |
| (PWM_FPV1) Fault Protection Value for PWML output on channel 2 More... | |
| #define | PWM_FPV1_FPVL3 (0x1u << 19) |
| (PWM_FPV1) Fault Protection Value for PWML output on channel 3 More... | |
| #define | PWM_FPE_FPE0_Pos 0 |
| #define | PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) |
| (PWM_FPE) Fault Protection Enable for channel 0 More... | |
| #define | PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) |
| #define | PWM_FPE_FPE1_Pos 8 |
| #define | PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) |
| (PWM_FPE) Fault Protection Enable for channel 1 More... | |
| #define | PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) |
| #define | PWM_FPE_FPE2_Pos 16 |
| #define | PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) |
| (PWM_FPE) Fault Protection Enable for channel 2 More... | |
| #define | PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) |
| #define | PWM_FPE_FPE3_Pos 24 |
| #define | PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) |
| (PWM_FPE) Fault Protection Enable for channel 3 More... | |
| #define | PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) |
| #define | PWM_ELMR_CSEL0 (0x1u << 0) |
| (PWM_ELMR[2]) Comparison 0 Selection More... | |
| #define | PWM_ELMR_CSEL1 (0x1u << 1) |
| (PWM_ELMR[2]) Comparison 1 Selection More... | |
| #define | PWM_ELMR_CSEL2 (0x1u << 2) |
| (PWM_ELMR[2]) Comparison 2 Selection More... | |
| #define | PWM_ELMR_CSEL3 (0x1u << 3) |
| (PWM_ELMR[2]) Comparison 3 Selection More... | |
| #define | PWM_ELMR_CSEL4 (0x1u << 4) |
| (PWM_ELMR[2]) Comparison 4 Selection More... | |
| #define | PWM_ELMR_CSEL5 (0x1u << 5) |
| (PWM_ELMR[2]) Comparison 5 Selection More... | |
| #define | PWM_ELMR_CSEL6 (0x1u << 6) |
| (PWM_ELMR[2]) Comparison 6 Selection More... | |
| #define | PWM_ELMR_CSEL7 (0x1u << 7) |
| (PWM_ELMR[2]) Comparison 7 Selection More... | |
| #define | PWM_SSPR_SPRD_Pos 0 |
| #define | PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) |
| (PWM_SSPR) Spread Spectrum Limit Value More... | |
| #define | PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) |
| #define | PWM_SSPR_SPRDM (0x1u << 24) |
| (PWM_SSPR) Spread Spectrum Counter Mode More... | |
| #define | PWM_SSPUP_SPRDUP_Pos 0 |
| #define | PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) |
| (PWM_SSPUP) Spread Spectrum Limit Value Update More... | |
| #define | PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) |
| #define | PWM_SMMR_GCEN0 (0x1u << 0) |
| (PWM_SMMR) Gray Count ENable More... | |
| #define | PWM_SMMR_GCEN1 (0x1u << 1) |
| (PWM_SMMR) Gray Count ENable More... | |
| #define | PWM_SMMR_DOWN0 (0x1u << 16) |
| (PWM_SMMR) DOWN Count More... | |
| #define | PWM_SMMR_DOWN1 (0x1u << 17) |
| (PWM_SMMR) DOWN Count More... | |
| #define | PWM_FPV2_FPZH0 (0x1u << 0) |
| (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 More... | |
| #define | PWM_FPV2_FPZH1 (0x1u << 1) |
| (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 More... | |
| #define | PWM_FPV2_FPZH2 (0x1u << 2) |
| (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 More... | |
| #define | PWM_FPV2_FPZH3 (0x1u << 3) |
| (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 More... | |
| #define | PWM_FPV2_FPZL0 (0x1u << 16) |
| (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 More... | |
| #define | PWM_FPV2_FPZL1 (0x1u << 17) |
| (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 More... | |
| #define | PWM_FPV2_FPZL2 (0x1u << 18) |
| (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 More... | |
| #define | PWM_FPV2_FPZL3 (0x1u << 19) |
| (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 More... | |
| #define | PWM_WPCR_WPCMD_Pos 0 |
| #define | PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) |
| (PWM_WPCR) Write Protection Command More... | |
| #define | PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) |
| #define | PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) |
| (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. More... | |
| #define | PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) |
| (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. More... | |
| #define | PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) |
| (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. More... | |
| #define | PWM_WPCR_WPRG0 (0x1u << 2) |
| (PWM_WPCR) Write Protection Register Group 0 More... | |
| #define | PWM_WPCR_WPRG1 (0x1u << 3) |
| (PWM_WPCR) Write Protection Register Group 1 More... | |
| #define | PWM_WPCR_WPRG2 (0x1u << 4) |
| (PWM_WPCR) Write Protection Register Group 2 More... | |
| #define | PWM_WPCR_WPRG3 (0x1u << 5) |
| (PWM_WPCR) Write Protection Register Group 3 More... | |
| #define | PWM_WPCR_WPRG4 (0x1u << 6) |
| (PWM_WPCR) Write Protection Register Group 4 More... | |
| #define | PWM_WPCR_WPRG5 (0x1u << 7) |
| (PWM_WPCR) Write Protection Register Group 5 More... | |
| #define | PWM_WPCR_WPKEY_Pos 8 |
| #define | PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) |
| (PWM_WPCR) Write Protection Key More... | |
| #define | PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) |
| #define | PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) |
| (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 More... | |
| #define | PWM_WPSR_WPSWS0 (0x1u << 0) |
| (PWM_WPSR) Write Protect SW Status More... | |
| #define | PWM_WPSR_WPSWS1 (0x1u << 1) |
| (PWM_WPSR) Write Protect SW Status More... | |
| #define | PWM_WPSR_WPSWS2 (0x1u << 2) |
| (PWM_WPSR) Write Protect SW Status More... | |
| #define | PWM_WPSR_WPSWS3 (0x1u << 3) |
| (PWM_WPSR) Write Protect SW Status More... | |
| #define | PWM_WPSR_WPSWS4 (0x1u << 4) |
| (PWM_WPSR) Write Protect SW Status More... | |
| #define | PWM_WPSR_WPSWS5 (0x1u << 5) |
| (PWM_WPSR) Write Protect SW Status More... | |
| #define | PWM_WPSR_WPVS (0x1u << 7) |
| (PWM_WPSR) Write Protect Violation Status More... | |
| #define | PWM_WPSR_WPHWS0 (0x1u << 8) |
| (PWM_WPSR) Write Protect HW Status More... | |
| #define | PWM_WPSR_WPHWS1 (0x1u << 9) |
| (PWM_WPSR) Write Protect HW Status More... | |
| #define | PWM_WPSR_WPHWS2 (0x1u << 10) |
| (PWM_WPSR) Write Protect HW Status More... | |
| #define | PWM_WPSR_WPHWS3 (0x1u << 11) |
| (PWM_WPSR) Write Protect HW Status More... | |
| #define | PWM_WPSR_WPHWS4 (0x1u << 12) |
| (PWM_WPSR) Write Protect HW Status More... | |
| #define | PWM_WPSR_WPHWS5 (0x1u << 13) |
| (PWM_WPSR) Write Protect HW Status More... | |
| #define | PWM_WPSR_WPVSRC_Pos 16 |
| #define | PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) |
| (PWM_WPSR) Write Protect Violation Source More... | |
| #define | PWM_VERSION_VERSION_Pos 0 |
| #define | PWM_VERSION_VERSION_Msk (0xfffu << PWM_VERSION_VERSION_Pos) |
| (PWM_VERSION) Version of the Hardware Module More... | |
| #define | PWM_VERSION_MFN_Pos 16 |
| #define | PWM_VERSION_MFN_Msk (0x7u << PWM_VERSION_MFN_Pos) |
| (PWM_VERSION) Metal Fix Number More... | |
| #define | PWM_CMPV_CV_Pos 0 |
| #define | PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) |
| (PWM_CMPV) Comparison x Value More... | |
| #define | PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) |
| #define | PWM_CMPV_CVM (0x1u << 24) |
| (PWM_CMPV) Comparison x Value Mode More... | |
| #define | PWM_CMPVUPD_CVUPD_Pos 0 |
| #define | PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) |
| (PWM_CMPVUPD) Comparison x Value Update More... | |
| #define | PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) |
| #define | PWM_CMPVUPD_CVMUPD (0x1u << 24) |
| (PWM_CMPVUPD) Comparison x Value Mode Update More... | |
| #define | PWM_CMPM_CEN (0x1u << 0) |
| (PWM_CMPM) Comparison x Enable More... | |
| #define | PWM_CMPM_CTR_Pos 4 |
| #define | PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) |
| (PWM_CMPM) Comparison x Trigger More... | |
| #define | PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) |
| #define | PWM_CMPM_CPR_Pos 8 |
| #define | PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) |
| (PWM_CMPM) Comparison x Period More... | |
| #define | PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) |
| #define | PWM_CMPM_CPRCNT_Pos 12 |
| #define | PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) |
| (PWM_CMPM) Comparison x Period Counter More... | |
| #define | PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) |
| #define | PWM_CMPM_CUPR_Pos 16 |
| #define | PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) |
| (PWM_CMPM) Comparison x Update Period More... | |
| #define | PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) |
| #define | PWM_CMPM_CUPRCNT_Pos 20 |
| #define | PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) |
| (PWM_CMPM) Comparison x Update Period Counter More... | |
| #define | PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) |
| #define | PWM_CMPMUPD_CENUPD (0x1u << 0) |
| (PWM_CMPMUPD) Comparison x Enable Update More... | |
| #define | PWM_CMPMUPD_CTRUPD_Pos 4 |
| #define | PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) |
| (PWM_CMPMUPD) Comparison x Trigger Update More... | |
| #define | PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) |
| #define | PWM_CMPMUPD_CPRUPD_Pos 8 |
| #define | PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) |
| (PWM_CMPMUPD) Comparison x Period Update More... | |
| #define | PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) |
| #define | PWM_CMPMUPD_CUPRUPD_Pos 16 |
| #define | PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) |
| (PWM_CMPMUPD) Comparison x Update Period Update More... | |
| #define | PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) |
| #define | PWM_CMR_CPRE_Pos 0 |
| #define | PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) |
| (PWM_CMR) Channel Pre-scaler More... | |
| #define | PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) |
| #define | PWM_CMR_CPRE_MCK (0x0u << 0) |
| (PWM_CMR) Peripheral clock More... | |
| #define | PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) |
| (PWM_CMR) Peripheral clock/2 More... | |
| #define | PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) |
| (PWM_CMR) Peripheral clock/4 More... | |
| #define | PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) |
| (PWM_CMR) Peripheral clock/8 More... | |
| #define | PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) |
| (PWM_CMR) Peripheral clock/16 More... | |
| #define | PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) |
| (PWM_CMR) Peripheral clock/32 More... | |
| #define | PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) |
| (PWM_CMR) Peripheral clock/64 More... | |
| #define | PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) |
| (PWM_CMR) Peripheral clock/128 More... | |
| #define | PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) |
| (PWM_CMR) Peripheral clock/256 More... | |
| #define | PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) |
| (PWM_CMR) Peripheral clock/512 More... | |
| #define | PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) |
| (PWM_CMR) Peripheral clock/1024 More... | |
| #define | PWM_CMR_CPRE_CLKA (0xBu << 0) |
| (PWM_CMR) Clock A More... | |
| #define | PWM_CMR_CPRE_CLKB (0xCu << 0) |
| (PWM_CMR) Clock B More... | |
| #define | PWM_CMR_CALG (0x1u << 8) |
| (PWM_CMR) Channel Alignment More... | |
| #define | PWM_CMR_CPOL (0x1u << 9) |
| (PWM_CMR) Channel Polarity More... | |
| #define | PWM_CMR_CES (0x1u << 10) |
| (PWM_CMR) Counter Event Selection More... | |
| #define | PWM_CMR_UPDS (0x1u << 11) |
| (PWM_CMR) Update Selection More... | |
| #define | PWM_CMR_DPOLI (0x1u << 12) |
| (PWM_CMR) Disabled Polarity Inverted More... | |
| #define | PWM_CMR_TCTS (0x1u << 13) |
| (PWM_CMR) Timer Counter Trigger Selection More... | |
| #define | PWM_CMR_DTE (0x1u << 16) |
| (PWM_CMR) Dead-Time Generator Enable More... | |
| #define | PWM_CMR_DTHI (0x1u << 17) |
| (PWM_CMR) Dead-Time PWMHx Output Inverted More... | |
| #define | PWM_CMR_DTLI (0x1u << 18) |
| (PWM_CMR) Dead-Time PWMLx Output Inverted More... | |
| #define | PWM_CMR_PPM (0x1u << 19) |
| (PWM_CMR) Push-Pull Mode More... | |
| #define | PWM_CDTY_CDTY_Pos 0 |
| #define | PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) |
| (PWM_CDTY) Channel Duty-Cycle More... | |
| #define | PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) |
| #define | PWM_CDTYUPD_CDTYUPD_Pos 0 |
| #define | PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) |
| (PWM_CDTYUPD) Channel Duty-Cycle Update More... | |
| #define | PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) |
| #define | PWM_CPRD_CPRD_Pos 0 |
| #define | PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) |
| (PWM_CPRD) Channel Period More... | |
| #define | PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) |
| #define | PWM_CPRDUPD_CPRDUPD_Pos 0 |
| #define | PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) |
| (PWM_CPRDUPD) Channel Period Update More... | |
| #define | PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) |
| #define | PWM_CCNT_CNT_Pos 0 |
| #define | PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) |
| (PWM_CCNT) Channel Counter Register More... | |
| #define | PWM_DT_DTH_Pos 0 |
| #define | PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) |
| (PWM_DT) Dead-Time Value for PWMHx Output More... | |
| #define | PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) |
| #define | PWM_DT_DTL_Pos 16 |
| #define | PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) |
| (PWM_DT) Dead-Time Value for PWMLx Output More... | |
| #define | PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) |
| #define | PWM_DTUPD_DTHUPD_Pos 0 |
| #define | PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) |
| (PWM_DTUPD) Dead-Time Value Update for PWMHx Output More... | |
| #define | PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) |
| #define | PWM_DTUPD_DTLUPD_Pos 16 |
| #define | PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) |
| (PWM_DTUPD) Dead-Time Value Update for PWMLx Output More... | |
| #define | PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) |
| #define | PWM_CMUPD0_CPOLUP (0x1u << 9) |
| (PWM_CMUPD0) Channel Polarity Update More... | |
| #define | PWM_CMUPD0_CPOLINVUP (0x1u << 13) |
| (PWM_CMUPD0) Channel Polarity Inversion Update More... | |
| #define | PWM_CMUPD1_CPOLUP (0x1u << 9) |
| (PWM_CMUPD1) Channel Polarity Update More... | |
| #define | PWM_CMUPD1_CPOLINVUP (0x1u << 13) |
| (PWM_CMUPD1) Channel Polarity Inversion Update More... | |
| #define | PWM_ETRG1_MAXCNT_Pos 0 |
| #define | PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) |
| (PWM_ETRG1) Maximum Counter value More... | |
| #define | PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) |
| #define | PWM_ETRG1_TRGMODE_Pos 24 |
| #define | PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) |
| (PWM_ETRG1) External Trigger Mode More... | |
| #define | PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) |
| #define | PWM_ETRG1_TRGMODE_OFF (0x0u << 24) |
| (PWM_ETRG1) External trigger is not enabled. More... | |
| #define | PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) |
| (PWM_ETRG1) External PWM Reset Mode More... | |
| #define | PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) |
| (PWM_ETRG1) External PWM Start Mode More... | |
| #define | PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) |
| (PWM_ETRG1) Cycle-by-cycle Duty Mode More... | |
| #define | PWM_ETRG1_TRGEDGE (0x1u << 28) |
| (PWM_ETRG1) Edge Selection More... | |
| #define | PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) |
| (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 More... | |
| #define | PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) |
| (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 More... | |
| #define | PWM_ETRG1_TRGFILT (0x1u << 29) |
| (PWM_ETRG1) Filtered input More... | |
| #define | PWM_ETRG1_TRGSRC (0x1u << 30) |
| (PWM_ETRG1) Trigger Source More... | |
| #define | PWM_ETRG1_RFEN (0x1u << 31) |
| (PWM_ETRG1) Recoverable Fault Enable More... | |
| #define | PWM_LEBR1_LEBDELAY_Pos 0 |
| #define | PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) |
| (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx More... | |
| #define | PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) |
| #define | PWM_LEBR1_PWMLFEN (0x1u << 16) |
| (PWM_LEBR1) PWML Falling Edge Enable More... | |
| #define | PWM_LEBR1_PWMLREN (0x1u << 17) |
| (PWM_LEBR1) PWML Rising Edge Enable More... | |
| #define | PWM_LEBR1_PWMHFEN (0x1u << 18) |
| (PWM_LEBR1) PWMH Falling Edge Enable More... | |
| #define | PWM_LEBR1_PWMHREN (0x1u << 19) |
| (PWM_LEBR1) PWMH Rising Edge Enable More... | |
| #define | PWM_CMUPD2_CPOLUP (0x1u << 9) |
| (PWM_CMUPD2) Channel Polarity Update More... | |
| #define | PWM_CMUPD2_CPOLINVUP (0x1u << 13) |
| (PWM_CMUPD2) Channel Polarity Inversion Update More... | |
| #define | PWM_ETRG2_MAXCNT_Pos 0 |
| #define | PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) |
| (PWM_ETRG2) Maximum Counter value More... | |
| #define | PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) |
| #define | PWM_ETRG2_TRGMODE_Pos 24 |
| #define | PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) |
| (PWM_ETRG2) External Trigger Mode More... | |
| #define | PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) |
| #define | PWM_ETRG2_TRGMODE_OFF (0x0u << 24) |
| (PWM_ETRG2) External trigger is not enabled. More... | |
| #define | PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) |
| (PWM_ETRG2) External PWM Reset Mode More... | |
| #define | PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) |
| (PWM_ETRG2) External PWM Start Mode More... | |
| #define | PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) |
| (PWM_ETRG2) Cycle-by-cycle Duty Mode More... | |
| #define | PWM_ETRG2_TRGEDGE (0x1u << 28) |
| (PWM_ETRG2) Edge Selection More... | |
| #define | PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) |
| (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 More... | |
| #define | PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) |
| (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 More... | |
| #define | PWM_ETRG2_TRGFILT (0x1u << 29) |
| (PWM_ETRG2) Filtered input More... | |
| #define | PWM_ETRG2_TRGSRC (0x1u << 30) |
| (PWM_ETRG2) Trigger Source More... | |
| #define | PWM_ETRG2_RFEN (0x1u << 31) |
| (PWM_ETRG2) Recoverable Fault Enable More... | |
| #define | PWM_LEBR2_LEBDELAY_Pos 0 |
| #define | PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) |
| (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx More... | |
| #define | PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) |
| #define | PWM_LEBR2_PWMLFEN (0x1u << 16) |
| (PWM_LEBR2) PWML Falling Edge Enable More... | |
| #define | PWM_LEBR2_PWMLREN (0x1u << 17) |
| (PWM_LEBR2) PWML Rising Edge Enable More... | |
| #define | PWM_LEBR2_PWMHFEN (0x1u << 18) |
| (PWM_LEBR2) PWMH Falling Edge Enable More... | |
| #define | PWM_LEBR2_PWMHREN (0x1u << 19) |
| (PWM_LEBR2) PWMH Rising Edge Enable More... | |
| #define | PWM_CMUPD3_CPOLUP (0x1u << 9) |
| (PWM_CMUPD3) Channel Polarity Update More... | |
| #define | PWM_CMUPD3_CPOLINVUP (0x1u << 13) |
| (PWM_CMUPD3) Channel Polarity Inversion Update More... | |
SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller.
| #define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) |
(PWM_CCNT) Channel Counter Register
| #define PWM_CCNT_CNT_Pos 0 |
| #define PWM_CDTY_CDTY | ( | value | ) | ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) |
| #define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) |
(PWM_CDTY) Channel Duty-Cycle
| #define PWM_CDTY_CDTY_Pos 0 |
| #define PWM_CDTYUPD_CDTYUPD | ( | value | ) | ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) |
| #define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) |
(PWM_CDTYUPD) Channel Duty-Cycle Update
| #define PWM_CDTYUPD_CDTYUPD_Pos 0 |
| #define PWM_CLK_DIVA | ( | value | ) | ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) |
| #define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) |
(PWM_CLK) CLKA clock is turned off
| #define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) |
(PWM_CLK) CLKA Divide Factor
| #define PWM_CLK_DIVA_Pos 0 |
| #define PWM_CLK_DIVA_PREA (0x1u << 0) |
(PWM_CLK) CLKA clock is clock selected by PREA
| #define PWM_CLK_DIVB | ( | value | ) | ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) |
| #define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) |
(PWM_CLK) CLKB clock is turned off
| #define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) |
(PWM_CLK) CLKB Divide Factor
| #define PWM_CLK_DIVB_Pos 16 |
| #define PWM_CLK_DIVB_PREB (0x1u << 16) |
(PWM_CLK) CLKB clock is clock selected by PREB
| #define PWM_CLK_PREA | ( | value | ) | ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) |
| #define PWM_CLK_PREA_CLK (0x0u << 8) |
(PWM_CLK) Peripheral clock
| #define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) |
(PWM_CLK) Peripheral clock/1024
| #define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) |
(PWM_CLK) Peripheral clock/128
| #define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) |
(PWM_CLK) Peripheral clock/16
| #define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) |
(PWM_CLK) Peripheral clock/2
| #define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) |
(PWM_CLK) Peripheral clock/256
| #define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) |
(PWM_CLK) Peripheral clock/32
| #define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) |
(PWM_CLK) Peripheral clock/4
| #define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) |
(PWM_CLK) Peripheral clock/512
| #define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) |
(PWM_CLK) Peripheral clock/64
| #define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) |
(PWM_CLK) Peripheral clock/8
| #define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) |
(PWM_CLK) CLKA Source Clock Selection
| #define PWM_CLK_PREA_Pos 8 |
| #define PWM_CLK_PREB | ( | value | ) | ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) |
| #define PWM_CLK_PREB_CLK (0x0u << 24) |
(PWM_CLK) Peripheral clock
| #define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) |
(PWM_CLK) Peripheral clock/1024
| #define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) |
(PWM_CLK) Peripheral clock/128
| #define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) |
(PWM_CLK) Peripheral clock/16
| #define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) |
(PWM_CLK) Peripheral clock/2
| #define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) |
(PWM_CLK) Peripheral clock/256
| #define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) |
(PWM_CLK) Peripheral clock/32
| #define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) |
(PWM_CLK) Peripheral clock/4
| #define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) |
(PWM_CLK) Peripheral clock/512
| #define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) |
(PWM_CLK) Peripheral clock/64
| #define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) |
(PWM_CLK) Peripheral clock/8
| #define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) |
(PWM_CLK) CLKB Source Clock Selection
| #define PWM_CLK_PREB_Pos 24 |
| #define PWM_CMPM_CEN (0x1u << 0) |
(PWM_CMPM) Comparison x Enable
| #define PWM_CMPM_CPR | ( | value | ) | ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) |
| #define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) |
(PWM_CMPM) Comparison x Period
| #define PWM_CMPM_CPR_Pos 8 |
| #define PWM_CMPM_CPRCNT | ( | value | ) | ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) |
| #define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) |
(PWM_CMPM) Comparison x Period Counter
| #define PWM_CMPM_CPRCNT_Pos 12 |
| #define PWM_CMPM_CTR | ( | value | ) | ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) |
| #define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) |
(PWM_CMPM) Comparison x Trigger
| #define PWM_CMPM_CTR_Pos 4 |
| #define PWM_CMPM_CUPR | ( | value | ) | ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) |
| #define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) |
(PWM_CMPM) Comparison x Update Period
| #define PWM_CMPM_CUPR_Pos 16 |
| #define PWM_CMPM_CUPRCNT | ( | value | ) | ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) |
| #define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) |
(PWM_CMPM) Comparison x Update Period Counter
| #define PWM_CMPM_CUPRCNT_Pos 20 |
| #define PWM_CMPMUPD_CENUPD (0x1u << 0) |
(PWM_CMPMUPD) Comparison x Enable Update
| #define PWM_CMPMUPD_CPRUPD | ( | value | ) | ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) |
| #define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) |
(PWM_CMPMUPD) Comparison x Period Update
| #define PWM_CMPMUPD_CPRUPD_Pos 8 |
| #define PWM_CMPMUPD_CTRUPD | ( | value | ) | ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) |
| #define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) |
(PWM_CMPMUPD) Comparison x Trigger Update
| #define PWM_CMPMUPD_CTRUPD_Pos 4 |
| #define PWM_CMPMUPD_CUPRUPD | ( | value | ) | ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) |
| #define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) |
(PWM_CMPMUPD) Comparison x Update Period Update
| #define PWM_CMPMUPD_CUPRUPD_Pos 16 |
| #define PWM_CMPV_CV | ( | value | ) | ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) |
| #define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) |
(PWM_CMPV) Comparison x Value
| #define PWM_CMPV_CV_Pos 0 |
| #define PWM_CMPV_CVM (0x1u << 24) |
(PWM_CMPV) Comparison x Value Mode
| #define PWM_CMPVUPD_CVMUPD (0x1u << 24) |
(PWM_CMPVUPD) Comparison x Value Mode Update
| #define PWM_CMPVUPD_CVUPD | ( | value | ) | ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) |
| #define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) |
(PWM_CMPVUPD) Comparison x Value Update
| #define PWM_CMPVUPD_CVUPD_Pos 0 |
| #define PWM_CMR_CALG (0x1u << 8) |
(PWM_CMR) Channel Alignment
| #define PWM_CMR_CES (0x1u << 10) |
(PWM_CMR) Counter Event Selection
| #define PWM_CMR_CPOL (0x1u << 9) |
(PWM_CMR) Channel Polarity
| #define PWM_CMR_CPRE | ( | value | ) | ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) |
| #define PWM_CMR_CPRE_CLKA (0xBu << 0) |
(PWM_CMR) Clock A
| #define PWM_CMR_CPRE_CLKB (0xCu << 0) |
(PWM_CMR) Clock B
| #define PWM_CMR_CPRE_MCK (0x0u << 0) |
(PWM_CMR) Peripheral clock
| #define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) |
(PWM_CMR) Peripheral clock/1024
| #define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) |
(PWM_CMR) Peripheral clock/128
| #define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) |
(PWM_CMR) Peripheral clock/16
| #define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) |
(PWM_CMR) Peripheral clock/2
| #define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) |
(PWM_CMR) Peripheral clock/256
| #define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) |
(PWM_CMR) Peripheral clock/32
| #define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) |
(PWM_CMR) Peripheral clock/4
| #define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) |
(PWM_CMR) Peripheral clock/512
| #define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) |
(PWM_CMR) Peripheral clock/64
| #define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) |
(PWM_CMR) Peripheral clock/8
| #define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) |
(PWM_CMR) Channel Pre-scaler
| #define PWM_CMR_CPRE_Pos 0 |
| #define PWM_CMR_DPOLI (0x1u << 12) |
(PWM_CMR) Disabled Polarity Inverted
| #define PWM_CMR_DTE (0x1u << 16) |
(PWM_CMR) Dead-Time Generator Enable
| #define PWM_CMR_DTHI (0x1u << 17) |
(PWM_CMR) Dead-Time PWMHx Output Inverted
| #define PWM_CMR_DTLI (0x1u << 18) |
(PWM_CMR) Dead-Time PWMLx Output Inverted
| #define PWM_CMR_PPM (0x1u << 19) |
(PWM_CMR) Push-Pull Mode
| #define PWM_CMR_TCTS (0x1u << 13) |
(PWM_CMR) Timer Counter Trigger Selection
| #define PWM_CMR_UPDS (0x1u << 11) |
(PWM_CMR) Update Selection
| #define PWM_CMUPD0_CPOLINVUP (0x1u << 13) |
(PWM_CMUPD0) Channel Polarity Inversion Update
| #define PWM_CMUPD0_CPOLUP (0x1u << 9) |
(PWM_CMUPD0) Channel Polarity Update
| #define PWM_CMUPD1_CPOLINVUP (0x1u << 13) |
(PWM_CMUPD1) Channel Polarity Inversion Update
| #define PWM_CMUPD1_CPOLUP (0x1u << 9) |
(PWM_CMUPD1) Channel Polarity Update
| #define PWM_CMUPD2_CPOLINVUP (0x1u << 13) |
(PWM_CMUPD2) Channel Polarity Inversion Update
| #define PWM_CMUPD2_CPOLUP (0x1u << 9) |
(PWM_CMUPD2) Channel Polarity Update
| #define PWM_CMUPD3_CPOLINVUP (0x1u << 13) |
(PWM_CMUPD3) Channel Polarity Inversion Update
| #define PWM_CMUPD3_CPOLUP (0x1u << 9) |
(PWM_CMUPD3) Channel Polarity Update
| #define PWM_CPRD_CPRD | ( | value | ) | ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) |
| #define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) |
(PWM_CPRD) Channel Period
| #define PWM_CPRD_CPRD_Pos 0 |
| #define PWM_CPRDUPD_CPRDUPD | ( | value | ) | ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) |
| #define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) |
(PWM_CPRDUPD) Channel Period Update
| #define PWM_CPRDUPD_CPRDUPD_Pos 0 |
| #define PWM_DIS_CHID0 (0x1u << 0) |
(PWM_DIS) Channel ID
| #define PWM_DIS_CHID1 (0x1u << 1) |
(PWM_DIS) Channel ID
| #define PWM_DIS_CHID2 (0x1u << 2) |
(PWM_DIS) Channel ID
| #define PWM_DIS_CHID3 (0x1u << 3) |
(PWM_DIS) Channel ID
| #define PWM_DMAR_DMADUTY | ( | value | ) | ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) |
| #define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) |
(PWM_DMAR) Duty-Cycle Holding Register for DMA Access
| #define PWM_DMAR_DMADUTY_Pos 0 |
| #define PWM_DT_DTH | ( | value | ) | ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) |
| #define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) |
(PWM_DT) Dead-Time Value for PWMHx Output
| #define PWM_DT_DTH_Pos 0 |
| #define PWM_DT_DTL | ( | value | ) | ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) |
| #define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) |
(PWM_DT) Dead-Time Value for PWMLx Output
| #define PWM_DT_DTL_Pos 16 |
| #define PWM_DTUPD_DTHUPD | ( | value | ) | ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) |
| #define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) |
(PWM_DTUPD) Dead-Time Value Update for PWMHx Output
| #define PWM_DTUPD_DTHUPD_Pos 0 |
| #define PWM_DTUPD_DTLUPD | ( | value | ) | ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) |
| #define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) |
(PWM_DTUPD) Dead-Time Value Update for PWMLx Output
| #define PWM_DTUPD_DTLUPD_Pos 16 |
| #define PWM_ELMR_CSEL0 (0x1u << 0) |
(PWM_ELMR[2]) Comparison 0 Selection
| #define PWM_ELMR_CSEL1 (0x1u << 1) |
(PWM_ELMR[2]) Comparison 1 Selection
| #define PWM_ELMR_CSEL2 (0x1u << 2) |
(PWM_ELMR[2]) Comparison 2 Selection
| #define PWM_ELMR_CSEL3 (0x1u << 3) |
(PWM_ELMR[2]) Comparison 3 Selection
| #define PWM_ELMR_CSEL4 (0x1u << 4) |
(PWM_ELMR[2]) Comparison 4 Selection
| #define PWM_ELMR_CSEL5 (0x1u << 5) |
(PWM_ELMR[2]) Comparison 5 Selection
| #define PWM_ELMR_CSEL6 (0x1u << 6) |
(PWM_ELMR[2]) Comparison 6 Selection
| #define PWM_ELMR_CSEL7 (0x1u << 7) |
(PWM_ELMR[2]) Comparison 7 Selection
| #define PWM_ENA_CHID0 (0x1u << 0) |
(PWM_ENA) Channel ID
| #define PWM_ENA_CHID1 (0x1u << 1) |
(PWM_ENA) Channel ID
| #define PWM_ENA_CHID2 (0x1u << 2) |
(PWM_ENA) Channel ID
| #define PWM_ENA_CHID3 (0x1u << 3) |
(PWM_ENA) Channel ID
| #define PWM_ETRG1_MAXCNT | ( | value | ) | ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) |
| #define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) |
(PWM_ETRG1) Maximum Counter value
| #define PWM_ETRG1_MAXCNT_Pos 0 |
| #define PWM_ETRG1_RFEN (0x1u << 31) |
(PWM_ETRG1) Recoverable Fault Enable
| #define PWM_ETRG1_TRGEDGE (0x1u << 28) |
(PWM_ETRG1) Edge Selection
| #define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) |
(PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0
| #define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) |
(PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
| #define PWM_ETRG1_TRGFILT (0x1u << 29) |
(PWM_ETRG1) Filtered input
| #define PWM_ETRG1_TRGMODE | ( | value | ) | ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) |
| #define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) |
(PWM_ETRG1) External PWM Reset Mode
| #define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) |
(PWM_ETRG1) External PWM Start Mode
| #define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) |
(PWM_ETRG1) Cycle-by-cycle Duty Mode
| #define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) |
(PWM_ETRG1) External Trigger Mode
| #define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) |
(PWM_ETRG1) External trigger is not enabled.
| #define PWM_ETRG1_TRGMODE_Pos 24 |
| #define PWM_ETRG1_TRGSRC (0x1u << 30) |
(PWM_ETRG1) Trigger Source
| #define PWM_ETRG2_MAXCNT | ( | value | ) | ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) |
| #define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) |
(PWM_ETRG2) Maximum Counter value
| #define PWM_ETRG2_MAXCNT_Pos 0 |
| #define PWM_ETRG2_RFEN (0x1u << 31) |
(PWM_ETRG2) Recoverable Fault Enable
| #define PWM_ETRG2_TRGEDGE (0x1u << 28) |
(PWM_ETRG2) Edge Selection
| #define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) |
(PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0
| #define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) |
(PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
| #define PWM_ETRG2_TRGFILT (0x1u << 29) |
(PWM_ETRG2) Filtered input
| #define PWM_ETRG2_TRGMODE | ( | value | ) | ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) |
| #define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) |
(PWM_ETRG2) External PWM Reset Mode
| #define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) |
(PWM_ETRG2) External PWM Start Mode
| #define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) |
(PWM_ETRG2) Cycle-by-cycle Duty Mode
| #define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) |
(PWM_ETRG2) External Trigger Mode
| #define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) |
(PWM_ETRG2) External trigger is not enabled.
| #define PWM_ETRG2_TRGMODE_Pos 24 |
| #define PWM_ETRG2_TRGSRC (0x1u << 30) |
(PWM_ETRG2) Trigger Source
| #define PWM_FCR_FCLR | ( | value | ) | ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) |
| #define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) |
(PWM_FCR) Fault Clear
| #define PWM_FCR_FCLR_Pos 0 |
| #define PWM_FMR_FFIL | ( | value | ) | ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) |
| #define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) |
(PWM_FMR) Fault Filtering
| #define PWM_FMR_FFIL_Pos 16 |
| #define PWM_FMR_FMOD | ( | value | ) | ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) |
| #define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) |
(PWM_FMR) Fault Activation Mode
| #define PWM_FMR_FMOD_Pos 8 |
| #define PWM_FMR_FPOL | ( | value | ) | ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) |
| #define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) |
(PWM_FMR) Fault Polarity
| #define PWM_FMR_FPOL_Pos 0 |
| #define PWM_FPE_FPE0 | ( | value | ) | ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) |
| #define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) |
(PWM_FPE) Fault Protection Enable for channel 0
| #define PWM_FPE_FPE0_Pos 0 |
| #define PWM_FPE_FPE1 | ( | value | ) | ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) |
| #define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) |
(PWM_FPE) Fault Protection Enable for channel 1
| #define PWM_FPE_FPE1_Pos 8 |
| #define PWM_FPE_FPE2 | ( | value | ) | ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) |
| #define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) |
(PWM_FPE) Fault Protection Enable for channel 2
| #define PWM_FPE_FPE2_Pos 16 |
| #define PWM_FPE_FPE3 | ( | value | ) | ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) |
| #define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) |
(PWM_FPE) Fault Protection Enable for channel 3
| #define PWM_FPE_FPE3_Pos 24 |
| #define PWM_FPV1_FPVH0 (0x1u << 0) |
(PWM_FPV1) Fault Protection Value for PWMH output on channel 0
| #define PWM_FPV1_FPVH1 (0x1u << 1) |
(PWM_FPV1) Fault Protection Value for PWMH output on channel 1
| #define PWM_FPV1_FPVH2 (0x1u << 2) |
(PWM_FPV1) Fault Protection Value for PWMH output on channel 2
| #define PWM_FPV1_FPVH3 (0x1u << 3) |
(PWM_FPV1) Fault Protection Value for PWMH output on channel 3
| #define PWM_FPV1_FPVL0 (0x1u << 16) |
(PWM_FPV1) Fault Protection Value for PWML output on channel 0
| #define PWM_FPV1_FPVL1 (0x1u << 17) |
(PWM_FPV1) Fault Protection Value for PWML output on channel 1
| #define PWM_FPV1_FPVL2 (0x1u << 18) |
(PWM_FPV1) Fault Protection Value for PWML output on channel 2
| #define PWM_FPV1_FPVL3 (0x1u << 19) |
(PWM_FPV1) Fault Protection Value for PWML output on channel 3
| #define PWM_FPV2_FPZH0 (0x1u << 0) |
(PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0
| #define PWM_FPV2_FPZH1 (0x1u << 1) |
(PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1
| #define PWM_FPV2_FPZH2 (0x1u << 2) |
(PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2
| #define PWM_FPV2_FPZH3 (0x1u << 3) |
(PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3
| #define PWM_FPV2_FPZL0 (0x1u << 16) |
(PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0
| #define PWM_FPV2_FPZL1 (0x1u << 17) |
(PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1
| #define PWM_FPV2_FPZL2 (0x1u << 18) |
(PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2
| #define PWM_FPV2_FPZL3 (0x1u << 19) |
(PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3
| #define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) |
(PWM_FSR) Fault Input Value
| #define PWM_FSR_FIV_Pos 0 |
| #define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) |
(PWM_FSR) Fault Status
| #define PWM_FSR_FS_Pos 8 |
| #define PWM_IDR1_CHID0 (0x1u << 0) |
(PWM_IDR1) Counter Event on Channel 0 Interrupt Disable
| #define PWM_IDR1_CHID1 (0x1u << 1) |
(PWM_IDR1) Counter Event on Channel 1 Interrupt Disable
| #define PWM_IDR1_CHID2 (0x1u << 2) |
(PWM_IDR1) Counter Event on Channel 2 Interrupt Disable
| #define PWM_IDR1_CHID3 (0x1u << 3) |
(PWM_IDR1) Counter Event on Channel 3 Interrupt Disable
| #define PWM_IDR1_FCHID0 (0x1u << 16) |
(PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable
| #define PWM_IDR1_FCHID1 (0x1u << 17) |
(PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable
| #define PWM_IDR1_FCHID2 (0x1u << 18) |
(PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable
| #define PWM_IDR1_FCHID3 (0x1u << 19) |
(PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable
| #define PWM_IDR2_CMPM0 (0x1u << 8) |
(PWM_IDR2) Comparison 0 Match Interrupt Disable
| #define PWM_IDR2_CMPM1 (0x1u << 9) |
(PWM_IDR2) Comparison 1 Match Interrupt Disable
| #define PWM_IDR2_CMPM2 (0x1u << 10) |
(PWM_IDR2) Comparison 2 Match Interrupt Disable
| #define PWM_IDR2_CMPM3 (0x1u << 11) |
(PWM_IDR2) Comparison 3 Match Interrupt Disable
| #define PWM_IDR2_CMPM4 (0x1u << 12) |
(PWM_IDR2) Comparison 4 Match Interrupt Disable
| #define PWM_IDR2_CMPM5 (0x1u << 13) |
(PWM_IDR2) Comparison 5 Match Interrupt Disable
| #define PWM_IDR2_CMPM6 (0x1u << 14) |
(PWM_IDR2) Comparison 6 Match Interrupt Disable
| #define PWM_IDR2_CMPM7 (0x1u << 15) |
(PWM_IDR2) Comparison 7 Match Interrupt Disable
| #define PWM_IDR2_CMPU0 (0x1u << 16) |
(PWM_IDR2) Comparison 0 Update Interrupt Disable
| #define PWM_IDR2_CMPU1 (0x1u << 17) |
(PWM_IDR2) Comparison 1 Update Interrupt Disable
| #define PWM_IDR2_CMPU2 (0x1u << 18) |
(PWM_IDR2) Comparison 2 Update Interrupt Disable
| #define PWM_IDR2_CMPU3 (0x1u << 19) |
(PWM_IDR2) Comparison 3 Update Interrupt Disable
| #define PWM_IDR2_CMPU4 (0x1u << 20) |
(PWM_IDR2) Comparison 4 Update Interrupt Disable
| #define PWM_IDR2_CMPU5 (0x1u << 21) |
(PWM_IDR2) Comparison 5 Update Interrupt Disable
| #define PWM_IDR2_CMPU6 (0x1u << 22) |
(PWM_IDR2) Comparison 6 Update Interrupt Disable
| #define PWM_IDR2_CMPU7 (0x1u << 23) |
(PWM_IDR2) Comparison 7 Update Interrupt Disable
| #define PWM_IDR2_UNRE (0x1u << 3) |
(PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable
| #define PWM_IDR2_WRDY (0x1u << 0) |
(PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable
| #define PWM_IER1_CHID0 (0x1u << 0) |
(PWM_IER1) Counter Event on Channel 0 Interrupt Enable
| #define PWM_IER1_CHID1 (0x1u << 1) |
(PWM_IER1) Counter Event on Channel 1 Interrupt Enable
| #define PWM_IER1_CHID2 (0x1u << 2) |
(PWM_IER1) Counter Event on Channel 2 Interrupt Enable
| #define PWM_IER1_CHID3 (0x1u << 3) |
(PWM_IER1) Counter Event on Channel 3 Interrupt Enable
| #define PWM_IER1_FCHID0 (0x1u << 16) |
(PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable
| #define PWM_IER1_FCHID1 (0x1u << 17) |
(PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable
| #define PWM_IER1_FCHID2 (0x1u << 18) |
(PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable
| #define PWM_IER1_FCHID3 (0x1u << 19) |
(PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable
| #define PWM_IER2_CMPM0 (0x1u << 8) |
(PWM_IER2) Comparison 0 Match Interrupt Enable
| #define PWM_IER2_CMPM1 (0x1u << 9) |
(PWM_IER2) Comparison 1 Match Interrupt Enable
| #define PWM_IER2_CMPM2 (0x1u << 10) |
(PWM_IER2) Comparison 2 Match Interrupt Enable
| #define PWM_IER2_CMPM3 (0x1u << 11) |
(PWM_IER2) Comparison 3 Match Interrupt Enable
| #define PWM_IER2_CMPM4 (0x1u << 12) |
(PWM_IER2) Comparison 4 Match Interrupt Enable
| #define PWM_IER2_CMPM5 (0x1u << 13) |
(PWM_IER2) Comparison 5 Match Interrupt Enable
| #define PWM_IER2_CMPM6 (0x1u << 14) |
(PWM_IER2) Comparison 6 Match Interrupt Enable
| #define PWM_IER2_CMPM7 (0x1u << 15) |
(PWM_IER2) Comparison 7 Match Interrupt Enable
| #define PWM_IER2_CMPU0 (0x1u << 16) |
(PWM_IER2) Comparison 0 Update Interrupt Enable
| #define PWM_IER2_CMPU1 (0x1u << 17) |
(PWM_IER2) Comparison 1 Update Interrupt Enable
| #define PWM_IER2_CMPU2 (0x1u << 18) |
(PWM_IER2) Comparison 2 Update Interrupt Enable
| #define PWM_IER2_CMPU3 (0x1u << 19) |
(PWM_IER2) Comparison 3 Update Interrupt Enable
| #define PWM_IER2_CMPU4 (0x1u << 20) |
(PWM_IER2) Comparison 4 Update Interrupt Enable
| #define PWM_IER2_CMPU5 (0x1u << 21) |
(PWM_IER2) Comparison 5 Update Interrupt Enable
| #define PWM_IER2_CMPU6 (0x1u << 22) |
(PWM_IER2) Comparison 6 Update Interrupt Enable
| #define PWM_IER2_CMPU7 (0x1u << 23) |
(PWM_IER2) Comparison 7 Update Interrupt Enable
| #define PWM_IER2_UNRE (0x1u << 3) |
(PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable
| #define PWM_IER2_WRDY (0x1u << 0) |
(PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable
| #define PWM_IMR1_CHID0 (0x1u << 0) |
(PWM_IMR1) Counter Event on Channel 0 Interrupt Mask
| #define PWM_IMR1_CHID1 (0x1u << 1) |
(PWM_IMR1) Counter Event on Channel 1 Interrupt Mask
| #define PWM_IMR1_CHID2 (0x1u << 2) |
(PWM_IMR1) Counter Event on Channel 2 Interrupt Mask
| #define PWM_IMR1_CHID3 (0x1u << 3) |
(PWM_IMR1) Counter Event on Channel 3 Interrupt Mask
| #define PWM_IMR1_FCHID0 (0x1u << 16) |
(PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask
| #define PWM_IMR1_FCHID1 (0x1u << 17) |
(PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask
| #define PWM_IMR1_FCHID2 (0x1u << 18) |
(PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask
| #define PWM_IMR1_FCHID3 (0x1u << 19) |
(PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask
| #define PWM_IMR2_CMPM0 (0x1u << 8) |
(PWM_IMR2) Comparison 0 Match Interrupt Mask
| #define PWM_IMR2_CMPM1 (0x1u << 9) |
(PWM_IMR2) Comparison 1 Match Interrupt Mask
| #define PWM_IMR2_CMPM2 (0x1u << 10) |
(PWM_IMR2) Comparison 2 Match Interrupt Mask
| #define PWM_IMR2_CMPM3 (0x1u << 11) |
(PWM_IMR2) Comparison 3 Match Interrupt Mask
| #define PWM_IMR2_CMPM4 (0x1u << 12) |
(PWM_IMR2) Comparison 4 Match Interrupt Mask
| #define PWM_IMR2_CMPM5 (0x1u << 13) |
(PWM_IMR2) Comparison 5 Match Interrupt Mask
| #define PWM_IMR2_CMPM6 (0x1u << 14) |
(PWM_IMR2) Comparison 6 Match Interrupt Mask
| #define PWM_IMR2_CMPM7 (0x1u << 15) |
(PWM_IMR2) Comparison 7 Match Interrupt Mask
| #define PWM_IMR2_CMPU0 (0x1u << 16) |
(PWM_IMR2) Comparison 0 Update Interrupt Mask
| #define PWM_IMR2_CMPU1 (0x1u << 17) |
(PWM_IMR2) Comparison 1 Update Interrupt Mask
| #define PWM_IMR2_CMPU2 (0x1u << 18) |
(PWM_IMR2) Comparison 2 Update Interrupt Mask
| #define PWM_IMR2_CMPU3 (0x1u << 19) |
(PWM_IMR2) Comparison 3 Update Interrupt Mask
| #define PWM_IMR2_CMPU4 (0x1u << 20) |
(PWM_IMR2) Comparison 4 Update Interrupt Mask
| #define PWM_IMR2_CMPU5 (0x1u << 21) |
(PWM_IMR2) Comparison 5 Update Interrupt Mask
| #define PWM_IMR2_CMPU6 (0x1u << 22) |
(PWM_IMR2) Comparison 6 Update Interrupt Mask
| #define PWM_IMR2_CMPU7 (0x1u << 23) |
(PWM_IMR2) Comparison 7 Update Interrupt Mask
| #define PWM_IMR2_UNRE (0x1u << 3) |
(PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask
| #define PWM_IMR2_WRDY (0x1u << 0) |
(PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask
| #define PWM_ISR1_CHID0 (0x1u << 0) |
(PWM_ISR1) Counter Event on Channel 0
| #define PWM_ISR1_CHID1 (0x1u << 1) |
(PWM_ISR1) Counter Event on Channel 1
| #define PWM_ISR1_CHID2 (0x1u << 2) |
(PWM_ISR1) Counter Event on Channel 2
| #define PWM_ISR1_CHID3 (0x1u << 3) |
(PWM_ISR1) Counter Event on Channel 3
| #define PWM_ISR1_FCHID0 (0x1u << 16) |
(PWM_ISR1) Fault Protection Trigger on Channel 0
| #define PWM_ISR1_FCHID1 (0x1u << 17) |
(PWM_ISR1) Fault Protection Trigger on Channel 1
| #define PWM_ISR1_FCHID2 (0x1u << 18) |
(PWM_ISR1) Fault Protection Trigger on Channel 2
| #define PWM_ISR1_FCHID3 (0x1u << 19) |
(PWM_ISR1) Fault Protection Trigger on Channel 3
| #define PWM_ISR2_CMPM0 (0x1u << 8) |
(PWM_ISR2) Comparison 0 Match
| #define PWM_ISR2_CMPM1 (0x1u << 9) |
(PWM_ISR2) Comparison 1 Match
| #define PWM_ISR2_CMPM2 (0x1u << 10) |
(PWM_ISR2) Comparison 2 Match
| #define PWM_ISR2_CMPM3 (0x1u << 11) |
(PWM_ISR2) Comparison 3 Match
| #define PWM_ISR2_CMPM4 (0x1u << 12) |
(PWM_ISR2) Comparison 4 Match
| #define PWM_ISR2_CMPM5 (0x1u << 13) |
(PWM_ISR2) Comparison 5 Match
| #define PWM_ISR2_CMPM6 (0x1u << 14) |
(PWM_ISR2) Comparison 6 Match
| #define PWM_ISR2_CMPM7 (0x1u << 15) |
(PWM_ISR2) Comparison 7 Match
| #define PWM_ISR2_CMPU0 (0x1u << 16) |
(PWM_ISR2) Comparison 0 Update
| #define PWM_ISR2_CMPU1 (0x1u << 17) |
(PWM_ISR2) Comparison 1 Update
| #define PWM_ISR2_CMPU2 (0x1u << 18) |
(PWM_ISR2) Comparison 2 Update
| #define PWM_ISR2_CMPU3 (0x1u << 19) |
(PWM_ISR2) Comparison 3 Update
| #define PWM_ISR2_CMPU4 (0x1u << 20) |
(PWM_ISR2) Comparison 4 Update
| #define PWM_ISR2_CMPU5 (0x1u << 21) |
(PWM_ISR2) Comparison 5 Update
| #define PWM_ISR2_CMPU6 (0x1u << 22) |
(PWM_ISR2) Comparison 6 Update
| #define PWM_ISR2_CMPU7 (0x1u << 23) |
(PWM_ISR2) Comparison 7 Update
| #define PWM_ISR2_UNRE (0x1u << 3) |
(PWM_ISR2) Synchronous Channels Update Underrun Error
| #define PWM_ISR2_WRDY (0x1u << 0) |
(PWM_ISR2) Write Ready for Synchronous Channels Update
| #define PWM_LEBR1_LEBDELAY | ( | value | ) | ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) |
| #define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) |
(PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx
| #define PWM_LEBR1_LEBDELAY_Pos 0 |
| #define PWM_LEBR1_PWMHFEN (0x1u << 18) |
(PWM_LEBR1) PWMH Falling Edge Enable
| #define PWM_LEBR1_PWMHREN (0x1u << 19) |
(PWM_LEBR1) PWMH Rising Edge Enable
| #define PWM_LEBR1_PWMLFEN (0x1u << 16) |
(PWM_LEBR1) PWML Falling Edge Enable
| #define PWM_LEBR1_PWMLREN (0x1u << 17) |
(PWM_LEBR1) PWML Rising Edge Enable
| #define PWM_LEBR2_LEBDELAY | ( | value | ) | ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) |
| #define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) |
(PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx
| #define PWM_LEBR2_LEBDELAY_Pos 0 |
| #define PWM_LEBR2_PWMHFEN (0x1u << 18) |
(PWM_LEBR2) PWMH Falling Edge Enable
| #define PWM_LEBR2_PWMHREN (0x1u << 19) |
(PWM_LEBR2) PWMH Rising Edge Enable
| #define PWM_LEBR2_PWMLFEN (0x1u << 16) |
(PWM_LEBR2) PWML Falling Edge Enable
| #define PWM_LEBR2_PWMLREN (0x1u << 17) |
(PWM_LEBR2) PWML Rising Edge Enable
| #define PWM_OOV_OOVH0 (0x1u << 0) |
(PWM_OOV) Output Override Value for PWMH output of the channel 0
| #define PWM_OOV_OOVH1 (0x1u << 1) |
(PWM_OOV) Output Override Value for PWMH output of the channel 1
| #define PWM_OOV_OOVH2 (0x1u << 2) |
(PWM_OOV) Output Override Value for PWMH output of the channel 2
| #define PWM_OOV_OOVH3 (0x1u << 3) |
(PWM_OOV) Output Override Value for PWMH output of the channel 3
| #define PWM_OOV_OOVL0 (0x1u << 16) |
(PWM_OOV) Output Override Value for PWML output of the channel 0
| #define PWM_OOV_OOVL1 (0x1u << 17) |
(PWM_OOV) Output Override Value for PWML output of the channel 1
| #define PWM_OOV_OOVL2 (0x1u << 18) |
(PWM_OOV) Output Override Value for PWML output of the channel 2
| #define PWM_OOV_OOVL3 (0x1u << 19) |
(PWM_OOV) Output Override Value for PWML output of the channel 3
| #define PWM_OS_OSH0 (0x1u << 0) |
(PWM_OS) Output Selection for PWMH output of the channel 0
| #define PWM_OS_OSH1 (0x1u << 1) |
(PWM_OS) Output Selection for PWMH output of the channel 1
| #define PWM_OS_OSH2 (0x1u << 2) |
(PWM_OS) Output Selection for PWMH output of the channel 2
| #define PWM_OS_OSH3 (0x1u << 3) |
(PWM_OS) Output Selection for PWMH output of the channel 3
| #define PWM_OS_OSL0 (0x1u << 16) |
(PWM_OS) Output Selection for PWML output of the channel 0
| #define PWM_OS_OSL1 (0x1u << 17) |
(PWM_OS) Output Selection for PWML output of the channel 1
| #define PWM_OS_OSL2 (0x1u << 18) |
(PWM_OS) Output Selection for PWML output of the channel 2
| #define PWM_OS_OSL3 (0x1u << 19) |
(PWM_OS) Output Selection for PWML output of the channel 3
| #define PWM_OSC_OSCH0 (0x1u << 0) |
(PWM_OSC) Output Selection Clear for PWMH output of the channel 0
| #define PWM_OSC_OSCH1 (0x1u << 1) |
(PWM_OSC) Output Selection Clear for PWMH output of the channel 1
| #define PWM_OSC_OSCH2 (0x1u << 2) |
(PWM_OSC) Output Selection Clear for PWMH output of the channel 2
| #define PWM_OSC_OSCH3 (0x1u << 3) |
(PWM_OSC) Output Selection Clear for PWMH output of the channel 3
| #define PWM_OSC_OSCL0 (0x1u << 16) |
(PWM_OSC) Output Selection Clear for PWML output of the channel 0
| #define PWM_OSC_OSCL1 (0x1u << 17) |
(PWM_OSC) Output Selection Clear for PWML output of the channel 1
| #define PWM_OSC_OSCL2 (0x1u << 18) |
(PWM_OSC) Output Selection Clear for PWML output of the channel 2
| #define PWM_OSC_OSCL3 (0x1u << 19) |
(PWM_OSC) Output Selection Clear for PWML output of the channel 3
| #define PWM_OSCUPD_OSCUPH0 (0x1u << 0) |
(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0
| #define PWM_OSCUPD_OSCUPH1 (0x1u << 1) |
(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1
| #define PWM_OSCUPD_OSCUPH2 (0x1u << 2) |
(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2
| #define PWM_OSCUPD_OSCUPH3 (0x1u << 3) |
(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3
| #define PWM_OSCUPD_OSCUPL0 (0x1u << 16) |
(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0
| #define PWM_OSCUPD_OSCUPL1 (0x1u << 17) |
(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1
| #define PWM_OSCUPD_OSCUPL2 (0x1u << 18) |
(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2
| #define PWM_OSCUPD_OSCUPL3 (0x1u << 19) |
(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3
| #define PWM_OSS_OSSH0 (0x1u << 0) |
(PWM_OSS) Output Selection Set for PWMH output of the channel 0
| #define PWM_OSS_OSSH1 (0x1u << 1) |
(PWM_OSS) Output Selection Set for PWMH output of the channel 1
| #define PWM_OSS_OSSH2 (0x1u << 2) |
(PWM_OSS) Output Selection Set for PWMH output of the channel 2
| #define PWM_OSS_OSSH3 (0x1u << 3) |
(PWM_OSS) Output Selection Set for PWMH output of the channel 3
| #define PWM_OSS_OSSL0 (0x1u << 16) |
(PWM_OSS) Output Selection Set for PWML output of the channel 0
| #define PWM_OSS_OSSL1 (0x1u << 17) |
(PWM_OSS) Output Selection Set for PWML output of the channel 1
| #define PWM_OSS_OSSL2 (0x1u << 18) |
(PWM_OSS) Output Selection Set for PWML output of the channel 2
| #define PWM_OSS_OSSL3 (0x1u << 19) |
(PWM_OSS) Output Selection Set for PWML output of the channel 3
| #define PWM_OSSUPD_OSSUPH0 (0x1u << 0) |
(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0
| #define PWM_OSSUPD_OSSUPH1 (0x1u << 1) |
(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1
| #define PWM_OSSUPD_OSSUPH2 (0x1u << 2) |
(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2
| #define PWM_OSSUPD_OSSUPH3 (0x1u << 3) |
(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3
| #define PWM_OSSUPD_OSSUPL0 (0x1u << 16) |
(PWM_OSSUPD) Output Selection Set for PWML output of the channel 0
| #define PWM_OSSUPD_OSSUPL1 (0x1u << 17) |
(PWM_OSSUPD) Output Selection Set for PWML output of the channel 1
| #define PWM_OSSUPD_OSSUPL2 (0x1u << 18) |
(PWM_OSSUPD) Output Selection Set for PWML output of the channel 2
| #define PWM_OSSUPD_OSSUPL3 (0x1u << 19) |
(PWM_OSSUPD) Output Selection Set for PWML output of the channel 3
| #define PWM_SCM_PTRCS | ( | value | ) | ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) |
| #define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) |
(PWM_SCM) DMA Controller Transfer Request Comparison Selection
| #define PWM_SCM_PTRCS_Pos 21 |
| #define PWM_SCM_PTRM (0x1u << 20) |
(PWM_SCM) DMA Controller Transfer Request Mode
| #define PWM_SCM_SYNC0 (0x1u << 0) |
(PWM_SCM) Synchronous Channel 0
| #define PWM_SCM_SYNC1 (0x1u << 1) |
(PWM_SCM) Synchronous Channel 1
| #define PWM_SCM_SYNC2 (0x1u << 2) |
(PWM_SCM) Synchronous Channel 2
| #define PWM_SCM_SYNC3 (0x1u << 3) |
(PWM_SCM) Synchronous Channel 3
| #define PWM_SCM_UPDM | ( | value | ) | ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) |
| #define PWM_SCM_UPDM_MODE0 (0x0u << 16) |
(PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels
| #define PWM_SCM_UPDM_MODE1 (0x1u << 16) |
(PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels
| #define PWM_SCM_UPDM_MODE2 (0x2u << 16) |
(PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels
| #define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) |
(PWM_SCM) Synchronous Channels Update Mode
| #define PWM_SCM_UPDM_Pos 16 |
| #define PWM_SCUC_UPDULOCK (0x1u << 0) |
(PWM_SCUC) Synchronous Channels Update Unlock
| #define PWM_SCUP_UPR | ( | value | ) | ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) |
| #define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) |
(PWM_SCUP) Update Period
| #define PWM_SCUP_UPR_Pos 0 |
| #define PWM_SCUP_UPRCNT | ( | value | ) | ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) |
| #define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) |
(PWM_SCUP) Update Period Counter
| #define PWM_SCUP_UPRCNT_Pos 4 |
| #define PWM_SCUPUPD_UPRUPD | ( | value | ) | ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) |
| #define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) |
(PWM_SCUPUPD) Update Period Update
| #define PWM_SCUPUPD_UPRUPD_Pos 0 |
| #define PWM_SMMR_DOWN0 (0x1u << 16) |
(PWM_SMMR) DOWN Count
| #define PWM_SMMR_DOWN1 (0x1u << 17) |
(PWM_SMMR) DOWN Count
| #define PWM_SMMR_GCEN0 (0x1u << 0) |
(PWM_SMMR) Gray Count ENable
| #define PWM_SMMR_GCEN1 (0x1u << 1) |
(PWM_SMMR) Gray Count ENable
| #define PWM_SR_CHID0 (0x1u << 0) |
(PWM_SR) Channel ID
| #define PWM_SR_CHID1 (0x1u << 1) |
(PWM_SR) Channel ID
| #define PWM_SR_CHID2 (0x1u << 2) |
(PWM_SR) Channel ID
| #define PWM_SR_CHID3 (0x1u << 3) |
(PWM_SR) Channel ID
| #define PWM_SSPR_SPRD | ( | value | ) | ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) |
| #define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) |
(PWM_SSPR) Spread Spectrum Limit Value
| #define PWM_SSPR_SPRD_Pos 0 |
| #define PWM_SSPR_SPRDM (0x1u << 24) |
(PWM_SSPR) Spread Spectrum Counter Mode
| #define PWM_SSPUP_SPRDUP | ( | value | ) | ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) |
| #define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) |
(PWM_SSPUP) Spread Spectrum Limit Value Update
| #define PWM_SSPUP_SPRDUP_Pos 0 |
| #define PWM_VERSION_MFN_Msk (0x7u << PWM_VERSION_MFN_Pos) |
(PWM_VERSION) Metal Fix Number
| #define PWM_VERSION_MFN_Pos 16 |
| #define PWM_VERSION_VERSION_Msk (0xfffu << PWM_VERSION_VERSION_Pos) |
(PWM_VERSION) Version of the Hardware Module
| #define PWM_VERSION_VERSION_Pos 0 |
| #define PWM_WPCR_WPCMD | ( | value | ) | ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) |
| #define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) |
(PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'.
| #define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) |
(PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'.
Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface.
| #define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) |
(PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'.
| #define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) |
(PWM_WPCR) Write Protection Command
| #define PWM_WPCR_WPCMD_Pos 0 |
| #define PWM_WPCR_WPKEY | ( | value | ) | ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) |
| #define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) |
(PWM_WPCR) Write Protection Key
| #define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) |
(PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0
| #define PWM_WPCR_WPKEY_Pos 8 |
| #define PWM_WPCR_WPRG0 (0x1u << 2) |
(PWM_WPCR) Write Protection Register Group 0
| #define PWM_WPCR_WPRG1 (0x1u << 3) |
(PWM_WPCR) Write Protection Register Group 1
| #define PWM_WPCR_WPRG2 (0x1u << 4) |
(PWM_WPCR) Write Protection Register Group 2
| #define PWM_WPCR_WPRG3 (0x1u << 5) |
(PWM_WPCR) Write Protection Register Group 3
| #define PWM_WPCR_WPRG4 (0x1u << 6) |
(PWM_WPCR) Write Protection Register Group 4
| #define PWM_WPCR_WPRG5 (0x1u << 7) |
(PWM_WPCR) Write Protection Register Group 5
| #define PWM_WPSR_WPHWS0 (0x1u << 8) |
(PWM_WPSR) Write Protect HW Status
| #define PWM_WPSR_WPHWS1 (0x1u << 9) |
(PWM_WPSR) Write Protect HW Status
| #define PWM_WPSR_WPHWS2 (0x1u << 10) |
(PWM_WPSR) Write Protect HW Status
| #define PWM_WPSR_WPHWS3 (0x1u << 11) |
(PWM_WPSR) Write Protect HW Status
| #define PWM_WPSR_WPHWS4 (0x1u << 12) |
(PWM_WPSR) Write Protect HW Status
| #define PWM_WPSR_WPHWS5 (0x1u << 13) |
(PWM_WPSR) Write Protect HW Status
| #define PWM_WPSR_WPSWS0 (0x1u << 0) |
(PWM_WPSR) Write Protect SW Status
| #define PWM_WPSR_WPSWS1 (0x1u << 1) |
(PWM_WPSR) Write Protect SW Status
| #define PWM_WPSR_WPSWS2 (0x1u << 2) |
(PWM_WPSR) Write Protect SW Status
| #define PWM_WPSR_WPSWS3 (0x1u << 3) |
(PWM_WPSR) Write Protect SW Status
| #define PWM_WPSR_WPSWS4 (0x1u << 4) |
(PWM_WPSR) Write Protect SW Status
| #define PWM_WPSR_WPSWS5 (0x1u << 5) |
(PWM_WPSR) Write Protect SW Status
| #define PWM_WPSR_WPVS (0x1u << 7) |
(PWM_WPSR) Write Protect Violation Status
| #define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) |
(PWM_WPSR) Write Protect Violation Source
| #define PWM_WPSR_WPVSRC_Pos 16 |
| #define PWMCH_NUM_NUMBER 4 |
| #define PWMCMP_NUMBER 8 |
Pwm hardware registers.


Note: There are two ways to navigate this guide:
Chapter 1: OverviewWhat Is Java Plug-in? What Does It Support? Chapter 2: Using the Conventional Applet Tag Chapter 3: Using OBJECT, EMBED and APPLET Tags in Java Plug-in Chapter 4: Using the HTML Converter to Convert Applet Tags for Java Plug-in Chapter 5: Proxy Configuration Chapter 6: Protocol Support: HTTP, HTTPS, FTP, GOPHER, SOCKS, and NTLM Chapter 7: Cookie Support Chapter 8: Applet Caching Chapter 9: Using the Java Plug-in Control Panel to Set Plug-in Behavior/Options
Chapter 10: Installation for Conventional Applets (Microsoft Windows Only) Chapter 11: Intranet With OBJECT/EMBED Tag Chapter 12: Internet Deployment Chapter 13: Silent Installation Chapter 14: Jar Indexing Chapter 15: Java Server Pages
OBJECT/EMBED
Chapter 16: OverviewApplet Security Basics Chapter 17: How RSA Signed Applet Verification Works in Java Plug-in Chapter 18: How to Sign Applets Using RSA-Signed Certificates Chapter 19: How to Deploy RSA-Signed Applets in Java Plug-in
Chapter 20: Debugging Support Chapter 21: Java Plug-in Console Chapter 22: Tracing and Logging
Chapter 23: Supporting Multiple Versions of JRE/Java Plug-in Chapter 24: Java-to-JavaScript Communication Chapter 25: JavaScript-to-Java Communication (Scripting) Chapter 26: Deploying Java Extensions Chapter 27: Applet Persistence API Chapter 28: Special Applet Attributes
Appendix 1: Netscape 6 Appendix 2: Frequently Asked Questions (FAQ) Basic Information FAQ Developer Information FAQ Troubleshooting FAQ About Applet Tag Support in Java Plug-in Appendix 3: More About HTML Converter Appendix 4: Microsoft VM and Java 2 Applet Compatibility Issues Appendix 5: Complete ExampleDeploying Java Media Framework as Java Extension Appendix 6: Sun-Supported Specification-Version and Implemenation-Version Formats
Specification-Version
Implemenation-Version


Before Change
// Convert data to a list of arrays matching SRM input.
// Each element is a matrix of voxels by TRs.
movie_data = list(movie_data["movie_data_lh"])
subjects = len(movie_data)
// Z-score the data
for subject in range(subjects):
movie_data[subject] = stats.zscore(movie_data[subject], axis=1, ddof=1)
After Change
// Load the input data that contains the movie stimuli for unsupervised training with SRM
movie_file = scipy.io.loadmat("data/movie_data.mat")
movie_data_left = movie_file["movie_data_lh"]
movie_data_right = movie_file["movie_data_rh"]
subjects = movie_data_left.shape[2]
// Convert data to a list of arrays matching SRM input.
// Each element is a matrix of voxels by TRs.
// Also, concatenate data from both hemispheres in the brain.
movie_data = []
for s in range(subjects):
movie_data.append(np.concatenate([movie_data_left[:, :, s], movie_data_right[:, :, s]], axis=0))
// Z-score the data
for subject in range(subjects):
movie_data[subject] = stats.zscore(movie_data[subject], axis=1, ddof=1)
// Run SRM with the movie data


Draining the happy soup - Part 3
In Part 2 we had a look at the plan. Now it is time to put it into motion. Let's setup our project structure
Put some order in your files
Our goal is to distribute happy soup artifacts into packages. In this installment we setup the directory structure for that. Sticking to a clear structure makes it easier to get a step closer to package Nirvana step by step.
Let me run through some of the considerations:
- I'll keep all packages inside a single directory structure. Name the root after your org. What might pose a challenge is to name it
sfdx
- too close to that hidden directory.sfdx
that does exist in your home directory and might exist in the project directories - You could keep the whole tree in a single repository or subject each package directory to its own repository. I'd prefer the later, since it allows a developer to pull only the relevant directories from source control (That's Option B)
- The base directory, containing the artifacts that won't be packaged shall be named
HappySoup
. While it is a rather colloquial term, it is well established - I'm a little old fashioned when it comes to directory names: no spaces, double byte characters (that includes 💩) or special characters
- You need to pay attention to
sfdx-project.json
and.sfdx
as well as.gitignore
. More and that below - When you have mixed OS developer communities using Windows, MAC or Linux, directory delimiters could become a headache. My tongue-in-cheek recommendation for Windows would be to use WSL
Key files and directories
Initially you want to divide, but not yet package. So your projects need to know about each other. Higher level packages, that in future will depend on base packages need to know about them and each package needs to know about the HappySoup
. To get there I adjust my sfdx-project.json
:
{
"packageDirectories" : [
{ "path": "force-app", "default": true},
{ "path" : "../ObjectBase/force-app" },
{ "path" : "../HappySoup/force-app" }
],
"namespace": "",
"sfdcLoginUrl" : "https://login.salesforce.com",
"sourceApiVersion": "45.0"
}
The key here are the relative path entries like ../HappySoup/force-app
. When you use sfdx force:source:push
the content gets pushed to your scratch org, so it is complete. When you use sfdx force:source:pull
changes you made are copied down to the default path, so the adjacent projects remain as is.
When using pull
and push
from VSCode it will use the default user name configured for SFDX. To ensure that you don't push to or pull from the wrong place, you need to create one scratch org each using sfdx force:org:create --f config/project-scratch-def.json -a [ScratchOrgAlias]
and then execute sfdx force:config:set defaultusername=[ScratchOrgAlias]
.
The command will create a .sfdx
directory and config files inside in your project. Unless all developers checking out that repository use the same aliases (unlikely), you want to add .sfdx
to your .gitignore file.
Now you are all set to move files from the happy soup to future package directories. With the relative path in your sfdx-project.json
no packaging is required now and you still can get a fully functioning scratch org.
One pro tip: instead of relying on individual scratch definition files, you might opt to use the one in the happy soup, so all your scratches have the same shape.
Next stop: building the solution before you package. As usual YMMV.
Posted by Stephan H Wissel on 22 February 2019 | Comments (0) | categories: Salesforce SFDX


“May your trails be crooked, winding, dangerous, leading to the most amazing view. May your mountains rise into and above the clouds.” – Edward Abbey
Here's to the mountaineer in you ready to face all the challenges in your way to ultimate glory, are you ready for this summer's contest too ?


As usual for controlling CRTs, the VIC builds the video frame line by line. The line number and the number of clock cycles per line are constant for every VIC type. The VIC works character-based, every character consists of a matrix of 8×8 pixels, so a text line is made up of 8 pixel lines. 40×25 text characters are displayed in the text based modes, 320×200 or 160×200 pixels in the bitmap modes. In this article, the specification of a position on the screen is done with the raster line number as the Y coordinate (RASTER, register $d011/$d012) and a X coordinate that corresponds to the sprite coordinate system. When specifying the time of a VIC memory access or an internal operation in the VIC, the raster line number is used as Y coordinate and the number of the clock cycle within the line as X coordinate. As previously mentioned, 8 pixels make a clock cycle, so the specification of a sprite X coordinate is eight times more precise than that of a cycle number. The graphics are displayed in an unmovable window in the middle of the visible screen area, the "display window". The area outside the display window is covered by the screen border and is displayed in the border color (EC, register $d020). You can also turn off the border partially or completely with some little tweaking; then you see that the display window is part of a "display column" that is made up by the linear extension of the display window to the top and bottom. With that you can divide the border in an upper/lower border and a left/right border. The visible screen area is surrounded by blanking intervals in which the video signal is turned off and in which the raster beam returns to the start of the next line or the start of the frame, respectively. The following figure (not in scale) illustrates the last paragraph: The height and width of the display window can each be set to two different values with the bits RSEL and CSEL in the registers $d011 and $d016:
If RSEL=0 the upper and lower border are each extended by 4 pixels into the display window, if CSEL=0 the left border is extended by 7 pixels and the right one by 9 pixels. The position of the display window and its resolution do not change, RSEL/CSEL only switch the starting and ending position of the border display. The size of the video matrix also stays constantly at 40×25 characters. With XSCROLL/YSCROLL (bits 0-2 of registers $d011 (XSCROLL) and $d016 (YSCROLL)), the position of the graphics inside the display window can be scrolled in single-pixel units up to 7 pixels to the right and to the bottom. This can be used for soft scrolling. The position of the display window itself doesn't change. To keep the graphics aligned with the window, X/YSCROLL have to be 0 and 3 for 25 lines/40 columns and both 7 for 24 lines/38 columns. The dimensions of the video display for the different VIC types are as follows:
If you are wondering why the first visible X coordinates seem to come after the last visible ones: This is because for the reference point to mark the beginning of a raster line, the occurrence of the raster IRQ has been chosen, which doesn't coincide with X coordinate 0 but with the coordinate given as "First X coo. of a line". The X coordinates run up to $1ff (only $1f7 on the 6569) within a line, then comes X coordinate 0. This is explained in more detail in the explanation of the structure of a raster line. As already mentioned, the VIC needs 40 additional bus cycles when fetching the character pointers (i.e. the character codes of one text line from the video matrix), because the 63-65 bus cycles available for transparent (unnoticed by the processor) access for the VIC during the first clock phases within a line are not sufficient to read both the character pointers and the pixel data for the characters from memory. For this reason, the VIC uses the mechanism described in section 2.4.3. to "stun" the processor for 40-43 cycles during the first pixel line of each text line to read the character pointers. The raster lines in which this happens are usually called "Bad Lines" ("bad" because they stop the processor and thus slow down the computer and lead to problems if the precise timing of a program is essential, e.g. for the transmission of data to/from a floppy drive). The character pointer access is also done in the bitmap modes, because the video matrix data is then used for color information. Normally, every eighth line inside the display window, starting with the very first line of the graphics, is a Bad Line, i.e the first raster lines of each text line. So the position of the Bad Lines depends on the YSCROLL. As you will see later, the whole graphics display and memory access scheme depend completely on the position of the Bad Lines. It is therefore necessary to introduce a more general definition, namely that of a "Bad Line Condition":
This definition has to be taken literally. You can generate and take away a Bad Line condition multiple times within an arbitrary raster line in the range of $30-$f7 by modifying YSCROLL, and thus make every raster line within the display window completely or partially a Bad Line, or trigger or suppress all the other functions that are connected with a Bad Line Condition. If YSCROLL=0, a Bad Line Condition occurs in raster line $30 as soon as the DEN bit (register $d011, bit 4) is set (for more about the DEN bit, see section 3.10.). The following three sections describe the function units that are used for displaying the graphics. Section 3.6. explains the the memory interface that is used to read the graphics data and the timing of the accesses within a raster line. Section 3.7. is about the display unit that converts the text and bitmap graphics data into colors and generates the addresses for the memory access. Section 3.8. covers the sprites and their address generation. |


Go to index page.
gifrotat
A program to rotate a GIF image by a specified angle.
Usage:
gifrotat -a Angle [-q] [-s Width Height] [-h] gif-file
If no gif-file is given, GifRotat will try to read a GIF file from stdin.
Memory required:
Screen (of source image).
Options:
- -a Angle
- Specifies the angle to rotate in degrees with respect to
the X (horizontal) axis.
- [-q]
- Quiet mode. Defaults off on MSDOS, on under UNIX. Controls printout
of running scan lines. Use -q- to invert.
- [-s Width Height]
- Since the rotated image will have the same image size as
the original, some parts of the image will by clipped out and lost. By
specifing a (bigger) size explicitly using the `-s' option, these parts
may be saved.
- [-h]
- Print one line of command line help, similar to Usage above.
Notes:
The image is rotated around its center. No filtering is performed on the
output, which have the same color map as the input. This is mainly since
filtering would require color quantization which is very memory/time intensive
and out of MSDOS memory limits even for small images.
Author:
Gershon Elber
Eric S. Raymond <esr@snark.thyrsus.com>