| Note: After ADC conversion is done, SW needs to wait at least one ADC clock before to set this bit high again. | ||
| [13:12] | TMSEL | Select A/D Enable Time-out Source |
| Selects one of four timer events source to trigger ADC starts to convert. | ||
| 00 = TMR0. | ||
| 01 = TMR1. | ||
| 10 = TMR2. | ||
| 11 = TMR3. | ||
| [15] | TMTRGMOD | Timer Event Trigger ADC Conversion Mode |
| 0 = Timer event trigger ADC conversion disabled. | ||
| 1 = ADC can be start to conversion by timer out event. | ||
| Note1: setting TMSEL (ADC_CTL[13:12]) to select timer event from timer0~3. | ||
| Note2: If timer event is used as ADC trigger source, ADCEN (ADC_CTL[0]) needs to be disabled. | ||
| [17:16] | REFSEL | Reference Voltage Source Selection |
| 00 = Select as reference voltage. | ||
| 01 = Select as reference voltage. | ||
| 10 = Select as reference voltage. | ||
| 11 = Reserved. | ||
| [19:18] | RESSEL | Resolution Selection |
| 00 = 6-bit. ADC result will put at RESULT (ADC_DATx[5:0]). | ||
| 01 = 8-bit. ADC result will put at RESULT (ADC_DATx[7:0]). | ||
| 10 = 10-bit. ADC result will put at RESULT (ADC_DATx[9:0]). | ||
| 11 = 12-bit. ADC result will put at RESULT (ADC_DATx[11:0]). | ||
| [31:24] | TMPDMACNT | Timer Event PDMA Count |
| When each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting. | ||
| Note: The total amount of PDMA transferring data should be set in PDMA byte count register | ||
| When PDMA finish is set, ADC will not be enabled and will start transfer even though the timer event occurred. |
| PWM_T::CTL0 |
[0x0000] PWM0 Control Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | CTRLDn | Center Re-load |
| Each bit n controls the corresponding PWM0 channel n. | ||
| In up-down counter type, PERIOD will load to PBUF at the end point of each period | ||
| CMPDAT will load to CMPBUF at the center point of a period | ||
| [21:16] | IMMLDENn | Immediately Load Enable Bits |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = PERIOD will load to PBUF at the end point of each period | ||
| CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. | ||
| 1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. | ||
| Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. | ||
| [30] | DBGHALT | ICE Debug Mode Counter Halt (Write Protect) |
| If counter halt is enabled, PWM0 all counters will keep current value until exit ICE debug mode. | ||
| 0 = ICE debug mode counter halt Disabled. | ||
| 1 = ICE debug mode counter halt Enabled. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. | ||
| [31] | DBGTRIOFF | ICE Debug Mode Acknowledge Disable Bit (Write Protect) |
| 0 = ICE debug mode acknowledgement effects PWM0 output. | ||
| PWM0 pin will be forced as tri-state while ICE debug mode acknowledged. | ||
| 1 = ICE debug mode acknowledgement disabled. | ||
| PWM0 pin will keep output no matter ICE debug mode acknowledged or not. | ||
| Note: This bit is write protected. Refer to SYS_REGLCTL register. |
| ACMP_T::CTL0 |
[0x0000] Analog Comparator 0 Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ACMPEN | Comparator Enable Bit |
| 0 = Comparator 0 Disabled. | ||
| 1 = Comparator 0 Enabled. | ||
| [1] | ACMPIE | Comparator Interrupt Enable Bit |
| 0 = Comparator 0 interrupt Disabled. | ||
| 1 = Comparator 0 interrupt Enabled | ||
| If WKEN (ACMP_CTL0[31]) is set to 1, the wake-up interrupt function will be enabled as well. | ||
| [2] | HYSEN | Comparator Hysteresis Enable Bit |
| 0 = Comparator 0 hysteresis Disabled. | ||
| 1 = Comparator 0 hysteresis Enabled. | ||
| [5:4] | NEGSEL | Comparator Negative Input Selection |
| 00 = ACMP0_N pin. | ||
| 01 = Internal comparator reference voltage (CRV). | ||
| 10 = Internal reference voltage (Int_VREF). | ||
| 11 = AVSS pin. | ||
| [31] | WKEN | Power-down Wake-up Enable Bit |
| 0 = Wake-up function Disabled. | ||
| 1 = Wake-up function Enabled. |
| PWM_T::CTL1 |
[0x0004] PWM0 Control Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | CNTTYPE0 | PWM0 Counter Behavior Type 0 |
| Each bit n controls corresponding PWM0 channel n. | ||
| 00 = Up counter type (supports in capture mode). | ||
| 01 = Down count type (supports in capture mode). | ||
| 10 = Up-down counter type. | ||
| 11 = Reserved. | ||
| [5:4] | CNTTYPE2 | PWM0 Counter Behavior Type 2 |
| Each bit n controls corresponding PWM0 channel n. | ||
| 00 = Up counter type (supports in capture mode). | ||
| 01 = Down count type (supports in capture mode). | ||
| 10 = Up-down counter type. | ||
| 11 = Reserved. | ||
| [9:8] | CNTTYPE4 | PWM0 Counter Behavior Type 4 |
| Each bit n controls corresponding PWM0 channel n. | ||
| 00 = Up counter type (supports in capture mode). | ||
| 01 = Down count type (supports in capture mode). | ||
| 10 = Up-down counter type. | ||
| 11 = Reserved. | ||
| [26:24] | PWMMODEn | PWM0 Mode |
| Each bit n controls the corresponding PWM0 channel n. | ||
| 0 = PWM0 independent mode. | ||
| 1 = PWM0 complementary mode. | ||
| Note: When operating in group function, these bits must all set to the same mode. |
| I2C_T::CTL2 |
[0x0040] I2C Control Register 2
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WKUPEN | I2C Wake-up Function Enable Bit |
| 0 = I2C wake-up function Disabled. | ||
| 1 = I2C wake-up function Enabled. | ||
| [1] | OVIEN | I2C Overrun Interrupt Control Bit |
| 0 = Overrun event interrupt Disabled. | ||
| 1 = Send a interrupt to system when the TWOLVBUF bit is enabled and there is overrun event in received buffer. | ||
| [2] | URIEN | I2C Under run Interrupt Control Bit |
| 0 = Under run event interrupt Disabled. | ||
| 1 = Send a interrupt to system when the TWOLVBUF bit is enabled and there is under-run event happened in transmitted buffer. | ||
| [4] | TWOLVBUF | Two Level Buffer Enable Bit |
| 0 = Two level buffer Disabled. | ||
| 1 = Two level buffer Enabled. | ||
| [5] | NOSTRETCH | I2C BuS Stretch |
| 0 = The I2C SCL bus is stretched by hardware if the SI (I2C_CTL[4]) is not cleared. | ||
| 1 = The I2C SCL bus is not stretched by hardware if the SI is not cleared. | ||
| [6] | DATMODE | Data Mode Enable Bit |
| 0 = Data mode Disabled. | ||
| 1 = Data mode Enabled. | ||
| [7] | MSDAT | Master or Slave in Data Mode Enable Control |
| 0 = Master writes data to device. | ||
| 1 = Slave reads data from device. |
| PDMA_CH_T::CTLn |
[0x0000] PDMA channel n Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CHEN | PDMA Channel Enable Bit |
| Setting this bit to 1 enables PDMA operation | ||
| If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. | ||
| Note: SWRST (PDMA_CTLn[1], n= 1~4) will clear this bit. | ||
| [1] | SWRST | Software Engine Reset |
| 0 = No effect. | ||
| 1 = Reset the internal state machine, pointers and internal buffer | ||
| The contents of all control registers will not be cleared | ||
| This bit will be automatically cleared after few clock cycles. | ||
| [5:4] | SASEL | Transfer Source Address Direction Selection |
| 00 = Transfer Source address is incremented successively. | ||
| 01 = Reserved. | ||
| 10 = Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations). | ||
| 11 = Transfer Source address is wrap around (When the PDMA_CCNT is equal to 0, the PDMA_CSA and PDMA_CCNT registers will be updated by PDMA_SA and PDMA_CNT automatically | ||
| PDMA will start another transfer without user trigger until CHEN disabled | ||
| When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address). | ||
| [7:6] | DASEL | Transfer Destination Address Direction Selection |
| 00 = Transfer Destination address is incremented successively. | ||
| 01 = Reserved. | ||
| 10 = Transfer Destination address is fixed | ||
| (This feature can be used when data transferred from multiple sources to a single destination). | ||
| 11 = Transfer Destination address is wrapped around (When the PDMA_CCNT is equal to 0, the PDMA_CDA and PDMA_CCNT registers will be updated by PDMA_DA and PDMA_CNT automatically | ||
| PDMA will start another transfer without user trigger until CHEN disabled | ||
| When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address). | ||
| [12] | TOUTEN | Time-out Enable Bit |
| This bit will enable PDMA Time-out counter (PDMA_TOCn, n=1~4) | ||
| While this counter counts to 0, the TOUTIF (PDMA_INTSTSn[6], n=1~4) will be set. | ||
| 0 = PDMA internal counter Disabled. | ||
| 1 = PDMA internal counter Enabled. | ||
| [20:19] | TXWIDTH | Transfer Width Selection |
| This field is used for transfer width. | ||
| 00 = One word (32-bit) is transferred for every PDMA operation. | ||
| 01 = One byte (8-bit) is transferred for every PDMA operation. | ||
| 10 = One half-word (16-bit) is transferred for every PDMA operation. | ||
| 11 = Reserved. | ||
| [23] | TRIGEN | Trigger Enable Bit |
| 0 = No effect. | ||
| 1 = PDMA data transfer Enabled. | ||
| Note1: When PDMA transfer completed, this bit will be cleared automatically. | ||
| Note2: If the bus error occurs, all PDMA transfer will be stopped | ||
| User must reset all PDMA channels, and then trigger again. |
| UART_T::CTRL |
[0x0004] UART Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXRST | RX Field Software Reset |
| When RXRST (UART_CTL[0]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the RX internal state machine and pointers. | ||
| Note: This bit will automatically clear at least 3 UART peripheral clock cycles. | ||
| [1] | TXRST | TX Field Software Reset |
| When TXRST (UART_CTL[1]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. | ||
| 0 = No effect. | ||
| 1 = Reset the TX internal state machine and pointers. | ||
| Note: This bit will automatically clear at least 3 UART peripheral clock cycles | ||
| [2] | RXOFF | Receiver Disable Bit |
| 0 = Receiver Enabled. | ||
| 1 = Receiver Disabled. | ||
| Note1: In RS-485 NMM mode, user can set this bit to receive data before detecting address byte. | ||
| Note2: In RS-485 AAD mode, this bit will be setting to 1 automatically. | ||
| Note3: In RS-485 AUD mode and LIN break + sync +PID header mode, hardware will control data automatically, so don't fill any value to this bit. | ||
| [3] | TXOFF | Transfer Disable Bit |
| 0 = Transfer Enabled. | ||
| 1 = Transfer Disabled. | ||
| [4] | ATORTSEN | nRTS Auto-flow Control Enable Bit |
| 0 = nRTS auto-flow control Disabled. | ||
| 1 = nRTS auto-flow control Enabled. | ||
| Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_TLCTL[13:12]), the UART will de-assert nRTS signal. | ||
| [5] | ATOCTSEN | nCTS Auto-flow Control Enable Bit |
| 0 = nCTS auto-flow control Disabled. | ||
| 1 = nCTS auto-flow control Enabled. | ||
| Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). | ||
| [6] | RXDMAEN | RX DMA Enable Bit |
| This bit can enable or disable RX DMA service. | ||
| 0 = RX DMA Disabled. | ||
| 1 = RX DMA Enabled. | ||
| [7] | TXDMAEN | TX DMA Enable Bit |
| This bit can enable or disable TX DMA service. | ||
| 0 = TX DMA Disabled. | ||
| 1 = TX DMA Enabled. | ||
| [8] | FTOEN | Frame Time Out Enable Bit |
| This bit is used to enable the timer counter even the FIFO is still empty. | ||
| 0 = Frame time out Disabled. | ||
| 1 = Frame time out Enabled. | ||
| [12] | ABRDEN | Auto-baud Rate Detect Enable Bit |
| 0 = Auto-baud rate detect function Disabled. | ||
| 1 = Auto-baud rate detect function Enabled. | ||
| Note: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (ABRIF) will be generated (If ABRIEN (UART_IER [7]) be enabled). | ||
| [14:13] | ABRDBITS | Auto-baud Rate Detect Bit Length |
| 00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. | ||
| 01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. | ||
| 10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. | ||
| 11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. | ||
| Note: The calculation of bit number includes the START bit. |
| PDMA_CH_T::DAn |
| DMA_CRC_T::DAT |
[0x0080] CRC Write Data Register
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | DATA | CRC Write Data Bits |
| When operating in CPU mode, user can write data to this field to perform CRC operation. | ||
| When operating in DMA mode, this field indicates the DMA read data from memory and cannot be written by user. | ||
| Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register are only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register are only DATA[15:0] bits. |
| UART_T::DAT |
[0x0000] UART Receive/Transmit Buffer Register
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DAT | Receive /Transmit Buffer |
| Write Operation: | ||
| By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_DAT. | ||
| Read Operation: | ||
| By reading this register, the UART will return an 8-bit data received from receiving FIFO. |
| SC_T::DAT |
[0x0000] SC Receive/Transmit Holding Buffer Register.
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | DAT | Receive/Transmit Holding Buffer |
| Write Operation: | ||
| By writing data to DAT, the SC will send out an 8-bit data. | ||
| Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed. | ||
| Read Operation: | ||
| By reading DAT, the SC will return an 8-bit received data. |
| I2C_T::DAT |
| ADC_T::DAT |
[0x0000] A/D Data Register 0 ~ 17
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | RESULT | A/D Conversion Result |
| This field contains conversion result of ADC. | ||
| [16] | VALID | Valid Flag |
| This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read. | ||
| 0 = Data in RESULT (ADC_DAT[11:0]) bits is not valid. | ||
| 1 = Data in RESULT (ADC_DAT[11:0]) bits is valid. | ||
| [17] | OV | over Run Flag |
| If converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register, OV is set to 1 | ||
| It is cleared by hardware after the ADC_DATx register is read. | ||
| 0 = Data in RESULT (ADC_DAT[11:0]) is recent conversion result. | ||
| 1 = Data in RESULT (ADC_DAT[11:0]) overwrote. |
| GPIO_T::DATMSK |
[0x000c] Pn Data Output Write Mask
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DMASK0 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [1] | DMASK1 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [2] | DMASK2 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [3] | DMASK3 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [4] | DMASK4 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [5] | DMASK5 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [6] | DMASK6 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [7] | DMASK7 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [8] | DMASK8 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [9] | DMASK9 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [10] | DMASK10 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [11] | DMASK11 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [12] | DMASK12 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [13] | DMASK13 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [14] | DMASK14 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [15] | DMASK15 | Port A-f Pin[N] Data Output Write Mask |
| These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit | ||
| When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected | ||
| If the write signal is masked, writing data to the protect bit is ignored. | ||
| 0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. | ||
| 1 = Corresponding DOUT (Px_DOUT[n]) bit protected. | ||
| Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. | ||
| Note2: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note3: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
| GP_DB_T::DBCTL |
[0x0180] Interrupt De-bounce Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | DBCLKSEL | De-bounce Sampling Cycle Selection |
| 0000 = Sample interrupt input once per 1 clocks. | ||
| 0001 = Sample interrupt input once per 2 clocks. | ||
| 0010 = Sample interrupt input once per 4 clocks. | ||
| 0011 = Sample interrupt input once per 8 clocks. | ||
| 0100 = Sample interrupt input once per 16 clocks. | ||
| 0101 = Sample interrupt input once per 32 clocks. | ||
| 0110 = Sample interrupt input once per 64 clocks. | ||
| 0111 = Sample interrupt input once per 128 clocks. | ||
| 1000 = Sample interrupt input once per 256 clocks. | ||
| 1001 = Sample interrupt input once per 2*256 clocks. | ||
| 1010 = Sample interrupt input once per 4*256 clocks. | ||
| 1011 = Sample interrupt input once per 8*256 clocks. | ||
| 1100 = Sample interrupt input once per 16*256 clocks. | ||
| 1101 = Sample interrupt input once per 32*256 clocks. | ||
| 1110 = Sample interrupt input once per 64*256 clocks. | ||
| 1111 = Sample interrupt input once per 128*256 clocks. | ||
| [4] | DBCLKSRC | De-bounce Counter Clock Source Selection |
| 0 = De-bounce counter clock source is the HCLK. | ||
| 1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). | ||
| [5] | ICLKON | Interrupt Clock on Mode |
| 0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. | ||
| 1 = All I/O pins edge detection circuit is always active after reset. | ||
| Note: It is recommended to disable this bit to save system power if no special application concern. |
| GPIO_T::DBEN |
[0x0014] Pn De-Bounce Enable Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DBEN0 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [1] | DBEN1 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [2] | DBEN2 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [3] | DBEN3 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [4] | DBEN4 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [5] | DBEN5 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [6] | DBEN6 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [7] | DBEN7 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [8] | DBEN8 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [9] | DBEN9 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [10] | DBEN10 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [11] | DBEN11 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [12] | DBEN12 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [13] | DBEN13 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [14] | DBEN14 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [15] | DBEN15 | Port A-f Pin[N] Input Signal De-bounce Enable Bit |
| The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit | ||
| If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt | ||
| The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). | ||
| 0 = Px.n de-bounce function Disabled. | ||
| 1 = Px.n de-bounce function Enabled. | ||
| The de-bounce function is valid only for edge triggered interrupt | ||
| If the interrupt mode is level triggered, the de-bounce enable bit is ignored. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
| FMC_T::DFBA |
[0x0014] Data Flash Base Address
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | DFBA | Data Flash Base Address |
| This register indicates Data Flash start address. It is a read only register. | ||
| The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1. | ||
| This register is valid when DFEN (CONFIG0[0]) =0 . |
| GPIO_T::DINOFF |
[0x0004] Pn Digital Input Path Disable Control
| Bits | Field | Descriptions |
|---|---|---|
| [16] | DINOFF0 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [17] | DINOFF1 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [18] | DINOFF2 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [19] | DINOFF3 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [20] | DINOFF4 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [21] | DINOFF5 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [22] | DINOFF6 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [23] | DINOFF7 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [24] | DINOFF8 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [25] | DINOFF9 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [26] | DINOFF10 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [27] | DINOFF11 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [28] | DINOFF12 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [29] | DINOFF13 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [30] | DINOFF14 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [31] | DINOFF15 | Port A-f Pin[N] Digital Input Path Disable Bit |
| Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled | ||
| If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. | ||
| 0 = Px.n digital input path Enabled. | ||
| 1 = Px.n digital input path Disabled (digital input tied to low). | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
| DMA_CRC_T::DMABCNT |
| DMA_CRC_T::DMACBCNT |
[0x001c] CRC DMA Current Transfer Byte Count Register
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CBCNT | CRC DMA Current Remained Byte Count (Read Only) |
| This field indicates the current remained byte count of CRC DMA. | ||
| Note: Setting the CRCRST (CRC_CTL[1]) bit to 1 will clear this register value. |
| DMA_CRC_T::DMACSA |
| DMA_CRC_T::DMAINTEN |
[0x0020] CRC DMA Interrupt Enable Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TABTIEN | CRC DMA Read/Write Target Abort Interrupt Enable Bit |
| Enable this bit will generate the CRC DMA Target Abort interrupt signal while TABTIF (CRC_DMAINTSTS[0]) bit is set to 1. | ||
| 0 = Target abort interrupt Disabled during CRC DMA transfer. | ||
| 1 = Target abort interrupt Enabled during CRC DMA transfer. | ||
| [1] | TDIEN | CRC DMA Block Transfer Done Interrupt Enable Bit |
| Enable this bit will generate the CRC DMA Transfer Done interrupt signal while TDIF (CRC_DMAINTSTS[1]) bit is set to 1. | ||
| 0 = Interrupt Disabled when CRC DMA transfer done. | ||
| 1 = Interrupt Enabled when CRC DMA transfer done. |
| DMA_CRC_T::DMAISTS |
[0x0024] CRC DMA Interrupt Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TABTIF | CRC DMA Read/Write Target Abort Interrupt Flag |
| This bit indicates that CRC bus has error or not during CRC DMA transfer. | ||
| 0 = No bus error response received during CRC DMA transfer. | ||
| 1 = Bus error response received during CRC DMA transfer. | ||
| Note1: This bit is cleared by writing 1 to it. | ||
| Note2: This bit indicates bus master received error response or not | ||
| If bus master received error response, it means that CRC transfer target abort is happened | ||
| DMA will stop transfer and respond this event to user then CRC state machine goes to IDLE state | ||
| When target abort occurred, user must reset DMA before transfer those data again. | ||
| [1] | TDIF | CRC DMA Transfer Done Interrupt Flag |
| This bit indicates that CRC DMA transfer has finished or not. | ||
| 0 = Not finished if TRIGEN (CRC_CTL[23]) has enabled. | ||
| 1 = CRC transfer done if TRIGEN (CRC_CTL[23]) has enabled. | ||
| Note1: This bit is cleared by writing 1 to it. | ||
| Note2: When CRC DMA transfer is done, TRIGEN (CRC_CTL[23]) will be cleared automatically. |
| DMA_CRC_T::DMASA |
| GPIO_T::DOUT |
[0x0008] Pn Data Output Value
| Bits | Field | Descriptions |
|---|---|---|
| [0] | DOUT0 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [1] | DOUT1 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [2] | DOUT2 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [3] | DOUT3 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [4] | DOUT4 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [5] | DOUT5 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [6] | DOUT6 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [7] | DOUT7 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [8] | DOUT8 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [9] | DOUT9 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [10] | DOUT10 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [11] | DOUT11 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [12] | DOUT12 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [13] | DOUT13 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [14] | DOUT14 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [15] | DOUT15 | Port A-f Pin[N] Output Value |
| Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output. | ||
| 0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output. | ||
| 1 = Px.n will drive High if the Px.n pin is configured as Push-pull output. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. |
| PWM_T::DTCTL0_1 |
[0x0070] PWM0 Dead-Time Control Register 0_1
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | DTCNT | Dead-time Counter (Write Protect) |
| The dead-time can be calculated from the following formula: | ||
| Dead-time = (DTCNT[11:0]+1) * PWM0_CLK period. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [16] | DTEN | Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0, PWM0_CH1) (PWM0_CH2, PWM0_CH3) (PWM0_CH4, PWM0_CH5) (Write Protect) |
| Dead-time insertion is only active when this PWM0 pair complementary mode is enabled | ||
| If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-time insertion Disabled on the pin pair. | ||
| 1 = Dead-time insertion Enabled on the pin pair. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [24] | DTCKSEL | Dead-time Clock Select (Write Protect) |
| 0 = Dead-time clock source from PWM0_CLKn. | ||
| 1 = Dead-time clock source from prescaler output. | ||
| Note: This register is write protected. Refer to REGWRPROT register. |
| PWM_T::DTCTL2_3 |
[0x0074] PWM0 Dead-Time Control Register 2_3
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | DTCNT | Dead-time Counter (Write Protect) |
| The dead-time can be calculated from the following formula: | ||
| Dead-time = (DTCNT[11:0]+1) * PWM0_CLK period. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [16] | DTEN | Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0, PWM0_CH1) (PWM0_CH2, PWM0_CH3) (PWM0_CH4, PWM0_CH5) (Write Protect) |
| Dead-time insertion is only active when this PWM0 pair complementary mode is enabled | ||
| If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-time insertion Disabled on the pin pair. | ||
| 1 = Dead-time insertion Enabled on the pin pair. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [24] | DTCKSEL | Dead-time Clock Select (Write Protect) |
| 0 = Dead-time clock source from PWM0_CLKn. | ||
| 1 = Dead-time clock source from prescaler output. | ||
| Note: This register is write protected. Refer to REGWRPROT register. |
| PWM_T::DTCTL4_5 |
[0x0078] PWM0 Dead-Time Control Register 4_5
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | DTCNT | Dead-time Counter (Write Protect) |
| The dead-time can be calculated from the following formula: | ||
| Dead-time = (DTCNT[11:0]+1) * PWM0_CLK period. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [16] | DTEN | Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0, PWM0_CH1) (PWM0_CH2, PWM0_CH3) (PWM0_CH4, PWM0_CH5) (Write Protect) |
| Dead-time insertion is only active when this PWM0 pair complementary mode is enabled | ||
| If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. | ||
| 0 = Dead-time insertion Disabled on the pin pair. | ||
| 1 = Dead-time insertion Enabled on the pin pair. | ||
| Note: This register is write protected. Refer to SYS_REGLCTL register. | ||
| [24] | DTCKSEL | Dead-time Clock Select (Write Protect) |
| 0 = Dead-time clock source from PWM0_CLKn. | ||
| 1 = Dead-time clock source from prescaler output. | ||
| Note: This register is write protected. Refer to REGWRPROT register. |
| TIMER_T::ECTL |
[0x0020] Timer Extended Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [31:24] | EVNTDPCNT | Event Drop Count |
| This field indicates timer how many events dropped after inter-timer trigger function enable. | ||
| For example, if user configured EVNTDPCNT to 7, timer would drop 7 first incoming events and starts the inter-timer trigger operation when it get 8th event. | ||
| Note: ECNTDPCNT only takes effect when INTRTGEN (TIMERx_CTL[24]) INTRTGMD (TIMERx_CTL[25]) are both set to 1. |
| SC_T::EGT |
| SC_T::ETUCTL |
[0x0014] SC Element Time Unit Control Register.
| Bits | Field | Descriptions |
|---|---|---|
| [11:0] | ETURDIV | ETU Rate Divider |
| The field indicates the clock rate divider. | ||
| The real ETU is ETURDIV + 1. | ||
| Note: Software can configure this field, but this field must be greater than 0x004. |
| ADC_T::EXTSMPT0 |
[0x0070] A/D Sampling Time Counter Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | EXTSMPT_CH0 | Additional ADC Sample Clock for Channel 0 |
| If the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal | ||
| The default sampling time is 1 ADC clocks | ||
| The additional clock number will be inserted to lengthen the sampling clock. | ||
| 0 = Number of additional clock cycles is 0. | ||
| 1 = Number of additional clock cycles is 1. | ||
| 2 = Number of additional clock cycles is 2. | ||
| 3 = Number of additional clock cycles is 4. | ||
| 4 = Number of additional clock cycles is 8. | ||
| 5 = Number of additional clock cycles is 16. | ||
| 6 = Number of additional clock cycles is 32. | ||
| 7 = Number of additional clock cycles is 64. | ||
| 8 = Number of additional clock cycles is 128. | ||
| 9 = Number of additional clock cycles is 256. | ||
| 10 = Number of additional clock cycles is 512. | ||
| 11 = Number of additional clock cycles is 1024. | ||
| 12 = Number of additional clock cycles is 1024. | ||
| 13 = Number of additional clock cycles is 1024. | ||
| 14 = Number of additional clock cycles is 1024. | ||
| 15 = Number of additional clock cycles is 1024. | ||
| [7:4] | EXTSMPT_CH1 | Additional ADC Sample Clock for Channel 1 |
| The same as channel 0 description. | ||
| [11:8] | EXTSMPT_CH2 | Additional ADC Sample Clock for Channel 2 |
| The same as channel 0 description. | ||
| [15:12] | EXTSMPT_CH3 | Additional ADC Sample Clock for Channel 3 |
| The same as channel 0 description. | ||
| [19:16] | EXTSMPT_CH4 | Additional ADC Sample Clock for Channel 4 |
| The same as channel 0 description. | ||
| [23:20] | EXTSMPT_CH5 | Additional ADC Sample Clock for Channel 5 |
| The same as channel 0 description. | ||
| [27:24] | EXTSMPT_CH6 | Additional ADC Sample Clock for Channel 6 |
| The same as channel 0 description. | ||
| [31:28] | EXTSMPT_CH7 | Additional ADC Sample Clock for Channel 7 |
| The same as channel 0 description. |
| ADC_T::EXTSMPT1 |
| PWM_T::FAILBRK |
[0x00c4] PWM0 System Fail Brake Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [1] | BODBRKEN | Brown-out Detection Trigger PWM0 Brake Function 0 Enable Bit |
| 0 = Brake Function triggered by BOD Disabled. | ||
| 1 = Brake Function triggered by BOD Enabled. | ||
| [3] | CORBRKEN | Core Lockup Detection Trigger PWM0 Brake Function 0 Enable Bit |
| 0 = Brake Function triggered by Core lockup detection Disabled. | ||
| 1 = Brake Function triggered by Core lockup detection Enabled. |
| PWM_T::FCAPDAT0 |
| PWM_T::FCAPDAT1 |
| PWM_T::FCAPDAT2 |
| PWM_T::FCAPDAT3 |
| PWM_T::FCAPDAT4 |
| PWM_T::FCAPDAT5 |
| SPI_T::FIFOCTL |
[0x003c] SPI FIFO Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXFBCLR | Receive FIFO Buffer Clear |
| 0 = No clear the received FIFO. | ||
| 1 = Clear the received FIFO. | ||
| Note: This bit is used to clear the receiver counter in FIFO Mode | ||
| This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter | ||
| After the clear operation, the flag of RXEMPTY in SPI_STATUS[0] will be set to 1. | ||
| [1] | TXFBCLR | Transmit FIFO Buffer Clear |
| 0 = Not clear the transmitted FIFO. | ||
| 1 = Clear the transmitted FIFO. | ||
| Note: This bit is used to clear the transmit counter in FIFO Mode | ||
| This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter | ||
| After the clear operation, the flag of TXEMPTY in SPI_STATUS[2] will be set to 1. | ||
| [2] | RXTHIEN | Receive Threshold Interrupt Enable Bit |
| 0 = RX threshold interrupt Disabled. | ||
| 1 = RX threshold interrupt Enabled. | ||
| [3] | TXTHIEN | Transmit Threshold Interrupt Enable Bit |
| 0 = TX threshold interrupt Disabled. | ||
| 1 = TX threshold interrupt Enabled. | ||
| [4] | RXOVIEN | Receive FIFO over Run Interrupt Enable Bit |
| 0 = RX FIFO over run interrupt Disabled. | ||
| 1 = RX FIFO over run interrupt Enabled. | ||
| [7] | RXTOIEN | RX Read Time Out Interrupt Enable Bit |
| 0 = RX read Timeout Interrupt Disabled. | ||
| 1 = RX read Timeout Interrupt Enabled. | ||
| [26:24] | RXTH | Received FIFO Threshold |
| If RX valid data counts are greater than RXTH, RXTHIF (SPI_STATUS[8]) will be set to 1. | ||
| [30:28] | TXTH | Transmit FIFO Threshold |
| If TX valid data counts are smaller than or equal to TXTH, TXTHIF (SPI_STATUS[10]) will be set to 1. |
| UART_T::FIFOSTS |
[0x0018] UART FIFO Status Register.
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXOVIF | RX Overflow Error Status Flag (Read Only) |
| This bit is set when RX FIFO overflow | ||
| If the number of bytes of received data is greater than RX_FIFO (UART_RBR) size, this bit will be set. | ||
| 0 = RX FIFO is not overflow. | ||
| 1 = RX FIFO is overflow. | ||
| Note: This bit is read only, but can be cleared by writing 1 to it. | ||
| [1] | RXEMPTY | Receiver FIFO Empty (Read Only) |
| This bit initiate RX FIFO empty or not. | ||
| 0 = RX FIFO is not empty. | ||
| 1 = RX FIFO is empty. | ||
| Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high | ||
| It will be cleared when UART receives any new data. | ||
| [2] | RXFULL | Receiver FIFO Full (Read Only) |
| This bit initiates RX FIFO full or not. | ||
| 0 = RX FIFO is not full. | ||
| 1 = RX FIFO is full. | ||
| Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. | ||
| [4] | PEF | Parity Error State Status Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid parity bit. | ||
| 0 = No parity error is generated. | ||
| 1 = Parity error is generated. | ||
| Note: This bit is read only, but can be cleared by writing '1' to it. | ||
| [5] | FEF | Framing Error Flag (Read Only) |
| This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). | ||
| 0 = No framing error is generated. | ||
| 1 = Framing error is generated. | ||
| Note: This bit is read only, but can be cleared by writing '1' to it. | ||
| [6] | BIF | Break Interrupt Flag( Read Only) |
| This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). | ||
| 0 = No Break interrupt is generated. | ||
| 1 = Break interrupt is generated. | ||
| Note: This bit is read only, but can be cleared by writing '1' to it. | ||
| [8] | TXOVIF | TX Overflow Error Interrupt Status Flag (Read Only) |
| If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. | ||
| 0 = TX FIFO did not overflow. | ||
| 1 = TX FIFO overflowed. | ||
| Note: This bit is read only, but can be cleared by writing 1 to it. | ||
| [9] | TXEMPTY | Transmitter FIFO Empty (Read Only) |
| This bit indicates TX FIFO empty or not. | ||
| 0 = TX FIFO is not empty. | ||
| 1 = TX FIFO is empty. | ||
| Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high | ||
| It will be cleared when writing data into DAT (TX FIFO not empty). | ||
| [10] | TXFULL | Transmitter FIFO Full (Read Only) |
| This bit indicates TX FIFO full or not. | ||
| 0 = TX FIFO is not full. | ||
| 1 = TX FIFO is full. | ||
| Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. | ||
| [11] | TXENDF | Transmitter Empty Flag (Read Only) |
| This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. | ||
| 0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. | ||
| 1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. | ||
| Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. | ||
| [20:16] | RXPTR | RX FIFO Pointer (Read Only) |
| This field indicates the RX FIFO Buffer Pointer | ||
| When UART receives one byte from external device, RXPTR increases one | ||
| When one byte of RX FIFO is read by CPU, RXPTR decreases one. | ||
| The Maximum value shown in RXPTR is 15 | ||
| When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0 | ||
| As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15 | ||
| [28:24] | TXPTR | TX-fIFO Pointer (Read Only) |
| This field indicates the TX FIFO Buffer Pointer | ||
| When CPU writes one byte into UART_DAT, TXPTR increases one | ||
| When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. | ||
| The Maximum value shown in TXPTR is 15 | ||
| When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0 | ||
| As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15 |
| RTC_T::FREQADJ |
| FMC_T::FTCTL |
[0x0018] Flash Access Time Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [6:4] | FOM | Frequency Optimization Mode (Write Protect) |
| The Nano103 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency. | ||
| 001 = Frequency <= 20MHz. | ||
| 100 = Frequency <= 36MHz. (default power-on setting) | ||
| Others = Reserved | ||
| Note:This bit is write protected. Refer to the SYS_REGLCTL register. | ||
| [7] | CACHEOFF | Flash Cache Disable Control (Write Protect) |
| 0 = Flash Cache function Enabled (default). | ||
| 1 = Flash Cache function Disabled. | ||
| Note:This bit is write protected. Refer to the SYS_REGLCTL register. |
| UART_T::FUNCSEL |
| DMA_GCR_T::GCTL |
[0x0000] PDMA Global Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [9] | CKEN1 | PDMA Controller Channel 1 Clock Enable Bit |
| 0 = PDMA channel 1 clock Disabled. | ||
| 1 = PDMA channel 1 clock Enabled. | ||
| [10] | CKEN2 | PDMA Controller Channel 2 Clock Enable Bit |
| 0 = PDMA channel 2 clock Disabled. | ||
| 1 = PDMA channel 2 clock Enabled. | ||
| [11] | CKEN3 | PDMA Controller Channel 3 Clock Enable Bit |
| 0 = PDMA channel 3 clock Disabled. | ||
| 1 = PDMA channel 3 clock Enabled. | ||
| [12] | CKEN4 | PDMA Controller Channel 4 Clock Enable Bit |
| 0 = PDMA channel 4 clock Disabled. | ||
| 1 = PDMA channel 4 clock Enabled. | ||
| [24] | CKENCRC | CRC Controller Clock Enable Bit |
| 0 = CRC channel clock Disabled. | ||
| 1 = CRC channel clock Enabled. |
| DMA_GCR_T::GINTSTS |
[0x000c] PDMA Global Interrupt Status Register
| Bits | Field | Descriptions |
|---|---|---|
| [1] | IF1 | PDMA Channel 1 Interrupt Status (Read Only) |
| This bit indicates the interrupt status of PDMA channel 1. | ||
| [2] | IF2 | PDMA Channel 2 Interrupt Status Flag of (Read Only) |
| This bit indicates the interrupt status of PDMA channel 2. | ||
| [3] | IF3 | PDMA Channel 3 Interrupt Status (Read Only) |
| This bit indicates the interrupt status of PDMA channel 3. | ||
| [4] | IF4 | PDMA Channel 4 Interrupt Status Flag (Read Only) |
| This bit indicates the interrupt status of PDMA channel 4. | ||
| [16] | IFCRC | CRC Controller Interrupt Status Flag (Read Only) |
| This bit indicates the interrupt status of CRC controller |
| SYS_T::GPA_MFPH |
[0x0034] GPIOA High Byte Multiple Function Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PA8MFP | PA.8 Multi-function Pin Selection |
| 0000 = GPIOA[8] | ||
| 0001 = I2C0 data input/output pin. | ||
| 0010 = Timer0 external counter input. | ||
| 0011 = SmartCard0 clock pin. | ||
| 0100 = SPI2 slave select pin. | ||
| 0101 = Timer0 toggle output. | ||
| 0110 = UART0 Clear to Send input pin. | ||
| [7:4] | PA9MFP | PA.9 Multi-function Pin Selection |
| 0000 = GPIOA[9] | ||
| 0001 = I2C0 clock pin. | ||
| 0010 = Timer1 external counter input. | ||
| 0011 = SmartCard0 data pin. | ||
| 0100 = SPI0 serial clock pin. | ||
| 0101 = Timer1 toggle output. | ||
| 0110 = UART1 Request to Send output pin. | ||
| 0111 = Snooper pin. | ||
| [11:8] | PA10MFP | PA.10 Multi-function Pin Selection |
| 0000 = GPIOA[10] | ||
| 0001 = I2C1 data input/output pin. | ||
| 0010 = Timer2 external counter input. | ||
| 0011 = SmartCard0 power pin. | ||
| 0100 = SPI2 1st MISO (Master In, Slave Out) pin. | ||
| 0101 = Timer2 toggle output. | ||
| [15:12] | PA11MFP | PA.11 Multi-function Pin Selection |
| 0000 = GPIOA[11] | ||
| 0001 = I2C1 clock pin. | ||
| 0010 = Timer3 external counter input. | ||
| 0011 = SmartCard0 reset pin. | ||
| 0100 = SPI2 1st MOSI (Master Out, Slave In) pin. | ||
| 0101 = Timer3 toggle output. | ||
| [19:16] | PA12MFP | PA.12 Multi-function Pin Selection |
| 0000 = GPIOA[12] | ||
| 0001 = PWM0 channel0 output/capture input. | ||
| 0011 = Timer0 capture input. | ||
| 0101 = I2C0 data input/output pin. | ||
| [23:20] | PA13MFP | PA.13 Multi-function Pin Selection |
| 0000 = GPIOA[13] | ||
| 0001 = PWM0 channel1 output/capture input. | ||
| 0011 = Timer1 capture input. | ||
| 0101 = I2C0 clock pin. | ||
| [27:24] | PA14MFP | PA.14 Multi-function Pin Selection |
| 0000 = GPIOA[14] | ||
| 0001 = PWM0 channel2 output/capture input. | ||
| 0010 = I2C1 data input/output pin. | ||
| 0011 = I2C1 data input/output pin. | ||
| 0101 = Timer2 external counter input. | ||
| 0110 = Data receiver input pin for UART0. | ||
| 0111 = Timer2 toggle output. | ||
| [31:28] | PA15MFP | PA.15 Multi-function Pin Selection |
| 0000 = GPIOA[15] | ||
| 0001 = PWM0 channel3 output/capture input. | ||
| 0010 = I2C1 clock pin. | ||
| 0011 = Timer1 capture input. | ||
| 0100 = SmartCard0 power pin. | ||
| 0110 = Data transmitter output pin for UART0. | ||
| 0111 = Timer3 toggle output. |
| SYS_T::GPA_MFPL |
[0x0030] GPIOA Low Byte Multiple Function Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PA0MFP | PA.0 Multi-function Pin Selection |
| 0000 = GPIOA[0] | ||
| 0001 = ADC analog input0. | ||
| 0010 = Comparator1 P-end input. | ||
| 0011 = Timer0 capture input. | ||
| 0101 = PWM0 channel2 output/capture input. | ||
| [7:4] | PA1MFP | PA.1 Multi-function Pin Selection |
| 0000 = GPIOA[1] | ||
| 0001 = ADC analog input1. | ||
| 0010 = Comparator1 N-end input. | ||
| 0110 = SPI0 2nd MISO (Master In, Slave Out) pin. | ||
| [11:8] | PA2MFP | PA.2 Multi-function Pin Selection |
| 0000 = GPIOA[2] | ||
| 0001 = ADC analog input2. | ||
| 0101 = Data receiver input pin for UART1. | ||
| [15:12] | PA3MFP | PA.3 Multi-function Pin Selection |
| 0000 = GPIOA[3] | ||
| 0001 = ADC analog input3. | ||
| 0101 = Data transmitter output pin for UART1. | ||
| 0110 = SPI3 1st MOSI (Master Out, Slave In) pin. | ||
| [19:16] | PA4MFP | PA.4 Multi-function Pin Selection |
| 0000 = GPIOA[4] | ||
| 0001 = ADC analog input4. | ||
| 0101 = I2C0 data input/output pin. | ||
| 0110 = SPI3 1st MISO (Master In, Slave Out) pin. | ||
| [23:20] | PA5MFP | PA.5 Multi-function Pin Selection |
| 0000 = GPIOA[5] | ||
| 0001 = ADC analog input5. | ||
| 0101 = I2C0 clock pin. | ||
| 0110 = SPI3 serial clock pin. | ||
| [27:24] | PA6MFP | PA.6 Multi-function Pin Selection |
| 0000 = GPIOA[6] | ||
| 0001 = ADC analog input6. | ||
| 0010 = Comparator1 output. | ||
| 0011 = Timer3 capture input. | ||
| 0100 = Timer3 external counter input. | ||
| 0101 = PWM0 channel3 output/capture input. | ||
| 0111 = Timer3 toggle output. |
| SYS_T::GPB_MFPH |
[0x003c] GPIOB High Byte Multiple Function Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PB8MFP | PB.8 Multi-function Pin Selection |
| 0000 = GPIOB[8] | ||
| 0001 = ADC external trigger input. | ||
| 0010 = Timer0 external counter input. | ||
| 0011 = External interrupt0 input pin. | ||
| 0100 = Timer0 toggle output. | ||
| 0111 = Snooper pin. | ||
| [7:4] | PB9MFP | PB.9 Multi-function Pin Selection |
| 0000 = GPIOB[9] | ||
| 0001 = SPI1 slave select pin. | ||
| 0010 = Timer2 external counter input. | ||
| 0100 = Timer2 toggle output. | ||
| 0101 = External interrupt0 input pin. | ||
| [11:8] | PB10MFP | PB.10 Multi-function Pin Selection |
| 0000 = GPIOB[10] | ||
| 0001 = SPI0 1st MOSI (Master Out, Slave In) pin. | ||
| 0100 = Timer2 toggle output. | ||
| 0101 = SPI0 slave select pin. | ||
| [15:12] | PB11MFP | PB.11 Multi-function Pin Selection |
| 0000 = GPIOB[11] | ||
| 0001 = PWM0 channel4 output/capture input. | ||
| 0010= Timer3 external counter input. | ||
| 0100 = Timer3 toggle output. | ||
| 0101 = SPI0 1st MISO (Master In, Slave Out) pin. | ||
| [23:20] | PB13MFP | PB.13 Multi-function Pin Selection |
| 0000 = GPIOB[13] | ||
| 0011 = SPI2 2nd MISO (Master In, Slave Out) pin. | ||
| 0111 = Snooper pin. | ||
| [27:24] | PB14MFP | PB.14 Multi-function Pin Selection |
| 0000 = GPIOB[14] | ||
| 0001 = External interrupt0 input pin. | ||
| 0011 = SPI2 2nd MOSI (Master Out, Slave In) pin. | ||
| 0100 = SPI2 slave select pin. | ||
| [31:28] | PB15MFP | PB.15 Multi-function Pin Selection |
| 0000 = GPIOB[15] | ||
| 0001 = External interrupt1 input pin. | ||
| 0011 = Snooper pin. | ||
| 0100 = SmartCard1 card detect pin. |
| SYS_T::GPB_MFPL |
[0x0038] GPIOB Low Byte Multiple Function Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PB0MFP | PB.0 Multi-function Pin Selection |
| 0000 = GPIOB[0] | ||
| 0001 = Data receiver input pin for UART0. | ||
| 0011 = SPI1 1st MOSI (Master Out, Slave In) pin. | ||
| [7:4] | PB1MFP | PB.1 Multi-function Pin Selection |
| 0000 = GPIOB[1] | ||
| 0001 = Data transmitter output pin for UART0. | ||
| 0011 = SPI1 1st MISO (Master In, Slave Out) pin. | ||
| [11:8] | PB2MFP | PB.2 Multi-function Pin Selection |
| 0000 = GPIOB[2] | ||
| 0001 = UART0 Request to Send output pin. | ||
| 0011 = SPI1 serial clock pin. | ||
| 0100 = Frequency Divider output pin. | ||
| [15:12] | PB3MFP | PB.3 Multi-function Pin Selection |
| 0000 = GPIOB[3] | ||
| 0001 = UART0 Clear to Send input pin. | ||
| 0011 = SPI1 slave select pin. | ||
| 0100 = SmartCard1 card detect pin. | ||
| [19:16] | PB4MFP | PB.4 Multi-function Pin Selection |
| 0000 = GPIOB[4] | ||
| 0001 = Data receiver input pin for UART1. | ||
| 0011 = SmartCard0 card detect pin. | ||
| 0100 = SPI2 slave select pin. | ||
| 0110 = RTC 1Hz output. | ||
| [23:20] | PB5MFP | PB.5 Multi-function Pin Selection |
| 0000 = GPIOB[5] | ||
| 0001 = Data transmitter output pin for UART1. | ||
| 0011 = SmartCard0 reset pin. | ||
| 0100 = SPI2 serial clock pin. | ||
| [27:24] | PB6MFP | PB.6 Multi-function Pin Selection |
| 0000 = GPIOB[6] | ||
| 0001 = UART1 Request to Send output pin. | ||
| 0100 = SPI2 1st MISO (Master In, Slave Out) pin. | ||
| [31:28] | PB7MFP | PB.7 Multi-function Pin Selection |
| 0000 = GPIOB[7] | ||
| 0001 = UART1 Clear to Send input pin. |
| SYS_T::GPC_MFPH |
[0x0044] GPIOC High Byte Multiple Function Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PC8MFP | PC.8 Multi-function Pin Selection |
| 0000 = GPIOC[8] | ||
| 0001 = SPI1 slave select pin. | ||
| 0101 = I2C1 data input/output pin. | ||
| [7:4] | PC9MFP | PC.9 Multi-function Pin Selection |
| 0000 = GPIOC[9] | ||
| 0001 = SPI1 serial clock pin. | ||
| 0101 = I2C1 clock pin. | ||
| [11:8] | PC10MFP | PC.10 Multi-function Pin Selection |
| 0000 = GPIOC[10] | ||
| 0001 = SPI0 1st MISO (Master In, Slave Out) pin. | ||
| 0101 = Data receiver input pin for UART1. | ||
| [15:12] | PC11MFP | PC.11 Multi-function Pin Selection |
| 0000 = GPIOC[11] | ||
| 0001 = SPI1 1st MOSI (Master Out, Slave In) pin. | ||
| 0101 = Data transmitter output pin for UART1. | ||
| [27:24] | PC14MFP | PC.14 Multi-function Pin Selection |
| 0000 = GPIOC[14] | ||
| 0001 = UART0 Clear to Send input pin. | ||
| [31:28] | PC15MFP | PC.15 Multi-function Pin Selection |
| 0000 = GPIOC[15] | ||
| 0001 = UART1 Request to Send output pin. | ||
| 0011 = Timer0 capture input. |
| SYS_T::GPC_MFPL |
[0x0040] GPIOC Low Byte Multiple Function Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PC0MFP | PC.0 Multi-function Pin Selection |
| 0000 = GPIOC[0] | ||
| 0001 = SPI0 slave select pin. | ||
| 0100 = SmartCard1 clock pin. | ||
| 0101 = PWM0 break1 input 1. | ||
| [7:4] | PC1MFP | PC.1 Multi-function Pin Selection |
| 0000 = GPIOC[1] | ||
| 0001 = SPI0 serial clock pin. | ||
| 0100 = SmartCard1 data pin. | ||
| 0101 = PWM0 break1 input 0. | ||
| [11:8] | PC2MFP | PC.2 Multi-function Pin Selection |
| 0000 = GPIOC[2] | ||
| 0001 = SPI0 1st MISO (Master In, Slave Out) pin. | ||
| 0100 = SmartCard1 power pin. | ||
| 0101 = PWM0 break0 input 1. | ||
| [15:12] | PC3MFP | PC.3 Multi-function Pin Selection |
| 0000 = GPIOC[3] | ||
| 0001 = SPI0 1st MOSI (Master Out, Slave In) pin. | ||
| 0100 = SmartCard1 reset pin. | ||
| 0101 = PWM0 break0 input 0. | ||
| [27:24] | PC6MFP | PC.6 Pin Function Selection |
| 0000 = GPIOC[6] | ||
| 0001 = Data receiver input pin for UART1. | ||
| 0011 = Timer0 capture input. | ||
| 0100 = SmartCard1 card detect pin. | ||
| 0101 = PWM0 channel0 output/capture input. | ||
| [31:28] | PC7MFP | PC.7 Multi-function Pin Selection |
| 0000 = GPIOC[7] | ||
| 0001 = Data transmitter output pin for UART1. | ||
| 0010 = ADC analog input7. | ||
| 0011 = Timer1 capture input. | ||
| 0101 = PWM0 channel1 output/capture input. |
| SYS_T::GPD_MFPH |
[0x004c] GPIOD High Byte Multiple Function Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [27:24] | PD14MFP | PD.14 Multi-function Pin Selection |
| 0000 = GPIOD[14] | ||
| 0001 = SPI0 2nd MOSI (Master Out, Slave In) pin. | ||
| [30:28] | PD15MFP | PD.15 Multi-function Pin Selection |
| 0000 = GPIOD[15] | ||
| 0001 = SPI0 2nd MISO (Master In, Slave Out) pin. | ||
| 0100 = SmartCard1 clock pin. |
| SYS_T::GPD_MFPL |
[0x0048] GPIOD Low Byte Multiple Function Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [27:24] | PD6MFP | PD.6 Multi-function Pin Selection |
| 0000 = GPIOD[6] | ||
| 0011 = SPI1 2nd MOSI (Master Out, Slave In) pin. | ||
| 0100 = SmartCard1 reset pin. | ||
| [31:28] | PD7MFP | PD.7 Multi-function Pin Selection |
| 0000 = GPIOD[7] | ||
| 0011 = SPI1 2nd MISO (Master In, Slave Out) pin. | ||
| 0100 = SmartCard1 power pin. |
| SYS_T::GPE_MFPL |
| SYS_T::GPF_MFPL |
[0x0058] GPIOF Low Byte Multiple Function Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PF0MFP | PF.0 Multi-function Pin Selection |
| 0000 = GPIOF[1] | ||
| 0101 = External interrupt0 input pin. | ||
| X111 = Serial wired debugger data pin | ||
| [7:4] | PF1MFP | PF.1 Multi-function Pin Selection |
| 0000 = GPIOF[1] | ||
| 0100 = Frequency Divider output pin. | ||
| 0101 = External interrupt1 input pin. | ||
| X111 = Serial wired debugger clock pin. | ||
| [11:8] | PF2MFP | PF.2 Multi-function Pin Selection |
| 0000 = GPIOF[2] | ||
| X111 = External 4~36 MHz (high speed) crystal output pin. | ||
| [15:12] | PF3MFP | PF.3 Multi-function Pin Selection |
| 0000 = GPIOF[3] | ||
| X111 = External 4~36 MHz (high speed) crystal input pin. | ||
| [27:24] | PF6MFP | PF.6 Multi-function Pin Selection |
| 0000 = GPIOF[6] | ||
| 0001 = I2C1 data input/output pin. | ||
| X111 = External 32.768 kHz crystal output pin(default). | ||
| [31:28] | PF7MFP | PF.7 Multi-function Pin Selection |
| 0000 = GPIOF[7] | ||
| 0001 = I2C1 clock pin. | ||
| 0011 = SmartCard0 card detect pin. | ||
| X111 = External 32.768 kHz crystal input pin(default). |
| RTC_T::INIT |
[0x0000] RTC Initiation Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | INIT_ACTIVE | RTC Active Status (Read Only) |
| 0 = RTC is at reset state. | ||
| 1 = RTC is at normal active state. | ||
| [31:1] | INIT | RTC Initiation |
| When RTC block is powered on, RTC is at reset state | ||
| User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state | ||
| Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. | ||
| The INIT is a write-only field and read value will be always 0. |
| GPIO_T::INTEN |
[0x001c] Pn Interrupt Enable Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FLIEN0 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [1] | FLIEN1 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [2] | FLIEN2 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [3] | FLIEN3 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [4] | FLIEN4 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [5] | FLIEN5 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [6] | FLIEN6 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [7] | FLIEN7 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [8] | FLIEN8 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [9] | FLIEN9 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [10] | FLIEN10 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [11] | FLIEN11 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [12] | FLIEN12 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [13] | FLIEN13 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [14] | FLIEN14 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [15] | FLIEN15 | Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit |
| The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the FLIEN (Px_INTEN[n]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. | ||
| If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. | ||
| 0 = Px.n level low or high to low interrupt Disabled. | ||
| 1 = Px.n level low or high to low interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [16] | RHIEN0 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [17] | RHIEN1 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [18] | RHIEN2 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [19] | RHIEN3 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [20] | RHIEN4 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [21] | RHIEN5 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||
| If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. | ||
| 0 = Px.n level high or low to high interrupt Disabled. | ||
| 1 = Px.n level high or low to high interrupt Enabled. | ||
| Note1: | ||
| Max. n=15 for port A/B/C/D/E. | ||
| Max. n=7 for port F. | ||
| Note2: | ||
| The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/ | ||
| PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/ | ||
| PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored. | ||
| [22] | RHIEN6 | Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit |
| The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin | ||
| Set bit to 1 also enable the pin wake-up function. | ||
| When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : | ||
| If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. | ||